DS2411P/T [DALLAS]
Silicon Serial Number with VCC Input; 硅与VCC输入序列号
| 型号： | DS2411P/T |
| 厂家： | 
DALLAS SEMICONDUCTOR |
| 描述： | Silicon Serial Number with VCC Input |
| 文件： | 总11页 (文件大小：231K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS2411
Silicon Serial Number with VCC Input
www.maxim-ic.com
FEATURES
PIN CONFIGURATION
C Unique, Factory-Lasered and Tested 64-Bit
Registration Number (8-Bit Family Code
Plus 48-Bit Serial Number Plus 8-Bit CRC
Tester); Guaranteed No Two Parts Alike
C Standby Current <1µA
3
1
2
C Built-In Multidrop Controller Enables
Multiple DS2411s to Reside on a Common
SOT23-3, Top View
ꢀ
1-Wire Network
1
2
3
6
5
4
C Multidrop Compatible with Other 1-Wire
Products
C 8-Bit Family Code Identifies Device as
DS2411 to the 1-Wire Master
C Low-Cost TSOC, SOT23-3, and Flip-Chip
Surface-Mount Packages
TSOC, Top View
C Directly Connects to a Single-Port Pin of a
Microprocessor and Communicates at up to
15.4kbps
1
2
C Overdrive Mode Boosts Communication
Speed to 125kbps
A
B
C Operating Range: 1.5V to 5.25V, -40°C to
+85°C
Flip Chip, Top view, bumps
not visible
ORDERING INFORMATION
PIN DESCRIPTION
PART
DS2411R/
T&R
DS2411P
DS2411P/
T&R
TEMP RANGE
-40LC to +85LC
-40LC to +85LC
-40LC to +85LC
PACKAGE
PIN
SOT23-3,
NAME
FLIP
CHIP
A1
SOT23 TSOC
Tape-and-Reel
TSOC
I/O
VCC
GND
N.C.
N.C.
N.C.
1
2
2
6
1
3
4
5
TSOC,
B2
Tape-and-Reel
Flip Chip,
3
B1
—
—
—
A2
DS2411X
-40LC to +85LC
Tape-and-Reel
—
—
DESCRIPTION
The DS2411 silicon serial number is a low-cost, electronic registration number with external power
supply. It provides an absolutely unique identity that can be determined with a minimal electronic
interface (typically, a single port pin of a microcontroller). The DS2411’s registration number is a
factory-lasered, 64-bit ROM that includes a unique 48-bit serial number, an 8-bit CRC, and an 8-bit
family code (01h). Data is transferred serially through the Dallas Semiconductor’s 1-Wire protocol. The
external power supply is required, extending the operating voltage range of the device below typical
1-Wire devices.
1-Wire is a registered trademark of Dallas Semiconductor.
1 of 11
052003
DS2411
ABSOLUTE MAXIMUM RATINGS*
I/O Voltage to GND
-0.5V to +6V
-0.5V to +6V
±20mA
VCC Voltage to GND
I/O, VCC Current
Operating Temperature Range
Junction Temperature
-40°C to +85°C
+150°C
Storage Temperature Range
Soldering Temperature
-55°C to +125°C
See IPC/JEDEC J-STD-
020A Specification
ꢀ This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
ELECTRICAL CHARACTERISTICS (VCC = 1.5V to 5.25V; TA = -40LC to +85LC.)
PARAMETER
SYMBOL
CONDITIONS
MIN MAX UNITS
Operating Temperature
TA
(Note 1)
(Note 1)
-40
1.5
1.5
+85
5.25
5.25
LC
Supply Voltage
1-Wire Pullup
VCC
V
VCC = VPUP (Note 1)
V
I/O PIN GENERAL DATA
1-Wire Pullup Resistance
RPUP
(Notes 1, 2)
0.3
2.2
kꢁ
µs
VCC stable to first
Power-Up Delay
tPWRP
1200
1-Wire command (Notes 1, 3)
(Note 3)
0V ≤ V(I/O) ≤ VCC
V(I/O) ≤ VIL, or V(I/O) ≥ VIH
Input Capacitance
Input Load Current
Standby Supply Current
Active Supply Current
High-to-Low Switching
Threshold
CIO
IL
ICCS
ICCA
100
+1
1
pF
µA
µA
µA
-1
100
VTL
VIL
VIH
(Notes 3, 4, 5)
(Note 1)
0.4
3.2
V
V
V
Input Low Voltage
0.30
VCC
0.3
-
Input High Voltage
(Note 1)
Low-to-High Switching
Threshold
Switching Hysteresis
Output Low Voltage at 4mA
VTH
(Notes 3, 4, 6)
0.75
0.18
3.4
V
VHY
VOL
(Notes 3, 7)
(Note 8)
V
V
0.4
5
2
Standard speed (Note 9, 3)
Overdrive speed (Note 9, 3)
Standard speed,
1.25
0.5
Rising Edge Holdoff
tREH
µs
µs
5
2
5
RPUP = 2.2kꢁ (Note 1)
Overdrive speed,
Recovery Time
tREC
RPUP = 2.2kꢁ (Note 1)
Overdrive speed, directly prior to
reset pulse; RPUP = 2.2kꢁ (Note 1)
Standard speed
65
8
10
Timeslot Duration
tSLOT
Overdrive VCC ≥ 2.2V
Overdrive VCC ≥ 1.5V
µs
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DS2411
PARAMETER
SYMBOL
CONDITIONS
MIN MAX UNITS
I/O PIN, 1-Wire RESET, PRESENCE DETECT CYCLE
Standard speed
480
60
15
2
640
80
60
6
Reset Low Time
tRSTL
µs
µs
Overdrive speed
Standard speed
Presence-Detect High Time
tPDH
Overdrive VCC ≥ 2.2V
Overdrive VCC ≥ 1.5V
Standard speed
2
8.5
240
24
30
8
60
8
8
Presence-Detect Low Time
Presence-Detect Fall Time
tPDL
tFPD
tMSP
Overdrive VCC ≥ 2.2V
Overdrive VCC ≥ 1.5V
Standard speed (Note 10, 3)
Overdrive speed (Note 10, 3)
Standard speed (Note 1)
Overdrive VCC ≥ 2.2V (Note 1)
Overdrive VCC ≥ 1.5V (Note 1)
µs
µs
µs
0.4
0.05
60
6
1
75
10
10
Presence-Detect Sample
Time
8.5
I/O PIN, 1-Wire WRITE
Standard speed (Notes 1, 13)
Overdrive VCC ≥ 2.2V (Notes 1,
13)
60
6
120
16
Write-0 Low Time
tW0L
µs
µs
Overdrive VCC ≥ 1.5V (Notes 1,
13)
8
16
Standard speed (Notes 1, 11, 13)
Overdrive speed (Notes 1, 11, 13)
5
1
15 - ꢂ
2 - ꢂ
Write-1 Low Time
I/O PIN, 1-Wire READ
Read Low Time
tW1L
Standard speed (Notes 1, 11)
Overdrive speed (Notes 1, 11)
Standard speed (Notes 1, 12)
Overdrive speed (Notes 1, 12)
5
15 - ꢂ
2 - ꢂ
15
tRL
µs
µs
1
tRL + ꢃ
t+ ꢃ
Read Sample Time
tMSR
2
Note 1:
Note 2:
System requirement.
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the
system and 1-Wire recovery times. The specified value here applies to systems with only
one device and with the minimum 1-Wire recovery times. For more heavily loaded
systems, an active pullup such as that found in the DS2480B may be required. Minimum
allowable pullup resistance is slightly greater than the value necessary to produce the
absolute maximum current (20mA) during 1-Wire low times at VPUP = 5.25V assuming
VOL = 0V.
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Not production tested.
VTL and VTH are functions of VCC and temperature.
Voltage below which during a falling edge on I/O, a logic ‘0’ is detected.
Voltage above which during a rising edge on I/O, a logic ‘1’ is detected.
After VTH is crossed during a rising edge on I/O, the voltage on I/O has to drop by VHY to
be detected as logic ‘0’.
Note 8:
Note 9:
The I-V characteristic is linear for voltages less than 1V.
The earliest recognition of a negative edge is possible at tREH after VTH has been reached
on the previous edge.
Note 10:
Interval during the negative edge on I/O at the beginning of a presence-detect pulse
between the time at which the voltage is 90% of VPUP and the time at which the voltage is
10% of VPUP
.
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DS2411
ꢂ represents the time required for the pullup circuitry to pull the voltage on I/O up VIL to
VTH.
Note 11:
Note 12:
Note 13:
ꢃ represents the time required for the pullup circuitry to pull the voltage on I/O up from
VIL to the input-high threshold of the bus master.
Interval begins when the voltage drops below VTL during a negative edge on I/O and ends
when the voltage rises above VTH during a positive edge on I/O.
OPERATION
The DS2411’s registration number is accessed through a single data line. The 48-bit serial number, 8-bit
family code, and 8-bit CRC are retrieved using the Dallas 1-Wire protocol. This protocol defines bus
transactions in terms of the bus state during specified time slots that are bus-master-generated falling
edges on the I/O pin. All data is read and written least significant bit first. The device requires a delay
between VCC power-up and initial 1-Wire communication, tPWRP (1200ꢄs). During this time the device
may issue presence-detect pulses.
1-Wire BUS SYSTEM
The 1-Wire bus has a single bus master and one or more slaves. In all instances, the DS2411 is a slave
device. The bus master is typically either a microcontroller or a Dallas Semiconductor bridge chip such as
the DS2480, DS2490, or DS1481. The discussion of this bus system is broken down into three topics:
hardware configuration, transaction sequence, and 1-Wire signaling (signal type and timing).
Hardware Configuration
The 1-Wire bus has a single data line, I/O. It is important that each device on the bus be able to drive I/O
at the appropriate time. To facilitate this, each device has an open-drain or three-state output. The
DS2411 has an open-drain output with an internal circuit equivalent to that shown in Figure 3. The bus
master can have the same equivalent circuit. If a bidirectional pin is not available on the master, separate
output and input pins can be connected together. The bus requires a pullup resistor at the master end of
the bus, as shown in Figure 4. A multidrop bus consists of a 1-Wire bus with multiple slaves attached.
The 1-Wire bus has a maximum data rate of 15.4kbps in standard speed and 125kbps in overdrive.
The idle state for the 1-Wire bus is high. If a transaction needs to be suspended for any reason, I/O must
remain high if the transaction is to be resumed. If the bus is pulled low, slave devices on the bus will
interpret the low as either a timeslot, or a reset depending on the duration.
Figure 1. DS2411 REGISTRATION NUMBER
MSB
LSB
8-BIT CRC CODE
MSB LSB MSB
48-BIT SERIAL NUMBER
8-BIT FAMILY CODE
LSB MSB
LSB
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DS2411
Figure 2. 1-WIRE CRC GENERATOR
POLYNOMIAL = X8 + X5 + X4 + 1
1st
2nd
3rd
4th
5th
6th
7th
8th
STAGE STAGE
X1
STAGE STAGE
X3
STAGE
STAGE STAGE STAGE
X0
X2
X4
X5
X6 X7
INPUT DATA
X8
Figure 3. DS2411 EQUIVALENT CIRCUIT
VCC
Rx
Tx
I/O
-1 A IL 1 A
? ꢀ
ꢀ
?
100 Ω
GROUND
Figure 4. BUS MASTER CIRCUIT
a) Open Drain
b) DS2480B Serial Bridge
5V OPERATION ONLY
VDD
VCC to DS2411
BUS MASTER
DS5000 OR 8051
5V
Vcc
VPP
POL
RPUP
OPEN-DRAIN
UART
I/O
SIN (RxD)
Rx
Tx
PORT PIN
I/O to DS2411
RxD
1-W
OR µC
DS2480
TxD
GND
*
SOUT (TxD)
1
Ground to DS2411
GND
L
M
RPUP must be between 0.3 k and 2.2 k . The optimal
ꢀ
ꢀ
value depends on the 1-Wire communication speed and
the bus load characteristics.
START
0
STOP
* ONLY ONE DS9502 ESD PROTECTION DIODE WITH 5V
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DS2411
TRANSACTION SEQUENCE
The communication sequence for accessing the DS2411 through the 1-Wire bus is as follows:
C Initialization
C ROM Function Command
C Read Data
INITIALIZATION
All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence
consists of a reset pulse transmitted by the bus master followed by a presence pulse(s) transmitted by the
slave(s). The presence pulse lets the bus master know that the DS2411 is on the bus and is ready to
operate. For more details, see the 1-Wire Signaling section.
ROM FUNCTION COMMANDS
Once the bus master has detected a presence, it can issue one of the three ROM function commands. All
ROM function command codes are 1 byte long. A list of these commands follows (see the flowchart in
Figure 5).
Read ROM [33h]
This command allows the bus master to read the DS2411’s 8-bit family code, unique 48-bit serial
number, and 8-bit CRC. This command should only be used if there is a single slave device on the bus. If
more than one slave is present on the bus, a data collision results when all slaves try to transmit at the
same time (open drain produces a wired-AND result), and the resulting registration number read by the
master will be invalid.
Search ROM [F0h]
When a system is initially brought up, the bus master might not know the number of devices on the
1-Wire bus or their registration numbers. By taking advantage of the wired-AND property of the bus, the
master can use a process of elimination to identify the registration numbers of all slave devices. For each
bit of the registration number, starting with the least significant bit, the bus master issues a triplet of time
slots. On the first slot, each slave device participating in the search outputs the true value of its
registration number bit. On the second slot, each slave device participating in the search outputs the
complemented value of its registration number bit. On the third slot, the master writes the true value of
the bit to be selected. All slave devices that do not match the bit written by the master stop participating
in the search. If both of the read bits are zero, the master knows that slave devices exist with both states of
the bit. By choosing which state to write, the bus master branches in the romcode tree. After one complete
pass, the bus master knows the registration number of a single device. Additional passes identify the
registration numbers of the remaining devices. Refer to App Note 187: 1-Wire Search Algorithm for a
detailed discussion, including an example.
Overdrive Skip ROM [3Ch]
This command causes all overdrive-capable slave devices on the 1-Wire network to enter overdrive speed
(OD = 1). All communication following this command has to occur at overdrive speed until a reset pulse
of minimum 480ꢄs duration resets all devices on the bus to regular speed (OD = 0).
To subsequently address a specific overdrive-supporting device, a reset pulse at overdrive speed has to be
issued followed by a read ROM or search ROM command sequence. Overdrive speeds up the time for the
search process.
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DS2411
Figure 5. ROM FUNCTIONS FLOW CHART
Bus Master Tx
Reset Pulse
OD
N
OD = 0
Reset Pulse ?
Bus Master Tx ROM
Function Command
DS2411 Tx
Presence Pulse
33h
F0h
3Ch
N
N
N
Read ROM
Command?
Search ROM
OD Skip
Command?
Command?
Y
OD = 1
DS2411 Tx Bit 0
DS2411 Tx Bit 0
Master Tx Bit 0
DS2411 Tx
Family Code
(1 Byte)
N
N
Bit 0
Match?
DS2411 Tx Bit 1
DS2411 Tx Bit 1
Master Tx Bit 1
DS2411 Tx
Serial Number
(6 Bytes)
Bit 1
Match?
DS2411 Tx Bit 63
DS2411 Tx Bit 63
Master Tx Bit 63
DS2411 Tx
CRC Byte
N
Bit 63
Match?
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DS2411
1-WIRE SIGNALING
The DS2411 requires strict protocols to ensure data integrity. The protocol consists of four types of
signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1, and Read
Data. Except for the presence pulse the bus master initiates all these signals. The DS2411 can
communicate at two different speeds: standard speed and Overdrive speed. If not explicitly set into the
Overdrive mode, the DS2411 will communicate at standard speed. While in Overdrive Mode the fast
timing applies to all waveforms.
To get from idle to active, the voltage on the 1-Wire line needs to fall from VPUP below the threshold VTL.
To get from active to idle, the voltage needs to rise from VILMAX past the threshold VTH. The voltage
VILMAX is relevant for the DS2411 when determining a logical level, but not for triggering any events.
The initialization sequence required to begin any communication with the DS2411 is shown in Figure 6.
A Reset Pulse followed by a Presence Pulse indicates the DS2411 is ready to receive data, given the
correct ROM and memory function command. In a mixed population network, the reset low time tRSTL
needs to be long enough for the slowest 1-Wire slave device to recognize it as a reset pulse. If the bus
master uses slew-rate control on the falling edge, it must pull down the line for tRSTL + tF to compensate
for the edge. A tRSTL duration of 480µs or longer will exit the Overdrive Mode returning the device to
standard speed. If the DS2411 is in Overdrive Mode and tRSTL is no longer than 80µs, the device will
remain in Overdrive Mode.
After the bus master has released the line it goes into receive mode (RX). Now, the 1-Wire bus is pulled
to VPUP via the pullup resistor or, in case of a DS2480B driver, by active circuitry. When the threshold
VTH is crossed, the DS2411 waits for tPDH and then transmits a Presence Pulse by pulling the line low for
tPDL. To detect a presence pulse, the master must test the logical state of the 1-Wire line at tMSP
.
The tRSTH window must be at least the sum of tPDHMAX, tPDLMAX, and tRECMIN. Immediately after tRSTH is
expired, the DS2411 is ready for data communication. In a mixed population network, tRSTH should be
extended to minimum 480µs at standard speed and 48µs at Overdrive speed to accommodate other 1-
Wire devices.
Read/Write Time Slots
Data communication with the DS2411 takes place in time slots that carry a single bit each. Write time
slots transport data from bus master to slave. Read time-slots transfer data from slave to master. The
definitions of the write and read time slots are illustrated in Figure 7.
All communication begins with the master pulling the data line low. As the voltage on the 1-Wire line
falls below the threshold VTL, the DS2411 starts its internal timing generator that determines when the
data line will be sampled during a write time slot and how long data will be valid during a read time slot.
Master to Slave
For a write-one time slot, the voltage on the data line must have crossed the VTHMAX threshold after the
write-one low time tW1LMAX is expired. For a write-zero time slot, the voltage on the data line must stay
below the VTHMIN threshold until the write-zero low time tW0LMIN is expired. For most reliable
communication the voltage on the data line should not exceed VILMAX during the entire tW0L window.
After the VTHMAX threshold has been crossed, the DS2411 needs a recovery time tREC before it is ready for
the next time slot.
8 of 11
DS2411
INITIALIZATION PROCEDURE
Figure 6. Reset and Presence Pulse
MASTER Tx RESET PULSE
MASTER Rx PRESENCE PULSE
tMSP
ꢀ
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
tF
tRSTL
tPDL
tRSTH
tPDH
tREC
RESISTOR
MASTER
DS2411
READ/WRITE TIMING DIAGRAM
Figure 7a. Write-One Time Slot
tW1L
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
tF
ꢀ
tSLOT
RESISTOR
MASTER
DS2411
Figure 7b. Write-Zero Time Slot
tW 0L
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
tREC
tF
tSLOT
RESISTOR
MASTER
DS2411
Figure 7c. Read-data Time Slot
tMSR
tRL
VPUP
VIHMASTER
VTH
MASTER
SAMPLING
WINDOW
VTL
VILMAX
0V
tF
tREC
tSLOT
ꢀ
RESISTOR
MASTER
DS2411
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DS2411
Slave to Master
A read-data time slot begins like a write-one time slot. The voltage on the data line must remain below
VTLMIN until the read low time tRL is expired. During the tRL window, when responding with a 0, the
DS2411 will start pulling the data line low; its internal timing generator determines when this pull-down
ends and the voltage starts rising again. When responding with a 1, the DS2411 will not hold the data line
low at all, and the voltage starts rising as soon as tRL is over.
The sum of tRL + ꢃ (rise rime) on one side and the internal timing generator of the DS2411 on the other
side define the master sampling window (tMSRMIN to tMSRMAX) in which the master must perform a read
from the data line. For most reliable communication, tRL should be as short as permissible and the master
should read close to but no later than tMSRMAX. After reading from the data line, the master must wait until
tSLOT is expired. This guarantees sufficient recovery time tREC for the DS2411 to get ready for the next
time slot.
Improved Network Behavior
In a 1-Wire environment, line termination is possible only during transients controlled by the bus master
(1-Wire driver). 1-Wire networks therefore are susceptible to noise of various origins. Depending on the
physical size and topology of the network, reflections from end points and branch points can add up or
cancel each other to some extent. Such reflections are visible as glitches or ringing on the 1-Wire
communication line. A glitch during the rising edge of a time slot can cause a slave device to lose
synchronization with the master and, as a consequence, result in a search ROM command coming to a
dead end. For better performance in network applications, the DS2411 uses a new 1-Wire front end,
which makes it less sensitive to noise and also reduces the magnitude of noise injected by the slave
device itself.
The 1-Wire front end of the DS2411 differs from traditional slave devices in four characteristics.
1) The falling edge of the presence pulse has a controlled slew rate. This provides a better match to the
line impedance than a digitally switched transistor, converting the high frequency ringing known from
traditional devices into a smoother low-bandwidth transition. The slew rate control is specified by the
parameter tFPD, which has different values for standard and Overdrive speed.
2) There is additional low-pass filtering in the circuit that detects the falling edge at the beginning of a
time slot. This reduces the sensitivity to high-frequency noise. As a consequence, the duration of the
setup time tSU at standard speed is larger than with traditional devices. This additional filtering does
not apply at Overdrive speed.
3) There is a hysteresis at the low-to-high switching threshold VTH. If a negative glitch crosses VTH but
doesn’t go below VTH - VHY, it will not be recognized (Figure 8, Case A). The hysteresis is effective
at any 1-Wire speed.
4) There is a time window specified by the rising edge hold-off time tREH during which glitches will be
ignored, even if they extend below VTH - VHY threshold (Figure 8, Case B, tGL < tREH). Deep voltage
droops or glitches that appear late after crossing the VTH threshold and extend beyond the tREH
window cannot be filtered out and will be taken as beginning of a new time slot (Figure 8, Case C, tGL
O tREH). The duration of the hold-off time is independent of the 1-Wire speed.
Only devices which have the parameters tFPD, VHY and tREH specified in their electrical characteristics use
the improved 1-Wire front end.
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DS2411
NOISE SUPPRESSION SCHEME Figure 8
tREH
tREH
VPUP
VTH
VHY
Case A
Case B
Case C
tGL
0V
tGL
CRC GENERATION
To validate the registration number transmitted from the DS2411, the bus master can generate a CRC
value from the 8-bit family code and unique 48-bit serial number as it is received. If the CRC matches the
last 8 bits of the registration number, the transmission is error free.
The equivalent polynomial function of this CRC is: CRC = x8 + x5 + x4 + 1.
CUSTOM DS2411
Customization of a portion of the unique 48-bit serial number by the customer is available. Dallas
Semiconductor will register and assign a specific customer ID in the 12 most significant bits of the 48-bit
field. The next most significant bits are selectable by the customer as a starting value, and the least
significant bits are non-selectable and will be automatically incremented by one. Certain quantities and
conditions apply for these custom parts. Contact your Maxim/Dallas Semiconductor sales representative
for more information.
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