DS4404NR [DALLAS]
Two/Four-Channel, I2C Adjustable Current DAC; 双/四通道，可通过I²C调节的电流输出DAC
| 型号： | DS4404NR |
| 厂家： | 
DALLAS SEMICONDUCTOR |
| 描述： | Two/Four-Channel, I2C Adjustable Current DAC |
| 文件： | 总8页 (文件大小：152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rev 0; 4/06
2
Two/Four-Channel, I C Adjustable Current DAC
General Description
Features
ꢀ Two (DS4402) or Four (DS4404) Current DACs
2
The DS4402 and DS4404 contain two and four I C*
adjustable current DACs, respectively, that are each
capable of sinking or sourcing current. Each output has
31 sink and 31 source settings that are programmed by
ꢀ Full-Scale Range for Each DAC Determined by
External Resistors
ꢀ 31 Settings Each for Sink and Source Modes
2
the I C interface. External resistors set the full-scale
2
ꢀ I C-Compatible Serial Interface
range and step size of each output.
ꢀ Two Three-Level Address Pins Allow Nine
Applications
2
Devices on Same I C Bus
Power-Supply Adjustment
Power-Supply Margining
ꢀ Low Cost
ꢀ Small Package (14-Pin TDFN)
ꢀ -40°C to +85°C Temperature Range
ꢀ 1.7V to 5.5V Operation
Adjustable Current Sink or Source
Pin Configuration
Ordering Information
TOP VIEW
OUT3
(N.C.)
14
13
12
11
SDA
SCL
GND
1
2
3
4
5
6
7
PART
TEMP RANGE
PIN-PACKAGE
V
CC
DS4402N+
-40°C to +85°C 14 TDFN (3mm x 3mm)
-40°C to +85°C 14 TDFN (3mm x 3mm)
-40°C to +85°C 14 TDFN (3mm x 3mm)
-40°C to +85°C 14 TDFN (3mm x 3mm)
OUT2
(N.C.)
DS4402N+T&R
DS4404N+
FS3
(N.C.)
FS2
(N.C.)
A1
DS4404/
DS4402
10 OUT1
DS4404N+T&R
FS1
9
8
A0
+Denotes lead-free package.
T&R denotes tape-and-reel package.
FS0
OUT0
TDFN
(3mm x 3mm x 0.8mm)
( ) INDICATES FOR DS4402 ONLY.
Typical Operating Circuit
V
V
OUT0
CC
V
OUT1
OUT
OUT
4.7kΩ
4.7kΩ
V
CC
SDA
SCL
A1
DC/DC
CONVERTER
DC/DC
CONVERTER
R
R
0A
0B
1A
1B
FB
FB
OUT0
OUT1
DS4402
A0
R
R
GND
FS0
FS1
R
R
FS1
FS0
2
*Purchase of I C components from Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a
2
2
2
license under the Philips I C Patent Rights to use these components in an I C system, provided that the system conforms to the I C
Standard Specification as defined by Philips.
______________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
2
Two/Four-Channel, I C Adjustable Current DAC
ABSOLUTE MAXIMUM RATINGS
Voltage Range on V , SDA, and SCL
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-55°C to +125°C
Soldering Temperature .....................................Refer to IPC/JEDEC
J-STD-020 Specification
CC
Relative to Ground.............................................-0.5V to +6.0V
Voltage Range on A0, A1, FS0, FS1, FS2, FS3,
OUT0, OUT1, OUT2, and OUT3 Relative to
Ground ................-0.5V to (V
+ 0.5V) (Not to exceed 6.0V.)
CC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(T = -40°C to +85°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage
V
(Note 1)
2.7
5.5
V
CC
0.7 x
V
+
CC
0.3
Input Logic 1 (SDA, SCL, A0, A1)
Input Logic 0 (SDA, SCL, A0, A1)
V
V
V
IH
V
CC
0.3 x
V
V
-0.3
IL
CC
DC ELECTRICAL CHARACTERISTICS
(V
= +2.7V to +5.5V, T = -40°C to +85°C.)
A
CC
PARAMETER
SYMBOL
CONDITIONS
DS4402
MIN
TYP
MAX
500
500
1
UNITS
V
= 5.5V
CC
Supply Current
I
µA
CC
(Note 2)
DS4404
Input Leakage (SDA, SCL)
Output Leakage (SDA)
I
V
= 5.5V
µA
µA
IL
CC
I
1
L
V
V
= 0.4V
= 0.6V
3
6
OL
OL
Output Current Low (SDA)
I
mA
OL
Address Input Resistors
Reference Voltage
R
240
kΩ
IN
V
1.23
V
REF
OUTPUT CURRENT CHARACTERISTICS
(V
= +2.7V to +5.5V, T = -40°C to +85°C.)
A
CC
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Voltage for Sinking Current
V
(Note 3)
(Note 3)
0.5
V
V
OUT:SINK
CC
Output Voltage for Sourcing
Current
V
-
CC
V
0
V
OUT:SOURCE
0.5
Full-Scale Sink Output Current
Full-Scale Source Output Current
I
(Note 3)
(Note 3)
0.5
2.0
mA
mA
OUT:SINK
I
-2.0
-0.5
OUT:SOURCE
Output-Current Full-Scale
Accuracy
I
+25°C, V = 4.0V; using ideal R resistor
2.5
70
5.0
%
OUT:FS
OUT:TC
CC
FS
Output-Current Temperature Drift
I
(Note 4)
ppm/°C
2
______________________________________________________________________
2
Two/Four-Channel, I C Adjustable Current DAC
OUTPUT CURRENT CHARACTERISTICS (continued)
(V
= +2.7V to +5.5V, T = -40°C to +85°C.)
A
CC
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output-Current Power-Supply
Rejection Ratio
DC
0.33
%/V
Output Leakage Current at Zero
Current Setting
I
-1
+1
µA
ZERO
Output-Current Differential
Linearity
DNL
INL
(Note 5)
(Note 6)
0.5
1
LSB
LSB
Output-Current Integral Linearity
2
I C AC ELECTRICAL CHARACTERISTICS
(V
= +2.7V to +5.5V, T = -40°C to +85°C.)
A
CC
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCL Clock Frequency
f
(Note 7)
0
400
kHz
SCL
Bus Free Time Between STOP
and START Conditions
t
1.3
0.6
µs
µs
BUF
Hold Time (Repeated) START
Condition
t
HD:STA
Low Period of SCL
High Period of SCL
Data Hold Time
t
1.3
0.6
0
µs
µs
µs
ns
µs
LOW
t
HIGH
t
0.9
DH:DAT
Data Setup Time
START Setup Time
t
100
0.6
SU:DAT
t
SU:STA
20 +
SDA and SCL Rise Time
SDA and SCL Fall Time
t
(Note 8)
(Note 8)
300
300
ns
ns
R
0.1C
B
20 +
t
F
0.1C
B
STOP Setup Time
t
0.6
µs
SU:STO
SDA and SCL Capacitive Loading
C
(Note 8)
400
pF
B
Note 1: All voltages with respect to ground. Currents entering the IC are specified positive, and currents exiting the IC are negative.
Note 2: Supply current specified with all outputs set to zero current setting with all inputs (except A1 and A0, which can be open) driven
to well-defined logic levels. SDA and SCL are connected to V . Excludes current through R resistors (I ). Total current
CC
FS
RFS
including I
is I + (2 x I
).
RFS
RFS
CC
Note 3: The output-voltage full-scale current ranges must be satisfied to ensure the device meets its accuracy and linearity specifications.
Note 4: Temperature drift excludes drift caused by external resistor.
Note 5: Differential linearity is defined as the difference between the expected incremental current increase with respect to position
and the actual increase. The expected incremental increase is the full-scale range divided by 31.
Note 6: Integral linearity is defined as the difference between the expected value as a function of the setting and the actual value.
The expected value is a straight line between the zero and the full-scale values proportional to the setting.
2
Note 7: Timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I C standard-mode timing.
Note 8: C —total capacitance of one bus line in pF.
B
_____________________________________________________________________
3
2
Two/Four-Channel, I C Adjustable Current DAC
Pin Description
PIN
NAME
FUNCTION
I C Serial Data. Input/output for I C data.
DS4404
DS4402
2
2
1
2
1
2
SDA
SCL
2
2
I C Serial Clock. Input for I C clock.
Ground
3
3
GND
FS3
4
—
—
6
Full-Scale Calibration Input. A resistor to ground on these pins determines the full-scale
current for each output. FS0 controls OUT0, FS1 controls OUT1, etc. (DS4402 has only
two inputs: FS0 and FS1.)
5
FS2
6
FS1
7
7
FS0
8
8
OUT0
OUT1
OUT2
OUT3
2
10
12
14
10
—
—
Current Output. Sinks or sources the current determined by the I C interface and the
resistance connected to FSx. (DS4402 has only two outputs: OUT0 and OUT1.)
2
Address Select Inputs. Tri-level inputs (V , GND, N.C.) determine the I C slave address.
CC
9, 11
9, 11
A0, A1
See the Detailed Description section for the nine available device addresses.
13
—
—
13
4, 5, 12, 14
—
V
Power Supply
CC
N.C.
EP
No Connection
Exposed Pad. Leave floating or connect to GND.
SDA SCL A1 A0
V
CC
2
I C-COMPATIBLE
DS4402/DS4404
SERIAL INTERFACE
V
CC
FBh
F8h
F9h
FAh
SOURCE OR
SINK MODE
31-POSITIONS
EACH FOR SINK
AND SOURCE
MODE
CURRENT
DAC3
CURRENT
DAC0
CURRENT
DAC1
CURRENT
DAC2
GND
FS1
R
FS0
OUT0
OUT1
FS2
R
FS3
R
OUT3
OUT2
R
FS0
FS1
FS2
FS3
DS4404
Figure 1. Functional Diagram
4
______________________________________________________________________
2
Two/Four-Channel, I C Adjustable Current DAC
Detailed Description
2
The DS4402/DS4404 contain two/four I C adjustable
current sources (Figure 1) that are each capable of
sinking and sourcing current. Each output has 31 sink
and 31 source settings that are programmed through
V
CC
2
the I C interface. The full-scale ranges (and corre-
R
IN
IN
R
IN
IN
sponding step sizes) of the outputs are determined by
external resistors that adjust the output currents over a
4:1 range. The formula to determine the external resis-
2
I C
A1
A0
ADDRESS
DECODE
tor values (R ) for each of the outputs is given by:
FS
R
R
Equation 1:
R
= (V
/ I ) x (31 / 4)
REF FS
FS
where I = desired full-scale current
FS
On power-up, the DS4402/DS4404 output zero current.
This is done to prevent it from sinking or sourcing an
incorrect current before the system host controller has
had a chance to modify the device’s setting.
2
Figure 2. I C Address Inputs
As a source for biasing instrumentation or other cir-
cuits, the DS4402/DS4404 provide a simple and inex-
Table 1 lists the slave address determined by the
address input combinations.
2
pensive current source with an I C interface for control.
The adjustable full-scale range allows the application to
get the most out of its 5-bit sink or source resolution.
Table 1. Slave Addresses
SLAVE ADDRESS
(HEXADECIMAL)
When used in adjustable power-supply applications
(see the Typical Operating Circuit), the DS4402/DS4404
do not affect the initial power-up supply voltage because
it defaults to providing zero output current on power-up.
As it sources or sinks current into the feedback voltage
node, it changes the amount of output voltage required
by the regulator to reach its steady state operating point.
By using the external resistor to set the output current
range, the devices provide flexibility for adjusting the
impedances of the feedback network or the range over
which the power supply can be controlled or margined.
A1
A0
GND
GND
GND
90h
92h
94h
96h
98h
9Ah
9Ch
9Eh
A0h
V
CC
V
V
GND
CC
CC
V
CC
N.C.
N.C.
GND
GND
V
CC
N.C.
N.C.
N.C.
V
CC
2
I C Slave Address
N.C.
2
The DS4402/DS4404 respond to one of nine I C slave
addresses determined by the two tri-level address
inputs. The three input states are connected to V
,
CC
connected to ground, or disconnected. To sense the
disconnected state (Figure 2), the address inputs have
weak internal resistors that pull the pins to mid-supply.
_____________________________________________________________________
5
2
Two/Four-Channel, I C Adjustable Current DAC
2
Memory Organization
To control the DS4402/DS4404’s current sources, write
to the memory addresses listed in Table 2.
I C Serial Interface Description
2
I C Definitions
The following terminology is commonly used to describe
I C data transfers:
2
Table 2. Memory Addresses
Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses, START and STOP conditions.
MEMORY ADDRESS
CURRENT SOURCE
(HEXADECIMAL)
F8h
OUT0
OUT1
OUT2*
OUT3*
Slave Devices: Slave devices send and receive data
at the master’s request.
F9h
FAh*
Bus Idle or Not Busy: Time between STOP and START
conditions when both SDA and SCL are inactive and in
their logic-high states. When the bus is idle it often initi-
ates a low-power mode for slave devices.
FBh*
*Only for DS4404.
START Condition: A START condition is generated by
the master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a START condition. See Figure 3 for
applicable timing.
The format of each output control register is given by:
MSB
LSB
S
X
X
D
D
D
D
D
0
4
3
2
1
STOP Condition: A STOP condition is generated by the
master to end a data transfer with a slave. Transitioning
SDA from low to high while SCL remains high generates
a STOP condition. See Figure 3 for applicable timing.
Where:
POWER-ON
DEFAULT
BIT
NAME
FUNCTION
Repeated START Condition: The master can use a
repeated START condition at the end of one data trans-
fer to indicate that it will immediately initiate a new data
transfer following the current one. Repeated starts are
commonly used during read operations to identify a spe-
cific memory address to begin a data transfer. A repeat-
ed START condition is issued identically to a normal
START condition. See Figure 3 for applicable timing.
Determines if DAC sources
or sinks current. For sink
S = 0, for source S = 1.
S
Sign Bit
0b
Reserved. Both bits read
zero.
X
Reserved
Data
00b
5-Bit Data Word Controlling
DAC Output. Setting 00000b
outputs zero current
regardless of the state of the
sign bit.
Bit Write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL, plus the
setup and hold time requirements (Figure 3). Data is
shifted into the device during the rising edge of the SCL.
D
00000b
X
Bit Read: At the end of a write operation, the master
must release the SDA bus line for the proper amount of
setup time (Figure 3) before the next rising edge of SCL
during a bit read. The device shifts out each bit of data
on SDA at the falling edge of the previous SCL pulse
and the data bit is valid at the rising edge of the current
SCL pulse. Remember that the master generates all
SCL clock pulses, including when it is reading bits from
the slave.
Example: I
= 800µA, and register F8h is written to a
FS0
value of 92h. Calculate the value of external resistance
required, and the magnitude of the output current with
this register setting.
R
FS
= (V
/ 800µA) x (31 / 4) = 11.9kΩ
REF
The MSB of the output register is 1, so the output is
sourcing the value corresponding to position 12h (18
decimal). The magnitude of the output current is equal to:
800µA x (18 / 31) = 465µA
6
______________________________________________________________________
2
Two/Four-Channel, I C Adjustable Current DAC
Acknowledgement (ACK and NACK): An Acknowledge-
ment (ACK) or Not Acknowledge (NACK) is always the
ninth bit transmitted during a byte transfer. The device
receiving data (the master during a read or the slave
during a write operation) performs an ACK by transmit-
ting a zero during the ninth bit. A device performs a
NACK by transmitting a one during the ninth bit. Timing
for the ACK and NACK is identical to all other bit writes
(Figure 4). An ACK is the acknowledgment that the
device is properly receiving data. A NACK is used to
terminate a read sequence or as an indication that the
device is not receiving data.
the slave address in the most significant 7 bits and the
R/W bit in the least significant bit. The DS4402/DS4404s’
slave address is determined by the state of the A0 and A1
address pins. Table 1 describes the addresses corre-
sponding to the state of A0 and A1.
When the R/W bit is 0 (such as in A0h), the master is
indicating it will write data to the slave. If R/W = 1 (A1h
in this case), the master is indicating it wants to read
from the slave. If an incorrect slave address is written,
the DS4402/DS4404 assume the master is communi-
2
cating with another I C device and ignore the commu-
nication until the next START condition is sent.
Byte Write: A byte write consists of 8 bits of information
transferred from the master to the slave (most significant
bit first) plus a 1-bit acknowledgement from the slave to
the master. The 8 bits transmitted by the master are
done according to the bit-write definition, and the
acknowledgement is read using the bit-read definition.
2
Memory Address: During an I C write operation, the
master must transmit a memory address to identify the
memory location where the slave is to store the data.
The memory address is always the second byte trans-
mitted during a write operation following the slave
address byte.
Byte Read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the bit
read definition above, and the master transmits an ACK
using the bit write definition to receive additional data
bytes. The master must NACK the last byte read to ter-
minated communication so the slave will return control
of SDA to the master.
2
I C Communication
Writing to a Slave: The master must generate a START
condition, write the slave address byte (R/W = 0), write
the memory address, write the byte of data, and gener-
ate a STOP condition. Remember that the master must
read the slave’s acknowledgement during all byte-write
operations.
Reading from a Slave: To read from the slave, the
master generates a START condition, writes the slave
address byte with R/W = 1, reads the data byte with a
NACK to indicate the end of the transfer, and generates
a STOP condition.
2
Slave Address Byte: Each slave on the I C bus
responds to a slave address byte sent immediately follow-
ing a START condition. The slave address byte contains
SDA
t
BUF
t
SP
t
HD:STA
t
LOW
t
t
F
R
SCL
t
SU:STA
t
HD:STA
t
HIGH
t
REPEATED
START
t
SU:STO
SU:DAT
STOP
START
t
HD:DAT
NOTE: TIMING IS REFERENCE TO V
AND V
.
IH(MIN)
IL(MAX)
2
Figure 3. I C Timing Diagram
_____________________________________________________________________
7
2
Two/Four-Channel, I C Adjustable Current DAC
2
Changing the address select inputs resets the I C inter-
Application Information
Example Calculations
for an Adjustable Power Supply
face. This function aborts the current transaction and puts
the SDA driver into a high-impedance state. This hard-
ware reset function should never be required because it
is achievable through software, but it does provide an
Using the typical circuit, assuming a typical output volt-
age of 2.0V, a feedback voltage of 0.8V, R1 = 500Ω,
and R2 = 333Ω, to adjust or margin the supply 20%
requires a full-scale current equal to [(0.2 x 2.0V) /
2
alternative way of resetting the I C interface, if needed.
V
CC
Decoupling
To achieve the best results when using the DS4402/
DS4404, decouple the power supply with a 0.01µF or
0.1µF capacitor. Use a high-quality ceramic surface-
mount capacitor if possible. Surface-mount compo-
nents minimize lead inductance, which improves
performance, and ceramic capacitors tend to have
adequate high-frequency response for decoupling
applications.
500Ω = 800µA]. Using Equation 1, R can be calculat-
FS
ed [R = (V
/ 800µA) x (31 / 4) = 11.9kΩ]. The cur-
FS
REF
rent DAC in this configuration allows the output voltage
to be stepped linearly from 1.6V to 2.4V using 63 set-
tings. This corresponds to a resolution of 12.7mV/step.
Power-Supply Feedback Voltage
The feedback voltage for adjustable power supplies
must be between 0.5V and V
- 0.5V for the DS4402/
CC
Layout Considerations
Care should be taken to ensure that traces underneath
the DS4402/DS4404 do not short with the exposed pad.
The exposed pad should be connected to the signal
ground, or can be left floating.
DS4404 to properly sink/source currents for adjusting
the voltage.
2
I C Reset on Address Change
2
In addition to defining the I C slave address, the DS4402/
DS4404 address select inputs have an alternate function.
2
TYPICAL I C WRITE TRANSACTION
MSB
a7
LSB
MSB
LSB
MSB
LSB
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
START
a6
a5
a4 a3 a2
a1 R/W
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
STOP
READ/
WRITE
REGISTER/MEMORY ADDRESS
SLAVE
ADDRESS*
DATA
*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0 AND A1 (SEE TABLE 1).
2
EXAMPLE I C TRANSACTIONS (WHEN A0 AND A1 ARE N.C.)
A0h
F9h
A) SINGLE BYTE WRITE
-WRITE RESISTOR
F9h TO 00h
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
1 0 1 0 0 0 0 0
0 0 0 0 0 0 0 0
1 1 1 1 1 0 0 1
START
START
STOP
A0h
F8h
A1h
DATA
B) SINGLE BYTE READ
-READ RESISTOR F8h
MASTER
NACK
SLAVE
ACK
SLAVE
ACK
REPEATED
START
SLAVE
ACK
1 0 1 0 0 0 0 1
1 0 1 0 0 0 0 0
STOP
1 1 1 1 1 0 0 0
2
Figure 4. I C Communication Examples
Package Information
Chip Information
For the latest package outline information, go to
TRANSISTOR COUNT: 10,992
www.maxim-ic.com/DallasPackInfo.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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is a registered trademark of Maxim Integrated Products, Inc.
is a registered trademark of Dallas Semiconductor Corporation.
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