DS4412U+T&R [MAXIM]
D/A Converter, 1 Func, Serial Input Loading, PDSO8, LEAD FREE, MICRO, SOP-8;
| 型号： | DS4412U+T&R |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | D/A Converter, 1 Func, Serial Input Loading, PDSO8, LEAD FREE, MICRO, SOP-8 |
| 文件： | 总9页 (文件大小：137K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rev 0; 9/07
2
Dual-Channel, I C Adjustable
Sink/Source Current DAC
DS412
General Description
The DS4412 contains two I C adjustable-current DACs
that are each capable of sinking or sourcing current. Each
output has 15 sink and 15 source settings that are pro-
grammed by I C interface. The full-scale range and step
size of each output is determined by an external resistor
that can adjust the output current over a 4:1 range.
Features
2
♦ Two Current DACs
♦ Full-Scale Current 500µA to 2mA
♦ Full-Scale Range for Each DAC Determined by
2
External Resistors
♦ 15 Settings Each for Sink and Source Modes
2
♦ I C-Compatible Serial Interface
The output pins, OUT0 and OUT1, power-up in a high-
impedance state.
♦ Low Cost
♦ Small Package (8-Pin µSOP)
♦ -40°C to +85°C Temperature Range
♦ 2.7V to 5.5V Operation
Applications
Power-Supply Adjustment
Power-Supply Margining
Adjustable Current Sink or Source
Ordering Information
Pin Configuration
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
8 μSOP
DS4412U+
TOP VIEW
DS4412U+T&R
8 μSOP
+
+Denotes a lead-free package.
T&R = Tape and reel.
1
2
3
4
8
7
6
5
SDA
SCL
FS1
V
CC
OUT1
OUT0
FS0
DS4412
GND
μSOP
Typical Operating Circuit
V
CC
V
OUT0
V
OUT1
OUT
OUT
4.7kΩ
4.7kΩ
V
CC
SDA
SCL
DC-DC
CONVERTER
DC-DC
CONVERTER
R
0A
R
1A
FB
FB
OUT0
OUT1
DS4412
R
0B
R
1B
GND
FS0
FS1
R
FS0
R
FS1
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
2
Dual-Channel, I C Adjustable
Sink/Source Current DAC
ABSOLUTE MAXIMUM RATINGS
Voltage Range on V , SDA, and SCL
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-55°C to +125°C
Soldering Temperature .....................................Refer to IPC/JEDEC
J-STD-020 Specification
CC
Relative to Ground.............................................-0.5V to +6.0V
Voltage Range on OUT0, OUT1 Relative to
Ground ................-0.5V to (V
+ 0.5V) (Not to exceed 6.0V.)
CC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DS412
RECOMMENDED OPERATING CONDITIONS
(T = -40°C to +85°C)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage
V
(Note 1)
2.7
5.5
V
CC
0.7 x
V
+
CC
0.3
Input Logic 1 (SDA, SCL)
Input Logic 0 (SDA, SCL)
V
V
V
IH
V
CC
0.3 x
V
V
-0.3
IL
CC
DC ELECTRICAL CHARACTERISTICS
(V
CC
= +2.7V to +5.5V, T = -40°C to +85°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
500
1
UNITS
μA
Supply Current
I
V
V
= 5.5V (Note 2)
CC
CC
Input Leakage (SDA, SCL)
Output Leakage (SDA)
I
= 5.5V
μA
IL
CC
I
L
1
μA
V
V
= 0.4V
= 0.6V
3
6
OL
OL
Output Current Low (SDA)
I
mA
V
OL
RFS
R
FS
Voltage
V
0.607
OUTPUT CURRENT CHARACTERISTICS
(V
CC
= +2.7V to +5.5V, T = -40°C to +85°C.)
A
PARAMETER
SYMBOL
CONDITIONS
> V (Note 3)
OUT:SINK
MIN
TYP
MAX
UNITS
Output Voltage for Sinking
V
V
CC
0.5
3.5
V
OUT:SINK
Output Voltage for Sourcing
Current
V
0.75
-
CC
V
(Note 3)
0
V
OUT:SOURCE
Full-Scale Sink Output Current
Full-Scale Source Output Current
I
(Note 3)
(Note 3)
0.5
2.0
mA
mA
OUT:SINK
I
-2.0
-0.5
OUT:SOURCE
+25°C, V = 4.0V; using 0.1% R
CC
resistor (Note 4)
FS
Output-Current Full-Scale
Accuracy
I
6
%
OUT:FS
OUT:TC
V
= V
= 1.2V
OUT1
OUT0
Output-Current Temperature
Coefficient
I
(Note 5)
75
ppm/°C
%/V
DC source
DC sink
+0.36
+0.12
Output-Current Variation due to
Power-Supply Change
2
_______________________________________________________________________________________
2
Dual-Channel, I C Adjustable
Sink/Source Current DAC
DS412
OUTPUT CURRENT CHARACTERISTICS (continued)
(V
CC
= +2.7V to +5.5V, T = -40°C to +85°C.)
A
PARAMETER
SYMBOL
CONDITIONS
measured at 1.2V
MIN
TYP
-0.02
+0.12
MAX
UNITS
DC source, V
Output-Current Variation due to
Output Voltage Change
OUT
%/V
DC sink, V
measured at 1.2V
OUT
Output Leakage Current at Zero
Current Setting
I
-1
+1
μA
ZERO
Output-Current Differential
Linearity
DNL
INL
(Note 6)
(Note 7)
0.5
1
LSB
LSB
Output-Current Integral Linearity
2
I C AC ELECTRICAL CHARACTERISTICS
(V
CC
= +2.7V to +5.5V, T = -40°C to +85°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCL Clock Frequency
f
(Note 8)
0
400
kHz
SCL
Bus Free Time Between STOP
and START Conditions
t
1.3
0.6
µs
µs
BUF
Hold Time (Repeated) START
Condition
t
HD:STA
Low Period of SCL
High Period of SCL
Data Hold Time
t
1.3
0.6
0
µs
µs
µs
ns
µs
LOW
t
HIGH
t
0.9
DH:DAT
Data Setup Time
START Setup Time
t
100
0.6
SU:DAT
t
SU:STA
20 +
SDA and SCL Rise Time
SDA and SCL Fall Time
t
(Note 9)
(Note 9)
300
300
ns
ns
R
0.1C
B
20 +
t
F
0.1C
B
STOP Setup Time
t
0.6
µs
SU:STO
SDA and SCL Capacitive Loading
C
(Note 9)
400
pF
B
Note 1: All voltages with respect to ground, currents entering the IC are specified positive and currents exiting the IC are negative.
Note 2: Supply current specified with all outputs set to zero current setting with all inputs driven to well-defined logic levels. SDA and
SCL are connected to V . Excludes current through R resistors (I
). Total current includes I + 2.5 x (I
+ I
RFS0
).
CC
FS
RFS
CC
RFS0
Note 3: The output voltage range must be satisfied to ensure the device meets its accuracy and linearity specifications.
Note 4: Input resistors R must be between 2.25kΩ and 9.0kΩ to ensure the device meets its accuracy and linearity specifications.
FS
Note 5: Temperature drift excludes drift caused by external resistor.
Note 6: Differential linearity is defined as the difference between the expected incremental current increase with respect to position
and the actual increase. The expected incremental increase is the full-scale range divided by 15.
Note 7: Integral linearity is defined as the difference between the expected value as a function of the setting and the actual value.
The expected value is a straight line between the zero and the full-scale values proportional to the setting.
2
Note 8: Timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I C standard-mode timing.
Note 9: C —total capacitance of one bus line in pF.
B
_______________________________________________________________________________________
3
2
Dual-Channel, I C Adjustable
Sink/Source Current DAC
Pin Description
NAME
SDA
PIN
1
FUNCTION
2
2
I C Serial Data. Input/output for I C data.
2
2
SCL
2
I C Serial Clock. Input for I C clock.
FS1
3
Full-Scale Calibration Inputs. A resistor to ground on these pins determines the full-scale current
for each output. FS0 controls OUT0, FS1 controls OUT1.
DS412
FS0
5
GND
OUT0
OUT1
4
Ground
6
Current Outputs. Sinks or sources the current determined by the register settings and the
resistance connected to FS0 and FS1.
7
V
CC
8
Power Supply
Typical Operating Characteristics
(Applies to OUT0 and OUT1. V
otherwise noted.)
= 2.7V to 5.0V, SDA = SCL = V , T = +25°C, and no loads on OUT0, OUT1, FS0, or FS1, unless
CC A
CC
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. TEMPERATURE
VOLTCO (SOURCE)
2.5
2.4
2.3
2.2
2.1
2.0
0.5
0.4
0.3
0.2
0.1
0
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
2.2kΩ LOAD ON FS0 AND FS1
V
= 5.0V
CC
DOES NOT INCLUDE CURRENT DRAWN BY
RESISTORS CONNECTED TO FS0 AND FS1.
V
CC
= 3.3V
V
= 2.7V
CC
DOES NOT INCLUDE CURRENT DRAWN BY
RESISTORS CONNECTED TO FS0 AND FS1.
0
1
2
3
4
5
2.7
3.2
3.7
4.2
4.7
5.2
-40
-20
0
20
40
60
80
V
(V)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
OUT
TEMPERATURE COEFFICIENT
vs. SETTING (SOURCE)
TEMPERATURE COEFFICIENT
vs. SETTING (SINK)
VOLTCO (SINK)
-2.0
-2.1
-2.2
-2.3
-2.4
-2.5
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
2.2kΩ LOAD ON FS0 AND FS1
+25°C TO -40°C
+25°C TO -40°C
+25°C TO +85°C
+25°C TO +85°C
RANGE FOR THE 0.5mA TO 2.0mA
CURRENT-SOURCE RANGE.
RANGE FOR THE 0.5mA TO 2.0mA
CURRENT-SOURCE RANGE.
0
1
2
3
4
0
5
10
15
0
5
10
15
V
(V)
OUT
SETTING (DEC)
SETTING (DEC)
4
_______________________________________________________________________________________
2
Dual-Channel, I C Adjustable
Sink/Source Current DAC
DS412
Typical Operating Characteristics (continued)
(Applies to OUT0 and OUT1. V
otherwise noted.)
= 2.7V to 5.0V, SDA = SCL = V , T = +25°C, and no loads on OUT0, OUT1, FS0, or FS1, unless
CC A
CC
INTEGRAL LINEARITY
DIFFERENTIAL LINEARITY
1.0000
1.0
0.8
RANGE FOR THE 0.5mA TO 2.0mA
CURRENT SOURCE AND SINK RANGE
RANGE FOR THE 0.5mA TO 2.0mA
CURRENT SOURCE AND SINK RANGE
0.7500
0.5000
0.2500
0.0000
-0.2500
-0.5000
-0.7500
-1.0000
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
5
10
15
0
5
10
15
SETTING (DEC)
SETTING (DEC)
Block Diagram
SDA SCL
V
CC
2
I C-COMPATIBLE
SERIAL INTERFACE
DS4412
V
CC
F8h
F9h
SOURCE OR
SINK MODE
15 POSITIONS
EACH FOR SINK
AND SOURCE
MODE
CURRENT
DAC0
CURRENT
DAC1
GND
FS1
R
FS0
OUT0
OUT1
R
FS0
FS1
_______________________________________________________________________________________
5
2
Dual-Channel, I C Adjustable
Sink/Source Current DAC
Memory Organization
Detailed Description
The DS4412’s current sources are controlled by writing
to the memory addresses in Table 1.
2
The DS4412 contains two I C adjustable-current
sources that are each capable of sinking and sourcing
current. Each output, OUT0 and OUT1, has 15 sink and
15 source settings that are programmed through the
Table 1. Memory Addresses
2
I C interface. The full-scale ranges and corresponding
MEMORY ADDRESS
CURRENT SOURCE
(HEXADECIMAL)
step sizes of the outputs are determined by external
resistors, connected to pins FS0 and FS1, which can
adjust the output currents over a 4:1 range. The formula
to determine the positive and negative full-scale current
ranges for each of the four outputs is given by:
DS412
0xF8
0xF9
OUT0
OUT1
R
= (V / I ) x (15 / 1.974)
RFS FS
The format of each output control register is given by:
FS
MSB
LSB
where V
is the R
voltage (see DC Electrical
FS
FS
RFS
Characteristics), and R is the external resistor value.
S
X
X
X
D
D
D
D
0
3
2
1
On power-up, the DS4412 outputs zero current. This is
done to prevent it from sinking or sourcing an incorrect
current before the system host controller has had a
chance to modify the device’s setting.
Where:
POWER-ON
DEFAULT
BIT
NAME
FUNCTION
As a source for biasing instrumentation or other cir-
cuits, the DS4412 provides a simple and inexpensive
Determines if DAC sources
or sinks current. For sink
S = 0, for source S = 1.
2
current source with an I C interface for control. The
S
Sign Bit
0b
adjustable full-scale range allows the application to get
the most out of its 4-bit sink or source resolution.
X
Reserved Reserved.
4-Bit Data Word Controlling
XXX
When used in adjustable power-supply applications
(see Typical Operating Circuit), the DS4412 does not
affect the initial power-up supply voltage because it
defaults to providing zero output current on power-up.
As it sources or sinks current into the feedback voltage
node, it changes the amount of output voltage required
by the regulator to reach its steady state operating
DAC Output. Setting 0000b
outputs zero current
regardless of the state of the
sign bit.
D
Data
0000b
X
point. Using the external resistor, R , to set the output
FS
Example: R
= 4.8kΩ and register 0xF8h is written to
current range, the DS4412 provides some flexibility for
adjusting the range over which the power supply can
be controlled or margined.
FS0
a value of 0x8Ah. Calculate the output current.
I
FS
= (0.607V / 4.8kΩ) x (15 / 1.974) = 949.85µA
The MSB of the output register is 1, so the output is
sourcing the value corresponding to position Ah (10 dec-
imal). The magnitude of the output current is equal to:
949.85µA x (10 / 15) = 633.23µA
6
_______________________________________________________________________________________
2
Dual-Channel, I C Adjustable
Sink/Source Current DAC
DS412
2
new data transfer following the current one. Repeated
I C Serial Interface Description
starts are commonly used during read operations to
identify a specific memory address to begin a data
transfer. A repeated START condition is issued identi-
cally to a normal START condition. See Figure 1 for
applicable timing.
2
I C Slave Address
The DS4412’s slave address is 90h.
2
I C Definitions
The following terminology is commonly used to describe
I C data transfers:
Bit Write: Transitions of SDA must occur during the
low state of SCL. The data on SDA must remain valid
and unchanged during the entire high pulse of SCL,
plus the setup and hold time requirements (Figure 1).
Data is shifted into the device during the rising edge
of the SCL.
2
Master Device: The master device controls the slave
devices on the bus. The master device generates
SCL clock pulses and START and STOP conditions.
Slave Devices: Slave devices send and receive
data at the master’s request.
Bit Read: At the end of a write operation, the master
must release the SDA bus line for the proper amount
of setup time (Figure 1) before the next rising edge of
SCL during a bit read. The device shifts out each bit of
data on SDA at the falling edge of the previous SCL
pulse and the data bit is valid at the rising edge of the
current SCL pulse. Remember that the master gener-
ates all SCL clock pulses, including when it is reading
bits from the slave.
Bus Idle or Not Busy: Time between STOP and
START conditions when both SDA and SCL are inac-
tive and in their logic-high states. When the bus is
idle it often initiates a low-power mode for slave
devices.
START Condition: A START condition is generated
by the master to initiate a new data transfer with a
slave. Transitioning SDA from high to low while SCL
remains high generates a START condition. See
Figure 1 for applicable timing.
Acknowledgement (ACK and NACK): An
Acknowledgement (ACK) or Not Acknowledge
(NACK) is always the ninth bit transmitted during a
byte transfer. The device receiving data (the master
during a read or the slave during a write operation)
performs an ACK by transmitting a zero during the
ninth bit. A device performs a NACK by transmitting
a one during the ninth bit. Timing for the ACK and
NACK is identical to all other bit writes (Figure 2). An
ACK is the acknowledgment that the device is prop-
erly receiving data. A NACK is used to terminate a
STOP Condition: A STOP condition is generated by
the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL
remains high generates a STOP condition. See
Figure 1 for applicable timing.
Repeated START Condition: The master can use a
repeated START condition at the end of one data
transfer to indicate that it will immediately initiate a
SDA
t
BUF
t
SP
t
HD:STA
t
LOW
t
t
F
R
SCL
t
SU:STA
t
HD:STA
t
HIGH
t
REPEATED
START
t
SU:STO
SU:DAT
STOP
START
t
HD:DAT
NOTE: TIMING IS REFERENCED TO V
AND V
.
IL(MAX)
IH(MIN)
2
Figure 1. I C Timing Diagram
_______________________________________________________________________________________
7
2
Dual-Channel, I C Adjustable
Sink/Source Current DAC
2
TYPICAL I C WRITE TRANSACTION
MSB
1
LSB
R/W
MSB
LSB
MSB
LSB
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
START
0
0
1
0
0
0
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
STOP
READ/
WRITE
REGISTER/MEMORY ADDRESS
SLAVE
ADDRESS
DATA
DS412
2
EXAMPLE I C TRANSACTIONS
90h
F9h
A) SINGLE BYTE WRITE
-WRITE RESISTOR
F9h TO 00h
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
1 0 0 1 0 0 0 0
0 0 0 0 0 0 0 0
1 1 1 1 1 0 0 1
START
STOP
90h
F8h
90h
DATA
B) SINGLE BYTE READ
-READ RESISTOR F8h
MASTER
NACK
SLAVE
ACK
SLAVE
ACK
REPEATED
START
SLAVE
ACK
1 0 0 1 0 0 0 1
START
1 0 0 1 0 0 0 0
STOP
1 1 1 1 1 0 0 0
2
Figure 2. I C Communication Examples
read sequence or as an indication that the device is
not receiving data.
When the R/W bit is 0 (such as in 90h), the master is
indicating it will write data to the slave. If R/W = 1
(91h in this case), the master is indicating it wants to
read from the slave. If an incorrect slave address is
written, the DS4412 assumes the master is commu-
Byte Write: A byte write consists of 8 bits of informa-
tion transferred from the master to the slave (most sig-
nificant bit first) plus a 1-bit acknowledgement from
the slave to the master. The 8 bits transmitted by the
master are done according to the bit-write definition,
and the acknowledgement is read using the bit-read
definition.
2
nicating with another I C device and ignores the
communication until the next START condition is
sent.
2
Memory Address: During an I C write operation,
the master must transmit a memory address to iden-
tify the memory location where the slave is to store
the data. The memory address is always the second
byte transmitted during a write operation following
the slave address byte.
Byte Read: A byte read is an 8-bit information trans-
fer from the slave to the master plus a 1-bit ACK or
NACK from the master to the slave. The 8 bits of
information that are transferred (most significant bit
first) from the slave to the master are read by the
master using the bit read definition above, and the
master transmits an ACK using the bit write defini-
tion to receive additional data bytes. The master
must NACK the last byte read to terminated commu-
nication so the slave will return control of SDA to the
master.
2
I C Communication
Writing to a Slave: The master must generate a START
condition, write the slave address byte (R/W = 0), write
the memory address, write the byte of data, and gener-
ate a STOP condition. Remember that the master must
read the slave’s acknowledgement during all byte-write
operations.
2
Slave Address Byte: Each slave on the I C bus
responds to a slave address byte sent immediately fol-
lowing a START condition. The slave address byte
contains the slave address in the most significant 7
bits and the R/W bit in the least significant bit. The
DS4412’s slave address is 90h.
Reading from a Slave: To read from the slave, the
master generates a START condition, writes the slave
address byte with R/W = 1, reads the data byte with a
NACK to indicate the end of the transfer, and generates
a STOP condition.
8
_______________________________________________________________________________________
2
Dual-Channel, I C Adjustable
Sink/Source Current DAC
DS412
Where:
Application Information
V
R
FB
0B
Example Calculation
for an Adjustable Power Supply
I
=
R0B
In this example, the Typical Operating Circuit is used
as a base to create Figure 3, a 2.0V voltage supply with
20ꢀ margin. The adjustable power supply has a
And
V
− V
FB
OUT
R
I
=
R0A
DC-DC converter output voltage, V
, of 2.0V and a
OUT
0A
DC-DC converter feedback voltage, V , of 0.8V. To
FB
To create a 20ꢀ margin in the supply voltage, the value
determine the relationship of R and R , we start with
0A
0B
of V
is set to 2.4V. With these values in place, R is
OUT
0B
the equation:
calculated to be 267Ω, and R is calculated to be 400Ω.
0A
R
0B
+ R
The current DAC in this configuration allows the output
voltage to be moved linearly from 1.6V to 2.4V using 15
settings. This corresponds to a resolution of 25.8mV/step.
V
=
× V
OUT
FB
R
0A
0B
Substituting V = 0.8V and V
= 2.0V, the relation-
FB
OUT
V
Decoupling
CC
ship between R and R is determined to be:
0A
0B
To achieve the best results when using the DS4412,
decouple the power supply with a 0.01µF or 0.1µF
capacitor. Use a high-quality ceramic surface-mount
capacitor if possible. Surface-mount components mini-
mize lead inductance, which improves performance,
and ceramic capacitors tend to have adequate high-
frequency response for decoupling applications.
R
0A
= 1.5 x R
0B
I
is chosen to be 1mA (midrange source/sink cur-
OUT0
rent for the DS4412). Summing the currents into the
feedback node, we have the following
I
= I
− I
OUT0
R0B R0A
V
CC
V
OUT
= 2.0V
OUT
FB
4.7kΩ
4.7kΩ
V
CC
SDA
SCL
DC-DC
CONVERTER
I
I
R
= 400Ω
= 267Ω
R0A
0A
OUT0
V
FB
= 0.8V
DS4412
R0B
R
0B
GND
FS0
I
OUT0
R
FS0
= 4.612kΩ
Figure 3. Example Application Circuit
Package Information
For the latest package outline information, go to
www.maxim-ic.com/DallasPackInfo.
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相关型号：
DS4420N+T&R
Audio Amplifier, 2 Channel(s), 1 Func, 3 X 3 MM, 0.80 MM HEIGHT, LEAD FREE, TDFN-14
MAXIM
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