3D3612W-50 [DATADELAY]
8-BIT & 12-BIT PROGRAMMABLE PULSE GENERATORS; 8位和12位可编程脉冲发生器
| 型号： | 3D3612W-50 |
| 厂家： | 
DATA DELAY DEVICES, INC. |
| 描述： | 8-BIT & 12-BIT PROGRAMMABLE PULSE GENERATORS |
| 文件： | 总7页 (文件大小：352K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3D3608 & 3D3612
8-BIT & 12-BIT PROGRAMMABLE
PULSE GENERATORS
(SERIES 3D3608 & 3D3612: PARALLEL INTERFACE)
FEATURES
PACKAGES / PINOUTS
TRIG
RES
P0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDD
OUT
OUTB
P1
TRIG
RES
P0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
OUT
OUTB
P1
•
•
•
•
•
•
•
•
•
All-silicon, low-power CMOS technology
P2
3.3V operation
P2
P4
P3
Vapor phase, IR and wave solderable
Programmable via latched parallel interface
Increment range: 0.25ns through 800us
Pulse width tolerance: 1% (See Table 1)
Supply current: 8mA typical
P6
P5
P4
P3
P8
P7
P6
P5
NC
P9
NC
P7
P10
GND
AE
GND
AE
P11
3D3608R-xx SOIC
3D3612W-xx SOL
Temperature stability: ±1.5% max (-40C to 85C)
Vdd stability: ±1.0% max (3.0V to 3.6V)
For mechanical dimensions, click here.
For package marking details, click here.
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The 3D3608 & 3D3612 devices are versatile 8- & 12-bit
programmable monolithic pulse generators. A rising-edge on the
trigger input (TRIG) initiates the pulse, which is presented on the
output pins (OUT,OUTB). The pulse width, programmed via the
parallel interface, can be varied over 255 (3D3608) or 4095
(3D3612) equal steps according to the formula:
TRIG Trigger Input
RES
Reset Input
OUT Pulse Output
OUTB Complementary
Pulse Output
AE
Address Enable Input
P0-P11 Address Inputs
VDD +3.3 Volts
GND Ground
tPW = tinh + addr * tinc
where addr is the programmed address, tinc is the pulse width
increment (equal to the device dash number), and tinh is the
inherent (address zero) pulse width. The device also offers a reset
input (RES), which can be used to terminate the pulse before the
programmed time has expired.
NC
Do not connect externally
The all-CMOS 3D3608 & 3D3612 integrated circuits have been designed as reliable, economic alternatives
to hybrid TTL pulse generators. The 3D3608 is offered in a standard 16-pin SOIC, and the 3D3612 is
offered in a standard 20-pin SOL.
TABLE 1: PART NUMBER SPECIFICATIONS
PART #
(8-BIT)
PART #
(12-BIT)
Pulse Width
Increment
Maximum
Maximum
PART #
(8-BIT)
Pulse Width
Increment
Maximum
P.W. (8-Bit)
P.W. (12-Bit)
P.W. (8-Bit)
3D3608R-0.25 3D3612W-0.25
3D3608R-100K
0.25ns ± 0.12ns
0.50ns ± 0.25ns
1.0ns ± 0.5ns
2.0ns ± 1.0ns
5.0ns ± 2.5ns
10ns ± 5.0ns
20ns ± 10ns
73.25ns ± 3ns
137.5ns ± 3ns
265ns ± 3ns
520ns ± 6ns
1.03us ± 10ns
2.05us ± 21ns
4.10us ± 41ns
8.19us ± 82ns
100us ± 50us 25.5ms ± 260us
200us ± 100us 51.0ms ± 510us
3D3608R-0.5
3D3608R-1
3D3608R-2
3D3608R-5
3D3608R-10
3D3608R-20
3D3608R-50
3D3608R-100 3D3612W-100
3D3608R-200 3D3612W-200
3D3608R-500 3D3612W-500
3D3608R-1K
3D3608R-2K
3D3608R-5K
3D3608R-10K 3D3612W-10K
3D3608R-20K 3D3612W-20K
3D3608R-50K 3D3612W-50K
3D3612W-0.5
3D3612W-1
3D3612W-2
3D3612W-5
3D3612W-10
3D3612W-20
3D3612W-50
3D3608R-200K
3D3608R-500K
3D3608R-750K
500us ± 250us
750us ± 375us
128ms ± 1.3ms
191ms ± 1.9ms
1.28us ± 13ns 20.5us ± 205ns
2.56us ± 26ns 41.0us ± 410ns
5.11us ± 52ns 81.9us ± 819ns
50ns ± 25ns 12.8us ± 128ns
100ns ± 50ns 25.5us ± 255ns
200ns ± 100ns 51.0us ± 510ns
205us ± 2.1us
410us ± 4.1us
819us ± 8.2us
2.05ms ± 21us
4.10ms ± 41us
8.19ms ± 82us
NOTE: Any increment between 0.25ns
and 800us (50us for the 12-bit generator)
not shown is also available as a standard
device.
500ns ± 250ns
1.0us ± 0.5us
2.0us ± 1.0us
5.0us ± 2.5us
10us ± 5.0us
20us ± 10us
128us ± 1.3us
255us ± 2.6us
510us ± 5.2us
1.28ms ± 13us 20.5ms ± 205us
2.55ms ± 26us 41.0ms ± 410us
5.10ms ± 52us 81.9ms ± 819us
3D3612W-1K
3D3612W-2K
3D3612W-5K
50us ± 25us 12.8ms ± 128us 205ms ± 2.1 ms
2006 Data Delay Devices
Doc #06010
5/8/2006
DATA DELAY DEVICES, INC.
1
3 Mt. Prospect Ave. Clifton, NJ 07013
3D3608 & 3D3612
APPLICATION NOTES
GENERAL INFORMATION
The absolute error is defined as follows:
Figure 1 illustrates the main functional blocks of
the 3D3608 & 3D3612. Since these devices are
CMOS designs, all unused input pins must be
returned to well-defined logic levels, VDD or
Ground.
eabs = tPW – (tinh + addr * tinc)
where tinh is the nominal inherent delay. The
absolute error is limited to 1.5 LSB or 3.0 ns,
whichever is greater, at every address.
The pulse generator architecture is comprised of
a number of delay cells (for fine control) and an
oscillator & counter (for coarse control). Each
device is individually trimmed for maximum
accuracy and linearity throughout the address
range. The change in pulse width from one
address setting to the next is called the
The inherent pulse width error is the deviation of
the inherent width from its nominal value. It is
limited to 2.0 ns from the nominal inherent pulse
width of 10 ns.
PULSE WIDTH STABILITY
The characteristics of CMOS integrated circuits
are strongly dependent on power supply and
temperature. The 3D3608 & 3D3612 utilize novel
compensation circuitry to minimize the
increment, or LSB. It is nominally equal to the
device dash number. The minimum pulse width,
achieved by setting the address to zero, is called
the inherent pulse width.
performance variations induced by fluctuations in
power supply and/or temperature.
For best performance, it is essential that the
power supply pin be adequately bypassed and
filtered. In addition, the power bus should be of
as low an impedance construction as possible.
Power planes are preferred. Also, signal traces
should be kept as short as possible.
With regard to stability, the output pulse width of
the 3D3608 & 3D3612 at a given address, addr,
can be split into two components: the inherent
pulse width (tinh) and the relative pulse width (tPW
- tinh). These components exhibit very different
stability coefficients, both of which must be
considered in very critical applications.
PULSE WIDTH ACCURACY
There are a number of ways of characterizing the
pulse width accuracy of a programmable pulse
generator. The first is the differential nonlinearity
(DNL), also referred to as the increment error. It
is defined as the deviation of the increment at a
given address from its nominal value. For most
dash numbers, the DNL is within 0.5 LSB at
every address (see Table 1: Pulse Width Step).
The thermal coefficient of the relative pulse width
is limited to ±250 PPM/C (except for the -0.25),
which is equivalent to a variation, over the -40C
to 85C operating range, of ±1.5% (±9% for the
dash 0.25) from the room-temperature pulse
width. This holds for all dash numbers. The
thermal coefficient of the inherent pulse width is
nominally +20ps/C for dash numbers less than 5,
and +30ps/C for all other dash numbers.
The integrated nonlinearity (INL) is determined
by first constructing the least-squares best fit
straight line through the pulse-width-versus-
address data. The INL is then the deviation of a
given width from this line. For all dash numbers,
the INL is within 1.0 LSB at every address.
The power supply sensitivity of the relative pulse
width is ±1.0% (±3.0% for the dash 0.25) over the
3.0V to 3.6V operating range, with respect to the
pulse width at the nominal 3.3V power supply.
This holds for all dash numbers. The sensitivity of
the inherent pulse width is nominally -5ps/mV for
all dash numbers.
The relative error is defined as follows:
erel = (tPW – tinh) – addr * tinc
where addr is the address, tPW is the measured
width at this address, tinh is the measured
inherent width, and tinc is the nominal increment.
It is very similar to the INL, but simpler to
calculate. For most dash numbers, the relative
error is less than 1.0 LSB at every address (see
Table 1).
It should also be noted that the DNL is also
adversely affected by thermal and supply
variations, particularly at the MSL/LSB
crossovers (ie, 63 to 64, 127 to 128, etc).
Doc #06010
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
2
5/8/2006
3D3608 & 3D3612
APPLICATION NOTES (CONT’D)
TRIGGER & RESET TIMING
ADDRESS UPDATE
Figure 2 shows the timing diagram of the device
when the reset input (RES) is not used. In this
case, the pulse is triggered by the rising edge of
the TRIG signal and ends at a time determined
by the address loaded into the device. While the
pulse is active, any additional triggers occurring
are ignored. Once the pulse has ended, and after
a short recovery time, the next trigger is
The 3D3608/3D3612 can operate in one of two
addressing modes. In the transparent mode (AE
held high), the parallel address inputs must
persist for the duration of the output pulse, in
accordance with Figure 4. In the latched mode,
the address data is stored internally, which
allows the parallel inputs to be connected to a
multi-purpose data bus. Timing for this mode is
also shown in Figure 4.
recognized. Figure 3 shows the timing for the
case where a reset is issued before the pulse
has ended. Again, there is a short recovery time
required before the next trigger can occur.
TRIGGER
RESET
TRG
RES
OUT
INPUT
LOGIC
DELAY
LINE
OSCILLATOR/
COUNTER
OUTPUT
LOGIC
OUTB
PULSE OUT
BIT-SHIFT LOGIC
ADDR ENABLE
AE
8- OR 12-BIT LATCH
P10 P11
P0 P1
P7 P8 P9
Figure 1: Functional block diagram
tTW
TRIG
tID
tPW
tRTO
OUT
OUTB
Figure 2: Timing Diagram (RES=0)
tTW
TRIG
RES
tRTR
tRW
tID
tRD
OUT
OUTB
Figure 3: Timing Diagram (with reset)
Doc #06010
5/8/2006
DATA DELAY DEVICES, INC.
3
3 Mt. Prospect Ave. Clifton, NJ 07013
3D3608 & 3D3612
APPLICATION NOTES (CONT’D)
Addr
VALID
VALID
tOA
tAT1
TRIG
OUT
Transparent Mode (AE=1)
tAW
AE
tDS
tDH
tAT1
Addr
VALID
tOA
tAT2
TRIG
OUT
Latched Mode
Figure 4: Address Update
Doc #06010
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
4
5/8/2006
3D3608 & 3D3612
DEVICE SPECIFICATIONS
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Input Pin Current
Storage Temperature
Lead Temperature
SYMBOL
VDD
MIN
-0.3
-0.3
-10
MAX
7.0
UNITS NOTES
V
V
VIN
VDD+0.3
10
IIN
TSTRG
TLEAD
mA
C
25C
-55
150
300
C
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 3.0V to 3.6V)
PARAMETER
SYMBOL
MIN
TYP
MAX UNITS
NOTES
Static Supply Current*
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
IDD
VIH
VIL
IIH
8.0
12.0
mA
V
2.0
0.8
1.0
1.0
-4.0
V
VIH = VDD
VIL = 0V
VDD = 3.0V
VOH = 2.4V
VDD = 3.0V
VOL = 0.4V
CLD = 5 pf
µA
µA
mA
IIL
IOH
High Level Output
-35.0
15.0
2.0
Current
Low Level Output Current
IOL
4.0
mA
ns
Output Rise & Fall Time
TR & TF
2.5
*IDD(Dynamic) = 2 * CLD * VDD * F
Input Capacitance = 5 pf typical
Output Load Capacitance (CLD) = 25 pf max
where:
CLD = Average capacitance load/output (pf)
F = Trigger frequency (GHz)
TABLE 4: AC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 3.0V to 3.6V)
PARAMETER
SYMBOL MIN
TYP MAX UNITS
REFER TO
Figure 2 & 3
Figure 2 & 3
Figure 2
Figure 2
Figure 3
Figure 3
Figure 3
Figure 4
Figure 4
Figure 4
Figure 4
Figure 4
Figure 4
Trigger Width
tTW
tID
5
ns
Trigger Inherent Delay
Output Pulse Width
Re-trigger Time
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPW
tRTO
tRW
tRD
3
Reset Width
TBD
Reset to Output Low
End of Reset to Next Trigger
AE Width
5
tRTR
tAW
tDS
3
12
10
3
Data Setup to AE Low
Data Hold from AE Low
Output Low to AE High
Data Valid to Trigger
AE High to Trigger
tDH
tOA
3
tAT1
tAT2
10
10
Doc #06010
5/8/2006
DATA DELAY DEVICES, INC.
5
3 Mt. Prospect Ave. Clifton, NJ 07013
3D3608 & 3D3612
TYPICAL APPLICATIONS
EN
FOUT
TRIG
RES
OUT
OUTB
AE
Addr
3D3608
AE
or
Addr
3D3612
FOUT = 1 / (tPW + tID + tNOR
)
EN
tID + tNOR
FOUT
Figure 5: Programmable Oscillator
TRIG
RES
OUT
SETB
D
OUT
+5
+5
IN
OUTB
Q
0V
0V
D-FF
D-FF
CK
QB
3D3608/12
AE
R-Edge
Delay
RESB
Addr
TRIG
RES
OUT
OUTB
SETB
D
Q
AER
AEF
Addr
CK
QB
3D3608/12
AE
F-Edge
Delay
RESB
Addr
IN
tPWR + tID + tFF
tPWF + tID + tFF
OUT
Figure 6: Programmable Delay Line
Doc #06010
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
6
5/8/2006
3D3608 & 3D3612
SILICON DEVICE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
OUTPUT:
Ambient Temperature: 25oC ± 3oC
Supply Voltage (Vcc): 5.0V ± 0.1V
Rload
Cload
:
:
10KΩ ± 10%
5pf ± 10%
Input Pulse:
High = 3.0V ± 0.1V
Threshold: 1.5V (Rising & Falling)
Low = 0.0V ± 0.1V
50Ω Max.
Source Impedance:
Rise/Fall Time:
3.0 ns Max. (measured
between 0.6V and 2.4V )
PWIN = 20ns
Device
Under
Test
Digital
Scope
10KΩ
Pulse Width:
Period:
PERIN = 2 x Prog’d Pulse Width
5pf
470Ω
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
PRINTER
COMPUTER
SYSTEM
REF
PULSE
OUT TRIG DEVICE UNDER OUT
IN
DIGITAL SCOPE/
GENERATOR
TEST (DUT)
TIME INTERVAL COUNTER
TRIG
TRIG
Figure 7: Test Setup
PERIN
PWIN
tRISE
tFALL
INPUT
VIH
2.4
1.5
0.6
2.4
1.5
0.6
SIGNAL
VIL
tID
tPW
OUTPUT
SIGNAL
VOH
1.5
1.5
VOL
Figure 8: Timing Diagram
Doc #06010
5/8/2006
DATA DELAY DEVICES, INC.
7
3 Mt. Prospect Ave. Clifton, NJ 07013
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