3D7220G-100 [DATADELAY]

MONOLITHIC 10-TAP FIXED DELAY LINE (SERIES 3D7220); 单片10 -TAP固定的延时线（系列3D7220 ）


型号：	3D7220G-100
厂家：	DATA DELAY DEVICES, INC.
描述：	MONOLITHIC 10-TAP FIXED DELAY LINE (SERIES 3D7220) 单片10 -TAP固定的延时线（系列3D7220 ）
文件：	总4页 (文件大小：233K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

3D7220

MONOLITHIC 10-TAP

FIXED DELAY LINE

(SERIES 3D7220)

FEATURES

PACKAGES

•

All-silicon, low-power CMOS technology

TTL/CMOS compatible inputs and outputs

Vapor phase, IR and wave solderable

Auto-insertable (DIP pkg.)

VDD

N/C

VDD

N/C

GND

O10

Low ground bounce noise

3D7220D-xx SOIC

Leading- and trailing-edge accuracy

Delay range: 0.75ns through 7000ns

Delay tolerance: 2% or 0.5ns

GND

O10

N/C

VDD

N/C

Temperature stability: ±2% typical (-40C to 85C)

Vdd stability: ±1% typical (4.75V-5.25V)

Minimum input pulse width: 15% of total delay

14-pin Gull-Wing available as drop-in

3D7220-xx DIP

3D7220G-xx Gull-Wing

GND

O10

For mechanical dimensions, click here.

For package marking details, click here.

3D7220S-xx SOL

replacement for hybrid delay lines

FUNCTIONAL DESCRIPTION

PIN DESCRIPTIONS

The 3D7220 10-Tap Delay Line product family consists of fixed-delay

CMOS integrated circuits. Each package contains a single delay line,

tapped and buffered at 10 points spaced uniformly in time. Tap-to-tap

(incremental) delay values can range from 0.75ns through 700ns. The

input is reproduced at the outputs without inversion, shifted in time as

per the user-specified dash number. The 3D7220 is TTL- and CMOS-

compatible, capable of driving ten 74LS-type loads, and features both

rising- and falling-edge accuracy.

Delay Line Input

Tap 1 Output (10%)

Tap 2 Output (20%)

Tap 3 Output (30%)

Tap 4 Output (40%)

Tap 5 Output (50%)

Tap 6 Output (60%)

Tap 7 Output (70%)

Tap 8 Output (80%)

Tap 9 Output (90%)

The all-CMOS 3D7220 integrated circuit has been designed as a

reliable, economic alternative to hybrid TTL fixed delay lines. It is

offered in a standard 14-pin auto-insertable DIP and space saving

surface mount 14-pin SOIC and 16-pin SOL packages.

O10 Tap 10 Output (100%)

VDD +5 Volts

GND Ground

TABLE 1: PART NUMBER SPECIFICATIONS

DASH

TOLERANCES

INPUT RESTRICTIONS

NUMBER

TOTAL

DELAY (ns)

6.75 ± 0.5*

9.0 ± 0.5*

TAP-TAP

DELAY (ns)

0.75 ± 0.4

1.0 ± 0.5

1.5 ± 0.7

2.0 ± 0.8

2.5 ± 1.0

4.0 ± 1.3

5.0 ± 1.5

10.0 ± 2.0

20.0 ± 4.0

50.0 ± 10

100 ± 20

700 ± 140

Rec’d Max

Frequency

28.4 MHz

23.8 MHz

18.0 MHz

14.5 MHz

12.1 MHz

8.33 MHz

6.67 MHz

3.33 MHz

1.67 MHz

0.67 MHz

0.33 MHz

0.05 MHz

Absolute Max

Rec’d Min

Pulse Width

17.6 ns

Absolute Min

Pulse Width

3.00 ns

Frequency

166.7 MHz

125.0 MHz

133.3 MHz

66.7 MHz

33.3 MHz

16.7 MHz

6.67 MHz

3.33 MHz

0.48 MHz

-.75

-1

-1.5

-2

-2.5

-4

-5

-10

-20

-50

-100

-700

21.0 ns

3.00 ns

27.8 ns

3.00 ns

13.5 ± 0.5*

18.0 ± 0.5*

22.5 ± 0.5*

36.0 ± 0.7*

50.0 ± 1.0

100.0 ± 2.0

200.0 ± 4.0

500.0 ± 10

1000 ± 20

7000 ± 140

34.5 ns

3.00 ns

41.2 ns

4.00 ns

60.0 ns

6.00 ns

75.0 ns

7.50 ns

150 ns

15.0 ns

300 ns

30.0 ns

750 ns

75.0 ns

1500 ns

10500 ns

150 ns

1050 ns

* Total delay referenced to Tap1 output; Input-to-Tap1 = 5.0ns ± 1.0ns

NOTE: Any dash number between .75 and 700 not shown is also available as standard.

2005 Data Delay Devices

Doc #03004

4/15/05

DATA DELAY DEVICES, INC.

3 Mt. Prospect Ave. Clifton, NJ 07013

3D7220

APPLICATION NOTES

To guarantee the Table 1 delay accuracy for

input frequencies higher than the Maximum

Operating Frequency, the 3D7220 must be

tested at the user operating frequency.

OPERATIONAL DESCRIPTION

The 3D7220 ten-tap delay line architecture is

shown in Figure 1. The delay line is composed of

a number of delay cells connected in series.

Each delay cell produces at its output a replica of

the signal present at its input, shifted in time. The

delay cells are matched and share the same

compensation signals, which minimizes tap-to-

tap delay deviations over temperature and supply

voltage variations.

Therefore, to facilitate production and device

identification, the part number will include a

custom reference designator identifying the

intended frequency of operation. The

programmed delay accuracy of the device is

guaranteed, therefore, only at the user specified

input frequency. Small input frequency variation

about the selected frequency will only marginally

impact the programmed delay accuracy, if at all.

Nevertheless, it is strongly recommended that

the engineering staff at DATA DELAY DEVICES

be consulted.

INPUT SIGNAL CHARACTERISTICS

The Frequency and/or Pulse Width (high or low)

of operation may adversely impact the specified

delay accuracy of the particular device. The

reasons for the dependency of the output delay

accuracy on the input signal characteristics are

varied and complex. Therefore a Maximum and

an Absolute Maximum operating input frequency

and a Minimum and an Absolute Minimum

operating pulse width have been specified.

OPERATING PULSE WIDTH

The Absolute Minimum Operating Pulse Width

(high or low) specification, tabulated in Table 1,

determines the smallest Pulse Width of the delay

line input signal that can be reproduced, shifted

in time at the device output, with acceptable

pulse width distortion.

OPERATING FREQUENCY

The Minimum Operating Pulse Width (high or

low) specification determines the smallest Pulse

Width of the delay line input signal for which the

output delay accuracy tabulated in Table 1 is

guaranteed.

The Absolute Maximum Operating Frequency

specification, tabulated in Table 1, determines

the highest frequency of the delay line input

signal that can be reproduced, shifted in time at

the device output, with acceptable duty cycle

distortion.

To guarantee the Table 1 delay accuracy for

input pulse width smaller than the Minimum

Operating Pulse Width, the 3D7220 must be

tested at the user operating pulse width.

Therefore, to facilitate production and device

identification, the part number will include a

The Maximum Operating Frequency specification

determines the highest frequency of the delay

line input signal for which the output delay

accuracy is guaranteed.

O10

10%

Temp & VDD

Compensation

VDD

GND

Figure 1: 3D7220 Functional Diagram

DATA DELAY DEVICES, INC.

Doc #03004

4/15/05

Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com

3D7220

APPLICATION NOTES (CONT’D)

custom reference designator identifying the

intended frequency and duty cycle of operation.

The programmed delay accuracy of the device is

guaranteed, therefore, only for the user specified

input characteristics. Small input pulse width

variation about the selected pulse width will only

marginally impact the programmed delay

accuracy, if at all. Nevertheless, it is strongly

recommended that the engineering staff at DATA

DELAY DEVICES be consulted.

circuitry to minimize the delay variations induced

by fluctuations in power supply and/or

temperature.

The thermal coefficient is reduced to 250 PPM/C,

which is equivalent to a variation, over the -40C

to 85C operating range, of ±2% from the room-

temperature delay settings and/or 1.0ns,

whichever is greater. The power supply

coefficient is reduced, over the 4.75V-5.25V

operating range, to ±1% of the delay settings at

the nominal 5.0VDC power supply and/or 1.0ns,

whichever is greater. It is essential that the

power supply pin be adequately bypassed

and filtered. In addition, the power bus

should be of as low an impedance

POWER SUPPLY AND

TEMPERATURE CONSIDERATIONS

The delay of CMOS integrated circuits is strongly

dependent on power supply and temperature.

The monolithic 3D7220 programmable delay line

utilizes novel and innovative compensation

construction as possible. Power planes are

preferred.

DEVICE SPECIFICATIONS

TABLE 2: ABSOLUTE MAXIMUM RATINGS

PARAMETER

DC Supply Voltage

Input Pin Voltage

Input Pin Current

Storage Temperature

Lead Temperature

SYMBOL

V_DD

MIN

-0.3

-1.0

-55

MAX

7.0

UNITS NOTES

V_IN

V_DD+0.3

1.0

I_IN

T_STRG

T_LEAD

25C

150

300

10 sec

TABLE 3: DC ELECTRICAL CHARACTERISTICS

(-40C to 85C, 4.75V to 5.25V)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Static Supply Current*

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

I_DD

V_IH

V_IL

I_IH

3.5

5.5

2.0

0.8

1.0

-4.0

V_IH= V_DD

V_IL= 0V

µA

I_IL

I_OH

µA

High Level Output

-35.0

15.0

2.0

V_DD= 4.75V

Current

_OH= 2.4V

Low Level Output Current

I_OL

4.0

V_DD= 4.75V

V_OL= 0.4V

C_LD= 5 pf

Output Rise & Fall Time

T_R& T_F

2.5

*I_DD(Dynamic) = 10 * C_LD* V_DD* F

Input Capacitance = 10 pf typical

Output Load Capacitance (C_LD) = 25 pf max

where: C_LD= Average capacitance load/tap (pf)

F = Input frequency (GHz)

Doc #03004

4/15/05

DATA DELAY DEVICES, INC.

3 Mt. Prospect Ave. Clifton, NJ 07013

3D7220

SILICON DELAY LINE AUTOMATED TESTING

TEST CONDITIONS

INPUT:

OUTPUT:

Ambient Temperature: 25^oC ± 3^oC

Supply Voltage (Vcc): 5.0V ± 0.1V

R_load

C_load

10KΩ ± 10%

5pf ± 10%

Input Pulse:

High = 3.0V ± 0.1V

Threshold: 1.5V (Rising & Falling)

Low = 0.0V ± 0.1V

50Ω Max.

Source Impedance:

Rise/Fall Time:

3.0 ns Max. (measured

between 0.6V and 2.4V )

PW_IN= 1.25 x Total Delay

PER_IN= 2.5 x Total Delay

Device

Digital

Scope

10KΩ

Under

Test

Pulse Width:

Period:

5pf

470Ω

NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.

PRINTER

COMPUTER

SYSTEM

OUT1

REF

OUT2

PULSE

OUT

DIGITAL SCOPE/

DEVICE UNDER

TEST (DUT)

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

OUT9

OUT10

GENERATOR

TIME INTERVAL COUNTER

TRIG

Figure 2: Test Setup

PER_IN

PW_IN

t_RISE

t_FALL

INPUT

V_IH

2.4V

1.5V

2.4V

1.5V

0.6V

SIGNAL

V_IL

0.6V

t_PLH

t_PHL

OUTPUT

SIGNAL

V_OH

1.5V

V_OL

Figure 3: Timing Diagram

Doc #03004

4/15/05

DATA DELAY DEVICES, INC.

Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com

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