DLO31F [DATADELAY]

TTL-INTERFACED, GATED DELAY LINE OSCILLATOR (SERIES DLO31F); TTL -接口，封闭式延迟线振荡器（系列DLO31F ）


型号：	DLO31F
厂家：	DATA DELAY DEVICES, INC.
描述：	TTL-INTERFACED, GATED DELAY LINE OSCILLATOR (SERIES DLO31F) TTL -接口，封闭式延迟线振荡器（系列DLO31F ）振荡器延迟线
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DLO31F

TTL-INTERFACED, GATED

DELAY LINE OSCILLATOR

(SERIES DLO31F)

data

delay

devices,

inc.

FEATURES

PACKAGES

VCC

N/C

GND

Continuous or keyable wave train

Synchronizes with arbitrary gating signal

Fits standard 14-pin DIP socket

Low profile

Auto-insertable

Input & outputs fully TTL interfaced & buffered

Available in frequencies from 2MHz to 40MHz

GND

DLO31F-xx

DIP

Military SMD

DLO31F-xxA2 Gull-Wing

DLO31F-xxB2 J-Lead

DLO31F-xxMD1

DLO31F-xxMD4

DLO31F-xxM Military DIP

FUNCTIONAL DESCRIPTION

PIN DESCRIPTIONS

The DLO31F-series device is a gated delay line oscillator. The device

produces a stable square wave which is synchronized with the falling edge

of the Gate Input (GB). The frequency of oscillation is given by the device

dash number (See Table). The two outputs (C1,C2) are in phase during

oscillation, but return to opposite logic levels when the device is disabled.

Gate Input

Clock Output 1

Clock Output 2

+5 Volts

VCC

GND Ground

SERIES SPECIFICATIONS

DASH NUMBER

SPECIFICATIONS

Frequency accuracy:

Inherent delay (T_E0):

Output skew:

Output rise/fall time:

Supply voltage:

Supply current:

Operating temperature: 0° to 70° C

Temperature coefficient: 100 PPM/°C (See text)

5.5ns typical

3.5ns typical

2ns typical

5VDC ± 5%

40ma typical (7ma when disabled)

Part

Number

Frequency

(MHz)

DLO31F-2

DLO31F-2.5

DLO31F-3

DLO31F-3.5

DLO31F-4

DLO31F-4.5

DLO31F-5

DLO31F-5.5

DLO31F-6

DLO31F-7

DLO31F-8

DLO31F-9

DLO31F-10

DLO31F-12

DLO31F-14

DLO31F-15

DLO31F-20

DLO31F-25

DLO31F-30

DLO31F-35

DLO31F-40

2.0 ± 0.04

2.5 ± 0.05

3.0 ± 0.06

3.5 ± 0.07

4.0 ± 0.08

4.5 ± 0.09

5.0 ± 0.10

5.5 ± 0.11

6.0 ± 0.12

7.0 ± 0.14

8.0 ± 0.16

9.0 ± 0.18

10 ± 0.20

12 ± 0.24

14 ± 0.28

15 ± 0.30

20 ± 0.40

25 ± 0.50

30 ± 0.60

35 ± 0.70

40 ± 0.80

GATE

(GB)

t_GR

t_EO

t_DO

CLOCK 1

(C1)

t_CS

1/f₀

CLOCK 2

(C2)

Figure 1: Timing Diagram

NOTE: Any dash number

between 2 and 40 not shown

is also available.

Ó1998 Data Delay Devices

Doc #98001

3/17/98

DATA DELAY DEVICES, INC.

3 Mt. Prospect Ave. Clifton, NJ 07013

DLO31F

APPLICATION NOTES

THERMAL STABILITY

POWER SUPPLY BYPASSING

The delay line used internally to develop the clock

signals in the DLO31F has a thermal coefficient

of 100ppm/C. For low frequency units, this is also

the thermal coefficient of the output frequency.

For higher frequency units, however, other

internal effects must be considered, and the

actual thermal coefficient may be somewhat

higher.

The DLO31F relies on a stable power supply to

produce a repeatable frequency within the stated

tolerances. A 0.1uf capacitor from VCC to GND,

located as close as possible to the VCC pin, is

recommended. A wide VCC trace and a clean

ground plane should be used.

DEVICE SPECIFICATIONS

TABLE 1: ABSOLUTE MAXIMUM RATINGS

PARAMETER

DC Supply Voltage

Input Pin Voltage

Storage Temperature

Lead Temperature

SYMBOL

V_CC

V_IN

T_STRG

T_LEAD

MIN

-0.3

-55

MAX

7.0

V_DD+0.3

150

UNITS NOTES

300

10 sec

TABLE 2: DC ELECTRICAL CHARACTERISTICS

(0C to 70C, 4.75V to 5.25V)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

High Level Output Voltage

V_OH

2.5

3.4

V_CC= MIN, I_OH= MAX

V_IH= MIN, V_IL= MAX

V_CC= MIN, I_OL= MAX

V_IH= MIN, V_IL= MAX

Low Level Output Voltage

V_OL

0.35

0.5

High Level Output Current

Low Level Output Current

High Level Input Voltage

Low Level Input Voltage

Input Clamp Voltage

Input Current at Maximum

Input Voltage

High Level Input Current

Low Level Input Current

Short-circuit Output Current

Output High Fan-out

I_OH

I_OL

V_IH

V_IL

V_IK

I_IHH

-1.0

20.0

2.0

-60

0.8

-1.2

0.1

V_CC= MIN, I_I= I_IK

V_CC= MAX, V_I= 7.0V

I_IH

I_IL

I_OS

-0.6

-150

V_CC= MAX, V_I= 2.7V

V_CC= MAX, V_I= 0.5V

V_CC= MAX

Unit

Load

Output Low Fan-out

12.5

TABLE 3: AC ELECTRICAL CHARACTERISTICS

(0C to 70C, 4.75V to 5.25V)

PARAMETER

SYMBOL MIN TYP MAX

UNITS

Enable to Clock On (Inherent Delay)

Disable to Clock Off

Clock Skew

t_EO

t_DO

t_CS

t_GR

3.5

2.5

5.5

3.5

7.0

4.5

Gate Recovery Time

% of Clock Period

Doc #98001

3/17/98

DATA DELAY DEVICES, INC.

Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com

DLO31F

PACKAGE DIMENSIONS

Lead Material:

Nickel-Iron alloy 42

TIN PLATE

.410

TYP.

.280

MAX.

.780 MAX.

.820 MAX.

.290

MAX.

.320

MAX.

.020

TYP.

.015 TYP.

.070 MAX.

.130

.010 .002

.030

.020 TYP.

.018

.200

TYP.

.018 TYP.

.600 TYP.

TYP.

.300

TYP.

.350

MAX.

.600 .010

DLO31F-xxM (Military DIP)

DLO31F-xx (Commercial DIP)

.020 TYP.

.040

TYP.

.010 TYP.

.040

TYP.

.020 TYP.

.050 TYP.

.320

TYP.

.270

TYP.

.430

TYP.

.270

TYP.

.090

.300

MAX.

.110

.200

.350

MAX.

.110

TYP.

.050

TYP.

.600

.790 MAX.

.600

.790 MAX.

DLO31F-xxA2 (Commercial Gull-Wing)

DLO31F-xxB2 (Commercial J-Lead)

.650

.100

.017

.510

MAX.

.510

MAX.

.300

TYP.

.300

TYP.

.050

.025

.050

.100

.080

.300

.510 MAX.

.300

.510 MAX.

.360 TYP.

.080

.200 MAX. (Com)

.225 MAX. (Mil)

.008

.200 MAX. (Com)

.225 MAX. (Mil)

.008

.045

.065

TYP.

.360

TYP.

.065

TYP.

.005

.065 TYP.

DLO31F-xxD1 (Commercial SMD)

DLO31F-xxMD1 (Military SMD)

DLO31F-xxD4 (Commercial SMD)

DLO31F-xxMD4 (Military SMD)

Doc #98001

3/17/98

DATA DELAY DEVICES, INC.

3 Mt. Prospect Ave. Clifton, NJ 07013

DLO31F

DELAY LINE AUTOMATED TESTING

TEST CONDITIONS

INPUT:

OUTPUT:

Ambient Temperature: 25^oC ± 3^oC

Supply Voltage (Vcc): 5.0V ± 0.1V

Load:

C_load

1 FAST-TTL Gate

5pf ± 10%

Input Pulse:

High = 3.0V ± 0.1V

Threshold: 1.5V (Rising & Falling)

Low = 0.0V ± 0.1V

Source Impedance:

Rise/Fall Time:

50W Max.

3.0 ns Max. (measured

between 0.6V and 2.4V )

PW_IN= 10 x Clock Period

PER_IN= 20 x Clock Period

Pulse Width Low:

Period:

NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.

FREQUENCY

COUNTER

OUT

PULSE

GENERATOR

DEVICE UNDER

TEST (DUT)

OSCILLOSCOPE

TRIG

Test Setup

PER_IN

PW_IN

T_FALL

T_RISE

2.4V

1.5V

0.6V

2.4V

1.5V

0.6V

INPUT

SIGNAL

V_IH

V_IL

T_EO

OUTPUT

SIGNAL

V_OH

1.5V

V_OL

Timing Diagram For Testing

Doc #98001

3/17/98

DATA DELAY DEVICES, INC.

Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com

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