PDU54-200M [DATADELAY]

4-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU54); 4位， ECL -接口可编程延迟线（系列PDU54 ）


型号：	PDU54-200M
厂家：	DATA DELAY DEVICES, INC.
描述：	4-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU54) 4位， ECL -接口可编程延迟线（系列PDU54 ）延迟线光电二极管
文件：	总4页 (文件大小：250K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PDU54



4-BIT, ECL-INTERFACED

PROGRAMMABLE DELAY LINE

(SERIES PDU54)

data

delay

devices, _inc.

FEATURES

PACKAGES

N/C

GND

N/C

GND

OUT

N/C

VEE

N/C

VEE

N/C

VEE

•

Digitally programmable in 16 delay steps

Monotonic delay-versus-address variation

Precise and stable delays

Input & outputs fully 100K-ECL interfaced & buffered

Available in 24-pin DIP (600 mil) socket or SMD

GND

N/C

GND

OUT

N/C

VEE

N/C

PDU54-xx DIP

PDU54-xxC4 SMD

PDU54-xxM Military DIP

PDU54-xxMC4 Mil SMD

FUNCTIONAL DESCRIPTION

PIN DESCRIPTIONS

The PDU54-series device is a 4-bit digitally programmable delay line. The

delay, TD_A, from the input pin (IN) to the output pin (OUT) depends on the

address code (A3-A0) according to the following formula:

Signal Input

OUT Signal Output

A3-A0 Address Bits

VEE -5 Volts

TD_A= TD₀+ T_INC* A

GND Ground

where A is the address code, T_INCis the incremental delay of the device, and TD₀is the inherent delay of

the device. The incremental delay is specified by the dash number of the device and can range from

100ps through 3000ps, inclusively. The address is not latched and must remain asserted during normal

operation.

SERIES SPECIFICATIONS

DASH NUMBER SPECIFICATIONS

•

Total programmed delay tolerance: 5% or 40ps,

Part

Incremental Delay

Per Step (ps)

100 ± 50

Total Delay

Change (ns)

1.50

whichever is greater

Number

PDU54-100

PDU54-200

PDU54-250

PDU54-400

PDU54-500

PDU54-750

PDU54-1000

PDU54-1200

PDU54-1500

PDU54-2000

PDU54-2500

PDU54-3000

•

Inherent delay (TD₀): 3.3ns typical

Address to input setup (T_AIS): 2.9ns

Operating temperature: 0° to 85° C

Temperature coefficient: 100PPM/°C (excludes TD₀)

Supply voltage V_EE: -5VDC ± 0.7V

Power Supply Current: -300ma typical (50Ω to -2V)

Minimum pulse width: 3ns or 10% of total delay,

whichever is greater

3.00

200 ± 60

3.75

250 ± 60

6.00

400 ± 80

7.50

500 ± 100

750 ± 100

11.25

15.00

1000 ± 200

1200 ± 200

1500 ± 200

2000 ± 400

2500 ± 400

3000 ± 500

18.00

22.50

30.00

•

Minimum period: 8ns or 2 x pulse width, whichever

is greater

37.50

45.00

A3-A0

A _i-1

A_i

NOTE: Any dash number between 100 and 3000

not shown is also available.

PW_IN

T_OAX

T_AIS

TD_A

PW_OUT

OUT

Figure 1: Timing Diagram

1997 Data Delay Devices

Doc #98004

3/18/98

DATA DELAY DEVICES, INC.

3 Mt. Prospect Ave. Clifton, NJ 07013

PDU54

APPLICATION NOTES

conditions are those for which the delay

ADDRESS UPDATE

tolerance specifications and monotonicity are

guaranteed. The suggested conditions are

those for which signals will propagate through the

unit without significant distortion. The absolute

conditions are those for which the unit will

produce some type of output for a given input.

The PDU54 is a memory device. As such,

special precautions must be taken when

changing the delay address in order to prevent

spurious output signals. The timing restrictions

are shown in Figure 1.

When operating the unit between the

After the last signal edge to be delayed has

appeared on the OUT pin, a minimum time, T_OAX

is required before the address lines can change.

This time is given by the following relation:

recommended and absolute conditions, the

delays may deviate from their values at low

frequency. However, these deviations will

remain constant from pulse to pulse if the input

pulse width and period remain fixed. In other

words, the delay of the unit exhibits frequency

and pulse width dependence when operated

beyond the recommended conditions. Please

consult the technical staff at Data Delay Devices

if your application has specific high-frequency

requirements.

T_OAX= max { (A_i- A _i-1) * T_INC, 0 }

where A _i-1and A_iare the old and new address

codes, respectively. Violation of this constraint

may, depending on the history of the input signal,

cause spurious signals to appear on the OUT

pin. The possibility of spurious signals persists

until the required T_OAXhas elapsed.

Please note that the increment tolerances listed

represent a design goal. Although most delay

increments will fall within tolerance, they are not

guaranteed throughout the address range of the

unit. Monotonicity is, however, guaranteed over

all addresses.

INPUT RESTRICTIONS

There are three types of restrictions on input

pulse width and period listed in the AC

Characteristics table. The recommended

PACKAGE DIMENSIONS

24 23 22 21 20 19 18 17 16 15 14 13

.600

.580

MAX.

.005

.010

.002

9 10 11 12

1.270 .010

Lead Material:

Nickel-Iron alloy 42

.380

TIN PLATE

MAX.

.015 TYP.

.070 MAX.

.018 TYP.

1.100 .010

11 Equal spaces

each .100 .010

Non-Accumulative

PDU54-xx (Commercial DIP)

PDU54-xxM (Military DIP)

Doc #98004

3/18/98

DATA DELAY DEVICES, INC.

Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com

PDU54

PACKAGE DIMENSIONS (cont’d)

.020 TYP.

.040 TYP.

.010±.002

24 23 22 21 20 19 18 17 16 15 14 13

.882

.710 .590

MAX.

±.00

.007

±.00

10 11 12

.100

.090

.380

.050

±.01

MAX.

1.100

1.280±.020

PDU54-xxC4 (Commercial SMD)

PDU54-xxMC4 (Military SMD)

DEVICE SPECIFICATIONS

TABLE 1: AC CHARACTERISTICS

PARAMETER

SYMBOL

TD_T

MIN

TYP

3.3

UNITS

T_INC

Total Programmable Delay

Inherent Delay

TD₀

Address to Input Setup Time

Output to Address Change

T_AIS

T_OAX

2.9

See Text

Absolute

PER_IN

PW_IN

% of TD_T

Input Period

Suggested

Recommended

Absolute

200

Input Pulse Width

Suggested

Recommended

100

TABLE 2: ABSOLUTE MAXIMUM RATINGS

PARAMETER

DC Supply Voltage

Input Pin Voltage

Storage Temperature

Lead Temperature

SYMBOL

V_EE

MIN

-7.0

V_EE- 0.3

-65

MAX

0.3

UNITS NOTES

V_IN

0.3

T_STRG

T_LEAD

150

300

10 sec

TABLE 3: DC ELECTRICAL CHARACTERISTICS

(0C to 85C)

PARAMETER

SYMBOL

MIN

MAX

UNITS

NOTES

High Level Output Voltage

Low Level Output Voltage

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

V_OH

V_OL

V_IH

V_IL

I_IH

-1.025 -0.880

-1.810 -1.620

-1.165 -0.880

-1.810 -1.475

340

V_IH= MAX,50Ω to -2V

V_IL= MIN, 50Ω to -2V

µA

V_IH= MAX

V_IL= MIN

I_IL

0.5

Doc #98004

3/18/98

DATA DELAY DEVICES, INC.

3 Mt. Prospect Ave. Clifton, NJ 07013

PDU54

DELAY LINE AUTOMATED TESTING

TEST CONDITIONS

INPUT:

OUTPUT:

Ambient Temperature: 25^oC ± 3^oC

Supply Voltage (Vcc): -4.5V ± 0.1V

Load:

50Ω to -2V

5pf ± 10%

C_load

Input Pulse:

Standard 100K ECL

Threshold: (V_OH+ V_OL) / 2

levels

50Ω Max.

(Rising & Falling)

Source Impedance:

Rise/Fall Time:

1.0 ns Max. (measured

between 20% and 80%)

PW_IN= 10ns

Pulse Width:

Period:

PER_IN= 100ns

NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.

REF

PULSE

OUT

DEVICE UNDER

TEST (DUT)

OSCILLOSCOPE

GENERATOR

TRIG

ADDRESS SELECT

Test Setup

PER_IN

PW_IN

T_RISE

T_FALL

INPUT

V_IH

80%

50%

80%

50%

20%

SIGNAL

V_IL

20%

T_RISE

T_FALL

OUTPUT

SIGNAL

V_OH

50%

V_OL

Timing Diagram For Testing

Doc #98004

3/18/98

DATA DELAY DEVICES, INC.

Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com

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