DEI1046 [DEIAZ]

OCTAL ARINC 429 LINE RECEIVER;


型号：	DEI1046
厂家：	Device Engineering Incorporated
描述：	OCTAL ARINC 429 LINE RECEIVER
文件：	总8页 (文件大小：413K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Device

Engineering

Incorporated

DEI1046

OCTAL ARINC 429 LINE

RECEIVER

385 East Alamo Drive

Chandler, AZ 85225

Phone: (480) 303-0822

Fax: (480) 303-0824

E-mail: admin@deiaz.com

NOT FOR NEW DESIGNS

REPLACED BY DEI1046A

FEATURES

Octal ARINC 429 to TTL/CMOS logic line receivers

Drop-in replacement for HI-8456PS_

Operates from single +5 V ± 10% or 3.3 V + 10% -5% power supply

ARINC inputs internally protected to lightning requirements of DO-160 Level 3 pin injection

Withstands inadvertent short to 115 Vac on inputs

Operates in high noise environment

Input Common Voltage Range: ± 20 V

2 V minimum Input hysteresis

High input resistance allows use of external series resistors to support:

Lightning protection beyond Level 3

Fault isolation

Package: 38L TSSOP, 4.4 mm body

DEI1046 PINOUT

Table 1 DEI1046 Pin Description

NAME

DESCRIPTION

15, 13, 11, 9,

7, 5, 3, 1

429 INPUTS. ARINC 429 format serial

digital data “A” inputs.

IN[8:1]A

16, 14, 12, 10,

8, 6, 4, 2

429 INPUTS. ARINC 429 format serial

digital data “B” inputs.

IN[8:1]B

Not connected.

TESTA

TESTB

LOGIC INPUT, Test input A

LOGIC INPUT, Test input B

21, 23, 25, 27,

32, 34, 36, 38

LOGIC OUTPUTS. CMOS/TTL format

serial digital data “A” outputs.

OUT[8:1]A

OUT[8:1]B

20, 22, 24, 26,

31, 33, 35, 37

LOGIC OUTPUTS. CMOS/TTL format

serial digital data “B” outputs.

VDD

VSS

POWER INPUT. 5 V or 3.3 V.

POWER INPUT. Ground.

28, 30

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FUNCTIONAL DESCRIPTION

The DEI1046 is a BiCMOS device which contains eight differential line receivers. Each receiver channel translates

incoming ARINC 429 data bus signals (tri-level RZ bipolar differential modulation) to a pair of TTL/CMOS logic

outputs. Each channel operates independently and meets the requirements of the ARINC 429 Digital Information

Transfer Standard. Refer to Figure 1 DEI1046 Block Diagram and Truth Table.

The device is designed to operate in a high noise environment. Inputs are accepted over a ±20 V common mode

voltage range and the receivers provide over 2 V of hysteresis. Circuit speed is optimized to reject high frequency

transients.

The DEI1046 device provides logic level TEST inputs for built in system test. They force the outputs of all eight

receivers to the specified ZERO, ONE or NULL state. The ARINC inputs are ignored when the device is in test mode.

The DEI1046 has a single test port which controls all 8 channels.

The ARINC input pins are designed with internal protection from damage due to lighting induced transients of DO-

160 Level 3 pin injection. The protection incorporates on-chip high value resistors to minimize IR heating and high-

voltage dielectric isolation to withstand the voltage transients.

Higher protection levels can be achieved with the addition of external TVS devices between the inputs and ground,

or alternately, TVS devices in combination with series current limiting resistors between the ARINC bus and the

IC/TVS node. The series resistors reduce the power requirement and size of the TVS. Resistor values up to 10 kΩ

are feasible.

The ARINC inputs withstand inadvertent short to 115 Vac aircraft power without sustaining damage.

Figure 1 DEI1046 Block Diagram and Truth Table

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ELECTRICAL DESCRIPTION

Table 2: Absolute Maximum Rating

PARAMETER

Supply Voltage (with respect to VSS)

MIN

-0.3

-65

MAX

7.0

UNIT

Storage Temperature

+150

115

800

145

260

°C

Input Voltage, continuous (ARINC Inputs)

Power Dissipation @ 85 °C

Vac

°C

Junction Temperature, Tjmax (limited by molding compound Tg)

Peak Body Temperature

°C

Lightning Protection (ARINC 429 Channel Inputs)

Waveform 3 (2)

Waveform 4, 5A (2) (3)

-720

-360

+720

+360

ESD JS-001-2017 HBM

Class

Notes:

1. Stresses above these limits can cause permanent damage.

2. Per DO160, Sect 22 Level 3 pin injection. See Figures 4 - 6.

3. Inputs can be protected to withstand higher stress by adding series resistors and shunt TVS on inputs. Inputs

withstand 1500 V Waveform 5A when clipped ≤ 600 V.

Table 3: Recommended Operating Conditions

SYMBOL

VDD

CONDITIONS

PARAMETER

Supply Voltage

Logic Input Levels

+5 V ±10%

+3.3 V +10% -5%

TESTA/B

0 to VDD

Operating Temperature

-TES

-TMS

-55 to +85 °C

-55 to +125 °C

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Table 4: Electrical Characteristics

Conditions: Temperature: -55 °C to +85 °C (-TES); -55 °C to +125 °C (-TMS)

VDD = +5 V ±10% and +3.3 V +10% -5%

PARAMETER

TEST CONDITION

ARINC INPUTS

SYMBOL

MIN

MAX

UNIT

V_A– V_B= Logic +1

V_A– V_B= Logic -1

OUTA = 1

OUTB = 1

V₊₁

V_-1

6.5

-6.5

-13

OUTA = 0

OUTB = 0

V_A– V_B= Logic Null

V_NULL

V_HY

-2.5

2.0

-20

2.5

4.0

+20

Input Hysteresis

Input Common Mode

Voltage Range

Logic +1, Null, Logic -1

V_CM

VDD open,

Shorted to VSS or +5 V

(1)

Input Resistance

IN_Ato IN_B

R_IN

280

140

kΩ

Input Resistance

IN_Aor IN_Bto V_SS

VDD open,

Shorted to VSS or +5 V

R_S

C_IN

C_S

kΩ

Input Capacitance

IN_Ato IN_B

VDD open,

Shorted to VSS or +5 V (1)

Input Capacitance

IN_Aor IN_Bto V_SS

VDD open,

Shorted to VSS or +5 V (1)

LOGIC INPUTS

Logic 0 Voltage

Logic 1 Voltage

Logic 0 Current

Logic 1 Current

V_IL

V_IH

I_IL

0.8

2.0

2.4

V_IL= 0.8

µA

V_IH= 2.0

I_IH

LOGIC OUTPUTS

_OH= -5mA (VDD = 5.0 V)

_OH= -5mA (VDD = 3.3 V)

TTL Compatible

OUTPUT HIGH VOLTAGE

TTL

V_OH

V_OL

OUTPUT LOW VOLTAGE

TTL

I_OL= 5 mA (VDD = 5.0 V)

0.4

.05

8.5

OUTPUT HIGH VOLTAGE

CMOS

I_OH= 100 µA

CMOS Compatible

VDD

–.05

V_OH

V_OL

OUTPUT LOW VOLTAGE

CMOS

I_OL= 100 µA

CMOS Compatible

SUPPLY CURRENT

Data Rate = 0 MHZ,

INA/B = open,

OUTA/B = open,

VDDCurrent

I_DD

1.5

VDD = 5.5 V or 3.63 V

Notes:

1. Guaranteed by design, not production tested.

2. Current flowing into device is positive. Current flowing out of device is negative. All

voltages are with respect to VSS unless otherwise noted.

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Table 5: Switching Characteristics

MAX

VDD 3.3V

MAX

VDD 5V

PARAMETER

TEST CONDITION (1,2) SYMBOL

UNIT

TESTA = TESTB = 0

C_L= 50 pF

INA/B to OUTA/B Prop Delay

t_LH

t_HL

1000

900

TESTA = TESTB = 0

C_L= 50 pF

1000

OUTA/B rise time

OUTA/B fall time

10% to 90%, C_L= 50 pF

t_r

t_f

TESTA/B to OUTA/B Prop

delay

C_L= 50 pF

t_TOH

t_TOL

100

TESTA/B to OUTA/B Prop

delay

Notes:

1. Sample tested.

2. Refer to Figures 2 – 3.

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INA

TESTA OR B

1.5V

Vdif = 6.5V

Vdif = 2.5V

t_TOH

t_TOL

INB

t_HL

t_LH

OUTA OR B

1.5V

OUTA

OUTB

1.5V

Figure 3 TEST Input to Logic Output Switching

Waveform

Figure 2 ARINC 429 Input to Logic Output Switching

Waveform

V/I

Peak

Largest

Peak

25% to 75%

of Largest Peak

T1 = 6.4 µs +-20%

T2 = 70 µs +-20%

50%

Figure 4 DO160 Lightning Induced Transient Voltage

Waveform #4 Pin Injection

Figure 5 DO160 Lightning Induced Transient Voltage

Waveform #3 Pin Injection

Voc = 300 V, Isc = 60 A

Voc = 600 V, Isc = 24 A. Freq = 1 MHZ ±20%

V/I

5A: T1 = 40 us +-20%

Peak

T2 = 120 us +-20%

LIGHTNING TRANSIENT NOTES:

1. Voc = Peak Open Circuit Voltage available at

the calibration point.

2. Isc = Peak Short Circuit Current available at

the calibration point.

50%

3. Amplitude tolerances: +10%, -0%.

4. The ratio of Voc to Isc is the generator

source impedance to be used for generating

the waveforms.

Figure 6 DO160 Lightning Induced Transient Voltage

Waveform #5 Pin Injection

Voc = 300 V, Isc = 300 A

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ORDERING INFORMATION

Table 6: Ordering Information

TEMPERATURE

DEI PN

MARKING (1)

TEST INPUTS

PACKAGE

38L TSSOP G

SCREENING

Standard

RANGE

DEI1046-TES

(e4)

DEI1046-TES-G

DEI1046-TMS-G

YES

-55/+85 °C

DEI1046-TMS

(e4)

-55/+125 °C

Standard

Notes:

1. All packages marked with Lot Code and Date Code. (e4) after Date Code denotes Pb Free category.

Table 7: Screening Process

SCREENING

ELECTRICAL TEST:

STANDARD

ROOM TEMPERATURE

HIGH TEMPERATURE

LOW TEMPERATURE

100%

100% @ 85 °C or 125 °C

0.65% AQL @ -55 °C

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PACKAGE DESCRIPTION

Table 8: Package Characteristics

CHARACTERISTIC

VALUE

38L

TSSOP G

REFERENCE

75 °C/W

15 °C/W

Q_JA

(4 layer PCB with Power Planes)

Q_JC

JEDEC MOISTURE

SENSITIVITY LEVEL (MSL)

MSL 2 / 260 °C

LEAD FINISH MATERIAL /

JEDEC Pb-free CODE

NiPdAu

Pb-Free DESIGNATION

JEDEC REFERENCE

RoHS Compliant

MO-153-BD-1

Figure 7 38L TSSOP Mechanical Outline

DEI reserves the right to make changes to any products or specifications herein. DEI makes no warranty, representation, or

guarantee regarding suitability of its products for any particular purpose.

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