DEI1066 [DEIAZ]
OCTAL GND/OPEN INPUT, SERIAL OUTPUT INTERFACE IC;
| 型号： | DEI1066 |
| 厂家： | 
Device Engineering Incorporated |
| 描述： | OCTAL GND/OPEN INPUT, SERIAL OUTPUT INTERFACE IC 输入元件 输出元件 |
| 文件： | 总11页 (文件大小：287K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Device
Engineering
Incorporated
DEI1066
OCTAL GND/OPEN INPUT, SERIAL
OUTPUT INTERFACE IC
385 East Alamo Drive
Chandler, AZ 85225
Phone: (480) 303-0822
Fax: (480) 303-0824
E-mail: admin@deiaz.com
FEATURES
·
Eight GND/OPEN discrete inputs
o
o
o
o
o
Meet electrical requirements for ABD0100F GND/OPEN discrete input.
Hysteresis provides noise immunity
Internal pull up resistor with 1mA source current to prevent dry relay contacts.
Internal isolation diode
Inputs protected from Lightning Induced Transients per DO160D, Section 22, Cat A3 and B3.
·
3-wire serial interface (/CS, CLK, DO)
o
o
o
o
Direct interface to Serial Peripheral Interface (SPI) port.
TTL/CMOS compatible inputs and Tristate output
10MHz Data Rate
Serial input to expand Shift Register
·
·
·
Logic Supply Voltage (VCC):
Analog Supply Voltage (VDD):
16L NB SOIC package
3.3V or 5V
5V to 18V
PIN ASSIGNMENTS
1
16
VDD
GND
VCC
GND
SDIN
/CS
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
DEI1066
SCLK
DOUT
Figure 1 DEI1066 Pin Assignment
©2018 Device Engineering, Inc.
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GENERAL DESCRIPTION
The DEI1066 is an eight-channel discrete-to digital interface BICMOS device. It senses eight Ground/Open discrete signals of
the type commonly found in avionic systems. The data is read from the device via an eight-bit serial shift register with 3-state
output implemented as a Serial Peripheral Interface (SPI) bus, Mode 0 slave.
Table 1 Pin Descriptions
Pins
Name
Description
8-1
DIN[8:1]
Parallel data inputs. Eight Ground/Open format discrete signals. These
have an internal pull-up to VDD. The logic threshold and hysteresis
characteristics are determined by the applied VDD voltage.
Serial data output. This pin is the output from the last stage of the shift
register. This is a 3-state output.
Serial Shift Clock. A low-to-high transition on this input shifts data on
the serial data input into the shift register and data in stage 8 is shifted out
DOUT, being replaced by the data previously stored in stage 7.
Chip Select. A high-to-low transition on this input loads data from the
parallel DIN[8:1] inputs into the shift register. A low level on this input
enables the DOUT 3-state output and the shift register. A high level on
this input forces DOUT to the high impedance state and disables the shift
register so SCLK transitions have no effect.
9
DOUT
SCLK
10
11
12
/CS
SDIN
Serial Data Input. Data on this input is shifted into the shift register on
the rising edge of the SCLK input if the /CS input is low. This input has
an internal pull-down resistor to GND.
13
14
15
16
GND
VCC
GND
VDD
Logic Ground.
Logic Supply Voltage.
Analog Ground.
Analog Supply Voltage.
SDIN
SDIN
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
INPUT RESISTORS,
COMPARATORS,
FILTERING, AND
LIGHTNING
PROTECTION
(8 CHANNELS)
Q8
DOUT
SHIFT REG
SCK
SCLK
/CS
SH/LD
Figure 2 DEI1066 LOGIC DIAGRAM
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DIN[8:1] Inputs
Each discrete input consists of the circuit shown in Figure 3. Each DINn signal is conditioned by the resistor / diode network
and presented to the comparator IN+. The comparator IN-, and therefore the switching threshold, is developed from the Vdd
supply voltage. It includes positive feedback from the comparator output to provide hysteresis. Some notable features are:
·
The comparator includes an RC filter to provide noise rejection of transient pulses of up to several us. Thus, there is a
relatively large DINx setup time. (Refer to timing parameter tsu2).
·
The inputs can withstand continuous input voltages of 40V minimum. The isolation diode breakdown voltage is
greater than 50V. The 12K Ohm input resistor is designed to limit diode breakdown current to safe levels during
transient events.
Vdd
Comparator
Vdd
with RC filter
R2
3K
R1
12K
D1
+
-
DINn
Vout
(to Shift
Reg)
Vdd
R3
500
R4
50K
Figure 3 DINn Input Circuit
Q1
R5
80K
Table 2 Truth Table
/CS
1
↓
SCLK
X
X
SDIN
X
X
DIN[8:1]
SREG Q1
X
DIN1
DOUT
HI-Z
Enabled
DIN8
X
Sampled into Shift
Register
0
0
0
↑
↑
↑
↓
0
1
X
X
X
X
X
X
0
1
SREG Q8
SREG Q8
No Change
No Change
No Change
X
Disabled to HI-Z
©2018 Device Engineering, Inc.
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Serial Interface and Shift Register
The DEI1066 digital interface is an 8-Bit Serial or Parallel-Input / Serial-Output Shift Register with 3-State Output. The
control inputs to the shift register are connected as shown in Figure 2 to implement an SPI compatible bus consisting of /CS,
SCLK, DOUT, and SDIN. The Figure 4 waveform depicts a typical 8-Bit read cycle where the 8 DIN signals are read on to
the serial bus. The Figure 5 waveform demonstrates a daisy-chain application where a 16-Bit read cycle includes the serial
data passed through from the SDIN input.
/CS
X
SCLK
X
VALID
X
X
DIN[8:1]
X
X
SDIN
DIN8
DIN7
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
DOUT
DIN inputs latched in S-Reg
Figure 4 Serial Bus Read Cycle, 8 Bit
/CS
SCLK
X
X
VALID
X
X
DIN[8:1]
SI8
SI7
SI6
SI5
SI4
SI3
SI2
SI1
X
X
SDIN
DIN8
DIN7
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
SI8
SI7
SI6
SI5
SI4
SI3
SI2
SI1
DOUT
Figure 5 Serial Bus Read Cycle, 16 Bit Daisy Chain
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Lightning Protection
DINn inputs are designed to survive lightning induced transients as defined by RTCA DO160D, Section 22, Cat A3 and B3,
Waveforms 3, 4, and 5A, Level 3. See waveforms below.
V
V/I
Peak
25% to 75%
of Largest Peak
T1 = 6.4us
T2 = 70us
50%
0
t
50%
F = 1MHZ and 10MHZ
0
t
T1
T2
Figure 6 Voltage / Current Waveform 3
Figure 7 Current / Voltage Waveform 4
V/I
Peak
T1=40us
T2=120us
Waveform Source Impedance characteristics:
·
·
·
Waveform 3 Voc/Isc = 600V / 24A => 25 Ohms
Waveform 4 Voc/Isc = 300 V / 60 A => 5 Ohms
Waveform 5A Voc / Isc = 300V / 300A => 1 Ohm
50%
0
t
T1
T2
Figure 8 Current / Voltage Waveform 5A
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ELECTRICAL CHARACTERISTICS
Table 3 Absolute Maximum Ratings
PARAMETER
MIN
-0.3
-0.3
MAX
+7.0
20
UNITS
VCC Supply Voltage
VDD Supply Voltage
V
V
Input Voltage
DIN[8:1]
Continuous
DO160D, Waveform 3, Level 3
DO160D, Waveform 4 and 5, Level 3
-5
+40
+600
+300
V
V
V
V
V
-600
-300
-1.5
-0.5
Logic Inputs
DOUT
VCC + 1.5
VCC + 0.5
Power Dissipation @ 85 °C: (> 10 Sec)
16 Lead SOIC
0.8
W
Operating Temperature
-55
-65
+125
°C
+150
°C
°C
Storage Temperature
Junction Temperature
Tjmax
145
ESD per JEDEC A114-A Human Body Model
Logic and Supply pins
DIN pins
2000
1000
V
Notes:
1. Stresses above absolute maximum ratings may cause permanent damage to the device.
2. Voltages referenced to Ground
Table 4 Recommended Operating Conditions
PARAMETER
Supply Voltage
SYMBOL
CONDITIONS
VCC
VDD
5.0V±10%, 3.3V±10%
5.0 to 18V
Logic Inputs and Outputs
Discrete Inputs
0 to VCC
DIN[8:1]
Top
0 to 40V
Operating Temperature
-SES
-SMx
-55 to +85 ºC
-55 to +125 ºC
©2018 Device Engineering, Inc.
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Table 5 DC Characteristics
Symbol
Parameter
Conditions (1) (2)
LIMITS
Max
Unit
Min
LOGIC INPUTS AND OUTPUTS
VIH
VIL
HI level input voltage
LO level input voltage
2.0
V
0.8
V
VIhst
Input hysteresis voltage,
SCLK input
(3)
50
mV
VOH
HI level output voltage
Iout = -20uA
VCC – 0.1
V
Iout = -4.5mA,
3.2
3.0
V
V
-55°C to +85°C
-55°C to +125°C
Iout = 20uA
VOL
LO level output voltage
0.1
Iout = 4.5mA,
-55°C to +85°C
-55°C to +125°C
Vin = VCC or GND
0.33
0.4
V
IIN
Input leakage
Logic inputs except SDIN:
-55°C to +85°C
-55°C to +125°C
-1
-2
-2
1
2
750
uA
uA
SDIN:
IOZ
Max 3-state leakage current, Output in Hi Impedance state.
DOUT
Vout = VCC or GND
-5
-10
5
10
-55°C to +85°C
-55°C to +125°C
Cin
Logic input pin Capacitance (3)
10
15
pF
pF
Cout
DOUT pin capacitance,
output in HI-Z state
(3)
DISCRETE INPUTS
VIH
VIL
VIhst
IIH
HI level input voltage
LO level input voltage
Input hysteresis voltage
HI level input current
VDD = 18V
VDD = 5.0V
VDD = 18V
VDD = 5.0V
VDD = 18V
16.9
4.16
V
V
V
16.0
3.7
0.59
0.18
VDD = 5.0V
DINn = 18V
5
10
-55°C to +85°C
-55°C to +125°C
DINn = 40V
uA
20
40
-55°C to +85°C
-55°C to +125°C
DINn = 0V
IIL
LO level input current
VDD = 18V
VDD = 5.0V
SUPPLY VOLTAGES
-1.0
-0.25
-1.6
-0.5
mA
uA
ICC
Max quiescent logic supply Logic inputs = VCC or GND
current DIN[8:1] = Open
-55°C to +85°C
-55°C to +125°C
200
400
©2018 Device Engineering, Inc.
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Symbol
Parameter
Conditions (1) (2)
LIMITS
Min Max
Unit
IDD
Max quiescent analog
supply current
Logic Inputs = VCC or GND
DIN[8:1] = Open
11
DIN[8:1] = GND
mA
23
24
-55°C to +85°C
-55°C to +125°C
Notes:
1. Unless otherwise noted, Ta = rated temperature range. VCC = 3.0 to 5.5V. VDD = 5.0 to 18V.
2. Current flowing into device is positive. Current flowing out of device is negative. Voltages are
referenced to Ground.
3. By design, not tested.
Table 6 AC Electrical Characteristics
Symbol
Parameter
Conditions
(5)
Limits
Unit
Min
Max
fMAX
SCLK frequency. (50% duty cycle) (4)
VCC = 3.0V
VCC = 4.5V
4.8
24
MHz
Maximum usable SCLK frequency =
1/(tp2 + tsu3)
SCLK pulse width. (50% duty cycle)
VCC = 3.0V
VCC = 4.5V
VCC = 3.0V
VCC = 4.5V
VCC = 3.0V
VCC = 4.5V
VCC = 3.0V
VCC = 4.5V
2.8
10.7
tW
tsu1
th1
100
20
100
50
20
20
1
ns
ns
ns
Setup time, SCLK low to /CS↓.
Hold time, /CS↓ to SCLK↑.
tsu2
th2
tsu3
Setup time, DIN valid to /CS↓.
Hold time, /CS↓ to DIN not valid.
Setup time, SDIN valid to SCLK↑.
(6)
(6)
35
us
us
ns
-1
VCC = 3.0V
VCC = 4.5V
VCC = 3.0V
VCC = 4.5V
75
20
5
th3
tp1
tp2
tp3
tp4
Hold time, SCLK↑ to SDIN not valid.
ns
ns
ns
ns
ns
5
Propagation delay, /CS↓ to DOUT valid. VCC = 3.0V
250
70
250
100
200
80
(1)
VCC = 4.5V
VCC = 3.0V
VCC = 4.5V
Propagation delay, SCLK↑ to DOUT
valid. (1)
Propagation delay, /CS↑ to DOUT HI-Z. VCC = 3.0V
(1) (2) (3)
Delay time between /CS active.
VCC = 4.5V
VCC = 3.0V
VCC = 4.5V
25
25
Notes:
1. DOUT loaded with 50pF to GND.
2. DOUT loaded with 1K Ohms to GND for Hi output, 1K Ohms to VCC for Low output.
3. Timing measured at 25%VCC for “0” to Hi-Z, 75%VCC for “1” to Hi-Z.
4. By design, not tested
5. Unless otherwise noted: Ta = rated temperature range. VCC = 3.0 to 5.5V. VDD = 5V. VIL = 0V. VIH = VCC.
Timing measurement cursers at 50%VCC.
6. tsu2 represents the maximum possible propagation delay through the input comparator. th2 represents the minimum
possible propagation delay through the input comparator. The negative hold time denotes that DIN may change prior
to /CS↓ and still be valid data at the Shift Reg.
©2018 Device Engineering, Inc.
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/CS
SCLK
tp4
th1
tW
tsu1
1/fmax
tsu2
th2
valid
X
X
DIN[8:1]
tsu3
th3
X
X
valid
SDIN
tp2
tp1
tp3
DIN8
DIN7
DOUT
Figure 9 Switching Waveforms
DESIGN INFORMATION
©2018 Device Engineering, Inc.
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PACKAGE DESCRIPTION
16L Narrow Body SOIC -G Package
Table 7 Package Information
16 Lead SOIC
PACKAGE TYPE
Narrow Body,
Green
REFERENCE
16L SOIC NB G
THERMAL RESISTANCE:
qJA
(4 layer PCB with
Power Planes)
~74 °C/W
~30 °C/W
qJC
JEDEC MOISTURE
SENSITIVITY LEVEL (MSL)
MSL 1 / 260°C
LEAD FINISH MATERIAL /
JEDEC Pb-free CODE
NiPdAu
e4
Pb-Free DESIGNATION
JEDEC REFERENCE
RoHS Compliant
MS-012-AC
Figure 10 Mechanical Outline, 16L SOIC NB G
©2018 Device Engineering, Inc.
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ORDERING INFORMATION
Table 8
Package
Part Number
Marking
Burn In
Temperature
DEI1066-SES-G
DEI1066-SES
16 SOIC NB G
No
-55 / +85 ºC
E4
DEI1066-SMS
E4
DEI1066-SMB
E4
DEI1066-SMS-G
DEI1066-SMB-G
16 SOIC NB G
16 SOIC NB G
No
-55 / +125 ºC
-55 / +125 ºC
96hr / +125 ºC
DEI reserves the right to make changes to any products or specifications herein. DEI makes no warranty, representation, or
guarantee regarding suitability of its products for any particular purpose.
©2018 Device Engineering, Inc.
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