DEI1084-MES-G_技术文档

Device

Engineering

Incorporated

DEI1084/1085

ARINC 429 ENHANCED

TRANSCEIVER

385 East Alamo Drive

Chandler, AZ 85225

Phone: (480) 303-0822

Fax: (480) 303-0824

E-mail: admin@deiaz.com

GENERAL DESCRIPTION

FEATURES

The DEI1084 is a CMOS ARINC 429 Transceiver IC. It

is pin compatible with the Holt HI-3584 and HI-8584

products.

x

ARINC specification 429 compatible

3.3V/5.5V supply operation

Dual receiver and single transmitter interface

32nd transmit bit can be data or parity

Self test mode

Pin compatible with HI3584 & HI8584

Programmable label recognition

On-chip 16 label memory for each receiver

32 x 32 FIFO for transmitter and each receiver

Independent data rate selection for transmitter and

each receiver

Status register

Data scramble control

Package Options: 52L QFP, 52L CQFJ, & 64L

MLPQ

The DEI2084/85-Mxx versions are alternate package pin-

outs of the DEI1084/85-Mxx to provide access to the

/TXSEL output in the MLPQ package.

The enhancements relative to the DEI1016 transceiver

include: 32x32 bit FIFO for transmitter, 32x32 bit FIFO

for each receiver, a status register, label recognition

capability, bit timing feature and choice of scrambled or

unscrambled ARINC data output.

x

The DEI1085 version requires external serial 10KOhm

resistors on the receiver inputs. This simplifies the

implementation of external lightning protection networks.

The DEI1084 version has on-chip 10KOhm resistors and

do not require external resistors on the inputs.

ORDERING INFORMATION

Part Number

DEI1084-QES-G

DEI1084-QMS-G

DEI1084-MES-G

DEI1084-UMS

DEI1085-QES-G

DEI1085-QMS-G

DEI1085-MES-G

DEI1085-UMS

DEI2084-MES-G

DEI2085-MES-G

DEI2084-MMS-G

DEI2085-MMS-G

Marking

Package

Burn In

No

10K Resistors

internal

external

internal

external

internal

external

Temperature

-55 / +85 ºC

-55 / +125 ºC

-55 / +85 ºC

-55 / +125 ºC

-55 / +85 ºC

-55 / +125 ºC

-55 / +85 ºC

-55 / +125 ºC

-55 / +85 ºC

-55 / +125 ºC

DEI1084-QES

DEI1084-QMS

DEI1084-MES

DEI1084-UMS

DEI1085-QES

DEI1085-QMS

DEI1085-MES

DEI1085-UMS

DEI2084-MES

DEI2085-MES

DEI2084-MMS

DEI2085-MMS

52L MQFP G

64L MLPQ G

52L CQFJ

52L MQFP G

64L MLPQ G

52L CQFJ

64L MLPQ G

No

DEI reserves the right to make changes to any products or specifications herein. DEI makes no warranty, representation, or

guarantee regarding suitability of its products for any particular purpose.

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PIN ASSIGNMENTS

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FUNCTIONAL DESCRIPTION

RECEIVER

The receiver signals (DI(A) and DI(B)) are differential,

bipolar, return-to-zero logic signals. The ARINC channels

can be connected directly to the receiver with no external

components.

ANALOG FRONT END (AFE) WITH LIGHTNING

PROTECTION. The AFE implements the analog detection

portion of the receiver circuit. The ARINC 429

characteristic describes RX detection levels as follows.

Table 1: DEI1084 Pin Description

STATE

ONE

NULL

ZERO

DIFFERENTIAL VOLTAGE

+6.5V to +13V

SIGNAL

VDD

FUNCTION

POWER

INPUT

DESCRIPTION

Power Input: +3V or +5V .

ARINC receiver 1 positive input.

ARINC receiver 1 negative input.

ARINC receiver 2 positive input.

ARINC receiver 2 negative input.

Receiver 1 data flag ready.

Receiver 1 FIFO full.

+2.5V to -2.5V

-6.5V to -13V

RIN1A

RIN1B

RIN2A

RIN1B

/DR1

INPUT

The AFE detects the received ARINC line signal and

converts it into a stream of digital logic levels. It consists

of a pair of differential comparators per receiver capable of

±10V of common mode rejection. The AFE is powered by

an on chip 2.5V voltage regulator. This makes the part

capable of operating from a supply voltage ranging from

2.97V to 5.5V. The DEI1085 version parts bypass 10K

ohms of the input resistors, facilitating the use of 10K

external series resistors to provide lightning immunity

without impacting the input resistance specifications.

INPUT

OUTPUT

INPUT

/FF1

/HF1

Receiver 1 FIFO half full.

/DR2

Receiver 2 data flag ready.

Receiver 2 FIFO full.

/FF2

/HF2

Receiver 2 FIFO half full.

SEL

Receiver data byte selection

(0 = BYTE 1) (1 = BYTE 2).

Data Bus control, enables receiver 1

data to output.

/EN1

/EN2

INPUT

Lightning transient protection is provided at the receiver

input pins. The receiver input pins, in combination with

external 10K Ohm resistors, provide immunity to DO160

Level 3 Lightning Induced Transients. (These include the

600V peak damped sinusoid and 300V/150µs pulse). This

immunity is provided by the external 10K resistors

combined with the on-chip Zener diodes located within the

receiver input network. During a voltage transient, the

diodes shunt current to ground and drop most of the

transient voltage across the external resistors, thus

protecting the chip’s input pins.

Data Bus control, enables receiver 2

data to output.

BD[15:0]

GND

I/O

Data Bus.

POWER

INPUT

Power and signal ground.

/NFD

No frequency discrimination if low (pull

up)

/PL1

/PL2

INPUT

Latch enable for byte 1 entered from

data bus to transmitter FIFO.

Latch enable for byte 2 entered from

data bus to transmitter FIFO. Must

follow /PL1.

When the internal resistor wire bond option is used, the

application must provide Transient Voltage Suppressor

(TVS) devices to limit transient voltage to ±120V.

TX/R

OUTPUT

Transmitter ready flag. Goes low when

ARINC word loaded into FIFO. Goes

high after transmission and FIFO empty.

Transmitter FIFO half full.

Transmitter FIFO full.

/HFT

OUTPUT

16 BIT DATA BUS

A 16 Bit parallel bi-directional tri-state data bus provides

communication to the host.

/FFT

429DO

/429DO

/TXSEL

“ONES” data output from transmitter.

“ZEROS” data output from transmitter.

Transmitter Speed Select Status. Hi =

High speed,

SERIAL INTERFACE

The DEI1084 consists of two receive channels and one

transmit channel. Each receive channel operates

independently of each other and the transmitter. The

receive data is asynchronous to the transmitter data and

can also be at a different data rate than the transmitter.

Lo = Low speed. Inverted control word

“TXSEL”.

ENTX

/CWSTR

/RSR

INPUT

Enable transmission.

Clock for control word register.

Read status register if SEL = 0, read

control register if SEL = 1 (pull up)

Master clock input.

TRANSMITTER

The transmitter clock is free running and in phase with the

transmitter data. The transmitter data (DO(A) and DO(B))

are TTL level signals. There are always at least 4 null bits

between data words. An external ARINC line driver is

required to interface the transmitter to the ARINC serial

data bus.

CLK

INPUT

TX CLK

OUTPUT

Transmitter clock equal to master clock

(CLK), divided by either 10 or 80.

Master reset.

/MR

INPUT

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CONTROL REGISTER

STATUS REGISTER

A 16-bit control register is used to configure the device.

The control register bits CR0 – CR15 are loaded from

BD00 – BD15 when /CWSTR is pulsed low. The control

register contents are output on the data bus when SEL = 1

and /RSR is pulsed low. Each bit of the control register

has the following function:

The device contains a 9-bit status register which can be

interrogated to determine the status of the ARINC

receivers, data FIFOs and transmitter. The contents of the

status register are output on BD0 - BD08 when the /RSR

pin is taken low and SEL = 0. Unused bits are output as

zeros. The following table defines the status register bits.

Table 2: Control Register Bit definition

Table 3: Status Register Bit Definition

CR Bit FUNCTION STATE

DESCRIPTION

Data rate HI = CLK/10

Data rate LO= CLK/80

SR Bit

FUNCTION STATE

DESCRIPTION

Receiver 1 FIFO empty

CR0

CR1

CR2

CR3

Receiver 1

Data clock

Select

0

1

SR0

Data ready

0

1

(Receiver 1)

Receiver 1 FIFO contains valid

data. Resets to zero when all data

has been read. /DR1 pin is the

inverse of this bit

Label

0

1

Normal operation

Memory

Load 16 labels using /PL1,/PL2

Read 16 labels using /EN1, /EN2

Disable label recognition

Read/Write

Enable Label

Recognition

(Receiver 1)

Enable Label

Recognition

(Receiver 2)

Enable 32nd

bit as parity

SR1

SR2

SR3

SR4

SR5

FIFO

half full

0

1

Receiver 1 FIFO holds less than

16 words

0

(Receiver 1)

Receiver 1 FIFO holds at least 16

words. /HF1 pin is the inverse of

this bit

1

0

1

Enable label recognition

Disable label recognition

Enable label recognition

FIFO full

0

1

Receiver 1 FIFO not full

Receiver 1 FIFO full. To avoid

data loss, the FIFO must be read

within one ARINC word period.

/FF1 pin is the inverse of this bit.

Receiver 2 FIFO empty

(Receiver 1)

CR4

CR5

0

1

0

Transmitter 32nd bit is data

Transmitter 32nd bit is parity

The 429DO and /429DO digital

outputs are internally connected to

the Rx logic inputs

Self Test

Data ready

0

1

(Receiver 2)

Receiver 2 FIFO contains valid

data. Resets to zero when all data

has been read. /DR2 pin is the

inverse of this bit

1

0

1

Normal operation

CR6

Receiver 1

decoder

Receiver 1 decoder disabled

ARINC bits 9 and 10 must match

CR7 and CR8

FIFO

half full

0

1

Receiver 2 FIFO holds less than

16 words

CR7

CR8

CR9

-

If receiver 1 decoder is enabled, the

ARINC bit 9 must match this bit

If receiver 1 decoder is enabled, the

ARINC bit 10 must match this bit

Receiver 2 decoder disabled

ARINC bits 9 and 10 must match

CR10 and CR11

(Receiver 2)

Receiver 2 FIFO holds at least 16

words. /HF2 pin is the inverse of

this bit

FIFO full

0

1

Receiver 2 FIFO not full

Receiver 2 FIFO full. To avoid

data loss, the FIFO must be read

within one ARINC word period.

/FF2 pin is the inverse of this bit.

Transmitter FIFO not empty

Transmitter FIFO empty

Transmitter FIFO not full

Transmitter FIFO full. /FFT pin

is the inverse of this bit

Receiver 2

decoder

0

1

(Receiver 2)

CR10

CR11

CR12

-

If receiver 2 decoder is enabled, the

ARINC bit 9 must match this bit

SR6

SR7

Transmitter

FIFO empty

Transmitter

FIFO full

0

1

0

1

If receiver 2 decoder is enabled, the

ARINC bit 10 must match this bit

Transmitter 32nd bit is Odd parity

Transmitter 32nd bit is Even parity

Invert

Transmitter

parity

0

1

SR8

Transmitter

FIFO

0

1

Transmitter FIFO contains less

than 16 words

CR13

CR14

CR15

Transmitter

data clock

select

0

1

Data rate = HI = CLK/10

Data rate = LO = CLK/80

half full

Transmitter FIFO contains at least

16 words. /HFT pin is the inverse

of this bit

Receiver 2

Data clock

Select

0

1

Data rate = HI = CLK/10

Data rate = LO = CLK/80

Data format

0

1

Scramble ARINC data

Unscramble ARINC data

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If the /NFD pin is HI, the device accepts signals that meet

these specifications and rejects signals outside the

tolerances. The way this is achieved is described below:

DATA FORMAT

Control register bit CR15 is used to control how individual

bits in the received or transmitted ARINC word are

mapped to the data bus during data read or write

operations. Table 4 describes this mapping:

/NFD=HI

/NFD=LO

LO Speed HI Speed

10.4KBPS 83KBPS

15.6KBPS 125KBPS 500KBPS

0.1KBPS

Data Bit Rate Min

Data Bit Rate Max

Table 4: Parallel Data Bus Format, Scrambled & Not

Scrambled

If /NFD pin is held low, frequency discrimination is

disabled and any data stream totaling 32 bits is accepted

even with gaps between bits. The protocol still requires a

word gap as defined in 4 above.

DATA

BUS

ARINC BIT CR15 = 0

WORD1

ARINC BIT CR15 = 1

WORD2

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

WORD1

WORD2

8

7

6

5

4

3

2

1

Label

1

2

3

4

5

6

7

8

9

Label

SDI

17

18

19

20

21

22

23

24

BD00

BD01

BD02

BD03

BD04

BD05

BD06

BD07

BD08

BD09

BD10

BD11

BD12

BD13

BD14

BD15

RECEIVER PARITY

The receiver parity circuit counts Ones received, including

the parity bit. If the result is odd, then “0” will appear in

the 32nd bit.

RETRIEVING DATA

32 Parity

30

31

25

Once ARINC 32-bit word is recognized, the receiver logic

check for correct decoding and label matching prior to

loading the word into (or reject the word from) the 32 x 32

receiver FIFO. If CR2 or CR3 is/are ONE, then ARINC

words with have matching labels will be accepted into

Receiver FIFO. If CR6 or CR9 is/are ONE, then ARINC

words with matching decoder value (CR7, CR8 for RX1)

and (CR10, CR11 for RX2) will be accepted into Receiver

FIFO. The following table describes this operation:

10 SDI

26

11

12

13

14

15

16

27

28

29

30

9

SDI

10 SDI

11

12

13

31

32 Parity

BIT TIMING

The ARINC 429 characteristic describes the RX

acceptance timing as follows.

Table 5: RX Data Filter Logic

HIGH SPEED LOW SPEED

100K BPS ± 1% 12K to 14.4K BPS

CR2(3)

ARINC

word

matches

label

CR6(9)

ARINC word

bits 9&10

match CR7&8

(10&11)

FIFO

BIT RATE

1.5 ± 0.5 µs

5µs ± 5%

10 ± 5 µs

34.5 to 41.7 µs

RISE TIME

FALL TIME

PULSE WIDTH

0

1

0

1

X

No

Yes

X

0

1

X

No

Yes

No

Yes

No

Yes

Load FIFO

Ignore data

Load FIFO

Ignore data

Load FIFO

Ignore data

Load FIFO

1. Key to the performance of timing checking logic is an

accurate 1 MHz clock source. Less than 0.1% error is

recommended.

X

Yes

No

Yes

2. The sampling shift registers are 10 bits long and must

show three consecutive Ones, Zeros or Nulls to be

considered valid data. Additionally, for data bits, the One

or Zero in the upper bits of the sampling shift registers

must be followed by a Null in the lower bits within the

data bit time. For a Null in the word gap, three

consecutive Nulls must be found in both the upper and

lower bits of the sampling shift register. In this manner the

minimum pulse width is guaranteed.

Once a valid ARINC word is loaded into the FIFO, the

DATA READY FLAG will be turned on; /DR1 or /DR2

(or both) will go low. The data flag for a receiver will

remain low until all ARINC words are retrieved and the

Receiver FIFO is empty.

When data ready in Receiver FIFO, data can be retrieved

by activating (/EN1, SEL) or (/EN2, SEL) to output the

receiver data to the 16 bit parallel bus (see table 1).

Example to retrieve Receiver 1 data, first set (SEL = 0,

then /EN1 = 0) to place WORD1 on the 16-bit bus.

Release the 16-bit bus with (/EN1 = 1). Next set (SEL =1,

then /EN1 = 0) for WORD2. Last, release the 16-bit bus

with (/EN1 = 1). Use (/EN2) for Receiver 2 data retrieval.

3. The Word Gap timer samples the Null shift register

every 10 input clocks (80 for low speed) after the last data

bit of a valid reception. If the Null is present, the Word

Gap counter is incremented. A count of 3 will enable the

next reception.

4. Each data bit must follow its predecessor by not less

than 8 samples and no more than 12 samples. In this

manner the bit rate is checked. With exactly 1 MHz clock

frequency, the acceptable data bit rates are as follows:

Up to 32 ARINC words may be loaded into each receiver’s

FIFO. The /FF1 (/FF2) pin will go low when the receiver

1 (2) FIFO is full. Failure to retrieve data from a full FIFO

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will cause the next valid ARINC word received to

overwrite the existing data in FIFO location 32.

(/HF2) pin is intended to act as an interrupt flag to the

systems external microprocessor, allowing a 16 word data

retrieval routine to be performed, without the user needing

to continually poll the status register bits.

A FIFO half full flag /HF1 (/HF2) goes low if the FIFO

contains 16 or more received ARINC words. The /HF1

RECEIVERS

Figure 1 Receiver Function Diagram

write to all 16 location of label memory to ensure that no

previous unwanted label memory residual affect the label

recognition. Note that ARINC word reception is suspended

during the label memory write sequence. Therefore, CR1

of control register has to be written with zero before

returning to normal operation.

LABEL RECOGNITION

The chip compares the incoming label to the stored labels

if label recognition is enabled. If a match is found, the

data is processed. If a match is not found, no indicators of

receiving ARINC data are presented. Note that 00 (Hex) is

treated in the same way as any other label value. Label bit

significance is not changed by the status of control register

bit CR15. Label bits BD00 – BD07 are always compared

to receive ARINC bits 1- 8 respectively.

READING LABELS

When writing to, or reading from the label memory, SEL

must be set HIGH. Write to control register with Enable

Label Read/Write (set CR1 = 1) and Disable Label

recognition (set CR2,3 = 0) during the label read sequence.

Then the next 16 data reads of the selected receiver (/EN

taken low) are labels. /EN1 is used to read labels for

receiver 1, and /EN2 to read labels for receiver 2. Label

data is presented on BD00 – BD07. All 16 locations should

be accessed, and CR1 must be written to zero before

returning to normal operation.

LOADING LABELS

When writing to, or reading from the label memory, SEL

must be set HIGH. Write to control register with Enable

Label Read/Write (set CR1 = 1) and Disable Label

recognition (set CR2,3 = 0) during the label write

sequence. Then the next 16 writes of data (/PL pulsed low)

load the label data into each location of the label memory

from the BD00 – BD07 pins. The /PL1 pin is used to write

label data for receiver 1 and /PL2 for receiver 2. Always

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TRANSMITTER

Figure 2 Transmitter Function Diagram

FIFO OPERATION

DATA TRANSMISSION

Prior to loading FIFO (TX Buffer), do these (sequence

does not matter):

Set ENTX to high to enable transmission, the FIFO

positions are incremented with the top register loading into

the data transmission shift register. Within 2.5 data clocks

the first data bit appears at 429DO and /429DO. The 32

bits in the data transmission shift register (or 31 bits plus

parity bit) are presented sequentially to the outputs in the

ARINC 429 format with the following timing:

HI Speed LO Speed

1) Hold ENTX at Low to stop enable transmission

2) Check if TX/R is low (which means TX Buffer is

empty).

When the FIFO is empty and ENTX low, then proceed to

load FIFO with /PL1 and /PL2.

Otherwise asserting /PL1 and /PL2 has not data loading

effect to the FIFO.

10 Clocks 80 Clocks

5 Clocks

ARINC Data Bit Time

Data Bit Time

Null Bit Time

40 Clocks

The FIFO is loaded sequentially by first pulsing /PL1 to

load byte 1 and then /PL2 to load byte 2. The control logic

automatically loads the 31 bit word (or 32 bit word if CR4

= 0) in the next available position of the FIFO. If TX/R,

the transmitter ready flag is high (FIFO empty), then up to

32 words, each 31 or 32 bits long, may be loaded. If TX/R

is low, then only the available positions may be loaded. If

all 32 positions are full, the /FFT flag is asserted and the

FIFO ignores further attempts to load data.

40 Clocks 320 Clocks

Word Gap Time

The word counter detects when all loaded positions have

been transmitted and sets the transmitter ready flag, TX/R,

high. Once the transmission start it will continue till the

TX FIFO is empty. Setting ENTX to low at the mid point

of transmission does not stop the transmission.

TRANSMITTER PARITY

The parity generator counts the Ones in the 31 bit word. If

control register bit CR12 is set low, the 32nd bit

transmitted will make parity odd. If the control bit is high,

the parity is even. Setting CR4 to a zero bypasses the

parity generator, and allows 32 bits of data to be

transmitted.

A transmitter FIFO half-full flag /HFT is provided. When

the transmit FIFO contains less than 16 words, /HFT is

high, indicating to the system microprocessor that a 16

ARINC word block write sequence can be initiated.

In normal operation (CR4 = 1), the 32nd bit transmitted is

MASTER RESET

a parity bit.

Odd or even parity is selected by

On a Master Reset data transmission and reception are

immediately terminated, all three FIFOs cleared as are the

FIFO flags at the device pins and in the Status Register.

The Control Register is not affected by a Master Reset.

programming control register bit CR12 to a zero or one. If

CR4 is programmed to a 0, the all 32 bits of data loaded

into the transmitter FIFO are treated as data and are

transmitted.

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2. The transmitter FIFO can store 32 words

maximum and ignores attempts to load additional

data if full.

SELF TEST

If control register bit CR5 is set low, the transmitter serial

output data are internally connected to each of the two

receivers, bypassing the analog interface circuitry. Data is

passed unmodified to receiver 1 and inverted to receiver 2.

The serial data from the transmitter is always present on

the 429DO and /429DO outputs regardless of the state of

CR5.

REPEATER OPERATION

Repeater mode of operation allows a data word that has

been received by the device to be placed directly into the

transmitter FIFO. Repeater operation is similar to normal

receiver operation. In normal operation, either byte of a

received data word may be read from the receiver latches

SYSTEM OPERATION

The two receivers are independent of the transmitter.

Therefore, control of data exchanges is strictly at the

option of the user. The only restrictions are:

first by use of SEL input.

During repeater operation

however, the lower byte of the data word must be read

first. This is necessary because, as the data is being read, it

is also being loaded into transmitter FIFO which is always

loaded with the lower byte of data word first. Signal flow

for repeater operation is shown in the timing diagram

section.

1. The receive data will be overwritten if the

receiver FIFO is full and at least one location is

not retrieved before the next complete ARINC

word is received.

TIMING DIAGRAMS

Figure 3 Data Rate Example

Figure 4 Receiver Operation

Figure 5 Transmitter Operation

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Figure 6 Load Control Word

Figure 7 Status Register Read Cycle

Figure 8 Control Register Read Cycle

Figure 9 Label Memory Load Sequence

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Figure 10 Label Memory Read Sequence

Figure 11 Transmitting Data

Figure 12 Repeater Operation

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ELECTRICAL CHARACTERISTICS

DC CHARACTERISTICS

Table 6: DC Characteristics

Conditions: Ta = -55 to +125 ºC, Vdd = 3.3V ± 10% and 5V ± 10%

PARAMETER SYMBOL CONDITIONS

MIN

TYP

MAX

UNIT

ARINC INPUTS: RIN[1A/1B/2A/2B] aka DI[1A/1B/2A/2B] or

RIN[1A/1B/2A/2B]E aka DI[1A/1B/2A/2B]E with external 10K Ohm resistors

Differential Input Voltage

ONE

ZERO

NULL

Vil

Vnull

6.5

-13.0

-2.5

-10

10.0

-10.0

0

-13.0

-6.5

2.5

V

Common Mode Input Voltage

Input Resistance:

Differential

Vcm

10

RI

RG

RH

CI

24

12

132

67

7500

200

100

KOhm

pF

To GND

To VDD

Input Capacitance

20

LOGIC INPUTS

Vdd = 3.0V to 5.5V 0.7*Vdd

Input Voltage HI

Input Voltage LO

Input Pull-up Current,

/NFD. /RSR pins

VIH

VIL

IPU

Vdd+0.5

0.8

V

µA

Vdd = 3.0V to 5.5V

-0.5

-100

Input Currents, all others pins

IIN

-10

10

µA

LOGIC OUTPUTS

IOH = -4ma

IOH = -100ua

IOL = 4ma

Output Voltage: TTL Logic 1

Output Voltage: CMOS Logic 1

Output Voltage: TTL Logic 0

Output Voltage: CMOS Logic 0

Output Capacitance:

VOH-T

VOH-C

VOL-T

VOL-C

Cout

Vdd -0.5

Vdd -0.1

V

pF

0.4

0.1

10

IOL = 100ua

OPERATING SUPPLY CURRENT

VDD = 3.3V or 5V

Supply Voltage

IDD

Fck = 1MHZ

IDD ~

4*(VDD-2.7)

10

mA

V

VDD

3.0

5.5

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AC CHARACTERISTICS

Table 7: General AC Characteristics

PARAMETER

SYMBOL

UNITS

Data Rate

100kbps

Data Rate

12.5kbps

MIN

0.99

MAX

1.01

MIN

0.99

MAX

1.01

1MCK Frequency

f1MCK

CKDC

TCRF

TDR

MHz

%

1MCK Duty Cycle

40

60

10

40

60

10

1MCK Rise/Fall Time

ns

Transmitter Data Rate (1MCK = 1MHz)

99

101

125

12.4

10.2

12.6

15.6

kbps

Receiver Data Rate (1MCK = 1MHz)

(DATA = 50% BIT/ 50% NULL TIME)

Receiver Data Rate

RDR

83.3

kbps

/NFD

71.4

166

8.77

19.2

kbps

No Frequency Discrimination (/NFD=0)

AC TIMING CHARACTERISTICS

Table 8: 3V AC Characteristics

SYMBOL MIN

PARAMETER

TYP

MAX UNITS

CONTROL WORD TIMING

Pulse Width: /CWSTR t_CWSTR

Setup: DATA BUS Valid to /CWSTR Hi t_CWSET

Hold: /CWSTR Hi to DATA BUS Hi-Z t_CWHLD

80

60

40

ns

RECEIVER FIFO AND LABEL READ TIMING

Delay: Start ARINC 32nd bit to /DR Lo:

High Speed

Low Speed

Delay: /DR Lo to /EN Lo

Delay: /EN Hi to /DR Hi

Setup: SEL to /EN Lo

Hold: SEL to /EN Hi

Delay: /EN Lo to DATA BUS Valid

Delay: /EN Hi to DATA BUS Hi-Z

Pulse Width: /EN1 or /EN2

Spacing: /EN Hi to next /EN Lo (Same ARINC Word)

Spacing: /EN Hi to next /EN Lo (Next ARINC Word)

t_D/R

16

128

µs

ns

t_D/REN

t_END/R

t_SELEN

t_ENSEL

t_ENDATA

t_DATAEN

t_EN

0

60

80

150

20

140

100

120

140

1033

t_ENEN

t_READEN

TRANSMITTER FIFO AND LABEL WRITE TIMING

Pulse Width: /PL1 or /PL2

t_PL

t_DWSET

t_DWHLD

t_PL12

t_LABEL

t_TX/R

80

60

40

60

ns

Setup: DATA BUS Valid to/PL Hi

Hold: /PL Hi to DATA BUS Hi-Z

Spacing: /PL1 to /PL2

Spacing between Label Write pulses

Delay: /PL2 Hi to TX/R Lo

100

50

TRANSMISSION TIMING

Spacing: /PL2 Hi to ENTX Hi

Delay: 32nd ARINC Bit to TX/R Hi

Spacing: TX/R Hi to ENTX Lo

t_PL2EN

t_DTX/R

t_ENTX/R

0

ns

REPEATER OPERATION TIMING

Delay: /EN Lo to /PL Lo

Hold: /PL Hi to /EN Hi

Delay: TX/R Lo to ENTX Hi

MASTER RESET PULSE WIDTH

t_ENPL

t_PLEN

t_TX/REN

t_MR

0

80

ns

ARINC DATA RATE AND BIT TIMING

± 1%

Table 9: 5V AC Characteristics

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PARAMETER

SYMBOL MIN

CONTROL WORD TIMING

TYP

MAX UNITS

Pulse Width: /CWSTR t_CWSTR

Setup: DATA BUS Valid to /CWSTR Hi t_CWSET

80

60

40

ns

Hold: /CWSTR Hi to DATA BUS Hi-Z

t_CWHLD

RECEIVER FIFO AND LABEL READ TIMING

Delay: Start ARINC 32nd bit to /DR Lo:

High Speed

Low Speed

Delay: /DR Lo to /EN Lo

Delay: /EN Hi to /DR Hi

Setup: SEL to /EN Lo

Hold: SEL to /EN Hi

Delay: /EN Lo to DATA BUS Valid

Delay: /EN Hi to DATA BUS Hi-Z

Pulse Width: /EN1 or /EN2

Spacing: /EN Hi to next /EN Lo (Same ARINC Word)

Spacing: /EN Hi to next /EN Lo (Next ARINC Word)

t_D/R

16

128

µs

ns

t_D/REN

t_END/R

t_SELEN

t_ENSEL

t_ENDATA

t_DATAEN

t_EN

0

20

80

100

20

140

100

120

140

1033

t_ENEN

t_READEN

TRANSMITTER FIFO AND LABEL WRITE TIMING

Pulse Width: /PL1 or /PL2

t_PL

t_DWSET

t_DWHLD

t_PL12

t_LABEL

t_TX/R

80

60

40

60

ns

Setup: DATA BUS Valid to/PL Hi

Hold: /PL Hi to DATA BUS Hi-Z

Spacing: /PL1 to /PL2

Spacing between Label Write pulses

Delay: /PL2 Hi to TX/R Lo

100

50

TRANSMISSION TIMING

Spacing: /PL2 Hi to ENTX Hi

Delay: 32nd ARINC Bit to TX/R Hi

Spacing: TX/R Hi to ENTX Lo

t_PL2EN

t_DTX/R

t_ENTX/R

0

ns

REPEATER OPERATION TIMING

Delay: /EN Lo to /PL Lo

Hold: /PL Hi to /EN Hi

Delay: TX/R Lo to ENTX Hi

MASTER RESET PULSE WIDTH

ARINC DATA RATE AND BIT TIMING

t_ENPL

t_PLEN

t_TX/REN

t_MR

0

50

ns

± 1%

ABSOLUTE MAXIMUM RATINGS

Table 10: Absolute Maximum Ratings

SYMBOL MIN

PARAMETER

MAX

UNITS

Supply Voltage

VDD

-0.5

-0.6

+7.0

V

DC Input Voltage, Logic inputs

VIN-logic

VCC

+ 0.6

DC Input Voltage, RX pins:

RIN[1A/1B/2A/2B] aka DI[1A/1B/2A/2B]

RIN[1A/1B/2A/2B]E aka DI[1A/1B/2A/2B]E at external 10K VIN-rxe

ohm series resistor

VIN-rx

±120

V

Clamp diode current, any pin except RX inputs

±25

mA

°C

DC Output Current per pin

DCV or GND current per pin

±50

Storage Temperature

Tstg

-65

+150

+145

Junction Temperature, operating

TJmax

°C

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ESD PROTECTION

ESD protection is provided on all pins per 2KV HBM specification, except the receiver input pins. These will be limited to

input resistor rupture voltage of ~1KV.

PACKAGE DESCRIPTION

Table 11 Package Characteristics

PACKAGE

TYPE

PACKAGE

REF

JEDEC MOISTURE

SENSITIVITY

LEVEL & PEAK

BODY TEMP

LEAD FINISH

MATERIAL /

JEDEC Pb-Free

DESIGNATION

Pb Free

Designation

JEDEC

MO

THERMAL

RESIST.

ș_JC/ ș_JA

(ºC/W)

52L METRIC

QUAD FLAT

PACK

RoHS

Compliant

MS-022-

AC

52L MQFP

G

MSL 3

260ºC

Matte Sn

e3

21 / 65

52L CERAMIC

QUAD FLAT J-

LEAD

Pb Free solder

terminals

Au

e4

52 CQFJ

TBD

HERMETIC

64L 9X9

MICRO LEAD

PACK QUAD

RoHS

Compliant

MO-220-

VMMD

64 9X9

MLPQ G

MSL 3

260ºC

Matte Sn

e3

10 / 30

Figure 13 52L MQFP G

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Figure 14 52L CQFJ

NOTE: The heat sink on bottom of package must be left floating or connected to GND. Do NOT connect to VDD.

Figure 15 64L 9x9 MLPQ G

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型号：	DEI1084-MES-G
厂家：	Device Engineering Incorporated
描述：	ARINC 429 ENHANCED TRANSCEIVER 通信时钟数据传输外围集成电路
文件：	总15页 (文件大小：1321K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DEI1084-MES-G [DEIAZ]

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