DEI1148 [DEIAZ]
OCTAL ARINC 429 LINE RECEIVER;
| 型号： | DEI1148 |
| 厂家： | 
Device Engineering Incorporated |
| 描述： | OCTAL ARINC 429 LINE RECEIVER |
| 文件： | 总8页 (文件大小：532K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Device
Engineering
Incorporated
DEI1148
OCTAL ARINC 429 LINE
RECEIVER
385 East Alamo Drive
Chandler, AZ 85225
Phone: (480) 303-0822
Fax: (480) 303-0824
E-mail: admin@deiaz.com
FEATURES
·
·
·
Octal ARINC 429 to TTL/CMOS logic line receivers
Operates from single +5 V ± 10% or 3.3 V ± 10% power supply
Operates in high noise environment
o
o
Input Common Voltage Range: ± 20 V
2 V minimum Input hysteresis
·
·
·
ARINC inputs internally protected to lightning requirements of DO-160 Level A3
Withstands inadvertent short to 115 Vac on inputs
Package: 44L MQFP, 13.9mm footprint
PINOUT
PIN
NAME
DESCRIPTION
429 INPUTS. ARINC 429 format serial
digital data “A” inputs.
15, 13, 11, 9,
2, 44, 42, 40
IN[8:1]A
429 INPUTS. ARINC 429 format serial
digital data “B” inputs.
16, 14, 12, 10,
3, 1, 43, 41
IN[8:1]B
TESTAA
LOGIC INPUT. Test input A (+) for odd
channels.
5
6
7
8
LOGIC INPUT. Test input A (-) for odd
channels.
TESTAB
LOGIC INPUT. Test input B (+) for even
channels.
TESTBA
LOGIC INPUT. Test input B (-) for even
channels.
TESTBB
LOGIC OUTPUTS. CMOS/TTL format
serial digital data “A” outputs.
19, 21, 23, 25,
32, 34, 36, 38
OUT[8:1]A
OUT[8:1]B
LOGIC OUTPUTS. CMOS/TTL format
serial digital data “B” outputs.
18, 20, 22, 24,
31, 33, 35, 37
29
27
VDD
VSS
POWER INPUT. 5 V OR 3.3 V.
POWER INPUT. Ground.
Figure 1 DEI1148 Pinout
©2019 Device Engineering Inc.
Page 1 of 8
DS-MW-01148-01 Rev B
01/08/2019
FUNCTIONAL DESCRIPTION
The DEI1148 is a BiCMOS device which contains eight differential line receivers. Each receiver channel translates
incoming ARINC 429 data bus signals (tri-level RZ bipolar differential modulation) to a pair of TTL/CMOS logic
outputs. Each channel operates independently and meets the requirements of the ARINC 429 Digital Information
Transfer Standard. Refer to Figure 2 DEI1148 Block Diagram and Truth Table.
The device is designed to operate in a high noise environment. Inputs are accepted over a ±20 V common mode
voltage range and the receivers provide over 2 Volts of hysteresis. Circuit speed is optimized to reject high
frequency transients.
The DEI1148 device provides logic level TEST inputs for built in system test. There are two TEST input ports, each
force the outputs of four receivers to the specified ZERO, ONE or NULL state. The ARINC inputs are ignored when
the device is in test mode.
The ARINC inputs incorporate on-chip lightning protection by use of high value resistors on the inputs to minimize
IR heating. The resistors have dielectric isolation to withstand the voltage transients. The inputs withstand lightning
induced transients up to and including DO160 Level 3 pin injection levels. Higher levels can be achieved with the
addition of external TVS devices between the inputs and VSS, or alternately, TVS devices in combination with series
current limiting resistors between the ARINC bus and the IC/TVS node. The series resistors reduce the power
requirement and size of the TVS. Resistor values up to 10K ohms are feasible.
The ARINC inputs withstand inadvertent short to 115 Vac aircraft power without sustaining damage.
Figure 2 DEI1148 Block Diagram and Truth Table
©2019 Device Engineering Inc.
Page 2 of 8
DS-MW-01148-01 Rev B
01/08/2019
ELECTRICAL DESCRIPTION
Table 1: Absolute Maximum Rating
PARAMETER
Supply Voltage (with respect to VSS)
MIN
-0.3
-65
MAX
7.0
UNITS
V
Storage Temperature
+150
115
°C
Input Voltage, continuous (ARINC Inputs)
Power Dissipation @ 85 °C
Vac
mW
°C
800
Junction Temperature, Tjmax (limited by molding compound Tg)
Peak Body Temperature
145
260
°C
Lightning Protection (ARINC 429 Channel Inputs)
Waveform 3 (2)
Waveform 4, 5A, 5B (2) (3)
-720
-360
+720
+360
V
V
ESD JS-001-2017 HBM
1B
Class
Notes:
1. Stresses above these limits can cause permanent damage.
2. Per DO160, Sect 22 Level 3 pin injection. See Figures 5 – 7.
3. Inputs can be protected to withstand higher stress by adding series resistors and shunt TVS on inputs. Inputs
withstand 1500 V Waveform 5A when clipped ≤ 600 V.
Table 2: Recommended Operating Conditions
SYMBOL
CONDITIONS
PARAMETER
+5 V ±10%
+3.3 V ±10%
Supply Voltage
VDD
Logic Input Levels
TESTA/B
0 to VDD
Operating Temperature
-QES
-QMS
Ta
-55 to +85 °C
-55 to +125 °C
©2019 Device Engineering Inc.
Page 3 of 8
DS-MW-01148-01 Rev B
01/08/2019
Table 3: Electrical Characteristics
Conditions: Temperature: -55 °C to +85 °C (-QES); -55 °C to +125 °C (-QMS)
VDD = +5 V ±10% or 3.3 V ±10%
PARAMETER
TEST CONDITION
ARINC INPUTS
SYMBOL
MIN
MAX
UNITS
VA – VB = Logic +1
VA – VB = Logic -1
OUTA = 1
OUTB = 1
V+1
V-1
6.5
13
V
V
-6.5
-13
OUTA = 0
OUTB = 0
VA – VB = Logic Null
Input Hysteresis
VNULL
VHY
-2.5
2.0
-20
2.5
4.0
+20
V
V
V
Input Common Mode
Voltage Range
Logic +1, Null, Logic -1
VCM
Input Resistance
INA to INB
VDD open,
Shorted to VSS or +5 V (1)
RIN
RS
280
140
kW
kW
pF
pF
Input Resistance
INA or INB to VSS
VDD open,
Shorted to VSS or +5 V
Input Capacitance
INA to INB
VDD open,
Shorted to VSS or +5 V (1)
CIN
CS
10
10
Input Capacitance
INA or INB to VSS
VDD open,
Shorted to VSS or +5 V (1)
LOGIC INPUTS
Logic 0 Voltage
Logic 1 Voltage
Logic 0 Current
Logic 1 Current
VIL
VIH
IIL
0.8
V
V
2.0
2.4
VIL = 0.8
VIH = 2.0
25
25
µA
µA
IIH
LOGIC OUTPUTS
IOH = -5 mA (VDD = 5.0 V)
IOH = -5 mA (VDD = 3.3 V)
TTL Compatible
OUTPUT HIGH VOLTAGE
TTL
VOH
VOL
V
OUTPUT LOW VOLTAGE
TTL
IOL = 5mA (VDD = 5.0 V)
0.4
V
V
V
OUTPUT HIGH VOLTAGE
CMOS
IOH = 100 µA
CMOS Compatible
VDD –
50mV
VOH
VOL
OUTPUT LOW VOLTAGE
CMOS
IOL = 100 µA
CMOS Compatible
VSS+
50mV
SUPPLY CURRENT
Data Rate = 0 MHZ,
INA/B = open,
OUTA/B = open,
VDDCurrent
IDD
1.5
8.5
mA
VDD = 5.5 V or 3.63 V
Notes:
1. Guaranteed by design, not production tested.
2. Current flowing into device is positive. Current flowing out of device is negative. All
voltages are with respect to VSS unless otherwise noted.
©2019 Device Engineering Inc.
Page 4 of 8
DS-MW-01148-01 Rev B
01/08/2019
Table 4: Switching Characteristics
MAX
VDD 3.3V VDD 5V
MAX
PARAMETER
TEST CONDITION (1,2)
SYMBOL
UNITS
TESTA = TESTB = 0
CL = 50 pF
INA/B to OUTA/B Prop Delay
tLH
1000
1000
900
900
ns
TESTA = TESTB = 0
CL = 50 pF
INA/B to OUTA/B Prop Delay
tHL
ns
OUTA/B rise time
OUTA/B fall time
10% to 90%, CL = 50 pF
10% to 90%, CL = 50 pF
tr
tf
50
50
25
25
ns
ns
TESTA/B to OUTA/B Prop
delay
CL = 50 pF
CL = 50 pF
tTOH
tTOL
100
100
60
60
ns
ns
TESTA/B to OUTA/B Prop
delay
Notes:
1. Refer to Figures 3 - 4.
2. Sample tested
©2019 Device Engineering Inc.
Page 5 of 8
DS-MW-01148-01 Rev B
01/08/2019
INA
TESTA OR B
1.5V
Vdif = 6.5V
Vdif = 2.5V
tTOH
INB
tTOL
tHL
tLH
OUTA OR B
OUTA
OUTB
1.5V
1.5V
1.5V
Figure 3 ARINC 429 Input to Logic Output Switching
Waveform
Figure 4 TEST Input to Logic Output Switching
Waveform
V
V/I
Peak
Largest
Peak
25% to 75%
of Largest Peak
T1 = 6.4 µs ±20%
T2 = 70 µs ±20%
50%
0
50%
t
0
t
T1
T2
Figure 5 DO160 Lightning Induced Transient Voltage
Waveform #4 Pin Injection
Figure 6 DO160 Lightning Induced Transient Voltage
Waveform #3 Pin Injection
Voc = 300 V, Isc = 60 A.
Voc = 600 V, Isc = 24 A. Freq = 1 MHZ ±20%
V/I
Peak
5A: T1 = 40 us ±20%
LIGHTNING TRANSIENT NOTES:
T2 = 120 us ±20%
1. Voc = Peak Open Circuit Voltage available at
the calibration point.
2. Isc = Peak Short Circuit Current available at
the calibration point.
50%
3. Amplitude tolerances: +10%, -0%.
4. The ratio of Voc to Isc is the generator
source impedance to be used for generating
the waveforms.
0
t
T1
T2
Figure 5 DO160 Lightning Induced Transient Voltage
Waveform #5A Pin Injection.
©2019 Device Engineering Inc.
Page 6 of 8
DS-MW-01148-01 Rev B
01/08/2019
ORDERING INFORMATION
Table 5: Ordering Information
TEST
INPUTS
TEMPERATURE
DEI PN
MARKING (1)
PACKAGE
44L MQFP G
44L MQFP G
SCREENING
Standard
RANGE
DEI1148-QES
(e3)
DEI1148-QES-G
DEI1148-QMS-G
YES
YES
-55/+85 °C
DEI1148-QMS
(e3)
-55/+125 °C
Standard
Notes:
1. All packages marked with Lot Code and Date Code. (e3) after Date Code denotes Pb Free category.
Table 6: Screening Process
SCREENING
ELECTRICAL TEST:
STANDARD
ROOM TEMPERATURE
HIGH TEMPERATURE
LOW TEMPERATURE
100%
100% @ 85 °C or 125 °C
0.65% AQL @ -55 °C
PACKAGE DESCRIPTION
Table 7: Package Characteristics
CHARACTERISTIC
VALUE
44L
MQFP G
REFERENCE
52 °C/W
12 °C/W
QJA
QJC
(4 layer PCB with Power Planes)
JEDEC MOISTURE
SENSITIVITY LEVEL (MSL)
MSL 3 / 260 °C
LEAD FINISH MATERIAL /
JEDEC Pb-free CODE
Matte Sn
e3
Pb-Free DESIGNATION
JEDEC REFERENCE
RoHS Compliant
MO-112 VAR AA-11
©2019 Device Engineering Inc.
Page 7 of 8
DS-MW-01148-01 Rev B
01/08/2019
Figure 6 44L PQFP Mechanical Outline
DEI reserves the right to make changes to any products or specifications herein. DEI makes no warranty, representation, or
guarantee regarding suitability of its products for any particular purpose.
©2019 Device Engineering Inc.
Page 8 of 8
DS-MW-01148-01 Rev B
01/08/2019
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