DEI1160-SMS [DEIAZ]
PROGRAMMABLE GND/OPN & 28V/OPN DISCRETE INPUT INTERFACE IC;
| 型号： | DEI1160-SMS |
| 厂家： | 
Device Engineering Incorporated |
| 描述： | PROGRAMMABLE GND/OPN & 28V/OPN DISCRETE INPUT INTERFACE IC 输入元件 光电二极管 接口集成电路 |
| 文件： | 总13页 (文件大小：517K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Device
Engineering
Incorporated
DEI1160
385 East Alamo Drive
Chandler, AZ 85225
Phone: (480) 303-0822
Fax: (480) 303-0824
E-mail: admin@deiaz.com
PROGRAMMABLE GND/OPN &
28V/OPN DISCRETE INPUT
INTERFACE IC
FEATURES
x
Eight discrete inputs
o
o
o
o
o
o
Individually configurable to sense either GND/OPEN or 28V/OPEN(or 28V/GND) discrete signals
Hysteresis provides noise immunity
1mA input current to prevent dry relay contacts.
Internal isolation diode
Inputs protected from Lightning Induced Transients per DO160E, Section 22, Cat A3 and B3.
Inputs protected from Power Input Abnormal Surge per DO160E, Section 16, Cat Z.
x
Serial I/O interface to read data register and write configuration register
o
o
o
o
Direct interface to Serial Peripheral Interface (SPI) port.
TTL/CMOS compatible inputs and Tristate output
10MHz Data Rate
Serial input to expand Shift Register
x
x
x
Logic Supply Voltage (VCC):
Analog Supply Voltage (VDD):
16L SOIC EP package
3.3V or 5V
15V +/-10%
PIN ASSIGNMENTS
1
16
VDD
GND
VCC
SEL
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
DEI1160
SDI
/CS
SCLK
SDO
Figure 1 DEI1160 Pin Assignment (16 Lead SOIC)
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FUNCTIONAL DESCRIPTION
The DEI1160 is an eight-channel discrete-to-digital interface IC implemented in an HV DMOS technology. It senses eight
discrete signals of the type commonly found in avionic systems and converts them to serial logic data. Each input can be
individually configured as either GND/OPEN or 28V/OPEN format input via a serial data input command. The discrete data
is read from the device via an eight-bit serial shift register with 3-state output. This serial interface is compatible with the
industry standard Serial Peripheral Interface (SPI) bus.
Table 1 Pin Descriptions
PINS
NAME
DESCRIPTION
1-8
DIN[1:8]
Discrete Inputs. Eight discrete signals which can be individually
configured as either GND/OPEN or 28V/OPEN format inputs.
Logic Output. Serial Data Output. This pin is the output from MSB (Bit
8) of the selected shift register (Data/Configuration). It is clocked by the
rising edge of SCLK. This is a 3-state output enabled by /CS.
Logic Input. Serial Shift Clock. A low-to-high transition on this input
shifts data on the serial data input into Bit 0 of the selected shift register.
The selected shift register is shifted from Bit 0 to Bit 7. Bit 7 of the
selected shift register is driven on DOUT.
9
SDO
10
SCLK
11
/CS
Logic Input. Chip Select. A low level on this input enables the SDO 3-
state output and the selected shift register. A high level on this input
forces DOUT to the high impedance state and disables the shift registers
so SCLK transitions have no effect. When the Data register is selected, a
high-to-low transition causes the Discrete Input data to be loaded into the
Data register. When the Configuration Register is selected, a low-to-high
transition causes the Serial Configuration register data to be loaded into
the parallel configuration outputs.
12
13
SDI
Logic Input. Serial Data Input. Data on this input is shifted into the LSB
(Bit 1) of the selected shift register on the rising edge of the SCLK when
/CS input is low.
Logic Input. Selects between the Serial DATA and CONFIGURATION
registers. H = DATA, L = CONF.
SEL
14
15
16
VCC
GND
VDD
Logic Supply Voltage. 3.3V or 5V
Logic/Signal Ground
Analog Supply Voltage. +15V+/-10%
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SCLK
Control
Logic
/CS
SEL
ENB
SDO
MUX
SFT/LD
SDI
CONFIGURATION REG
8 bit Shift Register
SDO
(D0)
w/ latched parallel output
SCK
PDO[1:8]
VDD
VCC
CFG_SEL[1:8]
DISCRETE AFE
Channels 1 to 8
DIN[1:8]
DIN[1:8]
DOUT[1:8]
GND
PDI[1:8]
SFT/LD
SDI
DATA REG
8 bit Shift Register
w/ Parallel Input
SDO
(D0)
SDI
SCK
Figure 2 FUNCTION DIAGRAM
Vdd
100K
2K
Vdd
dpda
50V
Vcc
DINN
+
10K
AMP
+
400khz
DOUTN
dpd
20V
Comparator
Vos
10K
-
dp
20V
qna
80v
Vthreshold
REFERENCE
SELECT
CFG_SELN
Figure 3 DISCRETE AFE FUNCTION DIAGRAM
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Table 2 Truth Table
SEL
X
H
/CS
H
Ļ
SCLK
SDI
X
X
DIN[1:8]
SDO
HI Z
DIN[8]
DR[8]
DESCRIPTION
Not Selected
DR[1:8]ĸ DIN[1:8]
X
L
Ĺ
X
Valid
X
H
L
DR[1]
DR[n+1] ĸ DR[n], DR[1] ĸ SDI
L
L
L
Ĺ
Ĺ
L
CR[1]
X
X
X
CR[8]
HI Z
CR[n+1] ĸ CR[n], CR[1] ĸ SDI
CL[1:8]ĸ CR[1:8]
Legend:
DR = Data Register
CR = Configuration Register
CL = Configuration Latch
DIN[1:8] Discrete AFE
The Discrete Input Analog Front End circuit function is represented in Figure 3. Each DINn signal is conditioned by the
resistor / diode network and presented to an amplifier followed by a comparator with hysteresis. When the input is configured
for GND/OPEN operation, the pull-up resistor & diode is enabled and the appropriate amplifier offset voltage and comparator
threshold voltage are selected. When configured for 28V/OPEN, the pull-down resistor is enabled and the amp/comparator is
appropriately configured.
Some notable features are:
x
x
The input current is ~1mA. This current will prevent a “dry” relay contact.
The input threshold voltage and hysteresis:
o
o
o
The falling Vth > 3.5V.
The rising Vth < 14V.
Hysteresis is maximum practical to meet the threshold requirements.
x
x
Input noise immunity is maximized with a combination of voltage hysteresis and use of a slow input voltage
comparator
The inputs can withstand continuous input voltages of 40V minimum. The isolation diode breakdown voltage is
greater than 45V. The 10K Ohm input resistor is designed to limit diode breakdown current to safe levels during
transient events.
Data Register
The 8-bit Data Register is a “parallel-input, serial-output” register that samples the input channels and reads-out the data to the
Serial Data Output. The register is read via the SDO output as described in Figure 4 and Figure 5. A low input level results in
a Logic 0, and a high input level results in a Logic 1.
Configuration Register
The 8-bit Configuration Register is a “serial-input, parallel-output with data latch” register that individually configures each
AFE input as either GND/OPEN or 28V/OPEN format. The register is programmed via the serial data input as described in
Figure 6 and Figure 7. Logic 0 sets the respective input to 28V/OPEN mode (pull-down); Logic 1 sets the respective input to
GND/OPEN mode (pull-up).
The register is Reset to 0’s when the Vcc Logic Supply voltage transitions from low to hi, thus initializing the AFE inputs to a
pull-down state.
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Serial Interface
The DEI1160 incorporates a serial IO interface for programming the Discrete Input configuration and for reading the Discrete
Input status. Refer to Figure 2. The interface is SPI compatible and consists of /CS, SEL, SCLK, SDO, and SDI signals.
Waveform Figures 4 – 7 depict the Data Read sequence and Configuration Write sequence for both 8-Bit cycles and also 16
bit “daisy chain” applications.
Power Up Initialization
The DEI1160 incorporates an on-chip power-up reset circuit and power sequencing provisions to force the DIN inputs to the
28V/Open (internal pull down) state upon power. The reset circuit monitors the VCC logic supply and forces the
Configuration Register to the Logic 0 (28V/Open) while VCC is stabilizing. The AFE circuit is designed to present the
28V/Open (internal pull down) condition when VDD supply is present and VCC is below operational voltage.
SEL
/CS
X
SCLK
X
VALID
X
X
DIN[1:8]
X
X
SDI
SDO
DIN8
DIN7
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
DIN inputs latched into DATA S-Reg
Figure 4 Read Data Register
SEL
/CS
X
SCLK
X
VALID
X
X
DIN[1:8]
SI8
SI7
SI6
SI5
SI4
SI3
SI2
SI1
X
X
SDI
DIN8
DIN7
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
SI8
SI7
SI6
SI5
SI4
SI3
SI2
SI1
SDO
DIN inputs latched into DATA S-Reg
SDI data shifted to SDO after 8 bit delay
Figure 5 Read Data Register, 16 Bit Daisy Chain
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SEL
/CS
X
SCLK
X
X
DIN[1:8]
NCD
8
NCD
7
NCD
6
NCD
5
NCD
4
NCD
3
NCD
2
NCD
1
X
X
SDI
PCD
8
PCD
7
PCD
6
PCD
5
PCD
4
PCD
3
PCD
2
PCD
1
NCD
8
SDO
PDO[1:8]
Internal Config Latch
New
Configuration
Present Configuration
NCDn = New Configuration Data Bits
PCDn = Present Configuration Bits
Figure 6 Write Configuration Register
SEL
/CS
SCLK
X
X
X
DIN[1:8]
DCD
8
DCD
7
DCD
6
DCD
5
DCD
4
DCD
3
DCD
2
DCD
1
NCD
8
NCD
7
NCD
6
NCD
5
NCD
4
NCD
3
NCD
2
NCD
1
X
X
SDI
PCD
8
PCD
7
PCD
6
PCD
5
PCD
4
PCD
3
PCD
2
PCD
1
DCD
8
DCD
7
DCD
6
DCD
5
DCD
4
DCD
3
DCD
2
DCD
1
NCD
8
SDO
New
Configuration
PDO[1:8]
Internal
Config
Present Configuration
DCDn = Daisy Chain Data Bits
NCDn = New Configuration Data Bits
PCDn = Present Configuration Bits
Latch
Figure 7 Write Configuration Register, 16 bit Daisy Chain
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LIGHTNING PROTECTION
DINn inputs are designed to survive lightning induced transients as defined by RTCA DO160E, Section 22, Cat A3 and B3,
Waveforms 3, 4, and 5A, Level 3. See waveforms below.
V
V/I
Peak
25% to 75%
of Largest Peak
T1 = 6.4us
T2 = 70us
50%
0
t
50%
F = 1MHZ and 10MHZ
0
t
T1
T2
Figure 8 Voltage / Current Waveform 3
Figure 9 Voltage Waveform 4
V/I
Peak
T1=40us
T2=120us
Waveform Source Impedance characteristics:
x
x
x
Waveform 3 Voc/Isc = 600V / 24A => 25 Ohms
Waveform 4 Voc/Isc = 500 V / 100A => 5 Ohms*
Waveform 5A Voc / Isc = 500V / 500A => 1 Ohm*
*Amplitude tolerances are +20%, -0%.
50%
0
t
T1
T2
Figure 10 Current/Voltage Waveform 5A
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ELECTRICAL DESCRIPTION
Table 3 Absolute Maximum Ratings
PARAMETER
MIN
-0.3
-0.3
MAX
+7.0
18
UNITS
Vcc Supply Voltage
Vdd Supply Voltage
V
V
Operating Temperature
Plastic Package
Storage Temperature
Plastic Package
-55
-55
+125
+150
°C
°C
Input Voltage
DIN[1:8]
Continuous
DO160E, Waveform 3, Level 3
DO160E, Waveform 4 and 5, Level 3+
-10
-600
-600
+49
+600
+600
V
V
V
V
V
V
DO160E, Abnormal Surge Voltage, 100ms
80
Logic Inputs
DOUT
-1.5
-0.5
VCC + 1.5
VCC + 0.5
Power Dissipation @ 125 °C: (> 10 Sec)
16L SOIC
Junction Temperature:
Tjmax, Plastic Packages
ESD per JEDEC A114-A Human Body Model
Logic and Supply pins
0.3
W
°C
V
145
2000
1000
235
DIN pins
Peak Body Temperature (10 sec duration)
°C
Notes:
1. Stresses above absolute maximum ratings may cause permanent damage to the device.
2. Voltages referenced to Ground
Table 4 Recommended Operating Conditions
PARAMETER
Supply Voltage
SYMBOL
CONDITIONS
VCC
VDD
5.0V±10%, 3.3V±10%
15V±10%
Logic Inputs and Outputs
Discrete Inputs
0 to VCC
DIN[1:8]
Ta
0 to 40V
Operating Temperature
Plastic
-55 to +125 ºC
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Table 5 DC Electrical Characteristics
SYMBOL
PARAMETER
CONDITIONS (1)
MIN
LIMITS
NOM
UNIT
MAX
Logic Inputs/Outputs
VIH
HI level input voltage
VCC = 5V
VCC = 3.3V
3.1
2.0
V
VIL
VIhst
LO level input voltage
Input hysteresis voltage,
SCLK input
0.8
V
mV
(3)
50
VOH
HI level output voltage
IOUT = -20uA
VCC
VCC – 0.1
2.4
V
IOUT = -4mA, Vcc = 3V
IOUT = 20uA
IOUT = 4mA, Vcc = 3V
Vin = Vcc or GND
3
V
V
V
VOL
LO level output voltage
0.1
0.4
10
IIN
Input leakage
-10
-10
uA
IOZ
3-state leakage current
Output in Hi Impedance
state.
10
uA
VOUT = VIHmin, VILmax
Discrete Inputs, Configured as Ground/Open (internal pull-up)
VIH
RIH
HI level input voltage
HI level Din-to-GND
resistance
14
50K
49
V
Ohm
Resistor from Din to GND to
guarantee HI input condition.
Vin = 28V, VDD = 15V
IIH
HI level input current
0
1.7
240
uA
mA
V
Vin = 49V, VDD = 15V
VIL
RIL
LO level input voltage
LO level Din-to-GND
resistance
-3
3.5
500
Resistor from Din to GND to
guarantee LO input
condition.
Ohm
IIL
VIhst
LO level input current
Input hysteresis voltage
Vin = 0V, VDD = 15V
-0.9
1
-1.1
-1.25
mA
V
Discrete Inputs, Configured as 28V/Open (internal pull-down)
VIH
IIH
VIL
IIL
HI level input voltage
14
1.1
-3
49
1.75
3.5
V
mA
V
uA
V
HI level input current
LO level input voltage
LO level input current
Input hysteresis voltage
Vin = 28V, VDD = 15V
Vin = 1V, VDD = 15V
1.3
48
100
VIhst
1
Power Supply
Vin(logic) = Vcc or GND
VIN[1:8]= open
Vin(logic) = Vcc or GND
VIN[1:8]= Open
ICC
IDD
Max quiescent logic supply
current
Max quiescent analog
supply current
1
2
6
13.5
25
mA
mA
VIN[1:8]= GND, All
configured as Ground/Open
34
Notes:
1. Ta = -55 to +125 ºC. VDD = +15V±10%, VCC = 3.0 to 5.5V unless otherwise noted.
2. Current flowing into device is positive. Current flowing out of device is negative. Voltages are referenced to
Ground.
3. Guaranteed by design. Not production tested.
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Table 6 AC Electrical Characteristics (4)
SYMBOL
PARAMETER
CONDITIONS
(6, 7)
LIMITS
UNIT
Min
Max
fMAX
tW
tsu1
th1
SCLK frequency. (50% duty cycle) (5) VCC = 3.0V
VCC = 4.5V
8.6
14
MHz
ns
SCLK pulse width. (5)
VCC = 3.0V
VCC = 4.5V
VCC = 3.0V
VCC = 4.5V
VCC = 3.0V
VCC = 4.5V
50
30
25
25
30
20
2
15
25
20
25
20
30
25
25
20
Setup time, SCLK low to /CSĻ.
Hold time, /CSĻ to SCLKĹ.
ns
ns
tsu2
th2
tsu3
Setup time, DIN valid to /CSĻ.
Hold time, /CSĻ to DIN not valid.
Setup time, SDIN valid to SCLKĹ.
us
ns
ns
VCC = 3.0V
VCC = 4.5V
VCC = 3.0V
VCC = 4.5V
VCC = 3.0V
VCC = 4.5V
VCC = 3.0V
VCC = 4.5V
VCC = 3.0V
VCC = 4.5V
VCC = 3.0V
VCC = 4.5V
VCC = 3.0V
VCC = 4.5V
VCC = 3.0V
VCC = 4.5V
th3
tsu4
th4
Hold time, SCLKĹ to SDIN not valid.
Setup time, SEL valid to /CSĻ.
Hold time, SEL valid to /CSĹ.
ns
ns
ns
ns
ns
ns
ns
pf
pf
tp1
Propagation delay, /CSĻ to DOUT
valid. (1)
Propagation delay, SCLKĹ to DOUT
valid. (1)
Propagation delay, /CSĹ to DOUT HI-
Z. (1) (2) (3)
Delay time between /CS active. (5)
105
60
90
50
80
60
tp2
tp3
tp4
20
20
Cin
Cout
Notes:
Maximum logic input pin Capacitance.
(5)
Maximum DOUT pin capacitance,
output in HI-Z state. (5)
10
15
1. DOUT loaded with 50pF to GND.
2. DOUT loaded with 1K Ohms to GND for Hi output, 1K Ohms to VCC for Low output.
3. Timing measured at 25%VCC for “0” to Hi-Z, 75%VCC for “1” to Hi-Z.
4. Sample tested on lot basis.
5. Not tested
6. Ta = -55 to +125ºC. VDD = +15V, VIL = 0V, VIH = VCC unless otherwise noted.
7. Measurements made at 50%VCC.
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th4
tsu4
SEL
/CS
tp4
th1
tsu1
tW
SCLK
DIN[1:8]
1/fmax
tsu2
th2
X
valid
X
tsu3
th3
X
X
valid
SDI
tp2
tp1
tp3
D/C0
D/C1
SDO
Figure 11 Switching Waveforms
ORDERING INFORMATION
Part Number
DEI1160-SES
DEI1160-SMS
Marking
DEI1160 SES
DEI1160 SMS
Package
16 EP SOIC
16 EP SOIC
Burn In
No
Temperature
-55 / +85 ºC
-55 / +125 ºC
No
DEI reserves the right to make changes to any products or specifications herein. DEI makes no warranty, representation, or
guarantee regarding suitability of its products for any particular purpose.
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APPLICATION INFORMATION
The 1160 power dissipation varies with channel configuration and operating conditions. Figure 12 shows the device package
power dissipation for various conditions. This includes the contributions from Supply currents and Input currents. The four
curves are as follows:
Table 7 Legend for Power Dissipation Curves
CURVE ID
+28V/OPN-Nom
+28V/OPN-Wst
CONFIGURATION SUPPLY VOLTAGE
/ TEMPERATURE
PROCESS
CONDITION
Typical
ACTIVE CHANNEL
All channels =
28V/OPN
3.3V, 15V / 27ºC
28V
28V
All channels =
28V/OPN
5.5V, 16.5V/ 125ºC
Worst case
(Low resistance and
fast transistors)
Typical
All channels =
GND/OPN
3.3V, 15V / 27ºC
GND
GND
GND/OPN-Nom
GND/OPN-Wst
All channels =
GND/OPN
5.5V, 16.5V / 125ºC
Worst case
(Low resistance and
fast transistors)
DEI1160 Pwr Dissipation Graph
800
700
600
500
400
300
200
100
0
+28V/OPN-Nom
+28V/OPN-Wst
GND/OPN-Nom
GND/OPN-Wst
0
1
2
3
4
5
6
7
8
Number CH Active
Figure 12 Power Dissipation for Various Conditions
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PACKAGE DESCRIPTION - 16L Narrow Body EP SOIC
Moisture Sensitivity:
MSL 1 / 260ÛC
Ĭja:
~40ÛC/W (Mounted on 4 layer PCB with exposed pad soldered to PCB land with
thermal vias to internal GND plane)
~10ÛC/W
Ĭjc:
Lead Finish:
SnPb plated
Exposed Pad:
Electrically Isolated from IC terminals.
The PCB design and layout is a significant factor in determining thermal resistance (Ĭja) of the IC package. Use maximum
trace width on all power and signal connections at the IC. These traces serve as heat spreaders which improve heat flow from
the IC leads. The exposed heat sink pad of the SOIC package should be soldered to a heat-spreader land pattern on the PCB.
The IC exposed pad is electrically isolated, so the PCB land may be at any potential, typically GND, for the best heat sink.
Maximize the PCB land size by extending it beyond the IC outline if possible. A grid of thermal VIAs, which drop down and
connect to the buried copper plane(s), should be placed under the heat-spreader land. A typical VIA grid is 12mil holes on a
50mil pitch. The barrel is plated to about 1.0 ounce copper. Use as many VIAs as space allows. VIAs should be plugged to
prevent voids being formed between the exposed pad and PCB heat-spreader land due to solder escaping by the capillary
effect. This can be avoided by tenting the VIAs with solder mask.
Figure 13 16 Lead Narrow Body EP SOIC Outline
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