DEI1198 [DEIAZ]
8CH GND/OPEN PARALLEL OUTPUT DISCRETE INTERFACE IC;
| 型号： | DEI1198 |
| 厂家： | 
Device Engineering Incorporated |
| 描述： | 8CH GND/OPEN PARALLEL OUTPUT DISCRETE INTERFACE IC 输出元件 |
| 文件： | 总12页 (文件大小：234K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Device
Engineering
Incorporated
DEI1198
8CH GND/OPEN
PARALLEL OUTPUT
DISCRETE INTERFACE IC
6031 South Maple Avenue
Tempe, AZ 85283
Phone: (480) 303-0822
Fax: (480) 303-0824
E-mail: admin@deiaz.com
FEATURES
·
Eight discrete inputs
o
Senses GND/OPEN discrete signals.
o
Meets input threshold and hysteresis requirements specified per AirBus ABD0100H specification.
§
Thresholds: 4.5 V / 10.5 V, Hysteresis: 3 V
o
o
o
~1 mA DIN source/sink current to prevent dry relay contacts.
Internal isolation diode.
Uses an external 3 kΩ resistor on the inputs to implement lightning transient immunity of 1600 V and
higher. i.e.: DO160E, Section 22, Levels 4 and 5.
o
Inputs protected from Lightning Induced Transients per DO160, Section 22, Cat A3 and B3 plus
waveform 5A to 500 V.
·
Parallel I/O interface
o
o
TTL/CMOS compatible inputs and Tristate outputs
CLK & /OE control inputs and outputs
·
·
·
Logic Supply Voltage (VCC):
Analog Supply Voltage (VDD):
Package Options
3.3 V ±%
12.0 V to 16.5 V
o
o
24 Lead TSSOP
24 Lead TSSOP EP Thermally Enhanced
·
Pin compatible with DEI1166/67
PIN ASSIGNMENTS
Figure 1 DEI1198 Pin Assignment (24 Lead TSSOP)
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FUNCTIONAL DESCRIPTION
DEI1198 is an eight-channel parallel discrete-to-digital interface IC implemented in an HV DIMOS technology. It
senses eight GND/OPEN discrete signals of the type commonly found in avionic systems and converts them to logic
data. The discrete data is read from the device via a parallel tri-state bus.
The discrete input circuits are designed to achieve a high level of lightning transient immunity. The application
design requires a series 3 kΩ resistor on each discrete input to achieve DO160 Level 3 and WF5A 500 V pin injection
immunity. Higher immunity levels can be achieved (i.e. Level 5) with the addition of a TVS between the resistor and
the input pin.
Table 1 Pin Description
PINS
1-8
9-10
11
NAME
DIN[1:8]
NC
DESCRIPTION
Discrete Inputs. Eight GND/OPEN discrete input signals.
Not Connected.
Latch Clock Logic Input. A low level on this input enables
transparent mode. A high level on this input enables latch mode.
Output Enable Logic Input. Low input will enable the tri-state
outputs
CLK
12
/OE
13
14
VDD
GND
Analog Supply Voltage. 12 V to 16.5 V
Logic/Signal Ground
19
VCC
Logic Supply Voltage. 3.3V+/-5%
22
15-18,20-21,23-
24
GND
DO[1:8]
Logic Ground
Logic Outputs. Eight tri-state data outputs
DIN[1:8] Discrete AFE
The Discrete Input Analog Front End circuit function is represented in Figure 3. Each DINn signal is conditioned by
the resistor / diode network and presented to a comparator with hysteresis. The external 3 kΩ resistor is part of
the front end circuitry for achieving threshold and hysteresis requirements while protecting the chip from Lightning
Induced Transients.
Some notable features are:
l
l
The DIN source/sink current is ~1 mA. This current will prevent a “dry” relay contact.
The input voltage and hysteresis:
o
o
o
Low Level:
High Level:
Hysteresis:
-4.0 to +4.5 V
10.5 to 49 V
> 3 V
l
l
Input noise immunity is maximized with a combination of voltage hysteresis and use of a slow input
voltage comparator
The inputs can withstand continuous input voltages of 49 V. The isolation diode breakdown voltage is
greater than 45 V. The 10 kΩ input resistance (consists of a 7 kΩ On-Chip resistor and a 3 kΩ Off-Chip
resistor) is designed to limit diode breakdown current to safe levels during transient events.
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Table 2 Truth Table
CLK /OE DIN[1:8] LATCH[1:8]
DO[1:8]
DESCRIPTION
1
1
X
Open
Ground
X
Hold
HiZ
Output = HiZ, Latch = Hold mode
0
1
X
X
Latch[1:8] <= DIN [1:8]
1
1
0
0
X
Hold
Latch[1:8]
Output = Latched data
X
DIN[1:8]
X
0
1
Latch = Transparent mode
Ground
Open
0
1
0
0
Output = Live data
Legend:
X = don’t care input or undefined output
HiZ = Hi Impedance
Figure 2 Function Block Diagram (two channels shown)
Figure 3 Analog Front End Detail
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LIGHTNING PROTECTION
DINn inputs are designed to survive lightning induced transients as defined by RTCA DO160, Section 22, Cat A3 and
B3, pin injection Waveforms 3, 4, and 5A. They can withstand Level 3 stress (and WF5A up to 500 V) with the external
3 kΩ series resistor for current limiting.
Protection for higher stress levels can be achieved (for example: the 3200 V of WF3 Level 5) with the addition of
transient voltage suppressor (TVS) devices at the DINn pins. First select the TVS clamp voltage < 450 V (the intrinsic
1198 device capability). A convenient value would be 48 V, which reduces the TVS capacitance to the lowest
practicable level. The 3 kΩ series resistor limits the TVS surge current, thus allowing small low power TVS devices.
V/I
V
25% to 75%
Peak
of Largest Peak
T1 = 6.4 us
T2 = 70 us
50%
0
t
50%
F = 1 MHZ
0
t
T1
T2
Figure 4 Voltage/Current Waveform 3
Figure 5: Voltage/Current Waveform 4
V/I
Peak
T1=40 us
T2=120 us
Waveform Source Impedance characteristics:
·
·
·
·
Waveform 3 Voc/Isc = 600 V / 24 A => 25 Ω
Waveform 4 Voc/Isc = 300 V / 60 A => 5 Ω
Waveform 5A Voc / Isc = 300 V / 300 A => 1 Ω
Waveform 5A Voc / Isc = 500 V / 500 A => 1 Ω
50%
0
t
T1
T2
Figure 6 Voltage/Current Waveform 5A
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ELECTRICAL DESCRIPTION
Table 3 Absolute Maximum Ratings
PARAMETER
MIN
-0.3
-0.3
MAX
+5.0
18
UNITS
VCC Supply Voltage
VDD Supply Voltage
V
V
Operating Temperature
1198-TES-G
-55
-55
+85
+125
°C
°C
1198-TMS-G
Storage Temperature
Plastic Package
-55
+150
°C
Input Voltage (3)(4)
DIN[1:8]
Continuous
-10
+49
+600
+300
+500
80
V
V
V
V
V
DO160, Waveform 3, Level 3
-600
-300
-500
DO160, Waveform 4 and 5, Level 3
DO160, Waveform 4 and 5
DO160, Abnormal Surge Voltage, 100ms
Logic Inputs
DOUT
-1.5
-0.5
VCC + 1.5
VCC + 0.5
0.8
V
V
W
W
Power Dissipation @ 85 °C steady state, 1198-TES-G
Power Dissipation @ 125 °C steady state, 1198-TMS-G
Junction Temperature:
0.8
Tjmax
145
°C
ESD per JEDEC A114 Human Body Model
Logic and Supply pins
2000
1000
V
DIN pins
Peak Body Temperature (10 sec duration)
260
°C
Notes:
1. Stresses above absolute maximum ratings may cause permanent damage to the device.
2. Voltages referenced to Ground
3. Stress applied to external 3 kΩ series resistor in series with DINn pin.
4. Discrete input voltage amplitude tolerance for WF3, 4 and 5 are +20% / -0%
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Table 4 Recommended Operating Conditions
PARAMETER
SYMBOL
CONDITIONS
Supply Voltage
VCC
VDD
3.3 V ±5%
12.0 V to 16.5 V
Logic Inputs and Outputs
Discrete Inputs
Operating Temperature
1198-TES-G
0 to VCC
0 to 49 V
DIN[1:8]
Ta
-55 to +85 °C
1198-TMS-G
-55 to +125 °C
Table 5 DC Electrical Characteristics
SYMOBL
PARAMETER
CONDITIONS (1)(2)
LIMITS
UNIT
MIN
2.0
NOM
MAX
Logic Inputs/Outputs
V1IH
V1IL
VOH
HI level input voltage
V
VCC = 3.3 V
LO level input voltage
HI level output voltage
0.8
V
V
I_DOUT = -20 uA
I_DOUT = -4 mA,
VCC = 3V
I_DOUT = 20 uA
I_DOUT = 4 mA,
VCC = 3 V
VCC – 0.1
2.4
V
V
V
VOL
LO level output voltage
0.1
0.4
IIN
Input leakage
VIN = VCC
VIN = GND
Output in Hi Impedance
state.
-10
-35
10
0
uA
uA
IOZ
3-state leakage current
-10
10
DOUT = VIHmin, VILmax
Discrete Inputs (4)
V2IH
RIH
HI level input voltage
10.5
50
49
V
HI level DIN-to-GND
resistance
Resistor from DIN to GND
to guarantee HI input
condition.
kΩ
IIH
HI level input current
DIN = 28 V, VDD = 15 V
DIN = 49 V, VDD = 15 V
1
1
240
2
uA
mA
V2IL
RIL
LO level input voltage
LO level DIN-to-GND
resistance
-4.0
4.5
500
-1.8
V
Resistor from DIN to GND
to guarantee LO input
condition.
Ω
IIL
VIhst
LO level input current
Input hysteresis voltage
DIN = 0V, VDD = 15V
-0.8
3
-1.3
1.8
mA
V
Power Supply
VIN(logic) = VCC or GND
DIN[1:8]= open
ICC
Max quiescent logic
supply current
mA
3
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SYMOBL
PARAMETER
CONDITIONS (1)(2)
LIMITS
UNIT
MIN
NOM
MAX
IDD
Max quiescent analog
supply current
VIN(logic) = VCC or GND
DIN[1:8]= Open
15
24
mA
DIN[1:8]= GND
22
33
Notes:
1. Ta = -55 to +85/+125 °C. VDD = 12.0 to 16.5 V, VCC = 3.3 V ±5% unless otherwise noted
2. Current flowing into device is ‘+’. Current flowing out of device is ‘- ‘. Voltages are referenced to Ground
3. Guaranteed by design. Not production tested
4. With 3 kΩ, 2% resistor in series with DIN input pin
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Table 6 AC Electrical Characteristics
LIMITS
CONDITIONS
(1,2)
CLK = /OE = 0
SYMOBL
PARAMETER
Propagation delay,
UNIT
MIN
MAX
550
tHL
tLH
ns
DIN to DO. (3)
tHZ
tLZ
Output disable delay, /OE↑ to DO HI-Z.
(4)(5)
Output Enable delay, /OE↓ to DO active.
(4)(5)
50
50
ns
ns
tZH
tZL
tSU
tH
Cin
Cout
DIN setup time, DIN to CLK↓ (6)
DIN hold time, DIN to CLK↑ (6)
Logic input pin Capacitance. (7)
DOUT pin capacitance, output in HI-Z state.
(7)
550
ns
ns
pf
pf
10
10
15
Notes:
1. DOUT loaded with 50 pF to GND.
2. Ta = -55 to +85/+125 °C. VDD = 12 V, VCC = 3 V. VIL = 0 V, VIH = VCC unless otherwise noted.
3. Timing measured from DO = 1.5 V to VDIN = 9 V (Rising Edge) / 4.5 V (Falling Edge). See Figure 7.
4. DOUT loaded with 1 kΩ to GND for Hi output, 1 kΩ to VCC for Low output.
5. Timing measured from /OE=1.5 V to DO=200 mV. See Figure 7.
6. Timing measured from CLK = 1.5 V to VDIN = 9 V (Rising Edge) / 4.5 V (Falling Edge). See Figure 7.
7. Not production tested. Guaranteed by design.
8. AC characteristics are sample tested on lot basis.
TIMING DIAGRAMS
3.0
DIN
9
1.5
CLK
4.5
0
tHL
tSU
tLH
HI
HI
tH
DO
9
1.5
DIN
4.5
0
3.0
3.0
1.5
1.5
1.5
OE
OE
0
0
tZH
tHZ
HIGH Z
tZL
tLZ
HIGH Z
HI
0.2
DO
DO
1.3
1.3
0.2
HIGH Z
LO
HIGH Z
Figure 7 Switching Waveforms
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APPLICATION INFORMATION
Discrete Input Filtering
The DEI1198 Analog Front End provides a moderate level of noise immunity via a combination of hysteresis and
limited bandwidth. The Hysteresis is 3 V minimum, and the comparator bandwidth is approximately 10 MHZ.
Many applications provide additional noise immunity by means of debounce/filtering in software or in digital
circuitry (i.e. FPGA). Common input debounce techniques are readily found with a web search of the term “software
debounce” and range from simple detectors of two or more sequential stable readings to FIR filters emulating RC
time constants.
Input Current Characteristics
The DIN Input Current vs. Voltage characteristics are shown in Figure 8.
Figure 8 Input IV Characteristics (VDD = 15 V)
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Package Power Dissipation
The DEI1198 power dissipation varies with operating conditions. Figure 9 shows the device package power
dissipation for various operating conditions. This includes the contributions from Supply currents and DIN Input
currents. The curves are as follows:
Table 7 Legend for Power Dissipation Curves
SUPPLY VOLTAGE, TEMPERATURE,
CURVE ID
IC VARIATION
GND/OPEN-Nom
3.3 V, 12 V / 27 °C / typical IC parameters
GND/OPEN-Wst
3.3 V, 16.5 V / 85 °C /
Worst case IC parameters
800
700
600
500
400
300
200
100
0
GND/OPN-Nom
GND/OPN-Wst
0
1
2
3
4
5
6
7
8
Number CH Active
Number of Active Channels
Figure 9 DEI1198 Power Dissipation vs Active Channels
ORDERING INFORMATION
Table 8 Ordering Information
PART NUMBER
DEI1198-TES-G
DEI1198-TMS-G
MARKING
DEI1198-TES
DEI1198-TMS
PACKAGE
24 TSSOP G
24 TSSOP EP G
TEMPERATURE
-55 / +85 °C
-55 / +125 °C
DEI reserves the right to make changes to any products or specifications herein. DEI makes no warranty, representation,
or guarantee regarding suitability of its products for any particular purpose.
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PACKAGE DESCRIPTIONS
Table 9 Package Information
CHARACTERISTIC
Moisture Sensitivity
Lead Finish
Materials
JEDEC Reference
Thermal Resistance (°C/W)
25TSSOP G
MSL 1 / 260 °C
NiPdAu
RoHS Compliant
MO-153-AD
24TSSOP EP G
MSL 3 / 260 °C
100% Matte Sn
RoHS Compliant
MO-153-AD
Θja:
Θjc:
~84
~16
~29
~7
The PCB design and layout are a significant factor in determining thermal resistance (Θja) of the IC package. Use
maximum trace width on all power and signal connections at the IC. These traces serve as heat spreaders which
improve heat flow from the IC leads.
The exposed thermal pad of the 24TSSOP EP G package must be soldered to a heat spreader land pattern on the
PCB to achieve required thermal performance.
·
·
·
Connect the exposed thermal pad to electrical Ground.
Use large and multi-layer PCB boards, at least 4 layers 3” x 3”, with internal solid GND and Power planes.
Maximize the thermal pad land size by extending it beyond the IC to form a dog-bone pattern on the top
layer and a similar sized heat spreader copper pattern on the bottom layer.
·
Use thermal VIAs to connect the thermal pad land pattern on the top layer, inter GND(s) and bottom GND
layer. Place as many thermal VIA’s in the land pattern as space allows to conduct heat from the thermal
pad to the internal ground plane and bottom heat spreader.
Figure 10 24 TSSOP G Outline
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Thermal
Pad
SYMBOLS
MIN
--
NOM
--
--
1.00
--
7.80
4.40
6.40 BSC
0.65 BSC
1.00 REF
0.60
--
MAX
1.20
0.15
1.05
0.30
7.90
4.50
A1
A2
b
D
E1
E
0.00
0.80
0.19
7.70
4.30
L1
L
S
0.45
0.20
0 °
0.75
--
8 °
--
E2
D1
2.28
3.70
--
--
3.00
4.75
Figure 11 24 TSSOP EP G Outline
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