DEI1282-SMS-G [DEIAZ]
8CH BIT PROGRAMMABLE GND/OPN & 28V/OPN DISCRETE INTERFACE IC;
| 型号： | DEI1282-SMS-G |
| 厂家： | 
Device Engineering Incorporated |
| 描述： | 8CH BIT PROGRAMMABLE GND/OPN & 28V/OPN DISCRETE INTERFACE IC 光电二极管 接口集成电路 |
| 文件： | 总17页 (文件大小：992K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DEI1282, 1284
Device
Engineering
Incorporated
8CH BIT PROGRAMMABLE
GND/OPN & 28V/OPN
DISCRETE INTERFACE IC
385 East Alamo Drive
Chandler, AZ 85225
Phone: (480) 303-0822
Fax: (480) 303-0824
E-mail: admin@deiaz.com
FEATURES
·
Eight discrete inputs
o
o
Individually configurable as either GND/OPEN or 28V/OPEN(GND) inputs.
Input threshold and hysteresis per AirBus ABD0100H specification.
§
§
GND/OPEN mode: 4.5V/10.5V threshold, 3V hysteresis
28V/OPEN mode: 6V/12V threshold, 3V hysteresis
o
o
o
o
o
o
1mA input current to prevent dry relay contacts.
Internal isolation diodes
Inputs protected from Lightning Induced Transients per DO160F, Section 22, Cat A3 and B3
1284 version supports higher lightning levels and input filtering via use of off-chip input resistors
Withstands inadvertent application of 115VAC/400Hz power
Built-in Test (BIT) to test internal circuits including input comparator
·
Serial I/O interface to read data register and write configuration register
o
o
o
o
Direct interface to Serial Peripheral Interface (SPI) port.
TTL/CMOS compatible inputs and Tristate output
8.6MHz Max Data Rate
Serial input to expand Shift Register
·
·
·
Logic Supply Voltage (VCC):
Analog Supply Voltage (VDD):
16L SOIC EP package
3.3V +/-5%
12V to 16.5V
PIN ASSIGNMENTS
1
16
VDD
GND
VCC
SEL
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
DEI
1282
&
1284
SDI
/CS
SCLK
SDO
Figure 1 DEI1282, 1284 Pin Assignment (16 Lead SOIC)
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FUNCTIONAL DESCRIPTION
DEI1282 and DEI1284 are eight-channel discrete-to-digital interface ICs implemented in a High Voltage Dielectric Isolated
technology. They sense eight discrete signals of the type commonly found in avionic systems and convert them to serial logic
data. Each input can be individually configured as either GND/OPEN or 28V/OPEN format input via a serial data input. The
discrete data is read from the device via an eight-bit serial shift register with 3-state output. This serial interface is compatible
with the industry standard Serial Peripheral Interface (SPI) bus.
The discrete inputs are implemented with a high voltage technology to provide immunity to lightning induced transients. The
DEI1282 tolerates DO160F Level 3 (600V) stress directly to the input pins without the need for additional protection
components.
The DEI1284 version operates with 3K Ohm off-chip series resistors on the inputs. These are used in combination with
Transient Voltage Suppressor (TVS) devices to achieve Level 4 (1500V) and Level 5 (3200V) immunity. The resistors act to
limit surge current, thus allowing small TVS devices. The resistors are also used to implement low pass filtering by adding
capacitors on the inputs. The filtering provides noise rejection and anti-aliasing of the sampled signal.
The on-chip Built-in Test (BIT) feature provides a Test Mode which provides a means to inject a test signal into each input
comparator without interfering with the discrete input signals. The test coverage includes each DIN comparator as well as the
digital logic and IO.
Table 1 Pin Descriptions
PINS
NAME
DESCRIPTION
1-8
DIN[1:8]
Discrete Inputs. Eight discrete signals which can be individually
configured as either GND/OPEN or 28V/OPEN format inputs.
Logic Output. Serial Data Output. This pin is the output from MSB (Bit
8) of the selected shift register (Data/Configuration). It is clocked by the
rising edge of SCLK. This is a 3-state output enabled by /CS.
Logic Input. Serial Shift Clock. A low-to-high transition on this input
shifts data on the serial data input into Bit 0 of the selected shift register.
The selected shift register is shifted from Bit 1 to Bit 8. Bit 8 of the
selected shift register is driven on SDO.
9
SDO
10
SCLK
11
/CS
Logic Input. Chip Select. A low level on this input enables the SDO 3-
state output and the selected shift register. A high level on this input
forces SDO to the high impedance state and disables the shift registers so
SCLK transitions have no effect. When the Data Register is selected, a
high-to-low transition causes the Discrete Input data to be loaded into the
Data Register. When the Configuration Register is selected, a low-to-
high transition causes the Serial Configuration Register data to be loaded
into the parallel configuration outputs.
12
13
SDI
Logic Input. Serial Data Input. Data on this input is shifted into the LSB
(Bit 1) of the selected shift register on the rising edge of the SCLK when
/CS input is low.
Logic Input. Selects between the Data Register and Configuration
Register. H = DATA, L = CONF.
SEL
14
15
16
VCC
GND
VDD
Logic Supply Voltage. 3.3V+/-5%
Logic/Signal Ground
Analog Supply Voltage. 12V to 16.5V
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Figure 2 Function Diagram
Figure 3 Discrete AFE Function Diagram
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Table 2 Truth Table
Serial Interface Operation
SEL
X
H
/CS SCLK
SDI
X
X
DIN[1:8]
SDO
HI Z
DIN[8]
DR[8]
Description
Not Selected
DR[1:8]← DIN[1:8]
H
↓
X
L
↑
X
Valid
X
H
L
DR[1]
DR[n+1] ← DR[n], DR[1] ← SDI
L
L
L
↑
↑
L
CR[1]
X
X
X
CR[8]
HI Z
CR[n+1] ← CR[n], CR[1] ← SDI
CL[1:8]← CR[1:8]
Legend:
DR = Data Register
CR = Configuration Register
CL = Configuration Latch
X = Don’t Care
DIN [1:8] Discrete AFE
The Discrete Input Analog Front End circuit function is represented in Figure 3. Each DINn signal is conditioned by the
resistor / diode network and presented to a comparator with hysteresis. When the input is configured for GND/OPEN
operation, the pull-up resistor and diode are enabled and comparator threshold voltage is selected. When the input is
configured for 28V/OPEN operation, the pull-down resistor is enabled and the comparator is appropriately configured. Prior to
configuration (after power up) and during BIT, neither pull-up nor pull-down is enabled and the AFE presents a high
impedance (Hi-Z).
Some notable features are:
·
Input voltage levels and hysteresis:
o
28V/OPEN
·
·
·
High level input voltage:
Low level input voltage:
Hysteresis:
12.0 to 49 V
-4 to 6.0 V
> 3 V
o
GND/OPEN
·
·
·
High level input voltage:
Low level input voltage:
Hysteresis:
10.5 to 49 V
-4 to 4.5 V
> 3 V
·
·
The input current is ~ 1mA. This current will prevent a “dry” relay contact.
Input noise immunity is maximized with a combination of voltage hysteresis and use of a slow input voltage
comparator.
·
The inputs can withstand continuous input voltages of 49V, lightning transient voltages per DO160 Level 3 pin
injection tests, and survive inadvertent application of 115VAC/400Hz.
Data Register
The 8-bit Data Register is a “parallel-input, serial-output” register that samples the input channels and reads-out the data to the
Serial Data Output. The register is read via the SDO output as described in Figure 4 and Figure 5. A low DIN input level
results in a Logic 0, and a high input level results in a Logic 1.
Configuration Register
The 9-bit Configuration Register (CR) is a “serial-input, parallel-output with data latch” register that individually configures
each AFE input as either GND/OPEN or 28V/OPEN format. (CR[n]: 0 sets DIN[n] to 28V/OPEN mode (pull-down); CR[n]: 1
sets DIN[n] to GND/OPEN mode (pull-up). The register is reset to 0’s at Power Up and the AFE inputs are forced into high
impedance mode until the CR is programmed (see Power Up Initialization). Bit 9 is used to enable or disable Built-in Test (see
BIT Operation). The register is programmed via the serial data input as described in Figures 6– 8.
Serial Interface
The DEI1282/1284 incorporates a serial IO interface for programming the Discrete Input configuration and for reading the
Discrete Input status. Refer to Figure 2. The interface is SPI Mode 0 compatible and consists of /CS, SEL, SCLK, SDO, and
SDI signals. Figures 4 – 5 depict the Data Read sequence and Configuration Write sequence for both a single device and dual
“daisy chained” devices; refer to Figure 16 for connection details.
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Power Up Initialization
The DEI1282/1284 incorporates an on-chip power-up reset (POR) circuit and logic to force the DIN inputs to a high
impedance state at power up; the AFE pull-up and pull-down circuits are disabled. POR monitors the Vcc logic supply and
forces the AFE to the high impedance state while Vcc is stabilizing. It remains high impedance until the Configuration Register
is programmed by the first Write Configuration Register cycle when the pull-up or pull-down state is defined.
The POR rising Vcc threshold is ~2.5V with ~0.4V of hysteresis. The POR includes a ~200us delay from the Vcc threshold to
reset output; the Configuration Register ignores attempts to program it during this POR delay time.
The POR will reset when there is sufficient voltage sag on Vcc. When Vcc drops below ~2.0V for ~9us, POR will activate, the
Configuration and Data Registers will reset to “0”, and the AFEs (DIN’s) are set to Hi-Z.
The part may be intentionally operated in the non-configured Hi-Z mode in order to read the inputs without presenting a pull-
up or pull-down load. Hi-Z mode is only accessible after POR and before the device configuration register is programmed. In
Hi-Z mode, the input thresholds are approximately:
VTLH = low to high threshold = ~14V
VTHL = high to low threshold = ~11V
BIT Operation
Bit 9 of the Configuration Register (CR) is used to enable or disable Built-in Test (1 = BIT enabled, 0 = NORMAL). When
BIT is enabled, each channel configuration bit value is used to drive a test stimulus on the respective channel comparator (see
Figure 3). Thus all channels can be tested by setting the BIT mode, programming test stimulus patterns into the CR, and
reading the results from the DR. The DIN inputs are placed in Hi-Impedance mode (pull up and pull down switches are OFF)
during test mode, so the test does not interfere with the DIN signals. The BIT test stimulus is isolated from the DIN pin by
680KW.
If a DINn input voltage is stuck within the input hysteresis voltage range during the time when the CR is programmed from
BIT to NORMAL mode and the DINn value read via a Read DR cycle, then the corresponding DINn bit will be reported as the
last BIT test value programmed in the CR BIT command.
SEL
/CS
X
X
SCLK
X
X
VALID
X
DIN[1:8]
SDI
SDO
DIN8
DIN7
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
DIN Data Shifted out from DATA S-Reg at SCLK
DIN inputs latched into DATA S-Reg at /CS ¯
Figure 4 Read Data Register
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SEL
/CS
SCLK
SDI
SDO
SDI datashifted to SDO after 8 bit delay
Figure 5 Read Data Register, 16 Bit Daisy Chain (See Figure 18)
SEL
/CS
X
SCLK
X
X
DIN[1:8]
NCD
9
NCD
8
NCD
7
NCD
6
NCD
5
NCD
4
NCD
3
NCD
2
NCD
1
X
X
SDI
PCD
9
PCD
8
PCD
7
PCD
6
PCD
5
PCD
4
PCD
3
PCD
2
PCD
1
NCD
9
SDO
New
Configuration
PDO[1:9]
Internal Config Latch
Present Configuration
NCDn = New Configuration Data Bits
PCDn = Present Configuration Data Bits
Figure 6 Write Configuration Register (9-bit cycle)
SEL
/CS
SCLK
X
DIN[1:8]
NCD
9
NCD
8
NCD
7
NCD
6
NCD
5
NCD
4
NCD
3
NCD
2
NCD
1
X
X
X
X
X
X
X
X
X
SDI
PCD
9
PCD
8
PCD
7
PCD
6
PCD
5
PCD
4
PCD
3
PCD
2
PCD
1
NCD
9
X
X
X
X
X
X
X
SDO
New
Configuration
PDO[1:8]
Internal
Config
Present Configuration
X
DCDn = Daisy Chain Data Bits
NCDn = New Configuration Data Bits
PCDn = Present Configuration Bits
Latch
NCD 9 latched into Config S-Reg at SCLK
Figure 7 Write Configuration Register (16-bit cycle)
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SEL
/CS
X
SCLK
X
DIN[1:8]
X
DCD
9
DCD
8
DCD
7
DCD
6
DCD
5
DCD
4
DCD
3
DCD
2
DCD
1
NCD
9
NCD
8
NCD
7
NCD
6
NCD
5
NCD
4
NCD
3
NCD
2
NCD
1
X
X
SDI
PCD PCD
PCD
7
PCD
6
PCD
5
PCD
4
PCD
3
PCD
2
PCD
1
DCD
9
DCD
8
DCD
7
DCD
6
DCD
5
DCD
4
DCD
3
DCD
2
DCD
1
NCD
9
SDO
9
8
New
Config
PDO[1:8]
Internal
Config
Present Configuration
Figure 8 Write Configuration Register, 18 bit Daisy Chain (See Figure 18)
DCDn= Daisy Chain Data Bits
NCDn= New Configuration Data Bits
PCDn= Present Configuration Data Bits
Latch
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LIGHTNING TRANSIENT IMMUNITY
The DIN inputs are designed to survive lightning induced transients as defined by RTCA DO160F, Section 22, Cat A3 and
B3, Waveforms 3, 4 and 5A, Level 3. The DEI1282 withstands this stress applied directly to the DIN pins. Contact
factory for lightning test report.
The DEI1284 withstands Level 3 stress applied to the 3K Ohm series resistor in series with DINn pins. Insert a Transient
Voltage Suppressor (48V bidirectional TVS) to ground on the DIN pin to implement higher immunity levels (i.e. Level 4
(1500V) or Level 5 (3200V)), see Figure 12. The 3K Ohm resistor limits surge current, thus allowing use of small TVS
devices.
V
V/I
Peak
25% to 75%
of Largest Peak
T1 = 6.4us
T2 = 70us
50%
0
t
50%
F = 1MHZ and 10MHZ
0
t
T1
T2
Figure 9 Voltage / Current Waveform 3
Figure 10 Voltage Waveform 4
V/I
Peak
T1=40us
T2=120us
Waveform Source Impedance characteristics:
·
·
·
·
Waveform 3 Voc/Isc = 600V / 24A => 25 W
Waveform 4 Voc/Isc = 300 V / 60 A => 5 W
Waveform 5A Voc / Isc = 300V / 300A => 1 W
Waveform 5A Voc / Isc = 500V / 500A => 1 W
50%
0
t
T1
T2
Figure 11 Voltage / Current Waveform 5A
INADVERTENT SHORT TO 115VAC POWER
The DIN inputs can withstand inadvertent shorts to 115VAC/400Hz aircraft power.
Contact factory for test report.
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ELECTRICAL DESCRIPTION
Table 3 Absolute Maximum Ratings
PARAMETER
MIN
MAX
UNITS
VCC Supply Voltage
-0.3
-0.3
+5.0
18
V
V
VDD Supply Voltage
Operating Temperature
Exposed pad soldered to heat sink
Storage Temperature
Plastic Package
-55
-55
+125
+150
°C
°C
Input Voltage
DIN[1:8]
Continuous
DO160F, Waveform 3, Level 3
DO160F, Waveform 4 and 5, Level 3
DO160F, Abnormal Surge Voltage, 100ms
(3)
(3)
(3)
(3)
-10
-600
-300
+49
+600
+300
Vdc
Vpk
Vpk
Vpk
V
80
Logic Inputs
DOUT
-1.5
-0.5
VCC + 1.5
VCC + 0.5
V
Power Dissipation @ 125°C, Steady state
16L SOIC
Junction Temperature:
Tjmax, Plastic Packages
ESD per JEDEC A114-A Human Body Model
Logic and Supply pins
0.63
150
W
°C
2000
1000
V
V
DIN pins
Peak Body Temperature (10 sec duration)
Notes:
260
°C
1. Stresses above absolute maximum ratings may cause permanent damage to the device.
2. Voltages referenced to Ground.
3. Stress applied to external 3K Ohm series resistor in series with DINn pin. Applies to DEI1284 only.
Table 4 Recommended Operating Conditions
PARAMETER
SYMBOL
CONDITIONS
VCC
VDD
3.3V±5%
12V to 16.5V
Supply Voltage
Logic Inputs and Outputs
Discrete Inputs
0 to VCC
0 to 49V
DIN[1:8]
Ta
Operating Temperature
Plastic
-55ºC to 125ºC
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Table 5 DC Electrical Characteristics
CONDITIONS (1) MIN
SYMBOL PARAMETER
NOM
MAX
UNIT
LIMIT
LIMIT
Logic Inputs/Outputs
VIH
VIL
HI level input voltage
VCC = 3.3V
VCC = 3.3V
2.0
V
V
LO level input voltage
Input hysteresis voltage,
SCLK input
0.8
VIhst
(3)
50
mV
IOUT = -20uA
VCC – 0.1
2.4
V
VOH
HI level output voltage
IOUT = -4mA, VCC = 3V
IOUT = 20uA
IOUT = 4mA, VCC = 3V
V
V
V
0.1
0.4
10
VOL
IIN
LO level output voltage
Input leakage, except SEL VIN = VCC
or GND
-10
uA
IIN-SEL
IOZ
Input leakage, SEL
VIN = VCC
VIN = GND
Output in Hi Impedance state.
VOUT = VIHmin, VILmax
-10
-50
10
10
uA
uA
3-state leakage current
-10
10
Discrete Inputs, Configured as Ground/Open (internal pull-up) (4)
10.5
49
V
VIH
RIH
HI level input voltage
HI level DIN-to-GND
resistance
Resistor from DIN to GND to
guarantee HI input condition.
VIN = 28V, VDD = 15V
VIN = 49V, VDD = 15V
50K
W
17
45
100
250
4.5
uA
uA
V
IIH
VIL
RIL
HI level input current
-4.0
LO level input voltage
LO level DIN-to-GND
resistance
LO level input current
Input hysteresis voltage
Resistor from DIN to GND to
guarantee LO input condition.
VIN = 0V, VDD = 15V
500
-1.8
W
-0.8
3
-1.0
mA
V
IIL
VIhst
Discrete Inputs, Configured as 28V/Open (internal pull-down) (4)
VIH
IIH
VIL
IIL
HI level input voltage
12.0
0.6
-4
49
1.35
6.0
50
V
mA
V
uA
V
HI level input current
LO level input voltage
LO level input current
Input hysteresis voltage
VIN = 28V, VDD = 15V
VIN = 1V, VDD = 15V
0.8
VIhst
3
Power Supply
VIN(logic) = VCC or GND
VIN[1:8] = open
VIN(logic) = VCC or GND
Ground/Open Mode,
VIN[1:8] = Open
Max quiescent logic
supply current
ICC
IDD
1.8
3
mA
mA
Max quiescent analog
supply current
15
22
24
33
VIN[1:8] = GND
Notes:
1. Unless otherwise noted: Ta = -55ºC to 85/125ºC (-SES/-SMS). VDD = 12V to 16.5V. VCC = 3.3V+/-5%.
2. Current flowing into device is ‘+’. Current flowing out of device is ‘-‘. Voltages are referenced to Ground.
3. Guaranteed by design. Not production tested.
4. With 3K Ohm, 2% resistor in series with DIN input pin. Applies to DEI1284 only.
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Table 6 AC Electrical Characteristics
CONDITIONS (5,6,7)
MIN
LIMIT LIMIT
MAX
SYMBOL PARAMETER
UNIT
SCLK frequency.
SCLK pulse width.
50% duty cycle
fMAX
0.1
8.6
MHz
tW
tsu1
th1
tsu2
th2
tsu3
th3
tsu4
th4
tp1
tp2
tp3
tp4
50
30
25
15
500
25
25
30
25
ns
ns
ns
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
Setup time, SCLK to /CS↓.
Hold time, /CS↓ to SCLK.
Setup time, DIN valid to /CS↓.
Hold time, /CS↓ to DIN not valid.
Setup time, SDIN valid to SCLK↑.
Hold time, SCLK↑ to SDIN not valid.
Setup time, SEL valid to /CS↓.
Hold time, SEL valid to /CS↑.
Propagation delay, /CS↓ to DOUT valid.
Propagation delay, SCLK↑ to DOUT valid.
Propagation delay, /CS↑ to DOUT HI-Z.
Delay time between /CS active.
Hold time, SCLK↑ to DOUT
Maximum logic input pin Capacitance.
Maximum SDO pin capacitance, output in HI-Z state.
(1)
(1)
(1) (2) (3)
105
90
80
20
10
th5
Cin
Cout
(1)
10
15
Notes:
1. SDO loaded with 50pF to GND.
2. SDO loaded with 1KW to GND for Hi output, 1KW to VCC for Low output.
3. Timing measured at 25%VCC for “0” to Hi-Z, 75%VCC for “1” to Hi-Z.
4. Sample tested on lot basis.
5. Guaranteed by design. Not production tested.
6. Ta = -55ºC to 85 or 125ºC, VCC = 3V, VDD = 15V, VIL = 0V, VIH = VCC unless otherwise noted.
7. Measurements made at 50%VCC.
tsu4
th4
SEL
/CS
tp4
th1
tW
tsu1
SCLK
DIN[1:8]
1/fmax
tsu2
th2
valid
X
X
tsu3
th3
X
X
valid
SDI
tp1
tp3
D/C0
th5
D/C1
SDO
tp2
Figure 12 Switching Waveforms
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APPLICATION INFORMATION
Discrete Input Filtering
The DEI1282/84 Analog Front End provides a moderate level of noise immunity via a combination of hysteresis and limited
bandwidth. The Hysteresis is 3V minimum and the comparator bandwidth is approximately 10MHz. A capacitor may be
installed in parallel with a TVS on the DEI1284 DIN pin to provide additional noise filtering.
Figure 13 DEI1284 DIN with Filter Cap and TVS on DIN input.
Applications may require additional noise immunity by means of debounce/filtering in software or in digital circuitry (i.e.:
FPGA). Common input debounce techniques are readily found with a web search of the term “software debounce” and range
from simple detectors of two or more sequential stable readings to FIR filters emulating RC time constants.
Input Current Characteristics
Figures 14-17 depicts the DIN Input Current vs. Voltage characteristics for the various operating and non-operating modes.
Measurements are at Room temperature.
Figure 14 28V/Open Mode Input IV Characteristics (VDD = 15V)
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Figure 15 GND/OPEN Mode Input IV Characteristics (VDD = 15V)
Figure 16 Hi-Z (Un-configured and BIT) Mode Input IV Characteristics (VDD = 15V)
Figure 17 VDD = VCC= GND and VDD = VCC = Open Input IV Characteristics
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Daisy Chain Connection
Multiple DEI1282/1284 ICs can be connected as daisy chain. Figure 16 shows three devices connected in SPI series mode.
The critical timing is Tsu3 (see Fig 12), minimum SDIN valid to SCLK setup time.
Figure 18 Example connection of three DEI128X’s connected as daisy chain
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Package Power Dissipation
The DEI1282/84 power dissipation varies with channel configuration and operating conditions. Figure 18 shows the device
package power dissipation for various conditions. This includes the contributions from Supply currents and Input currents.
The four curves are as follows:
Table 7 Legend for Power Dissipation Curves
SUPPLY VOLTAGE, TEMPERATURE,
CURVE ID
IC VARIATION
+28V/OPEN-Nom
3.3V, 12V / 27ºC / typical IC parameters
+28V/OPEN-Wst
GND/OPEN-Nom
GND/OPEN-Wst
3.3V, 16.5V / 125ºC /
Worst case IC parameters
3.3V, 12V / 27ºC / typical IC parameters
3.3V, 16.5V / 125ºC /
Worst case IC parameters
DEI1282 Power Dissipation Graph
800
700
600
500
400
300
200
100
0
+28V/OPN-Nom
+28V/OPN-Wst
GND/OPN-Nom
GND/OPN-Wst
0
1
2
3
4
5
6
7
8
Number Channels Active
Notes:
1. The active channels are forced to Ground for GND/OPEN type and forced to 28V for 28V/OPEN type.
2. The DEI1284 package power dissipation is lower than the DEI1282 because a portion of the power is shifted to the
external resistors. The DEI1284 incremental Pd is ~20% lower for GND/OPEN and ~15% lower for 28V/OPEN.
Figure 19 Power Dissipation for Various Conditions
©2018 Device Engineering Inc.
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PACKAGE DESCRIPTION - 16L Narrow Body, Exposed Pad SOIC
Table 8 Package Information
JEDEC
Θjc/ Θja
(°C/W)
/1
Lead Finish /
JEDEC Pb-Free
Code
Moisture
Sensitivity
Level
Pb Free
Designation
JEDEC
MO
Package Type
Package Ref
16 EP
SOICN
85/15 SnPb plate
na
MS-
012-AC
16L SOIC NB SnPb
~10 / ~40
~10 / ~40
MSL 1 / 260°C
MSL 1 / 260°C
Not Pb-free
RoHS
16L SOIC NB
Matte Sn RoHS
16 EP
SOICN G
100% Matte Sn
e3
MS-
012-AC
Notes:
1. Mounted on 4 layer PCB with exposed pad soldered to PCB land with thermal VIAs to internal GND plane
The PCB design and layout is a significant factor in determining thermal resistance (Θja) of the IC package. Use maximum
trace width on all power and signal connections at the IC; these traces serve as heat spreaders which improve heat flow from
the IC leads.
The exposed pad on the bottom of the SOIC package must be soldered to a heat-spreader land pattern on the PCB. The IC
exposed pad is electrically isolated, but must be connected to some potential on the PCB, typically Ground or Vcc. Maximize
the PCB land size by extending it beyond the IC outline if possible. A grid of thermal VIAs, which drop down and connect to
the buried copper plane(s), should be placed under the heat-spreader land. A typical VIA grid is 12mil plated holes on a 50mil
pitch. Use as many VIAs as space allows. VIAs should be plugged to prevent voids being formed between the exposed pad
and PCB heat-spreader land due to solder escaping by the capillary effect. Wicking can be avoided by tenting the VIAs with
solder mask.
©2018 Device Engineering Inc.
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Note: The bottom thermal contact (exposed pad) is electrically isolated.
Figure 20 16 Lead Narrow Body EP SOIC Outline
ORDERING INFORMATION
Table 9 Ordering Information
Package (1)
Requires 3KΩ
Resistor on DIN
Part Number
Marking
Temperature
DEI1282-SES
DEI1282-SMS
DEI1282-SES
DEI1282-SMS
16 EP SOIC
16 EP SOIC
No
No
-55ºC / 85ºC
-55ºC / 125ºC
-55ºC / 85ºC
-55ºC / 125ºC
-55ºC / 85ºC
-55ºC / 125ºC
DEI1282-SES-G
DEI1282-SMS-G
DEI1284-SES-G
DEI1284-SMS-G
DEI1282-SES-G / e3
DEI1282-SMS-G / e3
DEI1284-SES-G / e3
DEI1284-SMS-G / e3
16 EP SOIC G
16 EP SOIC G
16 EP SOIC G
16 EP SOIC G
No
No
Yes
Yes
Notes:
1. Refer to Table 8
DEI reserves the right to make changes to any products or specifications herein. DEI makes no warranty, representation, or
guarantee regarding suitability of its products for any particular purpose.
©2018 Device Engineering Inc.
17 of 17
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05/18/2018
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