DEI3182A-EMS [DEIAZ]
ARINC 429 DIFFERENTIAL LINE DRIVER;
| 型号： | DEI3182A-EMS |
| 厂家： | 
Device Engineering Incorporated |
| 描述： | ARINC 429 DIFFERENTIAL LINE DRIVER 驱动 接口集成电路 驱动器 |
| 文件： | 总10页 (文件大小：385K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Device
Engineering
Incorporated
DEI3182A
ARINC 429 DIFFERENTIAL LINE
DRIVER
385 East Alamo Drive
Chandler, AZ 85225
Phone: (480) 303-0822
Fax: (480) 303-0824
E-mail: admin@deiaz.com
FEATURES
• Adjustable rise and fall times
• Low supply current
• Capable of driving 30 nF || 400Ω
• Digitally selectable 12.5 or 100 kbit/sec data rate
• Adjustable output voltages swing
• Output over-voltage protected
• Short circuit tolerant
• TTL and CMOS compatible inputs
• MIL-STD-883B burn-in screening available
• Package Options:16L SB DIP, 16L CERDIP, 28L CLCC
• Direct replacement for Fairchild/Raytheon RM3182A
FUNCTION DIAGRAM
©2005 Device Engineering Inc
Page 1 of 10
DS-MW-03182-01 Rev E
04/20/2005
Description
The DEI3182A is a complete differential line driver IC. When Data A = Data B or Sync or Clock Signal is low, the driver forces the
output to a Voltage Null level (0V ± 250 mV). Designed to address the ARINC 429 Standard, the DEI3182A has output rise and fall
times that can be adjusted by the selection of an external capacitor (CA or CB) and an output voltage range adjustable through an
externally applied VREF signal. All logic inputs and sync control inputs are TTL/CMOS compatible. The device is constructed on a
monolithic IC using a junction-isolated bipolar process. SiCr resistors in the internal bias circuitry provide for stable bias currents and
a tighter tolerance of output impedance. The DEI3182A is available in 16-lead ceramic side-brazed DIP and can be ordered with
MIL-STD-883B burn-in screening.
Functional Description
The device contains three main functional blocks. The first block is a digital section used to decode the ARINC Clock,
Synchronization, and Data inputs as shown in Block Diagram. This block takes these inputs and channels the data to the charge pump
circuits. The logical relationship for these pins is presented in Table 1.
Table 1. I/O Truth Table
Sync
X
Clock
Data A
Data B
Out A
0V
Out B
0V
Comments
Null
L
X
H
H
H
H
X
X
L
X
X
L
L
0V
0V
Null
H
0V
0V
Null
H
L
H
L
H
-VREF
+VREF
0V
+VREF
-VREF
0V
Low
H
H
H
High
H
Null
The second functional block is a charge pump circuit that is used to control the output waveform and its timing characteristics. This is
achieved through charging and discharging a capacitor with a known current. The capacitor is user selectable, and is connected
between CA or CB pins and ground. A rate select pin (digital input) enables to set the rise and fall time. If this pin is tied to ground,
the device functions in the high rate. This mode is recommended if the user does not have an application requiring data rate switching.
In the table below, recommended capacitor values are given for each possible data combination.
Table 2. Rate Select Pin Truth Table
Rate Select
CA
CB
10% to 90% Rise/Fall
time (µS)
Ca/Cb nom.
Data Rate
(Kbits/sec)
Comments
charge current
(pf)
68*
68*
470
470
(uA)
210
30
210
30
Logic 0
Logic 1
Logic 0
Logic 1
1.0 – 2.0
5 - 15
5 - 15
N/A
100
High Rate
Low Rate
Low Rate
Not Used
12-14.5
12-14.5
N/A
* Does not include the assumed 10pf for PCB trace and IC lead capacitance.
The last functional block of the device consists of a voltage follower and a high power output differential amplifier. The voltage
follower buffers the signals presented at the charge caps and presents the mirrored signal to the difference amplifier to drive the
ARINC line. Two different outputs are available from the differential amplifiers: Amp A, Amp B, and Out A, Out B. The outputs
Amp A and Amp B are the direct outputs of the power amplifier. The outputs Out A and Out B include 37.5Ω series resistors added to
minimize bus reflections by matching the power amplifier’s output impedance to the cable’s impedance of 75Ω . Amp A and Amp B
may be used to customize the output impedance of the device. These outputs can also be used to enhance the device’s drive
capability. For example, driving the standard 30 nF || 400Ω load defined in the ARINC specifications (see output drive capability and
capacitive loads for more details). All outputs are protected from voltage spikes with diodes connected between the output pins and
the supply lines.
Output Drive Capability and Capacitive Loads
The Traditional Approach
The DEI3182A is capable of driving a high capacitive/resistive load. If complete ARINC compliance is required then Out A and Out
B pins are recommended to maintain the output impedance. In this configuration, driving the full ARINC load of 30nF || 400Ω the
output characteristic takes on the transfer function of a low pass filter due to the internal 37.5Ω resistor, the line resistance and the
capacitance associated with the cable. This will result in a lower rise/fall time of the device. Equation 1.1 relates the output voltage at
Out A and Out B to the voltage at the power amplifier’s output. Output A is taken for this example: The output as a function of
©2005 Device Engineering Inc
Page 2 of 10
DS-MW-03182-01 Rev E
04/20/2005
frequency is given by equation 1.1
AmpA ZL /2
1.1 OutA =
(ZL/2) + ROUT
Where: ROUT = 37.5Ω and ZL = RL║CL
The output as a function of Frequency is given by Equation 1.2.
RL
1.2 AOUT(jω) = Amp A(jω) [
]
RL + 2ROUT(1+ jωCLRL)
Using equation 1.2, a time constant can be determined for the given application which is shown in equation 1.3.
1.3 τ = (ROUT║RL)CL
So, for the maximum loading condition of 30nF || 400Ω the resulting time constant is 1.9 µs. This shows that with a maximum load,
the output waveform is greatly affected by the low pass filter combination of the ROUT || RL resistor and the load capacitance.
A New Option: Amp A/Amp B
The DEI3182A also provides the user the option of connecting the data line directly to the power output amplifiers thus bypassing the
internal 37.5Ω resistance of the device and matching the line more precisely. For example, using a 1% 37.5Ω resistor allows better
control of the output impedance. By applying the load directly to the power amplifiers output pins, the resulting waveform is virtually
unchanged when driving other loads. There may be applications where these pins present a more desirable result. For instance, if the
line that the chip is driving is short, then the parasitic components of the line can be neglected, and power amplifier can be tied
directly to the lines. This option can be utilized to achieve a greater noise immunity through bypassing the internal resistors.
Pin Assignments
©2005 Device Engineering Inc
Page 3 of 10
DS-MW-03182-01 Rev E
04/20/2005
Absolute Maximum Ratings
Parameter
Min.
Max.
+36
Units
Supply Voltage:
+VS to -VS
+VS to GND
-Vs to GND
V
V
V
V
V
V
V
+20
-20
0
VLOGIC Threshold Voltage
VREF Voltage
+7
+6
0
Logic Input Voltage
AMP A/B Transient Pulse:
-0.5
-70
VLOGIC + 0.5
+70
150uS pulse applied through an external
37.5Ω resistor. (1)
Storage Temperature Range
Operating Temperature Range
Junction Temperature
-65
-55
-55
+150
+125
+175
+300
°C
°C
°C
°C
Lead Soldering Temperature (60 sec.)
Note:
1. Sample tested on each wafer lot.
Thermal Characteristics
(Still air, soldered into PC board)
Parameter
16-Lead Side-brazed DIP
16-Lead CERDIP
28-Lead LCC
60°C/W
Thermal Resistance, θJa
Thermal Resistance, θJC
70°C/W
28°C/W
70°C/W
28°C/W
25°C/W
Recommended Operating Conditions
Symbol Parameters
Min.
13.5
-16.5
4.5
Max.
Units
V
+Vs
Positive Supply Voltage
16.5
-13.5
5.5
-Vs
Negative Supply Voltage
VLOGIC Supply Voltage
VREF Voltage
V
VLOGIC
VREF
Top
V
4.75
-55
5.25
125
V
Case Temperature
ºC
Electrical Characteristics
Symbol Parameters
Test Conditions (1,2)
POWER SUPPLIES
Min.
Max.
Units
ICC
Positive Supply Current
Negative Supply Current
VLOGIC Supply Current
VREF Supply Current
+VS = 16.5V, -VS = -16.5V,
VLOGIC = VREF = 5.5V,
DATAA =CLOCK=SYNC=VIH
DATAB=RATE = VIL
4.0
18
mA
Outputs = HI, unloaded
+VS = 16.5V, -VS = -16.5V,
VLOGIC = VREF = 5.5V,
DATAA =CLOCK=SYNC=VIH
DATAB=RATE = VIL
IEE
4.0
150
-800
18
mA
µA
µA
Outputs = HI, unloaded
+VS = 16.5V, -VS = -16.5V,
VLOGIC = VREF = 5.5V,
DATAA =CLOCK=SYNC=VIH
DATAB=RATE = VIL
ILOGIC
IREF
300
-100
Outputs = HI, unloaded
+VS = 16.5V, -VS = -16.5V,
VLOGIC = VREF = 5.5V,
DATAA =CLOCK=SYNC=VIH
DATAB=RATE = VIL
Outputs = HI, unloaded
LOGIC INPUTS
VIH
Logic 1 Input Voltage
Functional Tests
2.0
V
©2005 Device Engineering Inc
Page 4 of 10
DS-MW-03182-01 Rev E
04/20/2005
Symbol Parameters
Test Conditions (1,2)
Min.
Max.
0.5
1
Units
V
VIL
IIH
Logic 0 Input Voltage
Functional Tests
Logic 1 Input Current
VIN = 2.0V,
µA
+Vs=+15V, -Vs=-15V,
VLOGIC=VREF=4.5V
IIL
Logic 0 Input Current
VIN = 0.5V,
-645
-50
nA
+Vs=+15V, -Vs=-15V,
VLOGIC=VREF=5.5V
CI
Input Capacitance
Output Voltage High
Output Voltage Low
Output Voltage Null
Output Resistance
(3)
15
pF
V
A429 OUTPUTS
VOH
VOL
VNULL
Rout
Outputs open, referenced to Ground,
Vref =5.0V, Supplies = min to max
Outputs open, referenced to Ground,
Vref =5.0V, Supplies = min to max
Outputs open, referenced to Ground,
Vref =5.0V, Supplies = min to max
Tc = 25ºC
4.75
-5.25
-250
5.25
-4.75
+250
V
mV
Ohms
33.7
33
41.2
44
TC = -55ºC to +125ºC
Rout = ∆Vout/∆Iout
Vout measured at 0mA & 10mA
RATE = VIL, Ca/Cb = 68pf,
Cload = 50pf
Trf-hi
Trf-lo
HI rate rise/fall time
LO rate rise/fall time
1.0
5.0
2.0
uS
uS
10 to 90% (4)
RATE = VIH, Ca/Cb = 68pf,
Cload = 50pf
15.0
10 to 90% (4)
CAPACITOR PINS
ICL
Low Rate Capacitor Current
Rate Sel = ‘1’, CA (CB) = 2.5V, HL
edge currents are negative
20
60
uA
uA
ICH
High Rate Capacitor Current Rate Sel = ‘0’, CA (CB) = 2.5V, HL
edge currents are negative
138
277
SHORT CIRCUIT CONDITIONS
ISC
Output Short Circuit Current
+VS Short Circuit Current
-VS Short Circuit Current
AOUT and/or BOUT shorted line-to-line
or to GND. Outputs HI or LOW.
AOUT and/or BOUT shorted line-to-line
or to GND. Outputs HI or LOW.
AOUT and/or BOUT shorted line-to-line
or to GND. Outputs HI or LOW.
100
100
100
156
165
165
mA
mA
mA
ISC+VS
ISC-VS
Notes:
1. Unless otherwise indicated, +VS = +15V, -VS = -15V, VREF = +5V, VLOGIC = +5V, Rate Select = 0V, RL = Open Circuit,
CL = 0 pF, and -55°C < Tcase < +125°C.
2. Unless otherwise indicated, currents flowing into DUT are positive, currents flowing out of DUT are negative, and voltages are
referenced to Ground.
3. Guaranteed by design. Not production tested
4. Sample tested.
Typical Power Dissipation Characteristics
(+VS = +15V, -VS = -15V, VREF = +5V, TA = + 25°C, CA = CB = 68pF)
Positive
Supply
Current
Negative
Supply
VLOGIC
Supply
Current
Total Power
Dissipation
Data
Load
Rate Select
Current
Rate
(Kbits/sec)
0 –100
Open Circuit
Full Load(1)
Full Load(1)
Logic 1,0
Logic 1
Logic 0
5.7 mA
19.6 mA
39.1 mA
4.9 mA
22.7 mA
38.4 mA
214 µA
200 µA
200 µA
160 mW
655 mW
1165 mW
12.5 – 14
100
Note:
1. RL = 400Ω, CL = 0.03 µF (see Block Diagram).
©2005 Device Engineering Inc
Page 5 of 10
DS-MW-03182-01 Rev E
04/20/2005
Applications
Heat Sinking / Air Flow and Short Circuit Protection
The user application will determine if and how much heat sinking/air flow will be required for the DEI3182A. Consideration must be
given to ambient temperature, load conditions and output voltage swing. In addition, power consumption increases with increased
operating frequency. Use the numbers given in the Thermal Characteristics Table to determine that the maximum allowable junction
temperature of 175°C is not exceeded.
Outputs Out A and Out B are short circuit protected by the internal 37.5Ω back termination resistors. During a short circuit of the
output to either power supply or ground, the device must be able to dissipate the generated heat. For example, if the output is shorted
to ground and +VS = +15V, the device must dissipate 15V x 0.165A = 2.5W. An appropriate heat sink is required in this situation.
Note that the Amp A and Amp B outputs are not short circuit protected. Shorting these pins to either power supply or ground will
cause failure of the device. An added external resistor will protect the circuit by limiting the current.
Power Supply Considerations
Three power supplies are required to operate the DEI3182A in a typical ARINC 429 bus application: +15V for +VS, -15V for -VS,
and +5V for both VREF and VLOGIC. The differential output swing of the DEI3182A is equal to 2 x VREF. Using +5V gives a
differential output swing of 10V. If a different output voltage swing is required, an additional power supply is needed to set VLOGIC.
Each power supply pin should be decoupled to ground using a high quality 10 µF tantalum capacitor. This is especially true when
driving a large capacitive or resistive loads. The decoupling capacitors should be located as close to the device pins as possible to
eliminate the wiring inductance.
Typical ARINC 429 Application
Figure 1 shows typical switching waveform for the DEI3182A in any configuration. Figure 2 depicts connections for a ARINC 429
high speed bus driver application. This circuit shows the complete configuration for a 100 Kbits/sec, 10V differential output swing
using the terminated output pins.
+VREF x 2
-VREF x 2
Figure 1. Switching Waveforms
©2005 Device Engineering Inc
Page 6 of 10
DS-MW-03182-01 Rev E
04/20/2005
68pF
68pF
Figure 2. ARINC 429 Bus Driver Applications (100 kb/s Mode)
©2005 Device Engineering Inc
Page 7 of 10
DS-MW-03182-01 Rev E
04/20/2005
Mechanical Dimensions
16-Lead Side-Braze Ceramic DIP
Lead Finish:
Au plated with Sn63/Pb37 solder dip covering the lead to the seating plane.
©2005 Device Engineering Inc
Page 8 of 10
DS-MW-03182-01 Rev E
04/20/2005
16-Lead CERDIP
PIN 1
0.025 RAD
.752 - .780
Dimensions Are in Inches
.280 - .296
0.308 - 0.325
0.050 MAX
.200 MAX
.056
.010 - .012
0.125 MIN
0.325 - 0.410
0.140 - 0.175
0.100 ± 0.010
0.018 ± 0.002
28-Lead CLCC
.008
+
SQ
- .005
.450
.300
+
.006
-
.060
TYP.
.050
+.002
-
TYP.
11
5
5
11
MIN.
12
4
4
.015
12
TYP.
PIN N0.1
INDEX.
1
1
MIN.
.035
+
.003
-
.025
TYP.
18
26
26
18
19
25
25
19
.050
0.015
TYP.
R .008
+.008
TYP.
-
.085
Lead Finish:
Au plated with Sn63/Pb37 solder dip.
©2005 Device Engineering Inc
Page 9 of 10
DS-MW-03182-01 Rev E
04/20/2005
Process Flow
Process Step
THERMAL CYCLE
Standard
10 Cycles
YES
Burn-In
10 Cycles
YES
MIL-STD-883B M1010.4 Condition B
CONSTANT ACCELERATION
MIL-STD-883B M2001, Method D
GROSS & FINE LEAK
MIL-STD-883B M1014.10
YES
YES
PRE-BURN-IN Electrical Test
BURN IN
NO
YES
MIL-STD-883B M1015 Condition A
FINAL ELECTRICAL TEST,
Room Temperature
NO
160hrs @ +125 °C
100%
100%
FINAL ELECTRICAL TEST,
High Temperature
100% @ +125°C 100% @ +125°C
FINAL ELECTRICAL TEST,
Low Temperature
0.65% AQL
@ -55°C
0.65% AQL
@ -55°C
Ordering Information
Part Number
Package
Operating Temperature Range
-55°C to + 125°C
Burn In
DEI3182A-DMS
DEI3182A-DMB
DEI3182A-CMS
DEI3182A-CMB
DEI3182A-EMS
DEI3182A-EMB
16-Lead Side-braze Ceramic DIP
16-Lead Side-braze Ceramic DIP
16-Lead CERDIP
N
Y
N
Y
N
Y
-55°C to + 125°C
-55°C to + 125°C
16-Lead CERDIP
-55°C to + 125°C
28 Lead Ceramic LCC
28 Lead Ceramic LCC
-55°C to + 125°C
-55°C to + 125°C
Note: The –CMB/-DMB/-EMB parts may be marked as –CMS /–DMS/-EMS with a “B” stamp to denote burn-in.
DEI reserves the right to make changes to any products or specifications herein. DEI makes no warranty, representation, or
guarantee regarding suitability of its products for any particular purpose.
©2005 Device Engineering Inc
Page 10 of 10
DS-MW-03182-01 Rev E
04/20/2005
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