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DEI3283-SES [DEIAZ]

DUAL ARINC 429 LINE RECEIVER;
DEI3283-SES
型号： DEI3283-SES
厂家： Device Engineering Incorporated    Device Engineering Incorporated
描述：

DUAL ARINC 429 LINE RECEIVER
文件： 总11页 (文件大小：590K)
中文：  中文翻译
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Device  
Engineering  
Incorporated  
DEI3283  
DUAL ARINC 429 LINE RECEIVER  
385 East Alamo Drive  
Chandler, AZ 85225  
Phone: (480) 303-0822  
Fax: (480) 303-0824  
E-mail: admin@deiaz.com  
FEATURES  
x
x
x
x
x
x
x
x
x
x
Two separate analog receiver channels  
Converts ARINC 429 levels to serial data  
ARINC 429 inputs withstand +/-200V  
TTL inputs to test complete analog/digital RX function  
TTL and CMOS compatible outputs  
Low power dissipation  
Internal band gap voltage reference  
MIL-STD-883B burn-in screening available  
Package Options: 20 Lead ceramic DIP, 20 Terminal ceramic LCC, and 20 Lead SOIC  
Direct replacement for Fairchild/Raytheon RM3283 and RM3183 and Holt HI-8482  
Function Diagram  
©2012 Device Engineering Inc  
Page 1 of 11  
DS-MW-03283-01 Rev L  
12/12/2012  
General Description  
The DEI3283 consists of two analog ARINC 429 receivers which take differentially encoded ARINC level data and convert it to  
serial TTL level data. The DEI3283 provides two complete analog ARINC receivers with no external components required. Input  
level shifting thin film resistors and bipolar technology allow ARINC input voltage transients up to rꢀ200V without damage to the  
DEI3283. Each channel is identical, featuring symmetrical propagation delays for better high speed performance. Input common  
mode rejection is excellent and threshold voltage is stable, independent of supply voltage. Data outputs are TTL and CMOS  
compatible. Two TTL compatible test inputs used to test the ARINC channels are available. They can be used to override the ARINC  
input data and set the channel outputs to a known state. The DEI ARINC line driver family IC’s are companion chips to the DEI3283  
line receiver. Together they provide the analog functions needed for the ARINC 429 interface.  
Functional Description  
The DEI3283 contains two discrete ARINC 429 receiver channels. Each channel contains three main sections: a resistor input  
network, a window comparator, and a logic output buffer stage. The first stage provides over voltage protection and biases the signal  
using voltage dividers and current sources, providing excellent input common mode rejection. The test inputs are provided to set the  
outputs to a predetermined state for built-in channel test capability. If the test inputs are not used, they should be grounded. The  
window comparator section detects data from the resistor input network. A LOGIC 1 corresponds to ARINC “High” state (OUTA)  
and a LOGIC 0, to ARINC “Low” state (OUTB). An ARINC “Null” state at the inputs forces both outputs to LOGIC 0. Threshold  
and hysteresis voltages are generated by a band gap voltage reference to maintain stable switching characteristics over temperature  
and power supply variations. The output stage generates a TTL compatible logic output capable of driving 3mA of load.  
Pin Assignments  
PIN  
1
NAME  
-Vs  
DESCRIPTION  
Supply Voltage (-15V)  
2
3
4
Logic Input, see functional characteristics.  
A429 INPUT, Ch 2, B Capacitor node  
A429 INPUT, Ch 2, B input  
TEST A  
CAP2B  
IN2B  
5
6
Logic Output, Ch 2, B’s output  
A429 INPUT, Ch 2, A input  
OUT2B  
IN2A  
7
A429 INPUT, Ch 2, A Capacitor node  
CAP2A  
©2012 Device Engineering Inc  
Page 2 of 11  
DS-MW-03283-01 Rev L  
12/12/2012  
PIN  
8
9
NAME  
OUT2A  
+VL  
DESCRIPTION  
Logic Output, Ch 2, A’s output  
Supply Voltage (+5V)  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
NC  
+VS  
OUT1B  
NC  
GND  
OUT1A  
IN1B  
CAP1B  
IN1A  
CAP1A  
TESTB  
Supply Voltage (+15V)  
Logic Output, Ch 1, B’s output  
Supply Return  
Logic Output, Ch 1, A’s output  
A429 INPUT, Ch 1, B input  
A429 INPUT, Ch 1, B Capacitor node  
A429 INPUT, Ch 1, A input  
A429 INPUT, Ch 1, A Capacitor node  
Logic Input, see functional characteristics.  
Absolute Maximum Ratings  
Parameter  
Supply Voltage:  
Min.  
Max.  
+36  
+20  
Units  
V
V
+VS to -VS  
+VS to GND  
-Vs to GND  
-20  
V
+VL Voltage  
+7  
+VL + 0.3  
+200  
+150  
+125  
V
V
V
°C  
°C  
°C  
Logic Input Voltage  
ARINC 429 Input Voltage  
Temperature Range  
-0.3  
-200  
-65  
-55  
-55  
Storage  
Operating  
Ceramic  
Junction Temperature  
+175  
Plastic  
-55  
+145  
Lead Soldering Temperature  
Peak Body Temperature, J-STD-020  
Non-G Package  
(60 sec., DIP, LCC)  
+300  
°C  
°C  
(SOIC)  
+240  
+260  
-G Package  
Recommended Operating Conditions  
Symbol Parameters  
Min.  
Max.  
16.5  
-13.5  
5.5  
Units  
+Vs  
-Vs  
+VL  
Top  
Positive Supply Voltage  
Negative Supply Voltage  
+VL Supply Voltage  
Case Temperature  
Ceramic  
13.5  
-16.5  
4.5  
V
V
V
-55  
-40  
-55  
+125  
+125  
+85  
°C  
°C  
°C  
Plastic: -SA  
-SE  
©2012 Device Engineering Inc  
Page 3 of 11  
DS-MW-03283-01 Rev L  
12/12/2012  
Electrical Characteristics  
Symbol  
ICC  
Parameter  
Conditions (1,2)  
POWER SUPPLIES  
Supply = +/- 16.5V, Vl = 5.0V,  
Test Inputs = 0V  
Test Inputs = 5V  
Supply = +/- 16.5V, Vl = 5.0V,  
Test Inputs = 0V  
Test Inputs = 5V  
Supply = +/- 16.5V, Vl = 5.0V,  
Test Inputs = 0V  
Min.  
Max.  
Units  
mA  
mA  
mA  
V
+VS (+15V) Supply  
Current  
3.5  
3.5  
6.0  
6.0  
IEE  
IL  
-Vs (-15V) Supply  
Current  
7.5  
11.0  
12.0  
18.5  
+VL (+5V) Supply  
Current  
4.5  
10.8  
9.0  
17.6  
Test Inputs = 5V  
A429 INPUTS  
Supply = +/-15.0V, Vl = 5.00V  
Test inputs = 0V  
VINB = -2.50V  
Supply = +/-15.0V, Vl = 5.00V  
Test inputs = 0V  
VHH  
VHL  
NULL to 1 transition,  
V(INA) – V(INB)  
5.70  
4.50  
6.30  
5.50  
1 to NULL transition,  
V(INA) – V(INB)  
V
VINB = -2.50V  
VHHYS  
VLL  
1 to NULL transition  
hysteresis  
NULL to 0 transition,  
V(INA) – V(INB)  
VHH-VHL  
0.8  
1.2  
V
V
Supply = +/-15.0V, Vl = 5.00V  
Test inputs = 0V  
-6.30  
-5.70  
VINB = +2.50V  
VHL  
0 to NULL transition,  
V(INA) – V(INB)  
Supply = +/-15.0V, Vl = 5.00V  
Test inputs = 0V  
-5.50  
-4.50  
V
VINB = +2.50V  
VLHYS  
VCM  
0 to NULL transition  
hysteresis  
Input common mode  
voltage range  
Input resistance,  
Input to GND  
Input resistor,  
INA to CAPA,  
INB to CAPB  
VLL-VLH  
-1.2  
-13  
20  
-0.8  
+13  
30  
V
V
RINGND  
RIN  
Unpowered,  
INA to GND, INB to GND  
Unpowered  
INA to CAPA, INB to CAPB  
Nȍ  
Nȍ  
8.5  
11.5  
CIN  
Input capacitance,  
INA to GND,  
(3)  
10  
pF  
INB to GND  
TEST LOGIC INPUTS  
VIH  
VIL  
IIH  
LOGIC 1 input voltage Functional Test  
LOGIC 0 input voltage Functional Test  
LOGIC 1 input current VIH = 5V  
2.0  
0
V
V
µA  
0.9  
600  
Supply = +/-15.0V, Vl = 5.00V  
LOGIC 0 input current VIL = 0.8V  
Supply = +/-15.0V, Vl = 5.00V  
IIL  
0
50  
µA  
LOGIC OUTPUTS  
Vsupply = +/-15.0V, Vl = 5.0V  
IOH = -100uA (Room Temp)  
IOH = -2.8mA  
Vsupply = +/-15.0V, Vl = 5.0V  
IOL = 100uA (Room Temp)  
IOL = 2.0mA  
VOH  
VOL  
LOGIC 1 output  
voltage  
4.0  
3.5  
V
V
LOGIC 0 output  
voltage  
0.1  
0.8  
V
V
©2012 Device Engineering Inc  
Page 4 of 11  
DS-MW-03283-01 Rev L  
12/12/2012  
Symbol  
Tr  
Tf  
Parameter  
Output rise time  
Output Fall Time  
Prop delay,  
A429 to LH output  
Prop delay,  
A429 to HL output  
Matching of  
TPLH and TPHL  
Prop delay,  
TESTA/B to LH output  
Prop delay,  
Conditions (1,2)  
CL = 60 pF (4)  
CL = 60 pF (4)  
A429 In = 0 to 10V (4)  
CAPA, CAPB, OUT CL = 60 pF  
A429 In = 0 to 10V (4)  
CAPA, CAPB, OUT CL = 60 pF  
|TPLH-TPHL| (4)  
Min.  
10  
Max.  
70  
Units  
ns  
ns  
10  
70  
1500  
TPLH  
ns  
TPHL  
DTP  
1500  
500  
ns  
ns  
ns  
ns  
TPTLH  
CL = 60 pF, VIN = 0.8V/2.0V (4)  
CL = 60 pF, VIN = 0.8V/2.0V (4)  
400  
800  
600  
TPTHL  
1300  
TESTA/B to HL output  
Notes:  
1. Unless otherwise noted, currents flowing in to DUT are positive, Currents flowing out of DUT are negative, Voltages are  
referenced to Ground.  
2. Unless otherwise noted, Tcase = -55°C to +125°C for -xMx, -40°C to +125°C for -xAx, and -55°C to +85°C for –xEx versions;  
+VS = +13.5 to 16.5V, -Vs = -13.5 to –16.5V, +VL = 4.5 to 5.5V.  
3. Guaranteed by design. Not production tested.  
4. Sample tested.  
AC Test Waveforms  
©2012 Device Engineering Inc  
Page 5 of 11  
DS-MW-03283-01 Rev L  
12/12/2012  
Functional Characteristics  
ARINC Inputs  
V(A) – V(B)  
Null  
Low  
High  
X
Test Inputs  
Outputs  
Output  
State  
Null  
Low  
High  
Low  
TEST A  
TEST B  
OUT_A  
OUT_B  
0
0
0
0
1
1
0
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
X
X
High  
Null  
V[INA – INB]  
V[OUT_A]  
V[OUT_B]  
Parameter  
Characteristics (100KBS)  
min  
9.75  
4.87  
0.5  
0.5  
+7.25  
max  
10.25  
5.13  
2
2
11  
units  
us  
us  
us  
Time Y  
Time X  
Pulse rise time  
Pulse fall time  
Vhigh  
Vhh  
Vhl  
Vnull  
Vll  
us  
V diff  
V diff  
V diff  
V diff  
V diff  
V diff  
V diff  
+6.5  
+2.5  
-0.5  
+0.5  
-2.5  
Vlh  
Vlow  
-6.5  
-11  
-7.25  
©2012 Device Engineering Inc  
Page 6 of 11  
DS-MW-03283-01 Rev L  
12/12/2012  
Applications Discussion  
The standard connections for the DEI3283 are shown in the figure below. Dual ±15VDC supplies are recommended for the +VS/-VS  
supplies. Decoupling of all supplies should be done near the IC to avoid propagation of noise spikes due to switching transients. The  
ground connection should be sturdy and isolated from large switching currents to provide as quiet a ground reference as possible. The  
noise filter capacitors are optional and are added to provide extra noise immunity by limiting bandwidth of the input signal before it  
reaches the window comparator stage. Two capacitors are used for each channel and they must be the same value. The suggested  
capacitor value for a 100 kHz operation is 39 pF. For lower data rates, larger values of capacitance may be used to yield better noise  
performance. To get optimum performance, the following equation can be used to calculate capacitor value for a specific data rate:  
Where CFILTER is the capacitor value in pF, and FO is the input frequency (10 kHz dꢀFO dꢀ150 kHz).  
Applications  
ARINC Receiver Standard Connections  
©2012 Device Engineering Inc  
Page 7 of 11  
DS-MW-03283-01 Rev L  
12/12/2012  
Process Flow  
Process Step  
Plastic  
Standard  
Ceramic  
Burn-In  
Ceramic  
Standard  
Plastic  
Burn-In  
THERMAL CYCLE  
MIL-STD-883B M1010.4 Condition B  
CONSTANT ACCELERATION  
MIL-STD-883B M2001, Method D.  
GROSS & FINE LEAK  
NO  
N/A  
N/A  
N/A  
N/A  
10 Cycles  
NO  
N/A  
N/A  
YES  
10 Cycles  
YES  
YES  
YES  
MIL-STD-883B M1014.10  
YES  
PRE-BURN-IN Electrical Test  
BURN IN  
MIL-STD-883B M1015 Condition A  
FINAL ELECTRICAL TEST,  
Room Temperature  
N/A  
YES  
N/A  
160hrs @ +125 °C 160hrs @ +125 °C  
100%  
100% @  
+85 or +125°C  
0.65% AQL  
@
100%  
100%  
100% @  
+85 or +125°C  
0.65% AQL  
@
100%  
FINAL ELECTRICAL TEST,  
High Temperature  
100% @ +125°C  
100% @ +125°C  
FINAL ELECTRICAL TEST,  
Low Temperature  
0.65% AQL  
@ -55°C  
0.65% AQL  
@ -55°C  
-55 or -40°C  
-55 or -40°C  
Burn-In Circuit  
©2012 Device Engineering Inc  
Page 8 of 11  
DS-MW-03283-01 Rev L  
12/12/2012  
Package Characteristics  
Package Characteristics  
PACKAGE TYPE  
20L  
Ceramic  
LCC  
20L CERDIP 20L CERDIP  
GREEN  
20L SOIC  
20L SOIC  
GREEN  
Reference  
(see ordering info)  
20 CLCC  
20 CERDIP  
20 CERDIP  
G
20 SOIC  
20 SOIC G  
MS-013-AE  
MS-030-A-  
AE  
MS-030-A-  
AE  
JEDEC MO Reference  
MO-047  
MS-013-AE  
THERMAL RESISTANCE:  
TJA (4 layer PCB)  
TJC  
85 °C/W  
30 °C/W  
70 °C/W  
28 °C/W  
70 °C/W  
28 °C/W  
85 °C/W  
30 °C/W  
85 °C/W  
30 °C/W  
JEDEC Moisture  
Sensitivity Level  
Lead Finish Material /  
JEDEC Pb-free code  
Hermetic  
Hermetic  
Hermetic  
MSL 1 /  
250°C  
SnPb  
plate  
na  
MSL 1 /  
250°C  
Matte Sn  
e3  
(MSL)  
SnPb  
solder dip  
na  
SnPb  
solder dip  
na  
SnAgCu  
solder dip  
e1  
Pb-Free DESIGNATION  
Not Pb-free  
Not Pb-free  
Pb free  
Not Pb-free  
RoHS  
Compliant  
20L SOIC ( – G and non - G ) Package  
©2012 Device Engineering Inc  
Page 9 of 11  
DS-MW-03283-01 Rev L  
12/12/2012  
20L CERDIP (-G and non-G) Package  
20L Ceramic LCC Package  
©2012 Device Engineering Inc  
Page 10 of 11  
DS-MW-03283-01 Rev L  
12/12/2012  
Ordering Information  
Operating Temperature  
Range  
Part Number  
Marking  
Package  
Burn In  
DEI3283-CMB  
DEI3283-CMB  
Y
20 CERDIP  
-55qC to +125qC  
DEI3283-CMB  
E1  
DEI3283-CMS  
DEI3283-CMS  
E1  
DEI3283-CMB-G  
DEI3283-CMS  
Y
N
N
20 CERDIP G  
20 CERDIP  
-55qC to +125qC  
-55qC to +125qC  
-55qC to +125qC  
DEI3283-CMS-G  
20 CERDIP G  
DEI3283-EMB  
DEI3283-EMS  
DEI3283-SAB  
DEI3283-EMB  
DEI3283-EMS  
DEI3283-SAB  
Y
N
Y
20 CLCC  
20 CLCC  
20 SOIC  
-55qC to +125qC  
-55qC to +125qC  
-40qC to +125qC  
DEI3283-SAB  
E3  
DEI3283-SAS  
DEI3283-SAS  
E3  
DEI3283-SEB  
DEI3283-SEB  
E3  
DEI3283-SES  
DEI3283-SES  
E3  
DEI3283-SMB  
DEI3283-SMB  
E3  
DEI3283-SMS  
DEI3283-SMS  
E3  
DEI3283-SAB-G  
DEI3283-SAS  
Y
N
N
Y
Y
N
N
Y
Y
N
N
20 SOIC G  
20 SOIC  
-40qC to +125qC  
-40qC to +125qC  
-40qC to +125qC  
-55qC to +85qC  
-55qC to +85qC  
-55qC to +85qC  
-55qC to +85qC  
-55qC to +125qC  
-55qC to +125qC  
-55qC to +125qC  
-55qC to +125qC  
DEI3283-SAS-G  
DEI3283-SEB  
20 SOIC G  
20 SOIC  
DEI3283-SEB-G  
DEI3283-SES  
20 SOIC G  
20 SOIC  
DEI3283-SES-G  
DEI3283-SMB  
DEI3283-SMB-G  
DEI3283-SMS  
DEI3283-SMS-G  
20 SOIC G  
20 SOIC  
20 SOIC G  
20 SOIC  
20 SOIC G  
Notes:  
1. All packages marked with Lot Code and Date Code. “E1” or “E3” after Date Code denotes Pb Free category.  
2. The –CMB/-EMB/-SAB/-SEB/-SMB parts may be marked as – CMS/-EMS/-SAS/-SES/-SMS with a “B” stamp to denote  
burn-in.  
DEI reserves the right to make changes to any products or specifications herein. DEI makes no warranty, representation, or  
guarantee regarding suitability of its products for any particular purpose.  
©2012 Device Engineering Inc  
Page 11 of 11  
DS-MW-03283-01 Rev L  
12/12/2012  

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