DEI5072-SES-G [DEIAZ]
ARINC 429 5V LINE DRIVER FAMILY;
| 型号： | DEI5072-SES-G |
| 厂家： | 
Device Engineering Incorporated |
| 描述： | ARINC 429 5V LINE DRIVER FAMILY 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总11页 (文件大小：324K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Device
Engineering
DEI5070, 5071, 5072, 5270
ARINC 429 ±5V LINE DRIVER
FAMILY
Incorporated
385 East Alamo Drive
Chandler, AZ 85225
Phone: (480) 303-0822
Fax: (480) 303-0824
E-mail: admin@deiaz.com
FEATURES
•
•
•
•
•
•
TTL/CMOS TO ARINC 429 Line Driver.
Rate control input set Hi (100KBS) or Lo (12.5KBS) speed slew rates.
Operates from ±5V power supply.
Drives full ARINC load.
Output resistor options: 7.5, 27.5 or 37.5 Ohms.
Packages:
o
o
8L SOIC Exposed Pad (single driver)
38L MLPQ (QFN) (dual driver)
GENERAL DESCRIPTION
The DEI5x7x family of CMOS integrated circuits are line drivers designed to directly drive the ARINC 429 avionics serial
digital data bus. The device converts TTL/CMOS serial input data to the tri-level RZ bipolar differential modulation format of
the ARINC bus. A TTL/CMOS control input selects the output slew rate for HI (100KBS) and LOW (12.5KBS) speed
operation. No external timing capacitors are required.
The 5070 has internal 37.5 Ohm output resistors, the 5071 has 27.5 Ohm resistors, the 5072 has 7.5 Ohm resistors, and the
5270 has two drivers with all output resistor options. The 27.5 and 7.5 Ohm options require external series resistors which are
typically used to implement a transient voltage protection network.
Table 1 5070/71/72 PIN DESCRIPTION
PIN
1
NAME
HI/LO
TTLIN0
TTLIN1
GND
DESCRIPTION
LOGIC INPUT: Slew rate control.
LOGIC INPUT: Serial digital data input 0
LOGIC INPUT: Serial digital data input 1
POWER INPUT: Ground
2
1
2
3
4
8
7
6
5
HI/LO
V+
3
TTLIN0
TTLIN1
429OUTB
429OUTA
4
POWER INPUT: -5VDC
5
V-
GND
V-
429 OUTPUT: ARINC 429 format serial digital data
6
429OUTA
output A
Note:
Heatsink pad is electrically isolated
© 2011 Device Engineering Inc
429 OUTPUT: ARINC 429 format serial digital data
7
8
429OUTB
V+
output B
POWER INPUT: +5VDC
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1
2
3
4
5
6
7
8
9 10 11 12
13
14
15
16
17
18
19
38
37
36
35
34
33
32
Notes:
1. Package: 38 Lead 5.0 x 7.0mm MLP
2. Exposed Pad is electrically isolated
31 30 29 28 27 26 25 24 23 22 21 20
BOTTOM VIEW
Table 2 5270 PIN DESCRIPTION
Channel 1
Pin
Channel 2
Pin
DESCRIPTION
SIGNAL NAME
HI/LO_n
LOGIC INPUT: Slew rate control. 1 = Hi speed. 0 = Low speed.
LOGIC INPUT: Serial digital data input 0.
5
24
25
7
TTLIN0_n
TTLIN1_n
429OUTA_7_n
429OUTA_27_n
429OUTA_37_n
429OUTB_7_n
429OUTB_27_n
429OUTB_37_n
V+
6
LOGIC INPUT: Serial digital data input 1.
26
34
33
32
36
37
38
2
429 OUTPUTS: ARINC 429 format serial digital data output A, 7.5 Ohm
429 OUTPUTS: ARINC 429 format serial digital data output A, 27.5 Ohm
429 OUTPUTS: ARINC 429 format serial digital data output A, 37.5 Ohm
429 OUTPUTS: ARINC 429 format serial digital data output B, 7.5 Ohm
429 OUTPUTS: ARINC 429 format serial digital data output B, 27.5 Ohm
429 OUTPUTS: ARINC 429 format serial digital data output B, 37.5 Ohm
POWER INPUT: +5 VDC
15
14
13
17
18
19
20
9
POWER INPUT: Ground
GND
28
30
POWER INPUT: -5 VDC
V-
12
1, 3, 4, 8, 10, 11, 16, 21, 22,
23, 27, 29, 31, 35
NC
No Internal Connect
© 2011 Device Engineering Inc
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FUNCTIONAL DESCRIPTION
HI/LO
429OUTA
429OUTB
TTLIN1
INPUT LOGIC
OUTPUT
DRIVERS
EDGE
and
SHAPING
LEVEL SHIFT
TTLIN0
Block Diagram (single channel shown)
Table 3 Speed Control Function Table
HI/LO
OUTPUT TRANSITION TIME
0
1
10us (12.5 KBS data)
1.5us (100KBS data)
Table 4 Transmit Data Function Table
TTLIN1
TTLIN0
429OUTA
429OUTB
NOTES
0
0
1
1
0
1
0
1
0V
0V
Null output
Zero output
One output
Null output
-5V
5V
5V
-5V
0V
0V
TTLIN1
TTLIN0
+5
50%
429OUTA
-5
+5
Tskew
50%
429OUTB
-5
Tfall
+10
90%
Differential
Tfall
429OUT
(A-B)
10%
10%
90%
Trise
-5
Trise
Figure 1 Timing Waveforms
© 2011 Device Engineering Inc
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ELECTRICAL DESCRIPTION
Table 5 Absolute Maximum Ratings
PARAMETER
MIN
MAX
UNITS
Voltages referenced to Ground
V+ Supply Voltage
-0.3
0.3
+7
-7
V
V
V- Supply Voltage
Storage Temperature
-65
+150
°C
Input Voltage
TTLIN and HI/LO Inputs
Gnd – 0.3 V+ + 0.3
V
V
429OUT Outputs
V- – 0.3
V+ + 0.3
Power Dissipation @ 85 °C: (> 10 Sec), Thermal pad soldered to heat spreader
-Sxx package, derate 20mW/C above 85°C
-Mxx package, derate 28.3mW/C above 85°C
Junction Temperature:
1.2
1.7
W
Tjmax, Plastic Packages (Limited by molding compound Tg)
ESD per JEDEC A114-A Human Body Model
145
2000
°C
V
Peak Body Temperature (Pb Free solder profile)
260
°C
Notes:
1. Stresses above absolute maximum ratings may cause permanent damage to the device.
2. The device is tolerant of one or both outputs shorted to Ground and of both outputs shorted together.
Table 6 Recommended Operating Conditions
PARAMETER
Supply Voltage
SYMBOL
CONDITIONS
V+
4.8 to 5.3V
V-
-4.8 to -5.3V
Operating Temperature
-xEx variants
TOP
-55 to +85 °C
-55 to +125 °C
-xMx variants
© 2011 Device Engineering Inc
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Table 7 Electrical Characteristics
Conditions (Unless otherwise noted):
Temperature: -55°C to +85°C (-xEx) or -55°C to +125°C (-xMx)
V+ = +4.8V to +5.3V and V- = -4.8V to -5.3V
PARAMETER
TEST CONDITION
SYMBOL
MIN
NOM
MAX
UNITS
LOGIC INPUTS
Input Voltage, Logic 1
Input Voltage, Logic 0
VIH
2.0
V+
0.8
V
V
VIL
-0.3
Input Current
VIN = 0 to 5V
IIH
-10
10
uA
ARINC OUTPUTS
ARINC Output Voltage
(Differential)
Differential Output Voltage
One
= 429OUTA – 429OUTB.
No Load.
VDIF1
VDIFnull
VDIF0
9.0
-0.5
10.0
0
11.0
+0.5
-9.0
V
V
V
Null
Zero
-11.0
-10.0
ARINC Output Voltage
Referenced to Ground
No Load.
(Single Ended)
Hi
VoHI
Vonull,
VoLO
4.5
-0.25
-5.5
5.0
0
5.5
+0.25
-4.5
V
V
V
Null
Lo
-5.0
ARINC Output Short Circuit Outputs shorted to Ground
Current
with Rout = 37ohms
IscLO
IscHI
133
mA
mA
-133
Output Resistance:
DEI5070
Rout
37.5
27.5
7.5
Ohms
Ohms
Ohms
Room Temperature
DEI5071
DEI5072
Output Slew Rate
Hi Speed
HI/LO = 1
No Load
Trise
Tfall
10% to 90% voltage
amplitude of differential
output.
1.0
5.0
1.5
2.0
us
Output Slew Rate
Lo Speed
HI/LO = 0
No Load
Trise
Tfall
10% to 90% voltage
amplitude of differential
output.
10.0
15.0
200
us
ns
Output skew time between AHI/LO = 1
and B outputs.
Measured at 50% voltage
amplitude of both outputs.
Tskew
SUPPLY CURRENT
Quiescent Operating Supply
V+ =5V, V- = -5V
Current:
IV+
HI/LO = 0 or 1
TTLIN0=TTLIN1= 0V
No Load
IV+
IV-
-
6
10
-
mA
mA
IV-
-10
-6
© 2011 Device Engineering Inc
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DESIGN CONSIDERATIONS
Power Supplies and Bypass Capacitors
The DEI507X Line Driver operates from ±5V dual supplies. Proper bypassing capacitor ensures stability while driving large
capacitive loads. The Line Driver requires a minimum of a 0.1uF bypass capacitor placed as close as possible to the V+ and V-
pins.
Transient Voltage Protection
The DEI507X Line Driver requires external
V+
components to achieve immunity from surges such
DEI507xA
as those defined by DO160D Section 22, “Lightning
Induced Transient Susceptibility”. Typical surge
protection includes silicon Transient Voltage
R2
R1
OUTPUT
AMP
OUTA
Suppressor (TVS) devices and may include part of
the 37.5 Ohm output resistance as external resistors
to limit the surge current.
Rout:
7.5, 27.5,
37.5 Ohms
V-
TVS
to
The 507X has a robust output stage which includes
large driver devices and clamp diodes to the V+ and
V- power rails as shown in Figure 2. It withstands
surge currents of ±0.5A for 175us without damage
when powered with ±5V supplies. At that surge
current, the diodes clamp at ~1V above (below) the
V+ ( V-) supply rail. ~350mA flows to the V- (V+)
supply through the output amplifier, and ~150ma
flows to the V+ (V-) supply through the clamp
diode. The outputs may be damaged by surges
greater than 1A / 175uS. At that current, the diodes
clamp at ~1.8V above (below) the supply.
ARINC DATA BUS
Twisted Shielded Pair cable
V+
OUTPUT
AMP
OUTB
V-
Figure 2 Surge Protection Network
The external lightning protection network should be designed to meet the specific requirements and constraints of the
application equipment. The protection network should limit the OUTA/B pin surge current to the 0.5A / 175us maximum. The
generalized circuit of Figure 2 represents several TVS protection network options:
•
•
The on-chip Rout value is 7.5, 27.5, or 37.5 Ohms depending on the 5070 – 5072 part number
Select the total output resistance, Rout + R1 + R2, = 37.5 Ohms to meet ARINC bus requirements
o
o
o
Select R1 = 20Ω, R2 = 10Ω, Rout = 7.5Ω to use low TVS surge current rating (small TVS devices)
Select R1 = 0Ω, Rout + R2 = 37.5Ω to use high TVS clamp voltage (20V + V+/-)
If the V+/V- supplies are un-powered or below operating voltage during the surge event, large currents may flow
through the internal clamp diodes and damage the driver. If the application requires lightning immunity while un-
powered, Select R1 = 0Ω, Rout + R2 = 37.5Ω, and select the TVS clamp voltage for <20V.
•
Select TVS devices for the following
o
TVS Surge power/current rating must withstand the application requirements for Lightning Induced Transient
Levels and Waveforms. Microsemi Corporation publishes an application note specific to the DO160 lightning
requirements, available at: http://www.microsemi.com/micnotes/126.pdf
o
Select low capacitance TVS devices to minimize the load on the line driver. (Examples: Microsemi LC and
HSMBJSA series TVS) This is a priority for Hi Speed ARINC applications where the low capacitance is
important for optimum signal integrity and power consumption. Note that the maximum total capacitance on the
ARINC bus is 30nF line to line.
o
Select the TVS clamp voltage at the lightning surge conditions such that the voltage/current into the 507X OUT
pin is within the safe region.
•
If R1 is used to limit the TVS surge current, the resistor must withstand the surge current and voltage.
© 2011 Device Engineering Inc
Page 6 of 11
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Alternate protection methods may be appropriate in some applications.
•
•
External clamp diodes to the supply rails may be used to shunt surge current to the supply rails rather than to Ground.
PTC “resetable fuses” may be used for R1 to protect the driver and TVS from shorts to 28V aircraft power.
Some general considerations related to Lightning Immunity:
•
Analyze the TVS high current signal and ground return path to insure adequate surge current capability. The IR
voltage and L*di/dt voltage in the ground return will add additional stress beyond the TVS clamp voltage.
Observe suitable PCB design rules for traces subject to high voltage and high current surges.
When possible, locate TVS devices close to the equipment connector to minimize the length of the surge
voltage/current traces within the equipment.
The shields of ARINC 429 data bus cables should be terminated to aircraft ground at all ends and at all bulkhead
disconnects.
•
•
•
Thermal Management
Good thermal management is fundamental to Line Driver device reliability. It is particularly important in designs operating at
the HI speed data rate (100KBS) with high capacitive loads as this produces maximum power dissipation. While the 507X
device will function at a junction temperature (Tj) above 190°C, it is inappropriate to continuously operate the plastic package
above 150°C. Like all microcircuits, long term reliability is improved with lower operating temperatures.
The Line Driver’s operating Tj is determined by internal power dissipation, package thermal resistance, and ambient
temperature. The internal power dissipation (Pd) varies greatly with several variables:
•
•
Data Rate – The Hi Speed (100kbs) rate produces maximum power dissipation
Load – The maximum ARINC 429 load is 30nF||400 Ω line-to-line. Many applications only drive a fraction of the
full load.
•
Data Duty Cycle – ARINC bus activity, averaged over 10 seconds = Bits transmitted / total possible bits. Many
applications are active <70%.
•
•
Supply Voltage +V / -V supplies are ±5V
Rout configuration – The power dissipated in the two 37.5Ω output resistors is internal to the IC for the 5070 and
external for the 5072.
The internal power dissipation for 100kbs applications can be estimated from Figures 4-7. Power dissipation for low speed
operation (12.5kbs) is normally not an issue, so is not considered here. The curves in indicate power dissipation for various
loads, supply voltage, and Rout configuration. It represents Pd for 100% Data Duty Cycle (DDC) at 100KBS with no word
gap null times. Thus the indicated Pd values are considered maximum values and should be reduced to account for the Data
Duty Cycle as follows:
•
•
•
Estimate DDC = total bits transmitted in 10 sec period / 1,000,000
= 32 x total ARINC words transmitted in 10 sec period / 1,000,000
Select an indicated Pd for the application supply voltage and load. This may involve estimating the Line Driver’s load
and interpolating between the curves.
Calculate adjusted Pd = DDC * (Pd - 0.1) + 0.1 (W)
The operating junction temperature is calculated as follows:
Tj = Ta + Pd*Θja
where
Tj = junction temperature (°C)
Ta = Ambient temperature (°C)
Pd = Internal power dissipation (W)
Θja = IC package thermal resistance from junction to ambient (°C/W). Refer to package details.
© 2011 Device Engineering Inc
Page 7 of 11
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The ARINC 429 Line Driver outputs may be subject to short circuit conditions due to cable wiring errors or faults which
typically occur during equipment test and aircraft installation environments. The common cases are one or both outputs
shorted to Ground, or both outputs shorted together. These conditions may cause considerable internal power dissipation
depending on the following:
•
Data Duty Cycle – The line-to-line and line-to-Ground shorts cause little or no power dissipation when the outputs are
in the Null state. However when the output is driving a HI/LO state, the short circuit current is limited by the 37.5Ω
Rout at about ~133mA. This is modulated by the ARINC waveform, producing an effective current of ~88mA*
DDC. This current causes heating in the output amplifier and Rout resistor.
•
•
Supply Voltage – A lower supply voltage results in lower Pd during short circuit conditions. The internal Pd for both
outputs shorted while operating at 100% DDC is ~750mW with ±5V supplies, but is reduced to ~650mW with ±4.8V
supplies. This is for 37.5Ω Rout configurations.
Rout configuration – Each of the two 37.5Ω Rout resistors dissipates ~0.7W when shorted at 100% DDC. This power
is dissipated in the external resistors for the 5072 parts, and internal to the IC for the 5070 parts. Thus the 5072 have a
lower Tj and are more tolerant to short circuit conditions.
The PCB design and layout is a significant factor in determining thermal resistance (Θja) of the Line Driver IC package. Use
maximum trace width on all power and signal connections at the IC. These traces serve as heat spreaders which improve heat
flow from the IC leads. The exposed heat sink pad of the SOIC package should be soldered to a heat-spreader land pattern on
the PCB. The IC exposed pad is electrically isolated, so the PCB land may be at any potential; typically Ground for the best
heat sink. Maximize the PCB land size by extending it beyond the IC outline if possible. A grid of thermal VIAs, which drop
down and connect to the buried copper plane(s), should be placed under the heat-spreader land. A typical VIA grid is 12mil
holes on a 50mil pitch. The barrel is plated to about 1.0 ounce copper. Use as many VIAs as space allows. VIAs should be
plugged to prevent voids being formed between the exposed pad and PCB heat-spreader land due to solder escaping by the
capillary effect. This can be avoided by tenting the VIAs with solder mask.
Figure 3 Example of a Thermal VIA Land Pattern
© 2011 Device Engineering Inc
Page 8 of 11
DS-MW-05070-01 Rev D
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450.0
400.0
350.0
300.0
250.0
200.0
150.0
Full Load
2/3 Load
1/3 Load
Full Load
2/3 Load
1/3 Load
500.0
450.0
400.0
350.0
300.0
250.0
200.0
150.0
4.7
4.8
4.9
5
5.1
5.2
5.3
5.4
4.7
4.8
4.9
5
5.1
5.2
5.3
5.4
Supply Voltage (VDD/VSS)
Supply Voltage (VDD/VSS)
Figure 4 5070 Power Dissipation Comparison
Figure 5 5071 Power Dissipation Comparison
300.0
Full Load
Full Load
2/3 Load
1/3 Load
1050
950
850
750
650
550
450
350
280.0
260.0
240.0
220.0
200.0
180.0
160.0
140.0
120.0
100.0
2/3 Load
1/3 Load
4.7
4.8
4.9
5
5.1
5.2
5.3
5.4
4.7
4.8
4.9
5
5.1
5.2
5.3
5.4
Supply Voltage (VDD/VSS)
Supply Voltage (VDD/VSS)
Figure 6 5072 Power Dissipation Comparison
Figure 7 5270 Power Dissipation Comparison (2 chan,
OUT_27)
Note:
1. 100% Data Duty Cycle.
2. Full Load: 400 Ω//30nF, Mid Load: 600 Ω//20nF, Light Load: 1200 Ω//10nF
© 2011 Device Engineering Inc
Page 9 of 11
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PACKAGE DESCRIPTIONS
Table 8 Package Characteristics
PACKAGE TYPE PACKAGE THERMAL
JEDEC MOISTURE
SENSITIVITY LEVEL
& PEAK BODY
TEMP
LEAD FINISH
MATERIAL /
JEDEC Pb-Free
CODE
Pb Free
REF
RESIST.
θJC / θJA
(ºC/W)
DESIGNATION
8L EP SOIC
8 EP
10 / 49
(1)
MSL 1
260ºC
NiPdAu
e4
RoHS
SOIC G
Compliant
38L 5X7 MLPQ
38 5X7 I
MLPQ G
8 / 34
(1)
MSL 1
260ºC
NiPdAu
e4
RoHS
Compliant
Notes:
1. θJA with the exposed pad soldered to a PCB land with thermal vias connected to an internal ground plane
which is one of the 2 center layers on a 4 layer board .
8 Lead EP SOIC
© 2011 Device Engineering Inc
Page 10 of 11
DS-MW-05070-01 Rev D
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38 Lead MLPQ 5.0 x 7.0
2.50 BSC
5.00 BSC
37
38
TOP VIEW
1
2
Index
7.00 BSC
3.50 BSC
0.80
1.00
SIDE VIEW
0.20 REF
0.05 MAX
Seating
Plane
5.00
5.25
2.50
2.62
Index
2
1
0.25 BSC
BOTTOM VIEW
1.50
1.62
36
0.50 BSC
3.00 BSC
3.00
3.25
0.30
0.50
Exposed Pad
0.18
0.30
5.50 BSC
Dimensions in mm
ORDERING INFORMATION
Part Number
DEI5070-SES-G
DEI5071-SES-G
DEI5072-SES-G
DEI5270-MES-G
DEI5070-SMS-G
DEI5071-SMS-G
DEI5072-SMS-G
DEI5270-MMS-G
Marking
Package
8 EP SOIC G
8 EP SOIC G
8 EP SOIC G
38 5X7 I MLPQ G
8 EP SOIC G
8 EP SOIC G
8 EP SOIC G
38 5X7 I MLPQ G
Output Resistor
37.5 Ohm
Temperature
-55 / +85 ºC
-55 / +85 ºC
-55 / +85 ºC
-55 / +85 ºC
-55 / +125 ºC
-55 / +125 ºC
-55 / +125 ºC
-55 / +125 ºC
DEI5070 / ES
DEI5071 / ES
DEI5072 / ES
DEI5270 MES
DEI5070 / MS
DEI5071 / MS
DEI5072 / MS
DEI5270MMS
27.5 Ohm
7.5 Ohm
7.5/27.5/37.5 Ohm
37.5 Ohm
27.5 Ohm
7.5 Ohm
7.5/27.5/37.5 Ohm
DEI reserves the right to make changes to any products or specifications herein. DEI makes no warranty, representation, or guarantee
regarding suitability of its products for any particular purpose.
© 2011 Device Engineering Inc
Page 11 of 11
DS-MW-05070-01 Rev D
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