AT25PE16-SSHF-T [DIALOG]
16-Mbit DataFlash-L Page Erase Serial Flash Memory;
| 型号： | AT25PE16-SSHF-T |
| 厂家： | 
Dialog Semiconductor |
| 描述： | 16-Mbit DataFlash-L Page Erase Serial Flash Memory |
| 文件： | 总63页 (文件大小：922K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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AT25PE16
16-Mbit DataFlash-L
Page Erase Serial Flash Memory
DATASHEET
Features
ò
ò
Single 2.3V - 3.6V supply
Serial Peripheral Interface (SPI) compatible
ò
Supports SPI modes 0 and 3
ò
Supports RapidS™ operation
ò
ò
Continuous read capability through entire array
ò
ò
ò
Up to 85MHz
Low-power read option up to 15MHz
Clock-to-output time (tV) of 6ns maximum
User configurable page size
ò
512 bytes per page (default)
ò
528 bytes per page (customer selectable option)
ò
ò
Two fully independent SRAM data buffers (512/528 bytes)
Allows receiving data while reprogramming the main memory array
Flexible programming options
ò
ò
ò
ò
Byte/Page Program (1 to 512/528 bytes) directly into main memory
Buffer Write
Buffer to Main Memory Page Program
ò
Flexible erase options
ò
ò
ò
ò
Page Erase (512/528 bytes)
Block Erase (4KB)
Sector Erase (128KB)
Chip Erase (16-Mbits)
ò
128-byte Security Register
128 bytes factory programmed with a unique identifier
ò
ò
ò
ò
Hardware and software controlled reset options
JEDEC Standard Manufacturer and Device ID Read
Low-power dissipation
ò
ò
ò
ò
300nA Ultra-Deep Power-Down current (typical)
5µA Deep Power-Down current (typical)
25µA Standby current (typical)
7mA Active Read current (typical)
ò
ò
ò
ò
Endurance: 100,000 program/erase cycles per page minimum
Data retention: 20 years
Complies with full industrial temperature range
Green (Pb/Halide-free/RoHS compliant) packaging options
ò
8-lead SOIC (0.150" wide and 0.208" wide)
8-pad Ultra-thin DFN (5 x 6 x 0.6mm)
ò
DS-25PE16-143C–8/2018
Description
The Adesto® AT25PE16 is a 2.3V or 2.5V minimum, serial-interface sequential access Flash memory ideally suited for a
wide variety of digital voice, image, program code, and data storage applications. The AT25PE16 also supports the
RapidS serial interface for applications requiring very high speed operation. Its 17,301,504 bits of memory are organized
as 4,096 pages of 512 bytes (default) or 528 bytes (customer option) each. In addition to the main memory, the
AT25PE16 also contains two SRAM buffers of 512/528 bytes each. The buffers allow receiving of data while a page in
the main memory is being reprogrammed. Interleaving between both buffers can dramatically increase a system's ability
to write a continuous data stream. In addition, the SRAM buffers can be used as additional system scratch pad memory,
and E2PROM emulation (bit or byte alterability) can be easily handled with a self-contained three step read-modify-write
operation.
Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel interface, the
Adesto DataFlash-L® uses a serial interface to sequentially access its data. The simple sequential access dramatically
reduces active pin count, facilitates simplified hardware layout, increases system reliability, minimizes switching noise,
and reduces package size. The device is optimized for use in many commercial and industrial applications where
high-density, low-pin count, low-voltage, and low-power are essential.
To allow for simple in-system re-programmability, the AT25PE16 does not require high input voltages for programming.
The device operates from a single 2.3V to 3.6V or 2.5V to 3.6V power supply for the erase and program and read
operations. The AT25PE16 is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of
the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK).
All programming and erase cycles are self-timed.
1.
Pin Configurations and Pinouts
Figure 1-1. Pinouts
8-lead SOIC
Top View
8-pad UDFN
Top View
(through package)
CS
SO
1
2
3
4
8
7
6
5
Vcc
CS
SO
WP
1
2
3
4
8
7
6
5
Vcc
RESET
SCK
SI
RESET
SCK
SI
WP
GND
GND
Note: 1. The metal pad on the bottom of the UDFN package is not internally connected to a voltage potential.
This pad can be a “no connect” or connected to GND.
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Table 1-1. Pin Configurations
Asserted
State
Symbol
Name and Function
Type
Chip Select: Asserting the CS pin selects the device. When the CS pin is deasserted, the
device will be deselected and normally be placed in the standby mode (not Deep Power-Down
mode) and the output pin (SO) will be in a high-impedance state. When the device is
deselected, data will not be accepted on the input pin (SI).
CS
Low
Input
A high-to-low transition on the CS pin is required to start an operation and a low-to-high
transition is required to end an operation. When ending an internally self-timed operation such
as a program or erase cycle, the device will not enter the standby mode until the completion of
the operation.
Serial Clock: This pin is used to provide a clock to the device and is used to control the flow of
data to and from the device. Command, address, and input data present on the SI pin is
always latched on the rising edge of SCK, while output data on the SO pin is always clocked
out on the falling edge of SCK.
SCK
—
Input
Serial Input: The SI pin is used to shift data into the device. The SI pin is used for all data input
including command and address sequences. Data on the SI pin is always latched on the rising
edge of SCK. Data present on the SI pin will be ignored whenever the device is deselected (CS
is deasserted).
SI
—
—
Input
Serial Output: The SO pin is used to shift data out from the device. Data on the SO pin is
always clocked out on the falling edge of SCK. The SO pin will be in a high-impedance state
whenever the device is deselected (CS is deasserted).
SO
Output
Write Protect: When the WP pin is asserted, all sectors specified for protection by the Sector
Protection Register will be protected against program and erase operations regardless of
whether the Enable Sector Protection command has been issued or not. The WP pin functions
independently of the software controlled protection method. After the WP pin goes low, the
contents of the Sector Protection Register cannot be modified.
WP
If a program or erase command is issued to the device while the WP pin is asserted, the device
will simply ignore the command and perform no operation. The device will return to the idle
state once the CS pin has been deasserted.
Low
Input
The WP pin is internally pulled-high and may be left floating if hardware controlled protection
will not be used. However, it is recommended that the WP pin also be externally connected to
VCC whenever possible.
Reset: A low state on the reset pin (RESET) will terminate the operation in progress and reset
the internal state machine to an idle state. The device will remain in the reset condition as long
as a low level is present on the RESET pin. Normal operation can resume once the RESET pin
is brought back to a high level.
RESET
Low
Input
The device incorporates an internal power-on reset circuit, so there are no restrictions on the
RESET pin during power-on sequences. If this pin and feature is not utilized, then it is
recommended that the RESET pin be driven high externally.
Device Power Supply: The VCC pin is used to supply the source voltage to the device.
Operations at invalid VCC voltages may produce spurious results and should not be attempted.
VCC
—
—
Power
Ground: The ground reference for the power supply. GND should be connected to the system
ground.
GND
Ground
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2.
Block Diagram
Figure 2-1. Block Diagram
WP
Flash Memory Array
Page (512/528 bytes)
Buffer 1 (512/528 bytes)
Buffer 2 (512/528 bytes)
SCK
CS
I/O Interface
RESET
V
CC
GND
SI
SO
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3.
Memory Array
To provide optimal flexibility, the AT25PE16 memory array is divided into three levels of granularity comprising of sectors,
blocks, and pages. Figure 3-1, Memory Architecture Diagram illustrates the breakdown of each level and details the
number of pages per sector and block. Program operations to the DataFlash-L can be done at the full page level or at the
byte level (a variable number of bytes). The erase operations can be performed at the chip, sector, block, or page level.
Figure 3-1. Memory Architecture Diagram
Sector Architecture
Block Architecture
Page Architecture
Block 0
Block 1
Block 2
8 Pages
Page 0
Page 1
Sector 0a
Sector 0a = 8 pages
4,096/4,224 bytes
Sector 0b = 248 pages
126,976/130,944 bytes
Page 6
Page 7
Page 8
Page 9
Block 30
Block 31
Block 32
Block 33
Sector 1 = 256 pages
131,072 /135,168 bytes
Sector 2 = 256 pages
131,072/135,168 bytes
Page 14
Page 15
Page 16
Page 17
Page 18
Block 62
Block 63
Block 64
Block 65
Sector 14 = 256 pages
131,072/135,168 bytes
Sector 15 = 256 pages
131,072/135,168 bytes
Block 510
Block 511
Page 4,094
Page 4,095
Block = 4,096/4,224 bytes
Page = 512/528 bytes
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4.
Device Operation
The device operation is controlled by instructions from the host processor. The list of instructions and their associated
opcodes are contained in Table 15-1 on page 34 through Table 15-4 on page 35. A valid instruction starts with the falling
edge of CS followed by the appropriate 8-bit opcode and the desired buffer or main memory address location. While the
CS pin is low, toggling the SCK pin controls the loading of the opcode and the desired buffer or main memory address
location through the SI (Serial Input) pin. All instructions, addresses, and data are transferred with the Most Significant
Bit (MSB) first.
Three address bytes are used to address memory locations in either the main memory array or in one of the SRAM
buffers. The three address bytes will be comprised of a number of dummy bits and a number of actual device address
bits, with the number of dummy bits varying depending on the operation being performed and the selected device page
size. Buffer addressing for the optional DataFlash-L page size (528 bytes) is referenced in the datasheet using the
terminology BFA9 - BFA0 to denote the 10 address bits required to designate a byte address within a buffer. The main
memory addressing is referenced using the terminology PA11 - PA0 and BA9 - BA0, where PA11 - PA0 denotes the
12 address bits required to designate a page address, and BA9 - BA0 denotes the 10 address bits required to designate
a byte address within the page. Therefore, when using the optional DataFlash-L page size, a total of 22 address bits are
used.
For the default page size (512 Bytes), the buffer addressing is referenced in the datasheet using the conventional
terminology BFA8 - BFA0 to denote the nine address bits required to designate a byte address within a buffer. Main
memory addressing is referenced using the terminology A20 - A0, where A20 - A9 denotes the 12 address bits required
to designate a page address, and A8 - A0 denotes the nine address bits required to designate a byte address within a
page. Therefore, when using the default page size, a total of 21 address bits are used.
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5.
Read Commands
By specifying the appropriate opcode, data can be read from the main memory or from either one of the two SRAM data
buffers. The DataFlash-L supports RapidS protocols for Mode 0 and Mode 3. Please see Section 25., Detailed Bit-level
Read Waveforms: RapidS Mode 0/Mode 3 diagrams in this datasheet for details on the clock cycle sequences for each
mode.
5.1
Continuous Array Read (Legacy Command: E8h Opcode)
By supplying an initial starting address for the main memory array, the Continuous Array Read command can be utilized
to sequentially read a continuous stream of data from the device by simply providing a clock signal; no additional
addressing information or control signals need to be provided. The DataFlash-L incorporates an internal address counter
that will automatically increment on every clock cycle, allowing one continuous read from memory to be performed
without the need for additional address sequences. To perform a Continuous Array Read using the optional DataFlash-L
page size (528 bytes), an opcode of E8h must be clocked into the device followed by three address bytes (which
comprise the 22-bit page and byte address sequence) and four dummy bytes. The first 12 bits (PA11 - PA0) of the 22-bit
address sequence specify which page of the main memory array to read and the last 10 bits (BA9 - BA0) of the 22-bit
address sequence specify the starting byte address within the page. To perform a Continuous Array Read using the
default page size (512 bytes), an opcode of E8h must be clocked into the device followed by three address bytes and
four dummy bytes. The first 12 bits (A20 - A9) of the 21-bit address sequence specify which page of the main memory
array to read and the last nine bits (A8 - A0) of the 21-bit address sequence specify the starting byte address within the
page. The dummy bytes that follow the address bytes are needed to initialize the read operation. Following the dummy
bytes, additional clock pulses on the SCK pin will result in data being output on the SO (serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bytes, the dummy bytes, and the reading of
data. When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue
reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover
from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read,
the device will continue reading back at the beginning of the first page of memory. As with crossing over page
boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum
SCK frequency allowable for the Continuous Array Read is defined by the fCAR1 specification. The Continuous Array
Read bypasses the data buffers and leaves the contents of the buffers unchanged.
Warning:
This command is not recommended for new designs.
5.2
Continuous Array Read (High Frequency Mode: 1Bh Opcode)
This command can be used to read the main memory array sequentially at the highest possible operating clock
frequency up to the maximum specified by fCAR4. To perform a Continuous Array Read using the optional DataFlash-L
page size (528 bytes), the CS pin must first be asserted, and then an opcode of 1Bh must be clocked into the device
followed by three address bytes and two dummy bytes. The first 12 bits (PA11 - PA0) of the 22-bit address sequence
specify which page of the main memory array to read and the last 10 bits (BA9 - BA0) of the 22-bit address sequence
specify the starting byte address within the page. To perform a Continuous Array Read using the default page size (512
bytes), the opcode 1Bh must be clocked into the device followed by three address bytes (A20 - A0) and two dummy
bytes. Following the dummy bytes, additional clock pulses on the SCK pin will result in data being output on the SO
(Serial Output) pin.
The CS pin must remain low during the loading of the opcode, the address bytes, the dummy bytes, and the reading of
data. When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue
reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover
from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read,
the device will continue reading back at the beginning of the first page of memory. As with crossing over page
boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array.
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A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum
SCK frequency allowable for the Continuous Array Read is defined by the fCAR1 specification. The Continuous Array
Read bypasses both data buffers and leaves the contents of the buffers unchanged.
5.3
Continuous Array Read (High Frequency Mode: 0Bh Opcode)
This command can be used to read the main memory array sequentially at higher clock frequencies up to the maximum
specified by fCAR1. To perform a Continuous Array Read using the optional DataFlash-L page size (528 bytes), the CS pin
must first be asserted, and then an opcode of 0Bh must be clocked into the device followed by three address bytes and
one dummy byte. The first 12 bits (PA11 - PA0) of the 22-bit address sequence specify which page of the main memory
array to read and the last 10 bits (BA9 - BA0) of the 22-bit address sequence specify the starting byte address within the
page. To perform a Continuous Array Read using the default page size (512 bytes), the opcode 0Bh must be clocked into
the device followed by three address bytes (A20 - A0) and one dummy byte. Following the dummy byte, additional clock
pulses on the SCK pin will result in data being output on the SO pin.
The CS pin must remain low during the loading of the opcode, the address bytes, the dummy byte, and the reading of
data. When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue
reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover
from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read,
the device will continue reading back at the beginning of the first page of memory. As with crossing over page
boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum
SCK frequency allowable for the Continuous Array Read is defined by the fCAR1 specification. The Continuous Array
Read bypasses both data buffers and leaves the contents of the buffers unchanged.
5.4
Continuous Array Read (Low Frequency Mode: 03h Opcode)
This command can be used to read the main memory array sequentially at lower clock frequencies up to maximum
specified by fCAR2. Unlike the previously described read commands, this Continuous Array Read command for the lower
clock frequencies does not require the clocking in of dummy bytes after the address byte sequence. To perform a
Continuous Array Read using the optional DataFlash-L page size (528 bytes), the CS pin must first be asserted, and then
an opcode of 03h must be clocked into the device followed by three address bytes. The first 12 bits (PA11 - PA0) of the
22-bit address sequence specify which page of the main memory array to read and the last 10 bits (BA9 - BA0) of the 22-
bit address sequence specify the starting byte address within the page. To perform a Continuous Array Read using the
default page size (512 bytes), the opcode 03h must be clocked into the device followed by three address bytes (A20 -
A0). Following the address bytes, additional clock pulses on the SCK pin will result in data being output on the SO pin.
The CS pin must remain low during the loading of the opcode, the address bytes, and the reading of data. When the end
of a page in the main memory is reached during a Continuous Array Read, the device will continue reading at the
beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of
one page to the beginning of the next page). When the last bit in the main memory array has been read, the device will
continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will
be incurred when wrapping around from the end of the array to the beginning of the array.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum
SCK frequency allowable for the Continuous Array Read is defined by the fCAR2 specification. The Continuous Array
Read bypasses both data buffers and leaves the contents of the buffers unchanged.
5.5
Continuous Array Read (Low Power Mode: 01h Opcode)
This command is ideal for applications that want to minimize power consumption and do not need to read the memory
array at high frequencies. Like the 03h opcode, this Continuous Array Read command allows reading the main memory
array sequentially without the need for dummy bytes to be clocked in after the address byte sequence. The memory can
be read at clock frequencies up to maximum specified by fCAR3. To perform a Continuous Array Read using the optional
DataFlash-L page size (528 bytes), the CS pin must first be asserted, and then an opcode of 01h must be clocked into
the device followed by three address bytes. The first 12 bits (PA11 - PA0) of the 22-bit address sequence specify which
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page of the main memory array to read and the last 10 bits (BA9 - BA0) of the 22-bit address sequence specify the
starting byte address within the page. To perform a Continuous Array Read using the default page size (512 bytes), the
opcode 01h must be clocked into the device followed by three address bytes (A20 - A0). Following the address bytes,
additional clock pulses on the SCK pin will result in data being output on the SO pin.
The CS pin must remain low during the loading of the opcode, the address bytes, and the reading of data. When the end
of a page in the main memory is reached during a Continuous Array Read, the device will continue reading at the
beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of
one page to the beginning of the next page). When the last bit in the main memory array has been read, the device will
continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will
be incurred when wrapping around from the end of the array to the beginning of the array.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum
SCK frequency allowable for the Continuous Array Read is defined by the fCAR3 specification. The Continuous Array
Read bypasses both data buffers and leaves the contents of the buffers unchanged.
5.6
Main Memory Page Read
A Main Memory Page Read allows the reading of data directly from a single page in the main memory, bypassing both of
the data buffers and leaving the contents of the buffers unchanged. To start a page read using the optional DataFlash-L
page size (528 bytes), an opcode of D2h must be clocked into the device followed by three address bytes (which
comprise the 22-bit page and byte address sequence) and four dummy bytes. The first 12 bits
(PA11 - PA0) of the 22-bit address sequence specify the page in main memory to be read and the last 10 bits
(BA9 - BA0) of the 22-bit address sequence specify the starting byte address within that page. To start a page read using
the default page size (512 bytes), the opcode D2h must be clocked into the device followed by three address bytes and
four dummy bytes. The first 12 bits (A20 - A9) of the 21-bit address sequence specify which page of the main memory
array to read, and the last nine bits (A8 - A0) of the 21-bit address sequence specify the starting byte address within that
page. The dummy bytes that follow the address bytes are sent to initialize the read operation. Following the dummy
bytes, the additional pulses on SCK result in data being output on the SO (serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bytes, the dummy bytes, and the reading of
data. Unlike the Continuous Array Read command, when the end of a page in main memory is reached, the device will
continue reading back at the beginning of the same page rather than the beginning of the next page.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum
SCK frequency allowable for the Main Memory Page Read is defined by the fSCK specification. The Main Memory Page
Read bypasses both data buffers and leaves the contents of the buffers unchanged.
5.7
Buffer Read
The SRAM data buffers can be accessed independently from the main memory array, and utilizing the Buffer Read
command allows data to be sequentially read directly from either one of the buffers. Four opcodes, D4h or D1h for Buffer
1 and D6h or D3h for Buffer 2, can be used for the Buffer Read command. The use of each opcode depends on the
maximum SCK frequency that will be used to read data from the buffers. The D4h and D6h opcode can be used at any
SCK frequency up to the maximum specified by fCAR1 while the D1h and D3h opcode can be used for lower frequency
read operations up to the maximum specified by fCAR2
.
To perform a Buffer Read using the standard DataFlash-L buffer size (528 bytes), the opcode must be clocked into the
device followed by three address bytes comprised of 14 dummy bits and 10 buffer address bits (BFA9 - BFA0). To
perform a Buffer Read using the default buffer size (512 bytes), the opcode must be clocked into the device followed by
three address bytes comprised of 15 dummy bits and nine buffer address bits (BFA8 - BFA0). Following the address
bytes, one dummy byte must be clocked into the device to initialize the read operation if using opcodes D4h or D6h. The
CS pin must remain low during the loading of the opcode, the address bytes, the dummy byte (if using opcodes D4h or
D6h), and the reading of data. When the end of a buffer is reached, the device will continue reading back at the beginning
of the buffer. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO).
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6.
Program and Erase Commands
6.1
Buffer Write
Utilizing the Buffer Write command allows data clocked in from the SI pin to be written directly into either one of the
SRAM data buffers.
To load data into a buffer using the standard DataFlash-L buffer size (528 bytes), an opcode of 84h for Buffer 1 or 87h for
Buffer 2 must be clocked into the device followed by three address bytes comprised of 14 dummy bits and 10 buffer
address bits (BFA9 - BFA0). The 10 buffer address bits specify the first byte in the buffer to be written.
To load data into a buffer using the default buffer size (512 bytes), an opcode of 84h for Buffer 1 or 87h for Buffer 2, must
be clocked into the device followed by 15 dummy bits and nine buffer address bits (BFA8 - BFA0). The nine buffer
address bits specify the first byte in the buffer to be written.
After the last address byte has been clocked into the device, data can then be clocked in on subsequent clock cycles. If
the end of the data buffer is reached, the device will wrap around back to the beginning of the buffer. Data will continue to
be loaded into the buffer until a low-to-high transition is detected on the CS pin.
6.2
Buffer to Main Memory Page Program with Built-In Erase
The Buffer to Main Memory Page Program with Built-In Erase command allows data that is stored in one of the SRAM
buffers to be written into an erased or programmed page in the main memory array. It is not necessary to pre-erase the
page in main memory to be written because this command will automatically erase the selected page prior to the
program cycle.
To perform a Buffer to Main Memory Page Program with Built-In Erase using the optional DataFlash-L page size
(528 bytes), an opcode of 83h for Buffer 1 or 86h for Buffer 2 must be clocked into the device followed by three address
bytes comprised of two dummy bits, 12 page address bits (PA11 - PA0) that specify the page in the main memory to be
written, and 10 dummy bits.
To perform a Buffer to Main Memory Page Program with Built-In Erase using the default page size (512 bytes), an
opcode of 83h for Buffer 1 or 86h for Buffer 2 must be clocked into the device followed by three address bytes comprised
of three dummy bits, 12 page address bits (A20 - A9) that specify the page in the main memory to be written, and nine
dummy bits.
When a low-to-high transition occurs on the CS pin, the device will first erase the selected page in main memory (the
erased state is a Logic 1) and then program the data stored in the appropriate buffer into that same page in main
memory. Both the erasing and the programming of the page are internally self-timed and should take place in a
maximum time of tEP. During this time, the RDY/BUSY bit in the Status Register will indicate that the device is busy.
The device also incorporates an intelligent erase and program algorithm that can detect when a byte location fails to
erase or program properly. If an erase or programming error arises, it will be indicated by the EPE bit in the Status
Register.
6.3
Buffer to Main Memory Page Program without Built-In Erase
The Buffer to Main Memory Page Program without Built-In Erase command allows data that is stored in one of the SRAM
buffers to be written into a pre-erased page in the main memory array. It is necessary that the page in main memory to be
written be previously erased in order to avoid programming errors.
To perform a Buffer to Main Memory Page Program without Built-In Erase using the optional DataFlash-L page size (528
bytes), an opcode of 88h for Buffer 1 or 89h for Buffer 2 must be clocked into the device followed by three address bytes
comprised of two dummy bits, 12 page address bits (PA11 - PA0) that specify the page in the main memory to be written,
and 10 dummy bits.
To perform a Buffer to Main Memory Page Program using the default page size (512 bytes), an opcode of 88h for Buffer
1 or 89h for Buffer 2 must be clocked into the device followed by three address bytes comprised of three dummy bits, 12
page address bits (A20 - A9) that specify the page in the main memory to be written, and nine dummy bits.
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When a low-to-high transition occurs on the CS pin, the device will program the data stored in the appropriate buffer into
the specified page in the main memory. The page in main memory that is being programmed must have been previously
erased using one of the erase commands (Page Erase, Block Erase, Sector Erase, or Chip Erase). The programming of
the page is internally self-timed and should take place in a maximum time of tP. During this time, the RDY/BUSY bit in the
Status Register will indicate that the device is busy.
The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program
properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register.
6.4
Main Memory Page Program through Buffer with Built-In Erase
The Main Memory Page Program through Buffer with Built-In Erase command combines the Buffer Write and Buffer to
Main Memory Page Program with Built-In Erase operations into a single operation to help simplify application firmware
development. With the Main Memory Page Program through Buffer with Built-In Erase command, data is first clocked
into either Buffer 1 or Buffer 2, the addressed page in memory is then automatically erased, and then the contents of the
appropriate buffer are programmed into the just-erased main memory page.
To perform a Main Memory Page Program through Buffer using the optional DataFlash-L page size (528 bytes), an
opcode of 82h for Buffer 1 or 85h for Buffer 2 must first be clocked into the device followed by three address bytes
comprised of two dummy bits, 12 page address bits (PA11 - PA0) that specify the page in the main memory to be written,
and 10 buffer address bits (BFA9 - BFA0) that select the first byte in the buffer to be written.
To perform a Main Memory Page Program through Buffer using the default page size (512 bytes), an opcode of 82h for
Buffer 1 or 85h for Buffer 2 must first be clocked into the device followed by three address bytes comprised of three
dummy bits, 12 page address bits (A20 - A9) that specify the page in the main memory to be written, and nine buffer
address bits (BFA8 - BFA0) that select the first byte in the buffer to be written.
After all address bytes have been clocked in, the device will take data from the input pin (SI) and store it in the specified
data buffer. If the end of the buffer is reached, the device will wrap around back to the beginning of the buffer. When
there is a low-to-high transition on the CS pin, the device will first erase the selected page in main memory (the erased
state is a Logic 1) and then program the data stored in the buffer into that main memory page. Both the erasing and the
programming of the page are internally self-timed and should take place in a maximum time of tEP. During this time, the
RDY/BUSY bit in the Status Register will indicate that the device is busy.
The device also incorporates an intelligent erase and programming algorithm that can detect when a byte location fails to
erase or program properly. If an erase or program error arises, it will be indicated by the EPE bit in the Status Register.
6.5
Main Memory Byte/Page Program through Buffer 1 without Built-In Erase
The Main Memory Byte/Page Program through Buffer 1 without Built-In Erase command combines both the Buffer Write
and Buffer to Main Memory Program without Built-In Erase operations to allow any number of bytes (1 to 512/528 bytes)
to be programmed directly into previously erased locations in the main memory array. With the Main Memory Byte/Page
Program through Buffer 1 without Built-In Erase command, data is first clocked into Buffer 1, and then only the bytes
clocked into the buffer are programmed into the pre-erased byte locations in main memory. Multiple bytes up to the page
size can be entered with one command sequence.
To perform a Main Memory Byte/Page Program through Buffer 1 using the optional DataFlash-L page size (528 bytes),
an opcode of 02h must first be clocked into the device followed by three address bytes comprised of two dummy bits,
12 page address bits (PA11 - PA0) that specify the page in the main memory to be written, and 10 buffer address bits
(BFA9 - BFA0) that select the first byte in the buffer to be written. After all address bytes are clocked in, the device will
take data from the input pin (SI) and store it in Buffer 1. Any number of bytes (1 to 528) can be entered. If the end of the
buffer is reached, then the device will wrap around back to the beginning of the buffer.
To perform a Main Memory Byte/Page Program through Buffer 1 using the default page size (512 bytes), an opcode of
02h for Buffer 1 using must first be clocked into the device followed by three address bytes comprised of three dummy
bits, 12 page address bits (A20 - A9) that specify the page in the main memory to be written, and nine buffer address bits
(BFA8 - BFA0) that selects the first byte in the buffer to be written. After all address bytes are clocked in, the device will
take data from the input pin (SI) and store it in Buffer 1. Any number of bytes (1 to 512) can be entered. If the end of the
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buffer is reached, then the device will wrap around back to the beginning of the buffer. When using the default page size,
the page and buffer address bits correspond to a 21-bit logical address (A20-A0) in the main memory.
After all data bytes have been clocked into the device, a low-to-high transition on the CS pin will start the program
operation in which the device will program the data stored in Buffer 1 into the main memory array. Only the data bytes
that were clocked into the device will be programmed into the main memory.
Example: If only two data bytes were clocked into the device, then only two bytes will be programmed into main
memory and the remaining bytes in the memory page will remain in their previous state.
The CS pin must be deasserted on a byte boundary (multiples of eight bits); otherwise, the operation will be aborted and
no data will be programmed. The programming of the data bytes is internally self-timed and should take place in a
maximum time of tP (the program time will be a multiple of the tBP time depending on the number of bytes being
programmed). During this time, the RDY/BUSY bit in the Status Register will indicate that the device is busy.
The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program
properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register.
6.6
Read-Modify-Write
A completely self-contained read-modify-write operation can be performed to reprogram any number of sequential bytes
in a page in the main memory array without affecting the rest of the bytes in the same page. This command allows the
device to easily emulate an EEPROM by providing a method to modify a single byte or more in the main memory in a
single operation, without the need for pre-erasing the memory or the need for any external RAM buffers. The
Read-Modify-Write command is essentially a combination of the Main Memory Page to Buffer Transfer, Buffer Write, and
Buffer to Main Memory Page Program with Built-in Erase commands.
To perform a Read-Modify-Write using the optional DataFlash-L page size (528 bytes), an opcode of 58h for Buffer 1 or
59h for Buffer 2 must be clocked into the device followed by three address bytes comprised of 2 dummy bits, 12 page
address bits (PA11 - PA0) that specify the page in the main memory to be written, and 10 byte address bits (BA9 - BA0)
that designate the starting byte address within the page to reprogram.
To perform a Read-Modify-Write using the default page size (512 bytes), an opcode of 58h for Buffer 1 or 59h for Buffer
2 must be clocked into the device followed by three address bytes comprised of 3 dummy bits, 12 page address bits (A20
- A9) that specify the page in the main memory to be written, and 9 byte address bits (A8 - A0) designate the starting byte
address within the page to reprogram.
After the address bytes have been clocked in, any number of sequential data bytes from one to 512/528 bytes can be
clocked into the device. If the end of the buffer is reached when clocking in the data, then the device will wrap around
back to the beginning of the buffer. After all data bytes have been clocked into the device, a low-to-high transition on the
CS pin will start the self-contained, internal read-modify-write operation. Only the data bytes that were clocked into the
device will be reprogrammed in the main memory.
Example: If only one data byte was clocked into the device, then only one byte in main memory will be reprogrammed
and the remaining bytes in the main memory page will remain in their previous state.
The CS pin must be deasserted on a byte boundary (multiples of 8 bits); otherwise, the operation will be aborted and no
data will be programmed. The reprogramming of the data bytes is internally self-timed and should take place in a
maximum time of tP. During this time, the RDY/BUSY bit in the Status Register will indicate that the device is busy.
The device also incorporates an intelligent erase and programming algorithm that can detect when a byte location fails to
erase or program properly. If an erase or program error arises, it will be indicated by the EPE bit in the Status Register.
The Read-Modify-Write command uses the same opcodes as the Auto Page Rewrite command. If no data bytes are
clocked into the device, then the device will perform an Auto Page Rewrite operation. See the Auto Page Rewrite
command description on page 26 for more details.
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6.7
Page Erase
The Page Erase command can be used to individually erase any page in the main memory array allowing the Buffer to
Main Memory Page Program without Built-In Erase command or the Main Memory Byte/Page Program through Buffer 1
command to be utilized at a later time.
To perform a Page Erase with the optional DataFlash-L page size (528 bytes), an opcode of 81h must be clocked into the
device followed by three address bytes comprised of two dummy bits, 12 page address bits (PA11 - PA0) that specify the
page in the main memory to be erased, and 10 dummy bits.
To perform a Page Erase with the default page size (512 bytes), an opcode of 81h must be clocked into the device
followed by three address bytes comprised of three dummy bits, 12 page address bits (A20 - A9) that specify the page in
the main memory to be erased, and nine dummy bits.
When a low-to-high transition occurs on the CS pin, the device will erase the selected page (the erased state is a Logic
1). The erase operation is internally self-timed and should take place in a maximum time of tPE. During this time, the
RDY/BUSY bit in the Status Register will indicate that the device is busy.
The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly. If
an erase error arises, it will be indicated by the EPE bit in the Status Register.
6.8
Block Erase
The Block Erase command can be used to erase a block of eight pages at one time. This command is useful when
needing to pre-erase larger amounts of memory and is more efficient than issuing eight separate Page Erase
commands.
To perform a Block Erase with the optional DataFlash-L page size (528 bytes), an opcode of 50h must be clocked into
the device followed by three address bytes comprised of two dummy bits, nine page address bits (PA11 - PA3), and 13
dummy bits. The nine page address bits are used to specify which block of eight pages is to be erased.
To perform a Block Erase with the default page size (512 bytes), an opcode of 50h must be clocked into the device
followed by three address bytes comprised of three dummy bits, nine page address bits (A20 - A12), and 12 dummy bits.
The nine page address bits are used to specify which block of eight pages is to be erased.
When a low-to-high transition occurs on the CS pin, the device will erase the selected block of eight pages. The erase
operation is internally self-timed and should take place in a maximum time of tBE. During this time, the RDY/BUSY bit in
the Status Register will indicate that the device is busy.
The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly. If
an erase error arises, it will be indicated by the EPE bit in the Status Register.
Table 6-1. Block Erase Addressing
PA11/
A20
PA10/
A19
PA9/
A18
PA8/
A17
PA7/
A16
PA6/
A15
PA5/
A14
PA4/
A13
PA3/
A12
PA2/
A11
PA1/
A10
PA0/
A9
Block
0
0
0
0
•
0
0
0
0
•
0
0
0
0
•
0
0
0
0
•
0
0
0
0
•
0
0
0
0
•
0
0
0
0
•
0
0
1
1
•
0
1
0
1
•
X
X
X
X
•
X
X
X
X
•
X
X
X
X
•
0
1
2
3
•
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
508
509
510
511
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6.9
Sector Erase
The Sector Erase command can be used to individually erase any sector in the main memory.
The main memory array is comprised of 17 sectors, and only one sector can be erased at a time. To perform an erase of
Sector 0a or Sector 0b with the optional DataFlash-L page size (528 bytes), an opcode of 7Ch must be clocked into the
device followed by three address bytes comprised of two dummy bits, nine page address bits (PA11 - PA3), and
13 dummy bits. To perform a Sector 1-15 erase, an opcode of 7Ch must be clocked into the device followed by three
address bytes comprised of two dummy bits, four page address bits (PA11 - PA8), and 18 dummy bits.
To perform a Sector 0a or Sector 0b erase with the default page size (512 bytes), an opcode of 7Ch must be clocked into
the device followed by three address bytes comprised of three dummy bits, nine page address bits (A20 - A12), and
12 dummy bits. To perform a Sector 1-15 erase, an opcode of 7Ch must be clocked into the device followed by three
dummy bits, four page address bits (A20 - A17), and 17 dummy bits.
The page address bits are used to specify any valid address location within the sector to be erased. When a
low-to high transition occurs on the CS pin, the device will erase the selected sector. The erase operation is internally
self-timed and should take place in a maximum time of tSE. During this time, the RDY/BUSY bit in the Status Register will
indicate that the device is busy.
The device also incorporates an intelligent algorithm that can detect when a byte location fails to erase properly. If an
erase error arises, it will be indicated by the EPE bit in the Status Register.
Table 6-2. Sector Erase Addressing
PA11/ PA10/
PA9/
A18
PA8/
A17
PA7/
A16
PA6/
A15
PA5/
A14
PA4/
A13
PA3/
A12
PA2/
A11
PA1/
A10
PA0/
A9
A20
A19
Sector
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
0a
0b
1
0
0
0
0
X
X
X
X
X
X
X
X
X
X
0
0
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
12
13
14
15
6.10 Chip Erase
The Chip Erase command allows the entire main memory array to be erased can be erased at one time.
To execute the Chip Erase command, a 4-byte command sequence of C7h, 94h, 80h, and 9Ah must be clocked into the
device. Since the entire memory array is to be erased, no address bytes need to be clocked into the device, and any data
clocked in after the opcode will be ignored. After the last bit of the opcode sequence has been clocked in, the CS pin
must be deasserted to start the erase process. The erase operation is internally self-timed and should take place in a
time of tCE. During this time, the RDY/BUSY bit in the Status Register will indicate that the device is busy.
The Chip Erase command will not affect sectors that are protected or locked down; the contents of those sectors will
remain unchanged. Only those sectors that are not protected or locked down will be erased.
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The WP pin can be asserted while the device is erasing, but protection will not be activated until the internal erase cycle
completes.
The device also incorporates an intelligent algorithm that can detect when a byte location fails to erase properly. If an
erase error arises, it will be indicated by the EPE bit in the Status Register.
Table 6-3. Chip Erase Command
Command
Byte 1
Byte 2
Byte 3
Byte 4
Chip Erase
C7h
94h
80h
9Ah
Figure 6-1. Chip Erase
CS
C7h
94h
80h
9Ah
Each transition represents eight bits
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7.
Sector Protection
Two protection methods, hardware and software controlled, are provided for protection against inadvertent or erroneous
program and erase cycles. The software controlled method relies on the use of software commands to enable and
disable sector protection while the hardware controlled method employs the use of the Write Protect (WP) pin. The
selection of which sectors that are to be protected or unprotected against program and erase operations is specified in
the Nonvolatile Sector Protection Register. The status of whether or not sector protection has been enabled or disabled
by either the software or the hardware controlled methods can be determined by checking the Status Register.
7.1
Software Sector Protection
Software controlled protection is useful in applications in which the WP pin is not or cannot be controlled by a host
processor. In such instances, the WP pin may be left floating (the WP pin is internally pulled high) and sector protection
can be controlled using the Enable Sector Protection and Disable Sector Protection commands.
If the device is power cycled, then the software controlled protection will be disabled. Once the device is powered up, the
Enable Sector Protection command should be reissued if sector protection is desired and if the WP pin is not used.
7.1.1 Enable Sector Protection
Sectors specified for protection in the Sector Protection Register can be protected from program and erase operations by
issuing the Enable Sector Protection command. To enable the sector protection, a 4-byte command sequence of 3Dh,
2Ah, 7Fh, and A9h must be clocked into the device. After the last bit of the opcode sequence has been clocked in, the
CS pin must be deasserted to enable the Sector Protection.
Table 7-1. Enable Sector Protection Command
Command
Byte 1
Byte 2
Byte 3
Byte 4
Enable Sector Protection
3Dh
2Ah
7Fh
A9h
Figure 7-1. Enable Sector Protection
CS
A9h
3Dh
2Ah
7Fh
SI
Each transition represents eight bits
7.1.2 Disable Sector Protection
To disable the sector protection, a 4-byte command sequence of 3Dh, 2Ah, 7Fh, and 9Ah must be clocked into the
device. After the last bit of the opcode sequence has been clocked in, the CS pin must be deasserted to disable the
sector protection.
Table 7-2. Disable Sector Protection Command
Command
Byte 1
Byte 2
Byte 3
Byte 4
Disable Sector Protection
3Dh
2Ah
7Fh
9Ah
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Figure 7-2. Disable Sector Protection
CS
3Dh
2Ah
7Fh
9Ah
SI
Each transition represents eight bits
7.2
Hardware Controlled Protection
Sectors specified for protection in the Sector Protection Register and the Sector Protection Register itself can be
protected from program and erase operations by asserting the WP pin and keeping the pin in its asserted state. The
Sector Protection Register and any sector specified for protection cannot be erased or programmed as long as the WP
pin is asserted. In order to modify the Sector Protection Register, the WP pin must be deasserted. If the WP pin is
permanently connected to GND, then the contents of the Sector Protection Register cannot be changed. If the WP pin is
deasserted or permanently connected to VCC, then the contents of the Sector Protection Register can be modified.
The WP pin will override the software controlled protection method but only for protecting the sectors.
Example: If the sectors were not previously protected by the Enable Sector Protection command, then simply
asserting the WP pin would enable the sector protection within the maximum specified tWPE time. When the
WP pin is deasserted, however, the sector protection would no longer be enabled (after the maximum
specified tWPD time) as long as the Enable Sector Protection command was not issued while the WP pin was
asserted. If the Enable Sector Protection command was issued before or while the WP pin was asserted,
then simply deasserting the WP pin would not disable the sector protection. In this case, the Disable Sector
Protection command would need to be issued while the WP pin is deasserted to disable the sector
protection. The Disable Sector Protection command is also ignored whenever the WP pin is asserted.
A noise filter is incorporated to help protect against spurious noise that may inadvertently assert or deassert the WP pin.
Figures 7-3 and Table 7-3 detail the sector protection status for various scenarios of the WP pin, the Enable Sector
Protection command, and the Disable Sector Protection command.
Figure 7-3. WP Pin and Protection Status
1
2
3
WP
Table 7-3. WP Pin and Protection Status
Time
Sector
Protection
Status
Sector
Protection
Register
Disable Sector
Protection Command
Period
WP Pin
Enable Sector Protection Command
Command Not Issued Previously
X
Disabled
Disabled
Enabled
Enabled
Enabled
Disabled
Enabled
Read/Write
Read/Write
Read/Write
Read
1
2
3
High
—
Issue Command
Issue Command
—
Low
X
X
Command Issued During Period 1 or 2
Not Issued Yet
Issue Command
—
Read/Write
Read/Write
Read/Write
High
—
Issue Command
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7.3
Sector Protection Register
The nonvolatile Sector Protection Register specifies which sectors are to be protected or unprotected with either the
software or hardware controlled protection methods. The Sector Protection Register contains 16 bytes of data, of which
byte locations 0 through 15 contain values that specify whether Sectors 0 through 15 will be protected or unprotected.
The Sector Protection Register is user modifiable and must be erased before it can be reprogrammed. Table 7-4
illustrates the format of the Sector Protection Register.
Table 7-4. Sector Protection Register
Sector Number
Protected
0 (0a, 0b)
1 to 15
FFh
See Table 7-5
Unprotected
00h
Note: 1. The default values for bytes 0 through 15 are 00h when shipped from Adesto.
Table 7-5. Sector 0 (0a, 0b) Sector Protection Register Byte Value
Bit 7:6
Bit 5:4
Bit 3:2
Bit 1:0
Sector 0a
(Page 0-7)
Sector 0b
(Page 8-255)
Data
Value
N/A
XX
XX
XX
XX
N/A
XX
XX
XX
XX
Sectors 0a and 0b Unprotected
Protect Sector 0a
00
11
00
11
00
00
11
11
0xh
Cxh
3xh
Fxh
Protect Sector 0b
Protect Sectors 0a and 0b
Note: 1. x = Don’t care
7.3.1 Erase Sector Protection Register
In order to modify and change the values of the Sector Protection Register, it must first be erased using the Erase Sector
Protection Register command.
To erase the Sector Protection Register, a 4-byte command sequence of 3Dh, 2Ah, 7Fh, and CFh must be clocked into
the device. After the last bit of the opcode sequence has been clocked in, the CS pin must be deasserted to initiate the
internally self-timed erase cycle. The erasing of the Sector Protection Register should take place in a maximum time of
tPE. During this time, the RDY/BUSY bit in the Status Register will indicate that the device is busy. If the device is
powered-down before the completion of the erase cycle, then the contents of the Sector Protection Register cannot be
guaranteed.
The Sector Protection Register can be erased with sector protection enabled or disabled. Since the erased state (FFh) of
each byte in the Sector Protection Register is used to indicate that a sector is specified for protection, leaving the sector
protection enabled during the erasing of the register allows the protection scheme to be more effective in the prevention
of accidental programming or erasing of the device. If for some reason an erroneous program or erase command is sent
to the device immediately after erasing the Sector Protection Register and before the register can be reprogrammed,
then the erroneous program or erase command will not be processed because all sectors would be protected.
Table 7-6. Erase Sector Protection Register Command
Command
Byte 1
Byte 2
Byte 3
Byte 4
Erase Sector Protection Register
3Dh
2Ah
7Fh
CFh
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Figure 7-4. Erase Sector Protection Register
CS
SI
3Dh
2Ah
7Fh
CFh
Each transition represents eight bits
7.3.2 Program Sector Protection Register
Once the Sector Protection Register has been erased, it can be reprogrammed using the Program Sector Protection
Register command.
To program the Sector Protection Register, a 4-byte command sequence of 3Dh, 2Ah, 7Fh, and FCh must be clocked
into the device followed by 16 bytes of data corresponding to Sectors 0 through 15. After the last bit of the opcode
sequence and data have been clocked in, the CS pin must be deasserted to initiate the internally self-timed program
cycle. The programming of the Sector Protection Register should take place in a maximum time of tP. During this time,
the RDY/BUSY bit in the Status Register will indicate that the device is busy. If the device is powered-down before the
completion of the erase cycle, then the contents of the Sector Protection Register cannot be guaranteed.
If the proper number of data bytes is not clocked in before the CS pin is deasserted, then the protection status of the
sectors corresponding to the bytes not clocked in cannot be guaranteed.
Example: If only the first two bytes are clocked in instead of the complete 16 bytes, then the protection status of the
last 14 sectors cannot be guaranteed. Furthermore, if more than 16 bytes of data is clocked into the device,
then the data will wrap back around to the beginning of the register. For instance, if 17 bytes of data are
clocked in, then the 17th byte will be stored at byte location 0 of the Sector Protection Register.
The data bytes clocked into the Sector Protection Register need to be valid values (0xh, 3xh, Cxh, and Fxh for Sector 0a
or Sector 0b, and 00h or FFh for other sectors) in order for the protection to function correctly. If a non-valid value is
clocked into a byte location of the Sector Protection Register, then the protection status of the sector corresponding to
that byte location cannot be guaranteed.
Example: If a value of 17h is clocked into byte location 2 of the Sector Protection Register, then the protection status
of Sector 2 cannot be guaranteed.
The Sector Protection Register can be reprogrammed while the sector protection is enabled or disabled. Being able to
reprogram the Sector Protection Register with the sector protection enabled allows the user to temporarily disable the
sector protection to an individual sector rather than disabling sector protection completely.
The Program Sector Protection Register command utilizes Buffer 1 for processing. Therefore, the contents of Buffer 1
will be altered from its previous state when this command is issued.
Table 7-7. Program Sector Protection Register Command
Command
Byte 1
Byte 2
Byte 3
Byte 4
Program Sector Protection Register
3Dh
2Ah
7Fh
FCh
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Figure 7-5. Program Sector Protection Register
CS
Data Byte
n
Data Byte
n + 1
Data Byte
n + 15
3Dh
2Ah
7Fh
FCh
SI
Each transition represents eight bits
7.3.3 Read Sector Protection Register
To read the Sector Protection Register, an opcode of 32h and three dummy bytes must be clocked into the device. After
the last bit of the opcode and dummy bytes have been clocked in, any additional clock pulses on the SCK pin will result
in the Sector Protection Register contents being output on the SO pin. The first byte (byte location 0) corresponds to
Sector 0 (0a and 0b), the second byte corresponds to Sector 1, and the last byte (byte location 15) corresponds to Sector
15. Once the last byte of the Sector Protection Register has been clocked out, any additional clock pulses will result in
undefined data being output on the SO pin. The CS pin must be deasserted to terminate the Read Sector Protection
Register operation and put the output into a high-impedance state.
Table 7-8. Read Sector Protection Register Command
Command
Byte 1
Byte 2
Byte 3
Byte 4
Read Sector Protection Register
32h
XXh
XXh
XXh
Note: 1. XX = Dummy byte
Figure 7-6. Read Sector Protection Register
CS
32h
XX
XX
XX
SI
Data
n
Data
n + 1
Data
n + 15
SO
Each transition represents eight bits
7.3.4 About the Sector Protection Register
The Sector Protection Register is subject to a limit of 10,000 erase/program cycles. Users are encouraged to carefully
evaluate the number of times the Sector Protection Register will be modified during the course of the application’s life
cycle. If the application requires that the Security Protection Register be modified more than the specified limit of 10,000
cycles because the application needs to temporarily unprotect individual sectors (sector protection remains enabled
while the Sector Protection Register is reprogrammed), then the application will need to limit this practice. Instead, a
combination of temporarily unprotecting individual sectors along with disabling sector protection completely will need to
be implemented by the application to ensure that the limit of 10,000 cycles is not exceeded
.
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8.
Security Features
8.1
Security Register
The device contains a specialized Security Register that can be used for purposes such as unique device serialization or
locked key storage. The register is comprised of a total of 128 bytes (byte locations 0 through 127). All 128 bytes of the
Security Register are factory programmed by Adesto and will contain a unique value for each device. The factory
programmed data is fixed and cannot be changed.
Table 8-1. Security Register
Security Register Byte Number
0
1
· · ·
· · ·
· · ·
127
Data Type
Factory Programmed by Adesto
8.1.1 Reading the Security Register
To read the Security Register, an opcode of 77h and three dummy bytes must be clocked into the device. After the last
dummy bit has been clocked in, the contents of the Security Register can be clocked out on the SO pin. After the last
byte of the Security Register has been read, additional pulses on the SCK pin will result in undefined data being output
on the SO pin.
Deasserting the CS pin will terminate the Read Security Register operation and put the SO pin into a high-impedance
state.
Figure 8-1. Read Security Register
CS
SI
77h
XX
XX
XX
Data
n
Data
n + 1
Data
n + x
SO
Each transition represents eight bits
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9.
Additional Commands
9.1
Main Memory Page to Buffer Transfer
A page of data can be transferred from the main memory to either Buffer 1 or Buffer 2. To transfer a page of data using
the optional DataFlash-L page size (528 bytes), an opcode of 53h for Buffer 1 or 55h for Buffer 2 must be clocked into the
device followed by three address bytes comprised of two dummy bits, 12 page address bits (PA11 - PA0) which specify
the page in main memory to be transferred, and 10 dummy bits. To transfer a page of data using the default page size
(512 bytes), an opcode of 53h for Buffer 1 and 55h for Buffer 2 must be clocked into the device followed by three address
bytes comprised of three dummy bits, 12 page address bits (A20 - A9) which specify the page in the main memory to be
transferred, and nine dummy bits.
The CS pin must be low while toggling the SCK pin to load the opcode and the three address bytes from the input pin
(SI). The transfer of the page of data from the main memory to the buffer will begin when the CS pin transitions from a
low to a high state. During the page transfer time (tXFR), the RDY/BUSY bit in the Status Register can be read to
determine whether or not the transfer has been completed.
9.2
Main Memory Page to Buffer Compare
A page of data in main memory can be compared to the data in Buffer 1 or Buffer 2 as a method to ensure that data was
successfully programmed after a Buffer to Main Memory Page Program command. To compare a page of data with the
optional DataFlash-L page size (528 bytes), an opcode of 60h for Buffer 1 or 61h for Buffer 2 must be clocked into the
device followed by three address bytes comprised of two dummy bits, 12 page address bits (PA11 - PA0) which specify
the page in the main memory to be compared to the buffer, and 10 dummy bits. To compare a page of data with the
default page size (512 bytes), an opcode of 60h for Buffer 1 or 61h for Buffer 2 must be clocked into the device followed
by three address bytes comprised of three dummy bits, 12 page address bits (A20 - A9) which specify the page in the
main memory to be compared to the buffer, and nine dummy bits.
The CS pin must be low while toggling the SCK pin to load the opcode and the address bytes from the input pin (SI). On
the low-to-high transition of the CS pin, the data bytes in the selected Main Memory Page will be compared with the data
bytes in Buffer 1 or Buffer 2. During the compare time (tCOMP), the RDY/BUSY bit in the Status Register will indicate that
the part is busy. On completion of the compare operation, bit 6 of the Status Register will be updated with the result of the
compare.
9.3
Auto Page Rewrite
This command only needs to be used if the possibility exists that static (non-changing) data may be stored in a page or
pages of a sector and the other pages of the same sector are erased and programmed a large number of times.
Applications that modify data in a random fashion within a sector may fall into this category. To preserve data integrity of
a sector, each page within a sector must be updated/rewritten at least once within every 50,000 cumulative page
erase/program operations within that sector. The Auto Page Rewrite command provides a simple and efficient method to
“refresh” a page in the main memory array in a single operation.
The Auto Page Rewrite command is a combination of the Main Memory Page to Buffer Transfer and Buffer to Main
Memory Page Program with Built-In Erase commands. With the Auto Page Rewrite command, a page of data is first
transferred from the main memory to Buffer 1 or Buffer 2 and then the same data (from Buffer 1 or Buffer 2) is
programmed back into the same page of main memory, essentially “refreshing” the contents of that page. To start the
Auto Page Rewrite operation with the optional DataFlash-L page size (528 bytes), a 1-byte opcode, 58H for Buffer 1 or
59H for Buffer 2, must be clocked into the device followed by three address bytes comprised of two dummy bits, 12 page
address bits (PA11-PA0) that specify the page in main memory to be rewritten, and 10 dummy bits.
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To initiate an Auto Page Rewrite with the a default page size (512 bytes), the opcode 58H for Buffer 1 or 59H for Buffer 2,
must be clocked into the device followed by three address bytes consisting of three dummy bits, 12 page address bits
(A20 - A9) that specify the page in the main memory that is to be rewritten, and nine dummy bits. When a low-to-high
transition occurs on the CS pin, the part will first transfer data from the page in main memory to a buffer and then
program the data from the buffer back into same page of main memory. The operation is internally self-timed and should
take place in a maximum time of tEP. During this time, the RDY/BUSY Status Register will indicate that the part is busy.
If a sector is programmed or reprogrammed sequentially page by page and the possibility does not exist that there will be
a page or pages of static data, then the programming algorithm shown in Figure 26-1 on page 55 is recommended.
Otherwise, if there is a chance that there may be a page or pages of a sector that will contain static data, then the
programming algorithm shown in Figure 26-2 on page 56 is recommended.
The Auto Page Rewrite command uses the same opcodes as the Read-Modify-Write command. If data bytes are clocked
into the device, then the device will perform a Read-Modify-Write operation. See the Read-Modify-Write command
description on page 12 for more details.
9.4
Status Register Read
The 2-byte Status Register can be used to determine the device's ready/busy status, page size, a Main Memory Page to
Buffer Compare operation result, the sector protection status, erase/program error status, and the device density. The
Status Register can be read at any time, including during an internally self-timed program or erase operation.
To read the Status Register, the CS pin must first be asserted and then the opcode D7h must be clocked into the device.
After the opcode has been clocked in, the device will begin outputting Status Register data on the SO pin during every
subsequent clock cycle. After the second byte of the Status Register has been clocked out, the sequence will repeat
itself, starting again with the first byte of the Status Register, as long as the CS pin remains asserted and the clock pin is
being pulsed. The data in the Status Register is constantly being updated, so each repeating sequence may output new
data. The RDY/BUSY status is available for both bytes of the Status Register and is updated for each byte.
Deasserting the CS pin will terminate the Status Register Read operation and put the SO pin into a high-impedance
state. The CS pin can be deasserted at any time and does not require that a full byte of data be read.
Table 9-1. Status Register Format – Byte 1
Type(
1)
Bit
Name
Description
0
1
Device is busy with an internal operation.
7
RDY/BUSY
Ready/Busy Status
R
Device is ready.
0
Main memory page data matches buffer data.
Main memory page data does not match buffer data.
16-Mbit
6
5:2
1
COMP
Compare Result
R
R
R
1
DENSITY
PROTECT
Density Code
1011
0
Sector protection is disabled.
Sector protection is enabled.
Sector Protection Status
1
Device is configured for optional DataFlash-L page size (528
bytes).
0
1
0
PAGE SIZE
Page Size Configuration
R
Device is configured for default page size (512 Bytes).
Note: 1. R = Readable only
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Table 9-2. Status Register Format – Byte 2
Type(
1)
Bit
7
Name
Description
0
1
0
0
1
0
0
x
x
x
Device is busy with an internal operation.
RDY/BUSY
RES
Ready/Busy Status
Reserved for Future Use
Erase/Program Error
R
R
R
Device is ready.
6
Reserved for future use.
Erase or program operation was successful.
Erase or program error detected.
Reserved for future use.
Reserved for future use.
Reserved for future use.
Reserved for future use.
Reserved for future use.
5
EPE
4
3
2
1
0
RES
RES
RES
RES
RES
Reserved for Future Use
Reserved for Future Use
Reserved for Future Use
Reserved for Future Use
Reserved for Future Use
R
R
R
R
R
Note: 1. R = Readable only
2. x = ”Don’t care”. Can be “0” or “1”.
9.4.1 RDY/BUSY Bit
The RDY/BUSY bit is used to determine whether or not an internal operation, such as a program or erase, is in progress.
To poll the RDY/BUSY bit to detect the completion of an internally timed operation, new Status Register data must be
continually clocked out of the device until the state of the RDY/BUSY bit changes from a Logic 0 to a Logic 1.
9.4.2 COMP Bit
The result of the most recent Main Memory Page to Buffer Compare operation is indicated using the COMP bit. If the
COMP bit is a Logic 1, then at least one bit of the data in the Main Memory Page does not match the data in the buffer.
9.4.3 DENSITY Bits
The device density is indicated using the DENSITY bits. For the AT25PE16, the four bit binary value is 1011. The
decimal value of these four binary bits does not actually equate to the device density; the four bits represent a
combinational code relating to differing densities of DataFlash-L devices. The DENSITY bits are not the same as the
density code indicated in the JEDEC Device ID information. The DENSITY bits are provided only for backward
compatibility to older generation DataFlash-L devices.
9.4.4 PROTECT Bit
The PROTECT bit provides information to the user on whether or not the sector protection has been enabled or disabled,
either by the software-controlled method or the hardware-controlled method.
9.4.5 PAGE SIZE Bit
The PAGE SIZE bit indicates whether the buffer size and the page size of the main memory array is configured for the
default page size (512 Bytes) or the optional DataFlash-L page size (528 bytes).
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9.4.6 EPE Bit
The EPE bit indicates whether the last erase or program operation completed successfully or not. If at least one byte
during the erase or program operation did not erase or program properly, then the EPE bit will be set to the Logic 1 state.
The EPE bit will not be set if an erase or program operation aborts for any reason. The EPE bit is updated after every
erase and program operation.
10. Deep Power-Down
During normal operation, the device will be placed in the standby mode to consume less power as long as the CS pin
remains deasserted and no internal operation is in progress. The Deep Power-Down command offers the ability to place
the device into an even lower power consumption state called the Deep Power-Down mode.
When the device is in the Deep Power-Down mode, all commands including the Status Register Read command will be
ignored with the exception of the Resume from Deep Power-Down command. Since all commands will be ignored, the
mode can be used as an extra protection mechanism against program and erase operations.
Entering the Deep Power-Down mode is accomplished by simply asserting the CS pin, clocking in the opcode B9h, and
then deasserting the CS pin. Any additional data clocked into the device after the opcode will be ignored. When the CS
pin is deasserted, the device will enter the Deep Power-Down mode within the maximum time of tEDPD
.
The complete opcode must be clocked in before the CS pin is deasserted, and the CS pin must be deasserted on an
even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and return to the standby mode
once the CS pin is deasserted. In addition, the device will default to the standby mode after a power cycle.
The Deep Power-Down command will be ignored if an internally self-timed operation such as a program or erase cycle is
in progress. The Deep Power-Down command must be reissued after the internally self-timed operation has been
completed in order for the device to enter the Deep Power-Down mode.
Figure 10-1. Deep Power-Down
CS
tEDPD
0
1
2
3
4
5
6
7
SCK
SI
Opcode
1
0
1
1
1
0
0
1
MSB
High-impedance
Active Current
SO
I
CC
Standby Mode Current
Deep Power-Down Mode Current
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10.1 Resume from Deep Power-Down
In order to exit the Deep Power-Down mode and resume normal device operation, the Resume from Deep Power-Down
command must be issued. The Resume from Deep Power-Down command is the only command that the device will
recognize while in the Deep Power-Down mode.
To resume from the Deep Power-Down mode, the CS pin must first be asserted and then the opcode ABh must be
clocked into the device. Any additional data clocked into the device after the opcode will be ignored. When the CS pin is
deasserted, the device will exit the Deep Power-Down mode and return to the standby mode within the maximum time of
t
RDPD. After the device has returned to the standby mode, normal command operations such as Continuous Array Read
can be resumed.
If the complete opcode is not clocked in before the CS pin is deasserted, or if the CS pin is not deasserted on an even
byte boundary (multiples of eight bits), then the device will abort the operation and return to the Deep Power-Down
mode.
Figure 10-2. Resume from Deep Power-Down
CS
tRDPD
0
1
2
3
4
5
6
7
SCK
SI
Opcode
1
0
1
0
1
0
1
1
MSB
High-impedance
Active Current
SO
I
CC
Standby Mode Current
Deep Power-Down Mode Current
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10.2 Ultra-Deep Power-Down
The Ultra-Deep Power-Down mode allows the device to consume far less power compared to the standby and Deep
Power-Down modes by shutting down additional internal circuitry. Since almost all active circuitry is shutdown in this
mode to conserve power, the contents of the SRAM buffers cannot be maintained. Therefore, any data stored in the
SRAM buffers will be lost once the device enters the Ultra-Deep Power-Down mode.
When the device is in the Ultra-Deep Power-Down mode, all commands including the Status Register Read and Resume
from Deep Power-Down commands will be ignored. Since all commands will be ignored, the mode can be used as an
extra protection mechanism against program and erase operations.
Entering the Ultra-Deep Power-Down mode is accomplished by simply asserting the CS pin, clocking in the opcode 79h,
and then deasserting the CS pin. Any additional data clocked into the device after the opcode will be ignored. When the
CS pin is deasserted, the device will enter the Ultra-Deep Power-Down mode within the maximum time of tEUDPD
.
The complete opcode must be clocked in before the CS pin is deasserted, and the CS pin must be deasserted on an
even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and return to the standby mode
once the CS pin is deasserted. In addition, the device will default to the standby mode after a power cycle.
The Ultra-Deep Power-Down command will be ignored if an internally self-timed operation such as a program or erase
cycle is in progress. The Ultra-Deep Power-Down command must be reissued after the internally self-timed operation
has been completed in order for the device to enter the Ultra-Deep Power-Down mode.
Figure 10-3. Ultra-Deep Power-Down
CS
tEUDPD
0
1
2
3
4
5
6
7
SCK
SI
Opcode
0
1
1
1
1
0
0
1
MSB
High-impedance
Active Current
SO
ICC
Standby Mode Current
Ultra-Deep Power-Down Mode Current
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10.2.1 Exit Ultra-Deep Power-Down
To exit from the Ultra-Deep Power-Down mode, the CS pin must simply be pulsed by asserting the CS pin, waiting the
minimum necessary tCSLU time, and then deasserting the CS pin again. To facilitate simple software development, a
dummy byte opcode can also be entered while the CS pin is being pulsed just as in a normal operation. After the CS pin
has been deasserted, the device will exit from the Ultra-Deep Power-Down mode and return to the standby mode within
a maximum time of tXUDPD. If the CS pin is reasserted before the tXUDPD time has elapsed in an attempt to start a new
operation, then that operation will be ignored and nothing will be performed. The system must wait for the device to return
to the standby mode before normal command operations such as Continuous Array Read can be resumed.
Since the contents of the SRAM buffers cannot be maintained while in the Ultra-Deep Power-Down mode, the SRAM
buffers will contain undefined data when the device returns to the standby mode.
Figure 10-4. Exit Ultra-Deep Power-Down
CS
tCSLU
tXUDPD
High-impedance
SO
Active Current
ICC
Standby Mode Current
Ultra-Deep Power-Down Mode Current
Chip Select Low
By asserting the CS pin, waiting the minimum necessary tXUDPD time, and then clocking in the first bit of the next Opcode
command cycle. If the first bit of the next command is clocked in before the tXUDPD time has elapsed, the device will exit
Ultra Deep Power Down, however the intended operation will be ignored.
Figure 10-5. Exit Ultra-Deep Power-Down (Chip Select Low)
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11. Buffer and Page Size Configuration
The memory array of DataFlash-L devices is actually larger than other Serial Flash devices in that extra user-accessible
bytes are provided in each page of the memory array. For the AT25PE16, there are an extra 16 bytes of memory in each
page for a total of an extra 64KB (512-Kbits) of user-accessible memory.
Some applications, however, may not want to take advantage of this extra memory and instead architect their software to
operate on a binary, logical addressing scheme. To allow this, the DataFlash-L can be configured so that the buffer and
page sizes are 512 bytes instead of the optional 528 bytes. In addition, the configuration of the buffer and page sizes is
reversible and can be changed from 528 bytes to 512 bytes or from 512 bytes to 528 bytes. The configured setting is
stored in an internal nonvolatile register so that the buffer and page size configuration is not affected by power cycles.
The nonvolatile register has a limit of 10,000 erase/program cycles; therefore, care should be taken to not switch
between the size options more than 10,000 times.
Devices are initially shipped from Adesto with the buffer and page sizes set to 512 bytes. To configure the device for
default page size (512 Bytes), a 4-byte opcode sequence of 3Dh, 2Ah, 80h, and A6h must be clocked into the device.
After the last bit of the opcode sequence has been clocked in, the CS pin must be deasserted to initiate the internally self-
timed configuration process and nonvolatile register program cycle. The programming of the nonvolatile register should
take place in a time of tEP, during which time the RDY/BUSY bit in the Status Register will indicate that the device is busy.
The device does not need to be power cycled after the completion of the configuration process and register program
cycle in order for the buffer and page size to be configured to 512 bytes.
To configure the device for optional DataFlash-L page size (528 bytes), a 4-byte opcode sequence of 3Dh, 2Ah, 80h, and
A7h must be clocked into the device. After the last bit of the opcode sequence has been clocked in, the CS pin must be
deasserted to initial the internally self-timed configuration process and nonvolatile register program cycle. The
programming of the nonvolatile register should take place in a time of tEP, during which time the RDY/BUSY bit in the
Status Register will indicate that the device is busy. The device does not need to be power cycled after the completion of
the configuration process and register program cycle in order for the buffer and page size to be configured to 528 bytes.
Table 11-1. Buffer and Page Size Configuration Commands
Command
Byte 1
3Dh
Byte 2
2Ah
Byte 3
80h
Byte 4
A6h
Default DataFlash-L page size (512 Bytes)
Optional DataFlash-L page size (528 bytes)
3Dh
2Ah
80h
A7h
Figure 11-1. Buffer and Page Size Configuration
CS
Opcode
Byte 4
3Dh
2Ah
80h
SI
Each transition represents eight bits
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12. Manufacturer and Device ID Read
Identification information can be read from the device to enable systems to electronically query and identify the device
while it is in the system. The identification method and the command opcode comply with the JEDEC Standard for
“Manufacturer and Device ID Read Methodology for SPI Compatible Serial Interface Memory Devices”. The type of
information that can be read from the device includes the JEDEC-defined Manufacturer ID, the vendor-specific
Device ID, and the vendor-specific Extended Device Information.
The Read Manufacturer and Device ID command is limited to a maximum clock frequency of fCLK. Since not all Flash
devices are capable of operating at very high clock frequencies, applications should be designed to read the
identification information from the devices at a reasonably low clock frequency to ensure that all devices to be used in the
application can be identified properly. Once the identification process is complete, the application can then increase the
clock frequency to accommodate specific Flash devices that are capable of operating at the higher clock frequencies.
To read the identification information, the CS pin must first be asserted and then the opcode 9Fh must be clocked into
the device. After the opcode has been clocked in, the device will begin outputting the identification data on the SO pin
during the subsequent clock cycles. The first byte to be output will be the Manufacturer ID, followed by two bytes of the
Device ID information. The fourth byte output will be the Extended Device Information (EDI) String Length, which will be
01h indicating that one byte of EDI data follows. After the one byte of EDI data is output, the SO pin will go into a
high-impedance state; therefore, additional clock cycles will have no affect on the SO pin and no data will be output. As
indicated in the JEDEC Standard, reading the EDI String Length and any subsequent data is optional.
Deasserting the CS pin will terminate the Manufacturer and Device ID Read operation and put the SO pin into a
high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read.
Table 12-1. Manufacturer and Device ID Information
Byte No.
Data Type
Value
1Fh
26h
1
2
3
4
5
Manufacturer ID
Device ID (Byte 1)
Device ID (Byte 2)
00h
Extended Device Information (EDI) String Length
[Optional to Read] Extended Device Information Byte 1
01h
00h
Table 12-2. Manufacturer and Device ID Details
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
Hex
Value
Data Type
Details
JEDEC Assigned Code
Manufacturer ID
1Fh
26h
00h
JEDEC code: 0001 1111 (1Fh for Adesto)
0
0
0
0
0
1
0
1
0
0
1
0
1
1
1
0
0
Family Code
Density Code
1
Device ID (Byte
1)
Family code: 001 (AT45Dxxx Family)
Density code: 00110 (16-Mbit)
0
Sub Code
0
1
Product Variant
Device ID (Byte
2)
Sub code:
000 (Standard Series)
Product variant:00000
0
0
0
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Table 12-3. EDI Data
Bit
Hex
Valu
e
Bit
6
Bit
5
Bit
3
Bit
2
Bit
1
Bit
0
Byte Number
7
Bit 4
Details
RFU
0
Device Revision
RFU:
Reserved for Future Use
1
00h
Device revision:00000 (Initial Version)
0
0
0
0
0
0
0
Figure 12-1. Read Manufacturer and Device ID
CS
0
6
7
8
14 15 16
22 23 24
30 31 32
38 39 40
46
SCK
SI
Opcode
9Fh
High-impedance
1Fh
26h
00h
01h
EDI
00h
EDI
SO
Manufacturer ID
Device ID
Byte 1
Device ID
Byte 2
String Length
Data Byte 1
Note: Each transition
shown for SI and SO represents one byte (8 bits)
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13. Software Reset
In some applications, it may be necessary to prematurely terminate a program or erase cycle early rather than wait the
hundreds of microseconds or milliseconds necessary for the program or erase operation to complete normally. The
Software Reset command allows a program or erase operation in progress to be ended abruptly and returns the device
to an idle state.
To perform a Software Reset, the CS pin must be asserted and a 4-byte command sequence of F0h, 00h, 00h, and 00h
must be clocked into the device. Any additional data clocked into the device after the last byte will be ignored. When the
CS pin is deasserted, the program or erase operation currently in progress will be terminated within a time tSWRST. Since
the program or erase operation may not complete before the device is reset, the contents of the page being programmed
or erased cannot be guaranteed to be valid.
The Software Reset command has no effect on the states of the Sector Protection Register or the buffer and page size
configuration.
The complete 4-byte opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be
deasserted on a byte boundary (multiples of eight bits); otherwise, no reset operation will be performed.
Table 13-1. Software Reset
Command
Byte 1
Byte 2
Byte 3
Byte 4
Software Reset
F0h
00h
00h
00h
Figure 13-1. Software Reset
CS
F0h
00h
00h
00h
SI
Each transition represents eight bits
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14. Operation Mode Summary
The commands described previously can be grouped into four different categories to better describe which commands
can be executed at what times.
Group A commands consist of:
1. Main Memory Page Read
2. Continuous Array Read (SPI)
3. Read Sector Protection Register
4. Read Security Register
5. Buffer 1 (or 2) Read
Group B commands consist of:
1. Page Erase
2. Block Erase
3. Sector Erase
4. Chip Erase
5. Main Memory Page to Buffer 1 (or 2) Transfer
6. Main Memory Page to Buffer 1 (or 2) Compare
7. Buffer 1 (or 2) to Main Memory Page Program with Built-In Erase
8. Buffer 1 (or 2) to Main Memory Page Program without Built-In Erase
9. Main Memory Page Program through Buffer 1 (or 2) with Built-In Erase
10. Main Memory Byte/Page Program through Buffer 1 without Built-In Erase
11. Auto Page Rewrite
Group C commands consist of:
1. Buffer 1 (or 2) Write
2. Status Register Read
3. Manufacturer and Device ID Read
Group D commands consist of:
1. Erase Sector Protection Register
2. Program Sector Protection Register
3. Buffer and Page Size Configuration
If a Group A command is in progress (not fully completed), then another command in Group A, B, C, or D should not be
started. However, during the internally self-timed portion of Group B commands, any command in Group C can be
executed. The Group B commands using Buffer 1 should use Group C commands using Buffer 2 and vice versa. Finally,
during the internally self-timed portion of a Group D command, only the Status Register Read command should be
executed.
AT25PE16
DS-25PE16-143C–8/2018
33
15. Command Tables
Table 15-1. Read Commands
Command
Opcode
D2h
01h
Main Memory Page Read
Continuous Array Read (Low Power Mode)
Continuous Array Read (Low Frequency)
Continuous Array Read (High Frequency)
Continuous Array Read (High Frequency)
Continuous Array Read (Legacy Command – Not Recommended for New Designs)
Buffer 1 Read (Low Frequency)
03h
0Bh
1Bh
E8h
D1h
D3h
D4h
D6h
Buffer 2 Read (Low Frequency)
Buffer 1 Read (High Frequency)
Buffer 2 Read (High Frequency)
Table 15-2. Program and Erase Commands
Command
Opcode
Buffer 1 Write
84h
Buffer 2 Write
87h
Buffer 1 to Main Memory Page Program with Built-In Erase
Buffer 2 to Main Memory Page Program with Built-In Erase
Buffer 1 to Main Memory Page Program without Built-In Erase
Buffer 2 to Main Memory Page Program without Built-In Erase
Main Memory Page Program through Buffer 1 with Built-In Erase
Main Memory Page Program through Buffer 2 with Built-In Erase
Main Memory Byte/Page Program through Buffer 1 without Built-In Erase
Page Erase
83h
86h
88h
89h
82h
85h
02h
81h
Block Erase
50h
Sector Erase
7Ch
Chip Erase
C7h + 94h + 80h + 9Ah
Read-Modify-Write through Buffer 1
Read-Modify-Write through Buffer 2
58h
59h
AT25PE16
DS-25PE16-143C–8/2018
34
Table 15-3. Protection and Security Commands
Command
Opcode
3Dh + 2Ah + 7Fh + A9h
3Dh + 2Ah + 7Fh + 9Ah
3Dh + 2Ah + 7Fh + CFh
3Dh + 2Ah + 7Fh + FCh
32h
Enable Sector Protection
Disable Sector Protection
Erase Sector Protection Register
Program Sector Protection Register
Read Sector Protection Register
Read Security Register
77h
Table 15-4. Additional Commands
Command
Opcode
Main Memory Page to Buffer 1 Transfer
Main Memory Page to Buffer 2 Transfer
Main Memory Page to Buffer 1 Compare
Main Memory Page to Buffer 2 Compare
Auto Page Rewrite through Buffer 1
Auto Page Rewrite through Buffer 2
Deep Power-Down
53h
55h
60h
61h
58h
59h
B9h
Resume from Deep Power-Down
Ultra-Deep Power-Down
ABh
79h
Status Register Read
D7h
Manufacturer and Device ID Read
Configure Default (512 Byte) Page Size
Configure Optional (528 Byte) Page Size
Software Reset
9Fh
3Dh + 2Ah + 80h + A6h
3Dh + 2Ah + 80h + A7h
F0h + 00h + 00h + 00h
Table 15-5. Legacy Commands(1)
Command
Opcode
54H
Buffer 1 Read
Buffer 2 Read
56H
Main Memory Page Read
Continuous Array Read
Status Register Read
52H
68H
57H
Note: 1. Legacy commands are not recommended for new designs.
AT25PE16
DS-25PE16-143C–8/2018
35
Table 15-6. Detailed Bit-level Addressing Sequence for Default Page Size (512 bytes)
Page Size = 512 bytes Address Byte Address Byte
Address Byte
Additional
Dummy
Bytes
Opcode
Opcode
N/A
N/A
N/A
1
01h
02h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
0
1
1
1
1
1
1
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
1
0
0
0
1
1
1
1
0
0
1
0
0
0
0
0
1
1
1
0
1
1
1
1
1
0
1
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
1
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
1
0
1
1
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
0
1
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A
A
A
A
A
X
A
A
A
A
A
A
A
A
A
X
A
A
A
A
A
X
A
A
A
A
A
A
A
A
A
X
A
A
A
A
A
X
A
A
A
A
A
A
A
A
A
X
A
A
A
A
A
X
A
A
A
A
A
A
A
A
A
X
A
A
A
A
A
X
A
A
A
A
A
A
A
A
A
X
A
A
A
A
A
X
A
A
A
A
A
A
A
A
A
X
A
A
A
A
A
X
A
A
A
A
A
A
A
A
A
X
A
A
A
A
A
X
A
A
A
A
A
A
A
A
A
X
A
A
A
A
A
X
A
A
A
A
A
A
A
A
A
X
A
A
A
A
A
X
X
A
A
A
A
A
A
A
A
X
A
A
A
A
A
X
X
A
A
A
A
A
A
A
A
X
A
A
A
A
A
X
X
A
A
A
A
A
A
A
A
X
A
A
A
A
A
X
X
X
X
X
A
X
A
X
X
X
A
A
A
A
A
X
X
X
X
X
A
X
A
X
X
X
A
A
A
A
A
X
X
X
X
X
A
X
A
X
X
X
A
A
A
A
A
X
X
X
X
X
A
X
A
X
X
X
A
A
A
A
A
X
X
X
X
X
A
X
A
X
X
X
A
A
A
A
A
X
X
X
X
X
A
X
A
X
X
X
A
A
A
A
A
X
X
X
X
X
A
X
A
X
X
X
A
A
A
A
A
X
X
X
X
X
A
X
A
X
X
X
A
A
A
A
A
X
X
X
X
X
A
X
A
X
X
X
03h
0Bh
1Bh
32h
2
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
4
50h
53h
55h
58h (1)
58h (2)
59h (1)
59h (2)
60h
61h
77h
79h
N/A
N/A
N/A
7Ch
81h
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A
A
A
A
X
A
A
X
A
A
A
A
A
A
X
A
A
X
A
A
A
A
A
A
X
A
A
X
A
A
A
A
A
A
X
A
A
X
A
A
X
A
A
A
X
A
A
X
A
A
X
A
A
A
X
A
A
X
A
A
X
A
A
A
X
A
A
X
A
A
X
A
A
A
X
A
A
X
A
A
X
A
A
A
X
A
A
X
A
A
X
A
A
A
X
A
A
X
A
A
X
A
A
A
X
A
A
X
A
A
X
A
A
A
X
A
A
X
A
A
X
X
A
X
A
A
X
A
X
X
X
X
A
X
A
A
X
A
X
X
X
X
A
X
A
A
X
A
X
X
X
X
A
X
A
A
X
A
X
X
X
X
A
X
A
A
X
A
X
X
X
X
A
X
A
A
X
A
X
X
X
X
A
X
A
A
X
A
X
X
X
X
A
X
A
A
X
A
X
X
X
X
A
X
A
A
X
A
X
X
82h
83h
84h
85h
86h
87h
88h
89h
9Fh
B9h
ABh
D1h
D2h
D3h
D4h
D6h
D7h
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A
X
X
X
X
A
X
X
X
X
A
X
X
X
X
A
X
X
X
X
A
X
X
X
X
A
X
X
X
X
A
X
X
X
X
X
A
X
X
X
X
A
X
X
X
X
A
X
X
X
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
X
X
X
A
X
X
X
A
A
A
A
N/A
1
1
N/A
N/A
N/A
N/A
1. Shown to indicate when Auto Page Rewrite Operation is executed.
2. Shown to indicate when Read Modify Write Operation is executed.
Note: X = Dummy Bit
AT25PE16
DS-25PE16-143C–8/2018
36
Table 15-7. Detailed Bit-level Addressing Sequence for Optional Page Size (528 bytes)
Page Size = 528-bytes Address Byte Address Byte
Address Byte
Additional
Dummy
Bytes
Opcode
Opcode
01h
02h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
0
1
1
1
1
1
1
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
1
0
0
0
1
1
1
1
0
0
1
0
0
0
0
0
1
1
1
0
1
1
1
1
1
0
1
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
0
1
1
1
0
1
1
1
0
0
1
1
0
0
1
1
0
1
1
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
0
1
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
P
P
P
P
P
X
P
P
P
P
P
P
P
P
P
X
P
P
P
P
P
X
P
P
P
P
P
P
P
P
P
X
P
P
P
P
P
X
P
P
P
P
P
P
P
P
P
X
P
P
P
P
P
X
P
P
P
P
P
P
P
P
P
X
P
P
P
P
P
X
P
P
P
P
P
P
P
P
P
X
P
P
P
P
P
X
P
P
P
P
P
P
P
P
P
X
P
P
P
P
P
X
P
P
P
P
P
P
P
P
P
X
P
P
P
P
P
X
P
P
P
P
P
P
P
P
P
X
P
P
P
P
P
X
P
P
P
P
P
P
P
P
P
X
P
P
P
P
P
X
X
P
P
P
P
P
P
P
P
X
P
P
P
P
P
X
X
P
P
P
P
P
P
P
P
X
P
P
P
P
P
X
X
P
P
P
P
P
P
P
P
X
B
B
B
B
B
X
X
X
X
X
B
X
B
X
X
X
B
B
B
B
B
X
X
X
X
X
B
X
B
X
X
X
B
B
B
B
B
X
X
X
X
X
B
X
B
X
X
X
B
B
B
B
B
X
X
X
X
X
B
X
B
X
X
X
B
B
B
B
B
X
X
X
X
X
B
X
B
X
X
X
B
B
B
B
B
X
X
X
X
X
B
X
B
X
X
X
B
B
B
B
B
X
X
X
X
X
B
X
B
X
X
X
B
B
B
B
B
X
X
X
X
X
B
X
B
X
X
X
B
B
B
B
B
X
X
X
X
X
B
X
B
X
X
X
B
B
B
B
B
X
X
X
X
X
B
X
B
X
X
X
N/A
N/A
N/A
1
03h
0Bh
1Bh
32h
2
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
4
50h
53h
55h
58h (1)
58h (2)
59h(1)
59h(2)
60h
61h
77h
79h
N/A
N/A
N/A
7Ch
81h
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
P
P
P
P
X
P
P
X
P
P
P
P
P
P
X
P
P
X
P
P
P
P
P
P
X
P
P
X
P
P
P
P
P
P
X
P
P
X
P
P
X
P
P
P
X
P
P
X
P
P
X
P
P
P
X
P
P
X
P
P
X
P
P
P
X
P
P
X
P
P
X
P
P
P
X
P
P
X
P
P
X
P
P
P
X
P
P
X
P
P
X
P
P
P
X
P
P
X
P
P
X
P
P
P
X
P
P
X
P
P
X
P
P
P
X
P
P
X
P
P
X
X
B
X
B
B
X
B
X
X
X
X
B
X
B
B
X
B
X
X
X
X
B
X
B
B
X
B
X
X
X
X
B
X
B
B
X
B
X
X
X
X
B
X
B
B
X
B
X
X
X
X
B
X
B
B
X
B
X
X
X
X
B
X
B
B
X
B
X
X
X
X
B
X
B
B
X
B
X
X
X
X
B
X
B
B
X
B
X
X
X
X
B
X
B
B
X
B
X
X
82h
83h
84h
85h
86h
87h
88h
89h
9Fh
B9h
ABh
D1h
D2h
D3h
D4h
D6h
D7h
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
X
X
X
X
X
X
X
X
X
X
X
P
X
X
X
X
X
P
X
X
X
X
P
X
X
X
X
P
X
X
X
X
P
X
X
X
X
P
X
X
X
X
P
X
X
X
X
P
X
X
X
X
X
P
X
X
X
X
P
X
X
X
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
P
X
X
X
P
X
X
X
B
B
B
B
N/A
1
1
N/A
N/A
N/A
N/A
1. Shown to indicate when Auto Page Rewrite Operation is executed.
2. Shown to indicate when Read Modify Write Operation is executed.
Note: P = Page Address Bit B = Byte/Buffer Address Bit X = Dummy Bit
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16. Power-On/Reset State
When power is first applied to the device, or when recovering from a reset condition, the device will default to SPI
Mode 3. In addition, the output pin (SO) will be in a high impedance state, and a high-to-low transition on the CS pin will
be required to start a valid instruction. The SPI mode (Mode 3 or Mode 0) will be automatically selected on every falling
edge of CS by sampling the inactive clock state.
16.1 Initial Power-Up Timing Restrictions
As the device initializes, there will be a transient current demand. The system needs to be capable of providing this
current to ensure correct initialization. During power-up, the device must not be accessed for at least the minimum tVCSL
time after the supply voltage reaches the minimum VCC level. While the device is being powered-up, the internal Power-
On Reset (POR) circuitry keeps the device in a reset mode until the supply voltage rises above the maximum POR
threshold value (VPOR). During this time, all operations are disabled and the device will not respond to any commands.
After power-up, the device will be in the standby mode.
If the first operation to the device after power-up will be a program or erase operation, then the operation cannot be
started until the supply voltage reaches the minimum VCC level and an internal device delay has elapsed. This delay will
be a maximum time of tPUW
.
Table 16-1. Power-Up Timing
Symbol
tVCSL
Parameter
Min
Max
Units
µs
Minimum VCC to Chip Select Low Time
Power-Up Device Delay Before Program or Erase Allowed
Power-On Reset (POR) Voltage
70
tPUW
3
ms
V
VPOR
1.5
2.2
Figure 16-1. Power-Up Timing
V
CC
Read Operation Permitted
VCC (min)
POR (max)
tVCSL
tPUW
V
Do Not Attempt
Device Access
During this Time
Program/Erase Operations Permitted
VPOR (min)
Time
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17. System Considerations
The serial interface is controlled by the Serial Clock (SCK), Serial Input (SI), and Chip Select (CS) pins. These signals
must rise and fall monotonically and be free from noise. Excessive noise or ringing on these pins can be misinterpreted
as multiple edges and cause improper operation of the device. PCB traces must be kept to a minimum distance or
appropriately terminated to ensure proper operation. If necessary, decoupling capacitors can be added on these pins to
provide filtering against noise glitches.
As system complexity continues to increase, voltage regulation is becoming more important. A key element of any
voltage regulation scheme is its current sourcing capability. Like all Flash memories, the peak current for DataFlash-L
devices occurs during the programming and erasing operations. The supply voltage regulator needs to be able to supply
this peak current requirement. An under specified regulator can cause current starvation. Besides increasing system
noise, current starvation during programming or erasing can lead to improper operation and possible data corruption.
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18. Electrical Specifications
18.1 Absolute Maximum Ratings*
*Notice: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only
and functional operation of the device at these or
any other conditions beyond those indicated in
the operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.Voltage extremes referenced in the
“Absolute Maximum Ratings” are intended to
accommodate short duration
Temperature under Bias . . . . . . . -55°C to +125°C
Storage Temperature. . . . . . . . . . -65°C to +150°C
Absolute Maximum Vcc . . . . . . . . . . . . . . . . .3.96V
All Output Voltages with Respect to Ground
undershoot/overshoot conditions and does not
imply or guarantee functional device operation at
these levels for any extended period of time.
. . . . . . . . -0.6V to 4.2V (Max VCC of 3.6V + 0.6V)
All Input Voltages with Respect to Ground
(excluding VCC pin, including NC pins)
. . . . . . . . -0.6V to 4.2V (Max VCC of 3.6V + 0.6V)
18.2 DC and AC Operating Range
AT25PE16
2.3V
Operating Temperature (Case)
VCC Power Supply
Industrial
-40°C to 85°C
2.3V to 3.6V
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18.3 DC Characteristics
Symbol Parameter
Condition
Min
Typ
0.4
5
Max
1
Units
µA
IUDPD
IDPD
ISB
Ultra-Deep Power-Down Current CS= VCC. All other inputs at 0V or VCC
Deep Power-Down Current
Standby Current
CS= VCC. All other inputs at 0V or VCC
CS= VCC. All other inputs at 0V or VCC
f = 1MHz; IOUT = 0mA
12
50
9
µA
25
6
µA
mA
mA
mA
mA
Active Current, Low Power Read
(01h) Operation
ICC1
f = 15MHz; IOUT = 0mA
7
11
17
22
f = 50MHz; IOUT = 0mA
12
16
Active Current,
Read Operation
(1)
ICC2
f = 85MHz; IOUT = 0mA
Active Current,
Program Operation
ICC3
CS=VCC
CS=VCC
12
12
18
18
mA
mA
Active Current,
Erase Operation
ICC4
ILI
Input Load Current
All inputs at CMOS levels
All inputs at CMOS levels
1
1
µA
µA
ILO
Output Leakage Current
VCC
0.3
x
VIL
Input Low Voltage
V
VCC
0.7
x
VCC
0.6
+
VIH
Input High Voltage
Output Low Voltage
Output High Voltage
V
V
V
VOL
VOH
IOL = 100µA
IOH = -100µA
0.4
VCC
0.2V
-
Notes: 1. Typical values measured at 3.0V at 25°C.
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18.4 AC Characteristics
AT25PE16
2.3V
Symbol
fSCK
Parameter
Min
Max
Units
MHz
MHz
SCK Frequency
70
85
fCAR1
SCK Frequency for Continuous Read (0x0B)
SCK Frequency for Continuous Read (0x03)
(Low Frequency)
fCAR2
fCAR3
fCAR4
50
15
MHz
MHz
MHz
SCK Frequency for Continuous Read
(Low Power Mode – 01h Opcode)
SCK Frequency for Continuous Read
(0x1B)
104
tWH
tWL
SCK High Time
4
4
ns
ns
SCK Low Time
(1)
tSCKR
SCK Rise Time, Peak-to-peak
SCK Fall Time, Peak-to-peak
Minimum CS High Time
CS Setup Time
0.1
0.1
20
5
V/ns
V/ns
ns
(1)
tSCKF
tCS
tCSS
tCSH
tSU
tH
ns
CS Hold Time
5
ns
Data In Setup Time
2
ns
Data In Hold Time
1
ns
tHO
Output Hold Time
0
ns
(1)
tDIS
Output Disable Time
6
7
1
1
4
ns
tV
Output Valid
ns
tWPE
tWPD
WP Low to Protection Enabled
WP High to Protection Disabled
CS High to Ultra-Deep Power-Down
Minimum CS Low Time to Exit Ultra-Deep Power-Down
Exit Ultra-Deep Power-Down Time
CS High to Deep Power-Down
Resume from Deep Power-Down Time
Page to Buffer Transfer Time
Page to Buffer Compare Time
RESET Pulse Width
µs
µs
µs
ns
(1)
tEUDPD
tCSLU
20
tXUDPD
180
2
µs
µs
µs
µs
µs
µs
µs
µs
(1)
tEDPD
tRDPD
tXFR
tCOMP
tRST
35
200
200
10
tREC
RESET Recovery Time
Software Reset Time
1
tSWRST
35
Note: 1. Values are based on device characterization, not 100% tested in production.
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18.5 Program and Erase Characteristics
Symbol
tEP
Parameter
Min
Typ
17
3
Max
25*
4
Units
ms
ms
µs
Page Erase and Programming Time (512/528 bytes)
Page Programming Time
Byte Programming Time
Page Erase Time
tP
tBP
8
tPE
12
45
1.4
22
35
100
2*
ms
ms
s
tBE
Block Erase Time
tSE
Sector Erase Time
tCE
Chip Erase Time
40
s
Notes: 1. Specification waiver for legacy inventory may apply.
19. Input Test Waveforms and Measurement Levels
0.9VCC
AC
AC
Driving
Levels
VCC/2
Measurement
Level
0.1VCC
t , t < 2ns (10% to 90%)
R
F
20. Output Test Load
Device
Under
Test
30pF
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21. Utilizing the RapidS Function
To take advantage of the RapidS function's ability to operate at higher clock frequencies, a full clock cycle must be used
to transmit data back and forth across the serial bus. The DataFlash-L is designed to always clock its data out on the
falling edge of the SCK signal and clock data in on the rising edge of SCK.
For full clock cycle operation to be achieved, when the DataFlash-L is clocking data out on the falling edge of SCK, the
host controller should wait until the next falling edge of SCK to latch the data in. Similarly, the host controller should clock
its data out on the rising edge of SCK in order to give the DataFlash-L a full clock cycle to latch the incoming data in on
the next rising edge of SCK.
Figure 21-1. RapidS Mode
Slave CS
1
8
1
8
1
2
3
4
5
6
7
2
3
4
5
6
7
SCK
MOSI
MISO
B
E
A
C
D
MSB
LSB
BYTE-MOSI
H
G
I
F
MSB
LSB
BYTE-SO
MOSI = Master Out, Slave In
MISO = Master In, Slave Out
The Master is the host controller and the Slave is the DataFlash.
The Master always clocks data out on the rising edge of SCK and always clocks data in on the falling edge of SCK.
The Slave always clocks data out on the falling edge of SCK and always clocks data in on the rising edge of SCK.
A. Master clocks out first bit of BYTE-MOSI on the rising edge of SCK
B. Slave clocks in first bit of BYTE-MOSI on the next rising edge of SCK
C. Master clocks out second bit of BYTE-MOSI on the same rising edge of SCK
D. Last bit of BYTE-MOSI is clocked out from the Master
E. Last bit of BYTE-MOSI is clocked into the slave
F. Slave clocks out first bit of BYTE-SO
G. Master clocks in first bit of BYTE-SO
H. Slave clocks out second bit of BYTE-SO
I. Master clocks in last bit of BYTE-SO
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Figure 21-2. Command Sequence for Read/Write Operations for Page Size 512 bytes
(Except Status Register Read, Manufacturer and Device ID Read)
SI (INPUT)
MSB
CMD
8-bits
8-bits
8-bits
X X X X X X X X X X X X X X X X
X X X X X X X X
LSB
3 Dummy Bits
Page Address
(A20 - A9)
Byte/Buffer Address
(A8 - A0/BFA8 - BFA0)
Figure 21-3. Command Sequence for Read/Write Operations for Page Size 528 bytes
(Except Status Register Read, Manufacturer and Device ID Read)
SI (INPUT)
MSB
CMD
8-bits
8-bits
8-bits
X X X X X X X X X X X X X X X X
X X X X X X X X
LSB
2
Dummy Bits
Page Address
(PA11 - PA0)
Byte/Buffer Address
(BA9 - BA0/BFA9 - BFA0)
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22. AC Waveforms
Four different timing waveforms are shown in Figure 22-1 through Figure 22-4. Waveform 1 shows the SCK signal being
low when CS makes a high-to-low transition and Waveform 2 shows the SCK signal being high when CS makes a
high-to-low transition. In both cases, output SO becomes valid while the SCK signal is still low (SCK low time is specified
as tWL). Timing Waveforms 1 and 2 conform to RapidS serial interface but for frequencies up to 85MHz. Waveforms 1
and 2 are compatible with SPI Mode 0 and SPI Mode 3, respectively.
Waveform 3 and 4 illustrate general timing diagram for RapidS serial interface. These are similar to Waveform 1 and 2,
except that output SO is not restricted to become valid during the tWL period. These timing waveforms are valid over the
full frequency range (maximum frequency = 85MHz) of the RapidS serial case.
Figure 22-1. Waveform 1 = SPI Mode 0 Compatible
tCS
CS
tCSS
tWH
tWL
tCSH
SCK
SO
SI
tV
tHO
tDIS
High-impedance
tSU
High-impedance
Valid Out
tH
Valid In
Figure 22-2. Waveform 2 = SPI Mode 3 Compatible
tCS
CS
tCSS
tWL
tWH
tCSH
SCK
SO
tV
tHO
tDIS
High Z
High-impedance
Valid Out
tH
tSU
Valid In
SI
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Figure 22-3. Waveform 3 = RapidS Mode 0
tCS
CS
tCSS
tWH
tWL
tCSH
SCK
SO
SI
tV
tHO
tDIS
High-impedance
tSU
High-impedance
Valid Out
tH
Valid In
Figure 22-4. Waveform 4 = RapidS Mode 3
tCS
CS
tCSS
tWL
tWH
tCSH
SCK
SO
tV
tHO
tDIS
High Z
High-impedance
Valid Out
tH
tSU
Valid In
SI
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23. Write Operations
The following block diagram and waveforms illustrate the various write sequences available.
Figure 23-1. Block Diagram
Flash Memory Array
Page (512/528 bytes)
Buffer 1 To
Main Memory
Page Program
Buffer 2 To
Main Memory
Page Program
Buffer 1 (512/528 bytes)
Buffer 2 (512/528 bytes)
Buffer 1
Write
Buffer 2
Write
I/O Interface
SI
Figure 23-2. Buffer Write
Completes Writing into Selected Buffer
CS
Binary Page Size
15 Dummy Bits + BFA8-BFA0
CMD
X
X···X, BFA9-8
BFA7-0
n
n + 1
Last Byte
SI (Input)
Figure 23-3. Buffer to Main Memory Page Program
Starts Self-timed Erase/Program Operation
CS
Binary Page Size
A20-A9 + 9 Dummy Bits
CMD
PA11-6
PA5-0, XX
XXXX XX
SI (Input)
n
= 1st byte read
n+1 = 2nd byte read
Each transition represents eight bits
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24. Read Operations
The following block diagram and waveforms illustrate the various read sequences available.
Figure 24-1. Block Diagram
Flash Memory Array
Page (512/528 bytes)
Main Memory
Page To
Buffer 1
Main Memory
Page To
Buffer 2
Buffer 1 (512/528 bytes)
Buffer 2 (512/528 bytes)
Buffer 1
Read
Main Memory
Page Read
Buffer 2
Read
I/O Interface
SO
Figure 24-2. Main Memory Page Read
CS
Address for Binary Page Size
A20-A16
A15-A8
A7-A0
CMD
PA11-6
PA5-0, BA9-8
BA7-0
X
X
SI (Input)
4 Dummy Bytes
SO (Output)
n
n + 1
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Figure 24-3. Main Memory Page to Buffer Transfer
Data From the selected Flash Page is read into either SRAM Buffer
Starts Reading Page Data into Buffer
CS
Binary Page Size
A20-A9 + 9 Dummy Bits
CMD
PA11-6
PA5-0, XX
XXXX XX
SI (Input)
SO (Output)
Figure 24-4. Buffer Read
CS
Address for Binary Page Size
A20-A16
A15-A8
A7-A0
CMD
X
X... X, BFA9-8
BFA7-0
X
SI (Input)
No Dummy Byte (opcodes D1H and D3H)
1 Dummy Byte (opcodes D4H and D6H)
SO (Output)
n
n + 1
Each transition represents eight bits
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25. Detailed Bit-level Read Waveforms: RapidS Mode 0/Mode 3
Figure 25-1. Continuous Array Read (Legacy Opcode E8h)
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34
62 63 64 65 66 67 68 69 70 71 72
SCK
SI
Opcode
Address Bits
32 Dummy Bits
1
1
1
0
1
0
0
0
A
A
A
A
A
A
A
A
A
X
X
X
X
X
X
MSB
MSB
MSB
Data Byte 1
High-impedance
D
D
D
D
D
D
D
D
D
D
SO
MSB
MSB
Bit 0 of
Page n+1
Bit 4095/4223
of Page n
Figure 25-2. Continuous Array Read (Opcode 0Bh)
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
SCK
SI
Opcode
Address Bits A20 - A0
Dummy Bits
X
0
0
0
0
1
0
1
1
A
A
A
A
A
A
A
A
A
X
X
X
X
X
X
X
MSB
MSB
MSB
Data Byte 1
High-impedance
D
D
D
D
D
D
D
D
D
D
SO
MSB
MSB
Figure 25-3. Continuous Array Read (Opcode 01h or 03h)
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35 36 37 38 39 40
SCK
SI
Opcode
Address Bits A20-A0
0
0
0
0
0
0
1
1
A
A
A
A
A
A
A
A
A
MSB
MSB
Data Byte 1
High-impedance
D
D
D
D
D
D
D
D
D
D
SO
MSB
MSB
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Figure 25-4. Main Memory Page Read (Opcode D2h)
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34
62 63 64 65 66 67 68 69 70 71 72
SCK
SI
Opcode
Address Bits
32 Dummy Bits
1
1
0
1
0
0
1
0
A
A
A
A
A
A
A
A
A
X
X
X
X
X
X
MSB
MSB
MSB
Data Byte 1
High-impedance
D
D
D
D
D
D
D
D
D
D
SO
MSB
MSB
Figure 25-5. Buffer Read (Opcode D4h or D6h)
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
SCK
Address Bits
Binary Page Size = 15 Dummy Bits + BFA8-BFA0
Standard DataFlash Page Size =
14 Dummy Bits + BFA9-BFA0
Dummy Bits
Opcode
1
1
0
1
0
1
0
0
X
X
X
X
X
X
A
A
A
X
X
X
X
X
X
X
X
SI
MSB
MSB
MSB
Data Byte 1
High-impedance
D
D
D
D
D
D
D
D
D
D
SO
MSB
MSB
Figure 25-6. Buffer Read – Low Frequency (Opcode D1h or D3h)
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35 36 37 38 39 40
SCK
Address Bits
Binary Page Size = 15 Dummy Bits + BFA8-BFA0
Standard DataFlash Page Size =
14 Dummy Bits + BA9-BFA0
Opcode
1
1
0
1
0
0
0
1
X
X
X
X
X
X
A
A
A
SI
MSB
MSB
Data Byte 1
High-impedance
D
D
D
D
D
D
D
D
D
D
SO
MSB
MSB
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Figure 25-7. Read Sector Protection Register (Opcode 32h)
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35 36 37 38 39 40
SCK
SI
Opcode
Dummy Bits
0
0
1
1
0
0
1
0
X
X
X
X
X
X
X
X
X
MSB
MSB
Data Byte 1
High-impedance
D
D
D
D
D
D
D
D
D
SO
MSB
MSB
Figure 25-8. Read Security Register (Opcode 77h)
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35 36 37 38 39 40
SCK
SI
Opcode
Dummy Bits
0
1
1
1
0
1
1
1
X
X
X
X
X
X
X
X
X
MSB
MSB
Data Byte 1
High-impedance
D
D
D
D
D
D
D
D
D
SO
MSB
MSB
Figure 25-9. Status Register Read (Opcode D7h)
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCK
SI
Opcode
1
1
0
1
0
1
1
1
MSB
Status Register Data
Status Register Data
High-impedance
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
SO
MSB
MSB
MSB
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Figure 25-10. Manufacturer and Device Read (Opcode 9Fh)
CS
0
6
7
8
14 15 16
22 23 24
30 31 32
38 39 40
46
SCK
SI
Opcode
9Fh
High-impedance
1Fh
26h
00h
01h
EDI
00h
EDI
SO
Manufacturer ID
Device ID
Byte 1
Device ID
Byte 2
String Length
Data Byte 1
Note: Each transition
shown for SI and SO represents one byte (8 bits)
Figure 25-11.Reset Timing
CS
t
REC
t
CSS
SCK
RESET
t
RST
High Impedance
High Impedance
SO (Output)
SI (Input)
Note: 1. The CS signal should be in the high state before the RESET signal is deasserted.
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26. Auto Page Rewrite Flowchart
Figure 26-1. Algorithm for Programming or Re-programming of the Entire Array Sequentially
Notes: 1. This type of algorithm is used for applications in which the entire array is programmed sequentially, filling the
array page-by-page
2. A page can be written using either a Main Memory Page Program operation or a buffer write operation
followed by a buffer to Main Memory Page Program operation
3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially
for each page within the entire array
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Figure 26-2. Algorithm for Programming or Re-programming of the Entire Array Randomly
Notes: 1. To preserve data integrity, each page of an DataFlash-L sector must be updated/rewritten at least once
within every 50,000 cumulative page erase and program operations
2. A page address pointer must be maintained to indicate which page is to be rewritten. The auto page rewrite
command must use the address specified by the page address pointer
3. Other algorithms can be used to rewrite portions of the Flash array. Low-power applications may choose to
wait until 50,000 cumulative page erase and program operations have accumulated before rewriting all
pages of the sector.
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27. Ordering Information
27.1 Ordering Detail
A T 2 5 P E 1 6 - S S H F - B
Designator
Shipping Carrier Option
B = Bulk (tubes)
T = Tape and reel
Y = Trays
Product Family
25PE = DataFlash-L
Operating Voltage
F = 2.3V minimum (2.3V to 3.6V)
Device Density
16 = 16-Mbit
Device Grade
H = Green, NiPdAu lead finish,
Industrial temperature range
(–40°C to +85°C)
Package Option
SS = 8-lead,0.150” wide SOIC
S
= 8-lead,0.208” wide SOIC
= 8-pad, 5 x 6 x 0.6mm UDFN
M
27.2 Ordering Codes (Default 512 Byte Page Size)
Ordering Code(1)
AT25PE16-SSHF-B
AT25PE16-SSHF-T
AT25PE16-SHF-B
AT25PE16-SHF-T
AT25PE16-MHF-Y
AT25PE16-MHF-T
Package
Lead Finish
Operating Voltage
fSCK
Device Grade
8S1
Industrial
8S2
NiPdAu
2.3V to 3.6V
85MHz
(-40°C to 85°C)
8MA1
Notes: 1. The shipping carrier suffix is not marked on the device.
Package Type
8S1
8-lead 0.150" wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8-lead 0.208" wide, Plastic Gull Wing Small Outline (EIAJ SOIC)
8S2
8MA1
8-pad (5 x 6 x 0.6mm body), Thermally Enhanced Plastic Ultra Thin Dual Flat No-lead (UDFN)
AT25PE16
DS-25PE16-143C–8/2018
57
28. Packaging Information
28.1 8S1 – 8-lead JEDEC SOIC
C
1
E
E1
L
N
Ø
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.35
0.10
MAX
1.75
0.25
NOM
NOTE
SYMBOL
A1
A
–
–
A1
b
0.31
0.17
4.80
3.81
5.79
–
0.51
0.25
5.05
3.99
6.20
C
D
E1
E
e
–
–
D
–
–
SIDE VIEW
1.27 BSC
L
0.40
0°
–
–
1.27
8°
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
Ø
6/22/11
DRAWING NO. REV.
TITLE
GPC
8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
SWB
8S1
G
Package Drawing Contact:
contact@adestotech.com
AT25PE16
DS-25PE16-143C–8/2018
58
28.2 8S2 – 8-lead EIAJ SOIC
C
1
E
E1
L
N
q
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.70
0.05
0.35
0.15
5.13
5.18
7.70
0.51
0°
MAX
2.16
0.25
0.48
0.35
5.35
5.40
NOM
NOTE
SYMBOL
A1
A
A1
b
4
4
C
D
E1
E
D
2
8.10
L
0.85
8°
SIDE VIEW
q
e
1.27 BSC
3
Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
2. Mismatch of the upper and lower dies and resin burrs aren't included.
3. Determines the true geometric position.
4. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm.
4/15/08
REV.
GPC
DRAWING NO.
TITLE
8S2, 8-lead, 0.208” Body, Plastic Small
Outline Package (EIAJ)
Package Drawing Contact:
contact@adestotech.com
STN
8S2
F
AT25PE16
DS-25PE16-143C–8/2018
59
28.3 8MA1 – 8-pad UDFN
E
C
Pin 1 ID
SIDE VIEW
D
y
TOP VIEW
A1
A
K
E2
Option A
0.45
Pin #1
Chamfer
(C 0.35)
8
1
2
3
Pin #1 Notch
(0.20 R)
COMMON DIMENSIONS
(Unit of Measure = mm)
(Option B)
MIN
MAX
NOM
NOTE
SYMBOL
7
A
0.45
0.55
0.60
e
D2
A1
b
0.00
0.35
0.02
0.40
0.152 REF
5.00
4.00
6.00
3.40
1.27
0.60
–
0.05
0.48
6
C
D
D2
E
4.90
3.80
5.90
3.20
5.10
4.20
6.10
3.60
5
4
b
BOTTOM VIEW
L
E2
e
L
0.50
0.00
0.20
0.75
0.08
–
y
K
–
4/15/08
GPC
YFG
DRAWING NO.
TITLE
REV.
Package Drawing Contact: 8MA1, 8-pad (5 x 6 x 0.6 mm Body), Thermally
Enhanced Plastic Ultra Thin Dual Flat No Lead
Package (UDFN)
8MA1
D
contact@adestotech.com
AT25PE16
DS-25PE16-143C–8/2018
60
29. Revision History
Doc. Rev.
Date
Comments
DS-25PE16-143A
DS-25PE16-143B
07/2017
03/2018
Initial document release.
Change document status from ADVANCED to PRELIMINARY.
Change document status from PRELIMINARY to production.
Updated Figure 7-1.
DS-25PE16-143C
08/2018
Updated Figure 7-2.
AT25PE16
DS-25PE16-143C–8/2018
61
Corporate Office
California | USA
Adesto Headquarters
3600 Peterson Way
Santa Clara, CA 95054
Phone: (+1) 408.400.0578
Email: contact@adestotech.com
© 2017 Adesto Technologies. All rights reserved. / Rev.: DS-25PE16-143C–8/2018
Adesto®, the Adesto logo, CBRAM®, and DataFlash® are registered trademarks or trademarks of Adesto Technologies. All other marks are the property of their respective
owners. Adesto products in this datasheet are covered by certain Adesto patents registered in the United States and potentially other countries. Please refer to
http://www.adestotech.com/patents for details.
Disclaimer: Adesto Technologies Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Adesto's Terms
and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications
detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Adesto are granted by the
Company in connection with the sale of Adesto products, expressly or by implication. Adesto's products are not authorized for use as critical components in life support devices or systems.
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