AT25QF128A-SHB-T [DIALOG]
128 Mbit Serial NOR Flash Memory with Dual and Quad I/O Support;
| 型号： | AT25QF128A-SHB-T |
| 厂家： | 
Dialog Semiconductor |
| 描述： | 128 Mbit Serial NOR Flash Memory with Dual and Quad I/O Support |
| 文件： | 总55页 (文件大小：1610K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Following the acquisi�on of Adesto Technologies, Dialog Semiconductor offers memory products as part of its
product porꢀolio. The exis�ng content from datasheets, including part numbers and codes should be used. Terms of
Purchase are provided on the Dialog website
https://www.dialog-semiconductor.com/general-terms-and-conditions-purchase
View our Dialog memory products porꢀolio:
www.dialog-semiconductor.com/products/memory
Contacting Dialog Semiconductor
United Kingdom (Headquarters)
Dialog Semiconductor (UK) LTD
Phone: +44 1793 757700
North America
Dialog Semiconductor Inc.
Phone: +1 408 845 8500
Hong Kong
Dialog Semiconductor Hong Kong
Phone: +852 2607 4271
China (Shenzhen)
Dialog Semiconductor China
Phone: +86 755 2981 3669
Germany
Japan
Korea
China (Shanghai)
Dialog Semiconductor GmbH
Phone: +49 7021 805-0
Dialog Semiconductor K. K.
Phone: +81 3 5769 5100
Dialog Semiconductor Korea
Phone: +82 2 3469 8200
Dialog Semiconductor China
Phone: +86 21 5424 9058
The Netherlands
Taiwan
#
Dialog Semiconductor B.V.
Phone: +31 73 640 8822
Dialog Semiconductor Taiwan
Phone: +886 281 786 222
Email:
Web site:
enquiry@diasemi.com
www.dialog-semiconductor.com
DATASHEET
AT25QF128A
128 Mbit Serial NOR Flash Memory
with Dual and Quad I/O Support
Features
Single voltage operation with range of 2.7V to 3.6V
Default Operating Mode is SPI Quad I/O
Serial Peripheral Interface (SPI) compatible support
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-
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Supports SPI modes 0 and 3
Supports Dual Output and Quad Output read
Supports Dual I/O and Quad I/O read
Maximum Operating Frequency
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133 MHz maximum operating frequency at 85 oC
120 MHz maximum operating frequency at 105 oC
Read Operations
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70 MHz SPI normal read
120 MHz SPI fast read
133 MHz Quad Output fast read at 85 oC
Dual I/O data transfer rate up to 240 Mbps
Quad I/O data transfer rate up to 480 Mbps
Quad Output data transfer rate up to 532 Mbps
Continuous read with 8/16/32/64-byte wrap
Flexible programming
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Byte/Page program (1 to 256 Bytes)
Program suspend and resume
Fast program and erase times
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0.6 ms typical page (256 byte) program time
70 ms typical 4-Kbyte block erase time
150 ms typical 32-Kbyte block erase time
250 ms typical 64-Kbyte block erase time
Full chip erase: 60 s typical
Hardware and software Write Protection
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Hardware-controlled locking of protected sector via WP pin
Three 256-byte OTP-capable security registers
Write protect all or part of memory via software with top/bottom block selection
Serial Flash Discoverable Parameter (SFDP) register
Low power dissipation
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13 µA standby current at 85 oC
20 µA standby current at 105 oC
2 µA deep power down current at 85 oC
5 µA deep power down current at 105 oC
Endurance:
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100K program/erase cycles at 85 oC
10K program/erase cycles at 105 oC
Data Retention:
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20 years at 85 oC
10 years at 105 oC
Temperature Range:
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Industrial: -40 oC to 85 oC
Extended Temperature Range: -40 oC to 105 oC
Industry standard green (Pb/Halide-free/RoHS compliant) package options
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8-lead 0.208” Wide SOIC
8-pad (5 x 6 x 0.6 mm) UDFN
DS-AT25QF128A–176D–06-2020
Table of Contents
1. Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2. Package Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
3.1 Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2 Chip Select (CS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.4 Serial Input (Sl or I/O0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.5 Serial Data Output (SO or I/O1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.6 Write Protect (WP or I/O2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.7 Hold (HOLD or I/O3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.8 VCC Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.9 GND Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4. Block/Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
5. SPI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
5.1 Standard SPI Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.2 Dual SPI Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.3 Quad SPI Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6. Operating Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
6.1 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.1.1 Operating Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
6.1.2 Power-up Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
6.1.3 Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
6.1.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
6.2 Active Power and Standby Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.3 Hold Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.4 Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.4.1 Status Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
6.4.2 Status Register Protect Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
6.4.3 Write Protect Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
6.4.4 Status Register Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
7. Device Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
8. Instruction Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
8.1 Configuration and Status Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8.1.1 Write Enable (06h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
8.1.2 Write Disable (04h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
8.1.3 Read Status Register (05h or 35h or 15h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
8.1.4 Write Status Register (01h or 31h or 11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
8.1.5 Write Enable for Volatile Status Register (50h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
8.2 Read Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.2.1 Read Data (03h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
8.2.2 Fast Read (0Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
8.2.3 Dual Output Fast Read (3Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
AT25QF128A
DS-AT25QF128A–176D–06-2020
3
Table of Contents
8.2.4 Quad Output Fast Read (6Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
8.2.5 Dual I/O Fast Read (BBh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
8.2.6 Quad I/O Fast Read (EBh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
8.2.7 Quad I/O Word Fast Read (E7h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
8.2.8 Set Burst with Wrap (77h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
8.3 ID and Security Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.3.1 Read Manufacture ID/ Device ID (90h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
8.3.2 Dual I/O Read Manufacture ID/ Device ID (92h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
8.3.3 Quad I/O Read Manufacture ID/ Device ID (94h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
8.3.4 Read JEDEC ID (9Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
8.3.5 Read Unique ID Number (4Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
8.3.6 Deep Power-Down (B9h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
8.3.7 Release from Deep Power-Down/Read Device ID (ABh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
8.3.8 Read Security Registers (48h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
8.3.9 Erase Security Registers (44h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
8.3.10 Program Security Registers (42h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
8.3.11 Enable Reset (66h) and Reset Device (99h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
8.4 Program and Erase Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.4.1 Page Program (02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
8.4.2 SCKQuad Page Program (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
8.4.3 Fast Page Program (F2h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
8.4.4 Sector Erase (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
8.4.5 32KB Block Erase (52h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
8.4.6 64KB Block Erase (D8h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
8.4.7 Chip Erase (60/C7h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
8.4.8 Erase / Program Suspend (75h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
8.4.9 Erase / Program Resume (7Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
8.4.10 Read Serial Flash Discoverable Parameter (5Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
9. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
9.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.2 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.3 Data Retention and Endurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.4 Latch Up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.5 Power-up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.6 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.7 AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.8 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
11. Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
11.1 Package 8-Pin SOP 208-mil. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
11.2 Package 8 UDFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
12. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
AT25QF128A
DS-AT25QF128A–176D–06-2020
4
1.
Product Overview
The Adesto® AT25QF128A is a 128-Mbit Serial Peripheral Interface (SPI) Flash memory device designed for use
in a wide variety of high-volume consumer based applications in which program code is shadowed from Flash
memory into embedded or external RAM for execution. The flexible erase architecture of the AT25QF128A is ideal
for data storage as well, eliminating the need for additional data storage devices.
The SPI clock supports a maximum frequency of 133 MHz, enabling data transfers up to 532 Mbits/s for Quad
Output operations.
The AT25QF128A array is organized into 65,536 programmable pages of 256-bytes each. Up to 256 bytes can be
programmed at a time using the Page Program instructions. Pages can be erased in 4 KB, 32 KB, or 64 KB blocks,
or the entire chip.
The devices operate on a single 2.7V to 3.6V power supply with current consumption as low as 2 μA for Deep
Power Down at 85 oC. All devices offered in space-saving packages. The device supports JEDEC standard
manufacturer and device identification with three 256-byte secure OTP registers.
2.
Package Pinouts
Figure 2-1 show the package pinouts for the following devices.
1
2
3
4
8
7
6
5
VCC
CS
HOLD (I/O )
SO (I/O1)
3
8-lead 8S1 SOIC Package (208-mil)
WP (I/O2)
GND
SCK
SI (I/O0)
1
8
7
6
5
VCC
CS
SO (I/O1)
WP (I/O2)
GND
2
3
4
HOLD (I/O3)
8-pad UDFN Package
SCK
SI (I/O0)
Figure 2-1. Adesto AT25QF128A Flash Memory Package Types
AT25QF128A
DS-AT25QF128A–176D–06-2020
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3.
Pin Descriptions
During all operations, VCC must be held stable and within the specified valid range: VCC (min) to VCC (max).
All of the input and output signals must be held high or low (according to voltages of VIH, VOH, VIL or VOL, see
Section 9.6, DC Electrical Characteristics). These pins are described below.
3.1
Pin Summary
Table 3-1. AT25QF128A Pin Names
Pin Name
CS
I/O
I
Description
Chip select.
SO (IO1)
I/O
Serial Output for single bit data Instructions. IO1 for dual or quad Instructions.
Write Protect in single bit or dual data Instructions. IO2 in quad mode. The signal
has an internal pull-up resistor and may be left unconnected in the host system if
not used for quad Instructions.
WP (IO2)
I/O
GND
SI (IO0)
SCK
Ground.
I/O
I
Serial input for single bit data Instructions. IO0 for dual or quad Instructions.
Serial clock.
Hold (pause) serial transfer in single bit or dual data Instructions. IO3 in Quad-I/O
mode. The signal has an internal pull-up resistor and may be left unconnected in
the host system if not used for Quad Instructions.
HOLD (IO3)
VCC
I/O
Core and I/O power supply.
3.2
Chip Select (CS)
The chip select signal indicates when a instruction for the device is in process and the other signals are relevant for
the memory device. When the CS signal is at the logic high state, the device is not selected and all input signals
are ignored and all output signals are high impedance. Unless an internal Program, Erase or Write Status
Registers embedded operation is in progress, the device remains in the Standby Power mode. Driving the CS input
to logic low state enables the device, placing it in the Active Power mode. After Power Up, a falling edge on CS is
required prior to the start of any instruction.
3.3
3.4
Serial Clock (SCK)
This input signal provides the synchronization reference for the SPI interface. Instructions, addresses, or data input
are latched on the rising edge of the SCK signal. Data output changes after the falling edge of SCK.
Serial Input (Sl or I/O0)
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and data to be
programmed. Values are latched on the rising edge of serial SCK clock signal.
SI becomes I/O0 an input and output during Dual and Quad Instructions for receiving instructions, addresses, and
data to be programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out data (on
the falling edge of SCK).
AT25QF128A
DS-AT25QF128A–176D–06-2020
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3.5
3.6
Serial Data Output (SO or I/O1)
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of the
serial SCK clock signal.
The SO pin becomes an I/O pin (I/O1) during Dual and Quad Instructions for receiving instructions, addresses, and
data to be programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out data (on
the falling edge of SCK).
Write Protect (WP or I/O2)
When WP is driven low, while the Status Register Protect bits (SRP1 and SRP0) of the Status Registers are set to
0 and 1 respectively, it is not possible to write to the Status Registers. This prevents any alteration of the Status
Registers. As a consequence, all the data bytes in the memory area that are protected by the Block Protect, TB,
SEC, and CMP bits in the status registers, are also hardware protected against data modification while WP
remains low. The WP function is not available when the Quad mode is enabled. In the AT25QF128A, the QE bit in
Status Register 2 is set to 1 after power-on.
The WP function is replaced by I/O2 for input and output during Quad mode for receiving addresses, and data to be
programmed (values are latched on rising edge of the SCK signal) as well as shifting out data (on the falling edge
of SCK). WP has an internal pull-up resistance; when unconnected; WP is at VIH and may be left unconnected in
the host system if not used for Quad mode.
3.7
Hold (HOLD or I/O3)
The HOLD function is only available when the Quad Enable (QE) bit in Status Register 2 = O. If QE = 1, The HOLD
function is disabled and the pin acts as dedicated data I/O pin. Note that the AT25QF128A device ships with the
QE bit set at the factory, causing the device to power up in Quad mode.
The HOLD signal goes low to stop any serial communication with the device, but doesn't stop the operation of write
status register, programming, or erasing in progress.
3.8
3.9
VCC Power Supply
VCC is the supply voltage. It is the single voltage used for all device functions including read, program, and erase.
GND Ground
GND is the ground reference for the VCC supply voltage.
AT25QF128A
DS-AT25QF128A–176D–06-2020
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4.
Block/Sector Addresses
Table 4-1. Block/Sector Addresses of AT25QF128A
Block
(64k byte)
Block
(32k byte)
Memory
Density
Sector Size
(KB)
Sector No.
Address Range
Sector 0
4
:
000000h - 000FFFh
Half block
0
:
:
Sector 7
4
4
007000h - 007FFFh
Block 0
Sector 8
008000h - 008FFFh
Half block
1
:
:
Sector 15
4
4
:
00F000h - 00FFFFh
Sector 16
010000h - 010FFFh
Half block
2
:
:
Sector 23
4
4
:
017000h - 017FFFh
Block 1
Sector 24
018000h - 018FFFh
Half block
3
:
:
Sector 31
4
:
01F000h - 01FFFFh
128 Mbit
:
:
:
:
Sector 4064
:
4
:
FE0000h - FE0FFFh
Half block
508
:
Sector 4071
Sector 4072
:
4
4
:
FE7000h - FE7FFFh
FE8000h - FE8FFFh
:
Block 254
Half block
509
Sector 4079
Sector 4080
:
4
4
:
FEF000h - FEFFFFh
FF0000h - FF0FFFh
:
Half block
510
Sector 4087
Sector 4088
:
4
4
:
FF7000h - FF7FFFh
FF8000h - FF8FFFh
:
Block 255
Half block
511
Sector 4095
4
FFF000h - FFFFFFh
AT25QF128A
DS-AT25QF128A–176D–06-2020
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5.
SPI Operation
5.1
Standard SPI Instructions
The AT25QF128A features a 4-pin serial peripheral interface on 4 signals bus: Serial Clock (SCK), Chip Select
(CS), Serial Data Input (SI) and Serial Data Output (SO). SPI bus modes 0 and 3 are supported. Input data is
latched on the rising edge of SCK and data shifts out on the falling edge of SCK.
5.2
5.3
Dual SPI Instructions
The AT25QF128A supports Dual SPI operation when using the Dual Output Fast Read (3BH), Dual I/O Fast Read
(BBH) and Read Manufacture ID/Device ID Dual I/O (92H) instructions. These instructions allow data to be
transferred to or from the device at two times the rate of the standard SPI. When using the Dual SPI instruction the
SI and SO pins become bidirectional I/O pins: I/O0 and I/O1 respectively.
Quad SPI Instructions
The AT25QF28A device ships with the Quad Enable (QE) bit set in the Status Register. This causes the device to
power-up in SPI Quad I/O mode.
The AT25QF128A supports Quad SPI operation when using the Quad Output Fast Read (6BH), Quad I/O Fast
Read (EBH), Quad I/O Word Fast Read (E7h), Read Manufacture ID/Device ID Quad I/O (94H) and Quad Page
Program (32H) instructions. These instructions allow data to be transferred to or from the device at four times the
rate of the standard SPI. When using the Quad SPI instruction the SI and SO pins become bidirectional I/O pins:
I/O0 and I/O1, and /WP and HOLD pins become I/O2 and I/O3. Quad SPI instructions require the non-volatile Quad
Enable bit (QE) in Status Register to be set.
6.
Operating Features
6.1
Supply Voltage
6.1.1 Operating Supply Voltage
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified VCC
(min) / VCC (max) range must be applied. In order to secure a stable DC supply voltage, it is recommended to
decouple the VCC line with a 1 μF low-ESR ceramic decoupling capacitor, placed as close as possible to the
VCC/GND package pins. This voltage must remain stable and valid until the end of the transmission of the
instruction and, for a Write instruction, until the completion of the internal write cycle (tW).
6.1.2 Power-up Conditions
When the power supply is turned on, VCC rises continuously from GND to VCC. During this time, the Chip Select
(CS) line is not allowed to float but should follow the VCC voltage, it is therefore recommended to connect the CS
line to VCC via a pull-up resistor.
In addition, the CS input is both edge sensitive and level sensitive. After power-up, the device does not become
selected until a falling edge is first detected on CS. This ensures that CS must have been High, prior to going Low
to start the first operation.
AT25QF128A
DS-AT25QF128A–176D–06-2020
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6.1.3 Device Reset
In order to prevent inadvertent Write operations during power-up (continuous rise of VCC), a power on reset (POR)
circuit is included. At Power-up, the device does not respond to any instruction until VCC has reached the power
on reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined by the DC
operating ranges).
When VCC has passed the POR threshold, the device is reset.
6.1.4 Power-down
At Power-down (continuous decrease in VCC), as soon as VCC drops from the normal operating voltage to below
the power on reset threshold voltage, the device stops responding to any instruction sent to it. During Power-down,
the device must be deselected (Chip Select, CS, must be allowed to follow the voltage applied on VCC) and in
Standby Power mode (no internal Write cycle in progress).
6.2
6.3
Active Power and Standby Power Modes
When Chip Select (CS) is low, the device is selected and in the Active Power mode and consuming current (ICC).
When Chip Select (CS) is high, the device is deselected. If a Write cycle is not currently in progress, the device
enters the Standby Power mode, and the current consumption drops to ICC1.
Hold Condition
The HOLD signal pauses any serial communications with the device without resetting the clocking sequence.
During a Hold, the Serial Data Output (SO) is high impedance, and Serial Data Input (SI) and Serial Clock (SCK)
are don't care. Note that the HOLD function can only be used with the QE bit of the Status Register = 0.
To enter the Hold condition, the device must be selected, with Chip Select (CS) low. Normally, the device remains
selected for the duration of the Hold condition. Deselecting the device while it is in the Hold condition, has the effect
of resetting the state of the device, and this mechanism can be used if it is required to reset any processes that had
been in progress.
The Hold condition starts when the Hold (HOLD) signal is driven Low at the same time as Serial Clock (SCK)
already being Low (as shown in Figure 6-1).
The Hold condition ends when the Hold (HOLD) signal is driven High at the same time as Serial Clock (C) already
being Low. Figure 6-1 also shows what happens if the rising and falling edges are not timed to coincide with Serial
Clock (SCK) being Low.
CS
SCK
HOLD
HOLD
HOLD
Figure 6-1. Hold Condition Activation
AT25QF128A
DS-AT25QF128A–176D–06-2020
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6.4
Status Register
The AT25QF128A contains three Status registers. Each byte is written or read using specific instructions. For a
read operation, the 05h, 35h, and 15h instructions are used to access the S7 - S0, S15 - S8, and S23 - S16 bytes
respectively. For a write operation, the 01h, 31h, and 11h instructions are used as shown in Table 8-1.
The following diagram shows the layout of the Status Register bits.
Table 6-1. Status Register 3
S23
S22
S21
S20
S19
S18
S17
S16
Reserved
DRV1
DRV0
Reserved
Reserved
Reserved
Reserved
Reserved
Table 6-2. Status Register 2
S15
S14
S13
S12
S11
S10
S9
S8
SUS1
CMP
LB3
LB2
LB1
SUS2
QE
SRP1
Table 6-3. Status Register 1
S7
S6
S5
S4
S3
S2
S1
S0
SRP0
BP4
BP3
BP2
BP1
BP0
WEL
WIP
6.4.1 Status Register Bit Definitions
6.4.1.1 WIP bit (S0)
The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register
progress. When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when
WIP bit sets 0, means the device is not in program/erase/write status register progress.
6.4.1.2 WEL bit (S1)
The Write Enable Latch bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write
Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program
or Erase instruction is accepted.
6.4.1.3 BP4, BP3, BP2, BP1, BP0 Bits (S6 - S2)
The Block Protect (BP4, BP3, BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software
protected against Program and Erase instructions. These bits are written with the Write Status Register instruction.
• When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory becomes protected
against Page Program, Sector Erase and Block Erase instructions.
• The Block Protect (BP4, BP3, BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode
has not been set.
• The Chip Erase (CE) instruction is executed if the Block Protect (BP2, BP1, BP0) bits are 0 and CMP = 0 or the
Block Protect (BP2, BP1, BP0) bits are 1 and CMP = 1.
6.4.1.4 SRP1, SRP0 Bits (S8 - S7)
The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP
bits control the method of write protection: software protection, hardware protection, or power supply lock-down.
AT25QF128A
DS-AT25QF128A–176D–06-2020
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6.4.1.5 QE Bit (S9)
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When
the QE bit is cleared to 0 (default), the WP and HOLD pins are enabled. When the QE pin is set to 1, the Quad I/O2
and I/O3 pins are enabled. Note that the QE bit should never be set to 1 during standard SPI or Dual SPI operation
if the WP or HOLD pins are connected directly to the power supply or ground. Note that if these pins are connected
to power or ground, software must first clear the QE bit.
6.4.1.6 SUS1/SUS2 Bits (S15, S10)
The SUS1 and SUS2 bits are read only bits in the status register2 (S15 and S10) that are set to 1 after executing
an Erase/Program Suspend (75h) instruction (The Erase Suspend sets SUS1 to 1, and the Program Suspend sets
SUS2 to 1). The SUS1 and SUS2 bits are cleared to 0 by Erase/Program Resume (7Ah) instruction as well as a
power-down, power-up cycle.
6.4.1.7 LB3/LB2/LB1 bit (S13 - S11)
The LB bits are non-volatile One Time Program (OTP) bits in Status Register (S13 - S11) that provide the write
protect control and status to the Security Registers. The default state of LBx is 0, the security registers are
unlocked. The LBx bits can be set to 1 individually using the Write Register instruction. The LBx bits are One Time
Programmable. Once they are set to 1, the Security Registers become read-only permanently.
6.4.1.8 CMP Bit (S14)
The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction the SEC and
BP0 bits to provide more flexibility for the array protection. Please see the Status registers Memory Protection table
for details. The default setting is CMP = 0.
6.4.1.9 DRV1/DRV0 Bits (S22, S21)
The DRV1 and DRV0 bits are used to determine the output driver strength for the Read instruction. m
Table 6-4. DRV1 / DRV0 Bit Encoding
DRV1, DRV0
Driver Strength
100% (default)
75%
00
01
10
11
50%
25%
AT25QF128A
DS-AT25QF128A–176D–06-2020
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6.4.2 Status Register Protect Table
The Status Register Protect (SRP1 and SRP0) bit are non-volatile Read/Write bits in the Status Register. The SRP
bits control the method of write protection: software protection, hardware protection, power supply lock-down or
one time programmable protection.
Table 6-5. Status Register Protect Table
SRP1
SRP0
WP
Status Register
Description
The Status Register can be written to after a Write
Enable instruction, WEL = 1 (Factory Default).
0
0
X
Software Protected
WP = 0, the Status Register locked and cannot be
written.
0
0
1
1
0
1
Hardware Protected
WP = 1, the Status Register is unlocked and can be
written to after a Write Enable instruction, WEL = 1.
Hardware Unprotected
Power Supply Lock-Down 1
Status Register is protected and cannot be written to
again until the next Power-Down, Power-Up cycle.
1
1
0
1
X
X
Not allowed.
1. When SRP1, SRP0 = (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.
6.4.3 Write Protect Features
1. Software Protection: The Block Protect (BP4, BP3, BP2, BP1, BP0) bits define the section of the memory array
that can be read but not change.
2. Hardware Protection: WP going low to protected the writable bits of Status Register.
3. Deep Power-Down: In Deep Power-Down mode, all instructions are ignored except the Release from Deep
Power-Down Mode instruction.
4. Write Enable: The Write Enable instruction is set the Write Enable Latch (WEL) bit. The WEL bit is reset under
any of the following conditions:
• Power -up
• Write Disable
• Write Status Register
• Page Program
• Sector Erase/Block Erase/Chip Erase
• Software Reset
AT25QF128A
DS-AT25QF128A–176D–06-2020
13
6.4.4 Status Register Memory Protection
6.4.4.1 Protect Table
Table 6-6. AT25QF128A Status Register Memory Protection (CMP = 0)
Status Register Content
Memory Content
Addresses
BP4
X
0
BP3
X
0
BP2
0
0
0
0
1
1
1
0
0
0
1
1
1
1
0
0
0
1
1
0
0
0
1
1
BP1
0
BP0
0
Blocks
NONE
252 to 255
248 to 255
240 to 255
224 to 255
192 to 255
128 to 255
0 to 3
0 to 7
0 to 15
0 to 31
0 to 63
0 to 127
0 to 255
255
Density
NONE
256 kB
512 kB
1 MB
2 MB
4 MB
8 MB
256 kB
512 kB
1 MB
2 MB
4 MB
8 MB
16 MB
4 kB
Portion
NONE
NONE
0
1
FC0000h - FFFFFFh
F80000h - FFFFFFh
F00000h - FFFFFFh
E00000h - FFFFFFh
C00000h - FFFFFFh
800000h - FFFFFFh
000000h - 03FFFFh
000000h - 07FFFFh
000000h - 0FFFFFh
000000h - 1FFFFFh
000000h - 3FFFFFh
000000h - 7FFFFFh
000000h - FFFFFFh
FFF000h - FFFFFFh
FFE000h - FFFFFFh
FFC000h - FFFFFFh
FF8000h - FFFFFFh
FF8000h - FFFFFFh
000000h - 000FFFh
000000h - 001FFFh
000000h - 003FFFh
000000h - 007FFFh
000000h - 007FFFh
Upper 1/64
Upper 1/32
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
Upper 1/64
Upper 1/32
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
ALL
0
0
1
0
0
0
1
1
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
1
0
1
1
0
0
1
1
1
0
1
0
0
0
1
0
1
0
1
1
0
X
1
X
0
1
1
0
1
Top Block
Top Block
Top Block
Top Block
Top Block
Bottom Block
Bottom Block
Bottom Block
Bottom Block
Bottom Block
1
0
1
0
255
8 kB
1
0
1
1
255
16 kB
32 kB
32 kB
4 kB
1
0
0
X
0
255
1
0
1
255
1
1
0
1
0
1
1
1
0
0
8 kB
1
1
1
1
0
16 kB
32 kB
32 kB
1
1
0
X
0
0
1
1
1
0
AT25QF128A
DS-AT25QF128A–176D–06-2020
14
Table 6-7. AT25QF128A Status Register Memory Protection (CMP = 1)
Status Register Content
Memory Content
BP4
X
0
BP3
X
0
BP2
0
0
0
0
1
1
1
0
0
0
1
1
1
1
0
0
0
1
1
0
0
0
1
1
BP1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
1
1
0
1
0
1
1
0
1
BP0
0
Blocks
0 to 255
0 to 251
0 to 247
0 to 239
0 to 223
0 to 191
0 to 127
4 to 255
8 to 255
16 to 255
32 to 255
64 to 255
128 to 255
NONE
Addresses
Density
ALL
Portion
ALL
000000h - FFFFFFh
000000h - FBFFFFh
000000h - F7FFFFh
000000h - EFFFFFh
000000h - DFFFFFh
000000h - BFFFFFh
000000h - 7FFFFFh
040000h - FFFFFFh
080000h - FFFFFFh
100000h - FFFFFFh
200000h - FFFFFFh
400000h - FFFFFFh
800000h - FFFFFFh
NONE
1
16128 kB
15872 kB
15 KB
Lower 63/64
Lower 31/32
Lower 15/16
Lower 7/8
0
0
0
0
0
1
0
0
0
14 MB
0
0
1
12 MB
Lower 3/4
0
0
0
8 MB
Lower 1/2
0
1
1
16,128 kB
15,872 kB
15 kB
Upper 63/64
Upper 31/32
Upper 15/16
Upper 7/8
0
1
0
0
1
1
0
1
0
14 MB
0
1
1
12 MB
Upper 3/4
0
1
0
8 MB
Upper 1/2
X
1
X
0
1
NONE
NONE
1
0 to 255
0 to 255
0 to 255
0 to 255
0 to 255
0 to 255
0 to 255
0 to 255
0 to 255
0 to 255
000000h - FFEFFFh
000000h - FFDFFFh
000000h - FFBFFFh
000000h - FF7FFFh
000000h - FF7FFFh
001000h - FFFFFFh
002000h - FFFFFFh
004000h - FFFFFFh
008000h - FFFFFFh
008000h - FFFFFFh
16380 kB
16376 kB
16368 kB
16352 kB
16352 kB
16380 kB
16376 kB
16368 kB
16352 kB
16352 kB
L-4095/4096
L-2047/2048
L-1023/1024
L-511/512
L-511/512
U-4095/4096
U-2047/2048
U-1023/1024
U-511/512
U-511/512
1
0
0
1
0
1
1
0
X
0
1
0
1
1
1
1
1
0
1
1
1
1
1
X
0
1
1
AT25QF128A
DS-AT25QF128A–176D–06-2020
15
7.
Device Identification
Three legacy Instructions are supported to access device identification that can indicate the manufacturer, device
type, and capacity (density). The returned data bytes provide the information as shown in the below table.
Table 7-1. AT25QF128A ID Definition table
Operating Code
9Fh
M7-M0
1Fh
ID15-ID8
ID7-ID0
01h
89h
90h/92h/94h
ABh
1Fh
17h
17h
8.
Instruction Descriptions
All instructions, addresses and data are shifted in and out of the device, beginning with the most significant bit on
the first rising edge of SCK after CS is driven low. Then, the one byte instruction code must be shifted in to the
device, most significant bit first on SI, each bit being latched on the rising edges of SCK.
See Table 8-1, every instruction sequence starts with a one-byte instruction code. Depending on the instruction,
this might be followed by address bytes, data bytes, both, or none. The CS pin must be driven high after the last bit
of the instruction sequence has been shifted in.
For the Read, Fast Read, Read Status Register, Release from Deep Power Down, and Read Device ID
instructions, the shifted-in instruction sequence is followed by a data out sequence. The CS pin can be driven high
after any bit of the data-out sequence is being shifted out.
For the instruction of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable,
Write Disable or Deep Power-Down instruction, CS must be driven high exactly at a byte boundary, otherwise the
instruction is rejected, and is not executed. That is CS must driven high when the number of clock pulses after CS
being driven low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte,
nothing will happen and WEL will not be reset.
Table 8-1.Instruction Set
Instruction Name
Write Enable
Byte 1
06h
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
N-Bytes
Write Disable
04h
Read Status Register-1
Read Status Register-2
Read Status Register-3
05h
(S7 - S0)
(S15 - S8)
(S23 - S16)
continuous
continuous
continuous
35h
15h
Write Enable for Volatile
Status Register
50h
Write Status Register-1
Write Status Register-2
Write Status Register-3
Read Data
01h
31h
11h
03h
0Bh
(S7 - S0)
(S15 - S8)
(S23 - S16)
A23 - A16
A23 - A16
A15 - A8
A15 - A8
A7 - A0
A7 - A0
(D7 - D0)
dummy
Next byte
(D7 - D0)
continuous
continuous
Fast Read
AT25QF128A
DS-AT25QF128A–176D–06-2020
16
Table 8-1.Instruction Set (continued)
Instruction Name
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
N-Bytes
Dual Output Fast Read
3Bh
A23 - A16
A15 - A8
A7 - A0
dummy
(D7 - D0)(1)
continuous
A7 - A0
Dual I/O Fast Read
Quad Output Fast Read
Quad I/O Fast Read
BBh
6Bh
EBh
A23 - A8(2)
A23 - A16
(D7 - D0)(1)
A7 - A0
Next byte
dummy
Next byte
(D7 - D0)(3)
Next byte
continuous
continuous
continuous
M7 - M0(2)
A15 - A8
dummy(5)
A23 - A0
(D7 - D0)(3)
Next byte
M7 - M0(4)
Quad I/O Word Fast
Read(7)
A23 - A0
E7h
dummy(6)
(D7 - D0)(3)
Next byte
Next byte
continuous
M7 - M0 (4)
Page Program
Quad Page Program
Fast Page Program
Sector Erase
02h
32h
A23 - A16
A23 - A16
A23 - A16
A23 - A16
A23 - A16
A23 - A16
A15 - A8
A15 - A8
A15 - A8
A15 - A8
A15 - A8
A15 - A8
A7 - A0
A7 - A0
A7 - A0
A7 - A0
A7 - A0
A7 - A0
(D7 - D0)
(D7 - D0)(3)
(D7 - D0)
Next byte
Next byte
Next byte
continuous
continuous
continuous
F2h
20h
Block Erase(32K)
Block Erase (64K)
Chip Erase
52h
D8h
C7/60h
66h
Enable Reset
Reset
99h
dummy(6)
W7 - W0
Set Burst with Wrap
77h
Program/Erase Suspend
Program/Erase Resume
Deep Power-Down
75h
7Ah
B9h
Release From Deep
Power-Down, And Read
Device ID
ABh
dummy
dummy
dummy
dummy
00H
(ID7 - ID0)
continuous
Release From Deep
Power-Down
ABh
90h
Manufacturer/ Device ID
dummy
(MID7 - MID0)
(ID7 - ID0)
continuous
continuous
A7 - A0,
dummy
Manufacturer/ Device ID
by Dual I/O
(MID7 - MID0),
(DID7 -DID0)
92h
A23 - A8
dummy(10)
A23 - A0,
dummy
Manufacturer/ Device ID
by Quad I/O
(MID7 -
MID0)
94h
9Fh
continuous
continuous
(DID7 - DID0)
MID7 -
MID0
JEDEC ID
ID15 - ID8
ID7-ID0
AT25QF128A
DS-AT25QF128A–176D–06-2020
17
Table 8-1.Instruction Set (continued)
Instruction Name
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
N-Bytes
Read Serial Flash
Discoverable Parameter
5Ah
A23 - A16
A15 - A8
A7-A0
Dummy
D7 - D0
continuous
Erase Security
Registers(8)
44h
42h
48h
A23 - A16
A23 - A16
A23 - A16
A15 - A8
A15 - A8
A15 - A8
A7-A0
A7-A0
A7-A0
Program Security
Registers(8)
(D7 - D0)
dummy
(D7 - D0)
(D7 - D0)
continuous
continuous
Read Security
Registers(8)
Notes:
1. Dual Output data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
2. Dual Input Address
IO0 = A22, A20, A18, A16, A14, A12, A10, A8, A6, A4, A2, A0, M6, M4, M2, M0
IO1 = A23, A21, A19, A17, A15, A13, A11, A9, A7, A5, A3, A1, M7, M5, M3,M1
3. Quad Output Data
IO0 = (D4, D0,…..)
IO1 = (D5, D1,…..)
IO2 = (D6, D2,…..)
IO3 = (D7, D3,…..)
4. Quad Input Address
IO0 = A20, A16, A12, A8, A4, A0, M4, M0
IO1 = A21, A17, A13, A9, A5, A1, M5, M1
IO2 = A22, A18, A14, A10, A6, A2, M6, M2
IO3 = A23, A19, A15, A11, A7, A3, M7, M3
5. Fast Read Quad I/O Data
IO0 = (x, x, x, x, D4, D0,…)
IO1 = (x, x, x, x, D5, D1,…)
IO2 = (x, x, x, x, D6, D2,…)
IO3 = (x, x, x, x, D7, D3,…)
6. Fast Word Read Quad I/O Data
IO0 = (x, x, D4, D0,…)
IO1 = (x, x , D5, D1,…)
IO2 = (x, x, D6, D2,…)
IO3 = (x, x, D7, D3,…)
7. Fast Word Read Quad I/O Data:the lowest address bit must be 0.
8. Security Registers Address:
Security Register 1: A23 - A16 = 00h, A15 - A8 = 00010000b, A7 - A0 = Byte Address;
Security Register 2: A23 - A16 = 00h, A15 - A8 = 00100000b, A7 - A0 = Byte Address;
Security Register 3: A23 - A16 = 00h, A15 - A8 = 00110000b, A7 - A0 = Byte Address;
9. Dummy bits and Wraps Bits
IO0 = (x, x, x, x, x, x, w4, x)
IO1 = (x, x, x, x, x, x, w5, x)
IO2 = (x, x, x, x, x, x, w6, x)
IO3 = (x, x, x, x, x, x, x, x)
10. Address, continuous Read Mode bits, Dummy bits, Manufacture ID and Device ID
IO0 = (A20, A16, A12, A8, A4, A0, M4, M0, x, x, x, x, MID4, MID0, DID4, DID0)
IO1 = (A21, A17, A13, A9, A5, A1, M5, M1, x, x, x, x, MID5, MID1, DID5, DID1)
IO2 = (A22, A18, A14, A10, A6, A2, M6, M2, x, x, x, x, MID6, MID2, DID6, DID2)
IO3 = (A23, A19, A15, A11, A7, A3, M7, M3, x, x, x, x, MID7, MID3, DID7, DID3)
AT25QF128A
DS-AT25QF128A–176D–06-2020
18
8.1
Configuration and Status Instructions
8.1.1 Write Enable (06h)
The Write Enable instruction is for setting the Write Enable Latch (WEL) bit. The WEL bit must be set prior to every
Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, and Erase/Program Security
Registers instruction.
The Write Enable instruction sequence: CS goes low sending the Write Enable instruction CS goes high.
CS
0
1
2
3
4
5
6
7
SCK
SI
OPCODE
0
MSB
0
0
0
0
1
1
0
HIGH-IMPEDANCE
SO
Figure 8-1. Write Enable Sequence Diagram
8.1.2 Write Disable (04h)
The Write Disable instruction is for resetting the Write Enable Latch bit. The Write Disable instruction sequence:
CS goes low → sending the Write Disable instruction → CS goes high. The WEL bit is reset by following condition:
Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase, Chip
Erase, Erase/Program Security Registers, and Reset instructions.
CS
0
1
2
3
4
5
6
7
SCK
SI
OPCODE
0
MSB
0
0
0
0
1
0
0
HIGH-IMPEDANCE
SO
Figure 8-2. Write Disable Sequence Diagram
8.1.3 Read Status Register (05h or 35h or 15h)
The Read Status Register (RDSR) instruction is for reading the Status Register. The Status Register may be read
at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles
is in progress, it is recommended to check the Write in Progress (WIP) bit before sending a new instruction to the
device. It is also possible to read the Status Register continuously. For instruction code 05h, the SO outputs Status
Register bits S7 - S0. For instruction code 35h, the SO outputs Status Register bits S15 - S8. For instruction code
15h, the SO outputs Status Register bits S23 - 16.
AT25QF128A
DS-AT25QF128A–176D–06-2020
19
Figure 8-3 shows a Read Status Register operation for Status Register 1 (05h). The Read Status Register 2 and 3
operations would be the same, but with a different opcode in the first eight clocks.
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
SCK
SI
OPCODE
0
MSB
0
0
0
0
1
0
1
STATUS REGISTER
DATA
STATUS REGISTER
DATA
STATUS REGISTER
DATA
HIGH-IMPEDANCE
D
MSB
D
D
D
D
D
D
D
D
MSB
D
D
D
D
D
D
D
D
MSB
D
D
D
D
D
D
D
SO
Figure 8-3. Read Status Register Sequence Diagram
8.1.4 Write Status Register (01h or 31h or 11h)
The Write Status Register instruction allows new values to be written to the Status Register. Before it can be
accepted, a Write Enable instruction must previously have been executed. After the Write Enable instruction has
been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register instruction has no effect on S23, S20, S19, S18, S17, S16, S15, S1 and S0 of the Status
Register. CS must be driven high after the eighth bit of the data byte has been latched in. If not, the Write Status
Register instruction is not executed. As soon as CS is driven high, the self-timed Write Status Register cycle
(whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still
be read to check the value of the Write in Progress (WIP) bit. This bit is 1 during the self-timed Write Status
Register cycle, and is 0 when it is completed. When the cycle is completed, the WEL bit is reset.
The Write Status Register instruction allows the user to change the values of the Block Protect (BP4, BP3, BP2,
BP1, BP0) bits, to define the size of the area that is to be treated as read-only. The Write Status Register
instruction also allows the user to set or reset the Status Register Protect (SRP1 and SRP0) bits in accordance
with the Write Protect (WP) signal. The Status Register Protect (SRP1 and SRP0) bits and Write Protect (WP)
signal allow the device to be put in the Hardware Protected Mode. The Write Status Register instruction is not
executed once the Hardware Protected Mode is entered.
Figure 8-4 shows a Write Status Register operation for Status Register 1 (01h). The Write Status Register 2 and 3
operations would be the same, but with a different opcode in the first eight clocks.
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCK
SI
OPCODE
STATUS REGISTER IN
0
MSB
0
0
0
0
0
0
1
D
X
X
X
X
D
X
X
MSB
HIGH-IMPEDANCE
SO
Figure 8-4. Write Status Register Sequence Diagram
AT25QF128A
DS-AT25QF128A–176D–06-2020
20
8.1.5 Write Enable for Volatile Status Register (50h)
The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to change the
system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write
cycles or affecting the endurance of the Status Register non-volatile bits. The Write Enable for Volatile Status
Register instruction does not set the Write Enable Latch bit, it is only valid for the Write Status Registers instruction
to change the volatile Status Register bit values.
CS
0
1
2
3
4
5
6
7
Mode 3
Mode 0
Mode 3
Mode 0
SCK
Instruction
50h
S1 (IO0)
S0 (IO1)
HIGH-IMPEDANCE
Figure 8-5. Write Enable for Volatile Status Register
8.2
Read Instructions
8.2.1 Read Data (03h)
The Read Data instruction is followed by a 3-byte address (A23 - A0), each bit being latched-in during the rising
edge of SCK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max
frequency fC2, during the falling edge of SCK. The address automatically increments to the next higher address
after each byte of data is shifted out allowing for a continuous stream of data. This means that the entire memory
can be accessed with a single command as long as the clock continues. The command is completed by driving CS
high. The whole memory can be read with a single Read Data Bytes (READ) instruction. Any Read Data instruction
attempting to execute while an Erase, Program or Write cycle is in progress, is rejected without having any effects
on the cycle that is in progress.
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35 36 37 38 39 40
SCK
SI
OPCODE
ADDRESS BITS A23-A0
0
MSB
0
0
0
0
0
1
1
A
MSB
A
A
A
A
A
A
A
A
DATA BYTE 1
HIGH-IMPEDANCE
D
MSB
D
D
D
D
D
D
D
D
MSB
D
SO
Figure 8-6. Read Data Bytes Sequence Diagram
AT25QF128A
DS-AT25QF128A–176D–06-2020
21
8.2.2 Fast Read (0Bh)
The Read Data at Higher Speed (Fast Read) instruction is for quickly reading data out. It is followed by a three-byte
address (A23 - A0) and a dummy byte, each bit being latched-in during the rising edge of SCK. Then the memory
content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency of fc4 during the falling
edge of SCK. The first byte addressed can be at any location. The address automatically increments to the next
higher address after each byte of data is shifted out.
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
SCK
SI
OPCODE
ADDRESS BITS A23-A0
DON'T CARE
0
MSB
0
0
0
1
0
1
1
A
MSB
A
A
A
A
A
A
A
A
X
MSB
X
X
X
X
X
X
X
DATA BYTE 1
HIGH-IMPEDANCE
D
MSB
D
D
D
D
D
D
D
D
MSB
D
SO
Figure 8-7. Fast Read Sequence Diagram
8.2.3 Dual Output Fast Read (3Bh)
The Dual Output Fast Read instruction is followed by 3-byte address (A23 - A0) and a dummy byte, each bit being
latched in during the rising edge of SCK, then the memory contents are shifted out 2-bit per clock cycle from SI and
SO. The first byte addressed can be at any location. The address automatically increments to the next higher
address after each byte of data is shifted out.
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
SCK
OUTPUT
DATA BYTE1
OUTPUT
DATA BYTE2
OPCODE
ADDRESS BITS A23-A0
DON'T CARE
A
MSB
A
A
A
A
A
A
A
D
X
D
D
D
D
D
D
D
0
2
X
D
D
4
6
X
X
SI (SIO)
SO
X
X
X
X
4
0
4
6
2
6
MSB
HIGH-IMPEDANCE
D
D
D
D
D
D
D
D
D
D
5
7
5
1
5
1
7
3
7
3
Figure 8-8. Dual Output Fast Read Sequence Diagram
AT25QF128A
DS-AT25QF128A–176D–06-2020
22
8.2.4 Quad Output Fast Read (6Bh)
The Quad Output Fast Read instruction is followed by 3-byte address (A23 - A0) and a dummy byte, each bit being
latched in during the rising edge of SCK, then the memory contents are shifted out 4-bit per clock cycle from IO3,
IO2, IO1 and IO0. The first byte addressed can be at any location. The address automatically increments to the next
higher address after each byte of data is shifted out.
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Byte 1 Byte 2 Byte 3 Byte 4 Byte 5
SCK
OUT
OUT
OUT
OUT
OUT
Opcode
Address Bits A23-A0
Don't Care
C
C
C
C
C
C
C
A
MSB
A
A
A
A
A
A
A
A
X
MSB
X
X
X
X
X
X
X
D4 D0 D4 D0 D4 D0 D4 D0 D4 D0
D5 D1 D5 D1 D5 D1 D5 D1 D5 D1
D6 D2 D6 D2 D6 D2 D6 D2 D6 D2
C
MSB
I/O0
(SI)
High-impedance
High-impedance
High-impedance
I/O1
(SO)
I/O2
(WP)
D7 D3 D7 D3 D7 D3 D7 D3 D7 D3
I/O3
(HOLD)
MSB
MSB
MSB
MSB
MSB
Figure 8-9. Quad Output Fast Read Sequence Diagram
8.2.5 Dual I/O Fast Read (BBh)
The Dual I/O Fast Read instruction is similar to the Dual Output Fast Read instruction but with the capability to
input the 3-byte address (A23 - 0) and a Continuous Read Mode byte 2-bits per clock by SI and SO, each bit being
latched in during the rising edge of SCK, then the memory contents are shifted out two bits per clock cycle on the
SI and SO pins. The first byte addressed can be at any location. The address automatically increments to the next
higher address after each byte of data is shifted out.
Dual I/O Fast Read with Continuous Read Mode
The Dual I/O Fast Read instruction can further reduce instruction overhead through setting the Continuous Read
Mode bits (M7 - 4) after the inputs 3-byte address A23 - A0).
If the Continuous Read Mode bits (M5:M4) do not equal (1,0), the next instruction requires the first BBh instruction
code, thus returning to normal operation. A Continuous Read Mode Reset instruction can be used to reset (M5:M4)
before issuing normal instruction. The instruction sequence is shown in the following Figure 8-10.
If the Continuous Read Mode bits (M5:M4) = (1, 0), then the next Dual I/O fast Read instruction (after CS is raised
and then lowered) does not require the BBh instruction code. The instruction sequence is shown in the following
Figure 8-11.
AT25QF128A
DS-AT25QF128A–176D–06-2020
23
CS
0
1
1
0
2
1
3
4
5
6
7
8
9
10 11 12
19 20 21 22 23 24 25 26 27
SCK
Address Bits
A23-A16
Address Bits
A15-A8 A7-A0
Opcode
M7-M0
M2 M0
Byte 1
D2 D0
Byte 2
I/O0
(SI)
1
1
0
1
1
A
22
A
20
A18
A
16
A14
A
A
0
M
6
M4
D
6
D
4
D
6
MSB
MSB
I/O1
(SO)
M3 M1
D3 D1
D
A
23
A
21
A19
A
17
A15
A
A1
M7
M5
D
7
D
5
7
MSB
Figure 8-10. Dual I/O Fast Read Sequence Diagram (Initial command or previous (M5:4) ≠ (1,0))
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
SCK
Address Bits
A23-A16
Address Bits
A7-A0
M7-M0
Byte 1
Byte 2
A15-A8
A
M2 M0
D2 D0
A
22
A
20
A
18
A
16
A
14
A
A
0
1
M
M
6
7
M
4
5
D
D
6
7
D
4
5
D
6
I/O0
(SI)
MSB
M3 M1
D3 D1
A
23
A
21
A19
A
17
A
15
A
M
D
D
7
I/O1
(SO)
MSB
Figure 8-11. Dual I/O Fast Read Sequence Diagram (Previous command set (M5:4) = (1,0))
8.2.6 Quad I/O Fast Read (EBh)
The Quad I/O Fast Read instruction is similar to the Dual I/O Fast Read instruction but with the capability to input
the 3-byte address (A23-0) and a Continuous Read Mode byte and four dummy clocks, each bit being latched in
during the rising edge of SCK, then the memory contents are shifted out 4-bit per clock cycle from IO0, IO1, IO2,
IO3. The first byte addressed can be at any location. The address automatically increments to the next higher
address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register must be set to enable
for the Quad I/O Fast read instruction.
Quad I/O Fast Read with Continuous Read Mode
The Quad I/O Fast Read instruction can further reduce instruction overhead through setting the Continuous Read
Mode bits (M7-0) after the input Address bits (A23-0).
If the Continuous Read Mode bits M5-4 do not equal to (1,0), the next instruction requires the first EBh instruction
code, thus returning to normal operation. A Continuous Read Mode Reset command can also be used to reset
AT25QF128A
DS-AT25QF128A–176D–06-2020
24
(M5-4) before issuing normal command. The instruction sequence is shown in the followed Figure 8-12.
If the Continuous Read Mode bits (M5-4) = (1,0), then the next Fast Read Quad I/O instruction (after CS is raised
and then lowered) does not require the EBh instruction code. The instruction sequence is shown in the followed
Figure 8-13.
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Opcode
A23-A16 A15-A8
A7-A0
M7-M0
Dummy
Byte 1
Byte 2
D0 D4
I/O
0
D
4
D
0
1
1
1
0
1
0
1
1
A
20
A
16
A
12
A8
A
4
A0 M4 M0
(SI)
MSB
D1 D5
D2 D6
D3 D7
I/O1
A
21
A
17
A
13
A
9
D
5
D
1
A
5
A1 M5 M1
(SO)
I/O2
(WP)
D
6
D2
A
22
A
18
A
14
A10
A
6
A2 M6 M2
I/O3
D
7
D3
A23
A19
A15
A
11
A
7
A3 M7 M3
(HOLD)
Figure 8-12. Quad I/O Fast Read Sequence Diagram (Initial command or previous (M5-4) ≠ (1,0))
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCK
A23-A16 A15-A8
A7-A0
M7-M0
Dummy
Byte 1
Byte 2
I/O
0
D0 D4
4
A
20
A
16
A
12
A
8
A
4
A
0
M
4
M
0
D
D
0
(SI)
D1 D5
D2 D6
D3 D7
I/O1
A
21
A
17
A
13
A
9
A
5
A
1
M
5
M
1
D
5
D
1
(SO)
I/O2
A
22
A
18
A
14
A
10
A
6
A
2
M
6
M
2
D
6
D2
(WP)
I/O3
A
23
A
19
A
15
A
11
A
7
A
3
M
7
M
3
D
7
D3
(HOLD)
Figure 8-13. Quad I/O Fast Read Sequence Diagram (Previous command set (M5-4) = (1,0))
Quad I/O Fast Read with 8/16/32/64-Byte Wrap Around
The Quad I/O Fast Read instruction can also be used to access a specific portion within a page by issuing a Set
Burst with Wrap (77h) instruction prior to EBh. The Set Burst with Wrap (77h) instruction can either enable or
disable the Wrap Around feature for the following EBh instructions.
When Wrap Around is enabled, the data being accessed can be limited to either an 8, 16, 32 or 64-byte section of
a 256-byte page. The output data starts at the initial address specified in the instruction, once it reaches the ending
boundary of the 8/16/32/64-byte section, the output wraps around to the beginning boundary automatically until CS
is pulled high to terminate the instruction.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the
cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read instructions.
The Set Burst with Wrap instruction allows three Wrap Bits, W6-4 to be set. The W4 bit is used to enable or disable
the Wrap Around operation while W6-5 are used to specify the length of the wrap around section within a page.
AT25QF128A
DS-AT25QF128A–176D–06-2020
25
8.2.7 Quad I/O Word Fast Read (E7h)
The Quad I/O Word Fast Read instruction is similar to the Quad Fast Read instruction, except that the lowest
address bit (A0) must be 0 and there are two dummy clocks. The address automatically increments to the next
higher address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set
to enable for the Quad I/O Word Fast Read instruction.
Quad I/O Word Fast Read with Continuous Read Mode
The Quad I/O Word Fast Read instruction can further reduce instruction overhead through setting the Continuous
Read Mode bits (M7-0) after the input three-byte Address bits (A23-0).
If the Continuous Read Mode bits M5-4 do not equal to (1,0), the next instruction requires the first E7h instruction
code, thus returning to normal operation. A Continuous Read Mode Reset command can also be used to reset
(M5-4) before issuing normal command. The instruction sequence is shown in the followed Figure 8-14.
If the Continuous Read Mode bits (M5-4) = (1, 0), then the next Quad I/O Fast Read instruction (after CS is raised
and then lowered) does not require the E7h instruction code, the instruction sequence is shown in the followed
Figure 8-15.
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Opcode
A23-A16 A15-A8
A7-A0
M7-M0 Dummy
Byte 3
Byte 1
Byte 2
D0 D4
D4
D
I/O0
1
1
1
0
0
1
1
1
A
20
A
16
A
12
A8
A
4
A
0
M
4
M0
D
4
D
0
0
(SI)
MSB
D1 D5
D2 D6
D3 D7
D5
D6
D7
I/O1
A
21
A
17
A
13
A
9
A
5
A
1
M
5
M
1
D
5
D
1
D1
(SO)
I/O2
D
6
D2
D
2
A
22
A
18
A
14
A10
A
6
A
2
M
6
M
2
(WP)
I/O3
D
7
D3
D
3
A23
A19
A15
A
11
A
7
A
3
M
7
M
3
(HOLD)
Figure 8-14. Quad I/O Word Fast Read Sequence Diagram (Initial command or previous (M5-4) ≠ (1,0))
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCK
A23-A16 A15-A8
A7-A0
M7-M0 Dummy
Byte 3
Byte 1
Byte 2
D4
0
I/O0
D0 D4
D
0
A20
A
16
A
12
A
8
A4
A
0
M
4
M
0
D
4
D
(SI)
D5
D6
D7
D1 D5
D2 D6
D3 D7
I/O1
A
21
A
17
A
13
A
9
A
5
A
1
M
5
M
1
D
5
D
1
D1
(SO)
I/O2
D
2
A
22
A18
A
14
A
10
A
6
A
2
M
6
M
2
D
6
D2
(WP)
I/O3
D
3
A
23
A
19
A
15
A
11
A
7
A
3
M
7
M
3
D
7
D3
(HOLD)
Figure 8-15. Quad I/O Word Fast Read Sequence Diagram (Previous command set (M5-4) = (1,0))
Quad I/O Word Fast Read with 8/16/32/64-Byte Wrap Around in Standard SPI Mode
The Quad I/O Fast Read instruction can also be used to access a specific portion within a page by issuing a Set
Burst with Wrap (77h) instruction prior to E7h. The Set Burst with Wrap (77h) instruction can either enable or
AT25QF128A
DS-AT25QF128A–176D–06-2020
26
disable the Wrap Around feature for the following E7h instructions. When Wrap Around is enabled, the data being
accessed can be limited to either an 8, 16, 32 or 64-byte section of a 256-byte page. The output data starts at the
initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64-byte section, the
output will wrap around to the beginning boundary automatically until CS is pulled high to terminate the instruction.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the
cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read instructions. The Set
Burst with Wrap instruction allows three Wrap Bits, W6-4 to be set. The W4 bit is used to enable or disable the
Wrap Around operation while W6-5 are used to specify the length of the wrap around section within a page.
8.2.8 Set Burst with Wrap (77h)
The Set Burst with Wrap instruction is used in conjunction with Quad I/O Fast Read and Quad I/O Word Fast Read
instruction to access a fixed length of 8/16/32/64-byte section within a 256-byte page in standard SPI mode. The
Set Burst with Wrap instruction sequence is as follows: CS goes low → Send Set Burst with Wrap instruction →
Send 24 Dummy bits → Send 8 Wrap bits → CS goes high.
If W6-4 is set by a Set Burst with Wrap instruction, all the following Fast Read Quad I/O and Word Read Quad I/O
instructions will use the W6-4 setting to access the 8/16/32/64-byte section within any page. To exit the Wrap
Around function and return to normal read operation, another Set Burst with Wrap instruction should be issued to
set W4 = 1. The default value of W4 upon power on is 1.
Table 8-2. Set Burst with Wrap
W4 = 0
W4 = 1 (Default)
W6, W5
Wrap Around
Wrap Length
8-byte
Wrap Around
Wrap Length
0
0
1
1
0
1
0
1
Yes
Yes
Yes
Yes
No
No
No
No
N/A
N/A
N/A
N/A
16-byte
32-byte
64-byte
CS
0
0
1
1
2
1
3
4
5
6
7
8
9
10 11 12 13 14 15 16
SCK
Opcode
Byte 1
Byte 2
Byte 3
Byte 4
HIGH-IMPEDANCE
HIGH-IMPEDANCE
HIGH-IMPEDANCE
HIGH-IMPEDANCE
I/O0
1
0
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
W
4
X
X
X
X
(SI)
MSB
HIGH-IMPEDANCE
HIGH-IMPEDANCE
HIGH-IMPEDANCE
I/O1
X
X
X
W5
(SO)
I/O2
W
6
(WP)
I/O3
X
(HOLD)
Figure 8-16. Set Burst with Wrap Sequence Diagram
AT25QF128A
DS-AT25QF128A–176D–06-2020
27
8.3
ID and Security Instructions
8.3.1 Read Manufacture ID/ Device ID (90h)
The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-Down/Device ID
instruction that provides both the JEDEC assigned Manufacturer ID and the specific Device ID.
The instruction is initiated by driving the CS pin low and shifting the instruction code 90h followed by a 24-bit
address (A23-A0) of 000000h. If the 24-bit address is initially set to 000001h, the Device ID will be read first.
CS
0
1
2
3
4
5
6
7
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
SI
ADDRESS BYTES
(000000000h)
OPCODE
1
MSB
0
0
1
0
0
0
0
A
A
A
A
A
MANUFACTURER ID
DEVICE ID
HIGH-IMPEDANCE
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
SO
MSB
MSB
Figure 8-17. Read Manufacture ID/ Device ID Sequence Diagram
8.3.2 Dual I/O Read Manufacture ID/ Device ID (92h)
The Dual I/O Read Manufacturer/Device ID instruction is an alternative to the Release from Power-Down/Device
ID instruction that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by Dual I/O.
The instruction is initiated by driving the CS pin low and shifting the instruction code 92h followed by a 24-bit
address (A23 - A0) of 000000h. If the 24-bit address is initially set to 000001h, the Device ID is read first.
CS
0
2
4
5
6
7
12
15
21
1
3
8
9
10 11
13 14
16 17 18 19 20
22 23
SCK
Instruction
92H
SI
4
2
0
6
4
2
3
0
1
6
0
6
2
2
0
4
4
5
6
(IO0)
HIGH-IMPEDANCE
SO
(IO1)
7
5
7
3
1
7
5
3
1
7
5
1
3
A23-16
A15-8
A7-0
Dummy
CS
23 24 25 26
28 29 30 31 32
39
42 43 44 45 46 47
27
40 41
SCK
SI
HIGH-IMPEDANCE
HIGH-IMPEDANCE
6
7
2
6
7
0
4
5
2
4
5
6
7
4
5
0
6
7
2
3
4
5
0
1
(IO0)
2
0
1
MFR and Device ID
(repeat)
SO
( IO1)
1
3
3
3
1
MFR ID (repeat)
Device ID (repeat)
MFR ID
Device ID
Figure 8-18. Dual I/O Read Manufacture ID/ Device ID Sequence Diagram
AT25QF128A
DS-AT25QF128A–176D–06-2020
28
8.3.3 Quad I/O Read Manufacture ID/ Device ID (94h)
The Quad I/O Read Manufacturer/Device ID instruction is an alternative to the Release from Power-Down/Device
ID instruction that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by quad I/O.
The instruction is initiated by driving the CS pin low and shifting the instruction code 94h followed by a 24-bit
address (A23 - A0) of 000000h and four dummy clocks. If the 24-bit address is initially set to 000001h, the Device
ID is read out first.
CS
0
2
4
5
6
7
12
15
21
0
1
3
9
11
13
16
20
8
10
4
14
17 18 19
22 23
SCLK
Instruction
94H
SI
( IO0)
4
5
0
1
4
4
0
0
4
0
4
0
HIGH-IMPEDANCE
HIGH-IMPEDANCE
SO
( IO1)
1
2
5
6
5
6
1
2
1
2
5
6
1
2
5
6
1
2
5
WP
( IO2)
6
2
6
HOLD
( IO3)
HIGH-IMPEDANCE
3
7
3
7
3
7
3
7
3
7
3
7
Device ID
MFR ID
dummy
A7-0
A23-16
dummy
A15-8
CS
23 24 25 26
28 29 30 31
27
SCLK
SI
( IO0)
4
0
4
0
4
0
4
0
SO
5
6
1
2
5
6
1
2
5
6
1
2
5
6
1
2
( IO1)
WP
( IO2)
7
3
7
3
7
3
7
3
HOLD
( IO3)
Device ID MFR ID Device ID
MFR ID
( repeat) ( repeat) ( repeat) ( repeat)
Figure 8-19. Quad I/O Read Manufacture ID / Device ID Sequence Diagram
8.3.4 Read JEDEC ID (9Fh)
The JEDEC ID instruction allows the 8-bit manufacturer identification to be read, followed by two bytes of device
identification. The device identification indicates the memory type in the first byte, and the memory capacity of the
device in the second byte. JEDEC ID instruction while an Erase or Program cycle is in progress, is not decoded,
and has no effect on the cycle that is in progress. The JEDEC ID instruction should not be issued while the device
is in Deep Power-Down Mode.
The device is first selected by driving CS to low. Then, the 8-bit instruction code for the instruction is shifted in. This
is followed by the 24-bit device identification, stored in the memory, being shifted out on Serial Data Output, each
bit being shifted out during the falling edge of Serial Clock. The JEDEC ID instruction is terminated by driving CS to
high at any time during data output. When CS is driven high, the device is put in the Standby Mode. Once in the
Standby Mode, the device waits to be selected, so that it can receive, decode and execute instructions.
AT25QF128A
DS-AT25QF128A–176D–06-2020
29
CS
SCK
SI
0
6
7
8
14 15 16
22 23 24
30 31 32
OPCODE
9Fh
HIGH-IMPEDANCE
1Fh
89h
01h
SO
MANUFACTURER ID
DEVICE ID
BYTE1
DEVICE ID
BYTE2
Note: Each transition
shown for SI and SO represents one byte (8 bits)
Figure 8-20. JEDEC ID Sequence Diagram
8.3.5 Read Unique ID Number (4Bh)
The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique to each
AT25QF128A device. The ID number can be used in conjunction with user software methods to help prevent
copying or cloning of a system. The Read Unique ID instruction is initiated by driving the CS pin low and shifting
the instruction code 4Bh followed by a four bytes of dummy clocks. After which, the 64-bit ID is shifted out on the
falling edge of SCK as shown in Figure 8-21.
CS
19
Mode
Mode
13 14 15
20 21 22
0
1
2
3
4
5
6
7
8
9
10 11
16 17 18
23
3
0
12
SCK
SI
Dummy Byte
Instruction
4BH
1
Dummy Byte
2
HIGH-IMPEDANCE
SO
CS
_
26
Dummy Byte 3
23
25
27 28
103
102
29 30
33
40
24
34
36 37 38 39
100 101
Mode3
Mode0
31 32
35
41
SCK
Dummy Byte
4
SI
HIGH-IMPEDANCE
_
SO
1
2
63 62
MSB
0
bit Unique
Serial Number
64-
Figure 8-21. Read Unique ID Sequence Diagram
AT25QF128A
DS-AT25QF128A–176D–06-2020
30
8.3.6 Deep Power-Down (B9h)
Although the standby current during normal operation is relatively low, standby current can be further reduced with
the Deep Power-down instruction. The lower power consumption makes the Deep Power-down (DPD) instruction
especially useful for battery powered applications (see ICC1 and ICC2). The instruction is initiated by driving the
CS pin low and shifting the instruction code B9h, as shown in Figure 8-22.
The CS pin must be driven high after the eighth bit has been latched. If this is not done the Deep Power down
instruction is not executed. After CS is driven high, the power-down state is entered within the time tDP. While in the
power-down state only the Release from Deep Power-down / Device ID instruction, which restores the device to
normal operation, will be recognized. All other Instructions are ignored. This includes the Read Status Register
instruction, which is always available during normal operation. Ignoring all but one instruction also makes the
Power Down state a useful condition for securing maximum write protection. The device always powers-up in the
normal operation with the standby current of ICC1.
CS
tPD
0
1
2
3
4
5
6
7
SCK
SI
OPCODE
1
MSB
0
1
1
1
0
0
1
HIGH-IMPEDANCE
Active Current
SO
ICC
Standby Mode Current
Deep Power-Down Mode Current
Figure 8-22. Deep Power-Down Sequence Diagram
8.3.7 Release from Deep Power-Down/Read Device ID (ABh)
The Release from Power-Down or Device ID instruction is a multi-purpose instruction. It can be used to release the
device from the Power-Down state or obtain the devices electronic identification (ID) number.
To release the device from the Power-Down state, the instruction is issued by driving the CS pin low, shifting the
instruction code ABh and driving CS high Release from Power-Down takes time tRES1 (see Section 9.8, AC
Electrical Characteristics) before the device resumes normal operation and other instruction are accepted. The CS
pin must remain high during tRES1
.
When used only to obtain the Device ID while not in the Power-Down state, the instruction is initiated by driving the
CS pin low and shifting the instruction code ABh followed by three dummy bytes. The Device ID bits are then
shifted out on the falling edge of SCK with most significant bit (MSB) first, as shown in Figure 8-23. The Device ID
value for the AT25QF128A is listed in Manufacturer and Device Identification table. The Device ID can be read
continuously. The instruction is completed by driving CS high.
When used to release the device from the Power-Down state and obtain the Device ID, the instruction is the same
as previously described, and shown in Figure 8-23, except that after CS is driven high it must remain high for a
time of tRES2 (see Section 9.8, AC Electrical Characteristics), as shown in Figure 8-24. After this time, the device
resumes normal operation and other instructions are accepted. If the Release from Power-Down/Device ID
instruction is issued while an Erase, Program or Write cycle is in process (when WIP equal 1) the instruction is
ignored and does not effect the current cycle.
AT25QF128A
DS-AT25QF128A–176D–06-2020
31
CS
SCK
SI
tRES1
0
1
2
3
4
5
6
7
OPCODE
1
MSB
0
1
0
1
0
1
1
HIGH-IMPEDANCE
SO
Stand-By
Mode
Deep Power-Down Mode
Figure 8-23. Release Power-Down Sequence Diagram
CS
SCK
SI
0
1
2
3
4
5
6
7
8
9
29 30 31 32 33 34 35 36 37 38 39
Instruction
3 Dummy Bytes
tRES2
1
MSB
0
1
0
1
0
1
1
23 22
2
1
0
MSB
Device ID
High_Z
#
#
#
#
#
#
#
#
SO
MSB
Deep Power-down Mode
Stand-by Mode
Figure 8-24. Release Power-Down and Read Device ID Sequence Diagram
8.3.8 Read Security Registers (48h)
The Read Security Registers instruction is similar to Fast Read instruction. The instruction is followed by a 3-byte
address (A23 - A0) and a dummy byte, each bit being latched-in during the rising edge of SCK. Then the memory
content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during the falling
edge of SCK. The first byte addressed can be at any location. The address automatically increments to the next
higher address after each byte of data is shifted out. Once the A7 - A0 address reaches the last byte of the register
(Byte FFh), it resets to 000h, the instruction is completed by driving CS high.
Table 8-3. Read Security Registers
Address
A23-A16
00h
A15-A12
0001
A11-A8
0000
A7-A0
Security Registers 1
Security Registers 2
Security Registers 3
Byte Address
Byte Address
Byte Address
00h
0010
0000
00h
0011
0000
AT25QF128A
DS-AT25QF128A–176D–06-2020
32
ꢁꢀ
ꢀꢁꢂ
ꢀꢃ
ꢊ
ꢉ
ꢇ
ꢈ
ꢎ
ꢍ
ꢋ
ꢌ
ꢐ
ꢏ
ꢉꢊ ꢉꢉ ꢉꢇ
ꢇꢏ ꢈꢊ ꢈꢉ ꢈꢇ ꢈꢈ ꢈꢎ ꢈꢍ ꢈꢋ ꢈꢌ ꢈꢐ ꢈꢏ
ꢄꢑꢁꢄꢒꢓ
ꢔꢒꢒꢖꢓꢀꢀꢗꢆꢃꢘꢀꢗꢔꢇꢈꢙꢔꢊ
ꢒꢚꢅꢅꢛꢗꢆꢛꢘꢓ
ꢊ
ꢉ
ꢊ
ꢊ
ꢉ
ꢊ
ꢊ
ꢊ
ꢔ
ꢔ
ꢔ
ꢔ
ꢔ
ꢔ
ꢔ
ꢔ
ꢔ
ꢕ
ꢕ
ꢕ
ꢕ
ꢕ
ꢕ
ꢕ
ꢕ
ꢅꢀꢆ
ꢅꢀꢆ
ꢅꢀꢆ
ꢒꢔꢘꢔꢗꢆꢛꢘꢓꢗꢉ
ꢜꢃꢝꢜꢙꢃꢅꢑꢓꢒꢔ ꢁꢓ
ꢒ
ꢒ
ꢒ
ꢒ
ꢒ
ꢒ
ꢒ
ꢒ
ꢒ
ꢒ
ꢀꢄ
ꢅꢀꢆ
ꢅꢀꢆ
Figure 8-25. Read Security Registers Instruction Sequence Diagram
8.3.9 Erase Security Registers (44h)
The AT25QF128A provides three 256-byte Security Registers which can be erased and programmed individually.
These registers may be used by the system manufacturers to store security and other important information
separately from the main memory array.
The Erase Security Registers instruction is similar to Sector/Block Erase instruction. A Write Enable instruction
must previously have been executed to set the Write Enable Latch bit.
The Erase Security Registers instruction sequence: CS goes low → sending Erase Security Registers instruction
→ CS goes high. CS must be driven high after the eighth bit of the instruction code has been latched in otherwise
the Erase Security Registers instruction is not executed. As soon as CS is driven high, the self-timed Erase
Security Registers cycle (whose duration is tSE) is initiated. While the Erase Security Registers cycle is in progress,
the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP)
bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is completed. At some unspecified
time before the cycle is completed, the Write Enable Latch bit is reset. The Security Registers Lock Bit (LB) in the
Status Register can be used to OTP protect the security registers. Once the LB bit is set to 1, the Security
Registers are permanently locked; the Erase Security Registers instruction is ignored.
Table 8-4. Erase Security Registers
Address
A23 - A16
00h
A15 - A12
0001
A11 - A8
0000
A7 - A0
Security Registers 1
Security Registers 2
Security Registers 3
Byte Address
Byte Address
Byte Address
00h
0010
0000
00h
0011
0000
CS
0
1
2
3
4
5
6
7
8
9
29 30 31
SCK
SI
OPCODE
24-BIT ADDRESS
0
MSB
1
0
0
0
1
0
0
A
A
A
A
A
Figure 8-26. Erase Security Registers Instruction Sequence Diagram
AT25QF128A
DS-AT25QF128A–176D–06-2020
33
8.3.10 Program Security Registers (42h)
The Program Security Registers instruction is similar to the Page Program instruction. It allows from 1 to 256 bytes
Security Registers data to be programmed. A Write Enable instruction must previously have been executed to set
the Write Enable Latch (WEL) bit before sending the Program Security Registers instruction.
The Program Security Registers instruction is entered by driving CS low, followed by the instruction code (42h), a
3-byte address and at least one data byte on the SI pin. As soon as CS is driven high, the self-timed Program
Security Registers cycle (whose duration is tPP) is initiated. While the Program Security Registers cycle is in
progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In
Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the WEL bit is reset.
If the Security Registers Lock Bit (LB3/LB2/LB1) bits are set to 1, the Security Registers are permanently locked.
The Program Security Registers instruction is ignored.
Table 8-5. Program Security Registers
Address
A23 - A16
00h
A15 - A12
0001
A11 - A8
0000
A7 - A0
Security Registers 1
Security Registers 2
Security Registers 3
Byte Address
Byte Address
Byte Address
00h
0010
0000
00h
0011
0000
CS
SCK
SI
0
1
2
3
4
5
6
7
8
9
29 30 31 32 33 34 35 36 37 38 39
OPCODE
ADDRESS BITS A23-A0
DATA IN BYTE 1
DATA IN BYTE n
0
MSB
1
0
0
0
0
1
0
A
MSB
A
A
A
A
A
D
D
D
D
D
D
D
D
D
MSB
D
D
D
D
D
D
D
MSB
HIGH-IMPEDANCE
SO
Figure 8-27. Program Security Registers Instruction Sequence Diagram
8.3.11 Enable Reset (66h) and Reset Device (99h)
Because of the small package and the limitation on the number of pins, the AT25QF128A provides a software
Reset instruction instead of a dedicated RESET pin. Once the software Reset instruction is accepted, any on-going
internal operations are terminated and the device returns to its default power-on state and loses all of the current
volatile settings, such as Volatile Status Register bits, Write Enable Latch (WEL) status, Program/Erase Suspend
status, Continuous Read Mode bit setting (M7-M0) and Wrap Bit setting (W6-W4).
To avoid accidental reset, both Enable Reset (66h) and Reset (99h) instructions must be issued in sequence. Any
other commands other than Reset (99h) after the Enable Reset (66h) command will disable the Reset Enable
state. A new sequence of Enable Reset (66h) and Reset (99h) is needed to reset the device. Once the Reset
command is accepted by the device, the device takes approximately 30 μs to reset. During this period, no
commands are accepted.
The Enable Reset (66h) and Reset (99h) instruction sequence is shown in Figure 8-28.
AT25QF128A
DS-AT25QF128A–176D–06-2020
34
Data corruption may happen if there is an on-going or suspended internal Erase or Program operation when Reset
command sequence is accepted by the device. It is recommended to check the BUSY bit and the SUS bit in Status
Register before issuing the Reset command sequence.
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
SI
OPCODE
OPCODE
1
0
1
1
0
0
1
0
0
1
1
0
0
1
1
0
Figure 8-28. Enable Reset (66h) and Reset (99h) Command Sequence
8.4
Program and Erase Instructions
8.4.1 Page Program (02h)
The Page Program instruction is for programming the memory. A Write Enable instruction must previously have
been executed to set the Write Enable Latch bit before sending the Page Program instruction.
The Page Program instruction is entered by driving CS Low, followed by the instruction code, 3-byte address and
at least one data byte on SI. If the 8 least significant address bits (A7 - A0) are not all zero, all transmitted data that
goes beyond the end of the current page are programmed from the start address of the same page (from the
address whose 8 least significant bits (A7 - A0) are all zero). CS must be driven low for the entire duration of the
sequence. The Page Program instruction sequence: CS goes low → sending Page Program instruction → 3-byte
address on SI → at least 1 byte of data on SI → CS goes high.
If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are
guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they
are correctly programmed at the requested addresses without having any effects on the other bytes of the same
page. CS must be driven high after the eighth bit of the last data byte has been latched in; otherwise the Page
Program instruction is not executed.
As soon as CS is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page
Program cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP)
bit. The Write in Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Page Program instruction applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0)
bits is not executed.
CS
0
1
2
3
4
5
6
7
8
9
29 30 31 32 33 34 35 36 37 38 39
SCK
SI
OPCODE
ADDRESS BITS A23-A0
DATA IN BYTE 1
DATA IN BYTE n
0
MSB
0
0
0
0
0
1
0
A
A
A
A
A
A
D
MSB
D
D
D
D
D
D
D
D
MSB
D
D
D
D
D
D
D
MSB
HIGH-IMPEDANCE
SO
Figure 8-29. Page Program Sequence Diagram
AT25QF128A
DS-AT25QF128A–176D–06-2020
35
8.4.2 SCKQuad Page Program (32h)
The Quad Page Program instruction is for programming the memory using for pins: IO0, IO1, IO2 and IO3. To use
Quad Page Program the Quad Enable (QE) bit in the Status register must be set (QE = 1). A Write Enable
instruction must previously have been executed to set the Write Enable Latch bit before sending the Page Program
instruction. The Quad Page Program instruction is entered by driving CS low, followed by the command code
(32h), three address bytes and at least one data byte on IO pins.
The instruction sequence is shown in Figure 8-30. If more than 256 bytes are sent to the device, previously latched
data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page.
If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without
having any effects on the other bytes of the same page. CS must be driven high after the eighth bit of the last data
byte has been latched in; otherwise the Quad Page Program instruction is not executed.
As soon as CS is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is initiated. While
the Quad Page Program cycle is in progress, the Status Register may be read to check the value of the Write in
Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Quad Page Program cycle, and is 0
when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch bit is reset.A
Quad Page Program instruction applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1,
BP0) bits is not executed.
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35 36 37 38 39 40 41
DATA DATA DATA DATA DATA
SCK
IN 1
IN 2
IN 3
IN 4
IN 5
COMMAND
Address Bits A23-A0
0
1
1
0
D4 D0 D4 D0 D4 D0 D4 D0 D4 D0
D5 D1 D5 D1 D5 D1 D5 D1 D5 D1
D6 D2 D6 D2 D6 D2 D6 D2 D6 D2
0
MSB
0
0
1
A
MSB
A
A
A
A
A
A
A
A
I/O0
(SI)
HIGH-IMPEDANCE
HIGH-IMPEDANCE
HIGH-IMPEDANCE
I/O1
(SO)
I/O2
(WP)
D7 D3 D7 D3 D7 D3 D7 D3 D7 D3
I/O3
(HOLD)
MSB
MSB
MSB
MSB
MSB
Figure 8-30. Quad Page Program Sequence Diagram
8.4.3 Fast Page Program (F2h)
The Fast Page Program instruction is used to program the memory. A Write Enable instruction must previously
have been executed to set the WEL bit before sending the Page Program instruction.
The Fast Page Program instruction is entered by driving CS Low, followed by the instruction code, 3-byte address
and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data
that goes beyond the end of the current page are programmed from the start address of the same page (from the
address whose 8 least significant bits (A7-A0) are all zero). CS must be driven low for the entire duration of the
sequence.
The Fast Page Program instruction sequence: CS goes low → sending Page Program instruction → 3-byte
address on SI → at least 1 byte data on SI → CS goes high.
AT25QF128A
DS-AT25QF128A–176D–06-2020
36
The command sequence is shown in Figure 8-31. If more than 256 bytes are sent to the device, previously latched
data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page.
If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without
having any effects on the other bytes of the same page. CS must be driven high after the eighth bit of the last data
byte has been latched in; otherwise the Fast Page Program instruction is not executed.
As soon as CS is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page
Program cycle is in progress, the Status Register may be read to check the value of the Write-in-Progress (WIP)
bit. The WIP bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified
time before the cycle is completed, the WEL bit is reset.
A Fast Page Program instruction applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1,
BP0) bits is not executed.
ꢁꢀ
ꢊ
ꢉ
ꢇ
ꢈ
ꢎ
ꢍ
ꢋ
ꢌ
ꢐ
ꢏ
ꢇꢏ ꢈꢊ ꢈꢉ ꢈꢇ ꢈꢈ ꢈꢎ ꢈꢍ ꢈꢋ ꢈꢌ ꢈꢐ ꢈꢏ
ꢀꢁꢂ
ꢀꢃ
ꢄꢑꢁꢄꢒꢓ
ꢔꢒꢒꢖꢓꢀꢀꢗꢆꢃꢘꢀꢗꢔꢇꢈꢙꢔꢊ
ꢒꢔꢘꢔꢗꢃ ꢗꢆꢛꢘꢓꢗꢉ
ꢒꢔꢘꢔꢗꢃ ꢗꢆꢛꢘꢓꢗ!
ꢉ
ꢉ
ꢉ
ꢉ
ꢊ
ꢊ
ꢉ
ꢊ
ꢔ
ꢔ
ꢔ
ꢔ
ꢔ
ꢔ
ꢒ
ꢒ
ꢒ
ꢒ
ꢒ
ꢒ
ꢒ
ꢒ
ꢒ
ꢒ
ꢒ
ꢒ
ꢒ
ꢒ
ꢒ
ꢒ
ꢅꢀꢆ
ꢅꢀꢆ
ꢅꢀꢆ
ꢅꢀꢆ
ꢜꢃꢝꢜꢙꢃꢅꢑꢓꢒꢔ ꢁꢓ
ꢀꢄ
Figure 8-31. Fast Page Program Sequence Diagram
8.4.4 Sector Erase (20h)
The Sector Erase instruction is for erasing the all data of the chosen sector. A Write Enable instruction must
previously have been executed to set the Write Enable Latch bit. The Sector Erase instruction is entered by driving
CS low, followed by the instruction code, and 3-address byte on SI. Any address inside the sector is a valid
address for the Sector Erase instruction. CS must be driven low for the entire duration of the sequence.
The Sector Erase instruction sequence: CS goes low → sending Sector Erase instruction → 3-byte address on SI
→ CS goes high. CS must be driven high after the eighth bit of the last address byte has been latched in; otherwise
the Sector Erase instruction is not executed. As soon as CS is driven high, the self-timed Sector Erase cycle
(whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to
check the value of the Write-in-Progress (WIP) bit. The WIP bit is 1 during the self-timed Sector Erase cycle, and is
0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit
is reset. A Sector Erase instruction applied to a sector which is protected by the Block Protect (BP4, BP3, BP2,
BP1, BP0) bits is not executed.
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
26 27 28 29 30 31
SCK
SI
OPCODE
ADDRESS BITS A23-A0
A
A
A
A
A
MSB
A
A
A
A A
A
A
C
MSB
C
C
C
C
C
C
C
HIGH-IMPEDANCE
SO
Figure 8-32. Sector Erase Sequence Diagram
AT25QF128A
DS-AT25QF128A–176D–06-2020
37
8.4.5 32KB Block Erase (52h)
The 32 KB Block Erase instruction is for erasing all data of a chosen block. A Write Enable instruction must have
been previously executed to set the WEL bit. The 32 kB Block Erase instruction is entered by driving CS low,
followed by the instruction code, and 3-byte address on SI. Any address inside the block is a valid address for the
32 KB Block Erase instruction. CS must be driven low for the entire duration of the sequence.
The 32 KB Block Erase instruction sequence: CS goes low → sending 32 kB Block Erase instruction → 3-byte
address on SI → CS goes high. CS must be driven high after the eighth bit of the last address byte has been
latched in; otherwise the 32 kB Block Erase instruction is not executed.
As soon as CS is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block
Erase cycle is in progress, the Status Register may be read to check the value of the Write-in-Progress (WIP) bit.
The WIP bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time
before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A 32 kB Block Erase instruction applied to
a block which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) bits is not executed.
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
26 27 28 29 30 31
SCK
SI
OPCODE
ADDRESS BITS A23-A0
A
A
A
A
A
MSB
A
A
A
A A
A
A
C
MSB
C
C
C
C
C
C
C
HIGH-IMPEDANCE
SO
Figure 8-33. 32 kB Block Erase Sequence Diagram
8.4.6 64KB Block Erase (D8h)
The 64 KB Block Erase instruction is for erasing the all data of the chosen block. A Write Enable instruction must
previously have been executed to set the WEL bit. The 64 KB Block Erase instruction is entered by driving CS low,
followed by the instruction code, and 3-byte address on SI. Any address inside the block is a valid address for the
64 KB Block Erase instruction. CS must be driven low for the entire duration of the sequence.
The 64 KB Block Erase instruction sequence: CS goes low sending 64 KB Block Erase instruction 3-byte address
on SI CS goes high. CS must be driven high after the eighth bit of the last address byte has been latched in;
otherwise the 64 KB Block Erase instruction is not executed. As soon as CS is driven high, the self-timed Block
Erase cycle (whose duration is tBE) is initiated.
While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write-in-
Progress (WIP) bit. The WIP bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some
unspecified time before the cycle is completed, the WEL bit is reset. A 64 KB Block Erase instruction applied to a
block which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) bits is not executed.
AT25QF128A
DS-AT25QF128A–176D–06-2020
38
CS
SCK
SI
0
1
2
3
4
5
6
7
8
9
10 11 12
26 27 28 29 30 31
OPCODE
ADDRESS BITS A23-A0
A
A
A
A
A
A
A
A
MSB
A A
A
A
C
MSB
C
C
C
C
C
C
C
HIGH-IMPEDANCE
SO
Figure 8-34. 64 kB Block Erase Sequence Diagram
8.4.7 Chip Erase (60/C7h)
The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write Enable
instruction must be executed before the device accepts the Chip Erase Instruction (Status Register bit WEL must
equal 1). The instruction is initiated by driving the CS pin low and shifting the instruction code C7h or 60h. The Chip
Erase instruction sequence is shown in Figure 8-35.
The CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase instruction
is not executed. After CS is driven high, the self-timed Chip Erase instruction commences for a time of tCE. While
the Chip Erase cycle is in progress, the Read Status Register instruction may still be accessed to check the status
of the WIP bit.
The WIP bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is ready to accept
other Instructions again. After the Chip Erase cycle has finished the WEL bit in the Status Register is cleared to 0.
The Chip Erase instruction is executed only if all Block Protect (BP2, BP1, and BP0) bits are 0. The Chip Erase
instruction is ignored if one or more sectors are protected.
CS
0
1
2
3
4
5
6
7
SCK
SI
OPCODE
C
MSB
C
C
C
C
C
C
C
HIGH-IMPEDANCE
SO
Figure 8-35. Chip Erase Sequence Diagram
8.4.8 Erase / Program Suspend (75h)
The Erase/Program Suspend instruction allows the system to interrupt a Sector or Block Erase operation, then
read from or program data to any other sector. The Erase/Program Suspend instruction also allows the system to
interrupt a Page Program operation and then read from any other page or erase any other sector or block. The
Erase/Program Suspend instruction sequence is shown in Figure 8-36.
The Write Status Registers instruction (01h) and Erase instructions (20h, D8h, C7h, 60h, 44h) are not allowed
during Erase Suspend. Erase Suspend is valid only during the Sector or Block erase operation. If written during the
Chip Erase operation, the Erase Suspend instruction is ignored. The Write Status Registers instruction (01h), and
AT25QF128A
DS-AT25QF128A–176D–06-2020
39
SCKProgram instructions (02h, 42h) are not allowed during Program Suspend. Program Suspend is valid only
during the Page Program operation.
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
SI
OPCODE
tSUS
0
1
1
1
0
1
0
1
Instruction During Supend
MSB
HIGH-IMPEDANCE
SO
Figure 8-36. Erase/Program Suspend Command Sequence
Note: Repeated suspend/resume sequences might significantly impact progress of the erase or program
operation. In order to ensure timely completion of the erase or program operation, it is recommended to limit the
number of suspend/resume sequences during the same erase or program operation or, alternatively, provide
sufficient time (up to 60 ms) after a resume operation to allow the erase or program operation to complete.
8.4.9 Erase / Program Resume (7Ah)
The Erase/Program Resume instruction 7Ah must be written to resume the Sector or Block Erase operation or the
Page Program operation after an Erase/Program Suspend. The Resume instruction 7Ah is accepted by the device
only if the SUS bit in the Status Register equals to 1 and the WIP bit equals to 0.
After the Resume instruction is issued the SUS bit is cleared from 1 to 0 immediately, the WIP bit is set from 0 to 1
within 200 ns and the Sector or Block completes the erase operation or the page completes the program operation.
If the SUS bit equals to 0 or the WIP bit equals to 1, the Resume instruction 7Ah is ignored by the device. The
Erase/Program Resume instruction sequence is shown in Figure 8-37.
ꢁꢀ
ꢊ
ꢉ
ꢇ
ꢈ
ꢎ
ꢍ
ꢋ
ꢌ
ꢀꢁꢂ
ꢀꢃ
ꢄꢑꢁꢄꢒꢓ
0
ꢅꢀꢆ
1
ꢉ
ꢉ
1
0
1
0
ꢜꢃꢝꢜꢙꢃꢅꢑꢓꢒꢔ ꢁꢓ
ꢀꢄ
Figure 8-37. Erase/Program Resume Command Sequence
AT25QF128A
DS-AT25QF128A–176D–06-2020
40
8.4.10 Read Serial Flash Discoverable Parameter (5Ah)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the
functional and feature capabilities of serial Flash devices in a standard set of internal parameter tables. These
parameter tables can be interrogated by host system software to enable adjustments needed to accommodate
divergent features from multiple vendors. For more detail on the SFDP parameters, please contact Adesto.
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
SCK
DS
SI
Opcode
Address Bits A23-A0
8 Dummy Cycles
0
MSB
1
0
1
1
0
1
0
A
MSB
A
A
A
A
A
A
A
X
X
X
X
X
X
X
X
Output Data Byte 1
D
MSB
D
D
D
D
D
D
D
LSB
SO
Figure 8-38. Read Serial Flash Discoverable Parameter Command Sequence Diagram
AT25QF128A
DS-AT25QF128A–176D–06-2020
41
9.
Electrical Characteristics
9.1
Absolute Maximum Ratings
Table 9-1. Absolute Maximum Ratings
Parameter
Symbol
VCC
Conditions
Range
-0.5 to 4
-0.5 to 4
Units
Supply Voltage
V
V
Voltage Applied to Any Pin
VIO
Relative to Ground
<20nS Transient Relative to
Ground
Transient Voltage on any Pin
VIOT
-2.0 to VCC + 2.0
V
Storage Temperature
TSTG
VESD
-65 to +150
oC
V
Electrostatic Discharge Voltage
Human Body Model(1)
-2000 to +2000
Notes:
1. JEDEC Std JESD22-A114 (C1 = 100 pF, R1 = 1500Ω, R2 = 500Ω)
9.2
Operating Ranges
Table 9-2. Operating Range
Parameter
Symbol
Conditions
Min
2.7
-40
-40
Max
3.6
Unit
Supply Voltage
VCC
V
Industrial
Extended
+85
+105
oC
oC
Operating Temperature
TA
9.3
Data Retention and Endurance
Table 9-3. Data Retention and Endurance
Parameter
Condition
Max Temperature
85 oC
Min
Max
Units
Cycles
Cycles
Years
Years
100,000
10,000
20
4 KB sector, 32/64
KB block, or full chip
Erase/Program Cycles
105 oC
85 oC
Full temperature
range
Data Retention
105 oC
10
AT25QF128A
DS-AT25QF128A–176D–06-2020
42
9.4
Latch Up Characteristics
Table 9-4. Latch-up Characteristics
Parameter
Min
-1.0V
Max
Input Voltage Respect To GND on I/O Pins
VCC Current
VCC + 1.0V
100 mA
-100 mA
9.5
Power-up Timing
Table 9-5. Power-up Timing
Symbol
Parameter
VCC (min) To CS low
Min
Max
Unit
us
tVSL
300
VCC-MAX
Chip Selection is not allowed
VCC-MIN
tVSL
Device is fully
accessible
TIME
Figure 9-1. Power-up Timing and Voltage Levels
AT25QF128A
DS-AT25QF128A–176D–06-2020
43
9.6
DC Electrical Characteristics
Table 9-6 shows the DC electrical characteristics at 85 oC,
Table 9-6. DC Electrical Characteristics — 85 oC
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
ILI
Input Leakage Current
±2
μA
Output Leakage
Current
ILO
±2
25
5
μA
μA
μA
ICC1
ICC2
Standby Current
CS = VCC, VIN = VCC or GND
CS = VCC, VIN = VCC or GND
13
2
Deep Power-Down
Current
SCK = 0.1VCC/0.9VCC, at 120 MHz,
Q = Open (*1,*,2*4 I/O)
12
10
15
18
16
20
5
mA
mA
mA
mA
mA
mA
mA
Operating Current:
(Read)
ICC3
SCK = 0.1VCC/0.9VCC, at 80MHz,Q
= Open (*1,*,2*4 I/O)
Operating Current
(Page Program)
ICC4
ICC5
ICC6
ICC7
ICC8
CS = VCC
CS = VCC
CS = VCC
CS = VCC
CS = VCC
Operating Current
(WRSR)
Operating Current
(Sector Erase)
9
9
9
20
20
20
Operating Current
(Block Erase)
Operating Current
(Chip Erase)
VIL
VIH
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
-0.5
0.2VCC
VCC+0.4
0.4
V
V
V
V
0.8 VCC
VOL
VOH
IOL = 100 μA
IOH = -100 μA
VCC-0.2
AT25QF128A
DS-AT25QF128A–176D–06-2020
44
Table 9-7 shows the DC electrical characteristics at 105 oC.
Table 9-7. DC Electrical Characteristics — 105 oC
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
ILI
Input Leakage Current
±2
μA
Output Leakage
Current
ILO
±2
30
8
μA
μA
μA
ICC1
ICC2
Standby Current
CS = VCC, VIN = VCC or GND
CS = VCC, VIN = VCC or GND
20
5
Deep Power-Down
Current
SCK = 0.1VCC/0.9VCC, at 120
MHz,Q = Open (*1,*,2*4 I/O)
12
10
15
18
16
20
5
mA
mA
mA
mA
mA
mA
mA
Operating Current:
(Read)
ICC3
SCK = 0.1VCC/0.9VCC, at
80MHz,Q = Open(*1,*,2*4 I/O)
Operating Current
(Page Program)
ICC4
ICC5
ICC6
ICC7
ICC8
CS = VCC
CS = VCC
CS = VCC
CS = VCC
CS = VCC
Operating Current
(WRSR)
Operating Current
(Sector Erase)
9
9
9
20
20
20
Operating Current
(Block Erase)
Operating Current
(Chip Erase)
VIL
VIH
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
-0.5
0.2VCC
VCC+0.4
0.4
V
V
V
V
0.8VCC
VOL
VOH
IOL = 100 μA
IOH = -100 μA
VCC-0.2
AT25QF128A
DS-AT25QF128A–176D–06-2020
45
9.7
AC Measurement Conditions
Table 9-8. AC Measurement Conditions
Symbol
CL
Parameter
Min
Typ
Max
30
5
Unit
pF
ns
V
Conditions
Load Capacitance
tR, tF
VIN
Input Rise and Fall time
Input Pause Voltage
0.2VCC to 0.8VCC
0.5VCC
IN
Input Timing Reference Voltage
Output Timing Reference Voltage
V
OUT
0.5VCC
V
Input Timing
Input Levels Reference Levels
Output Timing
Reference Levels
0.8 VCC
0.2 VCC
0.5 VCC
0.5 VCC
Figure 9-2. AC Measurement I/O Waveform
9.8
AC Electrical Characteristics
Table 9-9 shows the AC electrical characteristics at 85 oC. .
Table 9-9. AC Electrical Characteristics — 85 oC
Symbol
Fc1
Parameter
Min
DC
DC
DC
Typ
Max
133
70
Units
Clock frequency for Quad Output Fast Read (6Bh) on 3.0V - 3.6V
power supply.
MHz
MHz
MHz
Fc2
Clock frequency for Read Data (03h) on 2.7V - 3.6V power supply.
Clock frequency except for Quad Output Fast Read (6Bh) or Read
Data (03h) on 3.0V - 3.6V power supply.
Fc3
120
Clock frequency except for Read Data (03h) on 2.7V - 3.6V power
supply.
Fc4
DC
108
MHz
tCLH
tCLL
Serial Clock High Time
3.75
3.75
0.1(1)
0.1(1)
5
ns
ns
Serial Clock Low Time
tCLCH
tCHCL
tSLCH
tCHSH
tSHCH
tCHSL
tSHSL
Serial Clock Rise Time (Slew Rate)
Serial Clock Fall Time (Slew Rate)
CS Active Setup Time
V/ns
V/ns
ns
CS Active Hold Time
5
ns
CS Not Active Setup Time
CS Not Active Hold Time
CS High Time (read/write)
5
ns
5
ns
20
ns
AT25QF128A
DS-AT25QF128A–176D–06-2020
46
Table 9-9. AC Electrical Characteristics — 85 oC (continued)
Parameter
Symbol
tSHQZ
tCLQX
tDVCH
tCHDX
tHLCH
tHHCH
tCHHL
tCHHH
tHLQZ
tHHQX
tCLQV
tWHSL
tSHWL
tDP
Min
Typ
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
Output Disable Time
Output Hold Time
Data In Setup Time
Data In Hold Time
6
0
2
2
5
5
5
5
HOLD Low Setup Time (relative to Clock)
HOLD High Setup Time (relative to Clock)
HOLD High Hold Time (relative to Clock)
HOLD Low Hold Time (relative to Clock)
HOLD Low To High-Z Output
6
6
7
HOLD Low To Low-Z Output
Clock Low To Output Valid
Write Protect Setup Time Before CS Low
Write Protect Hold Time After CS High
CS High To Deep Power-Down Mode
CS High To Standby Mode Without Electronic Signature Read
CS High To Standby Mode With Electronic Signature Read
CS High To Next Instruction After Suspend
CS High To Next Instruction After Reset (from read)
CS High To Next Instruction After Reset (from program)
CS High To Next Instruction After Reset (from erase)
Write Status Register Cycle Time
20
100
20
20
tRES1
tRES2
tSUS
20
20
tRST_R
tRST_P
tRST_E
tW
20
20
12
5
30
ms
µs
tBP1
Byte Program Time (First Byte)
30
2.5
0.6
70
50(2)
12(2)
2.4
300
tBP2
Additional Byte Program Time (After First Byte)
Page Programming Time
µs
tPP
ms
ms
tSE
Sector Erase Time
0.15/
0.25
tBE
tCE
Block Erase Time (32K Bytes/64K Bytes)
Chip Erase Time
1.6/2.0
120
sec
sec
30
Notes:
1. Tested with clock frequency lower than 50 MHz.
2. For multiple bytes after first byte within a page, tBPn = tBP1 + tBP2 * N, where N is the number of bytes
programmed.
AT25QF128A
DS-AT25QF128A–176D–06-2020
47
Table 9-10 shows the AC electrical characteristics at 105 oC.
Table 9-10. AC Electrical Characteristics — 105 oC
Symbol
Fc1
Parameter
Min
DC
DC
DC
Typ
Max
120
70
Units
MHz
MHz
Mhz
Clock frequency for Quad Output Fast Read (6Bh) on 3.0V - 3.6V
power supply.
Fc2
Clock frequency for Read Data (03h) on 2.7V - 3.6V power supply.
Clock frequency except for Quad Output Fast Read (6Bh) or Read
Data (03h) on 3.0V - 3.6V power supply.
Fc3
120
Clock frequency except for Read Data (03h) on 2.7V - 3.6V power
supply.
Fc4
DC
108
MHz
tCLH
tCLL
Serial Clock High Time
4
4
ns
ns
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
Serial Clock Low Time
tCLCH
tCHCL
tSLCH
tCHSH
tSHCH
tCHSL
tSHSL
tSHQZ
tCLQX
tDVCH
tCHDX
tHLCH
tHHCH
tCHHL
tCHHH
tHLQZ
tHHQX
tCLQV
tWHSL
tSHWL
tDP
Serial Clock Rise Time (Slew Rate)
Serial Clock Fall Time (Slew Rate)
CS Active Setup Time
0.1(1)
0.1(1)
5
CS Active Hold Time
5
CS Not Active Setup Time
5
CS Not Active Hold Time
5
CS High Time (read/write)
20
Output Disable Time
6
Output Hold Time
0
2
2
5
5
5
5
Data In Setup Time
Data In Hold Time
HOLD Low Setup Time (relative to Clock)
HOLD High Setup Time (relative to Clock)
HOLD High Hold Time (relative to Clock)
HOLD Low Hold Time (relative to Clock)
HOLD Low To High-Z Output
6
6
7
HOLD Low To Low-Z Output
Clock Low To Output Valid
Write Protect Setup Time Before CS Low
Write Protect Hold Time After CS High
CS High To Deep Power-Down Mode
CS High To Standby Mode Without Electronic Signature Read
CS High To Standby Mode With Electronic Signature Read
CS High To Next Instruction After Suspend
20
100
20
20
20
20
tRES1
tRES2
tSUS
AT25QF128A
DS-AT25QF128A–176D–06-2020
48
Table 9-10. AC Electrical Characteristics — 105 oC (continued)
Symbol
tRST_R
tRST_P
tRST_E
tW
Parameter
CS High To Next Instruction After Reset (from read)
CS High To Next Instruction After Reset (from program)
CS High To Next Instruction After Reset (from erase)
Write Status Register Cycle Time
Min
Typ
Max
20
Units
20
12
5
30
ms
µs
tBP1
Byte Program Time (First Byte)
30
2.5
0.6
70
50(2)
12(2)
2.4
300
tBP2
Additional Byte Program Time (After First Byte)
Page Programming Time
µs
tPP
ms
ms
tSE
Sector Erase Time
0.15/
0.25
tBE
tCE
Block Erase Time (32K Bytes/64K Bytes)
Chip Erase Time
1.6/2.0
120
sec
sec
60
Notes:
1. Tested with clock frequency lower than 50 MHz.
2. For multiple bytes after first byte within a page, tBPn = tBP1 + tBP2 * N, where N is the number of bytes
programmed.
tSHSL
CS
tSHCH
tCHSL
tCHSH
tSLCH
SCK
SI
tCHCL
tDVCH
tCLCH
tCHDX
MSB
LSB
High_Z
SO
Figure 9-3. Serial Input Timing
AT25QF128A
DS-AT25QF128A–176D–06-2020
49
CS
SCK
SO
tSHQZ
tCH
tCL
tCLQV
tCLQX
tCLQV
tQLQH
tQHQL
LSB
tCLQX
SI
Figure 9-4. Output Timing
CS
SCK
tHLCH
tCHHL
tHHCH
tCHHH
tHLQZ
tHHQX
SO
HOLD
Figure 9-5. HOLD Timing
CS
tSHWL
tWHSL
WP
CLK
IO
Input
Write Status Register is Allowed
Write Status Register is not Allowed
Figure 9-6. WP Timing
AT25QF128A
DS-AT25QF128A–176D–06-2020
50
10. Ordering Information
AT 25QF 128 A - S H B HD - T
Shipping Carrier
T = Tape and Reel
Designator
Extended Temperature
(not marked on the package)
HD = -40 oC to 105 oC
Product Family
Operating Voltage
B = 2.7V - 3.6V
Device Density
128 = 128 Mbit
Device Grade
H = Green NiPdAu lead frame
Generation
U = Green, matte Sn or Sn alloy
Package Options
S = 8-lead, SOP 208 mil
M = 8-pad 5 x 6 UDFN
Operating
Voltage
Maximum
Ordering Code
AT25QF128A-SHB-T
AT25QF128A-MHB-T
AT25QF128A-SHBHD-T
Package Type
8S2
Lead Finish
Frequency
133 MHz (1)
108 MHz
Operating Range
-40 oC to 85 oC
-40 oC to 105 oC
8MA1
NiPdAu
2.7 - 3.6V
8S2
1. Only for Quad Output Fast Read (6Bh) command with 3.0V - 3.6V power supply.
Package Type
8-lead, 0.208" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)
8S2
8MA1
8-pad (5 x 6 x 0.6 mm body), Thermally Enhanced Plastic Ultra-Thin Dual Flat No-lead (UDFN)
AT25QF128A
DS-AT25QF128A–176D–06-2020
51
11. Package Information
11.1 Package 8-Pin SOP 208-mil
C
1
E
E1
L
N
T
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.70
0.05
0.35
0.15
5.13
5.18
7.70
0.51
0°
MAX
2.16
0.25
0.48
0.35
5.35
5.40
8.26
0.85
8°
NOM
NOTE
SYMBOL
A1
A
A1
b
4
4
C
D
E1
E
D
2
L
SIDE VIEW
T
e
1.27 BSC
3
Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
2. Mismatch of the upper and lower dies and resin burrs aren't included.
3. Determines the true geometric position.
4. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm.
4/15/08
DRAWING NO.
REV.
GPC
TITLE
8S2, 8-lead, 0.208” Body, Plastic Small
Outline Package (EIAJ)
Package Drawing Contact:
contact@adestotech.com
STN
8S2
F
AT25QF128A
DS-AT25QF128A–176D–06-2020
52
11.2 Package 8 UDFN
E
C
Pin 1 ID
SIDE VIEW
D
y
TOP VIEW
E2
A1
A
K
8
Option A
0.45
Pin #1
1
2
3
Pin #1 Notch
(0.20 R)
(Option B)
Chamfer
(C 0.35)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
NOTE
SYMBOL
7
D2
6
A
0.45
0.55
0.60
e
A1
b
0.00
0.35
0.02
0.40
0.152 REF
5.00
4.00
6.00
3.40
1.27
0.60
–
0.05
0.48
C
D
D2
E
4.90
3.80
5.90
3.20
5.10
4.20
6.10
3.60
5
4
b
BOTTOM VIEW
L
E2
e
L
0.50
0.00
0.20
0.75
0.08
–
y
K
–
4/15/08
REV.
GPC
YFG
DRAWING NO.
8MA1
TITLE
Package Drawing Contact:
contact@adestotech.com
8MA1, 8-pad (5 x 6 x 0.6 mm Body), Thermally
Enhanced Plastic Ultra Thin Dual Flat No Lead
Package (UDFN)
D
AT25QF128A
DS-AT25QF128A–176D–06-2020
53
12. Revision History
Table 12-1. Document Revision History
Revision
Date
Change Description
A
03/2019
Initial release.
Removed SFDP tables and updated Section 8.4.10, Read SFDP (5Ah).
Updated text in Section 8.4.10, Read SFDP.
Updated document to new Adesto template.
Updated Section 3.7, HOLD.
Updated definition of SRP[1:0] bits in Section 6.4.2.4.
Reformatted tables in Section 6.4.1, Status registers.
Updated Table 6-2, Status register protections.
Added note to end of Section 8.4.8, Erase/Program Suspend (75h)
Changed ICC6, ICC7, and ICC8 maximum values in Tables 9-6 and 9-7
from 15 mA to 20 mA.
B
11/2019
Clarified use of decoupling capacitors in Section 6.1.1.
C
D
02/2020
06/2020
Changed status from PRELIMINARY DATASHEET to DATASHEET.
Exchanged 35 figures with new ones to conform to Adesto standard (no
change in content): 6-1, 8-1, 8-5, 8-11 through 8-38, 9-2 through 9-6.
Added reference to figure 8-24 in preceding text. Replaced instances of
Status Register Byte with Status Register. Replaced 8S4 reference and
drawing with 8S2.
AT25QF128A
DS-AT25QF128A–176D–06-2020
54
Corporate Office
California | USA
Adesto Headquarters
3600 Peterson Way
Santa Clara, CA 95054
Phone: (+1) 408.400.0578
Email: contact@adestotech.com
Copyright © 2020 Adesto Technologies Corporation. All rights reserved. DS-AT25QF128A–176D–06-2020
Adesto, the Adesto logo, CBRAM and DataFlash are trademarks or registered trademarks of Adesto Technologies Corporation in the United States and other countries. Other company, product, and service
names may be trademarks or service marks of others. Adesto products are covered by one or more patents listed at http://www.adestotech.com/patents.
Disclaimer: Adesto Technologies Corporation (“Adesto”) makes no warranties of any kind, other than those expressly set forth in Adesto’s Terms and Conditions of Sale at
http://www.adestotech.com/terms-conditions. Adesto assumes no responsibility or obligations for any errors which may appear in this document, reserves the right to change devices or specifications
herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Adesto are granted by Adesto
herewith or in connection with the sale of Adesto products, expressly or by implication. Adesto’s products are not authorized for use in medical applications (including, but not limited to, life support systems
and other medical equipment), weapons, military use, avionics, satellites, nuclear applications, or other high risk applications (e.g., applications that, if they fail, can be reasonably expected to result in
personal injury or death) or automotive applications, without the express prior written consent of Adesto.
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