AT25SF321B-SHB-B_技术文档

DATASHEET

AT25SF321B

32-Mbit SPI Serial Flash Memory

with Dual-I/O and Quad-I/O Support

Features



Serial Peripheral Interface (SPI) Compatible

-

Supports SPI modes 0 and 3 (1,1,1)

Supports dual input and dual output operation (1,1,2)

Supports quad input and quad output operation (1,1,4)

Supports quad I/O operation (1,4,4 and 0,4,4)



108 MHz Maximum Operating Frequency

Single 2.7 V - 3.6 V Single Supply Voltage

Continuous Read modes

Serial Flash Discoverable Parameters (SFDP, JDES216B) support

OTP Memory

-

Three Protected Programmable Security Register Pages (Page size: 256 bytes)

64-bit factory programmable UID register



Hardware Write Protection (WP pin)

Software Write protection (Programmable non-volatile control registers)

Program and Erase Suspend and Resume

Byte programming size: up to 256 bytes

Erase Size and Duration

-

Uniform 4-kbyte Block Erase (50 ms typical)

Uniform 32-kbyte Block Erase (150 ms typical)

Uniform 64-kbyte Block Erase (300 ms typical)

Full Chip Erase (15 seconds typical)



Low Power Dissipation

-

Standby Current (25 µA maximum)

Deep Power Down Current (5 µA maximum)



Endurance: 100,000 Program and Erase Cycles

Data Retention: 20 Years

Industrial Temperature Range (-40 ^oC to 85 ^oC)

Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options

-

8-lead SOIC (0.150” Narrow and 0.208” Wide)

8-pad Ultra-Thin DFN (5 x 6 x 0.6 mm)

Die Wafer Form

Other Package Options (contact Adesto)

DS-AT25SF321B–179E–06-2020

Table of Contents

1. Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Pin Descriptions and Package Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

3. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

4. Memory Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

5. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

5.1 Dual Output Read (1-1-2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.2 Dual I/O Read (1-2-2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.3 Quad Output Read (1-1-4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.4 Quad I/O Read (1-4-4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

6. Commands and Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

7. Read Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

7.1 Read Array (0Bh and 03h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7.2 Dual-Output Read Array (3Bh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7.3 Dual-I/O Fast Read Array (BBh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7.3.1 Dual-I/O Fast Read Array (BBh) with Continuous Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

7.4 Quad Output Fast Read Array (6Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.5 Quad-I/O Fast Read Array (EBh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.5.1 Quad-I/O Fast Read Array (EBh) with Continuous Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

7.5.2 Set Burst with Wrap (77h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

7.6 Quad-I/O Word Fast Read (E7h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.6.1 Quad I/O Word Fast Read with “Continuous Read Mode” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

7.6.2 Quad I/O Word Fast Read with 8-, 16-, 32-, 64-Byte Wrap Around in Standard SPI Mode . . . . . . . . . . . .20

7.7 Read Serial Flash Discoverable Parameter (5Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

8. Program and Erase Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

8.1 Byte/Page Program (02h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8.2 Quad Page Program (32h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8.3 Block Erase (20h, 52h, or D8h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.4 Chip Erase (60h or C7h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.5 Program/Erase Suspend (75h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8.6 Program/Erase Resume (7Ah). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

9. Protection Commands and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

9.1 Write Enable (06h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

9.2 Write Disable (04h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

9.3 Non-Volatile Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

9.4 Protected States and the Write Protect Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

9.5 Enable Reset (66h) and Reset Device (99h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

10. Security Register Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

10.1 Read Unique ID Number (4Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

10.2 Erase Security Registers (44h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

10.3 Program Security Registers (42h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

10.4 Read Security Registers (48h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

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Table of Contents

11. Status Register Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

11.1 Read Status Register (05h, 35h, and 15h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

11.1.1 SRP1, SRP0 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

11.1.2 CMP, BP4, BP3, BP2, BP1, BP0 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

11.1.3 WEL Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

11.1.4 RDY/BSY Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

11.1.5 LB3, LB2, LB1 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

11.1.6 E_SUS Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

11.1.7 P_SUS Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

11.1.8 QE Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

11.2 Write Status Register (01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

11.3 Write Enable for Volatile Status Register (50h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

12. Other Commands and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

12.1 Read Manufacturer and Device ID (9Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

12.2 Read ID (Legacy Command) (90h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

12.3 Dual I/O Read Manufacture ID/ Device ID (92h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

12.4 Quad I/O Read Manufacture ID / Device ID (94h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

12.5 Deep Power-Down (B9h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

12.6 Resume from Deep Power-Down (ABh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

12.6.1 Resume from Deep Power-Down and Read Device ID (ABh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

12.7 Hold Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

13. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

13.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

13.2 DC and AC Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

13.3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

13.4 AC Characteristics - Maximum Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

13.5 AC Characteristics - All Other Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

13.6 Program and Erase Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

13.7 Power Up Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

13.8 Input Test Waveforms and Measurement Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

13.9 Output Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

14. AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

15. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

16. Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

16.1 8S1 – 0.150” Narrow JEDEC SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

16.2 8S2 – 8-lead, 0.208” Wide EIAJ SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

16.3 8MA1 – UDFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

17. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

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1.

Product Overview

The Adesto^®AT25SF321B is a serial interface Flash memory device designed for a wide variety of high-volume

consumer based applications in which program code is shadowed from Flash memory into embedded or external

RAM for execution. The flexible erase architecture of the AT25SF321B also is ideal for data storage, eliminating

the need for additional data storage devices.

The AT25SF321B erase block sizes are optimized to meet the needs of today's code and data storage

applications. This means memory space can be used much more efficiently. Because certain code modules and

data storage segments must reside in their own erase regions, the wasted and unused memory space that occurs

with large-block-erase Flash memory devices can be reduced greatly. This increased memory space allows

additional code routines and data storage segments to be added, while maintaining the same overall device

density.

This device also contains three Security Register pages for unique device serialization, system-level Electronic

Serial Number (ESN) storage, locked key storage, etc. These pages can be locked individually.

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2.

Pin Descriptions and Package Pinouts

Table 2-1. Pin Descriptions

Asserted

State

Symbol

Name and Function

Type

CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is

deasserted, the device is deselected and normally be placed in standby mode.

A high-to-low transition on the CS pin is required to start an operation; a low-to-

high transition is required to end an operation. When ending an internally self-

timed operation, such as a program or erase cycle, the device does not enter the

standby mode until the operation is complete.

CS

Low

Input

SERIAL CLOCK: This pin provides a clock to the device. Command, address, and

input data present on the SI pin is latched in on the rising edge of SCK, while

output data on the SO pin is clocked out on the falling edge of SCK.

SCK

-

Input

SERIAL INPUT: The SI pin is used for all data input, including command and

address sequences. Data on the SI pin is always latched in on the rising edge of

SCK.

With the Dual-Output and Quad-Output Read commands, the SI pin becomes an

output pin (I/O₀) in conjunction with other pins to allow two or four bits of data (on

I/O_3-0) to be clocked in on every falling edge of SCK.

SI (I/O₀)

-

Input/Output

Data present on the SI pin is ignored whenever the device is deselected (CS is

deasserted).

SERIAL OUTPUT: Data on the SO pin is clocked out on the falling edge of SCK.

With the Dual-Output Read commands, the SO pin remains an output pin (I/O₀) in

conjunction with other pins to allow two bits of data (on I/O_1-0) to be clocked in on

every falling edge of SCK.

SO (I/O₁)

-

Input/Output

The SO pin is in a high-impedance state whenever the device is deselected (CS is

deasserted).

WRITE PROTECT: The WP pin controls the hardware locking feature of the

device.

With the Quad-Input Byte/Page Program command, the WP pin becomes an input

pin (I/O₂) and, along with other pins, allows four bits (on I/O_3-0) of data to be

clocked in on every rising edge of SCK. With the Quad-Output Read commands,

the WP Pin becomes an output pin (I/O₂) in conjunction with other pins to allow

four bits of data (on I/O3_3-0) to be clocked in on every falling edge of SCK.

WP

(I/O₂)

-

Input/Output

The WP pin is internally pulled-high and can be left floating if hardware-controlled

protection is not used; however, it is recommended that the WP pin also be

externally connected to V_CCwhenever possible.

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Table 2-1. Pin Descriptions (continued)

Asserted

State

Symbol

Name and Function

Type

HOLD: The HOLD pin temporarily pauses serial communication without

deselecting or resetting the device. While the HOLD pin is asserted, transitions on

the SCK pin and data on the SI pin are ignored, and the SO pin is in a high-

impedance state.

The CS pin must be asserted, and the SCK pin must be in the low state, for a Hold

condition to start. A Hold condition pauses serial communication only and does not

have an affect on internally self-timed operations, such as a program or erase

cycle. See “Hold Function”, on page 48, for additional details on this operation.

HOLD

(I/O₃)

-

Input/Output

With the Quad-Input Byte/Page Program command, the HOLD pin becomes an

input pin (I/O₃) and, along with other pins, allows four bits (on I/O_3-0) of data to be

clocked in on every rising edge of SCK. With the Quad-Output Read commands,

the HOLD pin becomes an output pin (I/O₃) in conjunction with other pins to allow

four bits of data (on I/O3_3-0) to be clocked in on every falling edge of SCK.

The HOLD pin is internally pulled-high and can be left floating if the Hold function is

not used. It is recommended, however, that the HOLD pin is externally connected

to V_CCwhenever possible.

V_CC

DEVICE POWER SUPPLY: The V_CCpin supplies the source voltage to the device.

-

Power

GROUND: The ground reference for the power supply. Connect GND to the

system ground.

GND

CS

SO (IO₁)

WP (IO₂)

GND

1

2

3

4

8

7

6

5

VCC

HOLD (IO₃)

SCK

CS 1

SO (IO₁) 2

WP (IO₂) 3

GND 4

8 VCC

7 HOLD (IO₃)

6 SCK

SI (IO₀)

5 SI (IO₀)

Figure 2-1. 8-SOIC (0.150” and 0.208”) — Top View

Figure 2-2. 8-UDFN — Top View

AT25SF321B

DS-AT25SF321B–179E–06-2020

6

3.

Block Diagram

Control and

Protection Logic

I/O Buffers

and Latches

CS

SRAM

Data Buffer

SCK

Interface

Control

And

SI (I/O )

0

Y-Decoder

Y-Gating

Logic

SO (I/O )

1

Flash

Memory

Array

WP (I/O )

2

X-Decoder

HOLD (I/O )

3

Note: I/O

3-0

pin naming convention is used for Dual-I/O and Quad-I/O commands.

Figure 3-1. Block Diagram

AT25SF321B

DS-AT25SF321B–179E–06-2020

7

4.

Memory Array

To provide the greatest flexibility, the memory array of the AT25SF321B can be erased in four levels of granularity,

including a full-chip erase. The size of the erase blocks is optimized for both code and data storage applications,

allowing both code and data segments to reside in their own erase regions. The Memory Architecture Diagram

illustrates each erase level.

Table 4-1. Memory Architecture Diagram: Block Erase Detail

64-kbyte Block Erase (D8h) 32-kbyte Block Erase (52h) 4-kbyte Block Erase (20h)

Block Address Range

3FF000h - 3FFFFFh

3FE000h - 3FEFFFh

3FD000h - 3FDFFFh

3FC000h - 3FCFFFh

3FB000h - 3FBFFFh

3FA000h - 3FAFFFh

3F9000h - 3F9FFFh

3F8000h - 3F8FFFh

3F7000h - 3F7FFFh

3F6000h - 3F6FFFh

3F5000h - 3F5FFFh

3F4000h - 3F4FFFh

3F3000h - 3F3FFFh

3F2000h - 3F2FFFh

3F1000h - 3F1FFFh

3F0000h - 3F0FFFh

4 kbytes (Block 1023)

4 kbytes (B1022)

4 kbytes (B1021)

32 kbytes

4 kbytes (B1020)

4 kbytes (B1019)

4 kbytes (B1018)

4 kbytes (B1017)

4 kbytes (B1016)

4 kbytes (B1015)

4 kbytes (B1014)

4 kbytes (B1013)

4 kbytes (B1012)

4 kbytes (B1011)

4 kbytes (B1010)

4 kbytes (B1009)

4 kbytes (B1008)

(block 127)

64 kbytes

(block 63)

32 kbytes

(block 126)

64 kbytes (block 62)

to

32 kbytes (block 125)

to

4 kbytes (B1007)

to

3EF000h - 3EFFFFh

to

64 kbytes (block 1)

32 kbytes (block 2)

4 kbytes (B16)

010000h - 010FFFh

4 kbytes (B15)

4 kbytes (B14)

4 kbytes (B13)

4 kbytes (B12)

4 kbytes (B11)

4 kbytes (B10)

4 kbytes (B9)

4 kbytes (B8)

4 kbytes (B7)

4 kbytes (B6)

4 kbytes (B5)

4 kbytes (B4)

4 kbytes (B3)

4 kbytes (B2)

4 kbytes (B1)

4 kbytes (B0)

00F000h - 00FFFFh

00E000h - 00EFFFh

00D000h - 00DFFFh

00C000h - 00CFFFh

00B000h - 00BFFFh

00A000h - 00AFFFh

009000h - 009FFFh

008000h - 008FFFh

007000h - 007FFFh

006000h - 006FFFh

005000h - 005FFFh

004000h - 004FFFh

003000h - 003FFFh

002000h - 002FFFh

001000h - 001FFFh

000000h - 000FFFh

32 kbytes

(block 1)

64 kbytes

(block 0)

32 kbytes

(block 0)

AT25SF321B

DS-AT25SF321B–179E–06-2020

8

Table 4-2. AT25SF321B Device Block Memory Map — Page Erase and Page Program

4 -kbyte Blocks

4 kbytes (Block 1023)

4 kbytes (B1022)

4 kbytes (B1021)

4 kbytes (B1020)

4 kbytes (B1019)

4 kbytes (B1018)

4 kbytes (B1017)

4 kbytes (B1016)

4 kbytes (B1015)

4 kbytes (B1014)

4 kbytes (B1013)

4 kbytes (B1012)

4 kbytes (B1011)

4 kbytes (B1010)

4 kbytes (B1009)

4 kbytes (B1008)

256 Byte Page Erase

256 Bytes

1 - 256 Byte Page Program

3FFF00h - 3FFFFFh

3FFE00h - 3FFEFFh

3FFD00h - 3FFDFFh

3FFC00h - 3FFCFFh

3FFB00h - 3FFBFFh

3FFA00h - 3FFAFFh

3FF900h - 3FF9FFh

3FF800h - 3FF8FFh

3FF700h - 3FF7FFh

3FF600h - 3F6FFFh

3FF500h - 3FF5FFh

3FF400h - 3FF4FFh

3FF300h - 3FF3FFh

3FF200h - 3FF2FFh

3FF100h - 3FF1FFh

3FF000h - 3FF0FFh

4 kbytes (B1007)

to

4 kbytes (B16)

.

4 kbytes (B15)

4 kbytes (B14)

4 kbytes (B13)

4 kbytes (B12)

4 kbytes (B11)

4 kbytes (B10)

4 kbytes (B9)

4 kbytes (B8)

4 kbytes (B7)

4 kbytes (B6)

4 kbytes (B5)

4 kbytes (B4)

4 kbytes (B3)

4 kbytes (B2)

4 kbytes (B1)

4 kbytes (B0)

256 Bytes

000F00h - 000FFFh

000E00h - 000EFFh

000D00h - 000DFFh

000C00h - 000CFFh

000B00h - 000BFFh

000A00h - 000AFFh

000900h - 0009FFh

000800h - 0008FFh

000700h - 0007FFh

000600h - 0006FFh

000500h - 0005FFh

000400h - 0004FFh

000300h - 0003FFh

000200h - 0002FFh

000100h - 0001FFh

000000h - 0000FFh

AT25SF321B

DS-AT25SF321B–179E–06-2020

9

5.

Device Operation

The AT25SF321B is controlled by a set of instructions sent from a host controller, SPI Master. The SPI Master

communicates with the AT25SF321B through the SPI bus, which consists of four pins: Chip Select (CS), Serial

Clock (SCK), Serial Input (SI), and Serial Output (SO).

The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3). The AT25SF321B supports the two

most common modes, SPI modes 0 and 3. For these modes, data is latched in on the rising edge of SCK and

output on the falling edge of SCK.

&6

6&.

06%

/6%

6,

MSB

/6%

62

Figure 5-1. SPI Mode 0 and 3

5.1

5.2

5.3

Dual Output Read (1-1-2)

The AT25SF321B features a Dual-Output Read mode that allows two bits of data to be clocked out of the device

every clock cycle to improve throughput. To do this, both the SI and SO pins are used as outputs for the transfer of

data bytes. With the Dual-Output Read Array command, the SI pin becomes an output along with the SO pin.

Dual I/O Read (1-2-2)

The AT25SF321B supports Dual I/O (1-2-2) transfers, which enhance throughput over the standard SPI mode.

This mode transfers the command on the SI pin, but the address and data are transferred on the SI and SO pins.

This means that only half the number of clocks are required to transfer the address and data.

Quad Output Read (1-1-4)

The AT25SF321B features a Quad-Output Read mode that allows four bits of data to be clocked out of the device

every clock cycle to improve throughput. To do this, the SI, SO, WP, and HOLD pins are used as outputs for the

transfer of data bytes. With the Quad-Output Read Array command, the SI, WP, and HOLD pins become outputs

along with the SO pin.

5.4

Quad I/O Read (1-4-4)

The AT25SF321B supports Quad I/O (1-4-4) transfers, which enhance throughput over the standard SPI mode.

This mode transfers the command on the SI pin, but the address and data are transferred on the SI, SO, WP, and

HOLD pins. This means that only a quarter of the number of clocks are required to transfer the address and data.

With the Quad I/O Read Array command, the SI, WP, and HOLD and SO pins become inputs during the address

transfer, and switch to outputs during the data transfer.

AT25SF321B

DS-AT25SF321B–179E–06-2020

10

6.

Commands and Addressing

A valid instruction or operation must be started by asserting the CS pin. After that, the host controller must clock

out a valid 8-bit opcode on the SPI bus. Following the opcode, instruction-dependent information, such as address

and data bytes, can be clocked out by the host controller. All opcode, address, and data bytes are transferred with

the most-significant bit (MSB) first. An operation is ended by deasserting the CS pin.

Opcodes not supported by the AT25SF321B are ignored, and no operation is started. The device continues to

ignore any data presented on the SI pin until the start of the next operation (CS pin deasserted, then reasserted). If

the CS pin is deasserted before complete opcode and address information is sent to the device, the device simply

returns to the idle state and waits for the next operation.

Device addressing requires three bytes, representing address bits A23-A0, to be sent. Since the upper address

limit of the AT25SF321B memory array is 3FFFFFh, address bits A23-A22 are always ignored by the device.

Table 6-1. AT25SF321B Command Table

Bus Transfer Type

(OP-AD-DA)⁽¹⁾

Command

Opcode

Mode Bit Mode Bit

Wait Cycle

# of Data

Bytes

Command Name

Present

Clocks Dummy Clocks

System Commands

Enable Reset

66h

99h

B9h

ABh

1-0-0

N

0

Reset Device

Deep Power-down

Release Power-down

Read Commands

Normal Read Data

03h

0Bh

3Bh

BBh

6Bh

EBh

E7h

1-1-1

1-1-2

1-2-2

0-2-2

1-1-4

1-4-4

0-4-4

1-4-4

N

Y

N

Y

0

4

0

2

0

8

0

8

4

2

1+

Fast Read

Dual Output Fast read

Dual I/O Fast read

Dual I/O Fast read (Continuous Mode)

Quad Output Fast read

Quad I/O Fast read

Quad I/O Fast read (Continuous Mode)

Word Read Quad I/O

Word Read Quad I/O (Continuous

Mode)

E7h

77h

0-4-4

1-0-4

Y

N

2

0

2

6

1+

Set Burst With Wrap

Write Commands

Write Enable

1, D[6:4]

06h

50h

04h

1-0-0

N

0

Volatile SR Write Enable

Write Disable

Program Commands

AT25SF321B

DS-AT25SF321B–179E–06-2020

11

Table 6-1. AT25SF321B Command Table (continued)

Bus Transfer Type

(OP-AD-DA)⁽¹⁾

Command

Opcode

Mode Bit Mode Bit

Wait Cycle

# of Data

Bytes

Command Name

Present

Clocks Dummy Clocks

Page Program

02h

32h

1-1-1

N

0

1+

Quad Page Program

1-1-4

Erase Commands

Block Erase (4 kbytes)

Block Erase (32 kbytes)

Block Erase (64 kbytes)

Chip Erase

20h

52h

1-1-0

1-0-0

N

0

D8h

C7h/60h

Suspend/Resume Commands

Program/Erase Suspend

Program/Erase Resume

Status Register Commands

Read Status Register 1

Read Status Register 2

Read Status Register 3

Write Status Register 1

Write Status Register 2

Write Status Register 3

Device Information Commands

Manufacturer/Device ID

Mfgr./Device ID Dual I/O

Mfgr./Device ID Quad I/O

Read JEDEC ID

75h

7Ah

1-0-0

N

0

05h

35h

15h

01h

31h

11h

1-0-1

N

0

1

90h

92h

94h

9Fh

1-1-1

1-2-2

1-4-4

1-0-1

N

0

4

0

2

3

Read Serial Flash Discoverable

Parameter

5Ah

1-1-1

N

0

8

1+

OTP Commands

Erase Security Registers

Program Security Registers

Read Security Registers

Read Unique ID Number

44h

42h

48h

4Bh

1-1-0

1-1-1

1-0-1

N

0

1+

8

32

1. OP = Opcode (command number), AD = Address. DA = Data. 0 indicates the corresponding transfer does not occur in that command. 1 indicates the

transfer does occur. For example, 1-0-0 indicates a command transfer occurs, but no address or data transfers occur.

Op: Opcode or Commands (8-bits): 0 => No Opcode [continuous Read], 1 => 8 clocks for Opcode, 2 => 4 clocks for Opcode, 4 => 2 clocks for opcode.

AD: Address (24-bits) Only: 0 => No address, Opcode only operation, 1 => 24 clocks for Address, 2 => 12 clocks for address, 4 => 6 clocks for address.

AD: Address (24-bits) + Mode (8-bits): 2 => 12 clocks for address, 4 clocks for mode [BBh only], 4 => 6 clocks for address, 2 clocks for mode [EBh and E7h].

DA: Data(8-bits): 1 => 8 clocks for byte, 2 => 4 clocks for byte, 4 => 2 clocks for byte.

AT25SF321B

DS-AT25SF321B–179E–06-2020

12

7.

Read Commands

7.1

Read Array (0Bh and 03h)

The Read Array command can be used to sequentially read a continuous stream of data from the device by

providing the clock pin once the initial starting address is specified. The device incorporates an internal address

counter that automatically increments every clock cycle.

To perform the Read Array operation, the CS pin first must be asserted, and the appropriate opcode (0Bh or 03h)

must be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in

to specify the starting address location of the first byte to read within the memory array. If the 0Bh opcode is used

for the Read Array operation, an additional dummy byte must be clocked into the device after the three address

bytes.

After the three address bytes (and the dummy byte, if using opcode 0Bh) have been clocked in, additional clock

cycles result in data being output on the SO pin. The data is always output with the MSB of a byte first. When the

last byte (3FFFFFh) of the memory array has been read, the device continues reading back at the beginning of the

array (000000h). No delays are incurred when wrapping around from the end of the array to the beginning of the

array.

Deasserting the CS pin terminates the read operation and puts the SO pin into high-impedance state. The CS pin

can be deasserted at any time and does not require a full byte of data be read.

CS

0

1

2

3

4

5

6

7

8

9

10 11 12

29 30 31 32 33 34 35 36 37 38 39 40

SCK

SI

OPCODE

ADDRESS BITS A23-A0

0

MSB

0

1

A

MSB

A

DATA BYTE 1

HIGH-IMPEDANCE

D

MSB

D

MSB

D

SO

Figure 7-1. Read Array - 03h Opcode

CS

0

1

2

3

4

5

6

7

8

9

10 11 12

29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

SCK

SI

OPCODE

ADDRESS BITS A23-A0

DON'T CARE

0

MSB

0

1

0

1

A

MSB

A

X

MSB

X

DATA BYTE 1

HIGH-IMPEDANCE

D

MSB

D

MSB

D

SO

Figure 7-2. Read Array - 0Bh Opcode

AT25SF321B

DS-AT25SF321B–179E–06-2020

13

7.2

Dual-Output Read Array (3Bh)

The Dual-Output Read Array command is similar to the standard Read Array command and can be used to

sequentially read a continuous stream of data from the device by providing the clock pin once the initial starting

address has been specified. Unlike the standard Read Array command, the Dual-Output Read Array command

allows two bits of data to be clocked out of the device on every clock cycle, rather than just one.

To perform the Dual-Output Read Array operation, the CS pin must first be asserted; then, the opcode 3Bh must

be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to

specify the location of the first byte to read within the memory array. Following the three address bytes, a single

dummy byte also must be clocked into the device.

After the three address bytes and the dummy byte have been clocked in, additional clock cycles output data on

both the SO and SI pins. The data is output with the MSB of a byte first, and the MSB is output on the SO pin.

During the first clock cycle, bit seven of the first data byte is output on the SO pin, while bit six of the same data

byte is output on the SI pin. During the next clock cycle, bits five and four of the first data byte are output on the SO

and SI pins, respectively. The sequence continues with each byte of data being output after every four clock

cycles. When the last byte (3FFFFFh) of the memory array has been read, the device continues reading from the

beginning of the array (000000h). There are no delays when wrapping around from the end of the array to the

beginning of the array. Deasserting the CS pin terminates the read operation and puts the SO and SI pins into a

high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be

read.

CS

0

1

2

3

4

5

6

7

8

9

10 11 12

29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

SCK

SI (SIO)

SO

ꢃꢖꢐꢄꢖꢐ

ꢆꢌꢐꢌꢎꢂꢗꢐꢇꢋ ꢆꢌꢐꢌꢎꢂꢗꢐꢇꢑ

ꢃꢖꢐꢄꢖꢐ

ꢃꢄꢅꢃꢆꢇ

ꢌꢆꢆꢍꢇꢁꢁꢎꢂꢏꢐꢁꢎꢌꢑꢊꢒꢌꢓꢎ

ꢆꢃꢔꢕꢐꢎꢎꢅꢌꢍꢇ

D

4

0

1

0

1

A

X

6

4

2

0

6

4

2

0

6

ꢀꢁꢂ

ꢘꢏꢙꢘꢒꢏꢀꢄꢇꢆꢌꢔꢅꢇ

ꢆ

ꢉ

ꢆ

ꢊ

ꢆ

ꢉ

ꢆ

ꢊ

ꢆ

ꢉ

ꢈ

ꢋ

7

ꢋ

ꢈ

ꢀꢁꢂ

Figure 7-3. Dual-Output Read Array

7.3

Dual-I/O Fast Read Array (BBh)

The Dual-I/O Fast Read Array command is similar to the Dual-Output Read Array command and can be used to

sequentially read a continuous stream of data from the device by providing the clock pin once the initial starting

address with two bits of address on each clock and two bits of data on every clock cycle.

To perform the Dual-I/O Fast Read Array operation, the CS pin must first be asserted; then, the opcode BBh must

be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to

specify the location of the first byte to read within the memory array. Following the three address bytes, a single

mode byte also must be clocked into the device.

After the three address bytes and the mode byte have been clocked in, additional clock cycles output data on both

the SO and SI pins. The data is always output with the MSB of a byte first, and the MSB is always output on the SO

pin. During the first clock cycle, bit seven of the first data byte is output on the SO pin, while bit six of the same data

byte is output on the SI pin. During the next clock cycle, bits five and four of the first data byte are output on the SO

and SI pins, respectively. The sequence continues with each byte of data output after every four clock cycles.

When the last byte (3FFFFFh) of the memory array has been read, the device continues reading from the

AT25SF321B

DS-AT25SF321B–179E–06-2020

14

beginning of the array (000000h). No delays are incurred when wrapping around from the end of the array to the

beginning of the array. Deasserting the CS pin terminates the read operation and puts the SO and SI pins into a

high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be

read.

CS

0

1

2

1

3

4

5

6

7

8

9

10 11 12

19 20 21 22 23 24 25 26 27

SCK

Address Bits

A23-A16

Address Bits

A15-A8 A7-A0

Opcode

M7-M0

M₂M₀

Byte 1

D₂D₀

Byte 2

1

0

1

0

1

A

22

A

20

A

18

A

16

A

14

A

0

M

6

M

4

D

6

D

4

D

6

I/O₀

(SI)

MSB

M₃M₁

D₃D₁

D

I/O₁

(SO)

A

23

A

21

A

19

A

17

A

15

A

1

M

7

M

5

D

7

D

5

7

MSB

Figure 7-4. Dual-I/O Fast Read Array (Initial command or previous M5, M4 ≠ 1,0)

7.3.1 Dual-I/O Fast Read Array (BBh) with Continuous Read Mode

The Fast Read Dual I/O command can further reduce instruction overhead through setting the Continuous Read

Mode bits (M7-0) after the input Address bits (A23-0), as shown in Figure 7-5. The upper nibble of M7-4 controls

the length of the next Fast Read Dual I/O command through the inclusion, or exclusion, of the first byte instruction

code. The lower nibble bits of M3-0 are don't care (“x”). However, the I/O pins must be high-impedance prior to the

falling edge of the first data out clock. If the “Continuous Read Mode” bits M5-4 = (1,0), the next Fast Read Dual I/O

command (after CS is raised and then lowered) does not require the BBh instruction code. This reduces the

command sequence by eight clocks and allows the Read address to be immediately entered after CS is asserted

low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next command (after CS is raised and then

lowered) requires the first byte instruction code, thus returning to normal operation. A Continuous Read Mode

Reset command can also be used to reset M7-0 before issuing normal commands.

CS

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21

SCK

Address Bits

A23-A16

Address Bits

A7-A0

M7-M0

Byte 1

Byte 2

A15-A8

A

M₂M₀

D₂D₀

A

22

A20

A

18

A

16

A

14

A

0

1

M

6

7

M

4

5

D

6

7

D

4

5

D

6

I/O₀

(SI)

MSB

M₃M₁

D₃D₁

I/O₁

(SO)

A

23

A

21

A

19

A

17

A

15

A

M

D

7

MSB

Figure 7-5. Dual-I/O Fast Read Array (Previous command set M5, M4 = 1,0)

AT25SF321B

15

DS-AT25SF321B–179E–06-2020

7.4

Quad Output Fast Read Array (6Bh)

The Quad-Output Fast Read Array command is followed by a three-byte address (A23 - A0) and one dummy byte,

each bit being latched in during the rising edge of SCLK; then, the memory contents are shifted out four bits per

clock cycle from I/O₃, I/O₂, I/O₁, and I/O₀. The first byte addressed can be at any location. The address

automatically increments to the next higher address after each byte of data is shifted out.

CS

0

1

2

3

4

5

6

7

8

9

10 11 12

29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

Byte 1 Byte 2 Byte 3 Byte 4 Byte 5

SCK

OUT

Opcode

Address Bits A23-A0

Don't Care

0

ꢀꢁꢂ

1

0

1

0

1

A

ꢀꢁꢂ

A

X

ꢀꢁꢂ

X

D₄D₀D₄D₀D₄D₀D₄D₀D₄D₀

D₅D₁D₅D₁D₅D₁D₅D₁D₅D₁

D₆D₂D₆D₂D₆D₂D₆D₂D₆D₂

I/O₀

(SI)

HIGH-IMPEDANCE

I/O₁

(SO)

I/O₂

(WP)

D₇D₃D₇D₃D₇D₃D₇D₃D₇D₃

I/O₃

(HOLD)

MSB

Figure 7-6. Quad-Output Fast Read Array

7.5

Quad-I/O Fast Read Array (EBh)

The Quad-I/O Fast Read Array command is similar to the Quad-Output Fast Read Array command. It allows four

bits of address to be clocked into the device on every clock cycle, rather than just one.

To perform the Quad-I/O Read Array operation, the CS pin must first be asserted; then, the opcode EBh must be

clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to

specify the location of the first byte to read within the memory array. Following the three address bytes, a single

mode byte must also be clocked into the device.

After the three address bytes, the mode byte and two dummy bytes have been clocked in, additional clock cycles

output data on the I/O_3-0pins. The data is output with the MSB of a byte first, and the MSB is output on the I/O₃pin.

During the first clock cycle, bit 7 of the first data byte is output on the I/O₃pin while bits 6, 5, and 4 of the same data

byte are output on the I/O₂, I/O₁and I/O₀pins, respectively. During the next clock cycle, bits 3, 2, 1, and 0 of the

first data byte are output on the I/O₃, I/O₂, I/O₁and I/O₀pins, respectively. The sequence continues with each byte

of data being output after every two clock cycles.

When the last byte (3FFFFFh) of the memory array has been read, the device continues reading from the

beginning of the array (000000h). No delays are incurred when wrapping around from the end of the array to the

beginning of the array. Deasserting the CS pin terminates the read operation and puts the I/O₃, I/O₂, I/O₁and I/O₀

pins into a high-impedance state. The CS pin can be deasserted at any time and does not require a full byte of data

to be read. The Quad Enable bit (QE) of the Status Register must be set to enable for the Quad-I/O Read Array

instruction.

AT25SF321B

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16

CS

0

1

2

1

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23

SCK

Opcode

A23-A16 A15-A8

A7-A0

M7-M0

Dummy

Byte 1

Byte 2

D₀D₄

I/O0

D

4

D

0

1

0

1

A

20

A

16

A

12

A8

A

4

A0 M4 M0

(SI)

MSB

D₁D₅

D₂D₆

D₃D₇

D

5

D

1

I/O₁

5

A1 M5 M1

A

21 A17 A13 A9 A

(SO)

I/O₂

D

6

D2

A

22

A

18

A

14

A

10

A

6

A2 M6 M2

(WP)

I/O₃

D

7

D3

A23

A

19

A

15

A

11

A

7

A3 M7 M3

(HOLD)

Figure 7-7. Quad-I/O Read Array (Initial command or previous M5, M4 ≠ 1,0)

7.5.1 Quad-I/O Fast Read Array (EBh) with Continuous Read Mode

The Fast Read Quad I/O command can further reduce instruction overhead through setting the Continuous Read

Mode bits (M7-0) after the input Address bits (A23-0), as shown in Figure 7-7. The upper nibble (M7-4) of the

Continuous Read Mode bits controls the length of the next Fast Read Quad I/O command through the inclusion, or

exclusion, of the first byte instruction code. The lower nibble bits (M3-0) of the Continuous Read Mode bits are

don't care. However, the IO pins must be high-impedance prior to the falling edge of the first data out clock. If the

Continuous Read Mode bits M5-4 = (1,0), the next Quad-I/O Read Array command (after CS is raised and then

lowered) does not require the EBh instruction code, as shown in Figure 7-8. This reduces the command sequence

by eight clocks and allows the Read address to be immediately entered after CS is asserted low. If the Continuous

Read Mode bits M5-4 do not equal to (1,0), the next command (after CS is raised and then lowered) requires the

first byte instruction code, thus returning to normal operation. A Continuous Read Mode Reset command can also

be used to reset M7-0 before issuing normal commands.

CS

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

SCK

A23-A16 A15-A8

A7-A0

M7-M0

Dummy

Byte 1

Byte 2

I/O0

D₀D₄

A20

A

16

A

12

A

8

A

4

A

0

M

4

M0

D

4

D

0

(SI)

D₁D₅

D₂D₆

D₃D₇

I/O₁

A

21

A

17

A

13

A

9

A

5

A

1

M

5

M

1

D

5

D

1

(SO)

I/O₂

A22

A

18

A

14

A

10

A

6

A

2

M

6

M

2

D

6

D2

(WP)

I/O₃

A

23

A

19

A

15

A

11

A

7

A

3

M

7

M

3

D

7

D3

(HOLD)

Figure 7-8. Quad I/O Read Array with Continuous Read Mode (Previous Command Set M5, M4 = 1,0)

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17

7.5.2 Set Burst with Wrap (77h)

The Set Burst with Wrap instruction is used in conjunction with the Quad I/O Fast Read and Quad I/O Word Fast

Read instruction to access a fixed length (8-, 16-, 32-, or 64-byte) section within a 256-byte page in standard SPI

mode (see Table 7-1 and Figure 7-9).

Table 7-1. Set Burst with Wrap Instruction Functions

W4 = 0

W4 = 1 (Default)

W6, W5

Wrap Around

Wrap Length

8 bytes

Wrap Around

Wrap Length

0

1

0

1

0

1

Yes

No

N/A

16 bytes

32 bytes

64 bytes

CS

0

1

2

1

3

4

5

6

7

8

9

10 11 12 13 14 15 16

SCK

Opcode

Byte 3

Byte 1

Byte 2

Byte 4

HIGH-IMPEDANCE

I/O0

1

0

1

X

W

4

X

(SI)

MSB

HIGH-IMPEDANCE

I/O₁

X

W5

(SO)

I/O₂

W

6

(WP)

I/O₃

X

(HOLD)

Figure 7-9. Set Burst with Wrap Timing (SPI Mode)

The Set Burst with Wrap instruction sequence is: CS goes low → Send Set Burst with Wrap instruction → Send

24 Dummy bits → Send 8 “Wrap bits” → CS goes high.

If W6-4 is set by a Set Burst with Wrap instruction, all the following “Fast Read Quad I/O” and “Word Read Quad

I/O” instructions use the W6-4 setting to access the 8-, 16-, 32-, or 64-byte section within any page. To exit the

“Wrap Around” function and return to normal read operation, issue another Set Burst with Wrap instruction to set

W4=1. The default value of W4 at power-on is 1.

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18

7.6

Quad-I/O Word Fast Read (E7h)

The Quad I/O Word Fast Read instruction is similar to the Quad Fast Read instruction, except that the lowest

address bit (A0) must equal 0 and have two dummy clock cycles. Figure 7-10 shows the instruction sequence; the

first byte addressed can be at any location. The address is automatically incremented to the next higher address

after each byte of data is shifted out. The Quad Enable bit (QE) of the Status Register (S9) must be set to enable.

CS

0

1

2

1

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23

SCK

Opcode

A23-A16 A15-A8

A7-A0

M7-M0 Dummy

Byte 3

Byte 1

Byte 2

D₄

0

D₀D₄

I/O0

D

4

D

0

1

0

1

A

20

A

16

A

12

A

8

A

4

A

0

M

4

M

0

(SI)

MSB

D₅

D₆

D₇

D₁D₅

D₂D₆

D₃D₇

I/O₁

A

21

A

17

A

13

A

9

A

5

A

1

M

5

M

1

D

5

D

1

D1

(SO)

I/O₂

D2

D

2

A

22

A

18

A

14

A

10

A

6

A

2

M

6

M

2

D

6

(WP)

I/O₃

D3

D

3

A23

A

19

A

15

A

11

A

7

A

3

M

7

M

3

D

7

(HOLD)

Figure 7-10. Quad I/O Word Fast Read Timing (Initial Command Set M5, M4 ≠ 1,0) SPI Mode

7.6.1 Quad I/O Word Fast Read with “Continuous Read Mode”

The Quad I/O Word Fast Read instruction can further reduce instruction overhead by setting the “Continuous Read

Mode” bits (M7-0) after input of the Address bits (A23-0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), the

next Quad I/O Fast Read instruction (after CS is raised and then lowered) does not require the E7h instruction

code. Figure 7-11 shows the instruction sequence. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0),

the next instruction requires the first E7h instruction code, thus returning to normal operation. A “Continuous Read

Mode” Reset command also can be used to reset (M5-4) before issuing normal command.

CS

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

SCK

A23-A16 A15-A8

A7-A0

M7-M0 Dummy

Byte 3

Byte 1

Byte 2

D₄

0

I/O0

D₀D₄

D

0

A20

A

16

A

12

A

8

A

4

A

0

M

4

M

0

D

4

D

(SI)

D₅

D₆

D₇

D₁D₅

D₂D₆

D₃D₇

I/O₁

D

1

A

21

A

17

A

13

A

9

A

5

A

1

M

5

M

1

D

5

D

1

(SO)

I/O₂

D

2

A

22

A

18

A

14

A

10

A

6

A

2

M

6

M

2

D

6

D

2

(WP)

I/O₃

D

3

A23

A

19

A

15

A

11

A

7

A

3

M

7

M

3

D

7

D

3

(HOLD)

Figure 7-11. Quad I/O Word Fast Read Timing (Previous Command Set M5, M4 = 1,0) SPI Mode

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19

7.6.2 Quad I/O Word Fast Read with 8-, 16-, 32-, 64-Byte Wrap Around in Standard SPI Mode

The Quad I/O Fast Read instruction also can be used to access a specific portion within a page by issuing a Set

Burst with Wrap (77h) instruction prior to E7h. The Set Burst with Wrap (77h) instruction can enable or disable the

Wrap Around feature for the following E7h instructions. When enabled, the data accessed can be limited to an 8-,

16-, 32-, or 64-byte section of a 256-byte page. The output data starts at the initial address specified in the

instruction when it reaches the ending boundary of the 8-, 16-, 32-, or 64-byte section. The output wraps around to

the beginning boundary automatically until CS is pulled high to terminate the instruction.

The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the

cache afterwards within a fixed length (8-, 16-, 32-, or 64-bytes) of data without issuing multiple read instructions.

The Set Burst with Wrap instruction allows three Wrap Bits (W6-4) to be set. W4 enables or disables the wrap

around operation; W5 specifies the length of the wrap around section within a page.

7.7

Read Serial Flash Discoverable Parameter (5Ah)

The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the

functional and feature capabilities of serial Flash devices in a standard set of internal parameter tables. These

parameter tables can be interrogated by host system software to enable adjustments needed to accommodate

divergent features from multiple vendors. SFDP is a JEDEC Standard, JESD216D. For more detailed SFDP

values, contact Adesto.

CS

0

1

2

3

4

5

6

7

8

9

10 11 12

29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

SCK

DS

SI

Opcode

Address Bits A₂₃-A₀

8 Dummy Cycles

0

MSB

1

0

1

0

1

0

A

MSB

A

X

Output Data Byte 1

D

MSB

D

LSB

SO

Figure 7-12. Read Serial Flash Discoverable Parameter Command Sequence Diagram

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20

8.

Program and Erase Commands

8.1

Byte/Page Program (02h)

The Byte/Page Program command allows one to 256 bytes of data to be programmed into previously erased

memory locations. An erased memory location is one that has all eight bits set to the logical “1” state (a byte value

of FFh). Before a Byte/Page Program command can be started, the Write Enable command must have been

issued to the device (see “Write Enable (06h)”, on page 27) to set the Write Enable Latch (WEL) bit of the Status

Register to a logical “1” state.

To perform a Byte/Page Program command, an opcode of 02h must be clocked into the device, followed by the

three address bytes denoting the first byte location of the memory array to begin programming at. After the address

bytes have been clocked in, data can then be clocked into the device and is stored in an internal buffer.

If the starting memory address denoted by A23-A0 does not fall on an even 256-byte page boundary (A7-A0 are

not all 0), special circumstances regarding which memory locations to be programmed apply. In this situation, any

data that is sent to the device that goes beyond the end of the page wraps around back to the beginning of the

same page. For example, if the starting address denoted by A23-A0 is 0000FEh, and three bytes of data are sent

to the device, then the first two bytes of data are programmed at addresses 0000FEh and 0000FFh, and the last

byte of data is programmed at address 000000h. The remaining bytes in the page (addresses 000001h through

0000FDh) are not programmed and remain in the erased state (FFh). Also, if more than 256 bytes of data are sent

to the device, only the last 256 bytes sent are latched into the internal buffer.

When the CS pin is deasserted, the device takes the data stored in the internal buffer and programs it into the

appropriate memory array locations based on the starting address specified by A23-A0 and the number of data

bytes sent to the device. If fewer than 256 bytes of data were sent to the device, the remaining bytes within the

page are not programmed and remain in the erased state (FFh). The programming of the data bytes is internally

self-timed and, if only programming a single byte, must take place in a time of t_PPor t_BP.

The three address bytes and at least one complete data byte must be clocked into the device before the CS pin is

deasserted, and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the

device aborts the operation and no data is programmed into the memory array. Also, if the memory is in the

protected state, the Byte/Page Program command is not executed, and the device returns to the idle state once the

CS pin has been deasserted. The WEL bit in the Status Register is reset to the logical “0” state if: the program

cycle aborts due to an incomplete address being sent, an incomplete byte of data is sent, the CS pin is deasserted

on uneven byte boundaries, or the memory location to be programmed is protected.

While the device is programming, the Status Register can be read and indicates that the device is busy. For faster

throughput, it is recommended that the Status Register be polled, rather than waiting the t_BPor t_PPtime to

determine if the data bytes have finished programming. At some point before the program cycle completes, the

WEL bit in the Status Register is reset to the logical “0” state.

CS

0

1

2

3

4

5

6

7

8

9

10 11 12

29 30 31 32 33 34 35 36 37 38 39

SCK

SI

OPCODE

ADDRESS BITS A23-A0

DATA IN

0

MSB

0

1

0

A

MSB

A

D

MSB

D

HIGH-IMPEDANCE

SO

Figure 8-1. Byte Program

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21

CS

SCK

SI

0

1

2

3

4

5

6

7

8

9

29 30 31 32 33 34 35 36 37 38 39

OPCODE

ADDRESS BITS A23-A0

DATA IN BYTE 1

DATA IN BYTE n

0

MSB

0

1

0

A

MSB

A

D

MSB

D

MSB

HIGH-IMPEDANCE

SO

Figure 8-2. Page Program

8.2

Quad Page Program (32h)

This instruction is for programming the memory using pins: IO0, IO1, IO2, and IO3. To use this instruction, the

Quad enable (bit 9 in Status Register) must be set (QE=1). A Write Enable instruction must previously have been

executed to set the Write Enable Latch bit before sending the Page Program instruction. The Quad Page Program

instruction is entered by driving CS low, followed by the command code (32H), three address bytes, and at least

one data byte on I/O pins.

Figure 8-3 shows the instruction sequence. If more than 256 bytes are sent to the device, previously latched data

are discarded, and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If

fewer than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without

affecting other bytes of the same page. CS must be driven high after the eighth bit of the last data byte has been

latched in; otherwise, the Quad Page Program instruction is not executed.

As soon as CS is driven high, the self-timed Quad Page Program cycle (whose duration is t_PP) is initiated. While

the Quad Page Program cycle is in progress, the Status Register can be read to check the value of the Write in

Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Quad Page Program cycle; it is 0

when done. At some unspecified time before the cycle is completed, the Write Enable Latch bit is reset. A Quad

Page Program instruction applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0)

bits (see Table 9-1 and Table 9-2) is not executed.

CS

0

1

2

3

4

5

6

7

8

9

10 11 12

29 30 31 32 33 34 35 36 37 38 39 40 41

DATA DATA DATA DATA DATA

SCK

IN 1

IN 2

IN 3

IN 4

IN 5

COMMAND

Address Bits A23-A0

C

D₄D₀D₄D₀D₄D₀D₄D₀D₄D₀

D₅D₁D₅D₁D₅D₁D₅D₁D₅D₁

D₆D₂D₆D₂D₆D₂D₆D₂D₆D₂

C

A

I/O₀

(SI)

HIGH-IMPEDANCE

I/O₁

(SO)

I/O₂

(WP)

D₇D₃D₇D₃D₇D₃D₇D₃D₇D₃

I/O₃

(HOLD)

MSB

Figure 8-3. Quad Page Program (32h) Timing

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22

8.3

Block Erase (20h, 52h, or D8h)

A block of 4, 32, or 64 kbytes can be erased (all bits set to the logical “1” state) in a single operation by using one

of three different opcodes for the Block Erase command. An opcode of 20h is used for a 4-kbytes erase, an opcode

of 52h is used for a 32-kbytes erase, and D8h is used for a 64-kbytes erase. Before a Block Erase command can

be started, the Write Enable command must have been previously issued to the device to set the WEL bit of the

Status Register to a logical “1” state.

To perform a Block Erase, the CS pin must first be asserted and the appropriate opcode (20h, 52h, or D8h) must

be clocked into the device. After the opcode has been clocked in, the three address bytes specifying an address

within the 4- or 32- or 64-kbytes block to be erased must be clocked in. Any additional data clocked into the device

is ignored. When the CS pin is deasserted, the device erases the appropriate block. The erasing of the block is

internally self-timed and takes place in a time of t_BLKE

.

Since the Block Erase command erases a region of bytes, the lower order address bits do not need to be decoded

by the device. Therefore, for a 4-kbytes erase, address bits A11-A0 are ignored by the device, and their values can

be either a logical “1” or “0”. For a 32-kbytes erase, address bits A14-A0 are ignored by the device. For a 64-kbytes

erase, address bits A15-A0 are ignored by the device. Despite the lower-order address bits not being decoded by

the device, the complete three address bytes must still be clocked into the device before the CS pin is deasserted,

and the CS pin must be deasserted on a byte boundary (multiples of eight bits); otherwise, the device aborts the

operation, and no erase operation is performed.

If the memory is in the protected state, the Block Erase command is not executed, and the device returns to the

idle state once the CS pin has been deasserted.

The WEL bit in the Status Register is reset to the logical “0” state if: the erase cycle aborts due to an incomplete

address being sent, the CS pin is deasserted on uneven byte boundaries, or because a memory location within the

region to be erased is protected.

While the device is executing a successful erase cycle, the Status Register can be read and indicates that the

device is busy. For faster throughput, it is recommended that the Status Register be polled to determine if the

device has finished erasing. At some point before the erase cycle completes, the WEL bit in the Status Register is

reset to the logical “0” state.

CS

0

1

2

3

4

5

6

7

8

9

10 11 12

26 27 28 29 30 31

SCK

SI

OPCODE

ADDRESS BITS A23-A0

C

MSB

C

A

MSB

A

HIGH-IMPEDANCE

SO

Figure 8-4. Block Erase Timing

8.4

Chip Erase (60h or C7h)

The entire memory array can be erased in a single operation by using the Chip Erase command. Before a Chip

Erase command can be started, the Write Enable command must have been previously issued to the device to set

the WEL bit of the Status Register to a logical “1” state.

AT25SF321B

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23

Two opcodes (60h and C7h) can be used for the Chip Erase command. There is no difference in device

functionality when using the two opcodes; thus, they can be used interchangeably. To perform a Chip Erase, one

of the two opcodes must be clocked into the device. Since the entire memory array is to be erased, no address

bytes need to be clocked into the device, and any data clocked in after the opcode is ignored. When the CS pin is

deasserted, the device erases the entire memory array. The erasing of the device is internally self-timed and takes

place in a time of t_CHPE

.

The complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be

deasserted on an byte boundary (multiples of eight bits); otherwise, no erase is performed. Also, if the memory

array is in the protected state, the Chip Erase command is not executed, and the device returns to the idle state

once the CS pin has been deasserted. The WEL bit in the Status Register is reset to the logical “0” state if the CS

pin is deasserted on uneven byte boundaries, or if the memory is in the protected state.

While the device is executing a successful erase cycle, the Status Register can be read and indicates that the

device is busy. For faster throughput, it is recommended that the Status Register be polled to determine if the

device has finished erasing. At some point before the erase cycle completes, the WEL bit in the Status Register is

reset to the logical “0” state.

CS

0

1

2

3

4

5

6

7

SCK

SI

OPCODE

C

MSB

C

HIGH-IMPEDANCE

SO

Figure 8-5. Chip Erase Timing

8.5

Program/Erase Suspend (75h)

The Program/Erase Suspend command allows an in-progress program or erase operation to be suspended so that

other device operations can be performed. For example, by suspending an erase operation to a particular block,

the system can perform functions such as a program or read to a different block.

Chip Erase cannot be suspended. The Program/Erase Suspend command is ignored if it is issued during a Chip

Erase.A program operation can be performed while an erase operation is suspended, but the program operation

cannot be suspended while an erase operation is currently suspended.

Other device operations, such as a Read Status Register, can also be performed while a program or erase

operation is suspended.

Since the need to suspend a program or erase operation is immediate, the Write Enable command does not need

to be issued prior to the Program/Erase Suspend command being issued. Thus, the Program/Erase Suspend

command operates independently of the state of the WEL bit in the Status Register.

To perform a Program/Erase Suspend, the CS pin must first be asserted, and the 75h opcode must be clocked into

the device. No address bytes need to be clocked into the device, and any data clocked in after the opcode is

ignored. When the CS pin is deasserted, the program or erase operation currently in progress is suspended. The

Suspend (E_SUS or P_SUS) bits in the Write Status Register are set to the logical “1” state to indicate that the

program or erase operation has been suspended. Also, the RDY/BSY bit in the Status Register indicates that the

device is ready for another operation. The complete opcode must be clocked into the device before the CS pin is

AT25SF321B

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24

deasserted, and the CS pin must be deasserted on a byte boundary (multiples of eight bits); otherwise, no suspend

operation is performed.

If a read operation is attempted to a suspended area (page for programming or block for erasing), the device

outputs undefined data. Thus, when performing a Read Array operation to an unsuspended area, and the device's

internal address counter increments and crosses into the suspended area, the device starts outputting undefined

data until the internal address counter crosses to an unsuspended area.

A program operation is not allowed to a block that has been erase suspended. If a program operation is attempted

to an erase suspended block, then the program operation aborts, and the WEL bit in the Status Register is reset to

a logical “0” state. Likewise, an erase operation is not allowed to a block that included the page that has been

program suspended. If attempted, the erase operation aborts, and the WEL bit in the Status Register is reset to a

logical “0” state.

If an attempt is made to perform an operation that is not allowed during a program or erase suspend, such as a

Write Status Register operation, the device ignores the opcode, and no operation is performed. The state of the

WEL bit in the Status Register is not affected.

Note: Repeated suspend/resume sequences might significantly impact progress of the erase or program

operation. To ensure timely completion of the erase or program operation, limit the number of suspend/resume

sequences during the same erase or program operation; alternatively, provide sufficient time (up to 3.5 ms for a

4 kB erase; up to 55 ms for a 64 kB erase) after a resume operation to allow the erase or program operation to

complete.

CS

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

SCK

SI

OPCODE

t_SUS

0

1

0

1

0

1

Instruction During Supend

Figure 8-6. Erase/Program Suspend Timing

8.6

Program/Erase Resume (7Ah)

The Program/Erase Resume command allows a suspended program or erase operation to be resumed and

continue programming a Flash page or erasing a Flash memory block where it left off. The Program/Erase Resume

instruction is accepted by the device only if the E_SUS or P_SUS bit in the Write Status Register is 1, and the

RDY/BSY bit is 0. If the E_SUS and P_SUS bits are 0, or the RDY/BSY bit is 1, the Program/Erase Resume

command is ignored by the device. As with the Program/Erase Suspend command, the Write Enable command

does not need to be issued before to the Program/Erase Resume command is issued. Thus, the Program/Erase

Resume command operates independently of the state of the WEL bit in the Status Register.

To perform Program/Erase Resume, the CS pin must first be asserted, and opcode 7Ah must be clocked into the

device.

No address bytes need to be clocked into the device, and any data clocked in after the opcode is ignored. When

the CS pin is deasserted, the program or erase operation currently suspended resumes. The E_SUS or P_SUS bit

in the Status Register is reset back to the logical “0” state to indicate the program or erase operation is no longer

suspended. Also, the RDY/BSY bit in the Status Register indicates that the device is busy performing a program or

erase operation. The complete opcode must be clocked into the device before the CS pin is deasserted, and the

CS pin must be deasserted on a byte boundary (multiples of eight bits); otherwise, no resume operation is

performed.

AT25SF321B

DS-AT25SF321B–179E–06-2020

25

During a simultaneous Erase Suspend/Program Suspend condition, issuing the Program/Erase Resume command

results in the program operation resuming first. After the program operation has been completed, the

Program/Erase Resume command must be issued again for the erase operation to be resumed.

While the device is busy resuming a program or erase operation, any attempts at issuing the Program/Erase

Suspend command are ignored. Thus, if a resumed program or erase operation needs to be subsequently

suspended again, the system must either wait before issuing the Program/Erase Suspend command, or it must

check the status of the RDY/BSY bit or the E_SUS or P_SUS bit in the Status Register to determine if the

previously suspended program or erase operation has resumed.

ꢅꢁ

ꢓ

ꢋ

ꢑ

ꢊ

ꢜ

ꢉ

ꢛ

ꢈ

ꢁꢅꢚ

ꢁꢏ

ꢃꢄꢅꢃꢆꢇ

0

ꢀꢁꢂ

1

ꢋ

1

0

1

0

ꢘꢏꢙꢘꢒꢏꢀꢄꢇꢆꢌꢔꢅꢇ

ꢁꢃ

Figure 8-7. Erase/Program Resume Command Timing

AT25SF321B

DS-AT25SF321B–179E–06-2020

26

9.

Protection Commands and Features

9.1

Write Enable (06h)

The Write Enable command sets the Write Enable Latch (WEL) bit in the Status Register to a logical “1” state. The

WEL bit must be set before a Byte/Page Program, Erase, Program Security Register Pages, Erase Security

Register Pages or Write Status Register command can be executed. This makes the issuance of these commands

a two step process, thus reducing the chances of a command being accidentally or erroneously executed. If the

WEL bit in the Status Register is not set prior to the issuance of one of these commands, the command is not

executed.

To issue the Write Enable command, the CS pin must first be asserted, and the opcode of 06h must be clocked

into the device. No address bytes need to be clocked into the device, and any data clocked in after the opcode is

ignored. When the CS pin is deasserted, the WEL bit in the Status Register is set to a logical “1”. The complete

opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an

byte boundary (multiples of eight bits); otherwise, the device aborts the operation, and the WEL bit state does not

change.

CS

0

1

2

3

4

5

6

7

SCK

SI

OPCODE

0

MSB

0

1

0

HIGH-IMPEDANCE

SO

Figure 9-1. Write Enable Timing

9.2

Write Disable (04h)

The Write Disable command resets the Write Enable Latch (WEL) bit in the Status Register to the logical “0” state.

With the WEL bit reset, all Byte/Page Program, Erase, Program Security Register Page, and Write Status Register

commands are not executed. Other conditions can also cause the WEL bit to be reset; for more details, see the

WEL bit section of the Status Register description (Section 9.1).

To issue this command, the CS pin must be asserted first, and the opcode of 04h must be clocked into the device.

No address bytes need to be clocked into the device, and any data clocked in after the opcode is ignored. When

the CS pin is deasserted, the WEL bit in the Status Register is reset to a logical “0”. The complete opcode must be

clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an byte boundary

(multiples of eight bits); otherwise, the device aborts the operation, and the WEL bit state does not change.

CS

0

1

2

3

4

5

6

7

SCK

SI

OPCODE

0

MSB

0

1

0

HIGH-IMPEDANCE

SO

Figure 9-2. Write Disable Timing

AT25SF321B

DS-AT25SF321B–179E–06-2020

27

9.3

Non-Volatile Protection

The device can be software-protected against erroneous or malicious program or erase operations by using the

Non-Volatile Protection feature. Non-Volatile Protection can be enabled or disabled by using the Write Status

Register command to change the value of the Protection (CMP, BP4, BP3, BP2, BP1, BP0) bits in the Status

Register. Table 9-1 outlines the states of the Protection bits and the associated protection area.

Table 9-1. Memory Array with CMP = 0

Protection Bits

Memory Content

BP4

X

0

BP3

X

0

BP2

0

1

0

1

0

1

0

1

BP1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

BP0

0

Address Range

None

Portion

None

1

3F0000h-3FFFFFh

3E0000h-3FFFFFh

3C0000h-3FFFFFh

380000h-3FFFFFh

300000h-3FFFFFh

200000h-3FFFFFh

000000h-00FFFFh

000000h-01FFFFh

000000h-03FFFFh

000000h-07FFFFh

000000h-0FFFFFh

000000h-1FFFFFh

000000h-3FFFFFh

3FF000h-3FFFFFh

3FE000h-3FFFFFh

3FC000h-3FFFFFh

3F8000h-3FFFFFh

000000h-000FFFh

000000h-001FFFh

000000h-003FFFh

000000h-007FFFh

Upper 1/64

Upper 1/32

Upper 1/16

Upper 1/8

Upper 1/4

Upper 1/2

Lower 1/64

Lower 1/32

Lower 1/16

Lower 1/8

Lower 1/4

Lower 1/2

ALL

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

1

X

0

1

Upper 1/512

Upper 1/256

Upper 1/128

Upper 1/64

Lower 1/512

Lower 1/256

Lower 1/128

Lower 1/64

1

0

1

0

1

0

X

0

1

0

1

0

1

X

0

1

AT25SF321B

DS-AT25SF321B–179E–06-2020

28

Table 9-2. Memory Array Protection with CMP = 1

Protection Bits

Memory Content

BP4

X

0

BP3

X

0

BP2

0

1

0

1

0

1

0

1

BP1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

BP0

0

Address Range

000000h-3FFFFFh

000000h-3EFFFFh

000000h-3DFFFFh

000000h-3BFFFFh

000000h-37FFFFh

000000h-2FFFFFh

000000h-1FFFFFh

010000h-3FFFFFh

020000h-3FFFFFh

040000h-3FFFFFh

080000h-3FFFFFh

100000h-3FFFFFh

200000h-3FFFFFh

NONE

Portion

All

1

Lower 63/64

Lower 31/32

Lower 15/16

Lower 7/8

0

1

0

1

Lower 3/4

0

Lower 1/2

0

1

Upper 63/64

Upper 31/32

Upper 15/16

Upper 7/8

0

1

0

1

0

1

0

1

Upper 3/4

0

1

0

Upper 1/2

X

1

X

0

1

NONE

1

000000h-3FEFFFh

000000h-3FDFFFh

000000h-3FBFFFh

000000h-3F7FFFh

001000h-3FFFFFh

002000h-3FFFFFh

004000h-3FFFFFh

008000h-3FFFFFh

Lower 1023/1024

Lower 511/512

Lower 255/256

Lower 127/128

Upper 1023/1024

Upper 511/512

Upper 255/256

Upper 127/128

1

0

1

0

1

0

X

0

1

0

1

0

1

X

0

1

As a safeguard against accidental or erroneous protecting or unprotecting of the memory array, the Protection can

be locked from updates by using the WP pin (see “Protected States and the Write Protect Pin”, on page 29, for

more details).

9.4

Protected States and the Write Protect Pin

The WP pin is not linked to the memory array itself and has no direct effect on the protection status of the memory

array. Instead, the WP pin, controls the hardware locking mechanism of the device.

If the WP pin is permanently connected to GND, then the protection bits cannot be changed.

AT25SF321B

DS-AT25SF321B–179E–06-2020

29

9.5

Enable Reset (66h) and Reset Device (99h)

Because of the small package and the limitation on the number of pins, the AT25SF161B provides a software

Reset instruction instead of a dedicated RESET pin. Once the software Reset instruction is accepted, any on-going

internal operations are terminated, and the device returns to its default power-on state and loses all the current

volatile settings, including the Volatile Status Register bits, Write Enable Latch (WEL) status, Program/Erase

Suspend status, Continuous Read Mode bit setting (M7-M0), and Wrap Bit setting (W6-W4).

To avoid accidental reset, the Enable Reset and Reset Device instructions must be issued in sequence. Any other

commands other than Reset (99h) after the Enable Reset command (66h) disables the Reset Enable state. A new

sequence of Enable Reset and Reset Device is needed to reset the device. Once the Reset command is accepted

by the device, the device takes approximately 30 µs to reset. During this period, no command is accepted.

The Enable Reset and Reset Device instruction sequence are shown in Figure 9-3.

Data corruption can happen if there is an on-going or suspended internal Erase or Program operation when the

Reset command sequence is accepted by the device. Check the BUSY bit and the E_SUS and P_SUS bits in the

Status Register before issuing the Reset command sequence.

CS

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

SCK

SI

OPCODE

1

0

ꢋ

1

0

1

0

1

0

1

0

Figure 9-3. Enable Reset (66h) and Reset Device (99h) Command Timing (SPI Mode)

AT25SF321B

DS-AT25SF321B–179E–06-2020

30

10. Security Register Commands

The device contains three extra Security Registers pages, that can be used for unique device serialization, system-

level Electronic Serial Number (ESN) storage, locked key storage, etc. The Security Registers are independent of

the main Flash memory.

Each page of the Security Register can be erased and programmed independently. Each page can also be

independently locked to prevent further changes.

10.1 Read Unique ID Number (4Bh)

The Read Unique ID Number instruction accesses a factory-set, read-only 64-bit number that is unique to each

AT25SF321B device. The ID number can be used in conjunction with user software methods to help prevent

copying or cloning of a system. The Read Unique ID instruction is initiated by driving the CS pin low and shifting

the instruction code 4Bh, followed by four dummy byte clock cycles. After this, the 64-bit ID is shifted out on the

falling edge of SCLK, as shown in Figure 10-1.

CS

19

Mode

13 14 15

20 21 22

0

1

2

3

4

5

6

7

8

9

10 11

16 17 18

23

3

0

12

SCK

SI

Dummy Byte

Instruction

4BH

1

Dummy Byte

2

HIGH-IMPEDANCE

SO

CS

_

26

Dummy Byte 3

23

25

27 28

103

102

29 30

33

40

24

34

36 37 38 39

100 101

Mode3

Mode0

31 32

35

41

SCK

Dummy Byte

4

SI

HIGH-IMPEDANCE

_

SO

1

2

63 62

MSB

0

bit Unique

Serial Number

64-

Figure 10-1. Read Unique ID Timing (SPI Mode)

AT25SF321B

DS-AT25SF321B–179E–06-2020

31

10.2 Erase Security Registers (44h)

Before an erase Security Register Page command can be started, the Write Enable command must have been

previously issued to the device to set the WEL bit of the Status Register to a logical “1” state.

To perform an Erase Security Register Page command, the CS pin must be asserted first, and the opcode 44h

must be clocked into the device. After the opcode has been clocked in, the three address bytes specifying the

Security Register Page to be erased must be clocked in. When the CS pin is deasserted, the device erases the

appropriate page. The erasing of the page is internally self-timed and takes place in a time of t_PP.

Since the Erase Security Register Page command erases a region of bytes, the lower-order address bits do not

need to be decoded by the device. Thus, address bits A7-A0 are ignored by the device. Despite the lower-order

address bits not being decoded by the device, the complete three address bytes must be clocked into the device

before the CS pin is deasserted, and the CS pin must be deasserted right after the last address bit (A0); otherwise,

the device aborts the operation, and no erase operation is performed.

While the device is executing a successful erase cycle, the Status Register can be read and indicates that the

device is busy. For faster throughput, it is recommended that the Status Register be polled (rather than waiting the

t_PPtime to determine if the device has finished erasing). At some point before the erase cycle completes, the

RDY/BSY bit in the Status Register is reset to the logical “0” state.

The WEL bit in the Status Register is reset to the logical “0” state if: the erase cycle aborts due to an incomplete

address being sent, the CS pin being deasserted on uneven byte boundaries, or because a memory location within

the region to be erased is protected.

The Security Registers Lock Bits (LB3-LB1) in the Status Register can be used to OTP protect the security

registers. Once a Lock Bit is set to 1, the corresponding Security Register is permanently locked. The Erase

Security Register Page instruction is ignored for Security Registers with their Lock Bit set.

Table 10-1. Security Register Addresses for Erase Security Register Page Command

Address

A23-A16

00h

A15-A12

A11-A8

0h

A7-A0

Security Register 1

Security Register 2

Security Register 3

1h

2h

3h

Don’t Care

00h

0h

00h

0h

CS

SCK

SI

0

1

2

3

4

5

6

7

8

9

29 30 31

OPCODE

24-BIT ADDRESS

0

MSB

1

0

1

0

A

Figure 10-2. Erase Security Register Page

AT25SF321B

DS-AT25SF321B–179E–06-2020

32

10.3 Program Security Registers (42h)

The Program Security Registers command uses the internal 256-byte buffer for processing. Thus, the contents of

the buffer are altered from their previous state when this command is issued.

The Security Registers can be programmed in a similar fashion to the Program Array operation up to the maximum

clock frequency specified by f_CLK. Before a Program Security Registers command can be started, the Write Enable

command must have been previously issued to the device (see “Write Enable (06h)”, on page 27) to set the Write

Enable Latch (WEL) bit of the Status Register to a logical “1” state. To program the Security Registers, the CS pin

must first be asserted, and the opcode of 42h must be clocked into the device. After the opcode has been clocked

in, the three address bytes must be clocked in to specify the starting address location of the first byte to program

within the Security Register.

CS

0

1

2

3

4

5

6

7

8

9

29 30 31 32 33 34 35 36 37 38 39

SCK

SI

OPCODE

ADDRESS BITS A23-A0

DATA IN BYTE 1

DATA IN BYTE n

0

MSB

1

0

1

0

A

D

MSB

D

MSB

D

MSB

HIGH-IMPEDANCE

SO

Figure 10-3. Program Security Registers

Table 10-2. Security Register Addresses for Program Security Registers Command

Address

A23-A16

00h

A15-A12

A11-A8

A7-A0

Security Register 1

Security Register 2

Security Register 3

1h

2h

3h

0h

Byte Address

00h

AT25SF321B

DS-AT25SF321B–179E–06-2020

33

10.4 Read Security Registers (48h)

The Security Register can be sequentially read in a similar fashion to the Read Array operation up to the maximum

clock frequency specified by f_CLK. To read the Security Register, the CS pin must first be asserted and the opcode

of 48h must be clocked into the device. After the opcode has been clocked in, the three address bytes must be

clocked in to specify the starting address location of the first byte to read within the Security Register. Following the

three address bytes, one dummy byte must be clocked into the device before data can be output.

After the three address bytes and the dummy byte have been clocked in, additional clock cycles result in the

Security Register data being output on the SO pin. When the last byte (0003FFh) of the Security Register has been

read, the device continues reading back at the beginning of the register (000000h). No delays are incurred when

wrapping around from the end of the register to the beginning of the register.

Deasserting the CS pin terminates the read operation and puts the SO pin into a high-impedance state. The CS pin

can be deasserted at any time and does not require that a full byte of data be read.

Table 10-3. Security Register Addresses for Read Security Registers Command

Address

A23-A16

00h

A15-A12

A11-A8

0h

A7-A0

Security Register 1

Security Register 2

Security Register 3

1h

2h

3h

Byte Address

00h

0h

00h

0h

&6

6&.

6,

ꢃ

ꢂ

ꢀ

ꢁ

ꢇ

ꢆ

ꢄ

ꢅ

ꢉ

ꢈ

ꢂꢃ ꢂꢂ ꢂꢀ

ꢀꢈ ꢁꢃ ꢁꢂ ꢁꢀ ꢁꢁ ꢁꢇ ꢁꢆ ꢁꢄ

23&2'(

$''5(66ꢊ%,76ꢊ$ꢀꢁꢋ$ꢃ

'21ꢌ7ꢊ&$5(

ꢃ

06%

ꢂ

ꢃ

ꢂ

ꢃ

$

06%

$

;

06%

'$7$ꢊ%<7(ꢊꢂ

+,*+ꢋ,03('$1&(

'

06%

'

06%

'

62

Figure 10-4. Read Security Registers

AT25SF321B

DS-AT25SF321B–179E–06-2020

34

11. Status Register Commands

11.1 Read Status Register (05h, 35h, and 15h)

The Status Register can be read to determine the device's ready/busy status, as well as the status of many other

functions, such as Block Protection. The Status Register can be read at any time, including during an internally

self-timed program or erase operation.

To read Status Register Byte 1, the CS pin must first be asserted and the opcode of 05h must be clocked into the

device. After the opcode has been clocked in, the device begins outputting Status Register Byte 1 data on the SO

pin during every subsequent clock cycle. After the last bit (0) of Status Register Byte 1 has been clocked out, the

sequence repeats itself, starting again with bit 7, as long as the CS pin remains asserted and the clock pin is being

pulsed. The data in the Status Register is constantly being updated, so each repeating sequence outputs new

data. Deasserting the CS pin terminates the Read Status Register operation and puts the SO pin into a high-

impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read.

To read Status Register Byte 2, the CS pin must first be asserted, and the opcode of 35h must be clocked into the

device. After the opcode has been clocked in, the device begins outputting Status Register Byte 2 data on the SO

pin during every subsequent clock cycle. After the last bit (0) of Status Register Byte 2 has been clocked out, the

sequence repeats itself starting again with bit 7 as long as the CS pin remains asserted and the clock pin is being

pulsed. The data in the Status Register is constantly being updated, so each repeating sequence outputs new

data. Deasserting the CS pin terminates the Read Status Register operation and puts the SO pin into a high-

impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read.

Table 11-1. Status Register 1 Bit Assignments

Bit¹

Mnemonic

Name

Type²

Description

7

SRP0

Status Register Protection

bit 0

R/W

See Table 11-4 on Status Register Protection.

6

5

4

3

2

1

BP4

BP3

BP2

BP1

BP0

WEL

Block Protection bit 4

Block Protection bit 3

Block Protection bit 2

Block Protection bit 1

Block Protection bit 0

Write Enable Latch Status

R/W

R

See Table 9-1 and Table 9-2 on Non-Volatile

Protection.

0

1

0

1

Device is not Write Enabled (default).

Device is Write Enabled.

0

RDY/BSY

Ready/Busy Status

R

Device is ready.

Device is busy with an internal operation.

1. Only bits designated as R/W can be modified when using the Write Status Register command. Bits designated as R cannot be modified.

2. R/W = Readable and writable; R = Readable only.

AT25SF321B

DS-AT25SF321B–179E–06-2020

35

&6

6&.

6,

ꢃ

ꢂ

ꢀ

ꢁ

ꢇ

ꢆ

ꢄ

ꢅ

ꢉ

ꢈ

ꢂꢃ ꢂꢂ ꢂꢀ ꢂꢁ ꢂꢇ ꢂꢆ ꢂꢄ ꢂꢅ ꢂꢉ ꢂꢈ ꢀꢃ ꢀꢂ ꢀꢀ ꢀꢁ ꢀꢇ ꢀꢆ ꢀꢄ ꢀꢅ ꢀꢉ ꢀꢈ ꢁꢃ

OPCODE

&

06%

&

STATUS REGISTER

BYTE 1

STATUS REGISTER

BYTE 1

STATUS REGISTER

BYTE 1

HIGH-IMPEDANCE

'

06%

'

06%

'

06%

'

62

Figure 11-1. Read Status Register 1

Table 11-2. Status Register 2 Bit Assignments

Bit⁽¹⁾

Name

Type⁽²⁾

Description

0

1

Erase operation is not suspended (default).

Erase operation is suspended.

7

E_SUS Erase Suspend Status

R

Complement Block

Protection

6

5

CMP

R/W

0

See table on Block Protection.

0

1

0

1

0

1

0

1

0

1

Security Register page-3 is not locked (default).

Security Register page-3 cannot be erased/programmed.

Security Register page-2 is not locked (default).

Security Register page-2 cannot be erased/programmed.

Security Register page-1 is not locked (default).

Security Register page-1 cannot be erased/programmed.

Program operation is not suspended (default).

Program operation is suspended.

LB3

LB2

Lock Security Register 3

Lock Security Register 2

Lock Security Register 1

4

3

2

R/W

R

LB1

Program Suspend

Status

P_SUS

HOLD and WP function normally (default).

HOLD and WP are I/O pins.

1

0

QE

Quad Enable

R/W

Status Register Protect

bit 1

SRP1

See Table 11-4 on Status Register Protection.

1. Only bits designated as R/W can be modified when using the Write Status Register command. Bits designated as R cannot be modified.

2. R/W = Readable and writable; R = Readable only.

AT25SF321B

DS-AT25SF321B–179E–06-2020

36

CS

SCK

SI

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

OPCODE

0

1

0

1

0

1

MSB

STATUS REGISTER

BYTE 2

STATUS REGISTER

BYTE 2

STATUS REGISTER

BYTE 2

HIGH-IMPEDANCE

D

SO

MSB

Figure 11-2. Read Status Register 2

Table 11-3 shows the bit assignments for Status Register 3. This register can be read using the Status Register 3

Read command (15h), and written using the Status Register 3 Write command (11h).

Table 11-3. Status Register 3 Bit Assignments

Bit⁽¹⁾

Mnemonic

Name

Reserved

Type⁽²⁾

Description

7

Res

R/W

0

Reserved bit.

Drive level. The DRV1 and DRV0 bits are used to determine

the output driver strength during read operations. A setting

of 2’b11 allows the drive strength to be set by hardware

based on the VCC level. Four drive settings are supported.

6:5

DRV[1:0]

Drive Strength

R/W

11 This field is encoded as follows:

11: Auto (7 pF based on VCC level)

10: 50% (15 pF)

01: 75% (22 pF)

00: 100% (30 pF)

4:0

Res

Reserved

R/W

0

Reserved bit.

1. Only bits designated as R/W can be modified when using the Write Status Register command. Bits designated as R cannot be modified.

2. R/W = Readable and writable; R = Readable only.

11.1.1 SRP1, SRP0 Bits

The SRP1 and SRP0 bits determine if the Status Register can be modified. The state of the WP pin, along with the

values of the SRP1 and SRP0, determine if the device is software-protected, hardware-protected, or permanently

protected, as shown in Table 11-4.

Table 11-4. Status Register Protection Table

SRP1

SRP0

WP

Status Register

Software Protected

Hardware Protected

Description

The Status Register can be written to after a Write Enable

instruction, WEL = 1.(Factory Default)

0

X

0

1

0

1

WP = 0, the Status Register is locked and cannot be written.

Hardware

Unprotected

WP = 1, the Status Register is unlocked and can be written

to after a Write Enable instruction, WEL = 1.

Power Supply Lock-

Down

Status Register is protected and cannot be written to again

until the next Power-Down, Power-Up cycle.

1

0

X

1. When SRP1, SRP0 = (1, 0), a Power-Down, Power-Up cycle changes SRP1, SRP0 to the (0, 0) state.

AT25SF321B

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11.1.2 CMP, BP4, BP3, BP2, BP1, BP0 Bits

The CMP, BP4, BP3, BP2, BP1, and BP0 bits control which portions of the array are protected from erase and

program operations (see Table 9-1 and Table 9-2).

The CMP bit complements the effect of the other bits.

The BP4 bit selects between large and small block size protection.

The BP3 bit selects between top of the array or bottom of the array protection.

The BP2, BP1, and BP0 bits determine how much of the array is protected.

11.1.3 WEL Bit

The WEL bit indicates the current status of the internal Write Enable Latch. When the WEL bit is in the logical “0”

state, the device does not accept any Byte/Page Program, erase, Program Security Register, Erase Security

Register, or Write Status Register commands. The WEL bit defaults to the logical “0” state after a device power-up

or reset operation. Also, the WEL bit is reset to the logical “0” state automatically under the following conditions:

•

Write Disable operation completes successfully.

Write Status Register operation completes successfully or aborts.

Program Security Register operation completes successfully or aborts.

Erase Security Register operation completes successfully or aborts.

Byte/Page Program operation completes successfully or aborts.

Block Erase operation completes successfully or aborts.

Chip Erase operation completes successfully or aborts.

If the WEL bit is in the logical “1” state, it is not reset to a logical “0” if an operation aborts because of an incomplete

or unrecognized opcode being clocked into the device before the CS pin is deasserted. For the WEL bit to be reset

when an operation aborts prematurely, the entire opcode for a Byte/Page Program, erase, Program Security

Register, Erase Security Register, or Write Status Register command must have been clocked into the device.

11.1.4 RDY/BSY Bit

The RDY/BSY bit is used to determine whether or not an internal operation, such as a program or erase, is in

progress. To poll the RDY/BSY bit to detect the completion of a program or erase cycle, new Status Register data

must be continually clocked out of the device until the state of the RDY/BSY bit changes from a logical “1” to a

logical “0”.

11.1.5 LB3, LB2, LB1 Bits

The LB3, LB2, and LB1 bits are used to determine if any of the three Security Register pages are locked.

The LB3 bit is in the logical “1” state if Security Register page-2 is locked and cannot be erased or programmed.

The LB2 bit is in the logical “1” state if Security Register page-1 is locked and cannot be erased or programmed.

The LB1 bit is in the logical “1” state if Security Register page-0 is locked and cannot be erased or programmed.

11.1.6 E_SUS Bit

This bit is set and cleared by hardware and indicates the status of an erase operation. This bit is encoded as

follows:

0: Erase operation is not suspended (default).

1: Erase operation is suspended.

Hardware clears this bit once the condition that caused the erase suspend operation has been removed. Hardware

typically sets this bit when a Program/Erase Suspend (75h) command is executed, and clears the bit when a

Program/Erase Resume (7Ah) command is executed.

AT25SF321B

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38

11.1.7 P_SUS Bit

This bit is set and cleared by hardware and indicates the status of an program operation. This bit is encoded as

follows:

0: Program operation is not suspended (default).

1: Program operation is suspended.

Hardware clears this bit once the condition that caused the program suspend operation has been removed.

Hardware typically sets this bit when a Program/Erase Suspend (75h) command is executed, and clears the bit

when a Program/Erase Resume (7Ah) command is executed.

11.1.8 QE Bit

The QE bit determines if the device is in the Quad Enabled mode. If it is in the logical “1” state, the HOLD and WP

pins functions as input/output pins similar to the SI and SO. If it is in the logical “0” state, the HOLD pin functions as

an input only, and the WP pin functions as an input only.

11.2 Write Status Register (01h)

The Write Status Register command modifies the Block Protection, Security Register Lock-down, Quad Enable,

and Status Register Protection. Before the Write Status Register command can be issued, the Write Enable

command must have been previously issued to set the WEL bit in the Status Register to a logical “1”.

The CS pin must be driven high after the eighth bit of the data byte has been latched in. If not, the Write Status

Register instruction is not executed. As soon as the CS pin is driven high, the self-timed Write Status Register

cycle is initiated.

While the Write Status Register cycle is in progress, the Status Register can be read to check the value of the

Write in Progress (WIP) bit. The WIP bit is 1 during the self-timed Write Status Register cycle, and 0 when it is

completed. When the cycle is completed, the Write Enable Latch is reset.

The Write Status Register instruction allows the user to change the values of the Block Protect (BP4, BP3, BP2,

BP1, BP0) bits, to define the size of the area that is to be treated as read-only. The Write Status Register

instruction also allows the user to set or reset the Status Register Protect (SRP1 and SRP0) bits in accordance

with the Write Protect (WP) pin.

The Status Register Protect (SRP1 and SRP0) bits and WP pin allow the device to be put in the hardware

protected mode. The Write Status Register instruction is not executed once the hardware protected mode is

entered.

CS

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

SCLK

SI

Status Register in

Instruction

01H or 31H or 11H

7

6

5

4

3

2

1

0

MSB

HIGH-IMPEDANCE

SO

Figure 11-3. Write Status Register

AT25SF321B

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39

.

Table 11-5. Write Status Register 1

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SRP0

BP4

BP3

BP2

BP1

BP0

WEL

RDY/BSY

Table 11-6.Write Status Register 2

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

E_SUS

CMP

LB3

LB2

LB1

P_SUS

QE

SRP1

Table 11-7.Write Status Register 3

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

DRV1

DRV0

Reserved

11.3 Write Enable for Volatile Status Register (50h)

The non-volatile Status Register bits can be written to as volatile bits. During power up reset, the non-volatile

Status Register bits are copied to a volatile version of the Status Register that is used during device operation. This

gives more flexibility to change the system configuration and memory protection schemes quickly without waiting

for the typical non-volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits.

To write the volatile version of the Status Register bits, the Write Enable for Volatile Status Register (50h)

instruction must be issued prior to each Write Status Registers (01h) instruction. The Write Enable for Volatile

Status Register instruction does not set the Write Enable Latch bit. It is valid only for the next Write Status

Registers instruction, to change the volatile Status Register bit values.

CS

0

1

2

3

4

5

6

7

SCK

SI

OPCODE

0

MSB

1

0

1

0

HIGH-IMPEDANCE

SO

Figure 11-4. Write Enable for Volatile Status Register

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12. Other Commands and Functions

The AT25SF321B supports three different commands to access device identification that indicates the

manufacturer, device type, and memory density. The returned data bytes provide the information shown in Table

12-1.

Table 12-1. Manufacturer and Device ID Information

Dummy

Bytes

Manufacturer ID

(Byte #1)

Device ID

(Byte #2)

Device ID

(Byte #3)

Instruction

Opcode

Read Manufacturer and Device ID

Read ID (Legacy Command)

Read ID (Dual I/O)

9Fh

90h

92h

94h

0

3

1Fh

87h

01h

15h

Read ID (Quad I/O)

Resume from Deep Power-Down and

Read Device ID

ABh

3

15h

12.1 Read Manufacturer and Device ID (9Fh)

Identification information can be read from the device to enable systems to electronically query and identify the

device.

Since not all Flash devices are capable of operating at very high clock frequencies, design applications to read the

identification information from the devices at a reasonably low clock frequency to ensure all devices used in the

application can be identified properly. Once the identification process is complete, the application can increase the

clock frequency to accommodate specific Flash devices that are capable of operating at the higher clock

frequencies.

To read the identification information, the CS pin must first be asserted and the opcode of 9Fh must be clocked into

the device. After the opcode has been clocked in, the device begins outputting the identification data on the SO pin

during the subsequent clock cycles. The first byte output is the Manufacturer ID, followed by two bytes of Device ID

information. Deasserting the CS pin terminates the Manufacturer and Device ID read operation and puts the SO

pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of

data be read.

Table 12-2. Manufacturer and Device ID Information

Byte Number

Data Type

Value

1Fh

1

2

3

Manufacturer ID

Device ID (Part 1)

Device ID (Part 2)

87h

01h

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Table 12-3. Manufacturer and Device ID Details

Hex

Value

Data Type

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Details

JEDEC Assigned Code

JEDEC Code:00011111

(1Fh for Adesto)

Manufacturer ID

1Fh

87h

0

1

0

1

Family Code

Density Code

Family Code:100

(AT25SFxxx series)

Density Code:00111

(32-Mbit)

Device ID (Part 1)

Device ID (Part 2)

1

0

1

Sub Code

0

Product Version Code

Sub Code: 000 (Standard

series)

Product Version: 00001

01h

0

CS

SCK

SI

0

6

7

8

14 15 16

22 23 24

30 31 32

OPCODE

9Fh

HIGH-IMPEDANCE

1Fh

87h

01h

SO

MANUFACTURER ID

DEVICE ID

BYTE1

DEVICE ID

BYTE2

Note: Each transition

shown for SI and SO represents one byte (8 bits)

Figure 12-1. Read Manufacturer and Device ID

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12.2 Read ID (Legacy Command) (90h)

Identification information can be read from the device to enable systems to electronically query and identify the

device. The JEDEC standard “Read Manufacturer and Device ID (9Fh)” method, described in Section 12.1, is

preferred; however, the legacy Read ID command is supported on the AT25SF321B to enable backwards

compatibility to previous generation devices.

To read the identification information, the CS pin must first be asserted, and the opcode 90h must be clocked into

the device, followed by three dummy bytes. After the opcode has been clocked, in followed by three dummy bytes,

the device begins outputting the identification data on the SO pin during the subsequent clock cycles. The first byte

output is the Manufacturer ID of 1Fh, followed by a single byte of data representing a device code 15h. After the

device code is output, the sequence of bytes repeats.

Deasserting the CS pin terminates the Read ID operation and puts the SO pin into a high-impedance state. The CS

pin can be deasserted at any time and does not require that a full byte of data read.

CS

0

1

2

3

4

5

6

7

29 30 31 32 33 34 35 36 37 38 39

SCK

SI

OPCODE

3 DUMMY BYTES

DEVICE ID

1

MSB

0

1

0

X

MANUFACTURE ID + DEVICE ID

HIGH-IMPEDANCE

D

SO

MSB

Figure 12-2. Read ID (Legacy Command)

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43

12.3 Dual I/O Read Manufacture ID/ Device ID (92h)

The Dual I/O Read Manufacturer/Device ID instruction is an alternative to the Release from Power-Down/Device

ID instruction that provides both the JEDEC-assigned Manufacturer ID and the specific Device ID by Dual I/O.

The instruction is initiated by driving the CS pin low and shifting the instruction code 92h, followed by a 24-bit

address (A23 - A0) of 000000h. If the 24-bit address is initially set to 000001h, the Device ID is read first.

CS

0

2

4

5

6

7

12

15

21

1

3

8

9

10 11

13 14

16 17 18 19 20

22 23

SCK

Instruction

92H

SI

4

2

0

6

4

2

3

0

1

6

0

6

2

0

4

5

6

(IO0)

HIGH-IMPEDANCE

SO

(IO1)

7

5

7

3

1

7

5

3

1

7

5

1

3

A23-16

A15-8

A7-0

Dummy

CS

23 24 25 26

28 29 30 31 32

39

42 43 44 45 46 47

27

40 41

SCK

SI

HIGH-IMPEDANCE

6

7

2

6

7

0

4

5

2

4

5

6

7

4

5

0

6

7

2

3

4

5

0

1

(IO0)

2

0

1

MFR and Device ID

(repeat)

SO

( IO1)

3

1

3

1

MFR ID (repeat)

Device ID (repeat)

MFR ID

Device ID

Figure 12-3. Dual I/O Read Manufacture ID/ Device ID Timing

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44

12.4 Quad I/O Read Manufacture ID / Device ID (94h)

The Quad I/O Read Manufacturer/Device ID instruction is an alternative to the Release from Power-Down/Device

ID instruction that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by quad I/O.

The instruction is initiated by driving the CS pin low and shifting the instruction code 94h, followed by a 24-bit

address (A23 - A0) of 000000h and four dummy clocks. If the 24-bit address is initially set to 000001h, the Device

ID is read out first.

CS

0

2

4

5

6

7

12

4

15

21

0

1

3

9

11

13

16

20

4

8

10

4

14

17 18 19

22 23

SCK

Instruction

94H

SI

0

4

0

(IO₀)

High_Z

SO

5

6

1

2

5

6

1

2

5

6

1

2

1

2

5

6

1

2

5

6

1

2

5

6

(IO₁)

WP

(IO₂)

High_Z

HOLD

(IO₃)

7

3

7

3

7

3

7

3

7

3

7

Device ID

MFR ID

dummy

A7-0

dummy

A23-16

A15-8

CS

23 24 25 26

28 29 30 31

27

SCK

SI

4

0

4

0

(IO₀)

SO

5

6

1

2

5

6

1

2

5

6

1

2

5

6

(IO₁)

2

WP

(IO₂)

7

3

7

3

7

3

7

HOLD

(IO₃)

MFR ID DID ID MFR ID DID ID

(repeat) (repeat)(repeat) (repeat)

Figure 12-4. Quad I/O Read Manufacture ID / Device ID Sequence Diagram

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12.5 Deep Power-Down (B9h)

During normal operation, the device is placed in Standby Mode to consume less power as long as the CS pin

remains deasserted and no internal operation is in progress. The Deep Power-Down command lets the device be

put into an even lower-power consumption state, called the Deep Power-Down mode.

When the device is in the Deep Power-Down mode, all commands, including the Read Status Register command,

are ignored, with the exception of the Resume from Deep Power-Down command. Since all commands are

ignored, the mode can be used as an extra protection mechanism against program and erase operations.

Entering the Deep Power-Down mode is done by asserting the CS pin, clocking in the opcode of B9h, and then

deasserting the CS pin. Any additional data clocked into the device after the opcode is ignored. When the CS pin is

deasserted, the device enters the Deep Power-Down mode.

The complete opcode must be clocked in before the CS pin is deasserted, and the CS pin must be deasserted on

an byte boundary (multiples of eight bits); otherwise, the device aborts the operation and returns to the Standby

Mode once the CS pin is deasserted. Also, the device defaults to the Standby Mode after a power-cycle.

The Deep Power-Down command is ignored if an internally self-timed operation, such as a program or erase cycle,

is in progress. The Deep Power-Down command must be reissued after the internally self-timed operation has

been completed in order for the device to enter the Deep Power-Down mode.

CS

t_EDPD

0

1

2

3

4

5

6

7

SCK

SI

OPCODE

1

MSB

0

1

0

1

HIGH-IMPEDANCE

Active Current

SO

I_CC

Standby Mode Current

Deep Power-Down Mode Current

Figure 12-5. Deep Power-Down

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12.6 Resume from Deep Power-Down (ABh)

To exit the Deep Power-Down mode and resume normal device operation, the Resume from Deep Power-Down

command must be issued. The Resume from Deep Power-Down command is the only command that the device

recognizes while in the Deep Power-Down mode.

To resume from the Deep Power-Down mode, the CS pin must be asserted first, and the opcode of ABh must be

clocked into the device. Any additional data clocked into the device after the opcode is ignored. When the CS pin is

deasserted, the device exits the Deep Power-Down mode and returns to the Standby Mode. After the device has

returned to the Standby Mode, normal command operations, such as Read Array, can be resumed.

If the complete opcode is not clocked in before the CS pin is deasserted, or if the CS pin is not deasserted on an

byte boundary (multiples of eight bits), the device aborts the operation and returns to the Deep Power-Down mode.

CS

t_RDPD

0

1

2

3

4

5

6

7

SCK

SI

OPCODE

1

MSB

0

1

0

1

0

1

HIGH-IMPEDANCE

Active Current

SO

I_CC

Standby Mode Current

Deep Power-Down Mode Current

Figure 12-6. Resume from Deep Power-Down

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12.6.1 Resume from Deep Power-Down and Read Device ID (ABh)

The Resume from Deep Power-Down command also can be used to read the Device ID.

When used to release the device from the Power-Down state and obtain the Device ID, the CS pin must first be

asserted and opcode ABh must be clocked into the device, followed by three dummy bytes. The Device ID bits are

then shifted out on the falling edge of SCLK with the MSB first, as shown in Figure 12-7. This command only

outputs a single byte Device ID. The Device ID value for the AT25SF321B is listed in Table 12-1 on page 41.

After the last bit (0) of the Device ID has been clocked out, the sequence repeats itself, starting again with bit 7, as

long as the CS pin remains asserted and the SCK pin is being pulsed. After CS is deasserted, it must remain high

until new commands can be received.

The same instruction can be used to read the device ID when not in power down mode. In that case, CS does not

have to remain high remain after it is deasserted.

CS

0

1

2

3

4

5

6

7

29 30 31 32 33 34 35 36 37 38 39

SCK

SI

OPCODE

3 DUMMY BYTES

t_RDPO

1

MSB

0

1

0

1

0

1

X

DEVICE ID

HIGH-IMPEDANCE

Active Current

D

MSB

D

SO

I_CC

Standby Mode Current

Deep Power-Down Mode Current

Figure 12-7. Resume from Deep Power-Down and Read Device ID Timing

12.7 Hold Function

The HOLD pin pauses the serial communication with the device without having to stop or reset the clock sequence.

This mode does not affect internally self-timed operations, such as a program or erase cycle. Thus, if an erase

cycle is in progress, asserting the HOLD pin does not pause the operation, and the erase cycle continues until it is

finished.

If the QE bit value in the Status Register has been set to 1, the HOLD pin does not function as a control pin. The

HOLD pin functions as an output for Quad-Output Read and input/output for Quad-I/O Read.

The Hold mode can only be entered while the CS pin is asserted. This mode is activated by asserting the HOLD

pin during the SCK low pulse. If the HOLD pin is asserted during the SCK high pulse, the Hold mode is not started

until the beginning of the next SCK low pulse. The device remains in this mode as long as the HOLD pin and CS

pin are asserted.

While in the Hold mode, the SO pin is in a high-impedance state. Also, both the SI pin and the SCK pin are ignored.

The WP pin, however, can be asserted or deasserted while in the Hold mode.

To end the Hold mode and resume serial communication, the HOLD pin must be deasserted during the SCK low

pulse. If the HOLD pin is deasserted during the SCK high pulse, the Hold mode does not end until the beginning of

the next SCK low pulse.

If the CS pin is deasserted while the HOLD pin is asserted, any operations that have been started are aborted, and

the device resets the WEL bit in the Status Register to 0.

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48

13. Electrical Specifications

13.1 Absolute Maximum Ratings

Notice: Stresses beyond those listed here can cause

permanent damage to the device. This is a stress

rating only; functional operation of the device at these

or any other conditions beyond those indicated in the

operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for

extended periods can affect device reliability.

Temperature under Bias. . . . . . . . . . . . -55 °C to +125 °C

Storage Temperature . . . . . . . . . . . . . . -65 °C to +150 °C

All Input Voltages (including NC Pins)

with Respect to Ground . . . . . . . . . . . . . -0.6 V to +4.1 V

All Output Voltages

with Respect to Ground . . . . . . . . . -0.6 V to V_CC+ 0.5 V

13.2 DC and AC Operating Range

Parameter

Condition

Value

Operating Temperature (Case)

V_CCPower Supply

Industrial

-40 °C to 85 °C

2.7 V to 3.6 V

13.3 DC Characteristics

2.7 V to 3.6 V

Symbol

Parameter

Condition

Min

Typ ¹

Max

Units

CS, HOLD, WP = V_IH

All inputs at CMOS levels

I_DPD

Deep Power-Down Current

Standby Current

1

5

µA

CS, HOLD, WP = V_IH

All inputs at CMOS levels

I_SB

13

3

25

4.2

5.2

7.8

6.4

8.8

8

µA

mA

f = 20 MHz; I_OUT= 0

f = 50 MHz; I_OUT= 0

f = 85 MHz; I_OUT= 0

f = 50 MHz; I_OUT= 0

Active Current, Read (03h,

0Bh) Operation

I_CC1

3.6

4.6

6.4

5.6

8.2

9

Active Current,(3Bh, BBh

Read Operation (Dual)

I_CC2

f = 85 MHz and 108 MHz;

I_OUT= 0

f = 50 MHz; I_OUT= 0

Active Current,(6Bh, EBh

Read Operation (Quad)

I_CC3

f = 85 MHz and 108 MHz;

I_OUT= 0

12

Active Current,

Program Operation

I_CC4

CS = V_CC

17

Active Current,

Erase Operation

I_CC5

7

11.5

AT25SF321B

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13.3 DC Characteristics (continued)

2.7 V to 3.6 V

Typ ¹

Symbol

Parameter

Condition

Min

Max

Units

I_LI

Input Load Current

All inputs at CMOS levels

±2

µA

I_LO

Output Leakage Current

±2

µA

V

V_IL

Input Low Voltage

-0.5

V_CCx 0.2

V_IH

V_OL

V_OH

Input High Voltage

Output Low Voltage

Output High Voltage

V_CCx 0.8

V_CC+ 0.4

0.4

V

I_OL= 100 µA

I_OH= -100 µA

V_CC- 0.2

1. Typical values measured at 3.0 V @ 25°C

13.4 AC Characteristics - Maximum Clock Frequencies

2.7 V to 3.6 V

Typ

Symbol

Parameter

Min

Max

Units

Maximum Clock Frequency for all opcodes except 03h, 0Bh, 3Bh,

6Bh

f_CLK

108

MHz

f_CLK1

f_CLK2

Maximum Clock Frequency for opcodes 0Bh, 3Bh, and 6Bh

85

55

MHz

Maximum Clock Frequency for 03h opcode

13.5 AC Characteristics - All Other Parameters

2.7 V to 3.6 V

Typ

Symbol ¹

Parameter

Units

ns

Min

4

Max

t_CLKH

t_CLKL

t_CLKR

t_CLK

Clock High Time

Clock Low Time

4

ns

Clock Rise Time, Peak-to-Peak (Slew Rate)

Clock Fall Time, Peak-to-Peak (Slew Rate)

CS High Time

0.1

20

5

V/ns

ns

t_CSH

t_CSLS

t_CSLH

t_CSHS

t_CSHH

t_DS

CS Low Setup Time (relative to Clock)

CS Low Hold Time (relative to Clock)

CS High Setup Time (relative to Clock)

CS High Hold Time (relative to Clock)

Data In Setup Time

ns

5

ns

5

ns

5

ns

2

ns

t_DH

Data In Hold Time

2

ns

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50

13.5 AC Characteristics - All Other Parameters (continued)

2.7 V to 3.6 V

Typ

Symbol ¹

Parameter

Units

ns

µs

ns

µs

Min

Max

6

t_DIS

t_V

Output Disable Time

Output Valid Time

Output Hold Time

7

t_OH

0

5

t_HLS

HOLD Low Setup Time (relative to Clock)

HOLD Low Hold Time (relative to Clock)

HOLD High Setup Time (relative to Clock)

HOLD High Hold Time (relative to Clock)

HOLD Low to Output High-Z

t_HLH

t_HHS

t_HHH

t_HLQZ

t_HHQZ

t_RES1

t_RES2

t_SUS

t_WPS

t_WPH

t_EDPD

t_RDPD

t_RDPO

6

HOLD High to Output High-Z

6

CS High to Standby Mode Without Electronic Signature Read

CS High to Standby Mode With Electronic Signature Read

CS High to Next Instruction After Suspend

Write Protect Setup Time

20

Write Protect Hold Time

100

CS High to Deep Power-Down

20

CS High to Standby Mode

Resume Deep Power-Down, CS High to ID

1. Not 100% tested. Value guaranteed by design and characterization.

13.6 Program and Erase Characteristics

2.7 V to 3.6 V

Symbol

Parameter

Condition

Min

Typ ¹

0.4

30

Max ²

Units

ms

t_PP

t_BP1

t_BP2

Page Program Time (256 Bytes)

First Byte Program Time

3.4

50

µs

Second Byte Program Time

2.5

55

12

µs

4 kbytes

32 kbytes

64 kbytes

250

450

700

30

t_BLKE

Block Erase Time

120

200

10

ms

t_CHPE

t_WRSR

Chip Erase Time

sec

ms

Write Status Register Time

5

30

1. Typical value is measured at 3.0 V, 25°C.

2. Unless specified otherwise, maximum is worst-case measurement at cycling conditions after 100k cycles.

AT25SF321B

DS-AT25SF321B–179E–06-2020

51

13.7 Power Up Conditions

Symbol

Parameter

Min

Max

Units

t_VCSL

Minimum V_CCto Chip Select Low Time

70

µs

Vcc(max)

Chip selection is not allowed

Vcc(min)

tVSL

Device is fully

accessible

Time

Figure 13-1. Power-up Timing and Voltage Levels

13.8 Input Test Waveforms and Measurement Levels

0.9V_CC

AC

DRIVING

LEVELS

V_CC/2

MEASUREMENT

LEVEL

0.1V_CC

13.9 Output Test Load

Device

Under

Test

30pF

AT25SF321B

DS-AT25SF321B–179E–06-2020

52

14. AC Waveforms

t_CSH

CS

t_CSLS

t_CSLH

t_CLKL

t_CSHH

t_CLKH

t_CSHS

SCK

t_DS

t_DH

MSB

LSB

MSB

SI

HIGH-IMPEDANCE

SO

Figure 14-1. Serial Input Timing

CS

t_CLKH

t_CLKL

t_DIS

SCK

SI

t_OH

t_V

SO

Figure 14-2. Serial Output Timing

CS

WP

SCK

SI

t_WPS

t_WPH

0

X

MSB

MSB OF

WRITE STATUS REGISTER

OPCODE

LSB OF

WRITE STATUS REGISTER

DATA BYTE

MSB OF

NEXT OPCODE

HIGH-IMPEDANCE

SO

Figure 14-3. WP Timing for Write Status Register Command When BPL = 1

AT25SF321B

DS-AT25SF321B–179E–06-2020

53

CS

SCK

HOLD

SI

t_HHH

t_HLS

t_HLH

t_HHS

HIGH-IMPEDANCE

SO

Figure 14-4. HOLD Timing – Serial Input

CS

SCK

HOLD

SI

t_HHH

t_HLS

t_HLH

t_HHS

t_HLQZ

t_HHQX

SO

Figure 14-5. HOLD Timing – Serial Output

AT25SF321B

DS-AT25SF321B–179E–06-2020

54

15. Ordering Information

AT 25SF 321 B - S H B - T

Shipping Carrier

T = Tape and Reel

B = Bulk (tube)

Designator

DWF = Die Wafer Form

Product Family

Operating Voltage

B = 2.7 V - 3.6 V

Device Density

Device Grade

321 = 32 Mbit

H = Green NiPdAu lead frame

(-40 ^oC to 85 ^oC)

Generation

Package Options

SS = 8-lead, SOP 0.150” (8S1)

S = 8-lead, SOP 0.208” (8S2)

M = 8-pad 5 x 6 UDFN (8MA1)

Max. Freq.

(MHz)

Ordering Code ¹

Package

Operating Voltage

Operation Range

AT25SF321B-SSHB-B

AT25SF321B-SSHB-T

AT25SF321B-SHB-B

AT25SF321B-SHB-T

AT25SF321B-MHB-T

AT25SF321B-DWF ²

8S1

Industrial

8S2

2.7 V to 3.6 V

108 MHz

(-40 °C to +85 °C)

8MA1

1. The shipping carrier option code is not marked on the devices.

2. Contact Adesto for detailed information.

Package Type

8S1

8S2

8-lead, 0.150" Narrow, Plastic Gull Wing Small Outline Package (EIAJ SOIC)

8-lead, 0.208" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)

8-pad (5 x 6 x 0.6mm body), Thermally Enhanced Plastic Ultra-thin Dual Flat No-lead (UDFN)

8MA1

AT25SF321B

DS-AT25SF321B–179E–06-2020

55

16. Packaging Information

16.1 8S1 – 0.150” Narrow JEDEC SOIC

C

1

E

E1

L

N

Ø

TOP VIEW

END VIEW

e

b

COMMON DIMENSIONS

(Unit of Measure = mm)

A

MIN

1.35

0.10

MAX

1.75

0.25

NOM

NOTE

SYMBOL

A1

A

–

A1

b

0.31

0.17

4.80

3.81

5.79

–

0.51

0.25

5.05

3.99

6.20

C

D

E1

E

e

–

D

–

SIDE VIEW

1.27 BSC

L

0.40

0°

–

1.27

8°

Notes: This drawing is for general information only.

Refer to JEDEC Drawing MS-012, Variation AA

8S1, 8-lead (0.150” Narrow Body), Plastic Gull

ꢀꢀꢀØꢀ

Wing Small Outline Package (JEDEC SOIC)

for proper dimensions, tolerances, datums, etc.

5/19/10

TITLE

GPC

DRAWING NO.

REV.

8S1, 8-lead (0.150” Narrow Body), Plastic Gull

Wing Small Outline (JEDEC SOIC)

SWB

8S1

F

Package Drawing Contact:

contact@adestotech.com

AT25SF321B

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56

16.2 8S2 – 8-lead, 0.208” Wide EIAJ SOIC

C

1

E

E1

L

N

T

TOP VIEW

END VIEW

e

b

COMMON DIMENSIONS

(Unit of Measure = mm)

A

MIN

1.70

0.05

0.35

0.15

5.13

5.18

7.70

0.51

0°

MAX

2.16

0.25

0.48

0.35

5.35

5.40

8.26

0.85

8°

NOM

NOTE

SYMBOL

A1

A

A1

b

4

C

D

E1

E

D

2

L

SIDE VIEW

T

e

1.27 BSC

3

Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.

2. Mismatch of the upper and lower dies and resin burrs aren't included.

3. Determines the true geometric position.

4. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm.

4/15/08

DRAWING NO.

REV.

GPC

TITLE

8S2, 8-lead, 0.208” Body, Plastic Small

Outline Package (EIAJ)

Package Drawing Contact:

contact@adestotech.com

STN

8S2

F

AT25SF321B

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57

16.3 8MA1 – UDFN

E

C

Pin 1 ID

SIDE VIEW

D

y

TOP VIEW

A1

A

K

E2

Option A

0.45

Pin #1

8

1

2

3

Pin #1 Notch

(0.20 R)

(Option B)

Chamfer

(C 0.35)

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

MAX

NOM

NOTE

SYMBOL

7

A

0.45

0.55

0.60

e

D2

A1

b

0.00

0.35

0.02

0.40

0.152 REF

5.00

4.00

6.00

3.40

1.27

0.60

–

0.05

0.48

6

C

D

D2

E

4.90

3.80

5.90

3.20

5.10

4.20

6.10

3.60

5

4

b

BOTTOM VIEW

L

E2

e

L

0.50

0.00

0.20

0.75

0.08

–

y

K

–

4/15/08

GPC

YFG

DRAWING NO.

TITLE

REV.

Package Drawing Contact: 8MA1, 8-pad (5 x 6 x 0.6 mm Body), Thermally

8MA1

D

contact@adestotech.com

Enhanced Plastic Ultra Thin Dual Flat No Lead

Package (UDFN)

AT25SF321B

DS-AT25SF321B–179E–06-2020

58

17. Revision History

Revision Number

Date

Tasks

Initial release of AT25SF321B data sheet.

A

5/2019

Revision B of AT25SF321B data sheet.

Change maximum frequency from 85 MHz to 108 MHz.

Update fclk, fclk1, and fclk2 parameters in Table 12.4.

Update maximum frequency in Ordering Code table.

B

C

6/2019

Changes to Section 6.4, Quad-Output Read Array (6Bh).

Addition of three rows to Table 12.5.

Added ordering number for Die Wafer Form in Section 15.

01/2020

Inclusion of section 7.5.2 for opcode 77h, section 7.6 for E7h, section 8.2 for

32h, section 9.5 for 66h and 99h, section 10.1 for 4Bh.

Changed SEC bit to BP4, and TBB bit to BP3.

Complete text edit for grammar, syntax, and consistency.

Changes to several numbers in Tables 13.3. and 13.6. Addition of notes to

Tables 13.3, 13.5, and 13.6.

D

E

5/2020

6/2020

Removed “Preliminary” from title page.

Addition of timing diagrams for opcodes 04h, 06h, 75h, 7Ah, and 60h/C7h.

In Table 13.3, changed I_DPDmax spec from 3 µA to 5 µA.

Updated the erase times at the end of Section 8.5.

Changed resume/suspend numbers on page 25: 2 ms --> 3.5 ms, and 18 ms -->

55 ms.

AT25SF321B

DS-AT25SF321B–179E–06-2020

59

Corporate Office

California | USA

Adesto Headquarters

3600 Peterson Way

Santa Clara, CA 95054

Phone: (+1) 408.400.0578

Email: contact@adestotech.com

Adesto, the Adesto logo, CBRAM and DataFlash are trademarks or registered trademarks of Adesto Technologies Corporation in the United States and other countries. Other company, product, and service

names may be trademarks or service marks of others. Adesto products are covered by one or more patents listed at http://www.adestotech.com/patents.

Disclaimer: Adesto Technologies Corporation (“Adesto”) makes no warranties of any kind, other than those expressly set forth in Adesto’s Terms and Conditions of Sale at

http://www.adestotech.com/terms-conditions. Adesto assumes no responsibility or obligations for any errors which may appear in this document, reserves the right to change devices or specifications

herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Adesto are granted by Adesto

herewith or in connection with the sale of Adesto products, expressly or by implication. Adesto’s products are not authorized for use in medical applications (including, but not limited to, life support systems

and other medical equipment), weapons, military use, avionics, satellites, nuclear applications, or other high risk applications (e.g., applications that, if they fail, can be reasonably expected to result in

personal injury or death) or automotive applications, without the express prior written consent of Adesto.


型号：	AT25SF321B-SHB-B
厂家：	Dialog Semiconductor
描述：	32-Mbit SPI Serial Flash Memory with Dual-I/O and Quad-I/O Support
文件：	总61页 (文件大小：1720K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT25SF321B-SHB-B [DIALOG]

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