AT25SF641_技术文档

AT25SF641

64-Mbit, 2.7V Minimum

SPI Serial Flash Memory with Dual I/O, Quad I/O and QPI Support

ADVANCE DATASHEET

Features

ò

Single 2.7V - 3.6V Supply

Serial Peripheral Interface (SPI) and Quad Peripheral Interface (QPI) Compatible

ò

Supports SPI Modes 0 and 3

Supports Dual Output Read and Quad I/O Program and Read

Supports QPI Program and Read

104 MHz* Maximum Operating Frequency

Clock-to-Output (t_V1) of 6 ns

Up tp 65MB/S continuous data transfer rate

ò

Full Chip Erase

Flexible, Optimized Erase Architecture for Code and Data Storage Applications

ò

0.6 ms Typical Page Program (256 Bytes) Time

60 ms Typical 4-Kbyte Block Erase Time

350 ms Typical 32-Kbyte Block Erase Time

700 ms Typical 64-Kbyte Block Erase Time

ò

Hardware Controlled Locking of Protected Blocks via WP Pin

4K-bit secured One-Time Programmable Security Register

Software and Hardware Write Protection

Serial Flash Discoverable Parameters (SFDP) Register

Flexible Programming

ò

Byte/Page Program (1 to 256 Bytes)

Dual or Quad Input Byte/Page Program (1 to 256 Bytes)

ò

Erase/Program Suspend and Resume

JEDEC Standard Manufacturer and Device ID Read Methodology

Low Power Dissipation

ò

2µA Deep Power-Down Current (Typical)

10µA Standby current (Typical)

5mA Active Read Current (Typical)

ò

Endurance: 100,000 program/erase cycles (4KB, 32KB or 64KB blocks)

Data Retention: 20 Years

Industrial Temperature Range: -40°C to +85°C

Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options

ò

8-lead SOIC (208-mil)

8-pad DFN (6 x 5 x 0.6 mm)

Die in Wafer Form

DS-25SF641–111E–3/2018

1.

Introduction

The Adesto^®AT25SF641 is a serial interface Flash memory device designed for use in a wide variety of high-volume

consumer based applications in which program code is shadowed from Flash memory into embedded or external RAM

for execution. The flexible erase architecture of the AT25SF641 is ideal for data storage as well, eliminating the need for

additional data storage devices.

The erase block sizes of the AT25SF641 have been optimized to meet the needs of today's code and data storage

applications. By optimizing the size of the erase blocks, the memory space can be used much more efficiently. Because

certain code modules and data storage segments must reside by themselves in their own erase regions, the wasted and

unused memory space that occurs with large block erase Flash memory devices can be greatly reduced. This increased

memory space efficiency allows additional code routines and data storage segments to be added while still maintaining

the same overall device density.

SPI clock frequencies of up to 104 MHz are supported allowing equivalent clock rates of 266 MHz for Dual Output and

532 MHz for Quad Output when using the QPI and Fast Read Dual/Quad I/O instructions.The AT25SF641 array is

organized into 65,536 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time using the

Page Program instructions. Pages can be erased 4KB Block, 32KB Block, 64KB Block or the entire chip.

The devices operate on a single 2.7V to 3.6V power supply with current consumption as low as 5 mA active and 3 µA for

Deep Power Down. All devices offered in space-saving packages. The device supports JEDEC standard manufacturer

and device identification with a 4K-bit Secured OTP.

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2.

Pinouts and Pin Descriptions

The following figures show the available package types.

Figure 1-1. 8-SOIC (Top View)

Figure 1-2. 8-UDFN (Top View)

1

2

3

4

8

7

6

5

CS

SO (IO₁)

WP (IO₂)

GND

VCC

CS

SO (IO₁)

WP (IO₂)

GND

1

2

3

4

8

7

6

5

VCC

HOLD (IO₃)

SCK

HOLD OR RESET

SCK

SI (IO₀)

During all operations, V_CCmust be held stable and within the specified valid range: V_CC(min) to V_CC(max).

All of the input and output signals must be held high or low (according to voltages of VIH, VOH, VIL or VOL.

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Table 1-1. Pin Descriptions

Asserted

State

Symbol

Name and Function

CHIP SELECT

Type

When this input signal is high, the device is deselected and serial data output pins are at

high impedance. Unless an internal program, erase or write status register cycle is in

progress, the device will be in the standby power mode (this is not the deep power down

mode). Driving Chip Select (CS) low enables the device, placing it in the active power

mode. After power-up, a falling edge on Chip Select (CS) is required prior to the start of

any instruction.

CS

Low

Input

SERIAL CLOCK

This input signal provides the timing for the serial interface. Instructions, addresses, or

data present at serial data input are latched on the rising edge of Serial Clock (SCK).

Data are shifted out on the falling edge of the Serial Clock (SCK).

SCK

-

Input

SERIAL INPUT

The SI pin is used to shift data into the device. The SI pin is used for all data input

including command and address sequences. Data on the SI pin is always latched in on

the rising edge of SCK.

With the Dual-Output and Quad-Output Read commands, the SI Pin becomes an output

pin (I/O₀) in conjunction with other pins to allow two or four bits of data on (I/O_3-0) to be

clocked in on every falling edge of SCK

SI (I/O₀)

-

Input/Output

To maintain consistency with the SPI nomenclature, the SI (I/O₀) pin is referenced as the

SI pin unless specifically addressing the Dual-I/O and Quad-I/O modes in which case it is

referenced as I/O_0.

Data present on the SI pin is ignored whenever the device is deselected (CS is

deasserted).

SERIAL OUTPUT

The SO pin is used to shift data out from the device. Data on the SO pin is always

clocked out on the falling edge of SCK.

With the Dual-Output Read commands, the SO Pin remains an output pin (I/O0) in

conjunction with other pins to allow two bits of data on (I/O_1-0) to be clocked in on every

falling edge of SCK

SO (I/O₁)

-

Input/Output

To maintain consistency with the SPI nomenclature, the SO (I/O₁) pin is referenced as

the SO pin unless specifically addressing the Dual-I/O modes in which case it is

referenced as I/O_1.The SO pin is in a high-impedance state whenever the device is

deselected (CS is deasserted).

WRITE PROTECT

The Write Protect (WP) pin can be used to protect the Status Register against data

modification. Used in company with the Status Register's Block Protect (SEC, TB, BP2, BP1

and BP0) bits and Status Register Protect SRP) bits, a portion or the entire memory array can

be hardware protected. The WP pin is active low. When the QE bit of Status Register-2 is set

for Quad I/O, the WP pin (Hardware Write Protect) function is not available since this pin is

used for IO₂. See figures 1-1, 1-2, and 1-3 for the pin configuration of Quad I/O and QPI

operation.

WP (I/O₂)

-

Input/Output

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Table 1-1. Pin Descriptions (Continued)

Asserted

State

Symbol

Name and Function

HOLD

Type

The HOLD pin is used to pause a serial sequence of the SPI flash memory without resetting

the clocking sequence. To enable the HOLD mode, the CS must be in low state. The HOLD

mode effects on with the falling edge of the HOLD signal with CLK being low. The HOLD mode

ends on the rising edge of HOLD signal with SCK being low.

HOLD

(I/O₃)

In other words, HOLD mode can't be entered unless SCK is low at the falling edge of the

HOLD signal. And HOLD mode can't be exited unless SCK is low at the rising edge of the

HOLD signal.

-

Input/Output

If CS is driven high during a HOLD condition, it resets the internal logic of the device. As

long as HOLD signal is low, the memory remains in the HOLD condition. To re-work

communication with the device, HOLD must go high, and CS must go low. See Figure

8.10 for HOLD timing.

DEVICE POWER SUPPLY

V_CCis the supply voltage. It is the single voltage used for all device functions including

read, program, and erase. The V_CCpin is used to supply the source voltage to the device.

Operations at invalid V_CCvoltages may produce spurious results and should not be attempted.

V_CC

-

Power

GROUND

GND

V_SSis the reference for the V_CCsupply voltage. The ground reference for the power supply.

GND should be connected to the system ground.

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2.

Block Diagram

Figure 2-1 shows a block diagram of the AT25SF641 serial Flash.

Figure 2-1. AT25SF641 Block Diagram

Control and

Protection Logic

I/O Buffers

and Latches

CS

SRAM

Data Buffer

SCK

Interface

Control

SI (I/O )

0

And

Logic

Y-Decoder

X-Decoder

Y-Gating

SO (I/O )

1

Flash

Memory

Array

WP (I/O )

2

HOLD

(I/O )

3

Note: I/O

3-0

pin naming convention is used for Dual-I/O and Quad-I/O commands.

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3.

Memory Array

To provide the greatest flexibility, the memory array of the AT25SF641 can be erased in four levels of granularity

including a full chip erase. The size of the erase blocks is optimized for both code and data storage applications, allowing

both code and data segments to reside in their own erase regions. The Memory Architecture Diagram illustrates the

breakdown of each erase level.

Figure 3-1. Memory Architecture Diagram

Block Erase Detail

Page Program Detail

64KB

32KB

4KB

1-256 byte

Block Address

Range

Page Address

Range

4KB

256 bytes

7FFFFFh – 7FF000h

7FEFFFh – 7FE000h

7FDFFFh – 7FD000h

7FCFFFh – 7FC000h

7FBFFFh – 7FB000h

7FAFFFh – 7FA000h

7F9FFFh – 7F9000h

7F8FFFh – 7F8000h

7F7FFFh – 7F7000h

7F6FFFh – 7F6000h

7F5FFFh – 7F5000h

7F4FFFh – 7F4000h

7F3FFFh – 7F3000h

7F2FFFh – 7F2000h

7F1FFFh – 7F1000h

7F0FFFh – 7F0000h

7EFFFFh – 7EF000h

7EEFFFh – 7EE000h

7EDFFFh – 7ED000h

7ECFFFh – 7EC000h

7EBFFFh – 7EB000h

7EAFFFh – 7EA000h

7E9FFFh – 7E9000h

7E8FFFh – 7E8000h

7E7FFFh – 7E7000h

7E6FFFh – 7E6000h

7E5FFFh – 7E5000h

7E4FFFh – 7E4000h

7E3FFFh – 7E3000h

7E2FFFh – 7E2000h

7E1FFFh – 7E1000h

7E0FFFh – 7E0000h

7FFFFFh – 7FFF00h

7FFEFFh – 7FFE00h

7FFDFFh – 7FFD00h

7FFCFFh – 7FFC00h

7FFBFFh – 7FFB00h

7FFAFFh – 7FFA00h

7FF9FFh – 7FF900h

7FF8FFh – 7FF800h

7FF7FFh – 7FF700h

7FF6FFh – 7FF600h

7FF5FFh – 7FF500h

7FF4FFh – 7FF400h

7FF3FFh – 7FF300h

7FF2FFh – 7FF200h

7FF1FFh – 7FF100h

7FF0FFh – 7FF000h

7FEFFFh – 7FEF00h

7FEEFFh – 7FEE00h

7FEDFFh – 7FED00h

7FECFFh – 7FEC00h

7FEBFFh – 7FEB00h

7FEAFFh – 7FEA00h

7FE9FFh – 7FE900h

7FE8FFh – 7FE800h

32KB

64KB

256 bytes

0017FFh – 001700h

0016FFh – 001600h

0015FFh – 001500h

0014FFh – 001400h

0013FFh – 001300h

0012FFh – 001200h

0011FFh – 001100h

0010FFh – 001000h

000FFFh – 000F00h

000EFFh – 000E00h

000DFFh – 000D00h

000CFFh – 000C00h

000BFFh – 000B00h

000AFFh – 000A00h

0009FFh – 000900h

0008FFh – 000800h

0007FFh – 000700h

0006FFh – 000600h

0005FFh – 000500h

0004FFh – 000400h

0003FFh – 000300h

0002FFh – 000200h

0001FFh – 000100h

0000FFh – 000000h

4KB

00FFFFh – 00F000h

00EFFFh – 00E000h

00DFFFh – 00D000h

00CFFFh – 00C000h

00BFFFh – 00B000h

00AFFFh – 00A000h

009FFFh – 009000h

008FFFh – 008000h

007FFFh – 007000h

006FFFh – 006000h

005FFFh – 005000h

004FFFh – 004000h

003FFFh – 003000h

002FFFh – 002000h

001FFFh – 001000h

000FFFh – 000000h

32KB

64KB

32KB

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4.

Device Operation

4.1

Standard SPI Operation

The AT25SF641 features a serial peripheral interface on four signals: Serial Clock (SCK). Chip Select (CS), Serial

Data Input (SI) and Serial Data Output (SO). Standard SPI instructions use the SI input pin to serially write instructions,

addresses or data to the device on the rising edge of SCK. The SO output pin is used to read data or status from the

device on the falling edge of SCK.

SPI bus operation Modes 0 (0, 0) and 3 (1, 1) are supported. The primary difference between Mode 0 and Mode 3

concerns the normal state of the SCK signal when the SPI bus master is in standby and data is not being transferred

to the Serial Flash. For Mode 0 the SCK signal is normally low on the falling and rising edges of CS. For Mode 3 the

SCK signal is normally high on the falling and rising edges of CS.

4.2

4.3

Dual SPI Operation

The AT25SF641 supports Dual SPI operation. This instruction allows data to be transferred to or from the device at two

times the rate of the standard SPI. The Dual Read instruction is ideal for quickly downloading code to RAM upon power-

up (code-shadowing) or for executing non-speed- critical code directly from the SPI bus (XIP). When using Dual SPI

instructions the SI and SO pins become bidirectional I/0 pins; IO₀and IO₁.

Quad SPI Operation

The AT25SF641 supports Quad SPI operation. This instruction allows data to be transferred to or from the device at

four times the rate of the standard SPI. The Quad Read instruction offers a significant improvement in continuous

and random access transfer rates allowing fast code- shadowing to RAM or execution directly from the SPI bus (XIP).

When using Quad SPI instruction the SI and SO pins become bidirectional IO₀and IO₁, and the WP and HOLD pins

become IO₂and IO₃respectively. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status

Register-2 to be set.

4.4

QPI Operation

The AT25SF641 supports Quad Peripheral Interface (QPI) operation when the device is switched from Standard/ Dual/

Quad SPI mode to QPI mode using the “Enable QPI (38h)” instruction. To enable QPI mode, the non-volatile Quad

Enable bit (QE) in Status Register-2 is required to be set. When using QPI instructions, the SI and SO pins become

bidirectional IO0 and IO1, and the WP and HOLD pins become IO₂and IO₃respectively.

The typical SPI protocol requires that the byte-long instruction code being shifted into the device only via SI pin in eight

serial clocks. The QPI mode utilizes all four IO pins to input the instruction code, thus only two serial clocks are required.

This can significantly reduce the SPI instruction overhead and improve system performance in an XIP environment.

Standard/ Dual/ Quad SPI mode and QPI mode are exclusive. Only one mode can be active at any given time, “Enable

QPI” and “Disable QPI/ Disable QPI 2” instructions are used to switch between these two modes. Upon power-up or after

software reset using “Reset (99h) instruction, the default state of the device is Standard/ Dual/ Quad SPI mode.

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5.

Write Protection

To protect inadvertent writes by the possible noise, several means of protection are applied to the Flash memory.

5.1

Write Protect Features

ò

While Power-on reset, all operations are disabled and no instruction is recognized.

ò

An internal time delay of t_PUWcan protect the data against inadvertent changes while the power supply is outside

the operating specification. This includes the Write Enable, Page program, Block Erase, Chip Erase, Write Security

Register and the Write Status Register instructions.

ò

For data changes, Write Enable instruction must be issued to set the Write Enable Latch (WEL) bit to “0”. Power-

up, Completion of Write Disable, Write Status Register, Page program, Block Erase and Chip Erase are subjected to

this condition.

Using setting the Status Register protect (SRP) and Block protect (SEC, TB, BP2, BP1, and BP0) bits a portion of

memory can be configured as reading only called software protection.

ò

Write Protect (WP) pin can control to change the Status Register under hardware control.

The Deep Power Down mode provides extra software protection from unexpected data changes as all instructions

are ignored under this status except for Release Deep Power Down instruction.

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6.

Status Register

The Read Status Register instruction can be used to provide status on the availability of the Flash memory array, if the device

is write enabled or disabled the state of write protection and the Quad SPI setting. The Write Status Register instruction can be

used to configure the devices writes protection features and Quad SPI setting. Write access to the Status Register is controlled

by in some cases of the WP pin.

Table 6-1. Status Register-1

S7

S6

S5

S4

S3

S2

S1

S0

SRP0

SEC

TB

BP2

BP1

BP0

WEL

BUSY

Status

Register

Protect 0

Sector Protect Top/Bott om Block Protect Block Protect Block Protect Write Enable Erase or Write

(Non- Volatile) Write Protect (Non- Volatile) (Non- Volatile) (Non- Volatile)

(Non- Volatile)

Latch

in Progress

(Non- Volatile)

Table 6-2. Status Register-2

S15

S14

S13

(R)

S12

(R)

S11

(R)

S10

(R)

S9

S8

SUS

CMP

QE

SRP1

Suspend

Status

Complement

Protect (Non-

Volatile)

Reserved

Quad Enable

(Non- Volatile)

Status

Register

Protect 1

(Non- Volatile)

6.1

Busy

BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a Page Program, Erase,

Write Status Register or Write Security Register instruction. During this time the device will ignore further instruction except for

the Read Status Register and Erase / Program Suspend instruction (see t_W, t_PP, t_SE, t_BE1, t_BE2and t_CEin Section 8.7, AC

Electrical Characteristics). When the Program, Erase, Write Status Register or Write Security Register instruction has

completed, the BUSY bit is cleared to 0, indicating the device is ready for further instructions.

6.2

6.3

Write Enable Latch (WEL)

Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to a 1 after executing a Write Enable instruction.

The WEL status bit is cleared to a 0 when device is write disabled. A write disable state occurs upon power-up or after any of

the following instructions: Write Disable, Page Program, Erase and Write Status Register.

Block Protect Bits (BP2, BP1, BP0)

The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3, and S2) that provide write

protection control and status. Block protect bits can be set using the Write Status Register Instruction (see t_Win Section 8.7, AC

Electrical Characteristics). All, none or a portion of the memory array can be protected from Program and Erase instructions

(see Status Register Memory Protection table). The factory default setting for the Block Protection Bits is 0, none of the array

protected.

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6.4

Top/Bottom Block protect (TB)

The Top/Bottom bit (TB) is non-volatile bits in the status register (S5) that controls if the Block Protect Bits (BP2, BP1, BP0)

protect from the Top (TB = 0) or the Bottom (TB = 1) of the array as shown in the Status Register Memory Protection table. The

factory default setting is TB = 0. The TB bit can be set with the Write Status Register Instruction depending on the state of the

SRP0, SRP1 and WEL bits.

6.5

6.6

Sector/Block Protect (SEC)

The Sector protect bit (SEC) is non-volatile bits in the status register (S6) that controls if the Block Protect Bits (BP2, BP1, BP0)

protect 4KB Sectors (SEC = 1) or 64KB Blocks (SEC = 0) in the Top (TB = 0) or the Bottom (TB = 1) of the array as shown in the

Status Register Memory protection table. The default setting is SEC = 0.

Status Register Protect (SRP1, SRP0)

The Status Register Protect bits (SRP1 and SRP0) are non

SRP bits control the method of write protection: software protection, hardware protection

programmable (OTP) protection

-

volatile read/write bits in the status register (S8 and S7)

. The

,

power supply lock down or one time

-

.

Table 6-3. Encoding of SRP and WP Bits

Status

SRP1

SRP0

WP

Register

Software

Protection

Description

WP pin no control. The register can be written to and is not affected

by the state of the WP pin.

0

X

Hardware

Protected

When WP pin is low the Status Register locked and cannot be

written to.

0

1

0

1

0

1

Hardware

When WP pin is high the Status register is unlocked and can be

written to after a Write Enable instruction, WEL=1

Unprotected

Power Supply

Lock-Down

Status Register is protected and cannot be written to again until

the next power down, power-up cycle. ⁽¹⁾

X

One Time

Program

Status Register is permanently protected and cannot be written to.

1. When SRP1, SRP0=(1,0), a power down, power-up cycle will change SRP1, SRP0 to(0,0) state.

6.7

6.8

Quad Enable (QE)

The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad operation.

When the QE bit is set to a 0 state (factory default) the WP pin and HOLD are enabled. When the QE pin is set to a 1 the

Quad IO2 and IO3 pins are enabled. WARNING: The QE bit should never be set to a 1 during standard SPI or Dual

SPI operation if the WP or HOLD pins are tied directly to the power supply or ground.

Complement Protect (CMP)

The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register (S14). It is used in conjunction

with SEC, TB, BP2, BP1 and BP0 bits to provide more flexibility for the array protection. Once CMP is set to 1, previous

array protection set by SEC, TB, BP2, BP1 and BP0 is reversed. For instance, when CMP = 0, a top 4KB sector can be

protected while the rest of the array is not; when CMP = 1, the top 4KB sector will become unprotected while the rest of

the array become read-only. Please refer to the Status Register Memory Protection table for details. The default setting is

CMP = 0.

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6.9

Erase/Program Suspend Status (SUS)

The Suspend Status bit (SUS) is a read only bit in the status register (S15) that is set to 1 after executing an Erase/Program

Suspend (75h) instruction

down power up cycle

. The SUS status bit is cleared to 0 by Erase/Program Resume (7Ah) instruction as well as a power

,

-

.

Table 6-4. Status Register Memory Protection (CMP = 0)

Status Register

Memory Protection

Addresses

SEC

X

0

TB

X

0

1

X

0

1

BP2

0

BP1

0

BP0

0

Block(s)

NONE

Density

NONE

128KB

256KB

512KB

1MB

Portion

NONE

0

1

126 and 127

124 thru 127

120 thru 127

112 thru 127

96 thru 127

64 thru 127

0 and 1

0 thru 3

0 thru 7

0 thru 15

0 thru 31

0 thru 63

0 thru 127

127

7E0000h-7FFFFFh

7C0000h-7FFFFFh

780000h-7FFFFFh

700000h-7FFFFFh

600000h-7FFFFFh

400000h-7FFFFFh

000000h-01FFFFh

000000h-03FFFFh

000000h-07FFFFh

000000h-0FFFFFh

000000h-1FFFFFh

000000h-3FFFFFh

000000h-7FFFFFh

7FF000h-7FFFFFh

7FE000h-7FFFFFh

7FC000h-7FFFFFh

7F8000h-7FFFFFh

000000h-000FFFh

000000h-001FFFh

000000h-003FFFh

000000h-007FFFh

Upper 1/64

Upper 1/32

Upper 1/16

Upper 1/8

Upper 1/4

Upper 1/2

Lower 1/64

Lower 1/32

Lower 1/16

Lower 1/8

Lower 1/4

Lower 1/2

ALL

0

1

0

1

0

1

0

1

0

1

2MB

0

1

0

4MB

0

1

128KB

256KB

512KB

1MB

0

1

0

1

0

1

0

1

0

1

2MB

0

1

0

4MB

X

1

8MB

0

1

4KB

U – 1/2048

U – 1/1024

U – 1/512

U – 1/256

L – 1/2048

L – 1/1024

L – 1/512

L – 1/256

1

0

1

0

127

8KB

1

0

1

127

16KB

32KB

4KB

1

0

X

1

127

1

0

1

0

1

0

8KB

1

0

1

0

16KB

32KB

1

0

X

0

Note:

1.

2.

3.

X = Don’t care

L = Lower; U = Upper

If any Erase or Program instruction specifies a memory region that contains protected data portion, this instruction will

be ignored.

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Table 6-5. Status Register Memory Protection (CMP = 1)

Status Register

Memory Protection

Addresses Density

SEC

X

0

TB

X

0

1

X

0

1

BP2

0

BP1

0

BP0

0

Block(s)

Portion

ALL

0 thru 127 000000h - 7FFFFFh

0 thru 125 000000h – 7DFFFFh

0 thru 123 000000h – 7BFFFFh

0 thru 119 000000h – 77FFFFh

0 thru 111 000000h – 6FFFFFh

8MB

0

1

8,064KB

7,936KB

7,680KB

7,168KB

6MB

Lower 63/64

Lower 31/32

Lower 15/16

Lower 7/8

0

1

0

1

0

1

0

1

0

1

0 thru 95

0 thru 63

000000h – 5FFFFFh

000000h – 3FFFFFh

Lower 3/4

0

1

0

4MB

Lower 1/2

0

1

2 thru 127 020000h - 7FFFFFh

4 and 127 040000h - 7FFFFFh

8,064KB

7,936KB

7,680KB

7,168KB

6MB

Upper 63/64

Upper 31/32

Upper 15/16

Upper 7/8

0

1

0

1

8 thru 127 080000h - 7FFFFFh

16 thru 127 100000h - 7FFFFFh

32 thru 127 200000h - 7FFFFFh

64 thru 127 400000h - 7FFFFFh

0

1

0

1

0

1

Upper 3/4

0

1

0

4MB

Upper 1/2

X

1

NONE

0

1

0 thru 127 000000h - 7FEFFFh

0 thru 127 000000h - 7FDFFFh

0 thru 127 000000h - 7FBFFFh

8,188KB

8,184KB

8,176KB

8,160KB

8,188KB

8,184KB

8,176KB

8,160KB

L – 2047/2048

L – 1023/1024

L – 511/512

L – 255/256

U – 2047/2048

U – 1023/1024

U – 511/512

U – 255/256

1

0

1

0

1

0

1

0

X

1

0 thru 127

000000h - 7F7FFFh

1

0

0 thru 127 001000h - 7FFFFFh

0 thru 127 002000h - 7FFFFFh

0 thru 127 004000h - 7FFFFFh

0 thru 127 008000h - 7FFFFFh

1

0

1

0

1

0

1

0

X

Note:

1.

X = don’t care

L = Lower; U = Upper

2.

3.

If any Erase or Program instruction specifies a memory region that contains protected data portion, this instruction will be ignored.

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7.

Instructions

The SPI instruction set of the AT25SF641 consists of thirty eight basic instructions and the QPI instruction set of the

AT25SF641 consists of thirty one basic instructions that are fully controlled through the SPI bus (see Instruction Set

table). Instructions are initiated with the falling edge of Chip Select (CS). The first byte of data clocked into the input

pins (SI or IO [3:0]) provides the instruction code. Data on the SI input is sampled on the rising edge of clock with

most significant bit (MSB) first.

Instructions are completed with the rising edge of edge CS. Clock relative timing diagrams for each instruction are

included in Figures 8-1 through Figure 8-66 all read instructions can be completed after any clocked bit. However, all

instructions that Write, Program or Erase must complete on a byte (CS driven high after a full 8-bit have been clocked)

otherwise the instruction will be terminated. This feature further protects the device from inadvertent writes. Additionally,

while the memory is being programmed or erased, or when the Status Register is being written, all instructions except for

Read Register will be ignored until the program or erase cycle has completed.

Table 7-1. Manufacturer and Device Identification

ID Type

Name

Adesto

ID Code

1Fh

Instruction(s)

90h, 92h, 94h, 9Fh

90h, 92h, 94h, ABh

9Fh

Manufacturer ID

Device ID

AT25SF641

SPI / QPI

64M

16h

Memory Type ID

Capacity Type ID

32h

17h

9Fh

7.1

Instruction Set Tables

The following tables list the instructions for the Single, Dual, Quad, and QPI modes of operation.

Table 7-2. Instruction Set Table 1 (SPI instructions)

Instruction Name

(Clock Number)

Byte 0

(0 – 7)

06h

Byte 1

(8 - 15)

Byte 2

Byte 3

Byte 4

Byte 5

(16 - 23)

(24 - 31)

(32 - 39)

(40 - 47)

Write Enable

50h

04h

Write Disable

Read

05h

35h

01h

31h

(SR7-SR0)⁽²⁾

(SR15-SR8)⁽²⁾

(SR7-SR0)

Status Register-1

Read

Status Register-2

Write

(SR15-SR8)

Status Register-1

Write

(SR15-SR8)

Status Register-2

03h

0Bh

02h

A23-A16

A15-A8

A7-A0

(D7-D0)

dummy

Read Data

(D7-D0)

Fast Read Data

Page Program

(D7-D0)⁽³⁾

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Table 7-2. Instruction Set Table 1 (SPI instructions) (Continued)

Instruction Name

(Clock Number)

Byte 0

(0 – 7)

38h

Byte 1

(8 - 15)

Byte 2

Byte 3

Byte 4

Byte 5

(16 - 23)

(24 - 31)

(32 - 39)

(40 - 47)

Enable QPI

20h

A23-A16

A15-A8

A7-A0

Block Erase (4KB)

Block Erase (32KB)

Block Erase (64KB)

Chip Erase

52h

D8h

60h/C7h

Erase/Program

Suspend

75h

7Ah

Erase/Program

Resume

B9h

ABh

Deep Power Down

Release Deep Power

Down/ Device ID⁽⁴⁾

dummy

(ID7-ID0)⁽²⁾

Read Manufacturer/

Device ID⁽⁴⁾

(MID7-

MID0)

90h

00h

00h or 01h

(D7-D0)

(DID7-DID0)

9Fh

66h

(MID7-MID0)

(D7-D0)

Read JEDEC ID

Reset Enable

Reset

99h

B1h

C1h

Enter Secured OTP

Exit Secured OTP

Read

0

)

2Bh

2Fh

5Ah

(SC7-SC0) ⁽¹

Security Register

Write

Security Register

Read Serial Flash

A23-A16

A15-A8

A7-A0

dummy

(D7-D0)

Discovery Parameter

Table 7-3. Instruction Set Table 2 (Dual SPI Instructions)

Instruction Name

(Clock Number)

Byte 0

(0 – 7)

3Bh

Byte 1

(8 - 15)

Byte 2

(16 - 23)

A15-A8

A7-A0,

Byte 3

(24 - 31)

Byte 4

(32 - 39)

dummy

Byte 5

(40 - 47)

(D7-D0)⁽⁶⁾

Fast Read Dual Output

A23-A16

A23-A8⁽⁵⁾

A7-A0

BBh

(D7-D0, ꢀ)⁽⁶⁾

Fast Read Dual I/O

Read Dual Manufacturer/

Device ID⁽⁴⁾

(00h, xxxx) or

(01h, xxxx)

(MID7-MID0)

(DID7-DID0)⁽⁶⁾

92h

0000h

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Table 7-4. Instruction Set Table 3 (Quad SPI Instructions)

Instruction Name

(Clock Number)

Byte 0

(0 – 7)

6Bh

Byte 1

(8 - 15)

A23-A16

Byte 2

(16 - 23)

A15-A8

Byte 3

(24 - 31)

A7-A0

Byte 4

(32 - 39)

dummy

Byte 5

(40 - 47)

(D7-D0) ⁽⁸⁾

Fast Read Quad Output

A23-A0,

M7-M0⁽⁷⁾

Fast Read Quad I/O

Quad Page Program

EBh

33h

(xxx, D7-D0,ꢀ)⁽⁹⁾(D7-D0, ꢀ)⁽⁸⁾

A23-A0

(D7-D0, ꢀ)⁽⁸⁾

(00_0000h, xx)

or

(xxxx,

Read Quad

94h

MID7-MID0) (xxxx,

DID7-DID0)⁽⁹⁾

Manufacturer /Device ID⁽⁴⁾

(00_0001h, xx)

A23-A0,

M7-M0⁽⁷⁾

Word Read Quad I/O

Set Burst with Wrap

E7h

77h

(xx, D7-D0)

(D7-D0)⁽⁸⁾

xxxxxx, W6-W4⁽⁷⁾

Table 7-5. Instruction Set Table 4 (QPI Instructions)

Instruction Name

(Clock Number)

Byte 0

(0 - 7)

06h

Byte 1

(8 - 15)

Byte 2

Byte 3

Byte 4

Byte 5

Byte 6

Byte 7 Byte 8

(16 - 23) (24 - 31)

(32 - 39) (40 - 47) (48 - 55) (56 - 63) (64 - 71)

Write Enable

50h

Write Enable for Volatile

Write Disable

04h

(SR7-

SR0)⁽²⁾

Read Status Register-1

Read Status Register-2

05h

35h

(SR15-

SR8)⁽²⁾

(SR7-

SR0)

(SR15-

SR8)

Write Status Register-1⁽⁵⁾01h

(SR15-

SR8)

Write Status Register-2

31h

>80MHz

A23-A16

A15-A8

A7-A0

dummy

dummy (D7-D0)

dummy dummy

Fast Read

0Bh

02h

(D7-

D0)

Data

>104MHz

Page Program

(D7-D0)⁽³⁾

20h

52h

D8h

A23-A16

A15-A8

A7-A0

Block Erase(4KB)

Block Erase(32KB)

Block Erase(64KB)

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Table 7-5. Instruction Set Table 4 (QPI Instructions) (Continued)

Instruction Name

(Clock Number)

Byte 0

(0 - 7)

Byte 1

(8 - 15)

Byte 2

Byte 3

Byte 4

Byte 5

Byte 6

Byte 7 Byte 8

(16 - 23) (24 - 31)

(32 - 39) (40 - 47) (48 - 55) (56 - 63) (64 - 71)

60h/

C7h

Chip Erase

75h

7Ah

B9h

ABh

Erase/Program Suspend

Erase/Program Resume

Deep Power Down

Release Deep Power

Read

00h or

(MID7-

MID0)

(DID7-

DID0)

90h

9Fh

00h

01h

Manufacturer/Device

ID⁽⁴⁾

(D7-D0) (D7-D0)

Memory Capacity

(MID7- MID0)

Manufacturer

Read JEDEC ID⁽⁴⁾

Type

B1h

C1h

Enter Security

Exit Security

(SC7-

Read Security Register

2Bh

2Fh

SC0) ⁽¹

0

)

Write Security Register

>80MHz

A23-A16

A15-A8

A7-A0

(M7-M0)

dummy (D7-D0)

dummy dummy

Fast Read

Quad I/O

EBh

(M7-

M0)

(D7-

D0)

>104MHz

Reset Enable

Reset

66h

99h

FFh

Disable QPI

>80MHz

A23-A16

A15-A8

A7-A0

dummy

dummy (D7-D0)

dummy dummy

Burst Read

with Wrap

0Ch

(D7-

D0)

>104MHz

Set Read Parameter

Quad Page Program

C0h

33h

P7-P0

A23-A16

A15-A8

A7-A0

(D7-D0)

Notes:

1.

Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “()” indicate data being read from the device

on the IO pin.

2.

3.

SR = status register, The Status Register contents and Device ID will repeat continuously until CS terminates the instruction.

At least one byte of data input is required for Page Program, Quad Page Program and Program Security Register, up to 256 bytes

of data input. If more than 256 bytes of data are sent to the device, the addressing will wrap to the beginning of the page and

overwrite previously sent data.

4.

5.

See Manufacturer and Device Identification table for Device ID information.

Dual Input Address

IO0 = A22, A20, A18, A16, A14, A12, A10, A8, A6, A4, A2, A0, M6, M4, M2, M0

IO1 = A23, A21, A19, A17, A15, A13, A11, A9, A7, A5, A3, A1, M7, M5, M3, M1

Dual Output data

6.

IO0 = (D6, D4, D2, D0)

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IO1 = (D7, D5, D3, D1)

Quad Input Address

7.

8.

Set Burst with Wrap Input

IO0 = A20, A16, A12, A8, A4, A0, M4, M0

IO1 = A21, A17, A13, A9, A5, A1, M5, M1

IO2 = A22, A18, A14, A10, A6, A2, M6, M2

IO3 = A23, A19, A15, A11, A7, A3, M7, M3

IO0 = x, x, x, x, x, x, W4,

IO1 = x, x, x, x, x, x, W5,

IO2 = x, x, x, x, x, x, W6,

IO3 = x, x, x, x, x, x, x

x

Quad Input/ Output Data

IO0 = (D4, D0ꢀ)

IO1 = (D5, D1ꢀ)

IO2 = (D6, D2ꢀ)

IO3 = (D7, D3ꢀ)

9.

Fast Read Quad I/O Data Output

IO0 = (x, x, x, x, D4, D0ꢀ)

IO1 = (x, x, x, x, D5, D1ꢀ)

IO2 = (x, x, x, x, D6, D2ꢀ)

IO3 = (x, x, x, x, D7, D3ꢀ)

10.

SC = security register

7.2

Write Enable (06h)

Write Enable instruction is for setting the Write Enable Latch (WEL) bit in the Status Register

.

The WEL bit must be set prior to

CS goes low prior to the

every Program Erase and Write Status Register instruction To enter the Write Enable instruction,

,

.

instruction “06h” into Data Input (SI) pin on the rising edge of SCK, and then driving CS high

.

Figure 7-1. Write Enable Instruction for SPI Mode (left) and QPI Mode (right)

7.3

Write Enable for Volatile Status Register (50h)

This gives more flexibility to change the system configuration and memory protection schemes quickly without waiting

for the typical non-volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. To write the

volatile values into the Status Register bits, the Write Enable for Volatile Status Register (50h) instruction must be issued

prior to a Write Status Register (01h) instruction. Write Enable for Volatile Status Register instruction (Figure 7-2) will

not set the Write Enable Latch (WEL) bit. Once Write Enable for Volatile Status Register is set, a Write Enable

instruction should not have been issued prior to setting Write Status Register instruction (01h or 31h).

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Figure 7-2. Write Enable for Volatile Status Register Instruction for SPI Mode (left) and QPI Mode (right)

7.4

Write Disable (04h)

The Write Disable instruction is to reset the Write Enable Latch (WEL) bit in the Status Register

instruction CS goes low prior to the instruction “04h” into Data Input (SI) pin on the rising edge of SCK, and then driving CS

high WEL bit is automatically reset write- disable status of “0” after Power up and upon completion of the every Program

Erase and Write Status Register instructions

. To enter the Write Disable

,

.

-

,

.

Figure 7-3. Write Disable Instruction for SPI Mode (left) and QPI Mode (right)

7.5

Read Status Register-1 (05h) and Read Status Register-2 (35h)

The Read Status Register instructions are to read the Status Register. The Read Status Register can be read at any

time (even in program/erase/write Status Register and Write Security Register condition). It is recommended to check

the BUSY bit before sending a new instruction when a Program, Erase, Write Status Register or Write Status Register

operation is in progress.

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The instruction is entered by driving CS low and sending the instruction code “05h” for Status Register-1 or “35h” for Status

Register-2 into the SI pin on the rising edge of SCK. The status register bits are then shifted out on the SO pin at the falling

edge of SCK with most significant bit (MSB) first as shown in (Figure 7-4 and Figure 7-5). The Status Register can be read

continuously. The instruction is completed by driving CS high.

Figure 7-4. Read Status Register Instruction (SPI Mode)

Figure 7-5. Read Status Register Instruction (QPI Mode)

7.6

Write Status Register (01h)

The Write Status Register instruction is to write only non-volatile Status Register-1 bits (SRP0, SEC, TB, BP2, BP1

and BP0) and Status Register-2 bits (CMP, QE and SRP1). All other Status Register bit locations are read-only and will

not be affected by the Write Status Register instruction.

A Write Enable instruction must previously have been issued prior to setting Write Status Register Instruction (Status

Register bit WEL must equal 1). Once write is enabled, the instruction is entered by driving CS low, sending the

instruction code, and then writing the status register data byte as illustrated in Figure 7-6 and Figure 7-7.

The CS pin must be driven high after the eighth or sixteenth bit of data that is clocked in. If this is not done the Write

Status Register instruction will not be executed. If CS is driven high after the eighth clock, the CMP QE and SRP1 bits

will be cleared to 0. After CS is driven high, the self- timed Write Status Register cycle will commence for a time duration

of t_W(See Section 8.7, AC Electrical Characteristics).

While the Write Status Register cycle is in progress, the Read Status Register instruction may still be accessed to

check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle and a 0 when the

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20

cycle is finished and ready to accept other instructions again. When the BUSY bit is asserted, the Write Enable Latch

(WEL) bit in Status Register will be cleared to 0.

Figure 7-6. Write Status Register Instruction (SPI Mode)

Figure 7-7. Write Status Register Instruction (QPI Mode)

7.7

Write Status Register-2 (31h)

The Write Status Register-2 instruction is to write only non-volatile Status Register-2 bits (CMP, QE and SRP1).

A Write Enable instruction must previously have been issued prior to setting Write Status Register Instruction (Status

Register bit WEL must equal 1). Once write is enabled, the instruction is entered by driving CS low, sending the

instruction code, and then writing the status register data byte as illustrated in Figure 7-8 and Figure 7-9.

Using Write Status Register-2 (31h) instruction

instructions

, software can individually access each one-byte status registers via different

.

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21

Figure 7-8. Write Status Register-2 Instruction (SPI Mode)

Figure 7-9. Write Status Register-2 Instruction (QPI Mode)

7.8

Read Data (03h)

The Read Data instruction is to read data out from the device

.

The instruction is initiated by driving the CS pin low and then

After the address is received the

sending the instruction code “03h” with following a 24 bit address (A23- A0) into the SI pin

-

.

,

data byte of the addressed memory location will be shifted out on the SO pin at the falling edge of SCK with most significant bit

(MSB) first. The address is automatically incremented to the next higher address after byte of data is shifted out allowing for a

continuous stream of data

continues The instruction is completed by driving CS high. The Read Data instruction sequence is shown in Figure 7-10. If a

Read Data instruction is issued while an Erase Program or Write Status Register cycle is in process (BUSY = 1) the instruction

is ignored and will not have any effects on the current cycle The Read Data instruction allows clock rates from D.C to a

maximum of f (see Section 8.7, AC Electrical Characteristics).

. This means that the entire memory can be accessed with a single instruction as long as the clock

.

,

.

R

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Figure 7-10. Read Data Instruction

7.9

Fast Read (0Bh)

The Fast Read instruction is high speed reading mode that it can operate at the highest possible frequency of FR

. The address

is latched on the rising edge of the SCK. After the 24

Figure 7-11 The dummy clocks means the internal circuits require time to set up the initial address

the data value on the SO pin is a “don’t care” Data of each bit shifts out on the falling edge of SCK.

-

bit address

,

this is accomplished by adding “dummy” clocks as shown in

.

During the dummy clocks,

.

Figure 7-11. Fast Read Instruction (SPI Mode)

7.10 Fast Read in QPI Mode

When QPI mode is enabled, the number of dummy clock is configured by the “Set Read Parameters (C0h)” instruction to

accommodate wide range applications with different needs for either maximum Fast Read frequency or minimum data

access latency. Depending on the Read Parameter Bit P[4] and P[5] setting, the number of dummy clocks can be

configured as either 4, or 6 or 8. The default number of dummy clocks upon power up or after a Reset instruction is 4.

(Please refer to Figure 7-12, Figure 7-13 and Figure 7.11).

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Figure 7-12. Fast Read instruction (QPI Mode, 80MHz)

Figure 7-13. Fast Read instruction (QPI Mode, 104MHz)

7.11 Fast Read Dual Output (3Bh)

By using two pins (IO

0

and IO

1

, instead of just IO

0

), The Fast Read Dual Output instruction allows data to be transferred from

the AT25SF641 at twice the rate of standard SPI devices. The Fast Read Dual Output instruction is ideal for quickly

downloading code from Flash to RAM upon power-up or for application that cache code-segments to RAM for execution.

The Fast Read Dual Output instruction can operate at the highest possible frequency of F

After the 24 bit address, this is accomplished by adding eight “dummy” clocks as shown in Figure 7-14. The dummy clocks

allow the internal circuits additional time for setting up the initial address. During the dummy clocks the data value on the SO

R

(see AC Electrical Characteristics).

-

,

pin is a “don’t care”. However

,

the IO

0

pin should be high

-

impedance prior to the falling edge of the first data out clock

.

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Figure 7-14. Fast Read Dual Output instruction (SPI Mode)

7.12 Fast Read Quad Output (6Bh)

By using four pins (IO

0

, IO

1

, IO

2

, and IO

3

), The Fast Read Quad Output instruction allows data to be transferred from the

AT25SF641 at four times the rate of standard SPI devices. A Quad enable of Status Register-2 must be executed before

the device will accept the Fast Read Quad Output instruction (Status Register bit QE must equal 1).

The Fast Read Quad Output instruction can operate at the highest possible frequency of F (see Section 8.7, AC

R

Electrical Characteristics). This is accomplished by adding eight “dummy” clocks after the 24- bit address as shown in

Figure 7-15. The dummy clocks allow the internal circuits additional time for setting up the initial address. During the

dummy clocks, the data value on the SO pin is a “don’t care”. However, the IO

pin should be high-impedance prior to

0

the falling edge of the first data out clock.

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Figure 7-15. Fast Read Quad Output instruction (SPI Mode)

7.13 Fast Read Dual I/O (BBh)

The Fast Read Dual I/O instruction reduces cycle overhead through double access using two IO pins: IO

0

and IO .

1

Continuous read mode

The Fast Read Dual I/O instruction can further reduce cycle overhead through setting the Mode bits (M7-0) after the

input Address bits (A23-0). The upper nibble of the Mode (M7-4) controls the length of the next Fast Read Dual I/O

instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the Mode (M3-0)

are don’t care (“X”), However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.

If the Mode bits (M7-0) equal “Ax” hex, then the next Fast Dual I/O instruction (after CS is raised and then lowered) does

not require the instruction (BBh) code, as shown in Figure 7-16 and Figure 7-17. This reduces the instruction sequence

by eight clocks and allows the address to be immediately entered after CS is asserted low. If Mode bits (M7-0) are any

value other “Ax” hex, the next instruction (after CS is raised and then lowered) requires the first byte instruction code,

thus returning to normal operation. A Mode Bit Reset can be used to reset Mode Bits (M7-0) before issuing normal

instructions.

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Figure 7-16. Fast Read Dual I/O Instruction (initial instruction or previous M7-0 ≠ Axh)

Figure 7-17. Fast Read Dual I/O Instruction (previous M7-0 = Axh)

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7.14 Fast Read Quad I/O (EBh)

The Fast Read Quad I/O instruction reduces cycle overhead through quad access using four IO pins: IO

The Quad Enable bit (QE) of Status Register-2 must be set to enable the Fast read Quad I/O Instruction.

0

, IO , IO2, and IO3.

1

Continuous read mode

The Fast Read Quad I/O instruction can further reduce instruction overhead through setting the Mode bits (M7-0) with

following the input Address bits (A23-0), as shown in Figure 7-18. The upper nibble of the Mode (M7-4) controls the

length of the next Fast Read Quad I/O instruction through the inclusion or exclusion of the first byte instruction code.

The lower nibble bits of the Mode (M3-0) are don’t care (“X”). However, the IO pins should be high-impedance prior to

the falling edge of the first data out clock.

If the Mode bits (M7-0) equal “Ax” hex, then the next Fast Read Quad I/O instruction (after CS is raised and then

lowered) does not require the EBh instruction code, as shown in Figure 7-19. This reduces the instruction sequence by

eight clocks and allows the address to be immediately entered after CS is asserted low. If the Mode bits (M7-0) are any

value other than “Ax” hex, the next instruction (after CS is raised and then lowered) requires the first byte instruction

code, thus retuning normal operation. A Mode Bit Reset can be used to reset Mode Bits (M7-0) before issuing normal

instructions.

Figure 7-18. Fast Read Quad I/O Instruction (Initial instruction or previous M7-0 ≠ Axh, SPI mode)

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Figure 7-19. Fast Read Quad I/O Instruction (previous M7-0 = Axh, SPI mode)

Wrap Around in SPI mode

The Fast Read Quad I/O instruction can also be used to access specific portion within a page by issuing a “Set Burst

with Wrap” (77h) instruction prior Fast Read Quad I/O (EBh) instruction. The “Set Burst with Wrap” (77h) instruction can

either enable or disable the “Wrap Around” feature for the following Fast Read Quad I/O instruction.

When “Wrap Around” is enabled, the data being accessed can be limited to an 8/16/32/64-byte section of a 256-byte

page. The output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the

8/16/32/64-byte section, the output will wrap around to the beginning boundary automatically until CS is pulled high to

terminate the instruction.

The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the

cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read instructions. (Please

refer to Section 7.31 Set Burst with Wrap).

Fast Read Quad I/O in QPI mode

When QPI mode in enabled, the number of dummy clocks is configured by the “Set Read Parameters (C0h)” instruction

to accommodate a wide range applications with different needs for either maximum Fast Read frequency or minimum

data access latency. Depending on the Read Parameter Bits P [4] and P [5] setting, the number of dummy clocks can

be configured as either 4 or 6 or 8. The default number of dummy clocks upon power up or after a Reset (99h)

instruction is 4.

“Continuous Read Mode” feature is also available in QPI mode for Fast Read Quad I/O instruction. In QPI mode, the

“Continuous Read Mode” bits M7-0 are also considered as dummy clocks. In the default setting, the data output will

follow the Continuous Read Mode bits immediately.

“Wrap Around” feature is not available in QPI mode for Fast Read Quad I/O instruction. To perform a read operation with

fixed data length wrap around in QPI mode, a “Burst Read with Wrap” (0Ch) instruction must be used. (Please refer to

Section 7.32 Burst Read with Wrap).

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Figure 7-20. Fast Read Quad I/O Instruction (Initial instruction or previous M7-0 ≠ Axh, QPI mode, 80MHz)

Figure 7-21. Fast Read Quad I/O Instruction (Initial instruction or previous M7-0 ≠ Axh, QPI mode, 104MHz)

7.15 Page Program (02h)

The Page Program instruction is for programming the memory to be “0”. A Write Enable instruction must be issued

before the device accept the Page Program Instruction (Status Register bit WEL=1). After the Write Enable (WREN)

instruction has been decoded, the device sets the Write Enable Latch (WEL). The instruction is entered by driving the

CS pin low and then sending the instruction code “02h” with following a 24-bits address (A23-A0) and at least one data

byte, into the SI pin. The CS pin must be driven low for the entire time of the instruction while data is being sent to the

device. (Please refer to Figure 7-22 and Figure 7-23).

If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits) should be set

to 0. If the last address byte is not zero, and the number of clocks exceeds the remaining page length, the addressing

will wrap to the beginning of the page. In some cases, less than 256 bytes (a partial page) can be programmed without

having any effect on other bytes within the same page. One condition to perform a partial page program is that the

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number of clocks cannot exceed the remaining page length. If more than 256 bytes are sent to the device the addressing

will wrap to the beginning of the page and overwrite previously sent data

The CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Page

Program instruction will not be executed. After CS is driven high, the self-timed Page Program instruction will

commence for a time duration of t_PP(See Section 8.7, AC Electrical Characteristics).

While the Page Program cycle is in progress, the Read Status Register instruction may still be accessed for checking the

status of the BUSY bit. The BUSY bit is a 1 during the Page Program cycle and becomes a 0 when the cycle is finished

and the device is ready to accept other instructions again. When the BUSY bit is asserted, the Write Enable Latch (WEL)

bit in the Status Register is cleared to 0. The Page Program instruction is not executed if the addressed page is

protected by the Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits.

Figure 7-22. Page Program Instruction (SPI Mode)

Figure 7-23. Page Program Instruction (QPI Mode)

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7.16 Quad Page Program (33h)

The Quad Page Program instruction is to program the memory as being “0” at previously erased memory areas. The Quad

Page Program takes four pins: IO^0,IO1, IO

2

and IO as address and data input, which can improve programmer performance

3

and the effectiveness of application of lower clock less than 5MHz. Systems using faster clock speeds will not get more benefit

for the Quad Page Program as the required internal page program time is far more than the time data clock-in.

To use Quad Page Program, the Quad Enable bit must be set, A Write Enable instruction must be executed before the

device will accept the Quad Page Program instruction (Status Register-1, WEL=1). The instruction is initiated by driving

the CS pin low then sending the instruction code “33h” with following a 24-bit address (A23-A0) and at least one data,

into the IO pins. The CS pin must be held low for the entire length of the instruction while data is being sent to the device.

All other functions of Quad Page Program are perfectly same as standard Page Program. (Please refer to Figure 7-

24 and Figure 7-25).

Figure 7-24. Quad Page Program Instruction (SPI mode)

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Figure 7-25. Quad Page Program Instruction (QPI mode)

7.17 Block Erase (20h)

The Block Erase instruction is to erase the data of the selected sector as being “1”. The instruction is used for 4K-byte

Block. Prior to the Block Erase Instruction, the Write Enable instruction must be issued. The instruction is initiated by

driving the CS pin low and shifting the instruction code “20h” followed a 24-bit Block address (A23-A0). (Please refer to

Figure 7-26 and Figure 7-27). The CS pin must go high after the eighth bit of the last byte has been latched in,

otherwise, the Block Erase instruction is not executed. After CS goes high, the self-timed Block Erase instruction

commences for a time duration of t_SE(See Section 8.7, AC Electrical Characteristics).

While the Block Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the

status of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished

and the device is ready to accept other instructions again. When the BUSY bit is asserted, the Write Enable Latch (WEL)

bit in the Status Register is cleared to 0. The Block Erase instruction will not be executed if the addressed page is

protected by the Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits.

Figure 7-26. Block Erase Instruction (SPI Mode)

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Figure 7-27. Block Erase Instruction (QPI Mode)

7.18 32KB Block Erase (52h)

The Block Erase instruction is to erase the data of the selected block as being “1”. The instruction is used for 32K-byte

Block erase operation. Prior to the Block Erase Instruction, a Write Enable instruction must be issued. The instruction is

initiated by driving the CS pin low and shifting the instruction code “52h” followed a 24-bit block address (A23-A0).

(Please refer to Figure 7-28 and Figure 7-29). The CS pin must go high after the eighth bit of the last byte has been

latched in, otherwise, the Block Erase instruction will not be executed. After CS is driven high, the self-timed Block Erase

instruction will commence for a time duration of t_BE1(See Section 8.7, AC Electrical Characteristics).

While the Block Erase cycle is in progress, the Read Status Register instruction may still be read the status of the

BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished and the

device is ready to accept other instructions again. When the BUSY bit is asserted, the Write Enable Latch (WEL) bit in

the Status Register is cleared to 0. The Block erase instruction will not be executed if the addressed page is protected

by the Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits.

Figure 7-28. 32KB Block Erase Instruction (SPI Mode)

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Figure 7-29. 32KB Block Erase Instruction (QPI Mode)

7.19 64KB Block Erase (D8h)

The Block Erase instruction is to erase the data of the selected block as being “1”. The instruction is used for 64K-byte

Block erase operation. Prior to the Block Erase Instruction, a Write Enable instruction must be issued. The instruction is

initiated by driving the CS pin low and shifting the instruction code “D8h” followed a 24-bit block address (A23-A0).

(Please refer to Figure 7-30 and Figure 7-31). The CS pin must go high after the eighth bit of the last byte has been

latched in, otherwise, the Block Erase instruction will not be executed. After CS is driven high, the self-timed Block Erase

instruction will commence for a time duration of t_BE2(See Section 8.7, AC Electrical Characteristics).

While the Block Erase cycle is in progress, the Read Status Register instruction may still be read the status of the

BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished and the

device is ready to accept other instructions again. When the BUSY bit is asserted, the Write Enable Latch (WEL) bit in

the Status Register is cleared to 0. The Block erase instruction will not be executed if the addressed page is protected

by the Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits.

Figure 7-30. 64KB Block Erase Instruction (SPI Mode)

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Figure 7-31. 64KB Block Erase Instruction (QPI Mode)

7.20 Chip Erase (C7h / 60h)

The Chip Erase instruction clears all bits in the device to be FFh (all 1s). Prior to the Chip Erase Instruction, a Write

Enable instruction must be issued. The instruction is initiated by driving the CS pin low and shifting the instruction code

“C7h” or “60h”. (Please refer to Figure 7-32). The CS pin must go high after the eighth bit of the last byte has been

latched in, otherwise, the Chip Erase instruction will not be executed. After CS is driven high, the self-timed Chip Erase

instruction will commence for a duration of t_CE(See Section 8.7, AC Electrical Characteristics).

While the Chip Erase cycle is in progress, the Read Status Register instruction may still be accessed to check the status

of the BUSY bit. The BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when the cycle is finished and the

device is ready to accept other instructions again. When the BUSY bit is asserted, the Write Enable Latch (WEL) bit in

the Status Register is cleared to 0. The Chip erase instruction is not executed if any page is protected by the Protect

(CMP, SEC, TB, BP2, BP1 and BP0) bits.

Figure 7-32. Chip Erase Instruction for SPI Mode (left) and QPI Mode (right)

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7.21 Erase / Program Suspend (75h)

The Erase/Program Suspend instruction allows the system to interrupt a Block Erase operation or a Page Program,

Quad Data Input Page Program, Quad Page Program operation.

Erase Suspend is valid only during the Block erase operation. The Write Status Register-1 (01h), Write Status Register-

2 (31h) instruction and Erase instructions (20h, 52h, D8h, C7h, 60h) are not allowed during Erase Suspend. During the

Chip Erase operation, the Erase Suspend instruction is ignored.

Program Suspend is valid only during the Page Program, Quad Data Input Page Program or Quad Page Program

operation. The Write Status Register-1(01h), Write Status Register-2 (31h) instruction and Program instructions (02h

and 33h) and Erase instructions (20h, 52h, D8h, C7h and 60h) are not allowed during Program Suspend.

The Erase/Program Suspend instruction “75h” will be accepted by the device only if the SUS bit in the Status Register

equals to 0 and the BUSY bit equals to 1 while a Block Erase or a Page Program operation is on-going. If the SUS bit

equals to 1 or the BUSY bit equals to 0, the Suspend instruction will be ignored by the device. A maximum of time of

t_SUS(See Section 8.7, AC Electrical Characteristics) is required to suspend the erase or program operation. After

Erase/Program Suspend, the SUS bit in the Status Register will be set from 0 to 1 immediately and The BUSY bit in the

Status Register will be cleared from 1 to 0 within “t_SUS”. For a previously resumed Erase/Program operation, it is also

required that the Suspend instruction “75h” is not issued earlier than a minimum of time of t_SUSfollowing the preceding

Resume instruction “7Ah”.

Unexpected power off during the Erase/Program suspend state resets the device and release the suspend state. SUS

bit in the Status Register also resets to 0. The data within the page or block that was being suspended may become

corrupted. It is recommended for the user to implement system design techniques against the accidental power

interruption and preserve data integrity during erase/program suspend state. (Please refer to Figure 7-33 and Figure 7-

34).

Figure 7-33. Erase Suspend instruction (SPI Mode)

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Figure 7-34. Erase Suspend instruction (QPI Mode)

7.22 Erase / Program Resume (7Ah)

The Erase/Program Resume instruction “7Ah” is to re-work the Block Erase operation or the Page Program operation

upon an Erase/Program Suspend. The Resume instruction “7Ah” will be accepted by the device only if the SUS bit in

the Status Register equals to 1 and the BUSY bit equals to 0. After issued, the SUS bit will be cleared from 1 to 0

immediately, the BUSY bit will be set from 0 to 1 within 200ns and the Block will complete the erase operation or the

page will complete the program operation. If the SUS bit equals to 0 or the BUSY bit equals to 1, the Resume

instruction “7Ah” will be ignored by the device.

Resume instruction cannot be accepted if the previous Erase/Program Suspend operation was interrupted by

unexpected power off. It is also required that a subsequent Erase/Program Suspend instruction not to be issued within a

minimum of time of “t_SUS” following a previous Resume instruction. (Please refer to Figure 7-35 and Figure 7-36).

Figure 7-35. Erase / Program Resume instruction (SPI Mode)

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Figure 7-36. Erase / Program Resume instruction (QPI Mode)

7.23 Deep Power Down (B9h)

Executing the Deep Power Down instruction is the best way to put the device in the lowest power consumption. The

Deep Power Down instruction reduces the standby current (from ICC1 to ICC2, as specified in Section 8.7, AC Electrical

Characteristics). The instruction is entered by driving the CS pin low with following the instruction code “B9h”. (Please

refer to Figure 7-37 and Figure 7-38).

The CS pin must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in);

otherwise, the Deep Power Down instruction is not executed. After CS goes high, it requires a delay of t_DPand the Deep

Power Down mode is entered. While in the Release Deep Power Down / Device ID instruction, which restores the device

to normal operation, will be recognized. All other instructions are ignored including the Read Status Register instruction,

which is always available during normal operation. Deep Power Down Mode automatically stops at Power-Down, and the

device always Power-up in the Standby Mode.

Figure 7-37. Deep Power Down Instruction (SPI Mode)

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Figure 7-38. Deep Power Down Instruction (QPI Mode)

7.24 Release Deep Power Down / Device ID (ABh)

The Release Deep Power Down / Device ID instruction is a multi-purpose instruction. It can be used to release the

device from the Deep Power Down state or obtain the device identification (ID).

The instruction is issued by driving the CS pin low, sending the instruction code “ABh” and driving CS high as shown in

figure Figure 7-39 and Figure 7-40. Release from Deep Power Down require the time duration of t_RES1(See Section 8.7,

AC Electrical Characteristics) for re-work a normal operation and accepting other instructions. The CS pin must keep high

during the t_RES1time duration.

The Device ID can be read during SPI mode only. In other words, Device ID feature is not available in QPI mode for Release

Deep Power Down/Device ID instruction. To obtain the Device ID in SPI mode, instruction is initiated by driving the CS pin

low and sending the instruction code “ABh” with following 3-dummy bytes. The Device ID bits are then shifted on the

falling edge of SCK with most significant bit (MSB) first as shown in Figure 7-41. After CS is driven high it must keep

high for a time duration of t_RES2(See Section 8.7, AC Electrical Characteristics). The Device ID can be read continuously.

The instruction is completed by driving CS high.

If the Release from Deep Power Down /Device ID instruction is issued while an Erase, Program or Write cycle is in process

(when BUSY equals 1) the instruction is ignored and does not have any effects on the current cycle.

Figure 7-39. Release Power Down Instruction (SPI Mode)

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Figure 7-40. Release Power Down Instruction (QPI Mode)

Figure 7-41. Release Power Down / Device ID Instruction (SPI Mode)

7.25 Read Manufacturer / Device ID Dual I/O (90h)

The Read Manufacturer/ Device ID Dual I/O instruction provides both the JEDEC assigned manufacturer ID and the

specific device ID.

The Read Manufacturer/ Device ID instruction is very similar to the Fast Read Dual I/O instruction. The instruction is

initiated by driving the CS pin low and shifting the instruction code “90h” followed by a 24-bit address (A23-A0) of

000000h. After which, the Manufacturer ID for Adesto (1Fh) and the Device ID(17h) are shifted out on the falling edge of

SCK with most significant bit (MSB) first as shown in Figure 7-42 and Figure 7-43. If the 24-bit address is initially set to

000001h the Device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device ID can

be read continuously, alternating from one to the other. The instruction is completed by driving CS high.

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Figure 7-42. Read Manufacturer/ Device ID instruction (SPI Mode)

Figure 7-43. Read Manufacturer/ Device ID instruction (QPI Mode)

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7.26 Read Manufacturer / Device ID Dual I/O (92h)

The Read Manufacturer/ Device ID Dual I/O instruction provides both the JEDEC assigned manufacturer ID and the

specific device ID.

The Read Manufacturer/ Device ID instruction is very similar to the Fast Read Dual I/O instruction. The instruction is

initiated by driving the CS pin low and shifting the instruction code “92h” followed by a 24-bit address (A23-A0) of

000000h. After which, the Manufacturer ID for Adesto (1Fh) and the Device ID(17h) are shifted out on the falling edge of

SCK with most significant bit (MSB) first as shown in Figure 7-44. If the 24-bit address is initially set to 000001h the

Device ID is read first and then followed by the Manufacturer ID. The Manufacturer and Device ID can be read

continuously, alternating from one to the other. The instruction is completed by driving CS high.

Figure 7-44. Read Dual Manufacturer/ Device ID Dual I/O instruction (SPI Mode)

7.27 Read Manufacturer / Device ID Quad I/O (94h)

The Read Manufacturer/ Device ID Quad I/O instruction provides both the JEDEC assigned manufacturer ID and the

specific device ID.

The Read Manufacturer/ Device ID instruction is very similar to the Fast Read Quad I/O instruction. The instruction is

initiated by driving the CS pin low and shifting the instruction code “94h” followed by a 24-bit address (A23-A0) of

000000h. After which, the Manufacturer ID for Adesto (1Fh) and the Device ID(17h) are shifted out on the falling edge of

SCK with most significant bit (MSB) first as shown in Figure 7-45. If the 24-bit address is initially set to 000001h the

Device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device ID can be read

continuously, alternating from one to the other. The instruction is completed by driving CS high.

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Figure 7-45. Read Quad Manufacturer/ Device ID Quad I/O instruction (SPI Mode)

JEDEC ID (9Fh)

For compatibility reasons, the AT25SF641 provides several instructions to electronically determine the identity of the

device. The Read JEDEC ID instruction is congruous with the JEDEC standard for SPI compatible serial flash memories

that was adopted in 2003. The instruction is entered by driving the CS pin low with following the instruction code “9Fh”.

JEDEC assigned Manufacturer ID byte for Adesto (1Fh) and two Device ID bytes, Memory Type (ID-15-ID8) and

Capacity (ID7-ID0) are then shifted out on the falling edge of SCK with most significant bit (MSB) first shown in Figure

7-46 and Figure 7-47. For memory type and capacity values refer to Manufacturer and Device Identification table. The

JEDEC ID can be read continuously. The instruction is terminated by driving CS high.

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Figure 7-46. Read JEDEC ID instruction (SPI Mode)

Figure 7-47. Read JEDEC ID instruction (QPI Mode)

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7.28 Enable QPI (38h)

The AT25SF641 support both Standard/Dual/Quad Serial Peripheral interface (SPI) and Quad Peripheral Interface

(QPI). However, SPI mode and QPI mode cannot be used at the same time. The ‘Enable QPI’ instruction is the only way

to switch the device from SPI mode to QPI mode.

In order to switch the device to QPI mode, the Quad Enable (QE) bit in Status Register 2 must be set to 1 first, and an

Enable QPI instruction must be issued. If the Quad Enable (QE) bit is 0, the Enable QPI instruction will be ignored and

the device will remain in SPI mode.

After power-up, the default state of the device is SPI mode. See the instruction Set Table 7-2 for all the commands

supported in SPI mode and the instruction Set Table 7-5 for all the instructions supported in QPI mode.

When the device is switched from SPI mode to QPI mode, the existing Write Enable and Program/Erase Suspend status,

and the Wrap Length setting will remain unchanged.

Figure 7-48. Enable QPI instruction (SPI Mode only)

7.29 Disable QPI (FFh)

By issuing Disable QPI (FFh) instruction, the device is reset SPI mode. When the device is switched from QPI mode to

SPI mode, the existing Write Enable Latch (WEL) and Program/Erase Suspend status, and the Wrap Length setting

remains unchanged.

Figure 7-49. Disable QPI instruction for QPI mode

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7.30 Word Read Quad I/O (E7h)

The Quad I/O dramatically reduces instruction overhead allowing faster random access for code execution (XIP) directly

from the Quad SPI. The Quad Enable bit (QE) of Status Register-2 must be set to enable the Word Read Quad I/O

instruction. The lowest Address bit (A0) must equal 0 and only two dummy clocks are required prior to the data output.

Continuous Read Mode

The Word Read Quad I/O instruction can further reduce instruction overhead through setting the “Continuous Read

Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 7-50. The upper nibble of the (M7-4)

controls the length of the next Word Read Quad I/O instruction through the inclusion or exclusion of the first byte

instruction code. The lower nibble bits of the (M[3:0]) are don’t care (“X”). However, the IO pins should be high-

impedance prior to the falling edge of the first data out clock.

If the “Continuous Read Mode” bits M[7-4] = Ah, then the next Fast Read Quad I/O instruction (after CS is raised and

then lowered) does not require the E7h instruction code, as shown in Figure 7-51. This reduces the instruction sequence

by eight clocks and allows the Read address to be immediately entered after CS is asserted low. If the “Continuous

Read Mode” bits M[7:4] do not equal to Ah (1,0,1,0) the next instruction (after CS is raised and then lowered) requires

the first byte instruction code, thus returning to normal operation.

Figure 7-50. Word Read Quad I/O instruction (Initial instruction or previous set M7-0 ≠ Axh, SPI Mode)

Figure 7-51. Word Read Quad I/O instruction (Previous instruction set M7-0= Axh, SPI Mode)

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Wrap Around in SPI mode

The Word Read Quad I/O instruction can also be used to access a specific portion within a page by issuing a “Set

Burst with Wrap” (77h) instruction prior to E7h. The “Set Burst with Wrap” (77h) instruction can either enable or disable

the “Wrap Around” feature for the following E7h commands. When “Wrap Around” is enabled, the output data starts at

the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64-byte section,

the output will wrap around to the beginning boundary automatically until CS is pulled high to terminate the instruction.

The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache

afterwards within a fixed length (8/16/32/64-byte) of data without issuing read instructions.

The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to enable or disable

the “Wrap Around” operation while W6-5 is used to specify the length of the wrap around section within a page.

7.31 Set Burst with Wrap (77h)

The Set Burst with Wrap (77h) instruction is used in conjunction with “Fast Read Quad I/O” and “Word Read Quad

I/O” instructions to access a fixed length of 8/16/32/64-byte section within a 256-byte page. Certain applications can

benefit from this feature and improve the overall system code execution performance. Before the device will accept the

Set Burst with Wrap instruction, a Quad enable of Status Register-2 must be executed (Status Register bit QE must

equal 1).

The Set Burst with Wrap instruction is initiated by driving the CS pin low and then shifting the instruction code “77h”

followed by 24 dummy bits and 8 “Wrap Bits”, W7-0. The instruction sequence is shown in Set Burst with Wrap

Instruction Sequence. Wrap bit W7 and W3-0 are not used.

Table 7-6. Set Burst with Wrap W6:W4 Encoding

W6, W5

W4 = 0

W4 = 1(Default)

Wrap Around

Wrap Length

Wrap Around

Wrap Length

00

01

10

11

Yes

8-byte

16-byte

32-byte

64-byte

No

N/A

Once W6-4 is set by a Set Burst with Wrap instruction

instructions will use the W6-4 setting to access the 8/16/32/64

and return to normal read operation, another Set Burst with Wrap instruction should be issued to set W4 = 1

value of W4 upon power on is 1 In the case of a system Reset while W4 = 0 it is recommended that the controller issues a

Set Burst with Wrap instruction or Reset (99h) instruction to reset W4 = 1 prior to any normal Read instructions since

AT25SF641 does not have a hardware Reset Pin

,

all the following “Fast Read Quad I/O” and Word Read Quad I/O

byte section within any page. To exit the “Wrap Around” function

The default

-

.

,

.

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Figure 7-52. Set Burst with Wrap Instruction Sequence

7.32 Burst Read with Wrap (0Ch)

The “Burst Read with Wrap (0Ch)” instruction provides an alternative way to perform the read operation with “Wrap

Around” in QPI mode. The instruction is similar to the “Fast Read (0Bh)” instruction in QPI mode, except the

addressing of the read operation “Wraps Around” to the beginning boundary of the “Wrap Length” once the ending

boundary is reached.

The “Wrap Length” and the number of dummy of clocks can be configured by the “Set Read Parameters (C0h)”

instruction.

Figure 7-53. Burst Read with Wrap instruction (QPI Mode, 80MHz)

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Figure 7-54. Burst Read with Wrap instruction (QPI Mode, 104MHz)

7.33 Set Read Parameters (C0h)

In QPI mode, to accommodate a wide range of applications with different needs for either maximum read frequency or

minimum data access latency, “Set Read Parameters (C0h)” instruction can be used to configure the number of

dummy clocks for “Fast Read (0Bh)”, “Fast Read Quad I/O (EBh)” & “Burst Read with Wrap (0Ch)” instructions, and

to configure the number of bytes of “Wrap Length” for the “Burst Read with Wrap (0Ch)” instruction.

In Standard SPI mode, the “Set Read Parameters (C0h)” instruction is not accepted. The dummy clocks for various Fast

Read instructions in Standard/Dual/Quad SPI mode are fixed, please refer to the instruction. and for details Table 7-2,

Table 7-3, Table 7-4, and Table 7-5. The “Wrap Length” is set by W6-5 bit in the “Set Burst with Wrap (77h)” instruction.

This setting will remain unchanged when the device is switched from Standard SPI mode to QPI mode.

The default “Wrap Length” after a power up or a Reset instruction is 8 bytes

,

the default number of dummy clocks is 4.

Table 7-7. Dummy Clock Encoding

Dummy

Clocks

Maximum

Read Freq.

P5, P4

00

01

10

4

6

80MHz

104MHz

Table 7-8. Wrap Length Encoding

P1, P0

Wrap Length

00

01

10

11

8-bytes

16-bytes

32-bytes

64-bytes

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Figure 7-55. Set Read Parameters instruction (QPI Mode)

7.34 Enable Reset (66h) and Reset (99h)

Because of the small package and the limitation on the number of pins, the AT25SF641 provide a software Reset

instruction instead of a dedicated RESET pin.

Once the Reset instruction is accepted, any on-going internal operations will be terminated and the device will return to

its default power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable

Latch (WEL) status, Program/Erase Suspend status, Continuous Read Mode bit setting, Read parameter setting and

Wrap bit setting.

“Enable Reset (66h)” and “Reset (99h)” instructions can be issued in either SPI mode or QPI mode. To avoid accidental

reset, both instructions must be issued in sequence. Any other instructions other than “Reset (99h)” after the “Enable

(66h)” instruction disables the “Reset Enable” state. A new sequence of “Enable Reset (66h)” and “Reset (99h)” is

needed to reset the device. Once the Reset instruction is accepted by the device takes approximately t_RST= 30us to

reset. During this period, no instruction will be accepted.

Data corruption may happen if there is an on-going or suspended internal Erase or Program operation when Reset

instruction sequence is accepted by device. It is recommended to check the BUSY bit and the SUS bit in Status Register

before issuing the Reset instruction sequence.

Figure 7-56. Enable Reset and Reset Instruction (SPI Mode)

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Figure 7-57. Enable Reset and Reset Instruction (QPI Mode)

7.35 Read Serial Flash Discovery Parameter (5Ah)

The Read Serial Flash Discovery Parameter (SFDP) instruction allows reading the Serial Flash Discovery Parameter

area (SFDP). This SFDP area is composed of 2048 read-only bytes containing operating characteristics and vendor

specific information. The SFDP area is factory programmed. If the SFDP area is blank, the device is shipped with all the

SFDP bytes at FFh. If only a portion of the SFDP area is written to, the portion not used is shipped with bytes in erased

state (FFh). The instruction sequence for the read SFDP has the same structure as that of a Fast Read instruction. First,

the device is selected by driving Chip Select (CS) low. Next, the 8-bit instruction code (5Ah) and the 24-bit address are

shifted in, followed by 8 dummy clock cycles. The bytes of SFDP content are shifted out on the Serial Data Output

(SO) starting from the specified address. Each bit is shifted out during the falling edge of Serial Clock (SCK). The

instruction sequence is shown here. The Read SFDP instruction is terminated by driving Chip Select (CS) High at any

time during data output.

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Figure 7-58. Read SFDP Register Instruction

Table 7-9. SFDP Signature and Headers

Address

(h) Byte

Address

(Bit)

Data (b)

(Bit)

Data (h)

(Byte)

Description

Comment

SFDP Signature

00h

01h

02h

03h

04h

05h

06h

07:00

15:08

23:16

31:24

07:00

15:08

23:16

0101 0011

0100 0110

0100 0100

0101 0110

0000 0110

0000 0001

53h

46h

44h

50h

06h

01h

Start from 00h

Start from 01h

Start from 00h

SFDP Minor Revision

SFDP Major Revision

Number of Parameters

Headers

Reserved

FFh

07h

08h

31:24

07:00

1111 1111

FFh

00h

JEDEC Parameter ID

(LSB) = 00H

0000 0000

JEDEC Parameter ID (LSB)

Start from 00

H

09h

0Ah

0Bh

15:08

23:16

31:24

0000 0110

0000 0001

0001 0000

06h

01h

10h

Parameter Table Minor

Revision

Start from 01H

Parameter Table Major

Revision

Parameter Table Length

(double words)

How many DWORDs in

the parameter table

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Table 7-9. SFDP Signature and Headers (Continued)

Address

(h) Byte

Address

(Bit)

Data (b)

(Bit)

Data (h)

(Byte)

Description

Comment

Parameter Table Pointer

Address of Adesto

Parameter Table

0Ch

0Dh

0Eh

0Fh

07:00

15:08

23:16

31:24

0011 0000

0000 0000

1111 1111

30h

00h

FFh

JEDEC Parameter ID (MSB)

JEDEC Parameter ID (LSB)

JEDEC Parameter ID

(MSB)

:FFH

Adesto Manufacturer ID

Start from 00H

10h

11h

07:00

15:08

0001 1111

0000 0000

1Fh

00h

Parameter Table Minor

Revision

Start from 01H

12h

13h

23:16

31:24

0000 0001

0000 0010

01h

02h

Parameter Table Major

Revision

Parameter Table Length

(double words)

How many DWORDs in

the parameter table

Parameter Table Pointer

(PTP)

Address of Adesto

Parameter Table

14h

15h

16h

17h

07:00

15:08

23:16

31:24

1000 0000

0000 0000

0000 0001

80h

00h

01h

Reserved

FFh

Table 7-10. SFDP Parameters Table 1

Address

(h) Byte

Address

Data (b)

Data (h)

(Byte)

Description

Comment

(Bit)

01:00

02

(Bit)

01

1

01:4KB available

Erase Granularity

11:4KB not available

Write Granularity

0:1Byte, 1:64 bytes or larger

0: Nonvolatile status bit

1: Volatile status bit

Volatile Status Register Block

Protect Bits

30h

E5h

03

0

Volatile Status Register Write

Enable Opcode

0:50H Opcode to enable,

if bit-3 = 1

04

0

Reserved

07:05

15:08

111

Opcode or FFh

31h

0010 0000

20h

4KB Erase Opccde

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Table 7-10. SFDP Parameters Table 1 (Continued)

Address

(h) Byte

Address

(Bit)

Data (b)

(Bit)

Data (h)

(Byte)

Description

Comment

Fast Dual Read Output

(1 -1 -2)

0=Not supported, 1=Supported

16

1

Number of Address Bytes

00:3 Byte only

01:3 or 4 Byte

10:4 Byte only

11:Reserved

18:17

00

Double Transfer Rate (DTR)

Clocking

0=Not supported, 1=Supported

19

20

21

22

0

1

32h

F1h

Fast Dual I/O Read

(1-2- 2)

Fast Quad I/O Read

(1-4-4)

Fast Quad Output Read

(1-1-4)

Reserved

FFh

23

1

33h

34h

35h

36h

37h

31:24

07:00

15:08

23:16

31:24

1111 1111

0000 0011

FFh

03h

Flash Memory Density

Fast Quad I/O (1-4-4)

Number of dummy clocks

04:00

07:05

15:08

20:16

23:21

31:24

04:00

07:05

15:08

00100

010

number of dummy clocks

number of mode bits

Opcode or FFh

38h

39h

3Ah

3Bh

3Ch

3Dh

44h

EBh

08h

6Bh

08h

3Bh

Fast Quad I/O (1-4-4)

Number of mode bits

Fast Quad I/O (1-4-4)

Read Opcode

1110 1011

01000

Fast Quad Output (1-1-4)

Number of dummy clocks

number of dummy clocks

number of mode bits

Opcode or FFh

Fast Quad Output (1-1-4)

Number of mode bits

000

Fast Quad Output (1-1-4)

Read Opcode

0110 1011

01000

Fast Dual Output (1-1-2)

Number of dummy clocks

number of dummy clocks

number of mode bits

Opcode or FFh

Fast Dual Output (1-1-2)

Number of mode bits

000

Fast Dual Output (1-1-2)

Read Opcode

0011 1011

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Table 7-10. SFDP Parameters Table 1 (Continued)

Address

(h) Byte

Address

(Bit)

Data (b)

(Bit)

Data (h)

(Byte)

Description

Comment

Fast Dual I/O (1-2-2)

Number of dummy clocks

20:16

23:21

31:24

00000

100

number of dummy clocks

3Eh

3Fh

80h

Fast Dual I/O (1-2-2)

Number of mode bits

number of mode bits

Opcode or FFh

Fast Dual I/O (1-2-2)

Read Opcode

1011 1011

BBh

Fast Dual DPI (2-2-2)

Reserved

0=Not supported, 1=Supported

0

FFh

03:01

04

111

40h

FEh

Fast Quad QPI (4-4-4)

Reserved

0=Not supported, 1=Supported

1

FFh

07:05

15:08

23:16

31:24

07:00

15:08

111

Reserved

41h

42h

43h

44h

45h

1111 1111

FFh

Reserved

Fast Dual DPI (2-2-2)

Number of dummy clocks

20:16

23:21

31:24

0 0000

000

number of dummy clocks

number of mode bits

Opcode or FFh

46h

00h

Fast Dual DPI (2-2-2)

Number of mode bits

Fast Dual DPI(2-2-2)

Read Opcode

47h

1111 1111

FFh

Reserved

FFh

48h

49h

07:00

15:08

1111 1111

FFh

Fast Quad QPI (4-4-4)

Number of dummy clocks

20:16

23:21

00010

010

number of dummy clocks

number of mode bits

Opcode or FFh

4Ah

4Bh

42h

Fast Quadl QPI (4-4-4)

Number of mode bits

Fast Quad QPI(4-4-4)

Read Opcode

31:24

07:00

1110 1011

EBh

Erase type-1 Size

4KB=2^0Ch,

32KB=2^0Fh,64KB=2^10h;

(2^Nbyte)

4Ch

4Dh

0000 1100

0010 0000

0Ch

20h

Erase type-1 Opcode

Erase type-2 Size

Opcode or FFh

15:08

23:16

31:24

4KB=2^0Ch,

32KB=2^0Fh,64KB=2^10h;

(2^Nbyte)

4Eh

4Fh

0000 1111

0101 0010

0Fh

52h

Opcode or FFh

Erase type-2 Opcode

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Table 7-10. SFDP Parameters Table 1 (Continued)

Address

(h) Byte

Address

(Bit)

Data (b)

(Bit)

Data (h)

(Byte)

Description

Comment

Erase Type-3 Size

4KB=2^0Ch,

32KB=2^0Fh,64KB=2^10h;

(2^Nbyte)

07:00

50h

51h

52h

53h

0001 0000

1101 1000

0000 0000

10h

D8h

00h

FFh

Opcode or FFh

Erase Type-3 Opcode

Erase Type-4 Size

15:08

23:16

4KB=2^0Ch,

32KB=2^0Fh,64KB=2^10h;

(2^Nbyte)

Opcode or FFh

Erase Type-4 Opcode

31:24

03:00

08:04

1111 1111

0011

Erase Maximum/Typical

Ratio

Maximum = 2 * (COUNT + 1) *

Typical

Erase type-1 Typical time

Erase type-1 Typical units

Erase type-2 Typical time

Erase type-2 Typical units

Erase type-3 Typical time

Erase type-3 Typical units

Erase type-4 Typical time

Erase type-4 Typical units

Count or 00h

0 0011

00b: 1ms

01b: 16ms

10b: 128ms

11b: 1s

10:09

15:11

17:16

22:18

24:23

29:25

31:30

01

0110 0

01

Count or 00h

00b: 1ms

01b: 16ms

10b: 128ms

11b: 1s

54h

55h

56h

57h

33h

62h

C9h

00h

Count or 00h

100 10

01

00b: 1ms

01b: 16ms

10b: 128ms

11b: 1s

Count or 00h

00 000

00

00b: 1ms

01b: 16ms

10b: 128ms

11b: 1s

Program Maximum/Typical

Ratio

Maximum = 2 * (COUNT + 1) *

Typical

03:00

07:04

0100

1000

58h

84h

Page Size

2^N bytes

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Table 7-10. SFDP Parameters Table 1 (Continued)

Address

(h) Byte

Address

(Bit)

Data (b)

(Bit)

Data (h)

(Byte)

Description

Comment

Program Page Typical time

Count or 00h

12:08

13

0 1001

1

0: 8us,

1: 64us

Program Page Typical units

Program Byte Typical time,

1st byte

Count or 00h

17:14

18

01 00

0

0: 1us,

1: 8us

Program Byte Typical units,

1st byte

59h

5Ah

5Bh

Program Additional Byte

Typical time

29h

01h

C7h

Count or 00h

22:19

000 0

0: 1us,

1: 8us

Program Additional Byte

Typical units

23

0

Erase Chip Typical time

Erase Chip Typical units

Reserved

Count or 00h

28:24

0 1110

00b: 16ms

01b: 256ms

10b: 4s

30:29

10

11b: 64s

1h

31

1

Prohibited Op during

Program Suspend

see datasheet

03:00

11010

5Ch

ECh

Prohibited Op during Erase

Suspend

see datasheet

07:04

1110

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Table 7-10. SFDP Parameters Table 1 (Continued)

Address

(h) Byte

Address

(Bit)

Data (b)

(Bit)

Data (h)

(Byte)

Description

Reserved

Comment

1h

08

1

Program Resume to

Suspend time

Count of 64us

Count or 00h

12:09

17:13

0 000

11 101

Program Suspend Maximum

time

00b: 128ns,

01b: 1us,

10b: 8us,

11b: 64us

Program Suspend Maximum

units

19:18

01

5Dh

5Eh

5Fh

A1h

07h

3Dh

Erase Resume to Suspend

time

Count of 64us

Count or 00h

23:20

28:24

0000

Erase Suspend Maximum

time

1 1101

00b: 128ns,

01b: 1us,

10b: 8us,

11b: 64us

Erase Suspend Maximum

units

30:29

31

01

0: Program and Erase suspend

supported

Suspend / Resume

supported

0

1: not supported

Opcode or FFh

11b

Program Resume Opcode

Program Suspend Opcode

Resume Opcode

60h

61h

62h

63h

7:0

0111 1010

0111 0101

0111 1010

0111 0101

11

7Ah

75h

7Ah

75h

15:8

23:16

31:24

01:00

Suspend Opcode

Reserved

xxxxx1b: Opcode = 05h, bit-0 =

1 Busy,

64h

F7h

Status Register Busy Polling

xxxx1xb: Opcode = 70h, bit-7 =

0 Busy,

07:02

1111 01

others: reserved

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Table 7-10. SFDP Parameters Table 1 (Continued)

Address

(h) Byte

Address

(Bit)

Data (b)

(Bit)

Data (h)

(Byte)

Description

Comment

Exit Deep Powerdown time

Count or 00h

12:08

0 0010

00b: 128ns,

01b: 1us,

10b: 8us,

11b: 64us

Exit Deep Powerdown units

14:13

01

65h

66h

67h

A2h

D5h

5Ch

22:15

30:23

31

101 0101 1

101 1100 1

0

Exit Deep Powerdown

Opcode

Opcode or FFh

Enter Deep Powerdown

Opcode

0: Deep Powerdown supported,

1: not supported

Deep Powerdown Supported

Disable 4-4-4 Read Mode

Enable 4-4-4 Read Mode

03:00

08:04

1001

0 0001

0: not supported,

Fast Quad I/O Continuous

(0-4-4) supported

09

1

1: Quad I/O 0-4-4 supported

Fast Quad I/O Continuous

(0-4-4) Exit

15:10

19:16

22:20

1111 01

1100

68h

69h

6Ah

19h

F6h

1Ch

Fast Quad I/O Continuous

(0-4-4) Enter

Quad Enable Requirements

(QER)

001

0: not supported,

HOLD or RESET Disable

23

0

1: use Configuration Register

bit-4

Reserved

FFh

6Bh

6Ch

31;24

06:00

07

1111 1111

110 1000

1

FFh

E8h

Status Register Opcode

Reserved

1h

Soft Reset Opcodes

4-Byte Address Exit

4-Byte Address Enter

6Dh

6Eh

6Fh

13:08

23:14

31:24

01 0000

10h

C0h

1100 0000 00

1000 0000

80h

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Table 7-11. SFDP Parameters Table 2

Description

Address

(h) Byte

Address

(Bit)

Data (b)

(Bit)

Data (h)

(Byte)

Comment

1650h: 1.65V,

1700h: 1.70V,

2300h: 2.30V,

2500h: 2.50V,

2700h: 2.70V

80h

81h

0000 0000

0001 0111

00h

27h

VCC Minimum Voltage

VCC Maximum Voltage

15:0

1950h: 1.95V,

3600h: 3.60V,

4000h: 4.00V,

4400h: 4.40V

82h

83h

0000 0000

0011 0110

00h

36h

31:16

10b: use non-volatile

status register

Array Protection Method

01:00

02

10

0

0: power up unprotected,

1: power up protected

Power up Protection default

Protection Disable Opcodes

Protection Enable Opcodes

011b: use status register

00b: not supported,

05:03

08:06

11:09

01 1

0 11

011

84h

85h

DAh

06h

Protection Read Opcodes

Protection Register Erase

Opcode

13:12

15:14

00

01b: Opcodes

3Dh,2Ah,7Fh,CFh,

00b: not supported,

Protection Register Program

Opcode

01b: Opcodes

3Dh,2Ah,7Fh,FCh

Reserved

FFh

86h

87h

23:16

31:24

1111 1111

FFh

88h-FFh

Reserved

7.36 Enter Secured OTP (B1h)

The Enter Secured OTP instruction is for entering the additional 4K-bit secured OTP mode. The additional 4K-bit

secured OTP is independent from main array, which may be used to store unique serial number for system identifier.

After entering the Secured OTP mode, and then follow standard read or program, procedure to read out the data or

update data. The Secured OTP data cannot be updated again once it is lock-down

Please note that Write Status Register-1, Write Status Register-2 and Write Security Register instructions are not

acceptable during the access of secure OTP region. Once security OTP is lock down, only commands related with read

are valid. The Enter Secured OTP instruction sequence is shown in Figure 7-59.

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Figure 7-59. Enter Secured OTP instruction for SPI Mode (left) and QPI Mode (right)

7.37 Exit Secured OTP (C1h)

The Exit Secured OTP instruction is for exiting the additional 4K-bit secured OTP mode. (Please refer to Figure 7-60).

Figure 7-60. Exit Secured OTP instruction for SPI Mode (left) and QPI Mode (right)

7.38 Read Security Register (2Bh)

The Read Security Register can be read the value of Security Register bits at any time (even in program/erase/write

status register-1 and write status register-2 condition) and continuously.

Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory before ex-factory or not.

When it is “0”, it indicates non-factory lock, “1” indicates factory-lock.

Lock-down Secured OTP (LDSO) bit. By writing Write Security Register instruction, the LDSO bit may be set to “1” for

customer lock-down purpose. However, once the bit it set to “1” (Lock-down), the LDSO bit and the 4K-bit Secured OTP

area cannot be updated any more. While it is in 4K-bit Secured OTP mode, array access is not allowed to write.

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62

Table 7-12. Security Register Definition

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

x

LDSO

Secured

OTP

(indicate if

lock- down)

indicator bit

0 = not

Reserved

0 = non

factory

lock

1 = factory

lock

lock-down

1 = lock

down

(cannot

program/

erase OTP)

Volatile

bit

Volatile

bit

Volatile

bit

Volatile

bit

Volatile

bit

Volatile

bit

Non

-

Non

-

Volatile bit

Figure 7-61. Read Security Register instruction (SPI Mode)

Figure 7-62. Read Security Register instruction (QPI Mode)

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7.39 Write Security Register (2Fh)

The Write Security Register instruction is for changing the values of Security Register bits. Unlike Write Status Register,

the Write Enable instruction is not required before writing Write Security Register instruction. The Write Security

Register instruction may change the value of bit 1 (LDSO bit) for customer to lock-down the 4K-bit Secured OTP area.

Once the LDSO bit is set to “1”, the Secured OTP area cannot be updated any more.

The CS must go high exactly at the boundary; otherwise, the instruction is rejected and not executed.

Figure 7-63. Write Security Register instruction for SPI Mode (left) and QPI Mode (right)

7.40 4K-bit Secured OTP

It’s for unique identifier to provide 4K-bit one-time-program area for setting device unique serial number which may

be set by factory or system customer. Please refer to table of “4K-bit secured OTP definition”.

- Security register bit 0 indicates whether the chip is locked by factory or not.

- To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with ENSO command) and going through

normal program procedure, and then exiting 4K-bit secured OTP mode by writing EXSO command

- Customer may lock-down bit1 as “1”. Please refer to “table of security register definition” for security register bit

definition and table of “4K-bit secured OTP definition” for address range definition.

Note. Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit secured OTP

mode, array access is not allowed to write.

Table 7-13. Secured OTP

Standard

Address Range

Size

Customer Lock

000000 ~ 00000F

128-bit

ESN

Determined by customer

(Electrical Serial Number)

000010 ~ 0001FF

3968-bit

N/A

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64

8.

ElectricalCharacteristics

(1)

8.1

Absolute Maximum Ratings

Parameter

Supply Voltage

Symbol

Conditions

Range

Units

VCC

V

-

0.6 to VCC+0.4

Voltage Applied to Any Pin

Transient Voltage on any Pin

V

IO

IOT

Relative to Ground

-0.6 to VCC +0.4

<20nS Transient

-

1.0V to VCC +1.0V

Relative to Ground

Storage Temperature

Lead Temperature

T

STG

˚C

V

-

65 to +150

TLEAD

See Note⁽²⁾

2000 to +2000

Electrostatic Discharge

Voltage

V

ESD

Human

Body Model⁽³⁾

-

Notes:

1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. The “Absolute Maximum

Ratings” are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Voltage extremes referenced in the “Absolute Maximum Ratings” are intended to accommodate short duration undershoot/overshoot conditions

and does not imply or guarantee functional device operation at these levels for any extended period of time.

2. Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and the European directive on restrictions

on hazardous substances (RoHS) 2002/95/EU.

3. JEDEC Std JESD22-A114A (C1=100pF, R1=1500 ohms, R2=500 ohms).

8.2

Operating Ranges

Parameter

Symbol

VCC

Conditions

Min

Max

Units

Erase/Program

Cycles

FR = 104MHz (Single/Dual/Quad SPI)

fR = 50MHz (Read Data 03h)

2.7

3.6

V

Ambient Operating

Temperature

T

A

Industrial

-40

+85

˚C

8.3

Endurance and Data Retention

Parameter

Symbol

Conditions

Min

Cycles

years

Erase/Program Cycles

Data Retention

100,000

4KB Block

, 32/64KB block or full chip.

Full Temperature Range

20

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65

8.4

Power-up Timing and Write Inhibit Threshold

Parameter

VCC (min) to CS Low

Symbol

Min

10

1

Max

Units

µs

(1)

t_VSL

(1)

Time Delay Before Write Instruction

Write Inhibit Threshold Voltage

t_PUW

10

ms

V

VWI⁽¹⁾

1.0

2.3

Note:

1. These parameters are characterized only.

Figure 8-1. Power-up Timing and Voltage Levels

8.5

DC Electrical Characteristics

Parameter

Symbol

CIN⁽¹⁾

COUT⁽¹⁾

ILI

Conditions

VIN = 0V⁽²⁾

Min

Typ

Max

6

Units

Input Capacitance

Output Capacitance

Input Leakage

pF

µA

VOUT = 0V⁽²⁾

8

±2

I/O Leakage

ILO

Standby Current

CS = VCC

ICC1

ICC2

ICC3

10

2

50

µA

VIN = GND or VCC

Power Down Current

CS = VCC

VIN = GND or VCC

Current Read Data/

C=0.1 VCC / 0.9VCC

7

mA

Dual/Quad 1MHz⁽²⁾

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66

8.5

DC Electrical Characteristics (Continued)

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Current Read Data/

ICC3

C = 0.1 VCC / 0.9VCC

IO = Open

15

mA

Dual/Quad 50MHz⁽²⁾

Current Read Data/

ICC3

ICC4

ICC5

ICC6

C = 0.1 VCC / 0.9VCC

IO = Open

18

25

20

25

mA

Dual/Quad 80MHz⁽²⁾

Current Read Data/

C = 0.1 VCC / 0.9VCC

IO = Open

Dual/Quad 104MHz²⁾

Current Write Status

Register

CS = VCC

10

15

Current page Program

Current Block Erase

Current Chip Erase

Input Low Voltages

Input High Voltages

Output Low Voltages

ICC7

VIL

25

mA

V

-0.5

VCC x0.2

VCC +0.4

0.2

VIH

VCC x0.8

V

VOL

VOH

IOL = 100 µA

IOH = -100 µA

V

Output

VCC -0.2

V

High Voltages

Notes:

1. Tested on sample basis and specified through design and characterization data, TA = 25˚C, VCC = 1.8V.

2. Checked Board Pattern.

8.6

AC Measurement Conditions

Parameter

Symbol

Min

Max

Units

C

L

30

5

pF

ns

V

Load Capacitance

T

R,

T

F

Input Rise and Fall Times

Input Pulse Voltages

V

IN

0.2 VCC to 0.8 VCC

0.3 VCC to 0.7 VCC

0.5 VCC to 0.5 VCC

IN

OUT

V

Input Timing Reference Voltages

Output Timing Reference Voltages

V

Note:

1.

Output Hi-Z is defined as the point where data out is no longer driven

AT25SF641

DS-25SF641–111E–3/2018

67

Figure 8-2. AC Measurement I/O Waveform

8.7

AC Electrical Characteristics

Parameter

Symbol

Alt

Min

Typ

Max

104⁽⁶⁾

50

Units

Clock frequency

For all instructions, except Read Data (03h)

1.65V-1.95V VCC and Industrial Temperature

F

R

fc

D.C.

MHz

f

R

D.C.

3.5

MHz

ns

Clock freq. Read Data instruction (03h)

t_CLH

,

Clock High, Low Time except Read Data (03h)

(1)

t_CLL

Clock High, Low Time for Read Data (03h)

instructions

t_CRLH

,

8

ns

(1)

t_CRLL

(2)

t_CLCH

0.1

5

V/ns

ns

Clock Rise Time peak to peak

Clock Fall Time peak to peak

(2)

t_CHCL

t_SLCH

t_CHSL

t_DVCH

t_CHDX

t_CHSH

t_SHCH

t_CSS

CS Active Setup Time relative to Clock

CS Not Active Hold Time relative to Clock

Data In Setup Time

5

ns

t_DSU

t_DH

2

ns

3

ns

Data In Hold Time

5

ns

CS Active Hold Time relative to Clock

CS Not Active Setup Time relative to Clock

5

ns

CS Deselect Time (for Read instructions/ Write,

Erase and Program instructions)

t_SHSL

t_CSH

30

ns

t_SHQZ(2)

t_CLQV

t_CLQX

t_HLCH

t_DIS

t_V1

7

6

7

ns

Output Disable Time

Clock Low to Output Valid

t_V2

Clock Low to Output Valid ( Except Main Read ) ⁽³⁾

Output Hold Time

t_HO

1.5

5

HOLD Active Setup Time relative to Clock

AT25SF641

DS-25SF641–111E–3/2018

68

8.7

AC Electrical Characteristics (Continued)

Parameter

Symbol

t_CHHH

Alt

Min

5

Typ

Max

Units

ns

HOLD Active Hold Time relative to Clock

HOLD Not Active Setup Time relative to Clock

HOLD Not Active Hold Time relative to Clock

HOLD to Output Low-Z

t_HHCH

5

ns

t_CHHL

5

ns

(2)

t_HHQX

t

LZ

7

ns

(2)

t_HLQZ

t

HZ

12

ns

HOLD to Output High-Z

(4)

t_WHSL

20

ns

Write Protect Setup Time Before CS Low

Write Protect Setup Time After CS High

CS High to Power Down Mode

(4)

t_SHWL

100

ns

(2)

3

µs

t_DP

CS High to Standby Mode without Electronic

Signature Read

(2)

t_RES1

µs

CS High to Standby Mode with Electronic

Signature Read

(2)

t_RES2

1.8

(2)

t_SUS

30

15

150

5

µs

ms

µs

ms

s

CS High to next Instruction after Suspend

CS High to next Instruction after Reset

Write Status Register Time

Byte Program Time

(2)

t_RST

t_W

t_BP

5

t_PP

0.6

0.06

0.35

0.7

80

Page Program Time

t_SE

0.4

1.5

2

Block Erase Time (4KB)

t_BE1

t_BE2

t_CE

s

Block Erase Time (32KB)

Block Erase Time (64KB)

Chip Erase Time

s

150

s

Notes:

1. Clock high + Clock low must be less than or equal to 1/fc.

2. Value guaranteed by design and/or characterization, not 100% tested in production.

3. Contains: Read Status Register-1,2/ Read Manufacturer/Device ID, Dual, Quad/ Read JEDEC ID/ Read Security Register/ Read Serial

Flash Discovery Parameter.

4. Only applicable as a constraint for a Write Status Register instruction when Sector Protect Bit is set to 1.

5. Commercial temperature only applies to Fast Read (FR). Industrial temperature applies to all other parameters.

AT25SF641

DS-25SF641–111E–3/2018

69

8.8

Input Timing

8.9

Output Timing

8.10 Hold Timing

AT25SF641

DS-25SF641–111E–3/2018

70

9.

Ordering Information

9.1

Ordering Code Detail

A T 2 5 S F 6 4 1 A – S U B – T

Designator

Shipping Carrier Option

T = Tape and reel

Product Family

Operating Voltage

B = 2.7V to 3.6V

Device Grade

U

= Green, Matte Sn or Sn alloy,

Industrial temperature range

(–40°C to +85°C)

Device Density

641 = 64-megabit

Device Revision

Package Option

= 8-pad, 5 x 6 x 0.75 mm DFN

M

S = 8-lead, 0.208" wide SOIC

CC = 1 mm pitch BGA

U = 0.5mm pitch dBGA

DWF = Die in Wafer Form

Operating

Voltage

Max. Freq.

(MHz)

Ordering Code ⁽¹⁾

Package

8MA1

8S4

Lead Finish

Operation Range

-40 to 85

AT25SF641-MHB-T

AT25SF641-SUB-T

AT25SF641-DWF ⁽²⁾

℃

SnAgCu

2.7V-3.6V

104 MHz

(Industrial

Temperature Range)

DWF

1. The shipping carrier option code is not marked on the devices.

2. Contact Adesto for mechanical drawing or sales information.

Package Type

8-lead, 0.208" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)

8S4

8MA1

DWF

8-pad (5 x 6 x 0.6 mm body), Thermally Enhanced Plastic Ultra-Thin Dual Flat No-lead (UDFN)

Die in Wafer Form

AT25SF641

DS-25SF641–111E–3/2018

71

10. Packaging Information–

10.1 8S4 – 8-lead, 0.208” EIAJ SOIC

MILLIMETERS

INCHES

NOM

0.077

0.006

0.071

0.017

0.008

0.208

0.311

0.208

0.050 BSC

0.026

-

SYMBOL

MIN

1.75

0.05

1.70

0.35

0.19

5.18

7.70

5.18

NOM

1.95

0.15

1.80

0.42

0.20

5.28

7.90

5.28

1.27 BSC

0.65

-

MAX

2.16

0.25

1.91

0.48

0.25

5.38

8.10

5.38

MIN

MAX

0.085

0.010

0.075

0.019

0.010

0.212

0.319

0.212

A

A1

A2

B

0.069

0.002

0.067

0.014

0.007

0.204

0.303

0.204

C

D

E

E1

e

L

0.50

0.80

8˚

0.020

0.031

8˚

Θ

0˚

Y

-

0.10

-

0.004

5/5/16

REV.

DRAWING NO.

GPC

STN

TITLE

®

8S3, 8-lead, 0.208”Body, Plastic Small

Outline Package (EIAJ)

Package Drawing Contact:

contact@adestotech.com

8S3

A

AT25SF641

DS-25SF641–111E–3/2018

72

10.2 8MA1 – UDFN

E

C

Pin 1 ID

SIDE VIEW

D

y

TOP VIEW

A1

A

K

8

E2

Option A

0.45

Pin #1

Cham fer

(C 0.35)

1

2

3

Pin #1 Notch

(0.20 R)

COMMON DIMENSIONS

(Unit of Measure = mm)

(Option B)

MIN

MAX

NOM

NOTE

SYMBOL

7

D2

6

A

0.45

0.55

0.60

e

A1

b

0.00

0.35

0.02

0.40

0.152 REF

5.00

4.00

6.00

3.40

1.27

0.60

–

0.05

0.48

C

D

D2

E

4.90

3.80

5.90

3.20

5.10

4.20

6.10

3.60

5

4

b

BOTTOM VIEW

L

E2

e

L

0.50

0.00

0.20

0.75

0.08

–

y

K

–

4/15/08

GPC

YFG

DRAWING NO.

TITLE

REV.

®

Package Drawing Contact:

contact@adestotech.com

8MA1, 8-pad (5 x 6 x 0.6 mm Body), Thermally

Enhanced Plastic Ultra Thin Dual Flat No Lead

Package (UDFN)

8MA1

D

AT25SF641

DS-25SF641–111E–3/2018

73

11. Revision History

Revision Level – Release Date

History

A – May 2016

Initial release of AT25SF641 data sheet.

Updated part number (was AT25SF641A). Revised to AT25SF641.

Added WLCSP package.

B – June 2016

Corrected memory type and capacity type IDs.

Added device grade H.

Changed AT25SF641-MUB-T to 25SF641-MHB-T.

Updated UDFN package drawing and dimensions.

Updated SFDP tables.

C – November 2016

Updated VWI and ICC3. Updated Section 7-21.

D – February 2017

E - March 2018

Updated Note 1 on Table 8.1.

Removed WLCSP and BGA packages.

Removed 133 MHz references.

Updated Block and Chip erase timing in AC Characteristics table.

AT25SF641

DS-25SF641–111E–3/2018

74

Corporate Office

California | USA

Adesto Headquarters

3600 Peterson Way

Santa Clara, CA 95054

Phone: (+1) 408.400.0578

Email: contact@adestotech.com

Disclaimer: Adesto Technologies Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Adesto's Terms

and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications

detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Adesto are granted by the

Company in connection with the sale of Adesto products, expressly or by implication. Adesto's products are not authorized for use as critical components in life support devices or systems.


型号：	AT25SF641
厂家：	Dialog Semiconductor
描述：	64-Mbit, 2.7V Minimum SPI Serial Flash Memory with Dual I/O, Quad I/O and QPI Support
文件：	总76页 (文件大小：5329K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT25SF641 [DIALOG]

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