DA9062-xxAM1-A_技术文档

DA9062

PMIC for applications requiring up to 8.5 A

General Description

DA9062 is a power management integrated circuit (PMIC) optimized for supplying systems with

single- and dual-core processors, I/O, DDR memory, and peripherals. It targets mobile devices,

medical equipment, IVI systems, and FPGA based applications.

DA9062 features four buck converters providing a total current of 8.5 A. High efficiency is achieved

over a wide load range by using automatic Pulse Frequency Modulation (PFM) mode. All power

switches are integrated, therefore, external Schottky diodes are not required. Furthermore, low-

profile inductors can be used with DA9062. Two of the buck converters can be used in a dual-phase

configuration, and one can be used as a DDR VTT supply. The four LDO regulators with

programmable output voltage provide up to 300 mA.

Dynamic Voltage Control (DVC) allows dynamic control of DA9062 supply voltages according to the

operating point of the system. It is controlled by writing directly to the registers using the I²C

compatible 2-wire interface or the GPIOs.

DA9062 features a programmable power sequencer that handles start-up and shutdown sequences.

Power mode transitions can be triggered with software control, GPIOs, or with the on-key. Several

types of on-key presses can be detected to trigger different power mode transitions.

The Real-Time Clock (RTC), with an external 32 kHz crystal oscillator, provides time keeping and

alarm functions. Additionally, the integrated watchdog timer monitors the system.

Five GPIOs are able to perform system functions, including: keypad supervision, application wakeup,

and timing-controlled external regulators/power switches or other ICs.

DA9062 is also available as an automotive AEC-Q100 Grade 3 version.

Key Features

■

Input voltage 2.8 V to 5.5 V

■

Programmable power mode sequencer

Four buck converters with dynamic voltage

control:

System supply and junction temperature

monitoring

□

Buck1: 0.3 V to 1.57 V, 2.5 A

■

Watchdog timer

Buck2: 0.3 V to 1.57 V, 2.5 A

(can be used in dual-phase configuration

with Buck1)

Five GPIOs

Coin cell/super-capacitor charger

Ultra-low power RTC with alarm

32 kHz oscillator with external crystal

-40 °C to +125 °C junction temperature range

□

Buck3: 0.8 V to 3.34 V, 2 A

Buck4: 0.53 V to 1.8 V, 1.5 A

(can be used as DDR VTT supply)

40-pin QFN 6 mm × 6 mm package, 0.5 mm

pitch (exposed paddle)

■

3 MHz switching frequency

(enables low profile inductors)

■

Automotive AEC-Q100 Grade 3 version

available

Four LDO regulators:

□

LDO1: 0.9 V to 3.6 V, 100 mA

LDO2, LDO3, LDO4: 0.9 V to 3.6 V,

300 mA

Applications

■

Single core application processors

Entry-level FPGAs

■

e-Book readers

Entry-level car infotainment

Datasheet

Revision 3.3

24-Nov-2016

1 of 96

DA9062

PMIC for applications requiring up to 8.5 A

Block Diagram

C_LDOCORE

VDDIO

VDDCORE

VSYS

VDD_BUCK1

L_BUCK1

Buck1

Buck2

Buck3

Buck4

LDO1

C_LDO1

C_BUCK1

C_BUCK2

C_BUCK3

VDD_LDO2

LDO2

C_LDO2

VDD_BUCK2

L_BUCK2

VDD_LDO34

LDO3

C_LDO3

LDO4

C_LDO4

DA9062

VDD_BUCK3

L_BUCK3

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO

VDD_BUCK4

L_BUCK4

(VTT)

nONKEY

nRESETREQ

nRESET

Control

and status

registers

Power

sequencer

C_BUCK4

WD

RTC

VBBAT

Interrupt

control

2-Wire

interface

32 kHz

oscillator

nIRQ

BBAT charger

C_VBBAT

+

-

C_VREF

VREF

IREF

XTAL_IN

XTAL_OUT

R_IREF

SCL SDA

TP

Figure 1: DA9062 Block Diagram

Datasheet

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DA9062

PMIC for applications requiring up to 8.5 A

Contents

General Description ............................................................................................................................ 1

Key Features ........................................................................................................................................ 1

Applications ......................................................................................................................................... 1

Block Diagram ..................................................................................................................................... 2

Contents ............................................................................................................................................... 3

1

Package Information..................................................................................................................... 6

1.1 Pin List................................................................................................................................... 6

1.2 Package Outline Drawing...................................................................................................... 8

2

3

4

Absolute Maximum Ratings ......................................................................................................... 9

Recommended Operating Conditions......................................................................................... 9

Electrical Characteristics ........................................................................................................... 10

4.1 Digital I/O ............................................................................................................................ 10

4.2 Watchdog............................................................................................................................ 11

4.3 2-Wire Interface................................................................................................................... 11

4.4 LDOs ................................................................................................................................... 13

4.4.1

4.4.2

4.4.3

LDO1.................................................................................................................... 13

LDO2, LDO3, LDO4............................................................................................. 14

LDOCORE ........................................................................................................... 15

4.5 Buck Converters.................................................................................................................. 16

4.5.1

4.5.2

4.5.3

Buck1, Buck2....................................................................................................... 16

Buck3................................................................................................................... 18

Buck4................................................................................................................... 20

4.6 Backup Battery Charger...................................................................................................... 23

4.7 32 kHz Crystal Oscillator..................................................................................................... 23

4.8 Internal Oscillator ................................................................................................................ 24

4.9 System Supply Voltage Supervision................................................................................... 24

4.10 Junction Temperature Supervision ..................................................................................... 25

4.11 Current Consumption.......................................................................................................... 25

5

6

Typical Characteristics............................................................................................................... 26

System Block Diagram ............................................................................................................... 29

6.1 DDR Power Management ................................................................................................... 30

7

Functional Description ............................................................................................................... 31

7.1 Control Signals.................................................................................................................... 31

7.1.1

7.1.2

7.1.3

7.1.4

nONKEY .............................................................................................................. 31

nRESETREQ....................................................................................................... 31

nRESET............................................................................................................... 32

nIRQ..................................................................................................................... 32

7.2 2-Wire Interface................................................................................................................... 32

7.2.1

7.2.2

Register Map Paging ........................................................................................... 33

Details of the 2-Wire Protocol.............................................................................. 33

7.3 GPIOs.................................................................................................................................. 35

7.3.1

7.3.2

7.3.3

GPI Functionality ................................................................................................. 36

GPO Functionality................................................................................................ 37

Alternate Functions.............................................................................................. 37

Datasheet

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DA9062

PMIC for applications requiring up to 8.5 A

7.3.4

7.3.5

GPIO Forwarding................................................................................................. 38

Analog Functions................................................................................................. 38

7.4 Dynamic Voltage Control .................................................................................................... 38

7.5 Regulator Voltage A And B Selection ................................................................................. 38

7.6 LDOs ................................................................................................................................... 39

7.6.1

7.6.2

7.6.3

Control ................................................................................................................. 39

Current Limit ........................................................................................................ 39

Output Pull-Down................................................................................................. 39

7.7 Switching Regulators .......................................................................................................... 40

7.7.1

7.7.2

7.7.3

7.7.4

7.7.5

7.7.6

7.7.7

7.7.8

7.7.9

Control ................................................................................................................. 40

Output Voltage Slewing ....................................................................................... 40

Soft-Start.............................................................................................................. 40

Active Discharge.................................................................................................. 40

Peak Current Limit............................................................................................... 40

Operating Mode................................................................................................... 41

Half-Current Mode ............................................................................................... 41

Buck1 and Buck2 in Dual-Phase Mode............................................................... 41

Buck4 in DDR Memory Bus Termination Mode................................................... 41

7.8 Power Modes ...................................................................................................................... 42

7.8.1

7.8.2

7.8.3

7.8.4

7.8.5

7.8.6

NO-POWER Mode............................................................................................... 43

RTC Mode ........................................................................................................... 43

RESET Mode....................................................................................................... 43

POWERDOWN Mode.......................................................................................... 44

Power-Up, Power-Down, and Shutdown Sequences.......................................... 45

ACTIVE Mode...................................................................................................... 45

7.9 Power Supply Sequencer.................................................................................................... 46

7.9.1

7.9.2

7.9.3

7.9.4

7.9.5

7.9.6

Sub-Sequences ................................................................................................... 47

Regulator Control................................................................................................. 47

GPO Control ........................................................................................................ 48

Wait Step ............................................................................................................. 49

32 kHz Clock Output............................................................................................ 49

Power-Down Disable ........................................................................................... 49

7.10 Junction Temperature Supervision ..................................................................................... 49

7.11 System Supply Voltage Supervision................................................................................... 49

7.12 Backup Battery Charger...................................................................................................... 50

7.13 Real-Time Clock (RTC)....................................................................................................... 50

7.13.1 32 kHz Crystal Oscillator ..................................................................................... 50

7.14 Internal Oscillator ................................................................................................................ 51

7.15 Watchdog............................................................................................................................ 51

8

9

Register Map................................................................................................................................ 52

8.1 Register Page Control......................................................................................................... 52

8.2 Overview ............................................................................................................................. 52

Application Information.............................................................................................................. 55

9.1 Component Selection.......................................................................................................... 55

9.1.1

9.1.2

9.1.3

Resistors.............................................................................................................. 55

Capacitors............................................................................................................ 55

Inductors .............................................................................................................. 56

Datasheet

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DA9062

PMIC for applications requiring up to 8.5 A

9.1.4

9.1.5

Crystal.................................................................................................................. 56

Backup Battery .................................................................................................... 57

9.2 PCB Layout......................................................................................................................... 57

9.2.1

9.2.2

9.2.3

9.2.4

General Recommendations................................................................................. 58

LDOs and Switched Mode Supplies.................................................................... 58

32 kHz Crystal Oscillator ..................................................................................... 58

Optimising Thermal Performance........................................................................ 58

10 Ordering Information .................................................................................................................. 59

Appendix A Register Descriptions .................................................................................................. 60

A.1 PAGE 0 ............................................................................................................................... 60

A.1.1

A.1.2

A.1.3

A.1.4

A.1.5

A.1.6

A.1.7

A.1.8

Page Control........................................................................................................ 60

Power Manager Control and Monitoring.............................................................. 60

IRQ Events .......................................................................................................... 61

IRQ Masks........................................................................................................... 62

System Control .................................................................................................... 63

GPIO Control ....................................................................................................... 66

Power Supply Control.......................................................................................... 69

RTC Calendar and Alarm .................................................................................... 74

A.2 PAGE 1 ............................................................................................................................... 77

A.2.1

A.2.2

A.2.3

Power Supply Sequencer .................................................................................... 77

Power Supply Control.......................................................................................... 82

BBAT Charger Control......................................................................................... 86

A.3 PAGE 2 ............................................................................................................................... 87

A.3.1

A.3.2

Customer Trim and Configuration ....................................................................... 87

Customer Device Specific.................................................................................... 90

Revision History ................................................................................................................................ 93

Datasheet

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DA9062

PMIC for applications requiring up to 8.5 A

1

Package Information

1.1 Pin List

Table 1: DA9062 Pin Description

Pin No.

Pin Name

Type

Description

Table 2

Paddle

1

GND

AO

PS

AO

AIO

AI

Power grounds of the bucks, digital ground

LDO1 output voltage

VLDO1

2

VLDO2

LDO2 output voltage

3

VDD_LDO2

IREF

LDO2 supply

4

Reference current

5

VREF

Reference voltage

6

XTAL_IN

VSS_ANA

XTAL_OUT

VLDO3

Crystal connection

7

GND

AO

PS

AO

DIO

DI

Analog ground

8

Crystal connection

9

LDO3 output voltage

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

VDD_LDO34

VLDO4

LDO3 and LDO4 supply

LDO4 output voltage

VBBAT

Backup battery connection

Data signal of the 2-wire interface

Clock signal of the 2-wire interface

Input for power-on key

Reset request input

SDA

SCL

nONKEY

nRESETREQ

VLX_BUCK4

VDD_BUCK4

VDD_BUCK3

VLX_BUCK3

GPIO0

DI

AO

PS

AO

DIO

PS

AI

Switching node of Buck4

Buck4 supply

Buck3 supply

Switching node of Buck3

General purpose I/O, VDDQ reference, WDKICK

General purpose I/O, VTTR

IO supply

GPIO1

VDDIO

VBUCK4

VBUCK3

VBUCK1

VBUCK2

GPIO2

Voltage feedback of Buck4

Voltage feedback of Buck3

Voltage feedback of Buck1

Voltage feedback of Buck2

General purpose I/O, PWR_EN

General purpose I/O

AI

DIO

AO

PS

GPIO3

GPIO4

General purpose I/O, SYS_EN

Switching node of Buck1

Buck1 supply

VLX_BUCK1

VDD_BUCK1

VDD_BUCK2

Buck2 supply

Datasheet

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DA9062

PMIC for applications requiring up to 8.5 A

Pin No.

Pin Name

Type

Description

Table 2

34

35

36

37

38

39

40

VLX_BUCK2_A

VLX_BUCK2_B

TP

AO

DIO

DO

AO

PS

Switching node of Buck2

Test pin

nIRQ

Interrupt signal to host processor

Reset output

nRESET

VDDCORE

VSYS

Internal supply

System supply, LDO1 supply

Table 2: Pin Type Definition

Pin Type

DI

Description

Pin Type

AI

Description

Digital Input

Analog Input

DO

Digital Output

Digital Input/Output

Power Supply

AO

Analog Output

DIO

PS

AIO

Analog Input/Output

Ground connection

GND

Datasheet

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DA9062

PMIC for applications requiring up to 8.5 A

1.2 Package Outline Drawing

Figure 2: DA9062 Package Outline Drawing

Datasheet

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DA9062

PMIC for applications requiring up to 8.5 A

2

Absolute Maximum Ratings

Table 3 lists the absolute maximum ratings of the device. Exceeding these ratings may cause

permanent damage to the device. Device functionality is only guaranteed under the conditions listed

in Sections 3 and 4. Operating the device in conditions exceeding those listed in Sections 3 and 4,

but compliant with the absolute maximum ratings listed in Table 3, for extended periods of time may

affect device reliability.

Table 3: Absolute Maximum Ratings

Parameter

Symbol

Note

Min

-65

-40

Typ

Max

Unit

°C

Storage temperature

Junction temperature

+150

T_J

+150

°C

Note 1

Supply voltage

V_SYS

-0.3

5.5

V

All other

pins

V_SYS+ 0.3

Note 2

ESD protection HBM

ESD protection CDM

V_{ESD_HBM}

V_{ESD_CDM}

2000

750

V

Corner pins

All other pins

500

Note 1 See Sections 4.10 and 7.10 for more details.

Note 2 Voltage must not exceed 5.5 V.

3

Recommended Operating Conditions

Table 4: Recommended Operating Conditions

Parameter

Symbol

Note

Min

Typ

Max

Unit

Operating junction

temperature

T_J

-40

+125

°C

Supply voltage

V_SYS

0

5.5

3.6

V

Supply voltage IO

V_DDIO

IO supply voltage

Note 1

1.2

Maximum power

dissipation Note 2

P_DISS

Derating factor above

T_A= 70 °C: 56 mW/°C

3000

mW

Note 1 V_DDIOmust not exceed V_SYS

.

Note 2 Obtained from package thermal simulation, board dimension 76 mm x 114 mm x 1.6 mm (JEDEC), 6-

layer board, 35 μm thick copper top/bottom layers, 17 μm thick copper inside layers, natural

convection (still air).

Datasheet

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DA9062

PMIC for applications requiring up to 8.5 A

4

Electrical Characteristics

4.1 Digital I/O

Unless otherwise noted, the following is valid for T_J= -40 °C to +125 ºC, V_SYS= 2.8 V to 5.5 V.

Table 5: Digital I/O Electrical Characteristics

Parameter

Symbol

Test Conditions

VDDCORE mode

VDDIO mode

Min

1.0

Typ

Max

V_SYS

Unit

Input high voltage

(GPI0-GPI4,

nRESETREQ)

V_IH

V

0.7 * V_DDIO

Input low voltage

(GPI0–GPI4,

nRESETREQ)

V_IL

V_IH

VDDCORE mode

VDDIO mode

-0.3

0.4

V

0.3 * V_DDIO

Input high voltage

(nONKEY)

RTC mode

1.0

V_SYS

VDDCORE mode

VDDIO mode

RTC mode

0.7 * V_DDIO

-0.3

Input low voltage

(nONKEY)

V_IL

0.4

V

VDDCORE mode

VDDIO mode

VDDCORE mode

VDDIO mode

VDDCORE mode

VDDIO mode

-0.3

0.3 * V_DDIO

Input high voltage

(SCL, SDA)

V_IH

V_IL

1.0

V

0.7 * V_DDIO

Input low voltage

(SCL, SDA)

0.4

0.3 * V_DDIO

Output high voltage

(GPO0–GPO4,

V_OH

I_LOAD= 1 mA

Push-pull mode

0.7 * V_DDIO

nRESET, nIRQ)

Output low voltage

(GPO0–GPO4,

nRESET, nIRQ)

V_OL

I_LOAD= 1 mA

0.3

V

Output low voltage

(SDA)

V_OL

I_LOAD= 20 mA

I_LOAD= 3 mA

0.4

0.24

Source current capability

(GPO0–GPO4)

I_OH

V_OUT= 0.7 * V_DDIO

V_DDIO≥ 1.8 V

-1

1

mA

pF

Sink current capability

(GPO0–GPO4)

I_OL

V_OUT= 0.3 V

Input capacitance

(SCL, SDA)

C_IN

R_PD

R_PU

10

Pull-down resistance

(GPI0–GPI4)

50

100

250

kΩ

k

Pull-up resistance

(GPO0–GPO4)

V_DDIO= 1.5 V

V_DDIO= 1.8 V

V_DDIO= 3.3 V

60

45

20

180

120

40

310

190

60

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DA9062

PMIC for applications requiring up to 8.5 A

4.2 Watchdog

Unless otherwise noted, the following is valid for T_J= -40 °C to +125 ºC, V_SYS= 2.8 V to 5.5 V.

Table 6: Watchdog Electrical Characteristics

Parameter

Symbol

Test Conditions

Min

Typ

Max Unit

Minimum watchdog time

t_WDMIN

External 32 kHz oscillator

110

200

ms

s

Internal 25 kHz oscillator

External 32 kHz oscillator

Internal 25 kHz oscillator

Maximum watchdog time

t_WDMAX

2

2.5

s

Minimum assert time of

WDKICK

t_WDKICKMIN

150

µs

4.3 2-Wire Interface

START

ACK

STOP

t_F

t_R

V_IH

V_IL

SDA

SCL

t_F

t_{SU_D}

t_{H_D}

t_HIGH

t_{VD_D}

t_{VD_ACK}

t_{SU_STO}

V_IH

V_IL

t_{H_STA}

1/f_SCL

t_LOW

Figure 3: 2-Wire Interface Timing

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DA9062

PMIC for applications requiring up to 8.5 A

Unless otherwise noted, the following is valid for T_J= -40 °C to +125 ºC, V_SYS= 2.8 V to 5.5 V.

Table 7: 2-Wire Interface Electrical Characteristics

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Bus free time

t_BUF

0.5

µs

STOP to START

Bus line capacitive load

Standard/Fast/Fast+ Mode

SCL clock frequency

C_B

150

pF

f_SCL

Note 1

0

1000

kHz

µs

ns

µs

Start condition set-up time

Start condition hold time

SCL low time

t_{SU_STA}

t_{H_STA}

t_{W_CL}

t_{W_CH}

0.26

0.5

SCL high time

0.26

2-WIRE SCL and SDA rise time t_R

(input requirement)

1000

300

2-WIRE SCL and SDA fall time

Data set-up time

t_F

t_{SU_D}

t_{H_D}

50

0

Data hold-time

Data valid time

t_{VD_D}

t_{VD_ACK}

t_{SU_STO}

0.45

Data valid time acknowledge

Stop condition set-up time

0.26

0

High Speed Mode

SCL clock frequency

f_SCL

Requires V_DDIO≥ 1.8 V

3400

kHz

Note 1

Start condition set-up time

Start condition hold time

SCL low time

t_{SU_STA}

t_{H_STA}

t_{W_CL}

t_{W_CH}

t_R

160

60

ns

SCL high time

2-wire SCL and SDA rise time

2-wire SCL and SDA fall time

Data set-up time

(input requirement)

160

t_F

t_{SU_D}

t_{H_D}

10

0

Data hold-time

Stop condition set-up time

t_{SU_STO}

160

Note 1 Minimum clock frequency is 10 kHz if 2WIRE_TO is enabled.

Datasheet

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DA9062

PMIC for applications requiring up to 8.5 A

4.4 LDOs

4.4.1

LDO1

Unless otherwise noted, the following is valid for T_J= -40 °C to +125 ºC.

Table 8: LDO1 Electrical Characteristics

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Input voltage

V_DD

V_DD= V_SYS

2.8

5.5

V

(Internally connected)

Maximum output current I_{OUT_MAX}

100

0.9

mA

V

Output voltage

V_LDO

Programmable in 50 mV steps

3.6

Output accuracy

I_OUT= I_{OUT_MAX}

-3%

+3%

including static line/load

regulation

Stabilisation capacitor

Output capacitor ESR

C_OUT

Including voltage and

temperature coefficient

-55%

0

1.0

+35%

300

µF

R_{COUT_ESR}f > 1 MHz

including wiring parasitics

mΩ

Short circuit current

Dropout voltage

I_SHORT

200

100

mA

mV

V_DROPOUT

V_LDO= 3.3 V

I_OUT= I_{OUT_MAX}

150

20

Static line regulation

V_{S_LINE}

V_DD= 3.0 V to 5.5 V

I_OUT= I_{OUT_MAX}

5

mV

Static load regulation

V_{S_LOAD}

V_{TR_LINE}

I_OUT= 1 mA to I_{OUT_MAX}

5

20

mV

Line transient response

V_DD= 3.0 V to 3.6 V

I_OUT= I_{OUT_MAX}

tr = tf = 10 µs

Load transient response

V_{TR_LOAD}

V_DD= 3.6 V, V_LDO= 3.3 V

I_OUT= 1 mA to I_{OUT_MAX}

tr = tf = 1 µs

30

50

mV

Power supply rejection

ratio

PSRR

V_DD= 3.6 V

V_DD- V_LDO≥ 0.6 V

I_OUT= I_{OUT_MAX}/2

f = f_{VDD_LDO}

f = 10 Hz to 10 kHz

40

60

70

dB

Output noise

N

V_DD= 3.6 V, V_LDO= 2.8 V

I_OUT= 5 mA to I_{OUT_MAX}

f = 10 Hz to 100 kHz

μV

rms

T_A= 25 ºC

Quiescent current in

ON mode

I_{Q_ON}

I_{Q_SLEEP}

I_{Q_OFF}

t_ON

9 +

0.9% I_OUT

μA

μs

Quiescent current in

SLEEP mode

T_A= 25 ºC

1.5 +

1.6% I_OUT

Quiescent current in

OFF mode

V_LDO< 0.5 V

T_A= 25 ºC

1

Turn-on time

10 % to 90 %

SLEEP mode

350

450

1

Turn-off time

t_OFF

90 % to 10%

ms

Pull-down enabled

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DA9062

PMIC for applications requiring up to 8.5 A

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Pull-down resistance in

OFF mode

R_OFF

V_LDO= 0.5 V

Can be disabled via

LDO1_PD_DIS

100

Ω

4.4.2

LDO2, LDO3, LDO4

Unless otherwise noted, the following is valid for T_J= -40 °C to +125 ºC.

Table 9: LDO2, LDO3, LDO4 Electrical Characteristics

Parameter

Symbol

Test Conditions

Min

2.8

Typ

Max

Unit

Input voltage

V_DD

V_DD= V_SYS

5.5

V

Supplied from buck converter

1.5

Maximum output current I_{OUT_MAX}

V_DD≥ 1.8 V

(I_OUT= I_{OUT_MAX}/3 V_DD< 1.8 V)

300

mA

V

Output voltage

V_LDO

Programmable in 50 mV steps

0.9

3.6

Output accuracy

I_OUT= I_{OUT_MAX}

-3%

+3%

including static line/load

regulation

Stabilisation capacitor

Output capacitor ESR

C_OUT

Including voltage and

temperature coefficient

-55%

0

2.2

+35%

300

µF

R_{COUT_ESR}f > 1 MHz

including wiring parasitics

mΩ

Short circuit current

Dropout voltage

I_SHORT

600

100

mA

mV

V_DROPOUT

I_OUT= I_{OUT_MAX}

(V_DD< 1.8 V I_OUT= I_{OUT_MAX}/3)

Note 1

150

20

Static line regulation

V_{S_LINE}

V_DD= 3.0 V to 5.5 V

I_OUT= I_{OUT_MAX}

5

mV

Static load regulation

V_{S_LOAD}

V_{TR_LINE}

I_OUT= 1 mA to I_{OUT_MAX}

5

20

mV

Line transient response

V_DD= 3.0 V to 3.6 V

I_OUT= I_{OUT_MAX}

t_R= t_F= 10 µs

Load transient response

V_{TR_LOAD}

V_DD= 3.6 V

30

50

mV

I_OUT= 1 mA to I_{OUT_MAX}

t_R= t_F= 1 µs

Power supply rejection

ratio

PSRR

V_DD= 3.6 V

V_DD- V_LDO≥ 0.6 V

I_OUT= I_{OUT_MAX}/2

f = f_{VDD_LDO}

f = 10 Hz to 1 kHz

f = 1 kHz to 10 kHz

f = 10 kHz to 100 kHz

70

60

40

80

70

50

dB

Output noise

N

V_DD= 3.6 V, V_LDO= 2.8 V

I_OUT= 5 mA to I_{OUT_MAX}

f = 10 Hz to 100 kHz

50

μV

rms

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Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Quiescent current in

ON mode

I_{Q_ON}

T_A= 25 ºC

9 +

0.34% I_OUT

μA

Quiescent current in

SLEEP mode

I_{Q_SLEEP}

I_{Q_OFF}

T_ON

T_A= 25 ºC

2 +

0.7% I_OUT

μA

µs

Quiescent current in

OFF mode

V_LDO< 0.5 V

T_A= 25 ºC

1

Turn-on time

10 % to 90 %

SLEEP mode

200

300

1

Turn-off time

T_OFF

R_OFF

90 % to 10 %

Pull-down enabled

ms

Pull-down resistance in

OFF mode

V_LDO= 0.5 V

Can be disabled via

LDO<x>_PD_DIS

100

Ω

Note 1 At V_DD= 1.8 V, the dropout voltage at I_{OUT_MAX}increases by 70%.

4.4.3

LDOCORE

Unless otherwise noted, the following is valid for T_J= -40 °C to +125 ºC, V_SYS= 2.8 V to 5.5 V.

Table 10: LDOCORE Electrical Characteristics

Parameter

Symbol

Test Conditions

Note 1

Min

Typ

Max

Unit

Output voltage

V_DDCORE

2.45

2.5

2.55

V

RESET mode

2.2

V

Stabilisation capacitor

Output capacitor ESR

Dropout voltage

C_OUT

Including voltage and

temperature coefficient

-55%

0

+35%

300

µF

R_{COUT_ESR}f > 1 MHz

including wiring parasitics

mΩ

V_DROPOUT

Note 2

50

100

mV

Note 1 Setting V_{DD_FAULT_LOWER}≥ 2.65 V avoids LDOCORE dropout, see Section 4.9.

Note 2 The LDOCORE supply, VSYS, must be maintained above V_DDCORE+ V_DROPOUT

.

Note

LDOCORE is only used to supply internal circuits.

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4.5 Buck Converters

4.5.1

Buck1, Buck2

Unless otherwise noted, the following is valid for T_J= -40 °C to +125 ºC.

Table 11: Buck1, Buck2 Electrical Characteristics

Parameter

Symbol

V_DD

Test Conditions

Min

2.8

Typ

Max

5.5

Unit

V

Input voltage

Output capacitor

V_DD= V_SYS

C_OUT

Half-current mode

-50%

2 * 22

+30%

µF

including voltage and

temperature coefficient

Full-current mode

including voltage and

temperature coefficient

-50%

2 * 47

15

+30%

50

Output capacitor ESR

R_{COUT_ESR}

C_OUT= 2 * 22 µF

f > 100 kHz

m

including wiring parasitics

C_OUT= 2 * 47 µF

f > 100 kHz

7.5

25

including wiring parasitics

Inductor value

L_BUCK

Including current and

temperature dependence

0.7

1.0

55

1.3

µH

Inductor resistance

PWM mode

R_{L_DCR}

100

m

Output voltage

V_BUCK

Programmable in 10 mV steps

Note 1

0.3

1.57

+1%

V

Output voltage accuracy

V_{BUCK_ACC}

V_DD= 4.2 V, V_BUCK= 1.03 V

excluding static line/load

regulation and voltage ripple

T_A= 25 ºC

-1%

Including static line/load

regulation and voltage ripple

Note 2

-3%

+3%

45

Transient load regulation V_{TR_LOAD}

V_DD= 3.6 V, V_BUCK= 1.15 V

I_OUT= 200 mA to 1000 mA

dI/dt = 3 A/µs

30

mV

L = 1 µH

Transient line regulation

V_{TR_LINE}

V_DD= 3.0 V to 3.6 V

I_OUT= 500 mA

0.2

3

t_R= t_F= 10 µs

Output current

Current limit

I_OUT

Half-current mode

Full-current mode

1250

2500

2200

mA

I_LIM

Half-current mode

controlled in BUCK<x>_ILIM

in 100 mA steps

700

1400

-20%

Full-current mode

controlled in BUCK<x>_ILIM

in 200 mA steps

4400

Current limit accuracy

I_{LIM_ACC}

I_{Q_OFF}

20%

1

Quiescent current in

OFF mode

µA

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Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Quiescent current in

PWM mode

I_{Q_ON}

Half-current mode

V_DD= 3.6 V

9

mA

I_OUT= 0 mA

T_A= 25 ºC

Full-current mode

V_DD= 3.6 V

11

I_OUT= 0 mA

T_A= 25 ºC

Switching frequency

Note 3

f

OSC_FRQ = ‘0000’

2.85

14%

3

3.15

MHz

ms

Switching duty cycle

Turn-on time

DC

t_ON

83%

1.2

V_BUCK= 1.15 V

0.37

BUCK_SLOWSTART = disabled

SLEW_RATE = 10 mV/1 µs

BUCK<x>_ILIM = 1500 mA

Output pull-down

resistance

R_PD

V_BUCK= 0.5 V

Disabled via BUCK<x>_PD_DIS

100

160

200

Ω

PMOS ON resistance

NMOS ON resistance

R_PMOS

Half-current mode

Including pin and routing

V_DD= 3.6 V

mΩ

Full-current mode

Including pin and routing

V_DD= 3.6 V

80

60

30

R_NMOS

Half-current mode

Including pin and routing

V_DD= 3.6 V

mΩ

Full-current mode

Including pin and routing

V_DD= 3.6 V

PFM mode

Output voltage

V_{BUCK_PFM}

I_{AUTO_THR}

Programmable in 10 mV steps

0.3

1.57

300

V

Mode transition current

threshold (PFM to PWM)

in AUTO mode

V_DD= 3.6 V, V_BUCK= 1.15 V

R_TRACK 45 mΩ including

bondwire, PCB, inductor ESR

400

mA

Output current

Current limit

I_{OUT_PFM}

I_{LIM_PFM}

I_{Q_PFM}

Forced PFM mode

mA

µA

1000

27

Quiescent current

Forced PFM mode

I_OUT= 0 mA

32

42

AUTO mode

I_OUT= 0 mA

35

Mode transition time

t_AUTO

AUTO mode

6

µs

Note 1 If control BUCK<x>_MODE = ‘10’ (Synchronous) then the buck operates in PFM mode for

V_BUCK< 0.7 V. For complete control of the buck mode (PWM versus PFM) use

BUCK<x>_MODE = ‘00’.

Note 2 Minimum tolerance 35 mV.

Note 3 Generated from internal 6 MHz oscillator and can be adjusted by ±10 % via control OSC_FRQ, see

Section 7.14.

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4.5.2

Buck3

Unless otherwise noted, the following is valid for T_J= -40 °C to +125 ºC.

Table 12: Buck3 Electrical Characteristics

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Input voltage

V_DD

V_DD= V_SYS

2.8

5.5

V

I_OUT≤ 1.5 A

V_DD= V_SYS

I_OUT> 1.5 A

3.3

5.5

Output capacitor

Output capacitor ESR

Inductor value

C_OUT

I_OUT≤ 1.5 A

Including voltage and

temperature coefficient

-50%

2 * 22

2 * 47

15

+30%

µF

I_OUT> 1.5 A

Including voltage and

temperature coefficient

-50%

+30%

50

R_{COUT_ESR}

C_OUT= 2 * 22 µF

f > 100 kHz

Including wiring parasitics

m

C_OUT= 2 * 47 µF

f > 100 kHz

Including wiring parasitics

7.5

25

L_BUCK

Including current and

temperature dependence

0.7

1.0

55

1.3

µH

Inductor resistance

PWM Mode

R_{L_DCR}

100

m

Output voltage

V_BUCK

Programmable in 20 mV steps

0.8

3.34

+3%

V

Output voltage accuracy V_{BUCK_ACC}

Including static line and load

regulation and voltage ripple

Note 1

-3%

Transient load regulation V_{TR_LOAD}

V_DD= 3.6 V, V_BUCK= 1.8 V

I_OUT= 200 mA to 1000 mA

dI/dt = 3 A/µs

30

60

0.2

45

90

3

mV

L = 1 µH

V_DD= 3.6 V, V_BUCK= 1.8 V

I_OUT= 200 to 2000 mA

dI/dt = 3 A/µs

L = 1 µH

V_DD= 5.0 V, V_BUCK= 3.34 V

I_OUT= 200 mA to 2000 mA

dI/dt = 3 A/µs

L = 1 µH

Transient line regulation

Output current

V_{TR_LINE}

V_DD= 3.0 V to 3.6 V

I_OUT= 500 mA

tr = tf = 10 µs

mV

mA

I_OUT

V_DD- V_BUCK≥ 1.25 V

V_DD- V_BUCK≥ 1.00 V

V_DD- V_BUCK≥ 0.75 V

2000

1250

900

Current limit

I_LIM

Controlled in BUCK3_ILIM

in 100 mA steps

1700

-20%

3200

mA

Current limit accuracy

I_{LIM_ACC}

20%

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Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Quiescent current in

OFF mode

I_{Q_OFF}

1

µA

Quiescent current in

PWM mode

I_{Q_ON}

f

I_OUT= 0 mA

T_A= 25 ºC

9

3

mA

Switching frequency

Note 2

OSC_FRQ = ‘0000’

2.85

15%

3.15

MHz

Switching duty cycle

Turn-on time

DC

t_ON

100%

1.5

V_BUCK= 1.8 V

0.44

ms

BUCK_SLOWSTART = disabled

SLEW_RATE = 20 mV/2 µs

BUCK3_ILIM = 2500 mA

Output pull-down

resistance

R_PD

V_BUCK= 0.5 V

Disabled via BUCK3_PD_DIS

100

150

60

200

Ω

PMOS ON resistance

R_PMOS

R_NMOS

Including pin and routing

V_DD= 3.6 V

mΩ

NMOS ON resistance

Including pin and routing

V_DD= 3.6 V

PFM Mode

Output voltage

V_{BUCK_PFM}

I_{AUTO_THR}

Programmable in 20 mV steps

0.8

3.34

300

V

Mode transition current

threshold (PFM to PWM)

in AUTO mode

V_DD= 3.6 V, V_BUCK= 1.8 V

R_TRACK 45 mΩ including

bondwire, PCB, inductor ESR

400

mA

Output current

Current limit

I_{OUT_PFM}

I_{LIM_PFM}

I_{Q_PFM}

Forced PFM mode

mA

µA

1000

22

Quiescent current

Forced PFM mode

I_OUT= 0 mA

25

35

AUTO mode

I_OUT= 0 mA

30

6

Mode transition time

t_AUTO

AUTO mode

µs

Note 1 Minimum tolerance 35 mV.

Note 2 Generated from internal 6 MHz oscillator and can be adjusted by ±10 % via control OSC_FRQ, see

Section 7.14.

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4.5.3

Buck4

Unless otherwise noted, the following is valid for T_J= -40 °C to +125 ºC.

Table 13: Buck4 Electrical Characteristics

Parameter

Symbol

V_DD

Test Conditions

Min

2.8

Typ

Max

5.5

Unit

V

Input voltage

Output capacitor

V_DD= V_SYS

C_OUT

Including voltage and

temperature coefficient

-50%

2 * 22

15

+30%

µF

Output capacitor ESR

Inductor value

R_{COUT_ESR}

L_BUCK

f > 100 kHz

Including wiring parasitics

50

1.3

100

m

µH

Including current and

temperature dependence

0.7

1.0

Inductor resistance

PWM Mode

R_{L_DCR}

55

m

Output voltage

V_BUCK

Programmable in 10 mV steps

Note 1

0.53

-3%

1.8

V

Output voltage accuracy

V_{BUCK_ACC}

Including static line/load

regulation and voltage ripple

Note 2

+3%

Transient load regulation V_{TR_LOAD}

V_DD= 3.6 V, V_BUCK= 1.35 V

I_OUT= 200 mA to 1000 mA

dI/dt = 3 A/µs

25

40

60

3

mV

L = 1 µH

V_DD= 3.6 V, V_BUCK= 1.35 V

I_OUT= 200 mA to 1500 mA

dI/dt = 3 A/µs

L = 1 µH

Transient line regulation

Output current

V_{TR_LINE}

V_DD= 3.0 V to 3.6 V

I_OUT= 500 mA

t_R= t_F= 10 µs

0.2

mV

I_OUT

V_DD- V_BUCK≥ 1.25 V

V_DD- V_BUCK≥ 1.00 V

1500

1250

2200

mA

Current limit

I_LIM

Controlled in BUCK4_ILIM

in 100 mA steps

700

Current limit accuracy

I_{LIM_ACC}

I_LIM= 700 mA to 1400 mA

I_LIM= 1400 mA to 2200 mA

-15%

-10%

+25%

+15%

1

Quiescent current in

OFF mode

I_{Q_OFF}

I_{Q_ON}

f

µA

mA

Quiescent current in

PWM mode

I_OUT= 0 mA

T_A= 25 ºC

9

3

Switching frequency

Note 3

OSC_FRQ = ‘0000’

2.85

14%

3.15

MHz

Switching duty cycle

Turn-on time

DC

t_ON

83%

1.2

V_BUCK= 1.35 V

0.39

100

ms

BUCK_SLOWSTART = disabled

SLEW_RATE = 10 mV/1 µs

BUCK4_ILIM = 1500 mA

Output pull-down

resistance

R_PD

V_BUCK= 0.5 V

Disabled via BUCK4_PD_DIS

200

Ω

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Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

PMOS ON resistance

R_PMOS

Including pin and routing

V_DD= 3.6 V

150

mΩ

NMOS ON resistance

R_NMOS

Including pin and routing

V_DD= 3.6 V

60

mΩ

PFM Mode

Output voltage

V_{BUCK_PFM}

I_{AUTO_THR}

Programmable in 10 mV steps.

0.53

1.8

V

Mode transition current

threshold (PFM to PWM)

in AUTO mode

V_DD= 3.6 V, V_BUCK= 1.35 V

R_TRACK 45 mΩ including

bondwire, PCB, inductor ESR

400

mA

Output current

Current limit

I_{OUT_PFM}

I_{LIM_PFM}

I_{Q_PFM}

300

mA

µA

1000

22

Quiescent current

Forced PFM mode

I_OUT= 0 mA

25

35

AUTO mode

I_OUT= 0 mA

30

6

Mode transition time

VTT Mode

t_AUTO

AUTO mode

µs

Input voltage

V_DD

2.8

5.5

V

Output capacitor

C_OUT

Including voltage and

temperature coefficient

-50%

2 * 47

7.5

+30%

µF

Output capacitor ESR

R_{COUT_ESR}

f > 100 kHz

Including wiring parasitics

25

m

Inductor value

L_BUCK

0.25

80

µH

m

V

Inductor resistance

Output voltage

R_{L_DCR}

V_BUCK

120

1.3

V_BUCK= V_DDQ/2

0.675

-3%

Output voltage accuracy

V_{BUCK_ACC}

Relative to VTTR

+4%

Including static line/load

regulation and voltage ripple.

Output current

I_OUT

V_BUCK= 0.675 V

V_BUCK= 0.700 V

V_BUCK= 0.750 V

±450

±550

±700

25

mA

mV

Transient load regulation V_{TR_LOAD}

V_DD= 3.6 V, V_BUCK= 0.675 V

I_OUT= +10 mA to +1.0 A

I_OUT= -450 mA to -10 mA

dI/dt = 3 A/µs

40

50

40

L = 0.25 µH

V_DD= 3.6 V, V_BUCK= 0.675 V

I_OUT= +1 A to +10 mA

I_OUT= -10 mA to -450 mA

dI/dt = 3 A/µs

35

25

L = 0.25 µH

V_DD= 3.6 V, V_BUCK= 0.75 V

I_OUT= +10 mA to +1.0 A

I_OUT= -700 mA to -10 mA

dI/dt = 3 A/µs

L = 0.25 µH

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Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

V_DD= 3.6 V

35

50

V_BUCK= 0.75 V

I_OUT= +1 A to +10 mA

I_OUT= -10 mA to -700 mA

dI/dt = 3 A/µs

L = 0.25 µH

Turn-on time

t_ON

V_BUCK= 0.75 V

0.33

1.2

ms

BUCK_SLOWSTART = disabled

SLEW_RATE = 10 mV/1 µs

BUCK4_ILIM = 1500 mA

VTTR Buffer

Feedback voltage

VTTR output voltage

VTTR voltage accuracy

VTTR output capacitor

V_DDQ

1.35

0.675

-49%

-50%

2.6

1.3

V

V_TTR

V_TTR= V_DDQ/2

V_{TTR_ACC}

C_VTTR

Relative to V_DDQinput voltage

+51%

+30%

Including voltage and

temperature coefficient

0.1

µF

VTTR output current

I_VTTR

Sink/source

-10

+10

mA

Note 1 If control BUCK4_MODE = ‘10’ (Synchronous) then the buck operates in PFM mode for V_BUCK< 0.7 V.

For complete control of the buck mode (PWM versus PFM) use BUCK4_MODE = ‘00’.

Note 2 Minimum tolerance 35 mV.

Note 3 Generated from internal 6 MHz oscillator and can be adjusted by ±10 % via control OSC_FRQ, see

Section 7.14.

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4.6 Backup Battery Charger

Unless otherwise noted, the following is valid for T_J= -40 °C to +125 ºC, V_SYS= 2.8 V to 5.5 V.

Table 14: Backup Battery Charger Electrical Characteristics

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Backup battery

charging current

I_{SET_BCHG}

V_SYS= 3.6 V

V_BBAT= 2.5 V

100

Note 1

6000

µA

Charger termination

voltage

V_{SET_BCHG}

I_SHORT

V_SYS= 3.6 V

1.1

Note 2

6.5

3.1

V

Backup battery short

circuit current

V_BBAT= 0 V

mA

Stabilisation capacitor

Output capacitor ESR

Dropout voltage

C_OUT

-55%

470

+35%

100

nF

m

mV

R_{COUT_ESR}

V_DROPOUT

f > 1 MHz

I_OUT= 5 mA

150

200

Note 1 Can be set in 100 µA steps from 100 µA to 1000 µA and 1 mA steps from 1 mA to 6 mA via

BCHG_ISET in register BBAT_CONT.

Note 2 Can be set in 100/200 mV steps via BCHG_VSET in register BBAT_CONT.

4.7 32 kHz Crystal Oscillator

Unless otherwise noted, the following is valid for T_J= -40 °C to +125 ºC, V_SYS= 2.8 V to 5.5 V.

Table 15: 32 kHz Crystal Oscillator Electrical Characteristics

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Supply voltage

V_DDRTC

Derived from V_BBATor

V_DDCORE

1.5

2.75

V

Oscillator frequency

Clock jitter

f_OSC

32.768

20

kHz

ns

k

pF

s

Cycle to cycle 1000 cycles

V_DDRTC= 1.5 V to 2.75 V

35

Crystal ESR

R_XTAL

C_XTAL

t_START

50

100

Crystal CAP

2

Start-up time

0.5

2

Bypass Mode

Input frequency

Input duty cycle

f_IN

-5%

40%

1.8

32

+5%

60%

V_SYS

kHz

V

DC

V_IH

XTAL_IN

RTC_EN = 0

Input high voltage

RTC_EN = 1

V_{BBAT <}V_SYS

1.1

RTC_EN = 1

V_{BBAT >}V_SYS

0.7 * V_BBAT

-0.3

V_BBAT

XTAL_OUT

V_IL

RTC_EN = 0

0.6

0.4

V

Input low voltage

RTC_EN = 1

V_{BBAT <}V_SYS

RTC_EN = 1

V_{BBAT >}V_SYS

0.2 * V_BBAT

Input slew rate

SR

2 pF input capacitance

0.1

V/ns

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4.8 Internal Oscillator

Unless otherwise noted, the following is valid for T_J= -40 °C to +125 ºC, V_SYS= 2.8 V to 5.5 V.

Table 16: Internal Oscillator Electrical Characteristics

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Oscillator frequency

OSC_FRQ = ‘0000’

5.7

6

6.3

MHz

f_OSC

Note 1 Oscillator frequency can be further adjusted by about ±10 %, see Section 7.14.

4.9 System Supply Voltage Supervision

Unless otherwise noted, the following is valid for T_J= -40 °C to +125 ºC, V_SYS= 2.8 V to 5.5 V.

Table 17: System Supply Voltage Supervision Electrical Characteristics

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Under-voltage

lockout lower

threshold

V_{POR_LOWER}

2.0

V

Under-voltage

lockout upper

threshold

V_{POR_UPPER}

2.3

2.8

V

V_SYSunder-voltage

lower threshold

V_{DD_FAULT_LOWER}

Note 1

2.5

3.25

+2%

V_SYSunder-voltage

lower threshold

accuracy

V_{SYS_LOWER}

-2%

V_SYShysteresis

100

-2%

-1%

200

450

+2%

+1%

mV

V_{DD_FAULT_HYS}

Note 2

V_SYSupper

threshold

V_{DD_FAULT_UPPER}

V_{DD_FAULT_LOWER}

V_{DD_FAULT_HYS}

+

Reference voltage

V_REF

1.2

2.2

V

VREF decoupling

capacitor

C_VREF

µF

Reference current

resistor

R_IREF

-1%

200

+1%

k

Note 1 Can be set in 50 mV steps via control VDD_FAULT_ADJ in register CONFIG_B,

setting V_{DD_FAULT_LOWER}≥ 2.65 V avoids LDOCORE dropout, see Section 4.4.3.

Note 2 Can be set in 50 mV steps via control VDD_HYST_ADJ in register CONFIG_B.

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4.10 Junction Temperature Supervision

Unless otherwise noted, the following is valid for T_J= -40 °C to +125 ºC, V_SYS= 2.8 V to 5.5 V.

Table 18: Junction Temperature Supervision Electrical Characteristics

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

POR temperature

threshold Note 1

T_POR

Note 2

135

150

165

°C

Critical temperature

threshold Note 1

T_CRIT

Note 2

125

110

140

125

155

140

°C

Warning temperature

threshold Note 1

T_WARN

Note 1 See Section 7.10.

Note 2 Thermal thresholds are non-overlapping.

4.11 Current Consumption

Unless otherwise noted, the following is valid for T_J= -40 °C to +125 ºC, V_SYS= 2.8 V to 5.5 V.

Table 19: Current Consumption Electrical Characteristics

Operating Mode

Symbol

Test Conditions

VBBAT

(Typ)

VSYS

(Typ)

Unit

RTC mode

I_DDRTC

V_SYS> 2.0 V

V_BBAT> V_SYS

1.5

1.0

µA

Note 1

V_SYS> 2.0 V

V_BBAT< V_SYS

0.5

7

µA

Note 2

POWERDOWN mode

ACTIVE mode

I_DDPD

V_SYS> 3.0 V

40

LDOCORE enabled

Bucks and LDOs disabled

I_DDACT

Bucks and LDOs enabled

400

µA

Note 1 Maximum current is 2.5 μA for T_A 85 C and V_BBAT 3.1 V.

Note 2 Maximum current is 10 μA for T_A 85 C and V_SYS 5.0 V.

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5

Typical Characteristics

Figure 4: Buck1 Efficiency in AUTO Mode

Figure 5: Buck2 Efficiency in AUTO Mode

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Figure 6: Buck3 Efficiency in AUTO Mode (V_IN= 3.60 V, V_OUT= 1.80 V)

Figure 7: Buck3 Efficiency in AUTO Mode (V_IN= 5.00 V, V_OUT= 3.34 V)

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Figure 8: Buck4 Efficiency in AUTO Mode

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6

System Block Diagram

A block diagram for a typical application is illustrated in Figure 9.

VDD_BUCK1

VDD_BUCK4

VDDQ 1.5 V (2.5 A)

Buck1

Buck4

DDR3

memory

VDDQ(GPIO0)

VTT 0.75 V (±700 mA)

VDD_BUCK2

VDD_BUCK3

0.7 V to 1.57 V (2.5 A)

0.8 V to 3.3 V (2 A)

Buck2

Buck3

DA9062

VSYS

LDOCORE

Application processor

0.9 V to 3.6 V (100 mA)

0.9 V to 3.6 V (300 mA)

LDO1

LDO2

LDO3

LDO4

RTC

VDD_LDO2

VDD_LDO34

BBAT

charger

Coin

cell

Figure 9: DA9062 Typical System Block Diagram

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6.1 DDR Power Management

Using DA9062 for DDR power management is illustrated in Figure 10.

5 V

VDD_BUCK4

Buck1/2

VDD_BUCK1

VDDQ (2.5 A)

Buck

control

VLX_BUCK1

VBUCK1

DAC

VBUCK1

Buck4

VTT (±700 mA)

Buck

control

VLX_BUCK4

VBUCK4

DAC

VDDQ

VTTR (±10 mA)

Figure 10: DA9062 DDR Power Management

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7

Functional Description

7.1 Control Signals

Each of the input signals described below feature a debounce filter. They share a common debounce

time control (DEBOUNCING).

7.1.1

nONKEY

nONKEY is an edge-sensitive signal that controls the power mode of DA9062. Both falling and rising

edges are detected and the time between the edges is measured. This enables different lengths of

key press detection. The detection circuitry is enabled in all power modes of the device.

The status of the signal after debouncing can be read from NONKEY (reg. STATUS_A). The mask

bit M_NONKEY prevents interrupt and wakeup events that would normally be caused by an nONKEY

event.

nONKEY has four modes of operation, see Table 20, which can be selected by NONKEY_PIN.

NONKEY_LOCK controls the wakeup event generation of the nONKEY. If NONKEY_LOCK is

asserted (depends on NONKEY_PIN), a short nONKEY press (shorter than KEY_DELAY) will not

generate a wakeup.

Table 20: nONKEY Functions

NONKEY_PIN Function

00

An event (E_nONKEY) is generated when nONKEY is asserted. If not masked, the event

causes an interrupt. A wakeup is triggered if the device is in POWERDOWN mode.

01

A timer is started when nONKEY is asserted. If the signal is de-asserted before the time

programmed in KEY_DELAY, an event (E_nONKEY) is generated at the rising edge. If the

signal stays asserted and the timer reaches the programmed value, an event is generated and

nONKEY_LOCK is asserted.

10

11

A timer is started when nONKEY is asserted. If the signal is de-asserted before the time

programmed in KEY_DELAY, an event (E_nONKEY) is generated at the rising edge. If the

signal stays asserted and the timer reaches the programmed value, an event is generated,

nONKEY_LOCK is asserted, and a power-down sequence is triggered by automatically

clearing SYSTEM_EN.

A timer is started when nONKEY is asserted. If the signal is de-asserted before the time

programmed in KEY_DELAY, an event (E_nONKEY) is generated at the rising edge,

SYSTEM_EN is cleared, and STANDBY is asserted. If the signal stays asserted and the timer

reaches the programmed value, an event is generated, nONKEY_LOCK is asserted, and

SYSTEM_EN and STANDBY are cleared.

Whenever nONKEY_LOCK is asserted, a long key press (longer than the time programmed in

KEY_DELAY) is required to wakeup from POWERDOWN mode. If the wakeup is also desired after a

short key press, nONKEY_LOCK has to be cleared before entering the POWERDOWN mode.

7.1.2

nRESETREQ

nRESETREQ is an active-low reset request that causes DA9062 to enter RESET mode. The

transition to the RESET mode is handled by the power sequencer and it can be sped up by setting

the HOST_SD_MODE bit. Before entering the RESET mode, a fault log bit is set (nRESETREQ) and

nRESET is asserted.

nRESETREQ should be tied to an always-on rail that is supplied in all modes of the DA9062 such as

VSYS. It is not recommended to tie nRESETREQ to any of the regulator outputs.

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7.1.3

nRESET

nRESET is an active-low reset output intended for resetting the host processor of the system. The

signal can be configured as either push-pull or open drain output (PM_O_TYPE).

nRESET is always asserted upon a cold boot from the no-power mode. It is always asserted at the

beginning of a shutdown sequence to the RESET mode. nRESET may also be asserted at the

beginning of the sequence to the POWERDOWN mode, if configured in control NRES_MODE.

De-assertion of nRESET is controlled by a reset timer. After being asserted, nRESET remains low

until the reset timer, which was started from the selected trigger signal, expires. The reset timer

trigger can be selected via RESET_EVENT and set to one of the following: an external signal

triggering the wakeup (EXT_WAKEUP), an internal signal indicating the end of the first power-up

sub-sequence (SYS_UP), an internal signal indicating the end of the second power-up sub-sequence

(PWR_UP), or the transition of DA9062 from reset to POWERDOWN mode. The expiry time can be

configured via RESET_TIMER from 1 ms to 1 s. If RESET_TIMER is set to 0 ms, nRESET is de-

asserted immediately after the trigger selected with RESET_EVENT.

7.1.4

nIRQ

nIRQ is a level-sensitive interrupt signal. It can be configured either as a push-pull or an open drain

output (selected via PM_O_TYPE). The polarity of nIRQ can be selected with IRQ_TYPE.

nIRQ is asserted when an unmasked event has occurred. The nIRQ will not be released until all

event registers have been cleared. New events that occur while reading an event register are saved

until the event register is cleared, ensuring that the host processor captures them. The same will

happen to all events occurring when the power sequencer is in transition.

7.2 2-Wire Interface

The 2-wire interface provides access to the control and status registers. The interface supports

operations compatible to the standard, fast, fast-plus, and high-speed modes of the I²C bus

specification Rev. 3. Communication on the 2-wire bus is always between two devices; one acting as

the master and the other as the slave. The DA9062 only operates as a slave.

SCL transmits 2-wire clock data and SDA transmits the bidirectional data. The 2-wire interface is

open-drain supporting multiple devices on one line. The bus lines have to be pulled high by an

external pull-up resistor (2 kΩ to 20 kΩ). The attached devices drive the bus lines low by connecting

them to ground. As a result, two devices can drive the bus simultaneously without conflict. In

standard/fast mode the highest frequency of the bus is 400 kHz. The exact frequency can be

determined by the application and it does not have any relation to the DA9062 internal clock signals.

DA9062 stays within the described host clock speed limitations and does not initiate clock slow-

down. An automatic interface reset is triggered when the clock signal ceases toggling for >35 ms

(controlled in TWOWIRE_TO).

When the SDA is stuck, the bus clears after receiving nine clock pulses. Operation in high-speed

mode at 3.4 MHz requires a minimum interface supply voltage of 1.8 V and a mode change in order

to enable slope-control. The high-speed mode can be enabled on a transfer-by-transfer basis by

sending the master code (0000 1XXX) at the beginning of the transfer. The DA9062 does not make

use of clock stretching and delivers read data without delay up to 3.4 MHz.

Alternatively, the interface can be configured to use high-speed mode continuously via PM_IF_HSM,

so that the master code is not required at the beginning of every transfer. This reduces

communication overhead on the bus and limits the attachable bus slaves to compatible devices.

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7.2.1

Register Map Paging

The 2-wire interface has direct access to two pages of the DA9062 register map (up to 256

addresses). The register at address zero on each page is used as a page control register (the LSB of

control PAGE is ignored). Writing to the page control register changes the active page for all

subsequent read/write operations unless an automatic return to page 0 is selected using control

REVERT. Unless REVERT was asserted after modifying the active page, it is recommended to read

back the page control register to ensure that future data exchange is accessing the intended

registers.

DA9062 also offers an alternative way to access register pages which avoids writing explicitly to

PAGE. DA9062 responds to multiple consecutive slave addresses and updates PAGE automatically

based on the slave address. For example, when IF_BASE_ADDR[7:4] = 0xB the slave address

changes PAGE as follows:

Slave address = 0xB0  PAGE = 0x00

Slave address = 0xB2  PAGE = 0x02

7.2.2

Details of the 2-Wire Protocol

All data is transmitted across the 2-wire bus in 8-bit groups. To send a bit, the SDA line is driven at

the intended state while the SCL is low. Once the SDA has settled, the SCL line is brought high and

then low. This pulse on SCL stores the SDA bit in the receiver’s shift register.

A 2-byte serial protocol is used: one address byte and one data byte. Data and address transfer

transmits the MSB first for both read and write operations. All transmissions begin with the START

condition from the master during which the bus is in IDLE state (the bus is free). It is initiated by a

high-to-low transition on the SDA line while the SCL is in high state. A STOP condition is indicated by

a low-to-high transition on the SDA line while the SCL is in high state. The START and STOP

conditions are illustrated in Figure 11.

SDA

SCL

START

Transaction

STOP

Figure 11: Timing of the START and STOP Conditions

DA9062 monitors the 2-wire bus for a valid slave address whenever the interface is enabled. It

responds immediately when it receives its own slave address. This is acknowledged by pulling the

SDA line low during the following clock cycle (white blocks marked with ‘A’ in the following figures).

The protocol for a register write from master to slave consists of a START condition, a slave address,

a read/write-bit, 8-bit address, 8-bit data, and a STOP condition. DA9062 responds to all bytes with

an ACK. A register write operation is illustrated in Figure 12.

P

S

SLAVEadr

7-bits

W

A

REGadr

8-bits

A

DATA

8-bits

A

1-bit

Master to Slave

Slave to Master

S = START condition

P = STOP condition

A = Acknowledge (low)

W = Write (low)

Figure 12: Byte Write Operation

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When the host reads register data the DA9062 first has to access the target register address with

write access and then with read access and a repeated START, or alternatively a second START,

condition. After receiving the data, the host sends NACK and terminates the transmission with a

STOP condition, see Figure 13.

A^*

P

S

SLAVEadr W A REGadr A Sr SLAVEadr

R

A

DATA

8-bits

1-bit

7-bits 1-bit

8-bits

7-bits

S

SLAVEadr W A REGadr

A

P

S

SLAVEadr

R

A

DATA

8-bits

A^*

P

7-bits 1-bit

8-bits

7-bits 1-bit

Master to Slave

Slave to Master

S = START condition

Sr = Repeated START condition

P = STOP condition

A = Acknowledge (low)

A^*= No Acknowledge

W = Write (low)

R = Read (high)

Figure 13: Examples of Byte Read Operations

Consecutive (page) read-out mode is initiated from the master by sending an ACK instead of NACK

after receiving a byte, see Figure 14. The 2-wire control block then increments the address pointer to

the next register address and sends the data to the master. The data bytes are read continuously

until the master sends a NACK followed by a subsequent STOP condition directly after receiving the

data. If a non-existent 2-wire address is read out then the DA9062 will return code zero.

A^*

P

S

SLAVEadr

W

A

REGadr

8-bits

A

Sr SLAVEadr

R

A

DATA

8-bits

A

DATA

8-bits

A

DATA

8-bits

7-bits

1 bit

7-bits 1-bit

S

SLAVEadr

W

A

REGadr

A

P

S

SLAVEadr

R

A

DATA

8-bits

A

DATA

8-bits

A^*

P

7-bits

8-bits

7-bits 1-bit

1-bit

Master to Slave

Slave to Master

A

S = START condition

= Acknowledge (low)

Sr = Repeat START condition

P = STOP condition

A^*= No Acknowledge

W = Write (low)

R = Read (high)

Figure 14: 2-Wire Page Read

The slave address after the repeated START condition must be the same as the previous slave

address.

Consecutive (page) write mode is supported if the master sends several data bytes after sending the

register address. The 2-wire control block then increments the address pointer to the next 2-wire

address, stores the received data, and sends an ACK until the master sends a STOP condition. The

page write mode is illustrated in Figure 15.

S

SLAVEadr

W

A

REGadr

8-bits

A

DATA

A

DATA

8-bits

A

DATA

8-bits

A

……….

Repeated writes

A

P

7-bits 1 bit

8-bits 1-bit

Master to Slave

Slave to Master

A

S = START condition

= Acknowledge (low)

Sr = Repeat START condition

P = STOP condition

A^*= No Acknowledge

W = Write (low)

R = Read (high)

Figure 15: 2-Wire Page Write

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A repeated write mode can be enabled with WRITE_MODE control. In this mode, the master can

execute back-to-back write operations to non-consecutive addresses by transmitting register

addresses and data pairs. The data is stored in the address specified by the preceding byte. The

repeated write mode is illustrated in Figure 16.

S

SLAVEadr

W

A

REGadr

8-bits

A

DATA

A

REGadr

8-bits

A

DATA

8-bits

A

……….

Repeated writes

A

P

7-bits 1 bit

8-bits 1-bit

Master to Slave

Slave to Master

A

S = START condition

= Acknowledge (low)

Sr = Repeat START condition

P = STOP condition

A^*= No Acknowledge

W = Write (low)

R = Read (high)

Figure 16: 2-Wire Repeated Write

If a new START or STOP condition occurs within a message, the bus returns to idle mode.

7.3 GPIOs

DA9062 features five general purpose IO pins. The basic structure of the GPIOs is depicted in

Figure 17. As illustrated, there are several additional functions:

●

analog function

alternate function

forwarding

regulator control

sequencer WAIT_STEP

interrupt and wakeup generation

The GPIOs are operational in POWERDOWN and ACTIVE modes. However, GPIs can be

configured as disabled in POWERDOWN mode in register PD_DIS (control GPI_DIS). In other

modes, the GPIO is disabled and all ports are configured as open drain outputs in high impedance

state. The level transitions on inputs will no longer be detected, but I/O drivers will keep their

configuration and programmed levels.

Alternate

function

Forwarding

output

Sequencer (WAIT_STEP),

regulator control

Analog function

Interrupt

GPIOx_MODE

GPIOx_PIN

GPIOx_TYPE

M_GPIOx

GPIOx_WKUP_MODE

Debounce

GPI

Edge

detection

GPIx

E_GPIOx

Mask

Wakeup

selection

Wakeup

enable

Wakeup

GPIOx_PUPD

GPIOx_PIN

VDDIO

GPIOx_WEN

GPIOx_OUT

GPIOx_PUPD

GPIOx_MODE

GPO OD

Forwarding input

Sequencer

0

1

Output

function

CLK_32K

VDD_FAULT

VDDIO

GPO push-pull

Figure 17: General GPIO Block Diagram

The functionality of a GPIO is configured in GPIO<x>_PIN, as listed in Table 21.

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Table 21: GPIO Functions

GPIO<X>_

Function

GPIO<X>_MOD

E

GPIO<X>_TY GPIO<X>_WKUP_MO GPIO<X>_WEN

PE

DE

0

Alternate

function

No effect

1

GPI

0: Debounce off

1: Debounce on

0: Active low

1: Active high wakeup

0: Edge-sensitive

0: Wakeup

disabled

1: Level-sensitive

1: Wakeup enabled

wakeup

2

3

GPO

0: Output low

1: Output high

No effect

Open drain

GPO

0: Output low

1: Output high

No effect

Push-pull

7.3.1

GPI Functionality

In GPI mode, the polarity of the input can be selected with GPIO<x>_TYPE. A debouncing filter can

be applied on the input signals with a configurable debouncing time (control DEBOUNCING). An

event is generated at the active edge of the input. The active edge is determined by the signal

polarity configured in GPIO<x>_TYPE. The event can be further configured to generate a wakeup via

GPIO<x>_WKUP_MODE and GPIO<x>_WEN. An internal pull-down can be activated for the inputs

in GPIO<x>_PUPD.

A level sensitive wakeup event can also be configured for each GPI via GPIO<x>_WKUP_MODE

and GPIO<x>_WEN. The functionality of the level-sensitive wakeup is described in Table 26.

7.3.1.1

Regulator Control

GPIO1, GPIO2, and GPIO3 can be used for controlling DA9062 regulators. When configured as

GPIs, they can be used to enable regulators or select between their two output voltage settings.

As seen in Figure 17, the regulator control is branched after the GPIO<x>_TYPE control allowing

active edge delegation for the regulator control. Finally, the functionality for the GPI is selected with

the regulator controls BUCK<x>_GPI, LDO<x>_GPI, VBUCK<x>_GPI, and VLDO<x>_GPI.

One GPI can be used to control the same function on multiple regulators simultaneously. When a

regulator is controlled by a GPI, the same function (on/off or voltage selection) can no longer be

controlled by the power supply sequencer. The regulator still responds normally to register writes to

the control bit.

Enable/Disable Control

A GPI is used for enabling/disabling regulators when it is selected in one of the BUCK<x>_GPI or

LDO<x>_GPI controls. A passive to active transition sets the regulator enable bit (BUCK<x>_EN,

LDO<x>_EN), and an active to passive transition clears it.

Output Voltage Control

A GPI is used for the output voltage selection when it is selected in one of the VBUCK<x>_GPI or

VLDO<x>_GPI controls. A passive to active transition sets the voltage selection bit

(VBUCK<x>_SEL, VLDO<x>_SEL), and an active to passive edge clears it.

7.3.1.2

Sequencer WAIT_STEP

GPIO3 can be used for the WAIT_STEP functionality. The power sequencer can be programmed to

wait for either a rising or falling edge of the WAIT_STEP input, see Section 7.9.4. The active edge is

selected from GPIO<x>_TYPE.

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7.3.2

GPO Functionality

The outputs can be configured as push-pull or open drain outputs, see Table 21. An internal pull-up

can be enabled/disabled from GPIO<x>_PUPD (open drain mode). The GPIO<x>_MODE settings

can control the output state.

Instead of controlling the output with GPIO<x>_MODE, a selection of alternatives is available in the

GPIO<x>_OUT controls. These include: the forwarding function, see Section 7.3.4, the power supply

sequencer, see Section 7.9, the 32 kHz clock (OUT_32K), and the status of the supply voltage

supervision (nVDD_FAULT). When the GPIO is configured as an output and GPIO<x>_OUT is set to

0x0, the GPIO<x>_MODE determines the state of the ouput.

7.3.2.1

nVDD_FAULT

nVDD_FAULT gives the status of the system supply monitoring, see Section 7.11. The assertion of

nVDD_FAULT indicates that the main supply input voltage is low (V_SYS< V_{DD_FAULT_UPPER}) and

therefore informs the host processor that the power will soon shut down. It can be configured to drive

a GPO from the GPIO<x>_OUT controls. The driver type (push-pull, open drain) selection and pull-

up resistor control function normally. The GPIO<x>_MODE can be used to invert the incoming

nVDD_FAULT signal.

7.3.2.2

OUT_32K

OUT_32K feeds a buffered 32 kHz clock signal that is derived from the internal oscillator. The signal

output buffer can be controlled either with the power sequencer or manually via EN_32KOUT, and

paused automatically during POWERDOWN mode with the OUT_32K_PAUSE bit.

Glitch-free switching between a 32 kHz clock output and another GPIO configuration is not

guaranteed. Therefore, configuring a GPIO for 32 kHz clock output should only be done in OTP.

However, enabling and disabling the buffer is still dynamic as described above.

7.3.3

Alternate Functions

GPIO0, GPIO2, and GPIO4 can be used for alternate functions. These are digital control signals that

don’t employ the debouncing, event detection, or interrupt generation functions. Only the input buffer

of the GPIO block is employed. The alternate functions of DA9062 are listed in Table 22 and

described in the following subsections. A debouncing filter can be applied also on the alternate

functions with a configurable debouncing time (control DEBOUNCING).

Table 22: GPIO Alternate Input Functions

Gpio

Alternate Function

Description

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

WDKICK

Watchdog kick or disable

-

PWR_EN

-

Power mode control

SYS_EN

7.3.3.1

SYS_EN

SYS_EN (pin GPIO4) controls the SYSTEM_EN bit and thereby the power mode of DA9062. It is

part of the power supply sequencer functionality described in Section 7.9. SYS_EN is an edge-

sensitive signal and its polarity can be chosen in the GPIO4_TYPE control.

Asserting SYS_EN causes an interrupt (E_GPIx) and a wakeup event. De-asserting SYS_EN

triggers a power-down sequence but no interrupt.

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7.3.3.2

PWR_EN

PWR_EN (pin GPIO2) controls the POWER_EN bit and thereby the power mode of DA9062. It is

part of the power supply sequencer functionality described in Section 7.9. PWR_EN is an edge-

sensitive signal and its polarity can be chosen in the GPIO2_TYPE control. A wakeup event can be

generated after assertion of PWR_EN if so configured in GPIO2_WEN.

7.3.3.3

WDKICK

A rising edge of the WDKICK signal resets the watchdog counter. The polarity of the signal can be

chosen in the GPIO0_TYPE control. If the signal is kept asserted, the watchdog is disabled as the

counter is not incremented (WDG_MODE), see Section 7.15.

7.3.4

GPIO Forwarding

GPIO forwarding works between GPIOs 0, 1, 2, and 3. Any of these GPIs can be routed directly to

GPO0, 1, and 3 after debouncing. Forwarding is one of the options for the GPIO<x>_OUT control.

7.3.5

Analog Functions

GPIO0 and GPIO1 can be used as analog IOs. In this case, the normal GPIO functions are disabled.

The analog functions and their corresponding control bits are listed in Table 23.

Table 23: GPIO Analog Functions

Gpio

Analog Function

Control

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

VDDQ

BUCK4_VTT_EN

BUCK4_VTTR_EN

VTTR

-

7.4 Dynamic Voltage Control

All of DA9062’s buck converters can be controlled in several ways to achieve dynamic voltage

control (DVC). The buck converters feature a voltage ramping feature that enables smooth transition

from one voltage setting to another.

All output voltages can be controlled with software via the 2-wire interface (VBUCK<x>_A). The 2-

wire interface is operational when the device is in ACTIVE mode.

7.5 Regulator Voltage A And B Selection

In addition, all regulators feature A and B settings which can be programmed with different voltages

(VBUCK<x>_A, VBUCK<x>_B), one of which is chosen according to the operating mode of the

system (VBUCK<x>_SEL, VLDO<x>_SEL). In addition to the output voltage, the A and B settings

include a bit to force the regulator into SLEEP mode which reduces the quiescent current.

The selection between the A and B settings can be done either with software via the 2-wire interface

or by the power sequencer, see Section 7.9. Furthermore, each regulator can be enabled with a GPI

pin, see Section 7.3.1.1, and the selection between the A and B settings done with another GPI.

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7.6 LDOs

All LDOs employ Dialog Semiconductor’s Smart Mirror™ dynamic biasing technology, see Figure 18,

which maintains high performance over a wide range of operating conditions and a power saving

mode (SLEEP mode) to minimize the quiescent current during very low output current. The circuit

technique offers significantly higher gain bandwidth performance than conventional designs, enabling

higher power supply rejection performance at higher frequencies. PSRR is maintained across the full

operating current range however quiescent current consumption is scaled to demand improved

efficiency when current demand is low.

Vin

Vref

Vout

Cout

Smart Mirror ^TMLDO

ESR

Figure 18: Smart Mirror^TMVoltage Regulator

7.6.1

Control

The LDOs can be enabled by writing directly to a control bit (LDO<x>_EN), controlling it via a GPI,

see Section 7.3.1.1, or assigning it to a power sequencer step, see Section 7.9.2. Each LDO features

two voltage control registers (VLDO<x>_A/VLDO<x>_B) that allow two output voltage pre-

configurations. The active setting can then be selected either with a control bit (VLDO<x>_SEL), via

a GPI, see Section 7.3.1.1, or automatically based on the DA9062 power mode. The SLEEP mode of

the LDOs can be linked to either the A or B setting (LDO<x>_SL_A/LDO<x>_SL_B). Therefore, the

LDO will switch to SLEEP mode when the setting is active.

LDO1 differs from the other LDOs because it can be configured as an always-on regulator. This

means that it is also enabled in RESET mode, see Section 7.8.3.

7.6.2

Current Limit

Each LDO provides over-current detection. The current limit is fixed for each LDO based on their

current capability. If any of the LDOs’ current limit is exceeded for longer than 10 ms, an event,

E_LDO_LIM, is triggered. The status of the limit comparator can be observed from LDO<x>_ILIM

(reg. STATUS_D). If an LDO’s current limit is exceeded for longer than 200 ms, the LDO is

automatically disabled. This shutdown feature can be disabled by clearing the LDO_SD control.

Once disabled due to an over-current, the LDO must be re-enabled by one of the sources described

in Section 7.6.1.

7.6.3

Output Pull-Down

When over-voltage (1.06 * VLDO<x>) occurs, the voltage regulators enable an internal load to

discharge the output back to its configured voltage. This feature can be disabled in

LDO<x>_PD_DIS.

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7.7 Switching Regulators

DA9062 includes four step-down switching regulators operating at 3 MHz. All switching regulators

employ a synchronous topology with an internal NFET, thus eliminating the need for an external

Schottky diode. The output voltage can be set in 10 mV steps (20 mV steps for Buck3) and the

regulation accuracy is ±3 % over the whole operating temperature range. Static line and load

regulation are also considered in this accuracy.

The switching frequency (3 MHz) is high enough to warrant the use of a small 1.0 µH inductor. The

programming of the converter current limit depends on the coil parameters, as illustrated in Table 24.

Table 24: Buck Current Limit

Min. ISAT (mA)

Frequency (MHz)

Buck current limit (mA)

1750

1460

1180

940

3

1500

1200

950

750

7.7.1

Control

The buck can be enabled manually by writing directly to a control register, with an external signal

connected to GPI, see Section 7.3.1.1, or by assigning it to a power sequencer step, see

Section 7.9.2. Each buck converter features two voltage control registers

(VBUCK<x>_A/VBUCK<x>_B) which can be programmed with two different voltages. The active

setting can then be selected via a control bit (VBUCK<x>_SEL), via a GPI, see Section 7.3.1.1, or

automatically based on the power mode of DA9062.

7.7.2

Output Voltage Slewing

To limit in-rush current from the input supply, the buck converters can achieve a new output voltage

with controlled ramping. Ramping is achieved by stepping through all the V_BUCKvalues between the

old and new settings, at a rate defined by SLEW_RATE. The actual output slew rate, in mV/µs, for a

particular buck converter is then defined by the minimum voltage step of that buck and the common

step time programmed in SLEW_RATE. During PFM mode, the negative slew rate is load dependent

and might be lower than the one mentioned above. An event E_DVC_RDY is triggered when all buck

converters have reached their target voltage.

7.7.3

Soft-Start

The buck converter supports two options for starting up. The normal start-up option ramps up the

power rail as fast as possible, typically within 1 ms. This implies a high in-rush current. The slow

start-up is selected by setting BUCK_SLOWSTART, which increases the start-up time and limits the

input current.

7.7.4

Active Discharge

When switching off a buck converter the output rail can be actively discharged. This feature is

enabled by setting BUCK_ACTV_DISCHRG. The discharge is implemented by ramping down the

output voltage using DVC.

7.7.5

Peak Current Limit

All buck converters feature a programmable current limit (BUCK<x>_ILIM). The current limit protects

the inductor and the pass devices from excessive current. If the current limit is exceeded, the buck

continues to run normally but the duty cycle is limited.

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7.7.6

Operating Mode

The operating mode of each converter can be set via the buck control (BUCK<x>_MODE) to

synchronous (PWM), sleep (PFM), or auto. In auto mode the buck converter switches between PWM

and PFM depending on the load current. This mode is recommended for applications that require fast

transitions from synchronous to sleep operation. The current consumption during PWM operation is

10 mA and drops to <1 µA in shutdown.

In addition, the buck mode can be controlled with the A and B setting. If BUCK<x>_SL_B is set, the

buck is forced to SLEEP mode when the B setting is active. Similarly, if BUCK<x>_SL_A is set, the

buck is forced to SLEEP mode when the A setting is active.

7.7.7

Half-Current Mode

Buck1 and Buck2 can operate in half-current mode where the quiescent current is reduced by

disabling half of the pass devices. As the name implies, enabling this option halves the output

current, and therefore, this feature is valuable in applications where quiescent current is critical and

full current is not needed. This feature is controlled with BUCK1_FCM and BUCK2_FCM. If the bit is

asserted (BUCK<x>_FCM = 1), the corresponding buck is in full-current mode and the full current is

available. If the bit is de-asserted, the corresponding buck is in half-current mode. Operating the

bucks in full-current mode requires twice as much output capacitance (2 x 47 µF) as the half-current

mode (2 x 22 µF).

7.7.8

Buck1 and Buck2 in Dual-Phase Mode

Buck1 and Buck2 can be merged as a dual-phase buck, with up to 5 A output current. If enabled in

OTP via BUCK1_2_MERGE, the outputs from both inductors must be routed together. The controls

for Buck2 are automatically disabled in this configuration, except for BUCK2_PD_DIS.

7.7.9

Buck4 in DDR Memory Bus Termination Mode

Buck4 can be used to generate the DDR memory termination voltage, VTT. In this mode, Buck4

tracks the divided VDDQ voltage and it is able to both sink and source current. As described in

Section 7.3.5, GPIO0 can be configured to carry the VDDQ and GPIO1 can be configured to carry

the VTTR signal. The VTTR output provides buffered version of the VDDQ/2 voltage with ±10 mA

source/sink capability (requires 0.1 µF stabilisation capacitor), see Figure 19. When used for memory

termination, Buck4 has to be forced in the synchronous (PWM) mode from the BUCK4_MODE

control. If BUCK4_VTT_EN and BUCK4_VTTR_EN are asserted at the same time, the VTTR

provides a buffered VTT reference, but otherwise Buck4 is running in a normal output voltage control

mode.

VDD_BUCK4

Buck4

BUCK4_VTT_EN

VLX_BUCK4

VTT (±700 mA)

Buck

control

VBUCK4

DAC

VDDQ

GPIO0

VBUCK4

+

-

VTTR (±10 mA)

GPIO1

Figure 19: Buck4 DDR Memory Bus Termination Mode

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Table 25: Buck4 VTT Mode Control

BUCK4_VTT_EN BUCK4_VTTR_EN

Mode

Normal

VTT

Buck4 V_REF

VDAC

GPIO0

Digital I/O

VDDQ

GPIO1

0

1

0

1

0

1

Digital I/O

VTTR

VDAC

VDDQ/2 un-buffered

VDDQ/2 buffered

VDDQ

Digital I/O

VTTR

VTT

VDDQ

7.8 Power Modes

NO-POWER

VDDCORE < VPOR_UPPER

VDDCORE > VPOR_UPPER

Active functions

·

VDDCORE comparator

RTC

Any state

Active functions

·

VDDCORE comparator

32 kHz oscillator

RTC counter

nONKEY

( nONKEY press || RTC alarm) &&

( ! Temp error && ! VSYS error )

RESET

RTC_MODE_SD

Sequence done ||

timeout

Active functions

·

VDDCORE comparator

32 kHz oscillator

RTC counter

nONKEY

Internal supplies

LDO1

Shutdown

sequence

VSYS error

Any state

·

nRESET asserted

time > RESET_DURATION &&

( ! Temp error && ! VSYS error )

nRESETREQ ||

nONKEY (long)

Shutdown

sequence

POWERDOWN

RTC_MODE_PD

Temp error

Any state

Active functions

·

VDDCORE comparator

32 kHz oscillator

RTC counter

nONKEY

Internal supplies

LDO1

Selected supplies

Sequence done ||

timeout

Retry count != 0

Power-down

sequence

Retry count == 0

POWERDOWN

nRESETREQ ||

nONKEY (long)

nONKEY press ||

GPIO wake-up event

Sequence done ||

timeout

(Freeze)

Shutdown

sequence

Power-up

sequence

Sequence done ||

timeout

nONKEY (short) ||

GPIO power-down event ||

Watchdog timeout

nRESETREQ ||

nONKEY (long)

ACTIVE

Active functions

·

VDDCORE comparator

32 kHz oscillator

RTC counter

nONKEY

Internal supplies

All supplies

Watchdog

alive

Watchdog

Figure 20: DA9062 Power Modes (State Transition Conditions Follow C-Language Syntax)

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7.8.1

NO-POWER Mode

The NO-POWER mode is initial state when powering up the DA9062 for the first time. When the

system supply rises above a threshold, DA9062 enters RESET mode.

7.8.2

RTC Mode

The RTC mode is a low-power mode with only a minimum set of functions to maintain the system

time. All supplies are disabled. RTC mode is entered either after a software request or when the

backup battery is the only supply. If enabled in control RTC_MODE_PD, the power sequencer

proceeds automatically from the POWERDOWN state to RTC mode. If the system supply is

removed, DA9062 will also enter RTC mode. Supply recovery will trigger an exit from RTC mode

automatically. DA9062 will exit RTC mode when nONKEY is asserted, or an RTC alarm is raised.

GPIOs are not operational in RTC mode.

7.8.3

RESET Mode

In RESET mode, the internal supplies, and LDO1 (if configured as an always-on supply) are enabled.

All other DA9062 supplies are disabled.

DA9062 is in RESET mode whenever a complete application shutdown is required. RESET mode

can be triggered by the user, a host processor, or an internal event.

RESET mode can be triggered by the user:

●

from a long press of nONKEY (interruptible by host) defined by control SHUT_DELAY.

by pressing a reset switch that is connected to port nRESETREQ (non-interruptible)

RESET mode can be forced from the host processor (non-interruptible):

●

by asserting nRESETREQ (falling edge)

by writing to control SHUTDOWN

DA9062 error conditions that force RESET mode (non-interruptible) are:

●

no WATCHDOG write (WDKICK signal assertion) from the host inside the watchdog time window

(if watchdog was enabled)

●

an under-voltage detected on VSYS (V_SYS< V_{DD_FAULT_LOWER}

)

an internal junction over-temperature

With the INT_SD_MODE, HOST_SD_MODE and KEY_SD_MODE controls, the shutdown

sequences from internal fault, host or user triggered, are individually configured to either implement

the reverse timing of the power-up sequence or transfer immediately to the RESET mode by skipping

any delay from sequencer or dummy slot timers. For the host to determine the reason for the reset a

FAULT_LOG register stores the root cause (either KEY_RESET or NRESETREQ). The host

processor resets this register by writing asserted bits with ‘1’.

KEY_SD_MODE = 1 triggers a complete power on reset (POR) (instead of entering RESET mode)

after the related keys are pressed extendedly.

If an OTP read is aborted, DA9062 enters RESET mode without an asserted bit inside register

FAULT_LOG.

A shutdown sequence to RESET mode will start with the assertion of the nRESET port. After the

sequencer completes the power-down sequence (sequencer position 0), DA9062 continues to

RESET mode with only the following active circuits: LDOCORE (at reduced output voltage 2.2 V),

control interfaces and GPIOs, BCD counter, band-gap and over-temperature/VSYS comparators. All

regulators, except for LDO1 and the backup battery charger, are automatically disabled to avoid

battery drainage. As described in Section 7.1.3, nRESET is always asserted at the beginning of a

shutdown sequence to RESET mode, and remains asserted when DA9062 is in RESET mode.

When entering RESET mode, all user and system events are cleared. The DA9062’s register

configuration will be re-loaded from OTP when leaving the RESET mode (with the exception of

control AUTO_BOOT in case of a VDD_START fault).

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FAULT_LOG, GP_ID_10 to GP_ID_19 and other non-OTP loaded registers, for example the RTC

calendar and alarm, will not be changed when leaving the RESET mode.

Some reset conditions such as writing a ‘1’ to control SHUTDOWN, a watchdog error, or a junction

over-temperature will be automatically cleared. Other reset triggers, such as asserting nRESETREQ,

need to be released to proceed from RESET to POWERDOWN mode. If the application requires

regulators to discharge completely before a power-up sequence, a minimum duration of the RESET

mode can be selected via RESET_DURATION.

If the reset was initiated by a user’s long press of nONKEY, initially only KEY_RESET is set and the

nIRQ port will be asserted. KEY_RESET signals the host that a shutdown sequence is started. If the

host does not then clear KEY_RESET within 1 second by writing a ‘1’ to the related bit in register

FAULT_LOG, the shutdown sequence will complete. When the reset condition has disappeared,

DA9062 requires a supply (V_SYS> V_{DD_FAULT_UPPER}) that provides enough power to start-up from the

POWERDOWN mode.

RESET mode also allows automatic transition to RTC mode where all features of DA9062, except

the RTC oscillator and calendar (including LDOCORE), are disabled. This mode is selected in control

RTC_MODE_SD.

7.8.4

POWERDOWN Mode

The POWERDOWN mode is a low-power state where most of the regulators are disabled. The

transition from active to POWERDOWN mode (and vice versa) is handled by the programmable

sequencer. Entry to POWERDOWN mode from ACTIVE mode is triggered by the de-assertion of

SYSTEM_EN (either via SYS_EN or register access) or by a short press of nONKEY. The

POWERDOWN mode is also passed during start-up and shutdown to RESET mode sequences.

In POWERDOWN mode the internal supplies are enabled, and the control interface and GPIOs are

operational.

The power state machine features a retry counter that limits the number of transitions from

POWERDOWN to ACTIVE under certain conditions. A watchdog timeout triggers POWERDOWN

mode entry, but it does not necessarily clear the conditions that trigger a transition back to the

ACTIVE mode. This could cause an endless loop between the ACTIVE and POWERDOWN modes.

Therefore, after each watchdog timeout the retry counter is decremented, and after the retry counter

reaches zero, DA9062 blocks all wakeup events and stays in POWERDOWN mode. This freeze

function can be regarded as a substate of the POWERDOWN mode that is undetectable from

outside the DA9062.

Table 26 describes the state transitions with a level-sensitive wakeup and the freeze function.

Table 26: State Transitions With a Level-Sensitive (LS) GPI

Current State

LS GPI

SYS_EN

PWR_EN

Freeze

Note 1

Next State

POWERDOWN

SYSTEM

x

0

x

1

0

x

1

x

0

1

x

0

1

x

0

1

0

1

x

0

1

0

1

0

x

POWERDOWN

SYSTEM

ACTIVE

SYSTEM

ACTIVE

POWERDOWN

SYSTEM

ACTIVE

SYSTEM

ACTIVE

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Current State

LS GPI

SYS_EN

PWR_EN

Freeze

Note 1

Next State

ACTIVE

0

x

1

0

1

x

0

1

0

1

x

POWERDOWN

SYSTEM

ACTIVE

SYSTEM

ACTIVE

Note 1 In this table, “Freeze” represents the result of the comparison retry count = 0.

The following events will reset the retry counter and release the state machine from the freeze state:

●

De-assertion of all blocked level-sensitive wakeup conditions

Entry to the RESET mode (over-temperature error, nRESETREQ or long press of nONKEY)

Entry to the RTC mode (system supply error)

The freeze operation is illustrated in Figure 21. Once the freeze state is cleared, DA9062 continues

operating normally. The freeze function can be enabled in the FREEZE_EN register and the number

of retries triggering the freeze can be configured in NFREEZE.

Retry count

Power mode

TWD_ERROR

GPI

1

0

NFREEZE

ACTIVE

POWERDOWN

ACTIVE

The level sensitive

wake-up condition

is blocked

The system

operates normally

upon the next

The watchdog

expires

The level sensitive

wake-up condition

is de-asserted

which resets the

retry count

wake-up event

The retry count is

decremented and

reaches zero

Figure 21: Freeze Function

7.8.5

Power-Up, Power-Down, and Shutdown Sequences

The power-up, power-down, and shutdown sequences, see Figure 20, are handled by the power

supply sequencer, see Section 7.9. All power-up sequences are identical, and the power-down

sequences mirror the power-up sequences.

The shutdown sequences are also identical to the power-down sequence, but after reaching

POWERDOWN mode, the state machine automatically proceeds to RESET mode. The shutdown

sequences caused by an internal error or nRESETREQ can be sped up from the INT_SD_MODE

and HOST_SD_MODE controls: see Section 7.8.3.

7.8.6

ACTIVE Mode

In the ACTIVE mode, all supplies and functions are active. The transition from POWERDOWN to

ACTIVE mode is handled by the programmable sequencer. DA9062 enters ACTIVE mode after the

sequence has completed and the watchdog is enabled (if configured to use watchdog).

Status information can be read from the host processor via the 2-wire interface and DA9062 can flag

interrupt requests to the host via a dedicated interrupt port (nIRQ).

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7.9 Power Supply Sequencer

DA9062 features a programmable Power Supply Sequencer that handles the system power-up,

power-down, and shutdown sequences. The sequencer has a step-up counter, a timer that controls

the step period, and a set of comparators that trigger power-on/off events at specific steps of the

counter. The structure of the sequencer is depicted in Figure 22.

The sequencer is composed of 16 steps, and the step time can be programmed between 32 µs and

8.192 ms. The sequencer will step until it reaches a programmable maximum value (MAX_COUNT),

whereupon an interrupt is issued. At each step, the sequencer will enable all the functions that are

pointing to that particular step.

The power-up and -down sequences cannot be configured separately. When DA9062 is powering

down, the sequencer will execute whatever was configured for the power-up sequence but in reverse

order. Supplies can also be configured to stay on in POWERDOWN mode. In this case, the

sequencer does not disable the regulator but switches to its B-configuration, see Section 7.5.

If any pointer is programmed to a step higher than MAX_COUNT, the function is no longer controlled

by the sequencer. Only the regulator control pointers (LDO<x>_STEP, BUCK<x>_STEP) are allowed

to point to step 0. Setting any other pointer to step 0, effectively disables that function.

POWERDOWN

mode

STANDBY

mode

ACTIVE

mode

Wake-up

Watchdog alive

System

Power

Power1

OTP_RD2

SYSTEM_EN

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Figure 22: Structure of the Power Supply Sequencer

Note

STANDBY mode can only be reached on power-down, not power-up.

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7.9.1

Sub-Sequences

As illustrated in Figure 22, the sequencer is partitioned into three sub-sequences. These three sub-

sequences can be used to define three power modes for the target application and to move between

them in a controlled sequence as a response to control signals or register writes.

The first sub-sequence starts from step 0 and ends at a step defined by the SYSTEM_END pointer.

After the power-up is triggered, DA9062 performs a partial OTP read (OTP_RD2) if OTPREAD_EN is

set. It then waits for control SYSTEM_EN to trigger the first sub-sequence. If SYSTEM_EN is already

set in the OTP the first sub-sequence starts automatically after the power-up trigger. Alternatively,

SYSTEM_EN can be asserted through the SYS_EN input. When the sequencer reaches the

SYSTEM_END step the first sub-sequence is completed and the sequencer starts waiting for control

POWER_EN to trigger the second sub-sequence. If POWER_EN is already set in the OTP, the

sequencer does not stop after the first sub-sequence. Alternatively, POWER_EN can be asserted

through the PWR_EN input or via a register access.

The second sub-sequence starts from the step following SYSTEM_END and stops at a step defined

by the POWER_END pointer. When the sequencer reaches the POWER_END step (and the

watchdog is active), DA9062 enters ACTIVE mode. The final sub-sequence is triggered by asserting

POWER1_EN via a register write. The third sub-sequence starts from the step following

POWER_END and stops at a step defined by the MAX_COUNT pointer. If MAX_COUNT points to an

earlier step than SYSTEM_END or POWER_END the remaining steps of the sequencer are

disabled.

The power-down sequences are executed in reverse order to the power-up sequences. If the power-

down sequence is triggered from the ACTIVE mode by de-asserting POWER_EN, the sequencer

stops after reversing to the SYSTEM_END step. However, if the power-down sequence is triggered

by de-asserting SYSTEM_EN, the sequencer does not stop and reverses back to step 0.

Furthermore, if the power-down sequence is triggered by a watchdog timeout, the sequencer

reverses to step 0 immediately.

A partial power-down can be achieved by setting control STANDBY. This makes the sequencer stop

at the step pointed to by the PART_DOWN pointer. The next power-up will then start from the

PART_DOWN step, instead of step 0. The PART_DOWN pointer has to point to a step smaller than

the SYSTEM_END pointer.

7.9.2

Regulator Control

Each of DA9062’s buck converters and LDOs can be assigned to any of the sequencer steps. In

general, when the sequencer reaches a step to which a regulator is assigned, that regulator is

enabled by the sequencer. Likewise, when the sequencer reaches the same step on the way down,

the regulator is disabled. Multiple supplies can point to the same counter step, however, enabling

multiple regulators in the same slot can lead to increased in-rush currents.

In the simplest scheme, the sequencer enables regulators during a power-up, and disables them

during a power-down. This functionality is achieved by setting BUCK<x>_AUTO/LDO<x>_AUTO and

clearing BUCK<x>_CONF/LDO<x>_CONF. Alternatively, the sequencer can be configured to keep

the regulator enabled, but switch between the A and B settings in ACTIVE and POWERDOWN

modes. The functionality of the BUCK<x>_AUTO/LDO<x>_AUTO and

BUCK<x>_CONF/LDO<x>_CONF controls is summarized in Table 27.

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Table 27: Regulator Control Functionality of the Power Supply Sequencer

Power-Up (Sequencer Direction Up)

POWERDOWN

Mode (Before)

ACTIVE Mode

(After)

Auto

Conf

En

Sel

En

Sel

Sequencer Functionality

0

x

0

The regulator is disabled at the step pointed to by

BUCK<x>_STEP/LDO<x>_STEP and the A-setting

(VBUCK<x>_A/VLDO<x>_A) is activated.

x

1

x

1

0

The regulator is enabled at the step pointed to by

BUCK<x>_STEP/LDO<x>_STEP and the A-setting

(VBUCK<x>_A/VLDO<x>_A) is activated.

1

Power-Down (Sequencer Direction Down)

ACTIVE Mode

(Before)

POWERDOWN

Mode (After)

Auto

Conf

En

Sel

En

Sel

x

0

x

0

The regulator is disabled at the step pointed to by

BUCK<x>_STEP/LDO<x>_STEP and the A-setting

(VBUCK<x>_A/VLDO<x>_A) is activated.

x

1

x

1

The regulator stays enabled but it is switched to the

B-setting (VBUCK<x>_B/VLDO<x>_B).

Step 0 of the sequencer has a special meaning. If control DEF_SUPPLY is set, the sequencer treats

all regulators pointing to step 0 as default supplies. This means that the regulators are enabled

automatically when entering the POWERDOWN mode. Regulators assigned to other steps are only

enabled after a wakeup condition occurs. Apart from this, step 0 acts the same as steps 1 to 15. If

control DEF_SUPPLY is ‘0’, step 0 of the sequencer does not have any affect.

As mentioned in Section 7.6.1, LDO1 can be programmed as an always-on supply. This is achieved

by setting controls DEF_SUPPLY, LDO1_CONF, and LDO1_EN in the OTP. In normal operation,

when the sequencer moves between ACTIVE and POWERDOWN modes, LDO1 behaves as

presented in Table 27. However, if DA9062 moves to the RESET mode, this configuration keeps

LDO1 enabled. This is not the case for any other regulator.

7.9.3

GPO Control

Any GPO can be asserted or de-asserted in a sequencer step (GP_RISE<x>_STEP,

GP_FALL<x>_STEP). The GPO control is summarized in Table 28. If a GPO is controlled by the

sequencer, it is driven to its inactive state when DA9062 is in RESET mode. The GPIO control only

works in sequencer steps greater than zero.

Table 28: GPO Control Functionality of the Power Supply Sequencer

GPIO<x>_MODE GPO State

After Reset

Sequencer

Direction

GPO Transition At

GP_RISE<x>

GPO Transition At

GP_FALL<x>

0 (active low)

1 (active high)

High

Low

Up

High

Low

High

Low

High

Low

High

Low

High to low

-

Low to high

Down

Up

-

High to low

Low to high

-

High to low

Low to high

High to low

-

Down

-

Low to high

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7.9.4

Wait Step

One of the sequencer steps (any step greater than zero) can be configured as a wait step, in which

the sequencer stays until an event is detected in the GPI3 input, see Section 7.3.1.2.

Note

The E_GPI3 event has to be cleared after the power-up sequence completes. Otherwise, the wait step in the

next power-up sequence will be ineffective.

The wait step features an optional 500 ms timeout, which can be used when the wait event never

occurs. If the timeout occurs, the steps following the wait step are not executed and a shutdown

sequence to RESET mode is triggered. The shutdown reason is signalled with the WAIT_SHUT bit.

Alternatively, the wait step can be used as a configurable delay in the sequence (WAIT_MODE,

WAIT_TIME).

7.9.5

32 kHz Clock Output

If a GPO is used as a 32 kHz clock output see Section 7.3.2.2, the clock buffer can be

enabled/disabled in one of the sequencer steps (any step greater than zero). The clock buffer is

enabled when, during power-up, the sequencer reaches the step EN32K_STEP. Likewise, the buffer

is disabled when the sequencer reaches the step EN32K_STEP on the way down.

7.9.6

Power-Down Disable

The PD_DIS_STEP pointer can be used to define a step in the power-up sequence above which a

group of functions will be enabled. The functions concerned can be controlled in the PD_DIS register.

Similarly, in the power-down sequence, the same groups of functions will be disabled when the

sequencer proceeds below the PD_DIS_STEP.

7.10 Junction Temperature Supervision

To protect DA9062 from damage due to excessive power dissipation, the junction temperature is

continuously monitored. The monitoring is split into three thresholds T_WARN(125 °C), T_CRIT(140 °C),

and T_POR(150 °C).

If the junction temperature rises above the first threshold (T_WARN), the event E_TEMP is asserted. If

the event is not masked, this will issue an interrupt. This first level of temperature supervision is

intended for non-invasive temperature control, where the necessary measures for cooling the system

down are left to the host software.

If the junction temperature increases even further and crosses the second threshold (T_CRIT), the

temperature error flag TEMP_CRIT (in register FAULT_LOG) is issued and a shutdown sequence to

RESET mode is triggered, see Section 7.8.3. The nRESET output is asserted at the beginning of the

shutdown sequence. Therefore, the second level of the temperature supervision does not rely on the

host software to take counter-measures. The fault flag can be evaluated by the application after the

next power-up.

There is also a third temperature threshold (T_POR) which causes DA9062 to enter RESET mode

without any sequencing and stop all functions except the RTC. This prevents possible permanent

damage due to fast temperature increases.

7.11 System Supply Voltage Supervision

Two comparators supervise the system supply V_SYS. One is monitoring the under-voltage level

(V_{DD_FAULT_LOWER}) and the other is indicating a good system supply (V_{DD_FAULT_UPPER}). The

V_{DD_FAULT_LOWER}threshold is OTP configurable and can be set via the VDD_FAULT_ADJ control from

2.5 V to 3.25 V in 50 mV steps. The V_{DD_FAULT_UPPER}threshold is also OTP configurable and can be

set via the VDD_HYST_ADJ control from 100 mV to 450 mV higher than the V_{DD_FAULT_LOWER}

threshold.

V_SYSdropping below the V_{DD_FAULT_UPPER}threshold asserts the event E_VDD_WARN. If the event is

not masked, this will issue an interrupt, which can be used by the host processor as an indication to

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decrease its activity. The status can also be signalled with a dedicated nVDD_FAULT signal, see

Section 7.3.2.1.

If V_SYSdrops below V_{DD_FAULT_LOWER}, the supply error flag VDD_FAULT (in register FAULT_LOG) is

asserted and a shutdown sequence to RESET mode is triggered, see Section 7.8.3. The nRESET

output is asserted at the beginning of the shutdown sequence.

7.12 Backup Battery Charger

The backup battery charger is designed to charge Lithium-Manganese coin cell batteries and super

capacitors. The charger provides a constant charge current with a programmable target voltage. The

charging current is programmable from 100 µA to 1000 µA in 100 µA steps and from 1 mA to 6 mA in

1 mA steps. The end-of-charge termination voltage is programmable in 100/200 mV steps from 1.1 V

to 3.1 V. When enabled, the charger will always keep the backup battery charged at its target

voltage. The backup battery charger can be temporarily disabled in POWERDOWN mode via control

BBAT_DIS.

The backup battery charger includes a reverse current protection and can also be used as an

always-on supply for low-power rails.

The backup battery provides an internal supply voltage for the 32 kHz crystal oscillator and RTC.

7.13 Real-Time Clock (RTC)

The RTC provides a real-time clock and alarm function that can be supplied from the backup battery.

RTC mode is described in Section 7.8.2.

The RTC counter will count the number of 32 kHz clock periods, providing a seconds, minutes,

hours, days, months, and years output. Year 0 corresponds to 2000. It is able to count up to 63

years. The value of the RTC calendar is read- and writeable via the 2-wire interface. A read of

COUNT_S (seconds) saves the current RTC calendar count into registers COUNT_S to COUNT_Y.

Registers are only valid when the RTC_READ status bit is asserted (assertion may take several ms

from leaving POR). After MONITOR has been set, host writing to CRYSTAL and RTC_EN is

prohibited to ensure that the RTC registers SECOND_A to SECOND_D are never stopped.

There is an alarm register containing min, hrs, day, month, and year. When the RTC counter register

value corresponds to the value set in the alarm an interrupt and a wakeup event are generated. The

trigger will also set a bit in an event register to notify that an alarm has occurred. The alarm can

alternatively be asserted from a periodic tick signal that, depending on control TICK_TYPE, is either

asserted every second or minute. After modifying TICK_TYPE or TICK_WAKE, a write to register

ALARM_Y is required to activate the new settings.

The power manager controls, ALARM_ON and TICK_ON, enable/disable the alarm/tick.

The power manager register bit MONITOR is set to 0 each time the RTC is powered up. Software

sets this bit to ‘1’ when setting the time and date, which allows detection of a subsequent loss of the

clock. Values written to the RTC calendar and alarm registers have to comply with the allowed value

range (see register description, for example, less than 60 for seconds or minutes).

7.13.1 32 kHz Crystal Oscillator

The oscillator is used to drive the real time clock (RTC) counter. It works with an external

piezoelectric oscillator crystal at 32 kHz. The oscillator output can be fed to a GPIO and used as a

clock source in the platform. The buffer can be enabled/disabled from a control register or with the

power sequencer.

In order to achieve the desired crystal frequency an external capacitor (10 pF to 20 pF, depending on

the parasitic capacitance of the board) is connected to ground from each of the crystal pins. The

start-up time of the oscillator is typically between 0.5 s and 1 s over the voltage range. When the

crystal is not mounted, the XTAL pins should be grounded.

The oscillator can be enabled from control CRYSTAL. A stabilisation timer can be used to blank the

clock output during the start-up. The timer can be started simultaneously with the oscillator or it can

be configured to wait until the clock’s duty cycle is within the range 30 % to 70 %. The start is

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configured from the DELAY_MODE control and the stabilisation time is programmed in the

STABILISATION_TIME control. OUT_CLOCK controls whether the clock feed to the OUT_32K

output (GPIO) is affected by the stabilisation timer. The RTC_CLOCK control provides a similar

gating function for the clock feed to the internal RTC counter.

The clock feed to the OUT_32K output can be controlled with the power sequencer, as described in

Section 7.9.5. In addition, the clock output is one of the features that can be disabled in the

POWERDOWN mode, as described in Section 7.9.6. When the OUT32K_PAUSE control is set, the

clock output is disabled in POWERDOWN.

7.14 Internal Oscillator

An internal oscillator provides a nominal 6.0 MHz clock that is divided to 3.0 MHz for the buck

converters. The frequency of the internal oscillator is adjusted during the initial start-up sequence of

DA9062 to within 5 % of the nominal 6.0 MHz.

Some applications require that the software is able to modify the oscillator frequency at runtime, for

example to avoid interference effects caused by harmonics of the buck converter operating

frequency. This can be achieved by writing a non-zero value to control OSC_FRQ. This control is a

signed 4-bit value where each step changes the frequency by about 1.33 %, which gives a range

from -10.65 % (-8) to +9.33 % (+7).

The tolerance of this frequency will affect most absolute timer values and PWM repetition rates.

7.15 Watchdog

The watchdog provides system monitoring functionality. A watchdog timeout triggers shutdown to

POWERDOWN mode, signalled in register FAULT_LOG. The watchdog can also be configured to

control a secondary reset output in addition to nRESET. This requires that one of the GPIOs is

configured as a GPO, controlled by the sequencer. The assertion/de-assertion is used as a reset,

and the GPIO is configured as a sequencer controlled GPO. This way, after the watchdog triggers

the power-down, the reset output is asserted by the sequencer during the power-down sequence.

Once enabled, the watchdog cannot be stopped and it runs in ACTIVE mode (this feature can be

bypassed with an OTP configuration). The source clock of the watchdog is automatically chosen

between the 32 kHz clock generated from the crystal oscillator and an internally generated slow

frequency clock.

After a cold boot, the watchdog is activated when entering ACTIVE mode. This first watchdog kick is

required for DA9062 to move to the ACTIVE mode after a cold boot, as illustrated in Figure 20. After

the watchdog is activated, the host must kick the watchdog periodically within the watchdog period

programmed with the TWDSCALE control. An interrupt can be generated to warn the host processor

of the watchdog timeout. The time for the warning interrupt is half of the watchdog period.

The kick can be done by a register write to control WATCHDOG (reg. CONTROL_F) or with the

GPIO0 pin configured as a WDKICK input. With control WDG_MODE = 1, the behavior of the

WDKICK input is modified so that either a pulse or a permanently asserted input prevents a

watchdog timeout. In this mode the parameter t_WDMINis not applicable.

If the host processor fails to feed the watchdog, DA9062 asserts a fault bit and enters

POWERDOWN mode. The watchdog timeout can also be configured to assert a reset output. This

requires that one of the GPIOs is configured as a reset output and assigned to a power sequencer

step, see Section 7.9.

After each watchdog timeout a retry counter is decremented. If the retry counter reaches zero,

DA9062 will stay in POWERDOWN mode, as described in Section 7.8.4. The number of allowed

retries can be programmed in the NFREEZE control.

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8

Register Map

8.1 Register Page Control

The device register map is larger than the address range directly addressable from the host

interface. The page control register provides the higher address bits and control for using the paging

mechanism. There are several copies of this register, one per host interface. These copies are

mirrored to addresses 0x080, 0x100 and 0x180.

8.2 Overview

Table 29 provides a summary of the registers. A description of each register is provided in Appendix

A.

Table 29: Register Summary

Address

Page Control

0x000

Name

7

6

5

4

3

2

1

0

PAGE_CON

REVERT

WRITE_MODE

PAGE

Reserved

Power Manager Control and Monitoring

0x001

STATUS_A

STATUS_B

STATUS_D

FAULT_LOG

·

DVC_BUSY

GPI2

Reserved

GPI1

NONKEY

GPI0

0x002

Reserved

GPI4

GPI3

0x004

Reserved

LDO4_ILIM

VDD_START

LDO3_ILIM

VDD_FAULT

LDO2_ILIM

POR

LDO1_ILIM

TWD_ERROR

0x005

WAIT_SHUT

NRESETREQ

KEY_RESET

TEMP_CRIT

IRQ Events

0x006

EVENT_A

EVENT_B

EVENT_C

Reserved

EVENTS_C

EVENTS_B

E_SEQ_RDY

Reserved

E_GPI4

E_WDG_WARN

E_LDO_LIM

E_GPI3

Reserved

E_GPI2

E_ALARM

E_TEMP

E_GPI1

E_NONKEY

Reserved

E_GPI0

0x007

E_VDD_WARN

Reserved

E_DVC_RDY

0x008

IRQ Masks

0x00A

IRQ_MASK_A Reserved

IRQ_MASK_B M_VDD_WARN

IRQ_MASK_C Reserved

M_SEQ_RDY

Reserved

M_GPI4

M_WDG_WARN Reserved

M_ALARM

M_TEMP

M_GPI1

M_NONKEY

Reserved

M_GPI0

0x00B

Reserved

M_DVC_RDY

M_LDO_LIM

M_GPI3

Reserved

0x00C

M_GPI2

System Control

0x00E

CONTROL_A

Reserved

M_POWER1_EN M_POWER_EN

NFREEZE

M_SYSTEM_EN STANDBY

POWER1_EN

FREEZE_EN

POWER_EN

SYSTEM_EN

BUCK_SLOWST

ART

0x00F

CONTROL_B

nONKEY_LOCK NRES_MODE

WATCHDOG_PD

Reserved

0x010

CONTROL_C

CONTROL_D

CONTROL_E

CONTROL_F

PD_DIS

DEF_SUPPLY

Reserved

SLEW_RATE

OTPREAD_EN

AUTO_BOOT

DEBOUNCING

TWDSCALE

RTC_EN

0x011

0x012

V_LOCK

Reserved

RTC_MODE_SD

SHUTDOWN

Reserved

RTC_MODE_PD

WATCHDOG

GPI_DIS

0x013

Reserved

WAKE_UP

PMIF_DIS

0x014

PMCONT_DIS

OUT32K_PAUSE BBAT_DIS

CLDR_PAUSE

Reserved

GPIO Control

0x015

GPIO_0_1

GPIO_2_3

GPIO_4

GPIO1_WEN

GPIO3_WEN

Reserved

GPIO1_TYPE

GPIO3_TYPE

GPIO1_PIN

GPIO3_PIN

GPIO0_WEN

GPIO2_WEN

GPIO4_WEN

GPIO0_TYPE

GPIO2_TYPE

GPIO4_TYPE

GPIO0_PIN

GPIO2_PIN

GPIO4_PIN

0x016

0x017

GPIO_WKUP_

MODE

GPIO4_WKUP_M GPIO3_WKUP_M GPIO2_WKUP_MO GPIO1_WKUP_MO GPIO0_WKUP_MOD

0x01C

0x01D

Reserved

ODE

DE

E

GPIO_MODE0_

4

GPIO4_MODE

GPIO3_MODE

GPIO2_MODE

GPIO1_MODE

GPIO0_MODE

0x01E

0x01F

GPIO_OUT0_2 GPIO2_OUT

GPIO1_OUT

GPIO0_OUT

GPIO3_OUT

GPIO_OUT3_4 Reserved

GPIO4_OUT

Power Supply Control

0x020

0x021

0x022

0x024

0x026

0x027

0x028

0x029

0x032

BUCK2_CONT Reserved

VBUCK2_GPI

VBUCK1_GPI

VBUCK4_GPI

VBUCK3_GPI

VLDO1_GPI

VLDO2_GPI

VLDO3_GPI

VLDO4_GPI

VLDO3_SEL

Reserved

VLDO1_SEL

BUCK2_CONF

BUCK1_CONF

BUCK4_CONF

BUCK3_CONF

LDO1_PD_DIS

LDO2_PD_DIS

LDO3_PD_DIS

LDO4_PD_DIS

VBUCK3_SEL

BUCK2_GPI

BUCK1_GPI

BUCK4_GPI

BUCK3_GPI

LDO1_GPI

LDO2_GPI

LDO3_GPI

LDO4_GPI

VBUCK4_SEL

BUCK2_EN

BUCK1_EN

BUCK4_EN

BUCK3_EN

LDO1_EN

BUCK1_CONT Reserved

BUCK4_CONT Reserved

BUCK3_CONT Reserved

LDO1_CONT

LDO2_CONT

LDO3_CONT

LDO4_CONT

DVC_1

LDO1_CONF

LDO2_CONF

LDO3_CONF

LDO4_CONF

VLDO4_SEL

LDO2_EN

LDO3_EN

LDO4_EN

VLDO2_SEL

VBUCK2_SEL

VBUCK1_SEL

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Address

Name

7

6

5

4

3

2

1

0

RTC Calendar and Alarm

0x040

0x041

0x042

0x043

0x044

0x045

0x046

0x047

0x048

0x049

0x04A

0x04B

0x04C

0x04D

0x04E

0x04F

COUNT_S

COUNT_MI

COUNT_H

COUNT_D

COUNT_MO

COUNT_Y

ALARM_S

ALARM_MI

ALARM_H

ALARM_D

ALARM_MO

ALARM_Y

SECOND_A

SECOND_B

SECOND_C

SECOND_D

RTC_READ

Reserved

COUNT_SEC

COUNT_MIN

Reserved

COUNT_HOUR

COUNT_DAY

Reserved

COUNT_MONTH

Reserved

MONITOR

COUNT_YEAR

ALARM_SEC

ALARM_MIN

ALARM_STATUS

Reserved

ALARM_HOUR

ALARM_DAY

TICK_TYPE

Reserved

TICK_WAKE

ALARM_MONTH

TICK_ON

ALARM_ON

ALARM_YEAR

SECONDS_A

SECONDS_B

SECONDS_C

SECONDS_D

Power Sequencer

0x081

0x082

0x083

0x084

0x088

0x089

0x08A

0x08D

0x08E

0x08F

0x090

0x091

0x092

0x095

0x096

0x097

0x098

0x099

SEQ

Reserved

SEQ_POINTER

SEQ_TIME

SEQ_TIMER

ID_2_1

SEQ_DUMMY

LDO2_STEP

LDO1_STEP

ID_4_3

LDO4_STEP

LDO3_STEP

ID_12_11

ID_14_13

ID_16_15

ID_22_21

ID_24_23

ID_26_25

ID_28_27

ID_30_29

ID_32_31

SEQ_A

PD_DIS_STEP

BUCK2_STEP

BUCK3_STEP

GP_FALL1_STEP

GP_FALL2_STEP

GP_FALL3_STEP

GP_FALL4_STEP

GP_FALL5_STEP

EN32K_STEP

POWER_END

PART_DOWN

WAIT_DIR

Reserved

BUCK1_STEP

BUCK4_STEP

GP_RISE1_STEP

GP_RISE2_STEP

GP_RISE3_STEP

GP_RISE4_STEP

GP_RISE5_STEP

WAIT_STEP

SYSTEM_END

MAX_COUNT

WAIT_TIME

SEQ_B

WAIT

TIME_OUT

WAIT_MODE

EN_32K

RESET

EN_32KOUT

Reserved

OUT_CLOCK

RESET_TIMER

DELAY_MODE

CRYSTAL

STABILISATION_TIME

RESET_EVENT

Power Supply Control

0x09A

0x09B

0x09C

0x09D

0x09E

BUCK_ILIM_A Reserved

BUCK_ILIM_B Reserved

BUCK_ILIM_C BUCK2_ILIM

BUCK3_ILIM

BUCK4_ILIM

BUCK1_ILIM

BUCK2_CFG

BUCK1_CFG

BUCK2_MODE

BUCK1_MODE

BUCK2_PD_DIS Reserved

BUCK1_PD_DIS Reserved

BUCK4_VTTR_E

N

0x09F

BUCK4_CFG

BUCK4_MODE

BUCK4_PD_DIS BUCK4_VTT_EN

Reserved

0x0A0

0x0A3

0x0A4

0x0A5

0x0A7

0x0A9

0x0AA

0x0AB

0x0AC

0x0B4

0x0B5

0x0B6

0x0B8

0x0BA

0x0BB

0x0BC

0x0BD

BUCK3_CFG

VBUCK2_A

VBUCK1_A

VBUCK4_A

VBUCK3_A

VLDO1_A

VLDO2_A

VLDO3_A

VLDO4_A

VBUCK2_B

VBUCK1_B

VBUCK4_B

VBUCK3_B

VLDO1_B

VLDO2_B

VLDO3_B

VLDO4_B

BUCK3_MODE

BUCK2_SL_A

BUCK1_SL_A

BUCK4_SL_A

BUCK3_SL_A

LDO1_SL_A

LDO2_SL_A

LDO3_SL_A

LDO4_SL_A

BUCK2_SL_B

BUCK1_SL_B

BUCK4_SL_B

BUCK3_SL_B

LDO1_SL_B

LDO2_SL_B

LDO3_SL_B

LDO4_SL_B

BUCK3_PD_DIS Reserved

VBUCK2_A

VBUCK1_A

VBUCK4_A

VBUCK3_A

Reserved

VLDO1_A

VLDO2_A

VLDO3_A

VLDO4_A

Reserved

VBUCK2_B

VBUCK1_B

VBUCK4_B

VBUCK3_B

Reserved

VLDO1_B

VLDO2_B

VLDO3_B

VLDO4_B

Reserved

BBAT Charger Control

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Address

Name

7

6

5

4

3

2

1

0

0x0C5

BBAT_CONT

BCHG_ISET

BCHG_VSET

Customer Trim and Configuration

0x105

0x106

0x107

INTERFACE

CONFIG_A

CONFIG_B

IF_BASE_ADDR

Reserved

PM_IF_HSM

PM_IF_FMP

PM_IF_V

IRQ_TYPE

PM_O_TYPE

Reserved

PM_I_V

Reserved

VDD_HYST_ADJ

VDD_FAULT_ADJ

BUCK_ACTV_DISC

HRG

0x108

CONFIG_C

Reserved

BUCK3_CLK_INV Reserved

BUCK4_CLK_INV BUCK1_CLK_INV

0x109

0x10A

0x10C

0x10D

0x10E

0x10F

0x110

0x112

CONFIG_D

CONFIG_E

CONFIG_G

CONFIG_H

CONFIG_I

CONFIG_J

CONFIG_K

CONFIG_M

Reserved

LDO_SD

IF_RESET

Reserved

OSC_FRQ

FORCE_RESET Reserved

BUCK3_AUTO

SYSTEM_EN_RD

BUCK4_AUTO

LDO3_AUTO

Reserved

NIRQ_MODE

BUCK2_AUTO

LDO2_AUTO

GPI_V

Reserved

BUCK1_AUTO

LDO1_AUTO

LDO4_AUTO

BUCK_MERGE

BUCK1_FCM

BUCK2_FCM

Reserved

INT_SD_MODE

TWOWIRE_TO

HOST_SD_MODE KEY_SD_MODE WATCHDOG_SD NONKEY_SD

NONKEY_PIN

KEY_DELAY

GPIO1_PUPD

Reserved

RESET_DURATION

SHUT_DELAY

GPIO3_PUPD

WDG_MODE

GPIO4_PUPD

GPIO2_PUPD

GPIO0_PUPD

Reserved

Customer Device Specific

0x121

0x122

0x123

0x124

0x125

0x126

0x127

0x128

0x129

0x12A

0x12B

0x12C

0x12D

0x12E

0x12F

0x130

0x131

0x132

0x133

0x134

0x181

0x182

GP_ID_0

GP_ID_1

GP_ID_2

GP_ID_3

GP_ID_4

GP_ID_5

GP_ID_6

GP_ID_7

GP_ID_8

GP_ID_9

GP_ID_10

GP_ID_11

GP_ID_12

GP_ID_13

GP_ID_14

GP_ID_15

GP_ID_16

GP_ID_17

GP_ID_18

GP_ID_19

DEVICE_ID

VARIANT_ID

CUSTOMER_I

D

GP_0

GP_1

GP_2

GP_3

GP_4

GP_5

GP_6

GP_7

GP_8

GP_9

GP_10

GP_11

GP_12

GP_13

GP_14

GP_15

GP_16

GP_17

GP_18

GP_19

DEV_ID

MRC

VRC

0x183

0x184

CUST_ID

CONFIG_ID

CONFIG_REV

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PMIC for applications requiring up to 8.5 A

9

Application Information

9.1 Component Selection

The following recommended components are examples selected from requirements of a typical

application. The final component selection will be dependent on the specific application. The

electrical characteristics (for example, supported voltage/current range) have to be cross-checked

and component types may need to be adapted from the individual needs of the target circuitry.

9.1.1

Resistors

Table 30: Recommended Resistors

Value

Tol.

Size (mm)

Rating (mW)

Part

IREF

200 kΩ

±1%

1005

100

Panasonic ERJ2RKF2003x

9.1.2

Capacitors

Ceramic capacitors are used as bypass capacitors at all VDD and output rails. When selecting a

capacitor, especially ones with high capacitance and small size, the DC bias characteristic has to be

taken into account.

On the VSYS main supply rail, a minimum distributed capacitance of 40 μF (actual capacitance after

voltage and temperature derating) is required.

Buck input capacitors should be within 1.5 mm distance from the supply pin, and the output capacitor

should be close to the inductor.

Table 31: Recommended Capacitors

Value

Tol.

Size

(mm)

Height Temp.

Rating Part

(V)

(mm)

0.55

0.95

0.5

Char.

X5R

VLDO1

VLDOx

1 µF

±10%

±20%

1005

2012

1005

2012

1608

1005

2012

1608

1005

10

GRM155R61A105KE15

2.2 µF

2 x 22 µF

10

GRM155R60J225ME95#

GRM219R60J226M***

CL05A226MR5NZNC

GRM219R60G476M***

CL10A476MR8NZN

VBUCK3

6.3

4.0

6.3

4.0

6.3

4.0

I_OUT≤ 1.5 A

VBUCK3

2 x 47 µF

2 x 22 µF

2 x 47 µF

2 x 22 µF

0.95

0.8

I_OUT> 1.5 A

VBUCK4

1

GRM188R60J226MEA0

CL05A226MR5NZNC

GRM219R60G476M***61

CL10A476MR8NZN

0.5

VBUCK4

0.95

0.8

(VTT mode)

VBUCK1,

VBUCK2

(half-current

mode)

1

GRM188R60J226MEA0

CL05A226MR5NZNC

0.5

VBUCK1,

VBUCK2

(full-current

mode)

2 x 47 µF

±20%

2012

1608

0.95

0.8

X5R

4.0

GRM219R60G476M***61

CL10A476MR8NZN

VSYS

1 x 1 µF

±10%

±20%

1005

2012

1005

0.5

X5R

10

GRM155R61A105KE15D

LMK212BJ226MG-T

VDD_BUCKx

2 x 22 µF

4 x 10 µF

1.25

0.5

GRM155R61A106ME21

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Value

Tol.

Size

(mm)

Height Temp.

Rating Part

(V)

(mm)

Char.

X5R

VDD_LDO2

VDD_LDO34

VBBAT

1 x 1 µF

470 nF

2.2 µF

±10%

±20%

1005

0.5

10

6.3

GRM155R61A105KE15D

0.5

GRM155R61A105KE15D

GRM155R61A474KE15#

GRM155R60J225ME95#

0.55

VDDCORE,

VREF

XTAL_IN,

12 pF

±5%

1005

0.55

U2J

50

GRM1557U1H120JZ01#

XTAL_OUT

9.1.3

Inductors

Inductors should be selected based upon the following parameters:

●

ISAT specifies the current causing a reduction in the inductance by a specific amount, typically

30 %

●

IRMS specifies the current causing a temperature rise of a specific amount

DC resistance (DCR) is critical for converter efficiency and should be therefore minimized.

ESR at the buck switching frequency is critical to converter efficiency in PFM mode and should

be therefore minimized.

Inductance is given in Table 32.

Table 32: Recommended Inductors

Buck

Value

ISAT IRMS DCR

Size

Part

(A)

(Typ.

(W×L×H) mm

mΩ)

Buck1 and Buck2

(half-current mode),

Buck3, Buck4

1 µH

2.7

2.3

55

60

2.0×1.6×1.0

Toko 1285AS-H-1R0M

2.65

2.45

Tayo Yuden

MAKK2016T1R0M

2.9

2.2

2.3

60

43

2.0×1.6×1.0

1.6×0.8×1.0

TDK TFM201610A-1R0M

Buck4

0.24 µH 1.65

Taiyo Yuden

MBKK1608TR24N

(VTT mode)

0.25 µH 9.7

11.45 7.64

4.0×4.0×1.2

2.5×2.0×1.0

2.5×2.0×1.2

Coilcraft XFL4012-251ME

Toko1269AS-H-1R0M

Buck1, Buck2

(full-current mode)

1 µH

3.4

3.6

3

60

45

3.1

Tayo Yuden

MAMK2520T1R0M

3.8

3.9

3.5

3.35

5.4

3.5

3.1

2.5

11

45

2.5×2.0×1.2

3.2×2.5×1.0

2.5×2.0×1.0

3.0×3.0×1.2

4.0×4.0×2.1

Toko 1239AS-H-1R0M

Toko1276AS-H-1R0M

TDK TFM252010A-1R0M

Cyntec PST031B-1R0MS

Coilcraft XFL4020-102ME

48

54

52

10.8

9.1.4

Crystal

The real-time clock module requires an external 32.768 kHz crystal. For correct component selection,

the effective load capacitance must to be taken into account. This includes external capacitors on

pins XTAL_IN and XTAL_OUT in series combination, plus the PCB and stray capacitances. For

example, if two 12 pF external capacitors are used, resulting in a total capacitance of 6 pF, and

assuming the stray capacitances are 3 pF, then a crystal that specifies a load capacitance of 9 pF

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DA9062

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should be chosen. Different stray capacitances may require different external capacitors and/or a

different crystal type. Furthermore, the series resistance of the crystal must not exceed 100 kΩ.

Table 33: Recommended Crystal

Type

Size (W×L×H) mm

Manufacturer

CC7V-T1A 32.768 kHz 9.0 pF ±30 ppm

3.2×1.5×0.9

Micro Crystal

9.1.5

Backup Battery

The backup battery charger supports lithium coin cells as well as Supercaps/Goldcaps.

Table 34: Recommended Backup Battery

Type

Size (mm)

Manufacturer

Sanyo, Panasonic

Korchip

Lithium battery (rechargeable) ML414, 1.0 mAh, 3.1 V

Starcap SC SM 2R8, 0.1 F, 2.8 V

4.8 (ø), 1.4 (h)

3.8 (ø), 1.5 (h)

Electric double layer capacitor (Gold Capacitor)

EECEP0E333A, 0.033 F, 2.6 V

Panasonic

9.2 PCB Layout

1608

LX2

LX1

VLDO1

GPIO4

GPIO3

VLDO2

Quiet ground

VDD

LDO2

1005

GPIO2

IREF

VBUCK2

VBUCK1

VBUCK3

VBUCK4

VDDIO

1005

GND

VREF

1005

XIN

VSS

ANA

Quiet ground

XOUT

VLDO3

GPIO1

1005

VDD

LDO34

GPIO0

1005

VBUCK3

2016

1005

VBUCK4

1608

Figure 23: PCB Layout for DA9062

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9.2.1

General Recommendations

Appropriate trace width and quantity of vias should be used for all power supply paths.

Too high trace resistances can prevent the system from achieving the best performance, for

example, the efficiency and the current ratings of switching converters might be degraded.

Furthermore, the PCB may be exposed to thermal hot spots, which can lead to critical overheating

due to the positive temperature coefficient of copper.

Special care must be taken with the DA9062 pad connections. The traces connecting the pads

should of the same width as the pads and they should become wider as soon as possible.

It is recommended to create a separate quiet ground to which the VREF capacitor, IREF resistor, and

the crystal capacitors are connected. The PCB layout should ensure these component grounds are

kept quiet, that is, they should be separated from the main ground return path for the noisy power

ground. The quiet ground can then be connected to the main ground at the paddle, as shown in

Figure 23.

All traces carrying high discontinuous currents should be kept as short as possible.

Noise sensitive analog signals, such as feedback lines or crystal connections, should be kept away

from traces carrying pulsed analog or digital signals. This can be achieved by separation or shielding

with quiet signals or ground traces.

9.2.2

LDOs and Switched Mode Supplies

The placement of the distributed capacitors on the VSYS rail must ensure that all VDD inputs and

VSYS are connected to a bypass capacitor close to the pad. It is recommended placing at least two

1 µF capacitors close to the VDD_LDOx pads and at least one 10 µF close to the VDD_BUCKx pads.

Using a local power plane underneath the device for VSYS might be considered.

Transient current loops in the area of the switching converters should be minimized.

The common references (IREF, VREF) should be placed close to the device and cross-coupling to

any noisy digital or analog trace must be avoided.

Output capacitors of the LDOs can be placed close to the input pins of the supplied devices (remote

from the DA9062).

Care must be taken with trace routing to ensure that no current is carried on feedback lines of the

buck output voltages (VBUCKx).

The inductor placement is less critical since parasitic inductances have negligible effect.

9.2.3

32 kHz Crystal Oscillator

The crystal and its load capacitors should be placed as close as possible to the IC with short and

symmetrical traces.

The traces must be isolated from noisy signals, especially from clocked digital ones. Ideally the lines

should be buried between two ground layers, surrounded by additional ground traces.

9.2.4

Optimising Thermal Performance

DA9062 features a ground paddle which should be connected with as many vias as possible to the

PCB’s main ground plane in order to achieve good thermal performance.

Solder mask openings for the ball landing pads must be arranged to prohibit solder balls flowing into

vias.

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10 Ordering Information

The ordering number consists of the part number followed by a suffix indicating the packing method.

The “xx” represents a placeholder for the specific OTP variant. For details and availability, please

consult Dialog Semiconductor’s customer portal or your local sales representative.

Table 35: Ordering Information

Part Number

Package (mm)

QFN40, 6 x 6

Package Description

Tray, 490 pcs

Comment

DA9062-xxAM1

DA9062-xxAM1-A

DA9062-xxAM2

DA9062-xxAM2-A

Tray, 490 pcs

Automotive AEC-Q100 Grade 3

T&R, 4000 pcs

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Appendix A Register Descriptions

This appendix describes the registers summarized in Section 8.

A.1 PAGE 0

A.1.1

Page Control

Table 36: PAGE_CON (0x000)

Field

Bit

Type

Description

REVERT

7:7

R/W

0: PAGE switches the regmap page until rewritten.

1: PAGE reverts to 0 after one access.

WRITE_MODE

PAGE

6:6

5:0

R/W

2-WIRE sequential write style.

0: Write data to consecutive addresses

1: Write data to random addresses using address/data pairs

The top 6 bits of the register address. For 2-WIRE, PAGE[0] is

ignored.

A.1.2

Power Manager Control and Monitoring

Table 37: STATUS_A (0x001)

Field

Bit

7:3

2:2

1:1

0:0

Type

R

Description

Reserved

DVC_BUSY

Reserved

NONKEY

Reserved

R

One or more DVC capable supplies are ramping

R

Reserved

R

nONKEY level

Table 38: STATUS_B (0x002)

Field

Reserved

GPI4

Bit

7:5

4:4

3:3

2:2

1:1

0:0

Type

R

Description

Reserved

GPI4 level

GPI3 level

GPI2 level

GPI1 level

GPI0 level

R

GPI3

R

GPI2

R

GPI1

R

GPI0

R

Table 39: STATUS_D (0x004)

Field

Bit

7:4

3:3

2:2

1:1

0:0

Type

R

Description

Reserved

LDO4_ILIM

LDO3_ILIM

LDO2_ILIM

LDO1_ILIM

Reserved

R

LDO4 over-current indicator

LDO3 over-current indicator

LDO2 over-current indicator

LDO1 over-current indicator

R

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Table 40: FAULT_LOG (0x005)

Field

Bit

Type

Description

WAIT_SHUT

7:7

R

Power-down due to sequencer WAIT_STEP timeout.

See section 7.9.4 for further information.

Note 1

NRESETREQ

KEY_RESET

TEMP_CRIT

VDD_START

VDD_FAULT

POR

6:6

5:5

4:4

3:3

2:2

1:1

0:0

R

Power-down due to nRESETREQ pin or control SHUTDOWN.

Note 1

R

Power-down due to nONKEY

Note 1

R

Junction over-temperature

Note 1

R

Power-down due to VSYS under-voltage before or within

16 seconds after release of nRESET.

Note 1

R

Power-down due to VSYS under-voltage.

DA9062 starts up from NO-POWER or RTC / DELIVERY mode.

Watchdog timeout

Note 1

R

Note 1

TWD_ERROR

R

Note 1

Note 1 Cleared from the host by writing back the read value.

A.1.3

IRQ Events

Table 41: EVENT_A (0x006)

Field

Bit

7:7

6:6

5:5

4:4

Type

R

Description

Reserved

EVENTS_C

EVENTS_B

E_SEQ_RDY

Reserved

R

Event in register EVENT_C is active.

Event in register EVENT_B is active.

Sequencer reached final position.

R

Note 1

E_WDG_WARN

3:3

R

Watchdog timeout warning

Note 1

E_TICK

2:2

1:1

R

RTC tick

E_ALARM

R

RTC alarm

Note 1

E_NONKEY

0:0

R

nONKEY event

Note 1

Note 1 Cleared from the host by writing back the read value.

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Table 42: EVENT_B (0x007)

Field

Bit

Type

Description

E_VDD_WARN

7:7

R

V_SYSunder-voltage (V_SYS< V_{DD_FAULT_UPPER})

Note 1

Reserved

6:6

5:5

Reserved

E_DVC_RDY

R

All supplies have finished DVC ramping

Note 1

Reserved

4:4

3:3

Reserved

E_LDO_LIM

R

LDO over-current

Note 1

Reserved

2:2

1:1

Reserved

E_TEMP

R

Junction over-temperature (T_J> T_WARN)

Note 1

Reserved

0:0

Reserved

Note 1 Cleared from the host by writing back the read value.

Table 43: EVENT_C (0x008)

Field

Bit

7:5

4:4

Type

Description

Reserved

E_GPI4

R

GPI4 event

Note 1

E_GPI3

E_GPI2

E_GPI1

E_GPI0

3:3

2:2

1:1

0:0

R

GPI3 event

GPI2 event

GPI1 event

GPI0 event

Note 1

R

Note 1

R

Note 1

R

Note 1

Note 1 Cleared from the host by writing back the read value.

A.1.4

IRQ Masks

Table 44: IRQ_MASK_A (0x00A)

Field

Bit

7:5

4:4

3:3

2:2

1:1

0:0

Type

R/W

Description

Reserved

M_SEQ_RDY

M_WDG_WARN

M_TICK

IRQ mask for sequencer final position indication (E_SEQ_RDY)

IRQ mask for watchdog timeout warning (E_WDG_WARN)

IRQ mask for RTC tick event (E_TICK)

M_ALARM

M_NONKEY

IRQ mask for RTC alarm (E_ALARM)

IRQ mask for nONKEY event (E_NONKEY)

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Table 45: IRQ_MASK_B (0x00B)

Field

Bit

Type

Description

M_VDD_WARN

7:7

R/W

IRQ mask for under-voltage event (E_VDD_WARN) V_SYS

V_{DD_FAULT_UPPER}

<

Reserved

6:6

Reserved

M_DVC_RDY

5:5

4:4

R/W

All supplies have finished DVC ramping.

Reserved

M_LDO_LIM

3:3

2:2

IRQ mask for LDO over-current event (E_LDO_LIM)

Reserved

M_TEMP

1:1

0:0

IRQ mask for junction over-temperature event (E_TEMP)

Reserved

Table 46: IRQ_MASK_C (0x00C)

Field

Bit

7:5

4:4

3:3

2:2

1:1

0:0

Type

R/W

Description

Reserved

M_GPI4

M_GPI3

M_GPI2

M_GPI1

M_GPI0

Reserved

IRQ mask for GPI4 event (E_GPI4)

IRQ mask for GPI3 event (E_GPI3)

IRQ mask for GPI2 event (E_GPI2)

IRQ mask for GPI1 event (E_GPI1)

IRQ mask for GPI0 event (E_GPI0)

A.1.5

System Control

Table 47: CONTROL_A (0x00E)

Field

Bit

7:7

6:6

5:5

4:4

3:3

Type

R/W

Description

Reserved

M_POWER1_EN

M_POWER_EN

M_SYSTEM_EN

STANDBY

Write mask for POWER1_EN

Write mask for POWER_EN

Write mask for SYSTEM_EN

Clearing control SYSTEM_EN or releasing SYS_EN (GPIO4

alternate function) or a long press of nONKEYwill:

0: Power-down to slot 0.

1: Power-down as far as defined by the PART_DOWN pointer.

POWER1_EN

POWER_EN

SYSTEM_EN

2:2

1:1

0:0

R/W

Target status of power domain POWER1.

Bus write masked with M_POWER1_EN.

Target status of power domain POWER.

Bus write masked with M_POWER_EN.

Target status of power domain SYSTEM.

Bus write masked with M_SYSTEM_EN.

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Table 48: CONTROL_B (0x00F)

Field

Bit

Type

Description

BUCK_SLOWSTART

7:7

R/W

Enable buck slow start (reduced inrush current; increased start-up

time).

NFREEZE

6:5

4:4

R/W

Block all wakeups after NFREEZE watchdog restart trials.

nONKEY_LOCK

0: normal POWERDOWN mode

1: Power-down controlled by KEY_DELAY

NRES_MODE

3:3

R/W

If powering down / up:0: Keep nRESET not asserted

1: Assert / clear nRESET when entering / leaving POWERDOWN

FREEZE_EN

WATCHDOG_PD

Reserved

2:2

1:1

0:0

R/W

Enable watchdog restart limit NFREEZE.

Watchdog timer is on (1) / off (0) in POWERDOWN mode.

Reserved

Table 49: CONTROL_C (0x010)

Field

Bit

Type

Description

DEF_SUPPLY

7:7

R/W

1: OTP enables / disables all supplies (except LDOCORE) when

sequencer enters slot 0.

SLEW_RATE

6:5

R/W

Buck DVC slew rate step width [10 mV/step (20 mV/step for

Buck3)]

00: 4 µs

01: 2 µs

10: 1 µs

11: 0.5 µs

OTPREAD_EN

AUTO_BOOT

4:4

3:3

R/W

When leaving POWERDOWN mode supplies are configured from

OTP.

After progressing from RESET mode, the sequencer:

0: requires a wakeup event to start up.

1: starts up automatically.

DEBOUNCING

2:0

R/W

GPI, nONKEY and nRESETREQ debounce time

000: no debouncing

001: 0.1 ms

010: 1.0 ms

011: 10.24 ms

100: 51.2 ms

101: 256 ms

110: 512 ms

111: 1024 ms

Table 50: CONTROL_D (0x011)

Field

Bit

7:3

2:0

Type

R/W

Description

Reserved

TWDSCALE

Reserved

Watchdog timeout scaling:

0: Watchdog disabled

Other: Timeout = 2.5 * 2^(TWDSCALE-1) s

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Table 51: CONTROL_E (0x012)

Field

Bit

7:7

6:3

2:2

1:1

Type

R/W

Description

V_LOCK

Prevent host from writing to registers 0x81 - 0x120 except 0x100.

Reserved

RTC_EN

Enable Real Time Clock and alarm.

RTC_MODE_SD

Disable all supplies and blocks and LDOCORE if PSM enters

RESET mode.

RTC_MODE_PD

0:0

R/W

Disable all supplies and blocks and LDOCORE if PSM enters

POWERDOWN mode.

Table 52: CONTROL_F (0x013)

Field

Bit

7:3

2:2

1:1

0:0

Type

R/W

Description

Reserved

WAKE_UP

SHUTDOWN

WATCHDOG

Reserved

Wakeup from POWERDOWN mode. Cleared automatically.

Power-down to RESET mode. Cleared automatically.

Reset watchdog timer. Cleared automatically.

Table 53: PD_DIS (0x014)

Field

Bit

Type

Description

PMCONT_DIS

7:7

R/W

Disable SYS_EN, PWR_EN and PWR1_EN in POWERDOWN

mode.

OUT32K_PAUSE

BBAT_DIS

CLDR_PAUSE

Reserved

6:6

5:5

4:4

3:3

2:2

1:1

0:0

R/W

Disable OUT_32K in POWERDOWN mode.

Disable backup battery charger in POWERDOWN mode.

Disable calendar update in POWERDOWN mode.

Reserved

PMIF_DIS

Disable 2-WIRE interface in POWERDOWN mode.

Reserved

GPI_DIS

Disable E_GPI<x> events in POWERDOWN mode.

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A.1.6

GPIO Control

Table 54: GPIO_0_1 (0x015)

Field

Bit

Type

Description

GPIO1_WEN

7:7

R/W

0: Passive-to-active transition triggers wakeup.

1: No wakeup

GPIO1_TYPE

GPIO1_PIN

6:6

5:4

R/W

GPI: active high (1) / low (0)

Function of GPIO1 pin (see GPIO1_OUT if output)

00: Reserved

01: Input (opt. regul. HW ctrl.)

10: Output (open drain)

11: Output (push-pull)

GPIO0_WEN

3:3

R/W

0: Passive-to-active transition triggers wakeup.

1: No wakeup

GPIO0_TYPE

GPIO0_PIN

2:2

1:0

R/W

GPI: active high (1) / low (0)

Function of GPIO0 pin (see GPIO0_OUT if output)

00: Watchdog trigger input

01: Input

10: Output (open drain)

11: Output (push-pull)

Table 55: GPIO_2_3 (0x016)

Field

Bit

Type

Description

GPIO3_WEN

7:7

R/W

0: Passive-to-active transition triggers wakeup.

1: No wakeup

GPIO3_TYPE

GPIO3_PIN

6:6

5:4

R/W

GPI: active high (1) / low (0)

Function of GPIO3 pin (see GPIO3_OUT if output)

00: Reserved

01: Input (opt. regul. HW ctrl.)

10: Output (open drain)

11: Output (push-pull)

GPIO2_WEN

3:3

R/W

0: Passive-to-active transition triggers wakeup.

1: No wakeup

GPIO2_TYPE

GPIO2_PIN

2:2

1:0

R/W

GPI: active high (1) / low (0)

Function of GPIO2 pin (see GPIO2_OUT if output)

00: GPI as PWR_EN

01: Input (opt. regul. HW ctrl.)

10: Output (open drain)

11: nVDD_FAULT

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Table 56: GPIO_4 (0x017)

Field

Bit

7:4

3:3

Type

R/W

Description

Reserved

GPIO4_WEN

Reserved

0: Passive-to-active transition triggers wakeup.

1: No wakeup

GPIO4_TYPE

GPIO4_PIN

2:2

1:0

R/W

GPI: active high (1) / low (0)

Function of GPIO pad (see GPIO4_OUT if output)

00: GPI as SYS_EN

01: Input

10: Output (open drain)

11: Output (push-pull)

Table 57: GPIO_WKUP_MODE (0x01C)

Field

Bit

7:5

4:4

3:3

2:2

1:1

0:0

Type

R/W

Description

Reserved

GPIO4_WKUP_MODE

GPIO3_WKUP_MODE

GPIO2_WKUP_MODE

GPIO1_WKUP_MODE

GPIO0_WKUP_MODE

GPI4 wakeup is edge (0) / level (1) sensitive.

GPI3 wakeup is edge (0) / level (1) sensitive.

GPI2 wakeup is edge (0) / level (1) sensitive.

GPI1 wakeup is edge (0) / level (1) sensitive.

GPI0 wakeup is edge (0) / level (1) sensitive.

Table 58: GPIO_MODE0_4 (0x01D)

Field

Bit

7:5

4:4

Type

R/W

Description

Reserved

GPIO4_MODE

Reserved

Output, STATIC: the output value

Output, other: active low (0) / high (1)

Input:

debouncing off (0) / on (1)

GPIO3_MODE

GPIO2_MODE

GPIO1_MODE

GPIO0_MODE

3:3

2:2

1:1

0:0

R/W

Output, STATIC: the output value

Output, other: active low (0) / high (1)

Input:

debouncing off (0) / on (1)

Output, STATIC: the output value

Output, other: active low (0) / high (1)

Input:

debouncing off (0) / on (1)

Output, STATIC: the output value

Output, other: active low (0) / high (1)

Input:

debouncing off (0) / on (1)

Output, STATIC: the output value

Output, other: active low (0) / high (1)

Input:

debouncing off (0) / on (1)

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Table 59: GPIO_OUT0_2 (0x01E)

Field

Bit

Type

Description

GPIO2_OUT

7:6

R/W

GPIO output function

00: Static value according GPIO2_MODE

01: nVDD_FAULT

10: 32 kHz crystal clock (OUT_32K)

11: Sequencer controlled

GPIO1_OUT

5:3

R/W

GPIO output function

000: Static value according GPIO1_MODE

001: nVDD_FAULT

010: 32 kHz crystal clock (OUT_32K)

011: Sequencer controlled

100: Forward GPI0

101: Reserved

110: Forward GPI2

111: Forward GPI3

GPIO0_OUT

2:0

R/W

GPIO output function

000: Static value according GPIO0_MODE

001: nVDD_FAULT

010: 32 kHz crystal clock (OUT_32K)

011: Sequencer controlled

100: Reserved

101: Forward GPI1

110: Forward GPI2

111: Forward GPI3

Table 60: GPIO_OUT3_4 (0x01F)

Field

Bit

7:5

4:3

Type

R/W

Description

Reserved

GPIO4_OUT

Reserved

GPIO output function

00: Static value according GPIO4_MODE

01: nVDD_FAULT

10: 32 kHz crystal clock (OUT_32K)

11: Sequencer controlled

GPIO3_OUT

2:0

R/W

GPIO output function

000: Static value according GPIO3_MODE

001: nVDD_FAULT

010: 32 kHz crystal clock (OUT_32K)

011: Sequencer controlled

100: Forward GPI0

101: Forward GPI1

110: Forward GPI2

111: Reserved

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PMIC for applications requiring up to 8.5 A

A.1.7

Power Supply Control

Table 61: BUCK2_CONT (0x020)

Field

Bit

7:7

6:5

Type

R/W

Description

Reserved

VBUCK2_GPI

Reserved

Voltage controlling GPI

(passive to active transition: VB*_B, act. to pas.: VB*_A)

Reserved

4:4

3:3

2:1

R/W

Reserved

BUCK2_CONF

BUCK2_GPI

Default supply, or sequenced and on in POWERDOWN

Enabling GPI

(passive to active transition: enable, act. to pas.: disable)

BUCK2_EN

0:0

R/W

Disable (0) / enable (1) the buck (dependent on on/off priority

order), except in BUCK1/2 dual-phase mode

Table 62: BUCK1_CONT (0x021)

Field

Bit

7:7

6:5

Type

R/W

Description

Reserved

VBUCK1_GPI

Reserved

Voltage controlling GPI

(passive to active transition: VB*_B, act. to pas.: VB*_A)

00: Sequencer controlled

01: Select GPI1

10: Select GPI2

11: Select GPI3

Reserved

4:4

3:3

2:1

R/W

Reserved

BUCK1_CONF

BUCK1_GPI

Default supply, or sequenced and on in POWERDOWN

Enabling GPI

(passive to active transition: enable, act. to pas.: disable)

00: Sequencer controlled

01: Select GPI1

10: Select GPI2

11: Select GPI3

BUCK1_EN

0:0

R/W

Disable (0) / enable (1) the buck (dependent on on/off priority

order)

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PMIC for applications requiring up to 8.5 A

Table 63: BUCK4_CONT (0x022)

Field

Bit

7:7

6:5

Type

R/W

Description

Reserved

VBUCK4_GPI

Reserved

Voltage controlling GPI

(passive to active transition: VB*_B, act. to pas.: VB*_A)

00: Sequencer controlled

01: Select GPI1

10: Select GPI2

11: Select GPI3

Reserved

4:4

3:3

2:1

R/W

Reserved

BUCK4_CONF

BUCK4_GPI

Default supply, or sequenced and on in POWERDOWN

Enabling GPI

(passive to active transition: enable, act. to pas.: disable)

00: Sequencer controlled

01: Select GPI1

10: Select GPI2

11: Select GPI3

BUCK4_EN

0:0

R/W

Disable (0) / enable (1) the buck (dependent on on/off priority

order)

Table 64: BUCK3_CONT (0x024)

Field

Bit

7:7

6:5

Type

R/W

Description

Reserved

VBUCK3_GPI

Reserved

Voltage controlling GPI

(passive to active transition: VB*_B, act. to pas.: VB*_A)

00: Sequencer controlled

01: Select GPI1

10: Select GPI2

11: Select GPI3

Reserved

4:4

3:3

2:1

R/W

Reserved

BUCK3_CONF

BUCK3_GPI

Default supply, or sequenced and on in POWERDOWN

Enabling GPI

(passive to active transition: enable, act. to pas.: disable)

00: Sequencer controlled

01: Select GPI1

10: Select GPI2

11: Select GPI3

BUCK3_EN

0:0

R/W

Disable (0) / enable (1) the buck (dependent on on/off priority

order)

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PMIC for applications requiring up to 8.5 A

Table 65: LDO1_CONT (0x026)

Field

Bit

7:7

6:5

Type

R/W

Description

LDO1_CONF

VLDO1_GPI

Default supply, or sequenced and on in POWERDOWN

Voltage controlling GPI

(passive to active transition: VLDO*_B, act. to pas.: VLDO*_A)

00: Sequencer controlled

01: Select GPI1

10: Select GPI2

11: Select GPI3

Reserved

4:4

3:3

2:1

R/W

Reserved

LDO1_PD_DIS

LDO1_GPI

Disable pull-down resistor when disabled.

Enabling GPI

(passive to active transition: enable, act. to pas.: disable)

00: Sequencer controlled

01: Select GPI1

10: Select GPI2

11: Select GPI3

LDO1_EN

0:0

R/W

Disable (0) / enable (1) the LDO (dependent on on/off priority

order)

Table 66: LDO2_CONT (0x027)

Field

Bit

7:7

6:5

Type

R/W

Description

LDO2_CONF

VLDO2_GPI

Default supply, or sequenced and on in POWERDOWN

Voltage controlling GPI

(passive to active transition: VLDO*_B, act. to pas.: VLDO*_A)

00: Sequencer controlled

01: Select GPI1

10: Select GPI2

11: Select GPI3

Reserved

4:4

3:3

2:1

R/W

Reserved

LDO2_PD_DIS

LDO2_GPI

Disable pull-down resistor when disabled.

Enabling GPI

(passive to active transition: enable, act. to pas.: disable)

00: Sequencer controlled

01: Select GPI1

10: Select GPI2

11: Select GPI3

LDO2_EN

0:0

R/W

Disable (0) / enable (1) the LDO (dependent on on/off priority

order)

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PMIC for applications requiring up to 8.5 A

Table 67: LDO3_CONT (0x028)

Field

Bit

7:7

6:5

Type

R/W

Description

LDO3_CONF

VLDO3_GPI

Default supply, or sequenced and on in POWERDOWN

Voltage controlling GPI

(passive to active transition: VLDO*_B, act. to pas.: VLDO*_A)

00: Sequencer controlled

01: Select GPI1

10: Select GPI2

11: Select GPI3

Reserved

4:4

3:3

2:1

R/W

Reserved

LDO3_PD_DIS

LDO3_GPI

Disable pull-down resistor when disabled.

Enabling GPI

(passive to active transition: enable, act. to pas.: disable)

00: Sequencer controlled

01: Select GPI1

10: Select GPI2

11: Select GPI3

LDO3_EN

0:0

R/W

Disable (0) / enable (1) the LDO (dependent on on/off priority

order)

Table 68: LDO4_CONT (0x029)

Field

Bit

7:7

6:5

Type

R/W

Description

LDO4_CONF

VLDO4_GPI

Default supply, or sequenced and on in POWERDOWN

Voltage controlling GPI

(passive to active transition: VLDO*_B, act. to pas.: VLDO*_A)

00: Sequencer controlled

01: Select GPI1

10: Select GPI2

11: Select GPI3

Reserved

4:4

3:3

2:1

R/W

Reserved

LDO4_PD_DIS

LDO4_GPI

Disable pull-down resistor when disabled.

Enabling GPI

(passive to active transition: enable, act. to pas.: disable)

00: Sequencer controlled

01: Select GPI1

10: Select GPI2

11: Select GPI3

LDO4_EN

0:0

R/W

Disable (0) / enable (1) the LDO (dependent on on/off priority

order)

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PMIC for applications requiring up to 8.5 A

Table 69: DVC_1 (0x032)

Field

Bit

7:7

6:6

5:5

4:4

3:3

2:2

1:1

0:0

Type

R/W

Description

VLDO4_SEL

VLDO3_SEL

VLDO2_SEL

VLDO1_SEL

VBUCK3_SEL

VBUCK4_SEL

VBUCK2_SEL

VBUCK1_SEL

Select VLDO4_A (0) / VLDO4_B (1).

Select VLDO3_A (0) / VLDO3_B (1).

Select VLDO2_A (0) / VLDO2_B (1).

Select VLDO1_A (0) / VLDO1_B (1).

Select VBUCK3_A (0) / VBUCK3_B (1).

Select VBUCK4_A (0) / VBUCK4_B (1).

Select VBUCK2_A (0) / VBUCK2_B (1).

Select VBUCK1_A (0) / VBUCK1_B (1).

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DA9062

PMIC for applications requiring up to 8.5 A

A.1.8

RTC Calendar and Alarm

Table 70: COUNT_S (0x040)

Field

Bit

7:7

6:6

5:0

Type

Description

RTC_READ

Reserved

COUNT_SEC

R

Indicates that RTC calendar is ready to be read by the host.

Reserved

R/W

Calendar seconds

Bus write is snapshot and updated on a write to COUNT_YEAR.

Bus read loads RTC calendar into 0x104-0x109.

Table 71: COUNT_MI (0x041)

Field

Bit

7:6

5:0

Type

R

Description

Reserved

COUNT_MIN

Reserved

R/W

Calendar minutes 0-59

Bus write is snapshot and updated on a write to COUNT_YEAR.

Bus read is snapshot and updated on a read from COUNT_SEC.

Table 72: COUNT_H (0x042)

Field

Bit

7:5

4:0

Type

R

Description

Reserved

COUNT_HOUR

Reserved

R/W

Calendar hours 0-23

Bus write is snapshot and updated on a write to COUNT_YEAR.

Bus read is snapshot and updated on a read from COUNT_SEC.

Table 73: COUNT_D (0x043)

Field

Bit

7:5

4:0

Type

R

Description

Reserved

COUNT_DAY

Reserved

R/W

Calendar days 1-31

Bus write is snapshot and updated on a write to COUNT_YEAR.

Bus read is snapshot and updated on a read from COUNT_SEC.

Table 74: COUNT_MO (0x044)

Field

Bit

7:4

3:0

Type

R

Description

Reserved

COUNT_MONTH

R/W

Calendar months 1-12

Bus write is snapshot and updated on a write to COUNT_YEAR.

Bus read is snapshot and updated on a read from COUNT_SEC.

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PMIC for applications requiring up to 8.5 A

Table 75: COUNT_Y (0x045)

Field

Bit

7:7

6:6

Type

R

Description

Reserved

MONITOR

Reserved

R/W

Read: RTC power has been lost (0) / RTC clock okay (1).

Write: RTC_EN and CRYSTAL writing enabled (0) / disabled (1).

Fetched from VDDRTC domain at VDDCORE POR.

If set, host writes to this register are ignored; thus the host cannot

clear it.

COUNT_YEAR

5:0

R/W

Calendar year 2000 - 2063

Bus write turns on the RTC clock and sets RTC calendar.

Bus read is snapshot and updated on a read from COUNT_SEC.

Table 76: ALARM_S (0x046)

Field

Bit

Type

Description

ALARM_STATUS

7:6

R

Alarm reason

00: No alarm

01: Tick

10: Timer

11: Tick + Timer

ALARM_SEC

5:0

R/W

Alarm seconds 0-59

Bus write is snapshot and updated on a write to ALARM_YEAR.

Table 77: ALARM_MI (0x047)

Field

Bit

7:6

5:0

Type

R

Description

Reserved

ALARM_MIN

Reserved

R/W

Alarm minutes 0-59

Bus write is snapshot and updated on a write to ALARM_YEAR.

Table 78: ALARM_H (0x048)

Field

Bit

7:5

4:0

Type

R

Description

Reserved

ALARM_HOUR

Reserved

R/W

Alarm hours 0-23

Bus write is snapshot and updated on a write to ALARM_YEAR.

Table 79: ALARM_D (0x049)

Field

Bit

7:5

4:0

Type

R

Description

Reserved

ALARM_DAY

Reserved

R/W

Alarm days 1-31

Bus write is snapshot and updated on a write to ALARM_YEAR.

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PMIC for applications requiring up to 8.5 A

Table 80: ALARM_MO (0x04A)

Field

Bit

7:6

5:5

4:4

Type

R

Description

Reserved

TICK_WAKE

TICK_TYPE

Reserved

R/W

Allows a tick to wake the chip from RTC mode

Tick period

0: every second

1: every minute

ALARM_MONTH

3:0

R/W

Alarm months 1-12

Bus write is snapshot and updated on a write to ALARM_YEAR.

Table 81: ALARM_Y (0x04B)

Field

Bit

7:7

6:6

Type

R/W

Description

TICK_ON

ALARM_ON

Enable the tick function.

Enable the alarm function. Alarm time is set with the ALARM_*

registers

ALARM_YEAR

5:0

R/W

Alarm years 2000 - 2063

Table 82: SECOND_A (0x04C)

Field

Bit

Type

Description

SECONDS_A

7:0

R

RTC seconds counter least significant byte

Table 83: SECOND_B (0x04D)

Field

Bit

Type

Description

SECONDS_B

7:0

R

RTC seconds counter byte

Bus read is snapshot and updated on a read from SECONDS_A.

Table 84: SECOND_C (0x04E)

Field

Bit

Type

Description

SECONDS_C

7:0

R

RTC seconds counter byte

Bus read is snapshot and updated on a read from SECONDS_A.

Table 85: SECOND_D (0x04F)

Field

Bit

Type

Description

SECONDS_D

7:0

R

RTC seconds counter most significant byte

Bus read is snapshot and updated on a read from SECONDS_A.

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A.2 PAGE 1

A.2.1

Power Supply Sequencer

Table 86: SEQ (0x081)

Field

Bit

7:4

3:0

Type

R/W

R

Description

Reserved

SEQ_POINTER

Actual power sequencer position

Table 87: SEQ_TIMER (0x082)

Field

Bit

Type

Description

SEQ_DUMMY

7:4

R/W

Waiting time for power sequencer slots which do not have an

associated power supply.

0000: 32 µs

0001: 64 µs

0010: 96 µs

0011: 128 µs

0100: 160 µs

0101: 192 µs

0110: 224 µs

0111: 256 µs

1000: 288 µs

1001: 384 µs

1010: 448 µs

1011: 512 µs

1100: 1.024 ms

1101: 2.048 ms

1110: 4.096 ms

1111: 8.192 ms

SEQ_TIME

3:0

R/W

Length of each sequencer time slot

0000: 32 µs

0001: 64 µs

0010: 96 µs

0011: 128 µs

0100: 160 µs

0101: 192 µs

0110: 224 µs

0111: 256 µs

1000: 288 µs

1001: 384 µs

1010: 448 µs

1011: 512 µs

1100: 1.024 ms

1101: 2.048 ms

1110: 4.096 ms

1111: 8.192 ms

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Table 88: ID_2_1 (0x083)

Field

Bit

7:4

3:0

Type

R/W

Description

LDO2_STEP

LDO1_STEP

Sequencer step for LDO2

Sequencer step for LDO1

Table 89: ID_4_3 (0x084)

Field

Bit

Type

R/W

Description

LDO4_STEP

LDO3_STEP

7:4

3:0

Sequencer step for LDO4

Sequencer step for LDO3

Table 90: ID_12_11 (0x088)

Field

Bit

7:4

3:0

Type

R/W

Description

PD_DIS_STEP

Reserved

Sequencer step for PD_DIS register functionality.

Reserved

Table 91: ID_14_13 (0x089)

Field

Bit

7:4

3:0

Type

R/W

Description

BUCK2_STEP

BUCK1_STEP

Sequencer step for Buck2

Sequencer step for Buck1

Table 92: ID_16_15 (0x08A)

Field

Bit

7:4

3:0

Type

R/W

Description

BUCK3_STEP

BUCK4_STEP

Sequencer step for Buck3

Sequencer step for Buck4

Table 93: ID_22_21 (0x08D)

Field

Bit

7:4

3:0

Type

R/W

Description

GP_FALL1_STEP

GP_RISE0_STEP

Sequencer step to de-assert GPO0

Sequencer step to assert GPO0

Table 94: ID_24_23 (0x08E)

Field

Bit

7:4

3:0

Type

R/W

Description

GP_FALL2_STEP

GP_RISE1_STEP

Sequencer step to de-assert GPO1

Sequencer step to assert GPO1

Table 95: ID_26_25 (0x08F)

Field

Bit

7:4

3:0

Type

R/W

Description

GP_FALL3_STEP

GP_RISE2_STEP

Sequencer step to de-assert GPO2

Sequencer step to assert GPO2

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PMIC for applications requiring up to 8.5 A

Table 96: ID_28_27 (0x090)

Field

Bit

7:4

3:0

Type

R/W

Description

GP_FALL4_STEP

GP_RISE3_STEP

Sequencer step to de-assert GPO3

Sequencer step to assert GPO3

Table 97: ID_30_29 (0x091)

Field

Bit

7:4

3:0

Type

R/W

Description

GP_FALL5_STEP

GP_RISE4_STEP

Sequencer step to de-assert GPO4

Sequencer step to assert GPO4

Table 98: ID_32_31 (0x092)

Field

Bit

7:4

3:0

Type

R/W

Description

EN32K_STEP

WAIT_STEP

Sequencer step to enable GPO and RTC clock

Sequencer step for WAIT register functionality

Table 99: SEQ_A (0x095)

Field

Bit

Type

Description

POWER_END

7:4

R/W

End of POWER power domain in the sequencer

SYSTEM_END <= POWER_END <= MAX_COUNT must be true.

SYSTEM_END

3:0

R/W

End of SYSTEM power domain in the sequencer

PART_DOWN <= SYSTEM_END <= POWER_END must be true.

Table 100: SEQ_B (0x096)

Field

Bit

Type

Description

PART_DOWN

7:4

R/W

Sequencer slot to stop at, when going down into STANDBY state.

1 <= PART_DOWN <= SYSTEM_END must be true.

MAX_COUNT

3:0

R/W

End of POWER1 power domain in the sequencer

POWER_END <= MAX_COUNT must be true.

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PMIC for applications requiring up to 8.5 A

Table 101: WAIT (0x097)

Field

Bit

Type

Description

WAIT_DIR

7:6

R/W

WAIT_STEP power sequence selection

00: Do not wait during WAIT_STEP of power sequencer except for

normal slot time.

01: Wait during up sequence.

10: Wait during down sequence.

11: Wait during up and down sequence.

TIME_OUT

5:5

R/W

Timeout when WAIT_MODE = 0

0: no timeout when waiting for external signal (GPIO3).

1: 500 ms timeout when waiting for external signal (GPIO3).

WAIT_MODE

WAIT_TIME

4:4

3:0

R/W

0: Wait for external signal (GPIO3) to be active.

1: Start timer and wait for expiration.

Wait timer during WAIT STEP of power sequencer (+/- 10%)

0000: Do not wait during WAIT_STEP of power sequencer except

for normal slot time.

0001: 512 µs

0010: 1.0 ms

0011: 2.0 ms

0100: 4.1 ms

0101: 8.2 ms

0110: 16.4 ms

0111: 32.8 ms

1000: 65.5 ms

1001: 128 ms

1010: 256 ms

1011: 512 ms

1100: 1.0 s

1101: 2.0 s

1110: 4.1 s

1111: 8.2 s

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Table 102: EN_32K (0x098)

Field

Bit

Type

Description

EN_32KOUT

7:7

R/W

Enable OUT_32K on the GPOs

(may be delayed depending on OUT32K_PAUSE).

RTC_CLOCK

OUT_CLOCK

6:6

5:5

R/W

Disable clock to RTC counter until stabilisation timer has expired.

Disable clock to GPOs configured as OUT_32K until stabilization

timer has expired.

DELAY_MODE

4:4

R/W

Start stabilization timer:

0: when oscillator signal is available (third falling edge)

1: when oscillator has been switched on (CRYSTAL risen)

CRYSTAL

3:3

2:0

R/W

External RTC crystal is present.

Fetched from VDDRTC domain at VDDCORE POR.

STABILISATION_TIME

Time to allow crystal oscillator to stabilize.

000: Delay off

001: 0.52 s

010: 1.0 s

011: 1.5 s

100: 2.1 s

101: 2.6 s

110: 3.1 s

111: 3.6 s

Table 103: RESET (0x099)

Field

Bit

Type

Description

RESET_EVENT

7:6

R/W

Reset timer started by:

00: EXT_WAKEUP

01: SYS_UP (register control or pin)

10: PWR_UP (register control or pin)

11: Leaving PMIC RESET mode

RESET_TIMER

5:0

R/W

0: Release nRESET immediately after the event selected by

RESET_EVENT.

1 - 31: 1.024 ms * RESET_TIMER

32-63: 1.024 ms * 32 * (RESET_TIMER-31)

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PMIC for applications requiring up to 8.5 A

A.2.2

Power Supply Control

Table 104: BUCK_ILIM_A (0x09A)

Field

Bit

7:4

3:0

Type

R/W

Description

Reserved

BUCK3_ILIM

Reserved

Buck3 current limit = (1700 + BUCK3_ILIM * 100) mA

Table 105: BUCK_ILIM_B (0x09B)

Field

Bit

7:4

3:0

Type

R/W

Description

Reserved

BUCK4_ILIM

Reserved

Buck4 current limit = (700 + BUCK4_ILIM * 100) mA

Table 106: BUCK_ILIM_C (0x09C)

Field

Bit

Type

Description

BUCK2_ILIM

7:4

R/W

Buck2 current limit = (700 + BUCK2_ILIM * 100) mA

In full-current mode the limit is internally doubled.

BUCK1_ILIM

3:0

R/W

Buck1 current limit = (700 + BUCK1_ILIM * 100) mA

In full-current mode the limit is internally doubled.

Table 107: BUCK2_CFG (0x09D)

Field

Bit

Type

Description

BUCK2_MODE

7:6

R/W

Controls the mode of the buck:

00: Controlled by BUCK2_SL_A and BUCK2_SL_B

01: Sleep (PFM)

10: Synchronous (PWM)

11: Automatic

BUCK2_PD_DIS

5:5

4:0

R/W

Disable pull-down resistor when disabled.

Reserved

Table 108: BUCK1_CFG (0x09E)

Field

Bit

Type

Description

BUCK1_MODE

7:6

R/W

Controls the mode of the buck:

00: Controlled by BUCK1_SL_A and BUCK1_SL_B

01: Sleep (PFM)

10: Synchronous (PWM)

11: Automatic

BUCK1_PD_DIS

Reserved

5:5

4:1

0:0

R/W

Disable pull-down resistor when disabled.

Reserved

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PMIC for applications requiring up to 8.5 A

Table 109: BUCK4_CFG (0x09F)

Field

Bit

Type

Description

BUCK4_MODE

7:6

R/W

Controls the mode of the buck:

00: Controlled by BUCK4_SL_A and BUCK4_SL_B

01: Sleep (PFM)

10: Synchronous (PWM)

11: Automatic

BUCK4_PD_DIS

BUCK4_VTT_EN

BUCK4_VTTR_EN

Reserved

5:5

4:4

3:3

2:0

R/W

Disable pull-down resistor when disabled.

Enable Buck4 memory bus termination mode.

Enable Buck4 memory bus termination reference voltage output.

Reserved

Table 110: BUCK3_CFG (0x0A0)

Field

Bit

Type

Description

BUCK3_MODE

7:6

R/W

Controls the mode of the buck:

00: Controlled by BUCK3_SL_A and BUCK3_SL_B

01: Sleep (PFM)

10: Synchronous (PWM)

11: Automatic

BUCK3_PD_DIS

5:5

4:0

R/W

Disable pull-down resistor when disabled.

Reserved

Table 111: VBUCK2_A (0x0A3)

Field

Bit

Type

Description

BUCK2_SL_A

7:7

R/W

This control is only effective when BUCK2_MODE = 0

0: forced to synchronous mode (PWM) when 'A' setting is active.

1: forced to sleep mode (PFM) when 'A' setting is active.

VBUCK2_A

6:0

R/W

From 0.3 V (0x00) to 1.57 V (0x7F) in steps of 10 mV

Table 112: VBUCK1_A (0x0A4)

Field

Bit

Type

Description

BUCK1_SL_A

7:7

R/W

This control is only effective when BUCK1_MODE = 0

0: forced to synchronous mode (PWM) when 'A' setting is active.

1: forced to sleep mode (PFM) when 'A' setting is active.

VBUCK1_A

6:0

R/W

From 0.3 V (0x00) to 1.57 V (0x7F) in steps of 10 mV

Table 113: VBUCK4_A (0x0A5)

Field

Bit

Type

Description

BUCK4_SL_A

7:7

R/W

This control is only effective when BUCK4_MODE = 0

0: forced to synchronous mode (PWM) when 'A' setting is active.

1: forced to sleep mode (PFM) when 'A' setting is active.

VBUCK4_A

6:0

R/W

From 0.53 V (0x00) to 1.8 V (0x7F) in steps of 10 mV

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Table 114: VBUCK3_A (0x0A7)

Field

Bit

Type

Description

BUCK3_SL_A

7:7

R/W

This control is only effective when BUCK3_MODE = 0

0: forced to synchronous mode (PWM) when 'A' setting is active.

1: forced to sleep mode (PFM) when 'A' setting is active.

VBUCK3_A

6:0

R/W

From 0.80 V (0x00) to 3.34 V (0x7F) in steps of 20 mV

Table 115: VLDO1_A (0x0A9)

Field

Bit

7:7

6:6

5:0

Type

R/W

Description

LDO1_SL_A

Reserved

VLDO1_A

Force LDO sleep mode if VLDO1_A is active.

Reserved

From 0.90 V (0x02) to 3.60 V (0x38) in steps of 50 mV

Less than 0x02: 0.90 V; greater than 0x38: 3.60 V

Table 116: VLDO2_A (0x0AA)

Field

Bit

7:7

6:6

5:0

Type

R/W

Description

LDO2_SL_A

Reserved

VLDO2_A

Force LDO sleep mode if VLDO2_A is selected.

Reserved

From 0.90 V (0x02) to 3.60 V (0x38) in steps of 50 mV

Less than 0x02: 0.90 V; greater than 0x38: 3.60 V

Table 117: VLDO3_A (0x0AB)

Field

Bit

7:7

6:6

5:0

Type

R/W

Description

LDO3_SL_A

Reserved

VLDO3_A

Force LDO sleep mode if VLDO3_A is selected.

Reserved

From 0.90 V (0x02) to 3.60 V (0x38) in steps of 50 mV

Less than 0x02: 0.90 V; greater than 0x38: 3.60 V

Table 118: VLDO4_A (0x0AC)

Field

Bit

7:7

6:6

5:0

Type

R/W

Description

LDO4_SL_A

Reserved

VLDO4_A

Force LDO sleep mode if VLDO4_A is selected.

Reserved

From 0.90 V (0x02) to 3.60 V (0x38) in steps of 50 mV

Less than 0x02: 0.90 V; greater than 0x38: 3.60 V

Table 119: VBUCK2_B (0x0B4)

Field

Bit

Type

Description

BUCK2_SL_B

7:7

R/W

This control is only effective when BUCK2_MODE = 0

0: forced to synchronous mode (PWM) when 'B' setting is active.

1: forced to sleep mode (PFM) when 'B' setting is active.

VBUCK2_B

6:0

R/W

From 0.3 V (0x00) to 1.57 V (0x7F) in steps of 10 mV

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Table 120: VBUCK1_B (0x0B5)

Field

Bit

Type

Description

BUCK1_SL_B

7:7

R/W

This control is only effective when BUCK1_MODE = 0

0: forced to synchronous mode (PWM) when 'B' setting is active.

1: forced to sleep mode (PFM) when 'B' setting is active.

VBUCK1_B

6:0

R/W

From 0.3 V (0x00) to 1.57 V (0x7F) in steps of 10 mV

Table 121: VBUCK4_B (0x0B6)

Field

Bit

Type

Description

BUCK4_SL_B

7:7

R/W

This control is only effective when BUCK4_MODE = 0

0: forced to synchronous mode (PWM) when 'B' setting is active.

1: forced to sleep mode (PFM) when 'B' setting is active.

VBUCK4_B

6:0

R/W

From 0.53 V (0x00) to 1.8 V (0x7F) in steps of 10 mV

Table 122: VBUCK3_B (0x0B8)

Field

Bit

Type

Description

BUCK3_SL_B

7:7

R/W

This control is only effective when BUCK3_MODE = 0

0: forced to synchronous mode (PWM) when 'B' setting is active.

1: forced to sleep mode (PFM) when 'B' setting is active.

VBUCK3_B

6:0

R/W

From 0.80 V (0x00) to 3.34 V (0x7F) in steps of 20 mV

Table 123: VLDO1_B (0x0BA)

Field

Bit

7:7

6:6

5:0

Type

R/W

Description

LDO1_SL_B

Reserved

VLDO1_B

Force LDO sleep mode when ‘B’ setting is active.

Reserved

From 0.90 V (0x02) to 3.60 V (0x38) in steps of 50 mV

Less than 0x02: 0.90 V; greater than 0x38: 3.60 V

Table 124: VLDO2_B (0x0BB)

Field

Bit

7:7

6:6

5:0

Type

R/W

Description

LDO2_SL_B

Reserved

VLDO2_B

Force LDO sleep mode if VLDO2_B is selected.

Reserved

From 0.90 V (0x02) to 3.60 V (0x38) in steps of 50 mV

Less than 0x02: 0.90 V; greater than 0x38: 3.60 V

Table 125: VLDO3_B (0x0BC)

Field

Bit

7:7

6:6

5:0

Type

R/W

Description

LDO3_SL_B

Reserved

VLDO3_B

Force LDO sleep mode if VLDO3_B is selected.

Reserved

From 0.90 V (0x02) to 3.60 V (0x38) in steps of 50 mV

Less than 0x02: 0.90 V; greater than 0x38: 3.60 V

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Table 126: VLDO4_B (0x0BD)

Field

Bit

7:7

6:6

5:0

Type

R/W

Description

LDO4_SL_B

Reserved

VLDO4_B

Force LDO sleep mode if VLDO4_B is selected.

Reserved

From 0.90 V (0x02) to 3.60 V (0x38) in steps of 50 mV

Less than 0x02: 0.90 V; greater than 0x38: 3.60 V

A.2.3

BBAT Charger Control

Table 127: BBAT_CONT (0x0C5)

Field

Bit

Type

Description

BCHG_ISET

7:4

R/W

Charging current setting:

0000: Disabled

0001: 100 µA

0010: 200 µA

0011: 300 µA

0100: 400 µA

0101: 500 µA

0110: 600 µA

0111: 700 µA

1000: 800 µA

1001: 900 µA

1010: 1 mA

1011: 2 mA

1100: 3 mA

1101: 4 mA

1110: 5 mA

1111: 6 mA

BCHG_VSET

3:0

R/W

Termination voltage setting:

0000: Disabled

0001: 1.1 V

0010: 1.2 V

0011: 1.4 V

0100: 1.6 V

0101: 1.8 V

0110: 2.0 V

0111: 2.2 V

1000: 2.4 V

1001: 2.5 V

1010: 2.6 V

1011: 2.7 V

1100: 2.8 V

1101: 2.9 V

1110: 3.0 V

1111: 3.1 V

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A.3 PAGE 2

A.3.1

Customer Trim and Configuration

Table 128: INTERFACE (0x105)

Field

Bit

Type

Description

IF_BASE_ADDR

7:4

R

2-WIRE slave address MSBs. The LSBs of the slave address are

“000”. The complete slave address is then IF_BASE_ADDR * 2³.

However, the device also responds to IF_BASE_ADDR * 2³+1.

Note 1

Reserved

3:0

Reserved

Note 1 The interface configuration can be written/modified only for unmarked samples which do not have the

control OTP_APPS_LOCK asserted/fused.

Table 129: CONFIG_A (0x106)

Field

Bit

7:7

6:6

5:5

4:4

3:3

2:2

1:1

0:0

Type

R

Description

Reserved

PM_IF_HSM

PM_IF_FMP

PM_IF_V

IRQ_TYPE

PM_O_TYPE

Reserved

PM_I_V

Reserved

R/W

2-WIRE interface permanently in high speed mode

2-WIRE interface selects fast mode+ timings

2-WIRE supplied from VDDCORE (0) / V_DDIO(1).

nIRQ is active low (0) / high (1).

nRESET and nIRQ are push pull (0) / open drain (1).

Reserved

nRESETREQ, SYS_EN, PWR_EN and KEEPACT supplied from

VDDCORE (0) / V_DDIO(1).

Table 130: CONFIG_B (0x107)

Field

Bit

7:7

6:4

Type

R/W

Description

Reserved

VDD_HYST_ADJ

nVDD_FAULT comparator hysteresis from 100 mV (0x0) to 450

mV (0x7) in 50 mV steps

VDD_FAULT_ADJ

3:0

R/W

nVDD_FAULT comparator level from 2.5 V (0x0) to 3.25 V (0xF) in

50 mV steps

Table 131: CONFIG_C (0x108)

Field

Bit

7:7

6:6

5:5

4:4

3:3

Type

R/W

Description

Reserved

BUCK3_CLK_INV

Reserved

Invert Buck3 clock polarity.

Reserved

BUCK4_CLK_INV

BUCK1_CLK_INV

Invert Buck4 clock polarity.

Invert Buck1 clock polarity with respect to Buck2.

Enable active discharging of buck rails.

Reserved

BUCK_ACTV_DISCHRG 2:2

Reserved

1:0

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Table 132: CONFIG_D (0x109)

Field

Bit

7:6

5:5

4:3

2:2

1:1

0:0

Type

R/W

Description

Reserved

FORCE_RESET

Reserved

Keep nRESET always asserted

Reserved

SYSTEM_EN_RD

NIRQ_MODE

GPI_V

Suppress loading SYSTEM_EN during OTP_RD2

nIRQ will be asserted from events during POWERDOWN

GPIs, except power manager controls, supplied from VDDCORE

(0) / VDDIO (1).

Table 133: CONFIG_E (0x10A)

Field

Bit

7:5

4:4

3:3

2:2

1:1

0:0

Type

R/W

Description

Reserved

BUCK3_AUTO

Reserved

When powering up, enable and select VBUCK3_A.

Reserved

BUCK4_AUTO

BUCK2_AUTO

BUCK1_AUTO

Enable and select VBUCK4_A when powering up.

Enable and select VBUCK2_A when powering up.

Enable and select VBUCK1_A when powering up.

Table 134: CONFIG_G (0x10C)

Field

Bit

7:4

3:3

2:2

1:1

0:0

Type

R/W

Description

Reserved

LDO4_AUTO

LDO3_AUTO

LDO2_AUTO

LDO1_AUTO

Enable and select VLDO4_A when powering up.

Enable and select VLDO3_A when powering up.

Enable and select VLDO2_A when powering up.

Enable and select VLDO1_A when powering up.

Table 135: CONFIG_H (0x10D)

Field

Bit

7:7

6:6

5:5

4:4

3:3

2:0

Type

R/W

Description

Reserved

BUCK1_FCM

BUCK2_FCM

Reserved

Buck full-current mode (double pass device and current limit).

Reserved

BUCK_MERGE

Reserved

Buck1/2 dual-phase configuration.

Reserved

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Table 136: CONFIG_I (0x10E)

Field

Bit

Type

Description

LDO_SD

7:7

R/W

Enable switching off an LDO if an over-current is detected longer

than 200 ms.

INT_SD_MODE

6:6

5:5

R/W

Skip sequencer and dummy slots on shutdown from internal fault.

HOST_SD_MODE

Skip sequencer and dummy slots on shutdown from control

SHUTDOWN or nRESETREQ pin.

KEY_SD_MODE

WATCHDOG_SD

NONKEY_SD

4:4

3:3

2:2

1:0

R/W

Enable power-on reset on shutdown from nONKEY.

Enable shutdown instead of power-down on watchdog timeout.

Enable shutdown via long press of nONKEY.

NONKEY_PIN

nONKEY function

See section 7.1.1 for further information.

Table 137: CONFIG_J (0x10F)

Field

Bit

7:7

6:6

5:4

Type

R/W

Description

IF_RESET

Enable host interface reset via nRESETREQ pin

Enable 35 ms timeout for 2-wire interfaces

Minimum RESET mode duration:

TWOWIRE_TO

RESET_DURATION

00: 22 ms

01: 100 ms

10: 500 ms

11: 1 s

SHUT_DELAY

KEY_DELAY

3:2

1:0

R/W

Shutdown delay (+ KEY_DELAY) for nONKEY

nONKEY locking threshold

Table 138: CONFIG_K (0x110)

Field

Bit

7:5

4:4

Type

R/W

Description

Reserved

GPIO4_PUPD

Reserved

GPI: pull-down enabled

open drain GPO: pull-up enabled

GPIO3_PUPD

GPIO2_PUPD

GPIO1_PUPD

GPIO0_PUPD

3:3

2:2

1:1

0:0

R/W

GPI: pull-down enabled

open drain GPO: pull-up enabled

GPI: pull-down enabled

open drain GPO: pull-up enabled

GPI: pull-down enabled

open drain GPO: pull-up enabled

GPI: pull-down enabled

open drain GPO: pull-up enabled

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Table 139: CONFIG_M (0x112)

Field

Bit

Type

Description

OSC_FRQ

7:4

R/W

Adjust internal oscillator frequency:

1000: -10.67 %

…

1111: -1.33 %

0000: 0.00 %

0001: +1.33 %

…

0111: +9.33 %

WDG_MODE

Reserved

3:3

2:2

1:1

0:0

R/W

Activate watchdog Halt operation mode.

Reserved

A.3.2

Customer Device Specific

Table 140: GP_ID_0 (0x121)

Field

Bit

Type

Description

GP_0

7:0

R/W

General purpose register Note 1

Note 1 Initial value at start-up is the OTP ini file version number.

Table 141: GP_ID_1 (0x122)

Field

Bit

Type

Description

GP_1

7:0

R/W

General purpose register

Table 142: GP_ID_2 (0x123)

Field

Bit

Type

Description

GP_2

7:0

R/W

General purpose register

Table 143: GP_ID_3 (0x124)

Field

Bit

Type

Description

GP_3

7:0

R/W

General purpose register

Table 144: GP_ID_4 (0x125)

Field

Bit

Type

Description

GP_4

7:0

R/W

General purpose register

Table 145: GP_ID_5 (0x126)

Field

Bit

Type

Description

GP_5

7:0

R/W

General purpose register

Table 146: GP_ID_6 (0x127)

Field

Bit

Type

Description

GP_6

7:0

R/W

General purpose register

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Table 147: GP_ID_7 (0x128)

Field

Bit

Type

Description

GP_7

7:0

R/W

General purpose register

Table 148: GP_ID_8 (0x129)

Field

Bit

Type

Description

GP_8

7:0

R/W

General purpose register

Table 149: GP_ID_9 (0x12A)

Field

Bit

Type

Description

GP_9

7:0

R/W

General purpose register

Table 150: GP_ID_10 (0x12B)

Field

Bit

Type

Description

GP_10

7:0

R/W

General purpose register Note 1

Note 1 The value is persistent through a warm reset such as triggered by the nRESETREQ pin or by the

SHUTDOWN control in register CONTROL_F.

Table 151: GP_ID_11 (0x12C)

Field

Bit

Type

Description

GP_11

7:0

R/W

General purpose register Note 1

Note 1 The value is persistent through a warm reset such as triggered by the nRESETREQ pin or by the

SHUTDOWN control in register CONTROL_F.

Table 152: GP_ID_12 (0x12D)

Field

Bit

Type

Description

GP_12

7:0

R/W

General purpose register Note 1

Note 1 The value is persistent through a warm reset such as triggered by the nRESETREQ pin or by the

SHUTDOWN control in register CONTROL_F.

Table 153: GP_ID_13 (0x12E)

Field

Bit

Type

Description

GP_13

7:0

R/W

General purpose register Note 1

Note 1 The value is persistent through a warm reset such as triggered by the nRESETREQ pin or by the

SHUTDOWN control in register CONTROL_F.

Table 154: GP_ID_14 (0x12F)

Field

Bit

Type

Description

GP_14

7:0

R/W

General purpose register Note 1

Note 1 The value is persistent through a warm reset such as triggered by the nRESETREQ pin or by the

SHUTDOWN control in register CONTROL_F.

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Table 155: GP_ID_15 (0x130)

Field

Bit

Type

Description

GP_15

7:0

R/W

General purpose register Note 1

Note 1 The value is persistent through a warm reset such as triggered by the nRESETREQ pin or by the

SHUTDOWN control in register CONTROL_F.

Table 156: GP_ID_16 (0x131)

Field

Bit

Type

Description

GP_16

7:0

R/W

General purpose register Note 1

Note 1 The value is persistent through a warm reset such as triggered by the nRESETREQ pin or by the

SHUTDOWN control in register CONTROL_F.

Table 157: GP_ID_17 (0x132)

Field

Bit

Type

Description

GP_17

7:0

R/W

General purpose register Note 1

Note 1 The value is persistent through a warm reset such as triggered by the nRESETREQ pin or by the

SHUTDOWN control in register CONTROL_F.

Table 158: GP_ID_18 (0x133)

Field

Bit

Type

Description

GP_18

7:0

R/W

General purpose register Note 1

Note 1 The value is persistent through a warm reset such as triggered by the nRESETREQ pin or by the

SHUTDOWN control in register CONTROL_F.

Table 159: GP_ID_19 (0x134)

Field

Bit

Type

Description

GP_19

7:0

R/W

General purpose register Note 1

Note 1 The value is persistent through a warm reset such as triggered by the nRESETREQ pin or by the

SHUTDOWN control in register CONTROL_F.

Table 160: DEVICE_ID (0x181)

Field

Bit

Type

Description

DEV_ID

7:0

R

Device ID

Table 161: VARIANT_ID (0x182)

Field

MRC

VRC

Bit

7:4

3:0

Type

R

Description

Mask revision code

Chip variant code

R/W

Table 162: CUSTOMER_ID (0x183)

Field

Bit

Type

Description

CUST_ID

7:0

R

Customer ID

Table 163: CONFIG_ID (0x184)

Field

Bit

Type

Description

CONFIG_REV

7:0

R

OTP settings revision

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Revision History

Table 164: Revision History

Revision

Date

Changes

3.3

17-Nov-2016

Table 4: Recommended Operating Conditions

●

Replaced ambient temperature parameter (T_A) with junction

temperature (T_J)

Section 4: Electrical Characteristics

●

Replaced ambient temperature parameter (T_A) with junction

temperature (T_J)

Table 8: LDO1 Electrical Characteristics

●

Renamed parameter I_OUTto I_{OUT_MAX}

Revised conditions:

○

V_DROPOUT: Removed I_OUTfor V_DD= 1.5 V condition

V_{TR_LOAD}: Added V_LDO= 3.3 V

●

Added T_Ato N, I_{Q_ON}, and I_{Q_SLEEP}conditions

Table 9: LDO2, LDO3, LDO4 Electrical Characteristics

●

Renamed parameter I_OUTto I_{OUT_MAX}

Revised conditions:

○

V_DD: Added V_DD= V_SYS

I_{OUT_MAX}and V_DROPOUT: Added 1.8 V condition

V_{TR_LOAD}: Added V_LDO= 3.3 V

●

Added T_Ato I_{Q_ON}and I_{Q_SLEEP}conditions

Added Note 1

Table 11: Buck1, Buck2 Electrical Characteristics

●

Revised conditions:

○

I_OUT: Removed inductor condition

I_{Q_ON}: Added V_DD= 3.6 V and T_A

f: Added OSC_FRQ = ‘0000’

R_PMOSand R_NMOS: V_SYSto V_DD

I_{AUTO_THR}: V_INto V_DD,R_TRACK 45 mΩ

●

V_BUCK: Min from 0.7 V to 0.3 V

Revised conditions and limits:

○

L_BUCK: Removed half/full-current mode, Min = 0.7 µH

R_{L_DCR}: Removed half/full-current mode, Typ = 55 mΩ

I_OUT: Removed half-current mode L > 0.6 µH

I_LIM: Split into half/full-current modes: Min/Max

700 mA/2200 mA and 1400 mA/4400 mA

●

Added Note 1 and Note 3

Table 12: Buck3 Electrical Characteristics

●

Revised conditions:

○

V_DD: Added V_DD= V_SYS

I_OUT: Removed inductor condition

I_{Q_ON}: Added T_A

f: Added OSC_FRQ = ‘0000’

R_PMOSand R_NMOS: V_SYSto V_DD

●

Revised limits:

○

L_BUCK: Min from 0.6 µH to 0.7 µH

R_{L_DCR}: Min/Max from 80 mΩ/120 mΩ to 55 mΩ/100 mΩ

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PMIC for applications requiring up to 8.5 A

Revision

Date

Changes

○

I_LIM: Min/Max from 1500 mA/3000 mA to 1700 mA/3200 mA

●

Added Note 2

Table 13: Buck4 Electrical Characteristics

●

Revised conditions:

○

V_DD: Added V_DD= V_SYS

I_OUT: Removed inductor from condition and L > 0.6 µH condition

I_{Q_ON}: Added T_A

f: Added OSC_FRQ = ‘0000’

R_PMOSand R_NMOS: V_SYSto V_DD

V_{BUCK_PFM}: Removed output voltages below 0.7 V

I_{AUTO_THR}: V_INto V_DD,R_TRACK 45 mΩ

●

Revised limits:

○

I_LIM: Min/Max from 500 mA/2000 mA to 700 mA/2200 mA

I_{LIM_ACC}: Split into 1400 mA/2200 mA, Min/Max: -15%/25% and

-10%/15%

Added Note 1 and Note 3

Table 16: Added Note 1

Table 18: Added Note 1

Table 19: Current Consumption Electrical Characteristics

●

I_DDRTC:

○

Revised condition from V_SYS> 2.2 V to > 2.0 V and removed

supplies and RTC condition

●

Added Note 1 and Note 2

Section 7.1.2: Removed internal pull-up from description

Section 7.7.8: New

Section 7.14: Added application oscillator information

Section 7.15: Revised WDKICK description

Section 8: Register Map

●

Table 29: CONFIG_A control names corrected to PM_IF_HSM,

PM_IF_FMP, and PM_IF_V, added Reserved to reserved registers

●

Table 41: Added E_TICK

Table 44: Added M_TICK

Appendix A: Updated part numbers, revised register descriptions,

added register Type column

Other:

●

Editorial changes

Datasheet

Revision 3.3

24-Nov-2016

94 of 96

DA9062

PMIC for applications requiring up to 8.5 A

Revision

Date

Changes

Table 3: Absolute Maximum Ratings

3.2

17-Feb-2016

●

replaced T_Aparameter with T_J

replaced Note 1

ESD tolerance renamed to ESD protection HBM and moved the

value to Min

●

added ESD protection CDM parameters

Table 4: Recommended Operating Conditions

●

added Maximum power dissipation

added Note 2

Table 5: Digital I/O Electrical Characteristics

R_PU: values aligned with characterisation results:

●

○

V_DDIO= 1.5 V: Min value changed from 100 kΩ to 60 kΩ

V_DDIO= 1.5 V: Max value changed from 340 kΩ to 310 kΩ

V_DDIO= 1.8 V: Min value changed from 65 kΩ to 45 kΩ

V_DDIO= 1.8 V: Max value changed from 175 kΩ to 190 kΩ

V_DDIO= 3.3 V: Min value changed from 25 kΩ to 20 kΩ

Table 10: LDOCORE Electrical Characteristics

●

removed V_DDparameter

added V_DROPOUTparameter

added Note 1 and Note 2

added NOTE

Table 11, Table 12, Table 13: Buck1 to Buck4 electrical characteristics

V_{BUCK_ACC}: added Note 1

Table 13: Buck4 Electrical Characteristics

●

V_TTR: removed I_OUTtest condition

C_OUT: renamed to C_VTTR

Table 14: Backup Battery Charger Electrical Characteristics

●

I_{SET_BCHG}: removed 1 mA to 6 mA test condition

added C_OUT, R_{COUT_ESR,}V_DROPOUTparameters

added Note 1 and Note 2

Table 17: System Supply Voltage Supervision Electrical Characteristics

●

added Note 1 and Note 2

V_{DD_FAULT_LOWER}: removed test condition

V_HYS: renamed to V_{DD_FAULT_HYS}and removed test condition

added V_REF,C_VREF, R_IREFparameters

Table 18: Junction Temperature Supervision Electrical Characteristics

added Note 1

Figure 22: Structure of the Power Supply Sequencer

●

added STANDBY mode

added NOTE

Register Map

●

Table 29 CONFIG_A control names corrected to PM_IF_HSM,

PM_IF_FMP, and PM_IF_V

●

Table 49: SLEW_RATE: 20 mV/step for Buck3 added

Table 105: BUCK_ILIM_B and BUCK4_ILIM: Note removed

regarding full-current mode

Other:

●

REG_PAGE corrected to PAGE

NSHUTDOWN corrected to NRESETREQ

Editorial changes

3.1

30-Oct-2015

First production datasheet release

Datasheet

Revision 3.3

24-Nov-2016

95 of 96

DA9062

PMIC for applications requiring up to 8.5 A

Status Definitions

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Development

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development. Specifications may be changed in any manner

without notice.

2.<n>

3.<n>

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Final

Qualification

Production

This datasheet contains the specifications and preliminary

characterization data for products in pre-production.

Specifications may be changed at any time without notice in

order to improve the design.

This datasheet contains the final specifications for products in

volume production. The specifications may be changed at any

time in order to improve the design, manufacturing and supply.

Major specification changes are communicated via Customer

Product Notifications. Datasheet changes are communicated via

www.dialog-semiconductor.com.

4.<n>

Obsolete

Archived

This datasheet contains the specifications for discontinued

products. The information is provided for reference only.

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Datasheet

Revision 3.3

24-Nov-2016

96 of 96


型号：	DA9062-xxAM1-A
厂家：	Dialog Semiconductor
描述：	PMIC for applications requiring up to 8.5 A 集成电源管理电路
文件：	总96页 (文件大小：1593K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DA9062-xxAM1-A [DIALOG]

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