DA9063-xxHO2-A_技术文档

DA9063

System PMIC for Mobile Application Processors

General Description

DA9063 is a high current system PMIC suitable for dual- and quad-core processors used in

smartphones, tablets, ultra-books, and other handheld applications that require up to 5 A core

processor supply.

DA9063 contains six DC-DC buck converters designed for small external 1 µH inductors capable of

supplying in total up to 12 A continuous output (0.3 V to 3.3 V). The buck converters do not require

external Schottky diodes. They dynamically optimize their efficiency depending on the load current

using an Automatic Sleep mode. The bucks incorporate pin and s/w controlled Dynamic Voltage

Control (DVC) to support processor load adaptive adjustment of the supply voltage. One buck can

also be used in a DDR memory termination mode.

Eleven SmartMirror^TMprogrammable LDO regulators are incorporated, rated up to 300 mA. All

support remote capacitor placement and can support operation from a low 1.5 V/1.8 V input voltage:

this allows the linear regulators to be cascaded with a suitable buck supply to improve overall system

efficiency.

Processor core leakage can be minimized by using the integrated rail switch controller for ultra-fast

power domain isolation/reconnection while current limited switches provide support for external

peripherals such as external accessory or memory cards.

There are five distinct operating modes consuming < 20 µA including a 1.5 µA RTC mode with alarm

and wakeup. A system monitor watchdog can be enabled in ACTIVE mode.

The DA9063 provides an OTP start-up sequencing engine that offers autonomous hardware system

start-up or software controlled start-up and configurable power modes. The on key detects the button

press time and offers configurable key lock and application shutdown functions. Up to 16 freely

configurable GPIO pins can perform system functions, including: keypad supervision, application

wakeup, and timing controlled external regulator, power switch, or other IC enable.

An integrated 10-channel ADC includes advanced voltage monitoring, internal temperature

supervision, three general-purpose channels with programmable high/low thresholds, an integrated

current source for resistive measurements, and system voltage monitoring with a programmable low-

voltage warning. The ADC has 8-bit resolution in AUTO mode and 10-bit resolution in manual

conversion mode.

Three RGB-LED driver pins are provided with PWM control.

LDO8 can be configured as a 6-bit, PWM-controlled, vibration motor driver with automatic battery

voltage correction.

Datasheet

DA9063_2v1

23-Mar-2017

CFR0011-120-00

1 of 219

DA9063

System PMIC for Mobile Application Processors

Key Features

■

6 DC-DC buck converters with DVC

■

RGB-LED driver with autonomous flashing

PWM vibration motor driver

□

2.5 A BuckCore1

2.5 A BuckCore2

2.5 A BuckPro

1.5 A BuckPeri

1.5 A BuckMem

1.5 A BuckIO

5 A in dual phase

mode

10-bit ADC with nine channels and

configurable alarm thresholds

■

Regulator supervision with automatic under-

/over-voltage protection

3 A in merged

mode

■

Coin cell/super-capacitor backup charger

Ultra-low power, 1.5 µA RTC with alarm and

oscillator circuitry with crystal frequency

adjustment

■

3 MHz switching frequency (± 10 %) (allows

use of low profile [1 mm] 1 μH inductors)

■

Buck with DDR memory termination option

11 programmable LDO regulators:

■

-40 °C to +125 °C junction temperature

operation

□

3 low noise, 4 with DVC, 5 with current

limited switch mode

Two package variants:

□

100 VFBGA 8.0 mm x 8.0 mm x 1.0 mm

(0.8 mm pitch), solder ball diameter

0.30 mm

■

Two rail switches

Power Manager with programmable

regulators, rail switch start-up, and

configurable low power modes

□

100 TFBGA 8.0 mm x 8.0 mm x 1.2 mm

(0.8 mm pitch), solder ball diameter

0.45 mm

■

Multiple master application support via two

independent control interfaces

■

Automotive AEC-Q100 Grade 3 available

■

System monitor with watchdog timer

Up to 16 flexible GPIO pins for enhanced

wakeup and peripheral control

Applications

■

Smartphones

■

Navigation devices

Ultrabooks

■

Set-top boxes, TV, and media players

Portable medical devices

Industrial control

Tablets, e-books

Car infotainment and ADAS

Datasheet

DA9063_2v1

23-Mar-2017

CFR0011-120-00

2 of 219

DA9063

System PMIC for Mobile Application Processors

Contents

General Description ............................................................................................................................ 1

Key Features ........................................................................................................................................ 2

Applications ......................................................................................................................................... 2

Contents ............................................................................................................................................... 3

1

2

3

4

References ..................................................................................................................................... 7

Block Diagram ............................................................................................................................... 7

Regulator Overview....................................................................................................................... 8

Package Information................................................................................................................... 11

4.1 Package Outlines................................................................................................................ 11

4.2 Pinout .................................................................................................................................. 13

5

Electrical Characteristics ........................................................................................................... 18

5.1 Absolute Maximum Ratings ................................................................................................ 18

5.2 Recommended Operating Conditions................................................................................. 18

5.2.1

Power Derating Curves........................................................................................ 19

5.3 Typical Current Consumption ............................................................................................. 20

5.4 Digital I/O Characteristics.................................................................................................... 21

5.5 Watchdog............................................................................................................................ 23

5.6 Power Manager and HS-2-Wire Control Bus...................................................................... 23

5.7 4-Wire Control Bus.............................................................................................................. 24

5.8 LDO Voltage Regulators ..................................................................................................... 26

5.8.1

5.8.2

5.8.3

5.8.4

5.8.5

5.8.6

5.8.7

5.8.8

5.8.9

LDO1.................................................................................................................... 26

LDO2.................................................................................................................... 27

LDO3.................................................................................................................... 28

LDO4.................................................................................................................... 30

LDO5.................................................................................................................... 31

LDO6.................................................................................................................... 33

LDO7.................................................................................................................... 34

LDO8.................................................................................................................... 36

LDO9.................................................................................................................... 38

5.8.10 LDO10.................................................................................................................. 39

5.8.11 LDO11.................................................................................................................. 41

5.8.12 LDOCORE ........................................................................................................... 42

5.9 DC/DC Buck Converters ..................................................................................................... 43

5.9.1

5.9.2

5.9.3

5.9.4

5.9.5

5.9.6

BUCKCORE1 and BUCKCORE2........................................................................ 43

BUCKPRO ........................................................................................................... 46

BUCKMEM .......................................................................................................... 50

BUCKIO ............................................................................................................... 52

BUCKPERI .......................................................................................................... 53

Typical Characteristics......................................................................................... 55

5.10 Buck Rail Switches.............................................................................................................. 58

5.11 Backup Battery Charger...................................................................................................... 58

5.12 General Purpose ADC ........................................................................................................ 59

Datasheet

DA9063_2v1

23-Mar-2017

CFR0011-120-00

3 of 219

DA9063

System PMIC for Mobile Application Processors

5.13 32K Oscillator...................................................................................................................... 60

5.14 Internal Oscillator ................................................................................................................ 60

5.15 POR, Reference Generation, and Voltage Supervision...................................................... 61

5.16 Thermal Supervision ........................................................................................................... 61

6

Functional Description ............................................................................................................... 62

6.1 Power Manager IO Ports..................................................................................................... 63

6.1.1

6.1.2

6.1.3

On/Off Port (nONKEY)......................................................................................... 63

Wakeup Port (CHG_WAKE)................................................................................ 64

Hardware Reset (nOFF, nSHUTDOWN, nONKEY, GPIO14, GPIO15,

WATCHDOG) ...................................................................................................... 64

6.1.4

6.1.5

6.1.6

6.1.7

6.1.8

6.1.9

Reset Output (nRESET) ...................................................................................... 64

System Enable (SYS_EN)................................................................................... 65

Power Enable (PWR_EN).................................................................................... 65

Power1 Enable (PWR1_EN) ............................................................................... 65

GP_FB1, General Purpose Signal 1 (EXT_WAKEUP/READY).......................... 65

GP_FB2, General Purpose Signal 2 (PWR_OK/KEEP_ACT)............................. 66

6.1.10 GP_FB3, General Purpose Signal 3 (OUT32K_2/nVIB_BRAKE)....................... 66

6.1.11 Supply Rail Fault (nVDD_FAULT)....................................................................... 66

6.1.12 Interrupt Request (nIRQ) ..................................................................................... 67

6.1.13 Real Time Clock Output (OUT_32K)................................................................... 67

6.1.14 IO Supply Voltage (VDD_IO1 and VDD_IO2) ..................................................... 67

6.2 Operating Modes................................................................................................................. 68

6.2.1

6.2.2

6.2.3

6.2.4

6.2.5

6.2.6

6.2.7

ACTIVE Mode...................................................................................................... 68

POWERDOWN Mode.......................................................................................... 68

RESET Mode....................................................................................................... 69

RTC Mode ........................................................................................................... 70

DELIVERY Mode................................................................................................. 70

NO-POWER Mode............................................................................................... 71

Power Commander Mode.................................................................................... 71

6.3 Start-Up from NO-POWER Mode ....................................................................................... 72

6.3.1 Power-On-Reset (nPOR)..................................................................................... 72

6.4 Exiting Reset Mode and Application Wakeup..................................................................... 72

6.5 Power Supply Sequencer.................................................................................................... 74

6.5.1

6.5.2

6.5.3

6.5.4

6.5.5

Powering Up ........................................................................................................ 74

Power-Up Timing................................................................................................. 77

Programmable Slot Delays.................................................................................. 77

Powering Down.................................................................................................... 78

User Programmable Delay .................................................................................. 78

6.6 System Monitor (Watchdog) ............................................................................................... 80

6.7 GPIO Extender.................................................................................................................... 80

6.8 Control Interfaces................................................................................................................ 84

6.8.1

6.8.2

Power Manager Interface (4- and 2-WIRE Control Bus)..................................... 84

High Speed 2-WIRE Interface ............................................................................. 91

6.9 Voltage Regulators.............................................................................................................. 91

6.9.1

6.9.2

6.9.3

Regulators Controlled by Software...................................................................... 92

Regulators Controlled by Hardware .................................................................... 92

Power Sequencer Control of LDOs ..................................................................... 93

Datasheet

DA9063_2v1

23-Mar-2017

CFR0011-120-00

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DA9063

System PMIC for Mobile Application Processors

6.9.4

6.9.5

6.9.6

6.9.7

6.9.8

6.9.9

Dynamic Voltage Control..................................................................................... 94

Voltage Tracking Mode LDO1 ............................................................................. 94

Pull-Down Resistor .............................................................................................. 94

Bypass Mode and Current Limit .......................................................................... 95

LDO Supply from Buck Converter ....................................................................... 95

LDO Sleep Mode for Reduced I_out....................................................................... 95

6.9.10 Vibration Motor Driver.......................................................................................... 96

6.9.11 Core Regulator LDOCORE.................................................................................. 96

6.10 DC/DC Buck Converters ..................................................................................................... 97

6.10.1 BUCKCORE1, BUCKCORE2, and BUCKPRO................................................... 99

6.10.2 BUCKPRO in DDR Memory Bus Termination Mode......................................... 100

6.10.3 BUCKMEM and BUCKIO in Merged Mode ....................................................... 100

6.11 Buck Rail Switches............................................................................................................ 101

6.12 Backup Battery Charger/RTC Supply Rail Generator....................................................... 102

6.13 General Purpose ADC ...................................................................................................... 103

6.13.1 ADC Overview ................................................................................................... 103

6.13.2 ADC Input MUX ................................................................................................. 103

6.13.3 Manual Conversion Mode.................................................................................. 104

6.13.4 Automatic Measurements Scheduler................................................................. 104

6.13.5 Fixed Threshold Comparator............................................................................. 108

6.14 Real Time Clock................................................................................................................ 109

6.14.1 32K Oscillator .................................................................................................... 109

6.14.2 RTC Counter and Alarm .................................................................................... 111

6.15 Adjustable Frequency Internal Oscillator .......................................................................... 112

6.16 Reference Voltage Generation: VREF, VLNREF ............................................................. 112

6.17 Thermal Supervision ......................................................................................................... 112

6.18 Main System Rail Voltage Supervision............................................................................. 112

7

8

Register Map.............................................................................................................................. 113

Application Information............................................................................................................ 116

8.1 Capacitor Selection........................................................................................................... 116

8.2 Backup Device .................................................................................................................. 117

8.3 Inductor Selection ............................................................................................................. 117

8.4 Resistors ........................................................................................................................... 118

8.5 External Pass Transistors ................................................................................................. 118

8.6 Crystal ............................................................................................................................... 118

8.7 Layout Guidelines ............................................................................................................. 119

8.7.1

8.7.2

8.7.3

8.7.4

General Recommendations............................................................................... 119

LDOs and Switched Mode Supplies.................................................................. 119

Crystal Oscillator................................................................................................ 119

Thermal Connection, Land Pad, and Stencil Design......................................... 119

9

Definitions.................................................................................................................................. 120

9.1 Power Dissipation and Thermal Design............................................................................ 120

9.2 Regulator Parameter - Dropout Voltage ........................................................................... 121

9.3 Regulator Parameter - Power Supply Rejection............................................................... 121

9.4 Regulator Parameter - Line Regulation ............................................................................ 121

9.5 Regulator Parameter - Load Regulation ........................................................................... 122

Datasheet

DA9063_2v1

23-Mar-2017

CFR0011-120-00

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DA9063

System PMIC for Mobile Application Processors

10 Ordering Information ................................................................................................................ 123

Appendix A Register Descriptions ................................................................................................ 124

A.1 Register Page Control....................................................................................................... 124

A.2 Register Page 0 ................................................................................................................ 124

A.2.1

A.2.2

A.2.3

A.2.4

A.2.5

A.2.6

Power Manager Control and Monitoring............................................................ 124

GPIO Control ..................................................................................................... 133

Regulator Control............................................................................................... 140

GPADC .............................................................................................................. 150

ADC Results ...................................................................................................... 151

RTC Calendar and Alarm .................................................................................. 153

A.3 Register Page 1 ................................................................................................................ 155

A.3.1

A.3.2

A.3.3

A.3.4

A.3.5

Power Sequencer .............................................................................................. 156

Regulator Settings ............................................................................................. 161

Backup Battery Charger .................................................................................... 196

High Power GPO PWM ..................................................................................... 197

GPADC Thresholds ........................................................................................... 199

A.4 Register Page 2 ................................................................................................................ 201

A.4.1

A.4.2

OTP.................................................................................................................... 201

Customer Trim and Configuration ..................................................................... 202

A.5 Register Page 3 ................................................................................................................ 216

Datasheet

DA9063_2v1

23-Mar-2017

CFR0011-120-00

6 of 219

DA9063

System PMIC for Mobile Application Processors

1

References

Dialog Semiconductor technical documentation is available on the support site:

www.dialog-semiconductor.com/support.

[1] AN-PM-068, Application Note, VBBAT Current in RTC or DELIVERY Modes, Dialog

Semiconductor.

[2] AN-PM-024, Application Note, DA9063 Voltage Monitoring, Dialog Semiconductor.

[3] AN-PM-010, Application Note, PCB Layout Guidelines, Dialog Semiconductor.

2

Block Diagram

CORE_SWG/GPIO3

BUCK RAIL

SWITCH

Controller

CORE_SWS/GPIO4

PERI_SWG/GPIO5

PERI_SWS/GPIO6

V_CP

VSYS/VBUCKx/VDDREF

VLDO1

LDO1(DVC)

0.6-1.86V

CP

1.0uF

2.2uF

1.0uF

2.2uF

DIG CTRL

47nF

VSYS/VBUCKx

VLDO2

VSYS

LDO2 (DVC)

0.6-1.86V

BUCK

CORE1

VBUCK_CORE1

DIG CTRL

1µH

2x22/47µF

Two-

Phase

DCDC

VSYS/VBUCKx

VLDO3

DA9063

LDO3 (DVC)

0.9-3.44V

VSYS

Z_T

BUCK

CORE2

VSYS/VBUCKx

VLDO4

1µH

2x22/47µF

Z_T

VBUCK_CORE2

LDO4 (DVC)

0.9-3.44V

VSYS/VBUCKx

VLDO5

VSYS

BUCK

PRO

LDO5

0.9-3.6V

VBUCK_PRO

1µH

2x47µF

VDDCORE

VSYS/VBUCKx

VLDO6

VSYS

LDO6 (LN)

0.9-3.6V

VOLTAGE

TEMP

BIASING

CIRCUIT

BUCK

PERI

SUPER-

VISION

DIG CTRL

SENSOR

VBUCK_PERI

1µH

2x22µF

VSYS/VBUCKx

VLDO7

LDO7

0.9-3.6V

2.2uF

DIG CTRL

VSYS

BUCK

MEM

VLDO8

LDO8 (VIB)

0.9–3.6V

DIG CTRL

OTP

MEMORY

INTERNAL

OSC

RTC

DIGITAL

VBUCK_MEM

1µH

2x22/47µF

2.2uF

Double

Current

DCDC

VSYS/VBUCKx

VLDO9

VSYS

LDO9 (LN)

0.95–3.6V

2.2uF

DIG CTRL

BUCK

IO

DIG CTRL

WATCH

DOG

TIMER

REF

VOLTAGE/

CURRENT

VBUCK_IO

1µH

2x22µF

RTC

32kHz OSC

VLDO10

LDO10 (LN)

0.9–3.6V

2.2uF

VDDCORE

ADCIN1/GPIO0

ADCIN2/GPIO1

ADCIN3/GPIO2

VSYS/VBUCKx

VLDO11

GENERAL PURPOSE

10BIT ADC

LDO11

0.9–3.6V

DIG CTRL

VDDCORE

DIG CTRL

2.2uF

DIG CTRL

nONKEY

SYS_EN/GPIO8

PWR_EN/GPIO9

VLNREF

2.2uF

POWER MANAGER

LDOCORE

2.5V

VDDCORE

2.2uF

DIG CTRL

PWR1_EN/GPIO10

nOFF

ON/OFF CONTROL

RESET GENERATION

OTP-PROGRAMMABLE

WAKE-UP AND

BACKUP

CHARGER

VBBAT

nSHUTDOWN

nRESET

470nF

SHUTDOWN

nIRQ

SEQUENCING CONTROL

SYSTEM MONITOR

INTERRUPT HANDLER

nVDD_FAULT/GPIO_12

GP_FB1/GPIO13

GP_FB2

OUT_32K

4-WIRE/2-WIRE

INTERFACE

HS 2-WIRE

INTERFACE

DIG CTRL

Multiplexed GPIO EXTENDER

GP_FB3

Pins-

Multiplexed

with GP-ADC/

CONTROL/

HS I2C

Figure 1: Block Diagram

Datasheet

DA9063_2v1

23-Mar-2017

CFR0011-120-00

7 of 219

DA9063

System PMIC for Mobile Application Processors

3

Regulator Overview

Table 1: Regulators

Regulator

Supplied Pins

Supplied Supplied

External

Notes

Voltage

(V)

Max.

Current

(mA)

Component

BUCKCORE1 VBUCKCORE1

0.3 to

1.57

1250/

2500

(full-current

mode)

1.0 µH/

44 µF /

88 µF

●

GPIO and host interface-

controlled DVC with

variable slew rate (10 mV

in [0.5, 1.0, 2.0, 4.0] µs)

●

10 mV steps

< 0.7 V PFM mode only

2500 mA in full-current

mode (double pass device

and current limit)

●

Provides dual-phase buck

with up to 5 A if combined

with BUCKCORE2

BUCKCORE2 VBUCKCORE2

0.3 to

1.57

1250/

2500

1.0 µH/

44/88 µF

GPIO and host interface-

controlled DVC with

(full-current

mode)

variable slew rate (10 mV

in [0.5/1.0/2.0/4.0] µs)

●

10 mV steps

< 0.7 V PFM mode only

2500 mA in full-current

mode (double pass device

and current limit)

●

Provides dual-phase Buck

if combined with

BUCKCORE1

BUCKPRO

VBUCKPRO

0.53 to

1.80

1250/

2500

1.0 µH/

44/88 µF

GPIO and host interface-

controlled DVC with

(full-current

mode)

variable slew rate, (10 mV

in [0.5/1.0/2.0/4.0] µs)

●

10 mV steps and VTT

regulator mode

●

< 0.7 V PFM mode only

2500 mA in full-current

mode (double pass device

and current limit)

BUCKMEM

VBUCKMEM

0.8 to

3.34

1500

1.0 µH/

44 µF

●

GPIO and host interface-

controlled DVC with

variable slew rate (10 mV

in [0.5/1.0/2.0/4.0] µs)

●

20 mV steps

Can be merged with

BUCK_IO towards single

buck with up to 3 A output

current

BUCKIO

VBUCKIO

0.8 to

3.34

1500

1.0 µH/

44 µF

●

GPIO and host interface-

controlled DVC with

variable slew rate (10 mV

in [0.5/1.0/2.0/4.0] µs)

20 mV steps, can be

merged with BUCK_MEM

Datasheet

DA9063_2v1

23-Mar-2017

CFR0011-120-00

8 of 219

DA9063

System PMIC for Mobile Application Processors

Regulator

Supplied Pins

Supplied Supplied

External

Notes

Voltage

(V)

Max.

Current

(mA)

Component

BUCKPERI

VBUCKPERI

0.8 to

3.34

1500

1.0 µH/

44 µF

●

GPIO and host interface-

controlled DVC with

variable slew rate (10 mV

in [0.5/1.0/2.0/4.0] µs)

●

20 mV steps

LDO1

VLDO1

0.6 to

1.86

100

1.0 µF

GPIO and host interface-

controlled DVC with

variable slew rate (10 mV

in [0.5/1.0/2.0/4.0] µs)

●

20 mV steps

Optional voltage tracking

of BUCKCORE or

BUCKPRO

LDO2

LDO3

VLDO2

VLDO3

0.6 to

1.86

200

2.2 µF

●

GPIO and host interface-

controlled DVC with

variable slew rate (10 mV

in [0.5/1.0/2.0/4.0] µs)

●

20 mV steps

Bypass mode

0.9 to

3.44

●

GPIO and host interface-

controlled DVC with

variable slew rate (10 mV

in [0.5/1.0/2.0/4.0] µs)

●

20 mV steps

Bypass mode

LDO4

VLDO4

0.9 to

3.44

200

2.2 µF

●

GPIO and host interface-

controlled DVC with

variable slew rate (10 mV

in [0.5/1.0/2.0/4.0] µs)

●

20 mV steps

LDO5

LDO6

VLDO5

VLDO6

0.9 to 3.6 100

0.9 to 3.6 200

1.0 µF

2.2 µF

50 mV steps

●

Low noise

50 mV steps

LDO7

VLDO7

0.9 to 3.6 200

2.2 µF

●

Bypass mode

50 mV steps

Common supply with

LDO8

VLDO8

0.9 to 3.6 200

2.2 µF

●

Bypass and switching

vibration motor driver

mode

●

50 mV steps

Common supply with

LDO7

LDO9

VLDO9

0.95 to

3.6

200

2.2 µF

●

Low noise

50 mV steps

OTP trimmed

Common supply with

LDO10

Datasheet

DA9063_2v1

23-Mar-2017

CFR0011-120-00

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DA9063

System PMIC for Mobile Application Processors

Regulator

Supplied Pins

Supplied Supplied

External

Notes

Voltage

(V)

Max.

Current

(mA)

Component

LDO10

VLDO10

0.9 to 3.6 300

2.2 µF

●

Low noise LDO

50 mV steps

Common supply with

LDO9

LDO11

VLDO11

VBBAT

0.9 to 3.6 300

2.2 µF

470 nF

●

Bypass mode

50 mV steps

BACKUP

1.1 to 3.1

6

4

●

100/200 mV steps

Configurable charge

current between 100 µA

and 6000 µA

●

Reverse current protection

(RCP)

LDOCORE

Internal PMIC

supply

2.5 ± 2 %

accuracy

2.2 µF

●

Internal LDO

OTP trimmed

Datasheet

DA9063_2v1

23-Mar-2017

CFR0011-120-00

10 of 219

DA9063

System PMIC for Mobile Application Processors

4

Package Information

4.1 Package Outlines

Figure 2: Package Outline Drawing 100 VFBGA 0.3 mm Ball Diameter

Datasheet

DA9063_2v1

23-Mar-2017

CFR0011-120-00

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DA9063

System PMIC for Mobile Application Processors

Figure 3: Package Outline Drawing 100 TFBGA 0.45 mm Ball Diameter

Datasheet

DA9063_2v1

23-Mar-2017

CFR0011-120-00

12 of 219

DA9063

System PMIC for Mobile Application Processors

4.2 Pinout

1

2

3

4

5

6

7

8

9

10

nVDD_FAULT

_

GPIO12

DATA_

GPIO14

CLK_

GPIO15

XTAL_OUT

VREF

VSYS

SO

SI

VDDCORE

OUT32K

A

B

C

D

E

F

A

B

C

D

E

F

DA9063 (8x8)

see balls through package

VTTR_

CMP1V2

SYS_EN_

GPIO8

PWR1_EN_

GPIO10

XTAL_IN

VLDO11

VLDO10

VLDO9

VLDO8

VLDO6

VLDO5

VLDO4

VLNREF

nCS

SK

CHG_WAKE

nIRQ

nSHUTDOWN

BGA100 (87 + 13 VSS)

Very High Power

Signals

VHPWR

up to 1A/ball,

maximize routing width

High Power Signals

ADCIN2_

GPIO1

ADCIN3_

GPIO2

ADCIN1_

GPIO0

PWR_EN_

GPIO9

HIPWR

IREF

VDD_IO2

VDD_IO1

GP_FB2

V_CP

up to 1A, use wide

routing

Power Signals

MPWR

up to 500mA

VDDQ_

E_GPI2

PERI_SWS_

GPIO6

SWBUCKPRO

_B

Noisy Digital Signals

not sensitive to noise

VDD_LDO11

GPIO_7

TP

VSS_QUIET

VSS_NOISY

VSS_QUIET

VSS_NOISY

nRESET

NOISY

Quasi Static Digital

NORM

Signals

not sensitive to noise

VDD_

LDO7_8

VDD_

LDO9_10

GP_FB1_

GPIO13

SWBUCKPRO

_A

Sensitive Analog

SENS

VSS_QUIET

VDD_LDO4

VSS_NOISY

GPIO11

Signals

Potentially not used

(improved heat sink

VSS plane when vias

removed)

XXX

SW

BUCKCORE2_

A

VDD_

BUCKPRO

VDD_

BUCKPRO

VLDO7

VDD_LDO6

VDD_LDO3

VDD_LDO1

VBUCKMEM

Via

Noisy High Power

Ground,

VSS_NOISY

maximize routing

width

SW

BUCKCORE2_

B

VDD_

BUCKCORE2

VDD_

BUCKCORE2

Quiet Ground,

VSS_QUIET

VDD_LDO5

VDD_LDO2

VBUCKPERI

G

H

J

G

H

J

use wide routing

PCB routing

SW

BUCKCORE1_

A

VDD_

BUCKPERI

VDD_

BUCKMEM

VDD_

BUCKIO

VDD_

BUCKCORE1

VDD_

BUCKCORE1

GP_FB3

SW

BUCKCORE1_

B

PERI_SWG_

GPIO5

CORE_SWG_

GPIO3

CORE_SWS_

GPIO4

nOFF

nONKEY

VBBAT

SWBUCKME

M

VBUCKCORE

1

VBUCKCORE

2

VLDO3

1

VLDO2

2

VLDO1

3

VBUCKIO

4

SWBUCKPERI

SWBUCKIO

VBUCKPRO

10

K

5

6

7

8

9

Figure 4: Connection Diagram

Table 2: Pin Type Definition

Pin Type

DI

Description

Pin Type

AI

Description

Analog input

Analog output

Digital input

DO

Digital output

Digital input/output

Power supply

AO

DIO

AIO

Analog input/output

Ground connection

PWR

GND

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Table 3: Pin Description

Pin name

Alternate

Function

Type

(Table 2)

Description

Power Manager

A9

nVDD_FAULT

GPIO12

DO/DIO

DI/PWR

Indication for low supply voltage / GPIO12 /

VDD_MON controlled GPO

B6

CHG_WAKE

Wakeup signal from companion charger to

trigger a start-up and temporary supply voltage

for PMIC (VBUS_PROT in case of an inserted

supply until charger Buck provides power to

V_SYS).

Connect to GND if not used.

B7

B8

nIRQ

DO

DI

IRQ line for host

nSHUTDOWN

Active-low input from switch or host to initiate

shutdown

B9

SYS_EN

GPIO8

DI/DIO

Hardware enable of power domain

SYSTEM/GPIO8

B10

PWR1_EN

GPIO10

Hardware enable of power domain

POWER1/GPIO10 with high power output / input

for power sequencer WAIT ID

C3

C4

C8

VDD_IO2

VDD_IO1

GP_FB2

PWR

DO/DI

Alternate supply I/O voltage

First supply I/O voltage rail

PWR_OK status indicator: all supervised

regulators are in-range / HW input for watchdog

supervision / dual-phase BUCKCORE voltage

sense at output capacitor

C9

PWR_EN

GPIO9

DI/DIO

Hardware enable of power domain power /

sequencer controlled GPO

D3

D5

GPIO7

TP

DIO

Sequencer controlled GPO

Test pin: enables power commander boot mode

and supply pin for OTP fusing voltage

D9

E8

nRESET

GP_FB1

DO

Active low reset for host

GPIO13

DO/DIO

Status indication for host of a valid wakeup

event (EXT_WAKEUP) / indicator for on-going

power mode transition (READY) / GPIO13,

regulator HW control

E9

H9

GPIO11

GP_FB3

DIO

GPIO11 with high power output and blinking

feature

DO/DO

Second 32K oscillator output: OUT32_2 /

VIB_BREAK control signal for vibration motor

driver (LDO8)

J4

J7

nOFF

DI

Active-low input from error indication line to

initiate fast emergency shutdown

nONKEY

On/off key with optional long press shutdown

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Pin name

Alternate

Function

Type

(Table 2)

Description

4-Wire/2-Wire Interfaces

A4

A5

A7

SO

DO

DIO

4-wire data output

SI

4-wire data input / 2-wire data

DATA

GPIO14

GPIO15

HS-2-WIRE data / GPIO14 (optional reset if long

press in parallel with GPI15) with high power

output and blinking feature

A8

CLK

DI

HS-2-WIRE clock / GPIO15 (optional reset if

long press in parallel with GPI14) with high

power output and blinking feature

B3

B4

nCS

SK

DI

4-wire (active low) chip select

4-wire/2-wire clock

Voltage Regulators

A3

A6

V_SYS

PWR

AO

Supply voltage for PMIC and input for voltage

supervision

(decouple with 1.0 µF)

VDDCORE

Regulated supply for internal circuitry

(2.2 V/2.5 V)

(decouple with 2.2 µF)

C1

D1

D2

E1

E2

E3

F1

F2

F3

G1

G2

G3

G4

H1

H2

H3

J1

VLDO11

AO

Output voltage from LDO11

Output voltage from LDO10

Supply voltage for LDO11

Output voltage from LDO9

Supply voltage for LDO7 and LDO8

Supply voltage for LDO9 and LDO10

Output voltage from LDO8

Output voltage from LDO7

Supply voltage for LDO6

Output voltage from LDO6

Supply voltage for LDO5

Supply voltage for LDO3

Supply voltage for LDO4

Output voltage from LDO5

Supply voltage for LDO2

Supply voltage for LDO1

Output voltage from LDO4

Output voltage from LDO3

Output voltage from LDO2

Output voltage from LDO1

VLDO10

VDD_LDO11

VLDO9

PWR

AO

VDD_LDO7_8

VDD_LDO9_10

VLDO8

PWR

AO

VLDO7

AO

VDD_LDO6

VLDO6

PWR

AO

VDD_LDO5

VDD_LDO3

VDD_LDO4

VLDO5

PWR

AO

VDD_LDO2

VDD_LDO1

VLDO4

PWR

AO

K1

K2

K3

VLDO3

AO

VLDO2

AO

VLDO1

AO

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System PMIC for Mobile Application Processors

Pin name

Alternate

Function

Type

(Table 2)

Description

DC/DC Buck Converters

A1

A2

XTAL_OUT

VREF

AIO

32 kHz crystal connection

(adjust with 10 pF)

Filter node for internal reference voltage

(decouple with 2.2 µF)

A10

B1

OUT_32K

XTAL_IN

DO

32 kHz oscillator buffer

AIO

32 kHz crystal connection

(adjust with 10 pF)

B2

B5

C2

C5

C6

C7

VLNREF

VTTR

Filter node for LN (low noise)

(decouple with 2.2 µF)

CMP1V2

AO/DO

AO

Memory bus termination reference voltage

(50 % of VDDQ), COMP1V2 controlled GPO

IREF

Connection for bias setting

(configure with high precision 200 kΩ resistor)

ADCIN2

ADCIN3

ADCIN1

GPIO1

GPIO2

GPIO0

AI/DIO

Connection to GPADC channel 2 with 1.2 V HW

comparator IRQ/GPIO1, regulator HW control

Connection to GPADC channel 3/GPIO2,

regulator HW control

Connection to GPADC auto channel 1 with

threshold IRQ and resistor measurement

option/GPIO0

C10

D4

V_CP

AIO

Charge pump output bypass

(decouple with 10 nF)

VDDQ

E_GPI2

GPIO6

AI/DO

BUCKPRO target voltage sense port / state of

E_GPI2 controlled GPO

D8

PERI_SWS

BUCKPERI sense node from rail switch output/

GPIO6

Pulled down when switch is open

D10

E10

SWBUCKPRO_B

SWBUCKPRO_A

AO

Switching node for BUCKPRO (full-current)

Switching node for BUCKPRO (half-current)

F8, F9 VDD_BUCKPRO

PWR

Supply voltage for buck

To be connected to V_SYS

F10

SWBUCKCORE2_A

AO

Switching node for BUCKCORE2 (half-current)

G8, G9 VDD_BUCKCORE2

PWR

Supply voltage for buck

To be connected to V_SYS

G10

H4

SWBUCKCORE2_B

VDD_BUCKPERI

AO

Switching node for BUCKCORE2 (full-current)

PWR

Supply voltage for buck

To be connected to V_SYS

H5

H6

VDD_BUCKMEM

VDD_BUCKIO

PWR

AO

Supply voltage for buck

To be connected to V_SYS

Supply voltage for buck

To be connected to V_SYS

H7, H8 VDD_BUCKCORE1

Supply voltage for buck

To be connected to V_SYS

H10

SWBUCKCORE1_A

Switching node for BUCKCORE1 (half-current)

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Pin name

Alternate

Function

Type

(Table 2)

Description

J2

J3

J5

J6

J8

VBUCKPERI

AI

Sense node for BUCKPERI

VBUCKMEM

PERI_SWG

CORE_SWG

CORE_SWS

Sense node for DC/DC BUCKMEM

GPIO5

AIO/DIO NMOS gate driver for buck rail switch/GPIO5

AIO/DIO NMOS gate driver for buck rail switch/GPIO3

GPIO3

GPIO4

AI/DO

BUCKCORE sense node from rail switch output

or output capacitor of dual-phase BUCKCORE/

connection of internal switch to the output of

LDO1/GPIO4

Pulled down when switch is open

Switching node for BUCKCORE1 (full-current)

Sense node for BUCKIO

J10

K4

K5

K6

K7

SWBUCKCORE1_B

VBUCKIO

AO

AI

SWBUCKPERI

SWBUCKMEM

SWBUCKIO

AO

Switching node for BUCKPERI

Switching node for BUCKMEM

Switching node for BUCKIO

To be connected to SWBUCKMEM for buck

merge

K8

K9

VBUCKCORE1

VBUCKCORE2

VBUCKPRO

AI

Sense node for BUCKCORE1

Sense node for BUCKCORE2

Sense node for BUCKPRO

K10

Backup Battery Charger

J9

VBBAT

AIO

Backup battery connection

Coin-cell or super-cap (decouple with 470 nF)

Vss

D6-7,

E4, F4

GND

VSS_LDO, VSS_ADC, VSS_CORE, VSUB

E5-7,

F5-7,

G5-7

VSS_BUCKCORE1_A, VSS_BUCKCORE1_B,

VSS_BUCKCORE2_A, VSS_BUCKCORE2_B,

VSS_BUCK_PRO_A, VSS_BUCK_PRO_B,

VSS_BUCK_IO, VSS_BUCK_MEM,

VSS_BUCK_PERI

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5

Electrical Characteristics

5.1 Absolute Maximum Ratings

Stresses beyond those listed under Absolute maximum ratings may cause permanent damage to the

device. These are stress ratings only, so functional operation of the device at these or any other

conditions beyond those indicated in the operational sections of the specification are not implied.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Table 4: Absolute Maximum Ratings

Parameter

Symbol/Pin

Conditions

Min

-65

-40

Typ

Max

+150

Unit

°C

Storage temperature

Junction temperature

T_STG

T_J

Note 1

°C

VSYS,

CHG_WAKE

-0.3

5.5

V

Supply voltage

All other

pins

Note 2

V_DDREF+ 0.3

ESD protection -

Human Body Model

(HBM)

V_{ESD_HBM}

2000

V

ESD protection -

Charged Device Model

(CDM)

V_{ESD_CDM}

Corner pins

All other pins

750

500

Note 1 See Section 5.16 and Section 6.17.

Note 2 Maximum V_DDREF= 5.5 V. An internal node V_DDREFis defined as the higher rail of CHG_WAKE and

VSYS.

5.2 Recommended Operating Conditions

All voltages are referenced to VSS unless otherwise stated. Currents flowing into DA9063 are

deemed positive; currents flowing out are deemed negative. All parameters are valid over the

recommended temperature range and power supply range unless otherwise stated. Please note that

the power dissipation must be limited to avoid overheating of DA9063.

Table 5: Recommended Operating Conditions

Parameter

Symbol/Pin

Conditions

Min

Typ

Max

Unit

Junction temperature

T_J

-40

+125

°C

Supply voltage

VSYS,

CHG_WAKE

0

5.5

3.6

V

Supply voltage IO

V_{DD_IO1/2}

Note 1

1.2

Thermal resistance

junction to ambient

100 VFBGA package

Note 2

27.7

26.1

°C/W

_JA

100 TFBGA package

Note 2

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Parameter

Symbol/Pin

Conditions

100 VFBGA

Min

Typ

Max

Unit

Maximum power

dissipation, see Section

5.2.1

P_D

2000

mW

Derating factor above

T_A= 70 °C:

36.1 mW/°C (1/θ_JA)

100 TFBGA

2100

mW

Derating factor above

T_A= 70 °C:

38.3 mW/°C (1/θ_JA)

Note 1 V_DDIO1/2must not exceed V_DDREF

.

Note 2 Obtained from package thermal simulations, JEDEC 2S2P four layer board (76.2 mm x 114 mm x

1.6 mm), 70 μm (2 oz) copper thickness power planes, 35 μm (1 oz) copper thickness signal layer

traces, natural convection (still air), see Section 4.14.1.

5.2.1

Power Derating Curves

Figure 5: 100 VFBGA Power Derating Curve

Table 6: Typical Temperatures

T_A= 70 °C

P_D= 1.99 W

P_D= 2.53 W

T_A= 85 °C

P_D= 1.44 W

P_D= 1.99 W

T_A= 105 °C

P_D= 0.72 W

P_D= 1.26 W

T_{J_WARN}

T_{J_CRIT}

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Figure 6:100 TFBGA Power Derating Curve

Table 7: Typical Temperatures

T_A= 70 °C

P_D= 2.11 W

P_D= 2.68 W

T_A= 85 °C

P_D= 1.53 W

P_D= 2.11 W

T_A= 105 °C

P_D= 0.77 W

P_D= 1.34 W

T_{J_WARN}

T_{J_CRIT}

5.3 Typical Current Consumption

Table 8: Typical Current Consumption

Operating Mode

Conditions (Note 1)

Backup

Device

Battery

Unit

NO-POWER mode (POR)

2.4 V > V_DDREF> VBBAT > 1.5 V

0

16

µA

0.4

Note 3

VBBAT > V_DDREF> 1.5 V

V_DDREF> VBBAT > 1.5 V

VBBAT > V_DDREF> 2.0 V

V_DDREF> VBBAT > 2.0 V

0.5

0

DELIVERY mode Note 2

RTC mode Note 2

µA

1.5

1.06

Note 3

1.4

0.05

7

V_DDREF> 2.2 V, supplies off (except

LDOCORE), RTC on, pulsed mode:

RESET mode

µA

VBBAT > V_DDREF

VBBAT < V_DDREF

1.6

11

18

0.05

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Operating Mode

Conditions (Note 1)

Backup

Device

Battery

Unit

VSYS > VDD_FAULT_LOWER,

supplies off (except LDOCORE), all

blocks in POWERDOWN mode,

RTC on, pulsed mode with limited

parametric compliance

LOW-POWER mode

18

µA

VSYS > VDD_FAULT_LOWER,

supplies off (except LDOCORE), all

blocks in POWERDOWN mode,

RTC on

POWERDOWN mode

(Hibernate)

40

µA

BUCKCORE, LDOCORE, LDO2, 4,

5 enabled, RTC and GPIO unit on

65

Note 4

POWERDOWN mode (Standby)

ACTIVE mode

µA

All supplies, GPIO, RTC and

GPADC on

320

Note 1 nONKEY/CHG_WAKE/V_DDREFdetection circuit is enabled in all modes.

Note 2 See VBBAT current in RTC or DELIVERY modes [1]

Note 3 0 µA if no main battery available.

Note 4 Regulators are running in sleep mode.

5.4 Digital I/O Characteristics

Table 9: Digital I/O Electrical Characteristics, T_J= -40 ºC to +125 ºC

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

GPI0 to GPI15, nOFF,

nSHUTDOWN

VDDCORE mode

1.0

V_SYS

SYS_EN, PWR_EN,

PWR1_EN

Input High Voltage

VIH

V

VDD_IO2 mode

0.7*VDD_IO2

-0.3

V_SYS

0.4

GPI0 to GPI15, nOFF,

nSHUTDOWN

VDDCORE mode

SYS_EN, PWR_EN,

PWR1_EN

Input Low Voltage

VIL

V

VDD_IO2 mode

RTC mode

-0.3

1.0

0.3*VDD_IO2

nONKEY, CHG_WAKE

Input High Voltage

VIH

VIL

V_SYS

0.4

V

nONKEY, CHG_WAKE

Input Low Voltage

RTC mode

-0.3

1.0

CLK, DATA, SK, SI

(2-WIRE mode)

VDDCORE mode

VDD_IO2 mode

VDDCORE mode

VDD_IO2 mode

VIH

VIL

VIH

VIL

V

0.7*VDD_IO2

Input High Voltage

CLK, DATA, SK, SI

(2-WIRE mode)

0.4

0.3*VDD_IO2

Input Low Voltage

SK, nCS, SI

(4-WIRE mode)

Input High Voltage

0.7*VDD_IOx

SK, nCS, SI

(4-WIRE mode)

Input Low Voltage

0.3*VDD_IOx

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System PMIC for Mobile Application Processors

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

GPO0 to GPO15,

nVDD_FAULT, SO,

nRESET, nIRQ, ,

E_GPI_2, COMP1V2,

OUT_32K, OUT_32K_2

VDD_IO1 mode

0.8*VDD_IO1

VOH = 1 mA

V

VDD_IOx ≥

1.5 V

VDD_IO2 mode

Open drain

0.8*VDD_IO2

Output High Voltage

GPO1, 3 to 6, 10, and 12

to 15, DATA, SI (2-WIRE

mode) SO, nRESET,

nIRQ, PWR_OK (open

drain mode)

VOH

V_DDREF

V

Output High Voltage

GPO0 to GPO15, SO,

nVDD_FAULT, nRESET

(Note 1), nIRQ (Note 1),

PWR_OK, E_GPI_2,

COMP1V2, OUT_32K,

OUT_32K_2,

VOL = 1 mA

VOL = 3 mA

0.3

V

Output Low Voltage

DATA, SI (2-WIRE

mode)

0.24

Output Low Voltage

SI (2-WIRE mode)

Output Low Voltage

VOL = 20 mA

C_IN

0.4

10

V

CLK, DATA, SK, SI

Input Capacitance

pF

Fast

20 + 0.1 Cb

120

40

Cb < 550 pF

SI (2-WIRE MODE)

Data Fall Time

HS

t_fDA

10

20

ns

10 < Cb < 100 pF

HS

80

Cb < 400 pF

Sink current capability

GPO 10, 11, 14, 15

V_GPIO= 0.5 V

Note 2

11

-4

mA

V_GPIO

=

Source current capability

GPO 10, 11,14,15

0.8*VDD_IO1/2

Note 2

Sink current capability

GPO 0 to 9, 12, 13

V_GPIO= 0.3 V

1

V_GPIO

0.8*VDD_IO1/2

=

Source current capability

GPO 0 to 9, 12, 13

-1

mA

Note 3

GPI pull-down resistor

50

100

250

kΩ

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Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

VDD_IO1/2 =

1.5 V

60

180

310

GPO pull-up resistor

Note 4

VDD_IO1/2 =

1.8 V

45

20

120

40

190

60

kΩ

VDD_IO1/2 =

3.3 V

Note 1 Electrical characteristics are guaranteed down to V_DDREF= 2.0 V (VPOR_LOWER). For lower voltages

the port continues operating with reduced performance.

Note 2 At low V_DDREFvalues and high temperatures, the sink current capability is reduced.

Note 3 For VDD_IO1/2 < 1.5 V the source current capability is reduced.

Note 4 V(PAD) = 0 V.

5.5 Watchdog

Table 10: Watchdog, T_J= -40 ºC to +125 ºC

Parameter

Symbol

T_WDMIN

T_WDMAX

Test Conditions

Min

0.18

1.44

Typ

Max

0.33

2.64

Unit

Minimum Watchdog time

Maximum Watchdog time

0.256

2.048

s

5.6 Power Manager and HS-2-Wire Control Bus

CLKL

CLKH

CLK/SK

STH

DST

TSS

DHT

DATA/SI

Figure 7: 2-Wire Bus Timing

Table 11: Power Manager and HS-2-Wire Control Bus Electrical Characteristics, T_J= -40 ºC to

+125 ºC

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

µs

Bus free time STOP to START

Bus line capacitive load

Standard/Fast/Fast+ Mode

CLK clock frequency

0.5

Cb

150

pF

Note 1

0

1000

kHz

µs

Bus free time STOP to START

Start condition set-up time

Start condition hold time

CLK low time

0.5

0.26

0.5

µs

STH

µs

CLKL

µs

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Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

µs

CLK high time

CLKH

0.26

2-WIRE CLK and DATA rise

time

(input requirement)

1000

300

ns

2-WIRE CLK and DATA fall

time

ns

Data set-up time

DST

DHT

50

0

ns

µs

Data hold-time

Data valid time

0.45

Data valid time acknowledge

Stop condition set-up time

High Speed Mode

CLK clock frequency

TSS

0.26

0

Requires VDDIO ≥ 1.8 V

3400

kHz

Note 1

Start condition set-up time

Start condition hold time

CLK low time

160

60

ns

STH

CLKL

CLKH

CLK high time

2-WIRE CLKH and SDAH

rise/fall time

Input requirement

160

Data set-up time

DST

DHT

TSS

10

0

ns

Data hold-time

Stop condition set-up time

160

Note 1 Minimum clock frequency is 10 kHz if 2WIRE_TO is enabled

5.7 4-Wire Control Bus

nCS

4

2

11

1

3

5

SK

SI

7

6

10

A4

R/W

LSB

A6

A5

BIT 1

8

9

SO

LSB

BIT 7

R/W

Address

DATA

Figure 8: 4-Wire Bus Timing

Note 1 The above timing is valid for active-low and high CS

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System PMIC for Mobile Application Processors

Table 12: 4-Wire Control Bus, T_J= -40 ºC to +125 ºC

Parameter

Symbol Label in Plot

Min

Typ

Max

Unit

pF

Bus line capacitive load

Cycle time

100

t_C

1

70

20

ns

Enable lead time

t_CSS

2, from nCS active to first SK

edge

ns

Enable lag time

Clock low time

t_SCS

t_CL

3, from last SK edge to nCS idle

20

0.4 * t_C

5

ns

4

Clock high time

Data-in setup time

Data-in hold time

Data-out valid time

Data-out hold time

CS inactive time

t_CH

5

t_SIS

6

t_SIH

t_SOV

t_SOH

t_WCS

7

5

8

22

9

6

11

20

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23-Mar-2017

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DA9063

System PMIC for Mobile Application Processors

5.8 LDO Voltage Regulators

5.8.1

LDO1

Table 13: LDO1, T_J= -40 ºC to +125 ºC

Parameter

Symbol

Test Conditions

Min

Typ

Max

5.5

Unit

V

V_DD= V_SYS

2.8

Input voltage

Output voltage

V_DD

1.5

Note 1

If supplied from buck

V_LDO

0.6

Note 2

1.86

V

V_DD= V_SYS= 2.8 V to 5.5 V

I_OUT= 100 mA

Output accuracy

-3

+3

%

Including static line/load

regulation

f > 1 MHz

Output capacitor ESR

R_{COUT_ESR}

0

300

mΩ

Including wiring parasitics

Output current

I_{OUT_max}

I_SHORT

V_DD= V_SYS= 2.8 V to 5.5 V

100

mA

Short circuit current

200

100

Maximum forced sleep

mode current

I_SLEEP

V_DD≥ 1.8 V

10

mA

mV

V_DD= V_SYS> 2.8 V

Dropout voltage

V_DROPOUT

150

I_OUT= 100 mA

(V_DD= 1.5 V, I_OUT= I_MAX/3)

V_DD= V_SYS= 3.0 V to 5.5 V

I_OUT= 100 mA

Static line regulation

Static load regulation

V_{S_LINE}

1

5

mV

V_{S_LOAD}

I_OUT= 1 mA to 100 mA

10

V_DD= V_SYS= 3.0 V to 3.6 V

I_OUT= 100 mA

tr = tf = 10 µs

Line transient response V_{TR_LINE}

5

10

50

mV

dB

V_DD= 3.6 V

I_OUT= 1 mA to 100 mA

tr = tf = 1 µs

Load transient

V_{TR_LOAD}

30

50

response

f = 10 Hz to 10 kHz , RT

V_DD= 3.6 V, I_OUT= I_MAX/2

V_DD– V_LDO≥ 0.6 V

PSRR

Note 3

40

Output noise

N

μV

rms

V_DD= V_SYS= 3.6 V,

V_LDO= 1.8 V

I_OUT= 5 mA to I_MAX

f = 10 Hz to 100 kHz , RT

70

Quiescent current in

ON mode

9 + 0.7 %

of I_OUT

I_{Q_ON}

Note 4

μA

1.5 +

1.4% of

I_OUT

Quiescent current

forced sleep mode

I_{Q_SLEEP}

Quiescent current OFF

mode

I_{Q_OFF}

1

μA

μs

10 % to 90 %

SLEEP mode

300

390

Turn-on time

t_ON

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23-Mar-2017

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DA9063

System PMIC for Mobile Application Processors

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

90 % to 10%

Turn off time

t_OFF

1

ms

Pull-down resistor enabled

Pull-down resistance in

OFF mode

Can be disabled via

LDO1_PD_DIS

R_OFF

100

Ω

Note 1 Max output current is 30 % when the input voltage is 1.5 V

Note 2 Programmable in 20 mV voltage steps, maximum output voltage is determined by V_DD- dropout

voltage

Note 3 Measured at point of load

Note 4 Internal regulator current flowing to ground

5.8.2

LDO2

Table 14: LDO2, T_J= -40 ºC to +125 ºC

Parameter

Symbol

Test conditions

Min

Typ

Max

5.5

Unit

V

V_DD= V_SYS

2.8

Input voltage

Output voltage

V_DD

1.5

Note 1

If supplied from buck

V_LDO

0.6

Note 2

1.86

V

V_DD= V_SYS= 2.8 V to 5.5 V

I_OUT= 200 mA

Output accuracy

-3

+3

%

Including static line/load

regulation

Including voltage and

temperature coefficient at

configured VLDO2

Stabilisation

capacitor

C_OUT

-55 %

2.2

+35 %

300

µF

Output capacitor

ESR

f > 1 MHz

including wiring parasitics

R_{COUT_ESR}

I_{OUT_max}

0

mΩ

Output current

V_DD= V_SYS= 2.8 V to 5.5 V

200

mA

Short circuit current I_SHORT

400

Maximum forced

I_SLEEP

V_DD≥ 1.8 V

20

mA

mV

sleep mode current

V_DD= V_SYS> 2.8 V

Dropout voltage

V_DROPOUT

100

1

150

5

I_OUT= 200 mA

(V_DD= 1.5 V, I_OUT= I_MAX/3)

Static line

regulation

V_DD= V_SYS= 3.0 V to 5.5 V

I_OUT= 200 mA

V_{S_LINE}

mV

5

10

Static load

regulation

V_{S_LOAD}

I_OUT= 1 mA to 200 mA

V_DD= V_SYS= 3.0 V to 3.6 V

I_OUT= 100 mA

tr = tf = 10 µs

Line transient

response

V_{TR_LINE}

10

50

mV

V_DD= 3.6 V

I_OUT= 1 mA to 200 mA

tr = tf = 1 µs

Load transient

response

V_{TR_LOAD}

30

50

mV

dB

f = 10 Hz to 10 kHz , RT

V_DD= 3.6 V, I_OUT= I_MAX/2

V_DD– V_LDO≥ 0.6 V

PSRR

Note 3

PSRR

40

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23-Mar-2017

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DA9063

System PMIC for Mobile Application Processors

Parameter

Symbol

Test conditions

Min

Typ

Max

Unit

Output noise

N

μV

rms

V_DD= V_SYS= 3.6 V

V_LDO= 1.8 V

I_OUT= 5 mA to I_MAX

f = 10 Hz to 100 kHz , RT

70

Quiescent current

in ON mode

9 + 0.4%

of I_OUT

I_{Q_ON}

Note 4

μA

1.5 +

0.9% of

I_OUT

Quiescent current

forced sleep mode

I_{Q_SLEEP}

Quiescent current

OFF mode

I_{Q_OFF}

1

μA

μs

10 to 90%

150

195

Turn-on time

Turn off time

t_ON

SLEEP mode

90 to 10%, pull-down resistor

enabled

t_OFF

1

ms

Pull-down

resistance in OFF

mode

Can be disabled via

LDO2_PD_DIS

R_OFF

100

Ω

Note 1 Max output current is 30% when the input voltage is 1.5 V

Note 2 Programmable in 20 mV voltage steps, maximum output voltage is determined by V_DD- dropout

voltage

Note 3 Measured at point of load

Note 4 Internal regulator current flowing to ground

5.8.3

LDO3

Table 15: LDO3, T_J= -40 ºC to +125 ºC

Parameter

Symbol

Test Conditions

Min

Typ

Max

5.5

Unit

V_DD= V_SYS

2.8

Input voltage

Output voltage

V_DD

V

(1.5)

Note 1

If supplied from buck

V_LDO

0.9

Note 2

3.44

V_DD= V_SYS= 2.8V to 5.5 V

I_OUT= 200 mA

Output accuracy

-3

+3

%

Including static line/load

regulation

Including voltage and

temperature coefficient at

configured VLDO3

Stabilisation

capacitor

C_OUT

-55%

2.2

+35%

300

µF

Output capacitor

ESR

f > 1 MHz including wiring

parasitics

R_{COUT_ESR}

I_{OUT_max}

0

mΩ

Output current

V_DD= V_SYS= 2.8 V to 5.5 V

200

mA

Short circuit current I_SHORT

400

100

Maximum forced

I_SLEEP

V_DD≥ 1.8 V

20

mA

mV

sleep mode current

V_DD= V_SYS> 2.8 V

Dropout voltage

V_DROPOUT

150

I_OUT= 100 mA

(V_DD= 1.5 V, I_OUT= I_MAX/3)

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23-Mar-2017

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DA9063

System PMIC for Mobile Application Processors

Parameter

Symbol

Test Conditions

Min

Typ

1

Max

5

Unit

Static line

regulation

V_DD= V_SYS= 3.0 V to 5.5 V

I_OUT= 200 mA

V_{S_LINE}

mV

5

10

Static load

regulation

V_{S_LOAD}

I_OUT= 1 mA to 200 mA

mV

V_DD= V_SYS= 3.0 V to 3.6 V

I_OUT= 100 mA

tr = tf = 10 µs

Line transient

response

V_{TR_LINE}

5

10

50

V_DD= 3.6 V

I_OUT= 1 mA to 200 mA

tr = tf = 1 µs

Load transient

response

V_{TR_LOAD}

30

mV

dB

f = 10 Hz to 10 kHz , RT

V_DD= 3.6 V, I_OUT= I_MAX/2

V_DD– V_LDO≥ 0.6 V

PSRR

Note 3

PSRR

40

50

70

Output noise

N

μV

rms

V_DD= V_SYS= 3.6 V,

V_LDO= 2.8 V

I_OUT= 5 mA to I_MAX

f = 10 Hz to 100 kHz , RT

9 +

0.45% of

I_OUT

Quiescent current

in ON mode

I_{Q_ON}

Note 4

μA

1.5 +

1.0% of

I_OUT

Quiescent current

forced sleep mode

I_{Q_SLEEP}

μA

Quiescent current

OFF mode

I_{Q_OFF}

1

300

10 to 90%

Turn-on time

Turn off time

t_ON

μs

SLEEP mode

390

1

90 % to 10 %

t_OFF

ms

Pull-down resistor enabled

Pull-down

resistance in OFF

mode

Can be disabled via

LDO3_PD_DIS

R_OFF

100

0.5

Ω

Bypass mode

V_DD> 2.2 V

0.7

1.0

Bypass on-

resistance

R_ON

Ω

V_DD> 1.8 V

Current limit in

Bypass mode

I_LIM

300

600

100

mA

Quiescent current

in Bypass mode

I_{Q_BYPASS}

50

μA

Note 1 Max output current is 30% when the input voltage is 1.5 V

Note 2 Programmable in 20 mV voltage steps, maximum output voltage is determined by V_DD- dropout

voltage

Note 3 Measured at point of load

Note 4 Internal regulator current flowing to ground

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DA9063

System PMIC for Mobile Application Processors

5.8.4

LDO4

Table 16: LDO4, T_J= -40 ºC to +125 ºC

Parameter

Symbol

Test Conditions

Min

Typ

Max

5.5

Unit

V

V_DD= V_SYS

2.8

Input voltage

Output voltage

V_DD

1.5

If supplied from buck

Note 1

V_LDO

0.9

-3

Note 2

3.44

V

V_DD= V_SYS= 2.8 V to 5.5 V

I_OUT= 200 mA

Output accuracy

+3

%

Including static line/load

regulation

Including voltage and

temperature coefficient at

configured VLDO4

Stabilisation

capacitor

C_OUT

-55 %

2.2

+35 %

300

µF

Output capacitor

ESR

f > 1 MHz

Including wiring parasitics

R_{COUT_ESR}

I_{OUT_max}

0

mΩ

Output current

V_DD= V_SYS= 2.8 V to 5.5 V

200

mA

Short circuit current I_SHORT

400

Maximum forced

I_SLEEP

V_DD≥ 1.8 V

30

mA

mV

sleep mode current

V_DD= V_SYS> 2.8 V

Dropout voltage

V_DROPOUT

100

1

150

5

I_OUT= 200 mA

(V_DD= 1.5 V, I_OUT= I_MAX/3)

Static line

regulation

V_DD= V_SYS= 3.0 V to 5.5 V

I_OUT= 200 mA

V_{S_LINE}

Static load

regulation

V_{S_LOAD}

I_OUT= 1 mA to 200 mA

5

10

mV

V_DD= V_SYS= 3.0V to 3.6 V

I_OUT= 100 mA

tr = tf = 10 µs

Line transient

response

V_{TR_LINE}

mV

dB

V_DD= 3.6 V

I_OUT= 1 mA to 200 mA

tr = tf = 1 µs

30

50

Load transient

response

V_{TR_LOAD}

f = 10 Hz to 10 kHz , RT

V_DD= 3.6 V, I_OUT= I_MAX/2

V_DD– V_LDO≥ 0.6 V

PSRR

Note 3

PSRR

40

50

70

Output noise

N

μV

rms

V_DD= V_SYS= 3.6 V,

V_LDO= 2.8 V

I_OUT= 5 mA to I_MAX

f = 10 Hz to 100 kHz , RT

Quiescent current

in ON mode

9 + 0.4%

of I_OUT

I_{Q_ON}

Note 4

μA

1.5 +

1.0% of

I_OUT

Quiescent current

forced sleep mode

I_{Q_SLEEP}

Quiescent current

OFF mode

I_{Q_OFF}

1

Datasheet

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23-Mar-2017

CFR0011-120-00

30 of 219

DA9063

System PMIC for Mobile Application Processors

Parameter

Symbol

Test Conditions

10 % to 90%

Min

Typ

Max

Unit

300

Turn-on time

t_ON

μs

SLEEP mode

390

1

90 % to 10%

Turn off time

t_OFF

ms

Pull-down resistor enabled

Pull-down

resistance in OFF

mode

Can be disabled via

LDO4_PD_DIS

R_OFF

100

0.5

Ω

Bypass mode

V_DD> 2.2 V

0.7

1.0

Bypass on-

resistance

R_ON

Ω

V_DD> 1.8 V

Current limit in

Bypass mode

I_LIM

200

400

100

mA

Quiescent current

in Bypass mode

I_{Q_BYPASS}

50

μA

Note 1 Max output current is 30% when the input voltage is 1.5 V

Note 2 Programmable in 20 mV voltage steps, maximum output voltage is determined by V_DD- dropout

voltage

Note 3 Measured at point of load

Note 4 Internal regulator current flowing to ground

5.8.5

LDO5

Table 17: LDO5, T_J= -40 ºC to +125 ºC

Parameter

Symbol

Test Conditions

Min

Typ

Max

5.5

Unit

V

V_DD= V_SYS

2.8

Input voltage

Output voltage

V_DD

1.5

If supplied from buck

Note 1

V_LDO

0.9

-3

Note 2

3.6

V

V_DD= V_SYS= 2.8 V to 5.5 V

I_OUT= 100 mA

Output accuracy

+3

%

Including static line/load

regulation

Including voltage and

temperature coefficient at

configured VLDO5

Stabilisation

capacitor

C_OUT

-55 %

1.0

+35 %

300

µF

Output capacitor

ESR

f > 1 MHz

Including wiring parasitics

R_{COUT_ESR}

I_{OUT_max}

I_SHORT

0

mΩ

mA

Output current

V_DD= V_SYS= 2.8 V to 5.5 V

100

Short circuit

current

200

100

Maximum forced

sleep mode

current

I_SLEEP

V_DD≥ 1.8 V

20

mA

mV

V_DD= V_SYS> 2.8 V

Dropout voltage

V_DROPOUT

150

I_OUT= 100 mA

(V_DD= 1.5 V, I_OUT= I_MAX/3)

Datasheet

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23-Mar-2017

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31 of 219

DA9063

System PMIC for Mobile Application Processors

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Static line

regulation

V_DD= V_SYS= 3.0 V to 5.5 V

I_OUT= 100 mA

V_{S_LINE}

1

5

mV

Static load

regulation

V_{S_LOAD}

I_OUT= 1 mA to 100 mA

5

10

mV

V_DD= V_SYS= 3.0 V to 3.6 V

I_OUT= 100 mA

tr = tf = 10 µs

Line transient

response

V_{TR_LINE}

V_DD= 3.6 V

I_OUT= 1 mA to 100 mA

tr = tf = 1 µs

Load transient

response

V_{TR_LOAD}

30

50

mV

dB

f = 10 Hz to 10 kHz , RT

V_DD= 3.6 V, I_OUT= I_MAX/2

V_DD– V_LDO≥ 0.6 V

40

PSRR

Note 3

PSRR

Output noise

N

μV

rms

V_DD= V_sys= 3.6 V,

V_LDO= 2.8 V

I_OUT= 5 mA to I_MAX

f = 10 Hz to 100 kHz , RT

70

Quiescent current

in ON mode

9 + 0.9 %

of I_OUT

I_{Q_ON}

Note 4

μA

Quiescent current

forced sleep

mode

1.5 +

1.6 % of

I_OUT

I_{Q_SLEEP}

Quiescent current

OFF mode

I_{Q_OFF}

1

350

10 % to 90 %

SLEEP mode

Turn-on time

Turn off time

t_ON

μs

450

1

90 % to 10 %

t_OFF

ms

Pull-down resistor enabled

Pull-down

resistance in OFF

mode

Can be disabled via

LDO5_PD_DIS

R_OFF

100

Ω

Note 1 Max output current is 30% when the input voltage is 1.5 V

Note 2 Programmable in 50 mV voltage steps, maximum output voltage is determined by V_DD- dropout

voltage

Note 3 Measured at point of load

Note 4 Internal regulator current flowing to ground

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23-Mar-2017

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DA9063

System PMIC for Mobile Application Processors

5.8.6

LDO6

Table 18: LDO6, T_J= -40 ºC to +125 ºC

Parameter

Symbol

Test Conditions

Min

Typ

Max

5.5

Unit

V

V_DD= V_SYS

2.8

Input voltage

Output voltage

V_DD

1.5

If supplied from buck

Note 1

V_LDO

0.9

-3

Note 2

3.6

V

V_DD= V_SYS= 2.8 V o 5.5 V

I_OUT= 200 mA

Output accuracy

+3

%

Including static line/load

regulation

Including voltage and

temperature coefficient at

configured VLDO6

Stabilisation

capacitor

C_OUT

-55%

2.2

+35%

300

µF

Output capacitor

ESR

f > 1 MHz

Including wiring parasitics

R_{COUT_ESR}

I_{OUT_max}

0

mΩ

Output current

V_DD= V_SYS= 2.8 V to 5.5 V

200

mA

Short circuit current I_SHORT

400

Maximum forced

I_SLEEP

V_DD≥ 1.8 V

30

mA

mV

sleep mode current

V_DD= V_SYS> 2.8 V

Dropout voltage

V_DROPOUT

100

1

150

5

I_OUT= 200 mA

(V_DD= 1.5 V, I_OUT= I_MAX/3)

Static line

regulation

V_DD= V_SYS= 3.0 V to 5.5 V

I_OUT= 200 mA

V_{S_LINE}

mV

5

10

Static load

regulation

V_{S_LOAD}

I_OUT= 1 mA to 200 mA

V_DD= V_SYS= 3.0 V to 3.6 V

I_OUT= 100 mA

tr = tf = 10 µs

Line transient

response

V_{TR_LINE}

mV

V_DD= 3.6 V

I_OUT= 1 mA to 200 mA

tr = tf = 1 µs

Load transient

response

V_{TR_LOAD}

30

80

50

V_DD= 3.6 V,

I_OUT= I_MAX/2

V_DD– V_LDO≥ 0.6 V

70

f = 10 Hz to 1 kHz , RT

f = 1 kHz to 10 kHz

PSRR

Note 3

PSRR

dB

60

40

30

70

50

40

f = 10 kHz to 100 kHz

f = 100 kHz to 10 MHz

Output noise

N

μV

rms

V_DD= V_SYS= 3.6 V,

V_LDO= 2.8 V

I_OUT= 5 mA to I_MAX

f = 10 Hz to 100 kHz , RT

35

Quiescent current

in ON mode

9+0.45%

of I_OUT

I_{Q_ON}

Note 4

μA

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DA9063

System PMIC for Mobile Application Processors

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Quiescent current

forced sleep mode

2+1.0%

of I_OUT

I_{Q_SLEEP}

μA

Quiescent current

OFF mode

I_{Q_OFF}

1

μA

μs

10 % to 90 %

SLEEP mode

200

260

Turn-on time

Turn off time

t_ON

90 % to 10 %

t_OFF

1

ms

Pull-down resistor enabled

Pull-down

resistance in OFF

mode

Can be disabled via

LDO6_PD_DIS

R_OFF

100

Ω

Note 1 Max output current is 30% when the input voltage is 1.5 V

Note 2 Programmable in 50 mV voltage steps, maximum output voltage is determined by VDD - dropout

voltage

Note 3 Measured at point of load

Note 4 Internal regulator current flowing to ground

5.8.7

LDO7

Table 19: LDO7, T_J= -40 ºC to 125 ºC

Parameter

Symbol

Test Conditions

Min

Typ

Max

5.5

Unit

V_DD= V_SYS

2.8

Input voltage

Output voltage

V_DD

V

1.5

Note 1

If supplied from buck

V_LDO

0.9

Note 2

3.6

V_DD= V_SYS= 2.8 V to 5.5 V

I_OUT= 200 mA

Output accuracy

-3

+3

%

Including static line/load

regulation

Including voltage and

temperature coefficient at

configured VLDO7

Stabilisation

capacitor

C_OUT

-55 %

2.2

+35 %

300

µF

f > 1 MHz

Including track impedance

ESR of capacitor

0

mΩ

mA

Maximum output

current

I_{OUT_max}

I_SHORT

V_DD= V_SYS= 2.8 V to 5.5 V

200

Short circuit

current

400

100

Maximum forced

sleep mode current

I_SLEEP

V_DD≥ 1.8 V

30

V_DD= V_SYS> 2.8 V

Dropout voltage

V_DROPOUT

150

mV

I_OUT= 200 mA

(V_DD= 1.5 V, I_OUT= I_MAX/3)

Static line

regulation

V_DD= V_SYS= 3.0V to 5.5 V

I_OUT= 200 mA

V_{S_LINE}

1

5

mV

10

Static load

regulation

V_{S_LOAD}

I_OUT= 1 mA to 200 mA

Datasheet

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23-Mar-2017

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DA9063

System PMIC for Mobile Application Processors

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

V_DD= V_SYS= 3.0 V to 3.6 V

I_OUT= 100 mA

tr = tf = 10 µs

5

10

Line transient

response

V_{TR_LINE}

mV

V_DD= 3.6 V

I_OUT= 1 mA to 200 mA

tr = tf = 1 µs

Load transient

response

V_{TR_LOAD}

30

50

mV

dB

f = 10 Hz to 10 kHz , RT

V_DD= 3.6 V, I_OUT= I_MAX/2

V_DD– V_LDO≥ 0.6 V

40

PSRR

Note 3

PSRR

Output noise

N

μV

rms

V_DD= V_sys= 3.6 V,

V_LDO= 2.8 V

I_OUT= 5 mA to I_MAX

f = 10 Hz to 100 kHz , RT

70

Quiescent current

in ON mode

9+0.4% of

I_OUT

I_{Q_ON}

Note 4

μA

Quiescent current

forced sleep mode

1.5+1.0%

of I_OUT

I_{Q_SLEEP}

I_{Q_OFF}

Quiescent current

OFF mode

1

10 % to 90 %

SLEEP mode

300

390

Turn-on time

Turn off time

T_ON

μs

90 % to 10 %

T_OFF

1

ms

Pull-down resistor enabled

Pull-down

resistance in OFF

mode

Can be disabled via

LDO7_PD_DIS

R_OFF

100

0.5

Ω

Bypass mode

V_DD> 2.2 V

0.7

1.0

Bypass on-

resistance

R_ON

V_DD> 1.8 V

Current limit in

Bypass mode

I_LIM

300

600

100

mA

Quiescent current

IQ_Bypass

50

μA

Note 1 Max output current is 30% when the input voltage is 1.5 V

Note 2 Programmable in 50 mV voltage steps, maximum output voltage is determined by V_DD- dropout

voltage

Note 3 Measured at point of load

Note 4 Internal regulator current flowing to ground

Datasheet

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23-Mar-2017

CFR0011-120-00

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DA9063

System PMIC for Mobile Application Processors

5.8.8

LDO8

Table 20: LDO8, T_J= -40 ºC to +125 ºC

Parameter

Symbol

Test Conditions

Min

Typ

Max

5.5

Unit

V

V_DD= V_SYS

2.8

Input voltage

Output voltage

V_DD

1.5

Note 1

If supplied from buck

V_LDO

0.9

Note 2

3.6

V

V_DD= V_SYS= 2.8 V to 5.5 V

I_OUT= 200 mA

Output accuracy

-3

+3

%

Including static line/load

regulation

Including voltage and

temperature coefficient at

configured VLDO8

Stabilisation

capacitor

C_OUT

-55 %

2.2

+35 %

300

µF

f > 1 MHz

Including track impedance

ESR of capacitor

0

mΩ

mA

Maximum output

current

I_{OUT_max}

I_SHORT

V_DD= V_SYS= 2.8 V to 5.5 V

200

Short circuit

current

400

Maximum forced

sleep mode

current

I_SLEEP

V_DD≥ 1.8 V

30

mA

mV

V_DD= V_SYS> 2.8 V

Dropout voltage

V_DROPOUT

100

1

150

5

I_OUT= 200 mA

(V_DD= 1.5 V, I_OUT= I_MAX/3)

Static line

regulation

V_DD= V_SYS= 3.0 V to 5.5 V

I_OUT= 200 mA

V_{S_LINE}

mV

5

10

Static load

regulation

V_{S_LOAD}

I_OUT= 1 mA to 200 mA

V_DD= V_SYS= 3.0 V to 3.6 V

I_OUT= 100 mA

tr = tf = 10 µs

Line transient

response

V_{TR_LINE}

mV

dB

V_DD= 3.6 V

I_OUT= 1 mA to 200 mA

tr = tf = 1 µs

30

50

Load transient

response

V_{TR_LOAD}

f = 10 Hz to 10 kHz , RT

V_DD= 3.6 V, I_OUT= I_MAX/2

V_DD– V_LDO≥ 0.6 V

40

PSRR

Note 3

PSRR

Output noise

N

μV

rms

V_DD= V_SYS= 3.6 V,

V_LDO= 2.8 V

I_OUT= 5 mA to I_MAX

f = 10 Hz to 100 kHz , RT

70

Quiescent current

in ON mode

9 + 0.4 %

of I_OUT

I_{Q_ON}

Note 4

μA

1.5 +

1.0 % of

I_OUT

Quiescent current

forced sleep mode

I_{Q_SLEEP}

Datasheet

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23-Mar-2017

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DA9063

System PMIC for Mobile Application Processors

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Quiescent current

OFF mode

I_{Q_OFF}

1

μA

10 % to 90 %

SLEEP mode

300

390

Turn-on time

Turn off time

T_ON

μs

90 % to 10 %

T_OFF

1

ms

Pull-down resistor enabled

Pull-down

resistance in OFF

mode

Can be disabled via

LDO8_PD_DIS

R_OFF

100

Ω

Vibration Motor Driver Mode

Output voltage

VIB_SET

6-bit resolution

0

8

3

V

(average)

Maximum output

I_MAX

300

mA

current

Short circuit

I_SHORT

400

current

Load resistance

Load impedance

Pull-up resistor

Pull-down resistor

Bypass Mode

R_LOAD

R_on

10

200

0.5

5

10000

Ω

µH

Ω

R_off

Ω

V_DD> 2.2 V

V_DD> 1.8 V

0.5

0.7

1.0

Bypass on-

resistance

R_ON

Ω

Current limit in

Bypass mode

I_LIM

300

600

100

mA

Quiescent current

in Bypass mode

IQ_Bypass

50

μA

Note 1 Max output current is 30% when the input voltage is 1.5 V

Note 2 Programmable in 50 mV voltage steps, maximum output voltage is determined by V_DD- dropout

voltage

Note 3 Measured at point of load

Note 4 Internal regulator current flowing to ground

Datasheet

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CFR0011-120-00

37 of 219

DA9063

System PMIC for Mobile Application Processors

5.8.9

LDO9

Table 21: LDO9, T_J= -40 ºC to +125 ºC

Parameter

Symbol

Test Conditions

Min

Typ

Max

5.5

Unit

V

V_DD= V_SYS

2.8

Input voltage

Output voltage

V_DD

1.5

If supplied from buck

Note 1

V_LDO

0.95

Note 2

3.6

V

V_DD= V_SYS= 2.8 V to 5.5 V

I_OUT= 200 mA

Output accuracy

-3

+3

%

Including static line/load

regulation

Note 3

Including voltage and

temperature coefficient at

configured VLDO9

Stabilisation

capacitor

C_OUT

-55 %

2.2

+35 %

300

µF

ESR of capacitor

f > 1 MHz

0

mΩ

Maximum output

current

I_{OUT_max}

I_SHORT

V_DD= V_SYS= 2.8 V to 5.5 V

200

mA

Short circuit

current

400

mA

Maximum forced

sleep mode current

I_SLEEP

V_DD≥ 1.8 V

30

V_DD= V_SYS> 2.8 V

Dropout voltage

V_DROPOUT

100

1

150

5

mV

I_OUT= 200 mA

(V_DD= 1.5 V, I_OUT= I_MAX/3)

Static line

regulation

V_DD= V_SYS= 3.0 V to 5.5 V

I_OUT= 200 mA

V_{S_LINE}

mV

5

10

Static load

regulation

V_{S_LOAD}

I_OUT= 1 mA to 200 mA

V_DD= V_SYS= 3.0 V to 3.6 V

I_OUT= 100 mA

tr = tf = 10 µs

Line transient

response

V_{TR_LINE}

mV

dB

V_DD= 3.6 V

I_OUT= 1 mA to 200 mA

tr = tf = 1 µs

Load transient

response

V_{TR_LOAD}

30

50

f = 10 Hz to 10 kHz , RT

V_DD= 3.6 V, I_OUT= I_MAX/2

V_DD– V_LDO≥ 0.6 V

40

PSRR

Note 4

PSRR

Output noise

N

μV

rms

V_DD= V_sys= 3.6 V,

V_LDO= 2.8 V

I_OUT= 5 mA to I_MAX

f = 10 Hz to 100 kHz , RT

35

Quiescent current

in ON mode

9+0.4% of

I_OUT

I_{Q_ON}

Note 5

μA

Quiescent current

forced sleep mode

2+1.0% of

I_OUT

I_{Q_SLEEP}

I_{Q_OFF}

Quiescent current

OFF mode

1

Datasheet

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23-Mar-2017

CFR0011-120-00

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DA9063

System PMIC for Mobile Application Processors

Parameter

Symbol

Test Conditions

10 % to 90 %

SLEEP mode

Min

Typ

Max

200

260

Unit

Turn-on time

T_ON

μs

90 % to 10 %

Turn off time

T_OFF

1

ms

Pull-down resistor enabled

Pull-down

resistance in OFF

mode

Can be disabled via

LDO9_PD_DIS

R_OFF

100

Ω

Note 1 Max output current is 30 % when the input voltage is 1.5 V

Note 2 Programmable in 50 mV voltage steps, maximum output voltage is determined by VDD - dropout

voltage

Note 3 At trimmed output voltage

Note 4 Measured at point of load

Note 5 Internal regulator current flowing to ground

5.8.10 LDO10

Table 22: LDO10, T_J= -40 ºC to 125 ºC

Parameter

Symbol

Test Conditions

Min

Typ

Max

5.5

Unit

V_DD= V_SYS

2.8

Input voltage

Output voltage

V_DD

V

1.5

Note 1

If supplied from buck

V_LDO

0.9

Note 2

3.6

V_DD= V_SYS= 2.8 to 5.5 V

I_OUT= 300 mA

Output accuracy

-3

+3

%

Including static line/load

regulation

Including voltage and

temperature coefficient

configured VLDO10

Stabilisation

capacitor

C_OUT

-55%

2.2

+35%

300

µF

Output capacitor

ESR

f > 1 MHz

Including wiring parasitics

R_{COUT_ESR}

I_{OUT_max}

0

mΩ

Output current

V_DD= V_SYS= 2.8 V to 5.5 V

300

mA

Short circuit current I_SHORT

600

Maximum sleep

I_SLEEP

V_DD≥ 1.8 V

30

mA

mV

mode current

V_DD= V_SYS> 2.8 V

Dropout voltage

V_DROPOUT

100

2

150

10

I_OUT= 300 mA

(V_DD= 1.5 V, I_OUT= I_MAX/3)

Static line

regulation

V_DD= V_SYS= 3.0 V to 5.5 V

I_OUT= 300 mA

V_{S_LINE}

mV

Static load

regulation

V_{S_LOAD}

I_OUT= 1 mA to 300 mA

5

20

10

V_DD= V_SYS= 3.0 V to 3.6 V

I_OUT= 300 mA

tr = tf = 10 µs

Line transient

response

V_{TR_LINE}

mV

Datasheet

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23-Mar-2017

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DA9063

System PMIC for Mobile Application Processors

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

V_DD= 3.6 V

I_OUT= 1 mA to 300 mA

tr = tf = 1 µs

Load transient

response

V_{TR_LOAD}

30

50

mV

V_DD= 3.6 V

I_OUT= I_MAX/2

V_DD– V_LDO≥ 0.6 V

70

80

f = 10 Hz to 1 kHz , RT

PSRR

Note 3

PSRR

dB

f = 1 kHz to 10 kHz

60

40

30

70

50

40

f = 10 kHz to 100 kHz

f = 100 kHz to 10 MHz

Output noise

N

μV

rms

V_DD= V_SYS= 3.6 V,

V_LDO= 2.8 V

I_OUT= 5 mA to I_MAX

f = 10 Hz to 100 kHz , RT

35

9 +

0.34 % of

I_OUT

Quiescent current

in ON mode

I_{Q_ON}

Note 4

μA

Quiescent current

forced sleep mode

2 + 0.7 %

of I_OUT

I_{Q_SLEEP}

I_{Q_OFF}

μA

Quiescent current

OFF mode

1

10 % to 90 %

SLEEP mode

200

300

Turn-on time

Turn off time

t_ON

μs

90 % to 10 %

t_OFF

1

ms

Pull-down resistor enabled

Pull-down

resistance in OFF

mode

Can be disabled via

LDO10_PD_DIS

R_OFF

100

Ω

Note 1 Max output current is 30 % when the input voltage is 1.5 V

Note 2 Programmable in 50 mV voltage steps, maximum output voltage is determined by V_DD- dropout

voltage

Note 3 Measured at point of load

Note 4 Internal regulator current flowing to ground

Datasheet

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DA9063

System PMIC for Mobile Application Processors

5.8.11 LDO11

Table 23: LDO11, T_J= -40 ºC to +125 ºC

Parameter

Symbol

Test Conditions

Min

Typ

Max

5.5

Unit

V

V_DD= V_SYS

2.8

Input voltage

Output voltage

V_DD

1.5

If supplied from buck

Note 1

V_LDO

0.9

-3

Note 2

3.6

V

V_DD= V_SYS= 2.8V to 5.5 V

I_OUT= 200 mA

Output accuracy

+3

%

Including static line/load

regulation

Including voltage and

temperature coefficient at

configured VLDO11

Stabilisation

capacitor

C_OUT

-55 %

2.2

+35 %

300

µF

f > 1 MHz

Including track impedance

ESR of capacitor

0

mΩ

Maximum output

current

I_{OUT_max}

V_DD= V_SYS= 2.8 V to 5.5 V

300

mA

Short circuit current I_SHORT

600

Maximum sleep

I_SLEEP

V_DD≥ 1.8 V

30

mode current

V_DD= V_SYS> 2.8 V

Dropout voltage

V_DROPOUT

100

2

150

15

mV

I_OUT= 300 mA

(V_DD= 1.5 V, I_OUT= I_MAX/3)

V_DD= V_SYS= 2.8 V to 5.5 V

Static line

regulation

V_{S_LINE}

mV

V_LDO= 1.86 V

I_OUT= 300 mA

Static load

regulation

V_{S_LOAD}

I_OUT= 1 mA to 300 mA

5

20

10

V_DD= V_SYS= 2.8 V to 5.5 V

Line transient

response

V_LDO= 1.86 V

I_OUT= 300 mA

tr = tf = 10 µs

V_{TR_LINE}

mV

V_DD= 3.6 V

I_OUT= 1 mA to 300 mA

tr = tf = 1 µs

30

50

Load transient

response

V_{TR_LOAD}

mV

dB

f = 10 Hz to 10 kHz , RT

V_DD= 3.6 V, I_OUT= I_MAX/2

V_DD– V_LDO≥ 0.6 V

40

PSRR

Note 3

PSRR

Output noise

N

μV

rms

V_DD= V_SYS= 3.6 V,

V_LDO= 2.8 V

I_OUT= 5 mA to I_MAX

f = 10 Hz to 100 kHz , RT

70

9 +

0.45 % of

I_OUT

Quiescent current

in ON mode

I_{Q_ON}

Note 4

μA

Quiescent current

forced sleep mode

2 + 0.7 %

of I_OUT

I_{Q_SLEEP}

Datasheet

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23-Mar-2017

CFR0011-120-00

41 of 219

DA9063

System PMIC for Mobile Application Processors

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Quiescent current

OFF mode

I_{Q_OFF}

1

μA

10 % to 90 %

SLEEP mode

200

260

Turn-on time

Turn off time

T_ON

μs

90 % to 10 %

T_OFF

1

ms

Pull-down resistor enabled

Pull-down

resistance in OFF

mode

Can be disabled via

LDO11_PD_DIS

R_OFF

100

0.3

Ω

Bypass Mode

V_DD> 2.2 V

0.7

1.0

Bypass on-

resistance

R_ON

Ω

V_DD> 1.8 V

Current limit in

Bypass mode

I_LIM

300

600

100

mA

Quiescent current

in Bypass mode

IQ_Bypass

50

μA

Note 1 Max output current is 30% when the input voltage is 1.5 V

Note 2 Programmable in 50 mV voltage steps, maximum output voltage is determined by VDD - dropout

voltage

Note 3 Measured at point of load

Note 4 Internal regulator current flowing to ground

5.8.12 LDOCORE

Table 24: LDOCORE, T_J= -40 ºC to 125 ºC

Parameter

Symbol

Test Conditions

Note 1

Min

Typ

2.5

2.2

Max

Unit

Output voltage

V_DDCORE

2.45

2.55

V

RESET mode

Stabilisation capacitor

Output capacitor ESR

Dropout voltage

C_OUT

Including voltage and

temperature coefficient

-55 %

0

+35 %

300

µF

R_{COUT_ESR}f > 1 MHz

Including wiring parasitics

mΩ

V_DROPOUT

Note 2

50

100

mV

Note 1 Setting VDD_FAULT_LOWER ≥ 2.65 V avoids LDOCORE dropout, see Section 5.15.

Note 2 The LDOCORE supply, VSYS or CHG_WAKE , must be maintained above V_DDCORE+ V_DROPOUT

Note

LDOCORE is only used to supply internal circuits.

Datasheet

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DA9063

System PMIC for Mobile Application Processors

5.9 DC/DC Buck Converters

5.9.1

BUCKCORE1 and BUCKCORE2

Table 25: BUCKCORE1, T_J= -40 ºC to +125 ºC

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Input voltage

V_DD

V_DD= V_SYS

2.8

5.5

V

Including voltage and

temperature coefficient

µF

Output capacitor

C_OUT

Half-current mode

Full-current mode

2 x 22

2 x 47

-50 %

+30 %

Including wiring parasitics

f > 100 kHz

Half-current mode

Output capacitor

ESR

15

50

25

mΩ

C_OUT= 2 * 22 μF

Full-current mode

7.5

C_OUT= 2 * 47 μF

Including current and

temperature dependence

Inductor value

L_BUCK

L_ESR

0.7

1.0

55

1.3

µH

Inductor resistance

100

mΩ

PWM Mode

Programmable in 10 mV

steps

Output voltage

V_BUCK

0.3

-1

1.57

+1

V

Note 1

Excluding static line/load

regulation and voltage

ripple

T_A= 25 °C

V_DD= 4.2 V

V_BUCK= 1.03 V

Excluding static line/load

regulation and voltage

ripple

-1.5

+1.5

T_A= -40 °C to +85 °C

V_DD= 4.2 V

Output voltage

accuracy

%

V_BUCK= 1.03 V

Including static line/load

regulation and voltage

ripple

-2

-3

+2

+3

I_OUT= I_MAX

V_BUCK= 1.03 V

L_BUCK, L_ESR= Typ

Including static line/load

regulation and voltage

ripple

I_OUT= I_MAX

Note 2

Datasheet

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23-Mar-2017

CFR0011-120-00

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DA9063

System PMIC for Mobile Application Processors

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

V_DD= 3.6 V

V_BUCK= 1.2 V

I_OUT= 200 mA / 0.8 * I_MAX

dI/dt = 3 A/µs

L_BUCK= 1.0 µH

Note 3

Load regulation

transient

V_{TR_LD}

-4

+4

%

V_DD= 3.0 V to 3.6 V

I_OUT= 500 mA

tr = tf = 10 µs

Line regulation

transient

V_{TR_LINE}

0.2

10

5

3

mV

mΩ

nH

From output capacitor to

sense connection at point-

of-load

Parasitic track

resistance

From output capacitor to

sense connection at point-

of-load

Parasitic track

inductance

Feedback

Comparator input

impedance

R_FB

500

kΩ

Half-current mode

Full-current mode

1250

2500

Output current

I_MAX

mA

BCORE1_ILIM=0000

BCORE1_ILIM=1111

-20 %

500

+20 %

mA

Current limit

(programmable)

I_LIM

Note 4

2000

Quiescent current

in OFF mode

I_{Q_OFF}

1

µA

Half-current mode

I_OUT= 0 mA

9.0

Quiescent current

in PWM mode

I_{Q_ON}

mA

Full-current mode

11.0

Switching

frequency

f

OSC_FRQ = 0000

2.85

10.5

3

3.15

84

MHz

%

Note 5

Switching duty

cycle

D

V_BUCK= 1.15 V

BUCK_SLOWSTART =

disabled

Turn on time

T_ON

0.37

1.2

ms

SLEW_RATE = 10

mV/1 µs

BUCK<x>_ILIM = 1500 mA

V_BUCK= 0.5 V

Output pull-down

resistor

R_PD

80

200

Ω

Can be disabled via

BCORE1_PD_DIS

PMOS ON

resistance

R_PMOS

Half-current mode

Including pin and routing

V_SYS= 3.6 V

160

mΩ

Full-current mode

Including pin and routing

V_SYS= 3.6 V

80

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DA9063

System PMIC for Mobile Application Processors

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

NMOS ON

resistance

R_NMOS

Half-current mode

Including pin and routing

V_SYS= 3.6 V

60

mΩ

Full-current mode

Including pin and routing

V_SYS= 3.6 V

30

84

V_DD= 3.6 V

Efficiency

Note 6

η

V_BUCK= 1.2 V

%

I_OUT= 0.1 to 0.7 * I_MAX

PFM Mode

Programmable in 10 mV

steps

Output voltage

V_BUCK

0.3

1.57

V

Typical automatic

mode switching

current

I_{AUTO_THR}

260

mA

Output current

Current limit

I_{OUT_PFM}

I_{LIM_PFM}

300

600

mA

I_OUT= 0

Quiescent current

I_{Q_PFM}

Forced PFM mode

AUTO mode

27

35

32

42

µA

Frequency of

operation

0

3

MHz

%

V_DD= 3.6 V

V_BUCK= 1.2 V

I_OUT= 10 mA

Efficiency

Note 6

η

86

Note 1 If BUCK<x>_MODE = 10 (synchronous) then the buck operates in PFM mode when V_BUCK< 0.7 V.

For complete control of the buck mode (PWM versus PFM) use BUCK<x>_MODE = 00.

Note 2 Minimum tolerance 35 mV

Note 3 Measured at C_OUT, depends on parasitics of PCB and external components when remote sensing

Note 4 Current limit values are doubled in full-current mode

Note 5 Generated from internal 6 MHz oscillator and can be adjusted by ± 10 % via control OSC_FRQ

Note 6 Depends on external components and PCB routing

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DA9063

System PMIC for Mobile Application Processors

5.9.2

BUCKPRO

Table 26: BUCKPRO, T_J= -40 ºC to +125 ºC

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Input voltage

V_DD

V_DD= V_SYS

2.8

5.5

V

Including voltage and

temperature coefficient

Output capacitor

C_OUT

µF

Half-current mode

Full-current mode

2 * 22

2 * 47

-50 %

+30 %

Including wiring parasitics

f > 100 kHz

Half-current mode

Output capacitor ESR

Inductor value

15

50

25

mΩ

COUT = 2 * 22 μF

Full-current mode

7.5

COUT = 2 * 47 μF

Including current and

temperature dependence

L_BUCK

L_ESR

0.7

1.0

55

1.3

µH

Inductor resistance

100

mΩ

PWM Mode

Programmable in 10 mV

steps

Output voltage

V_BUCK

0.53

-3

1.8

+3

V

Note 1

Including static line/load

regulation and voltage

ripple

I_OUT= I_MAX

Note 2

Output voltage accuracy

%

Excluding static line/load

regulation and voltage

ripple

-1

+1

T_A= 25 °C

V_BUCK> 1 V

V_DD= 5 V

V_DD= 3.6 V

V_BUCK= 1.2 V

I_OUT= 200 mA / 0.8 * I_MAX

dI/dt = 3 A/µs

L_BUCK= 1.0 µH

Note 3

Transient load regulation V_{TR_LD}

20

50

3

mV

V_DD= 3.0 V to 3.6 V

I_OUT= 500 mA

tr = tf = 10 µs

Transient line regulation

Output current

V_{TR_LINE}

0.2

mV

mA

Half-current mode

Full-current mode

BPRO_ILIM=0000

BPRO_ILIM=1111

1250

2500

I_MAX

-20 %

500

+20 %

mA

Current limit

(programmable)

I_LIM

2000

Datasheet

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23-Mar-2017

CFR0011-120-00

46 of 219

DA9063

System PMIC for Mobile Application Processors

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Quiescent current in

OFF mode

I_{Q_OFF}

1

µA

Half-current mode

Full-current mode

9.0

Quiescent current in

PWM mode

I_{Q_ON}

mA

11.0

Switching frequency

Note 4

f

OSC_FRQ = 0000

2.85

10.6

3

3.15

84

MHz

%

Switching duty cycle

D

@ V_OUT= 0.5 V

Output pull-down resistor R_PD

80

200

Ω

Can be disabled via

BPRO_PD_DIS

Including pin and routing

V_SYS= 3.6 V

mΩ

PMOS ON resistance

NMOS ON resistance

R_PMOS

150

60

Including pin and routing

V_SYS= 3.6 V

R_NMOS

V_DD= 3.6 V

Efficiency

Note 5

η

V_BUCK= 1.2 V

84

%

I_OUT= 0.1 mA to 0.7 * I_MAX

PFM Mode

Programmable in 10 mV

steps

Output voltage

V_BUCK

0.53

1.8

V

Typical automatic mode

switching current

I_{AUTO_THR}

260

mA

Output current

Current limit

I_{OUT_PFM}

I_LIM

300

600

mA

I_OUT= 0 mA

Quiescent current

I_{Q_PFM}

Forced PFM mode

AUTO mode

22

30

25

35

3

µA

Frequency of operation

f

0

MHz

%

V_DD= 3.6 V

V_BUCK= 1.2 V

I_OUT= 10 mA

Efficiency

Note 5

η

86

VTT Mode

Input voltage

V_DD

V_DD= V_SYS

2.8

5.5

V

Including voltage and

temperature coefficient

Output capacitor

Output capacitor ESR

Inductor value

C_OUT

-50 %

2 * 47

7.5

+30 %

µF

ESR of C_OUT

@ f > 100 kHz + track

impedance

R_{COUT_ESR}

25

mΩ

Including current and

temperature dependence

L_BUCK

0.7

1.0

55

1.3

µH

Inductor resistance

Output voltage

L_ESR

100

1.3

mΩ

V_BUCK

V_BUCK= V_DDQ/2

0.675

V

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System PMIC for Mobile Application Processors

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Relative to VTTR

Including static line and

load regulation

Output voltage accuracy

V_{BUCK_ACC}

- 3

4

%

I_OUT= 1 A

C_ESR

Output voltage ripple

V_{BPRO_RPL}

10

20

30

mV

Half-current mode

V_DD= 3.6 V

V_BUCK= 0.7 V

40

I_OUT= 10 mA to 1 A

I_OUT= -750 mA to -10 mA

L_BUCK= 0.24 µH

dI/dt = 3 A/µs

Full-current mode

V_DD= 3.6 V

V_BUCK= 0.75 V

I_OUT= 10 mA to 1.4 A

I_OUT= -10 mA to -1.4 A

L_BUCK= 0.24 µH

dI/dt = 3 A/µs

20

40

mV

Transient load regulation V_{TR_LD}

Full-current mode

V_DD= 3.6 V

V_BUCK= 0.7 V

I_OUT= 10 mA to 1.1 A

I_OUT= -10 mA to -1.1 A

L_BUCK= 0.24 µH

dI/dt = 3 A/µs

Full-current mode

V_DD= 3.6 V

V_BUCK= 0.675 V

I_OUT= 10 mA to 900 mA

I_OUT= -10 mA to -900 mA

L_BUCK= 0.24 µH

dI/dt = 3 A/µs

Half-current mode

V_BUCK= 0.7 V

-550

-1400

-1100

-900

1250

2500

mA

Full-current mode

V_BUCK= 0.75

Maximum output current

I_MAX

Full-current mode

V_BUCK= 0.7 V

Full-current mode

V_BUCK= 0.675 V

V_BUCK= 0.75 V

BUCK_SLOWSTART =

disabled

SLEW_RATE =

10 mV/1 µs

Turn-on time

t_ON

0.33

1.2

ms

BUCK4_ILIM = 1500 mA

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System PMIC for Mobile Application Processors

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

VTTR Buffer

Feedback voltage

Output voltage

VDDQ

V_VTTR

V_DD= V_SYS

1.35

2.6

1.3

V

I_OUT= 0 mA to I_VTTR

0.675

VDDQ/2

V_{VTTR_ACC}related to VDDQ

input voltage

Voltage accuracy

V_{VTTR_ACC}

-1

+1

%

Including voltage and

temperature coefficient

Output capacitor

C_OUT

I_OUT

-50 %

-10

0.1

+30 %

10

µF

Sink/source current

mA

Note 1 If BUCK<x>_MODE = 10 (synchronous) then the buck operates in PFM mode when V_BUCK< 0.7 V.

For complete control of the buck mode (PWM versus PFM) use BUCK<x>_MODE = 00.

Note 2 Minimum tolerance 35 mV

Note 3 Measured at C_OUT, depends on parasitics of PCB and external components when remote sensing

Note 4 Generated from internal 6 MHz oscillator and can be adjusted by ± 10 % via control OSC_FRQ

Note 5 Depends on external components and PCB routing

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System PMIC for Mobile Application Processors

5.9.3

BUCKMEM

Table 27: BUCKMEM, T_J= -40 ºC to +125 ºC

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Input voltage

V_DD

V_DD= V_SYS

2.8

5.5

V

Including voltage and

temperature coefficient

2 * 22

2 * 47

Output capacitor

C_OUT

-50 %

+30 %

µF

Merged mode

Including wiring parasitics

f > 100 kHz

Output capacitor ESR

C_OUT= 2 * 22 μF

C_OUT= 2 * 47 μF

15

50

25

mΩ

7.5

Including current and

temperature dependence

Inductor value

L_BUCK

L_ESR

0.7

0.8

1.0

55

1.3

100

3.34

µH

mΩ

V

Inductor resistance

Output voltage

Programmable in 20 mV

steps

V_BUCK

Including static line/load

regulation and voltage

ripple

-3

-2

+3

+2

I_OUT= I_MAX

Note 1

Output voltage accuracy

%

Excluding static line/load

regulation and voltage

ripple

T_A= 25 °C

V_DD= 5 V

V_BUCK> 1 V

V_DD= 3.6 V

V_BUCK= 1.2 V

I_OUT= 200 mA / 0.8 * I_MAX

dI/dt = 3 A/µs

Note 2

Transient load regulation V_{TR_LD}

-4

+4

3

%

V_DD= 3.0 V to 3.6 V

I_OUT= 500 mA

Transient line regulation

Output current

V_{TR_LINE}

0.2

mV

tr = tf = 10 µs

I_MAX

1500

-20 %

mA

BMEM_ILIM = 0000

BMEM_ILIM = 1111

1500

3000

+20 %

Current limit

I_LIM

(programmable)

Note 3

Quiescent current in

OFF mode

I_{Q_OFF}

I_{Q_ON}

1

µA

Quiescent current in

PWM mode

I_OUT= 0 mA

9

3

mA

Switching frequency

Note 4

f

OSC_FRQ = 0000

2.85

14.5

3.15

MHz

Switching duty cycle

D

100

200

%

Output pull-down resistor

V_BUCK= 0.5 V

80

Ω

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DA9063

System PMIC for Mobile Application Processors

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Disabled via

BMEM_PD_DIS

V_DD= 3.6 V

Efficiency

Note 5

η

V_BUCK= 1.2 V

83

%

I_OUT= 0.1 mA to 0.7 * I_MAX

PFM Mode

Programmable in 20 mV

steps

Output voltage

V_BUCK

0.8

3.34

V

Typical automatic mode

switching current

260

mA

Output current

Current limit

I_MAX

I_LIM

300

600

mA

I_OUT= 0 mA

Quiescent current

I_{Q_PFM}

Forced PFM mode

AUTO mode

22

30

25

35

3

µA

Frequency of operation

f

0

MHz

V_DD= 3.6 V

Efficiency

Note 5

η

V_BUCK= 1.2 V

I_OUT= 10 mA

86

%

Note 1 Minimum tolerance 35 mV

Note 2 Measured at C_OUT, depends on parasitics of PCB and external components when remote sensing

Note 3 The current limits are automatically doubled when BUCKMEM is merged with BUCKIO

Note 4 Generated from internal 6 MHz oscillator and can be adjusted by ± 10 % via control OSC_FRQ

Note 5 Depends on external components and PCB routing

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DA9063

System PMIC for Mobile Application Processors

5.9.4

BUCKIO

Table 28: BUCKIO, T_J= -40 ºC to +125 ºC

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Input voltage

V_DD

V_DD= V_SYS

2.8

5.5

V

Including voltage and

temperature coefficient

Output capacitor

Output capacitor ESR

Inductor value

C_OUT

-50%

2x22

15

+30%

50

µF

f > 100 kHz

mΩ

All caps + track impedance

Including current and

temperature dependence

L_BUCK

L_ESR

0.7

1.0

55

1.3

µH

Inductor resistance

100

mΩ

PWM Mode

Programmable in 20 mV

steps

3.34

Note 2

Output voltage

V_BUCK

0.8

-3

V

Note 1

Including static line/load

regulation and voltage

ripple @ I_OUT= I_MAX

Note 3

+3

+2

Output voltage

accuracy

T_A= 25 °C

I_OUT= 0

%

-2

-4

V_OUT> 1 V

V_DD= 5 V

I_OUT= 200 mA/0.8 * I_MAX

dI/dt = 3 A/µs

Load regulation

transient

V_{TR_LD}

Note 4

0.2

+4

3

%

V_DD= 3.0 V to 3.6 V

I_OUT= 500 mA

tr = tf = 10 µs

Line regulation

transient

V_{TR_LINE}

mV

Output current

I_MAX

I_LIM

1500

-20 %

mA

BIO_ILIM=0000

BIO_ILIM=1111

1500

3000

20 %

Current limit

(programmable)

Quiescent current in

OFF mode

I_{Q_OFF}

I_{Q_ON}

1

µA

Quiescent current in

PWM mode

9

3

mA

Switching frequency

Switching duty cycle

f

2.85

14.5

3.15

100

MHz

%

D

V_OUT= 0.5 V

Output pull-down

resistor

80

87

200

Ω

Can be disabled via

BIO_PD_DIS

V_DD= 3.6 V

Efficiency

Note 5

η

V_BUCK= 1.8 V

%

I_OUT= 0.1 to 0.7 * I_MAX

Datasheet

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DA9063

System PMIC for Mobile Application Processors

Parameter

PFM Mode

Symbol

Test Conditions

Min

Typ

Max

Unit

Typical automatic

mode switching

current

260

mA

Output current

Current limit

I_MAX

I_LIM

300

600

mA

Quiescent current in

PFM mode

25

Note 6

I_{Q_PFM}

I_OUT= 0

22

µA

Frequency of

operation

0

3

MHz

V_DD= 3.6 V

Efficiency

Note 5

η

V_BUCK= 1.8 V

I_OUT= 10 mA

90

%

Note 1 If BUCK<x>_MODE = 10 (synchronous) then the buck operates in PFM mode when V_BUCK< 0.7 V.

For complete control of the buck mode (PWM versus PFM) use BUCK<x>_MODE = 00.

Note 2 Maximum V_DDto 0.7 V

Note 3 Minimum tolerance 35 mV

Note 4 Measured at C_OUT, depends on parasitics of PCB and external components when remote sensing

Note 5 Depends on external components and PCB routing

Note 6 <35 µA with automatic mode switching enabled

5.9.5

BUCKPERI

Table 29: BUCKPERI, T_J= -40 ºC to +125 ºC

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Input voltage

V_DD

V_DD= V_SYS

2.8

5.5

V

Including voltage and

temperature coefficient

Output capacitor

C_OUT

-50 %

2 x 22

15

+30 %

50

µF

f > 100 kHz

Output capacitor ESR

mΩ

All caps + track impedance

Including current and

temperature dependence

Inductor value

L_BUCK

L_ESR

0.7

1.0

55

1.3

µH

Inductor resistance

100

mΩ

Programmable in 20 mV

steps

3.34

Note 2

Output voltage

V_BUCK

0.8

-3

V

Note 1

Including static line/load

regulation and voltage ripple

I_OUT= I_MAX

Note 3

+3

+2

Output voltage

accuracy

T_A= 25 °C

I_OUT= 0

%

-2

V_OUT> 1 V

V_DD= 5 V

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System PMIC for Mobile Application Processors

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

I_OUT= 200 mA/0.8 * I_MAX

dI/dt = 3 A/µs

Load regulation

transient

V_{TR_LD}

-4

Note 4

+4

%

V_DD= 3.0 V to 3.6 V

I_OUT= 500 mA

Line regulation

transient

V_{TR_LINE}

0.2

3

mV

tr = tf = 10 µs

Output current

I_MAX

I_LIM

1500

-20%

mA

BPERI_ILIM = 0000

BPERI_ILIM = 1111

1500

3000

+20%

Current limit

(programmable)

Quiescent current in

OFF mode

I_{Q_OFF}

I_{Q_ON}

1

µA

Quiescent current in

PWM mode

9

3

mA

Switching frequency

Switching duty cycle

f

2.85

14.5

3.15

100

MHz

%

D

V_OUT= 0.5 V

Output pull-down

resistor

80

91

200

Ω

Can be disabled via

BPERI_PD_DIS

V_DD= 3.6 V

Efficiency

Note 5

η

V_BUCK= 2.86 V

I_OUT= 0.1 to 0.7 * I_MAX

%

PFM Mode

Typical automatic

mode switching current

260

mA

Output current

Current limit

I_MAX

I_LIM

300

600

mA

Quiescent current in

PFM mode

25

Note 6

I_{Q_PFM}

I_OUT= 0

22

µA

Frequency of operation

0

3

MHz

V_DD= 3.6 V

Efficiency

Note 5

η

V_BUCK= 2.86 V

I_OUT= 10 mA

93

%

Note 1 If BUCK<x>_MODE = 10 (synchronous) then the buck operates in PFM mode when V_BUCK< 0.7 V.

For complete control of the buck mode (PWM versus PFM) use BUCK<x>_MODE = 00.

Note 2 Maximum V_DDto 0.7 V

Note 3 Minimum tolerance 35 mV

Note 4 Measured at C_OUT, depends on parasitics of PCB and external components when remote sensing

Note 5 Depends on external components and PCB routing

Note 6 <35 µA with automatic mode switching enabled

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23-Mar-2017

CFR0011-120-00

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System PMIC for Mobile Application Processors

5.9.6

Typical Characteristics

Figure 9: BUCKCORE1 Efficiency in AUTO Mode, V_OUT= 1.2 V

Figure 10: BUCKCORE2 Efficiency in AUTO Mode, V_OUT= 1.2 V

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Figure 11: BUCKPRO Efficiency in AUTO Mode, V_OUT= 1.2 V

Figure 12: BUCKMEM Efficiency in AUTO Mode, V_OUT= 1.2 V

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Figure 13: BUCKIO Efficiency in AUTO Mode, V_OUT= 1.8 V

Figure 14: BUCKPERI Efficiency in AUTO Mode, V_OUT= 2.86 V

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DA9063

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5.10 Buck Rail Switches

Table 30: Buck Rail Switches, T_J= -40 ºC to +125 ºC

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Input voltage

V_DD

V_DD= VDDCORE

2.45

2.5

2.55

V

Including voltage and

temperature coefficient

Output capacitor

Output voltage

C_OUT

V_CP

T_ON

-30%

4.5

47

nF

V

I_OUT= 10 µA

4.6

Charge pump turn on

time

20 to 80% of V_CP

0.6

2.8

5

ms

V

NMOS input voltage

V_BUCK

Gate driver source

current

Vgate = 4.4 V

Vgate = 0.5 V

µA

Gate driver sink current

Voltage slew rate

180

50

µA

1

mV/us

Note 1

Output pull-down

resistor

@ V_OUT= 0.1 V

370

Ω

Note 1 OTP programmable via SWITCH_SR (register SWITCH_CONT).

5.11 Backup Battery Charger

Table 31: Backup Battery Charger, T_J= -40 ºC to +125 ºC

Parameter

Symbol

Test Conditions

Min

100

Typ

Max

Unit

Backup Battery

Charging Current

V_SYS= 3.6 V,

VBBAT = 2.5 V

BCHG_ISET

Note 1

Note 2

6000

µA

Charger Termination

Voltage

BCHG_VSET

V_SYS= 3.6 V

VBBAT = 0 V

1.1

3.1

V

Backup Battery Short

Circuit Current

6.8

mA

Stabilization capacitor

ESR of capacitor

Dropout voltage

C_OUT

-55%

470

+35%

100

nF

mΩ

mV

f > 1 MHz

V_DROPOUT

I_OUT= 5 mA

150

200

5.25+1.75%

of I_OUT

I_OUT> 50 µA

µA

Quiescent Current

IQ

5.25+1.5%

of I_OUT

I_OUT< 50 μA

Note 1 Programmable in 100 µA increments from 100 µA to 1000 µA and 1 mA increments from 1 mA to

6 mA

Note 2 Programmable in steps of 100 mV /200 mV

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System PMIC for Mobile Application Processors

5.12 General Purpose ADC

Table 32: General Purpose ADC, T_J= -40 ºC to +125 ºC

Parameter

Symbol

Test Conditions

Min

Typ

Max

2.55

1

Unit

V

ADC reference voltage

Off current

V_DD

V_DD= VDDCORE

2.45

2.5

µA

bit

ADC resolution

10

ADC integral non

linearity

± 2

LSB

ADC differential non

linearity

± 0.8

13

LSB

mV

kΩ

ADC absolute accuracy

15

Maximum source

impedance

R_SRC

Note 1

120

Input capacitance

C_IN

Total input capacitance

V_SYSminus VDDCORE

10.5

pF

Vsys = 3.125*(ADC/255)+2.5

(Auto)

V_SYSvoltage range

Channel 0

2.5

0

5.5

2.5

V

Vsys = 3.125*(ADC/1023)+2.5

(Man)

ADCIN1 to 3 voltage

range

Channel 1 to 3

Vin= (ADC*2.5)/255 (Auto)

Vin= (ADC*2.5)/1023 (Man)

Internal temperature

Sensor voltage range

Channel 4

T_J= -0.398 * ADC +330

VBBAT = (ADC*5)/1023

0

0.833

5.0

V

VBBAT voltage range

Channel 5

Regulator monitor

voltage range

Channel 8 to 10

Vreg = (ADC*5)/255

Note 2

5.0

Inter channel isolation

60

dB

µA

ADCIN1,2 current source

Note 3

-3%

1-40

3%

COMP1V2 comparator

level

1.2

V

Channel 2

Note 1 R_SRCis the impedance of the external source the ADC is sampling

Note 2 80 dB for channel A2 (ADC_IN2)

Note 3 Variance guaranteed for 10 µA to 40 µA and up to 2 V output voltage

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DA9063

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5.13 32K Oscillator

Table 33: 32K Oscillator, T_J= -40 ºC to 125 ºC

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Supply voltage

VDDRTC

1.5

2.75

V

Oscillator crystal

frequency

f_OSC

32.768

kHz

Crystal series resistance

Output frequency

R_OSC

f_OUT

100

2.0

kΩ

32.768

0.5

kHz

Start-up time for cell over

the voltage range

T_START

VBBAT = 1.5 V to 2.75 V

s

Current consumption

from backup device

during RTC mode

0.5

8

µA

Current consumption

from V_DDREFwith

OUT_32K enabled

µA

ns

Cycle-to-cycle jitter (rms)

Period jitter (rms)

Bypass Mode

1000 pulse

20

12

35

20

10000 pulse

Input frequency

F_IN

DC

V_IH

-5%

40

32

+5%

60

kHz

%

Input duty cycle

XTAL_IN

Input high voltage

RTC_EN = 0

1.8

1.1

V_SYS

V

RTC_EN = 1

V_{BBAT <}V_SYS

RTC_EN = 1

V_{BBAT >}V_SYS

0.7 * V_BBAT

-0.3

V_BBAT

XTAL_OUT

V_IL

RTC_EN = 0

0.6

0.4

V

Input low voltage

RTC_EN = 1

V_{BBAT <}V_SYS

RTC_EN = 1

V_{BBAT >}V_SYS

0.2 * V_BBAT

Input slew rate

SR

2 pF input capacitance

0.1

V/ns

5.14 Internal Oscillator

Table 34: Internal Oscillator, T_J= -40 ºC to +125 ºC

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

MHz

Internal oscillator

frequency

After trimming

5.7

6.0

6.3

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DA9063

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5.15 POR, Reference Generation, and Voltage Supervision

Table 35: POR, Reference Generation and Voltage/Temperature Supervision, T_J= -40 ºC to

+125 ºC

Test

Conditions

Parameter

Symbol

Min

Typ

Max

Unit

Deep discharge

lockout lower

threshold

VPOR_LOWER

2.0

V

Deep discharge

lockout upper

threshold

VPOR_UPPER

2.3

2.8

±2

V

Under-voltage

lower threshold

VDD_FAULT_LOWER

Note 1

2.5

-1%

3.25

+1%

Under-voltage

lower threshold

accuracy

VDD_FAULT_LOWER

Accuracy

%

Under-voltage

upper threshold

VDD_FAULT_UPPER

Note 2

VDD_FAULT_LOWER

+ VDD_HST_ADJ

V

Reference

voltage

VREF

1.2

2.2

VREF decoupling

capacitor

uF

VLNREF

decoupling

capacitor

2.2

uF

Reference current

resistor

IREF

200

kΩ

Note 1 During production VDD_FAULT_LOWER voltage is configured via OTP over the range 2.5 V to 3.25 V

in 50 mV steps.

Note 2 During production the hysteresis between VDD_FAULT_LOWER and VDD_FAULT_UPPER is

configured via OTP over the range 100 mV to 450 mV in 50 mV steps, the hysteresis can be further

changed through control VDD_HYST_ADJ.

5.16 Thermal Supervision

Parameter

Symbol

Test Conditions

Note 1

Min

110

125

135

Typ

125

140

150

Max

140

155

165

Unit

°C

Thermal warning

Thermal shutdown

Thermal POR threshold

TEMP_WARN

TEMP_CRIT

TEMP_POR

Note 1

°C

Note 1

°C

Note 1 Thermal thresholds are non-overlapping.

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6

Functional Description

The DA9063 provides separate power domains for the host processor, memory, and peripherals to

nable a flexible low-power system design. Multiple low-power modes permit varying combinations of

peripherals to be powered off to conserve battery power. Other system components, such as DRAM

and FLASH memory, RF transceivers, audio codec, and companion chips, are supplied from

optimized regulators designed for dedicated power requirements. The DA9063 power supplies can

be programmed to default voltages via OTP and provide system-configuration flexibility by selecting

the power-up sequence of the regulators and switching converters.

Vdd

nSHUTDOWN

nIRQ

nONKEY

SYS_UP

CHG_WAKE

nVDD_FAULT

Host

processor

PMIC

VSYS

OUT_32K

nRESET

GPIO_0...15

Control IF

Figure 15: Control Ports and Interface

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DA9063

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6.1 Power Manager IO Ports

The power manager input ports are supplied from either the internal rail VDDCORE or VDD_IO2,

selected via PM_I_V. The output ports are supplied from VDD_IO1 or VDD_IO2, selected via

PM_O_V (nVDD_FAULT, GP_FB1 via GPIO controls). During the initial start-up sequence all power

manager IO ports (with the exception of nRESET and nIRQ) are in a high impedance (tri-state) mode

until they are configured from OTP prior to reaching POWERDOWN mode. Output ports are push-

pull except for nRESET and nIRQ, which can also be configured as open-drain via PM_O_TYPE.

The nONKEY and CHG_WAKE signals for the RTC block are supplied from V_DDREF

.

6.1.1

On/Off Port (nONKEY)

The nONKEY signal is a wakeup interrupt/event intended to power-on the application supplied by

DA9063. The level of the debounced signal is provided by status flag nONKEY (asserted at low

level). The nONKEY unit is always enabled so that the application can be powered-on when the

GPIO extender is disabled. The IRQ assertion and wakeup event can be suppressed via the interrupt

mask M_nONKEY.

nONKEY provides four modes of operation selected by field nONKEY_PIN in register CONFIG_I.

Table 36: nONKEY_PIN Settings

nONKEY_PIN

Description

00

An E_nONKEY event is generated when the debounced signal from port nONKEY goes low

(asserting edge). If not masked, an interrupt is signaled to the host via nIRQ (with wakeup

during POWERDOWN mode).

01

10

If (after powering up from POWERDOWN mode) the debounced signal from port nONKEY is

low after an asserting edge for less than the key-press time (selected by KEY_DELAY, default

2 s), an E_nONKEY event is generated at the releasing edge. If the signal is low for longer

than selected by KEY_DELAY, the DA9063 asserts the event E_nONKEY plus control

nONKEY_LOCK when it reaches the selected key-press time.

If (after powering up from POWERDOWN mode) the debounced signal from port nONKEY is

low after an asserting edge for less than the key-press time (selected by KEY_DELAY, default

2 s), an E_nONKEY event is generated at the releasing edge. If the signal is low for longer

than selected by KEY_DELAY, the DA9063 asserts the event E_nONKEY plus control

nONKEY_LOCK when it reaches the selected key-press time and powers down by clearing

control SYSTEM_EN.

11

If (after powering up from POWERDOWN mode) the debounced signal from port nONKEY is

low after an asserting edge for less than the key-press time (selected by KEY_DELAY, default

2 s), an E_nONKEY event is generated at the releasing edge. Control SYSTEM_EN is cleared

and STANDBY asserted, which triggers a partial power down from a short press. If the signal is

low for longer than selected by KEY_DELAY, the DA9063 asserts the event E_nONKEY plus

control nONKEY_LOCK and clear SYSTEM_EN plus STANDBY when it reaches the selected

pressing time (powers down to full POWERDOWN from a long press).

For nONKEY_PIN settings other than ‘00’, the wakeup is not suppressed by an asserted

M_nONKEY. With an asserted nONKEY_LOCK, the wakeup is only executed if the debounced

nONKEY signal is asserted for more than the key-press time (selected by KEY_DELAY, default 2 s).

This behaves similarly to a keypad lock since any short (unintended) pressing of nONKEY does not

wake the application. If the application also has wakeup from a short nONKEY press, the host has to

clear nONKEY_LOCK before entering POWERDOWN mode. In mode ‘10’ when nONKEY key press

is longer than the time selected by KEY_DELAY, SYSTEM_EN is re-asserted in mode ‘11’.

SYSTEM_EN is re-asserted from any consecutive pressing of nONKEY. nONKEY_LOCK is

automatically cleared by the DA9063 when powering up from POWERDOWN mode. POWERDOWN

mode is described in Section 6.2.2.

Note

During RTC/DELIVERY-MODE, the functionality of nONKEY is restricted to a termination of this mode. To

enable this feature, the pull-up resistor of nONKEY has to be connected to V_SYS. Asserting nONKEY stops the

RTC/DELIVERY-MODE and triggers a start-up of the DA9063.

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6.1.2

Wakeup Port (CHG_WAKE)

The CHG_WAKE signal is a rising edge sensitive, wakeup interrupt/event intended to wake the

DA9063 from an event on the companion charger (for example, supply insertion). The CHG_WAKE

port is always enabled so that the application can be powered-on with a disabled GPIO extender.

The IRQ assertion and wakeup event can be suppressed via the interrupt mask M_WAKE. During

RTC/DELIVERY mode, asserting CHG_WAKE terminates this mode.

6.1.3

Hardware Reset (nOFF, nSHUTDOWN, nONKEY, GPIO14, GPIO15,

WATCHDOG)

The DA9063 nOFF port is an active-low input (no debouncing) typically initiated by an asserted error

detection line. It asserts nSHUTDOWN in the fault register. The sequencer asserts port nRESET,

and all domains and supplies of the DA9063 except LDOCORE (and possibly LDO1) are disabled in

a fast emergency shutdown.

The DA9063 nSHUTDOWN port is an active-low input typically asserted from a host processor (or a

push button switch). It asserts nSHUTDOWN in the fault register. The sequencer asserts port

nRESET and then powers down all domains in reverse sequencer order down to slot 0 and all

supplies of the DA9063 except LDOCORE (and possibly LDO1) are disabled. HOST_SD_MODE

determines if normal power sequence timing or a fast shutdown is implemented.

The DA9063 includes a third hardware reset trigger that follows the debounced nONKEY signal after

being asserted for a period greater than KEY_DELAY + SHUT_DELAY. The same can be achieved

by a long parallel connection of GPI14 and GPI15 to ground. The long nONKEY shutdown and

GPIO14/15 shutdown are enabled by the power manager control register bits nONKEY_SD and

GPI14_15_SD.

If the hardware reset was initiated by a (debounced) press of nONKEY (or GPIO14 and GPIO15

together) longer than SD_DELAY, the DA9063 initially only asserts control bit KEY_RESET in the

fault register and signals a non-maskable interrupt allowing the host to clear the armed reset

sequence within 1 s. If the host does not clear KEY_RESET then a shutdown to RESET mode is

executed. KEY_SD_MODE determines if normal power sequence timing or a fast shutdown is

implemented.

The DA9063 then waits for a valid wakeup event (for example, a key press) or starts the power

sequencer automatically if AUTO_BOOT is configured.

If the WATCHDOG has been disabled, this hardware reset can be used to turn off the application in

the event of a software lock-up without removing the battery. This type of reset should only be used

for severe hardware or software problems as it will completely reset the processor and could result in

data loss.

6.1.4

Reset Output (nRESET)

The nRESET signal is an active-low output signal from DA9063 to the host processor that can either

be push-pull or open drain (selected via PM_O_TYPE), which tells the host to enter the reset state.

nRESET is always asserted at the beginning of a DA9063 cold start from NO-POWER, DELIVERY,

and RTC modes. It is asserted in ACTIVE mode before the DA9063 starts powering down to RESET

mode (triggered from user, host, or an error condition detected by the DA9063). nRESET may also

be asserted (depending on nRES_MODE setting) as a soft reset before the sequencer starts

powering down without progressing to RESET mode.

An assertion of nRESET from voltage supervised regulators being out-of-range can be enabled via

control MON_RES (minimum assertion time 1 ms).

After being asserted, nRESET remains low until the reset timer has been started from the selected

trigger signal and expires. The reset release timer trigger signal can be selected via RESET_EVENT

to be EXT_WAKEUP, SYS_UP, PWR_UP, or leaving PMIC RESET state. The expiry time can be

configured via RESET_TIMER from 1 ms to 1 s.

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6.1.5

System Enable (SYS_EN)

SYS_EN is an input signal from the host processor to the DA9063 that enables the regulators in

domain SYSTEM. The feature is enabled using GPIO8_PIN and configured as active-low or -high by

GPIO8_TYPE. It asserts SYSTEM_EN and simultaneously generates an IRQ. It also triggers a

wakeup event in POWERDOWN mode if enabled via GPIO8_WEN. De-asserting SYS_EN (changing

from active to passive state) clears control SYSTEM_EN which triggers a power down sequence into

hibernate/standby mode (without IRQ assertion or wakeup event trigger). By setting nRES_MODE,

the port SYS_EN can be used as a soft reset input with the assertion of nRESET before powering

down. With the exception of supplies that have the xxxx_CONF control bit asserted, all regulators in

power domains POWER1, POWER, and SYSTEM are sequentially disabled in reverse order.

Regulators with the <x>_CONF bit set remain on but change the active voltage control registers from

V<x>_A to V<x>_B (if V<x>_B is not already selected).

The control register bit SYSTEM_EN can also be used to power down domain SYSTEM by a

software command. It can be read and changed via the control interfaces and can be initialized from

OTP when leaving POWERDOWN mode. The DA9063 will not process any changes on port

SYS_EN or register control SYSTEM_EN until the sequencer has stopped processing IDs.

6.1.6

Power Enable (PWR_EN)

PWR_EN is an input signal from the host processor to the DA9063. The input signal can be

configured as active-high or -low via GPIO9_TYPE, and to trigger a wakeup event from

POWERDOWN mode if configured via GPIO9_WEN. Initialization, IRQ assertion and the direct

control via register bit POWER_EN is similar to the function of SYS_EN in domain SYSTEM as

described in Section 6.1.5. To ensure correct sequencing, SYSTEM_EN (SYS_EN) must be active

before asserting PWR_EN/POWER_EN. When de-asserting PWR_EN/POWER_EN, the sequencer

sequentially powers down POWER1 and POWER domains.

6.1.7

Power1 Enable (PWR1_EN)

PWR1_EN is an input signal from a host to the DA9063. The input signal can be configured as

active-high or -low via GPIO10_TYPE, and to trigger a wakeup event in POWERDOWN mode if

enabled via GPIO10_WEN. Initialization, IRQ assertion and the direct control via register bit

POWER1_EN is similar to the function of SYS_EN in domain SYSTEM as described in Section 6.1.5.

POWER1 is a general purpose power domain.

6.1.8

GP_FB1, General Purpose Signal 1 (EXT_WAKEUP/READY)

This port supports two different modes selected by the control PM_FB1_PIN.

Table 37: PM_FB1_PIN Settings

PM_FB1_PIN

Description

0

EXT_WAKEUP. This output signal to the host processor indicates a valid wakeup event during

POWERDOWN mode. External signals that can trigger wakeup events are debounced before

the EXT_WAKEUP signal is asserted. EXT_WAKEUP is released when register control

SYSTEM_EN is asserted (minimum pulse duration = 500 µs).

1

READY. The READY signal indicates on-going DVC or power sequencer activities. The

READY signal is asserted (typically active-low) from the DA9063 power sequencer when the

processing of IDs commences, and is released when the target power state (final sequencer

slot) has been reached. READY is also asserted during DVC voltage transitions.

The active level is configured via the control GPIO13_MODE. The logical threshold voltage is

selected by GPIO13_TYPE.

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6.1.9

GP_FB2, General Purpose Signal 2 (PWR_OK/KEEP_ACT)

The GP_FB2 port supports two different modes selected by the control PM_FB2_PIN.

Table 38: PM_FB2_PIN Settings

PM_FB2_PIN

Description

0

PWR_OK. In this mode the port is a regulator status indicator. The port is an open drain output

asserted if none of the selected regulators are out-of-range. The regulator monitoring via ADC

must be enabled and all regulators to be monitored must have supervision enabled with the

selected persistence, and mask bit M_REG_UVOV must be asserted. In case at least one of

the supervised regulators is out-of-range or regulator monitoring is disabled, the PWR_OK

signal is low.

1

KEEP_ACT. If enabled, every assertion of the port (rising to active level edge sensitive) sets

the watchdog trigger, similar to writing to bit WATCHDOG via the power manager bus. The

host has to release KEEP_ACT before the next assertion during continuous watchdog

supervision (if enabled). The minimum assertion and de-assertion cycle time is 150 µs.

The output active level (and driver type) can be configured via GP_FB2_TYPE.

Alternatively, with BCORE_MERGE = 1, FB in register BCORE1_CFG set to 0b000 and

MERGE_SENSE = 0, the GP_FB2 pin becomes a voltage feedback signal for BUCKCORE.

6.1.10 GP_FB3, General Purpose Signal 3 (OUT32K_2/nVIB_BRAKE)

The GP_FB3 port supports two different modes selected by the control PM_FB3_PIN.

Table 39: PM_FB3_PIN Settings

PM_FB3_PIN

Description

0

1

OUT32K_2. This provides a second 32K signal output (push-pull).

nVIB_BRAKE. If LDO8 is configured as a vibrator motor driver, GP_FB3 can be configured to

provide an external brake signal. The vibrator motor can be started or stopped by a change in

the level on the nVIB_BRAKE signal. If the port is not used as a brake command, the vibration

motor runs continuously at the speed configured by VIB_SET.

GP_FB3_TYPE defines the active level.

6.1.11 Supply Rail Fault (nVDD_FAULT)

nVDD_FAULT is a signal to the host processor to indicate a supply voltage (V_SYS) low status.

Asserting nVDD_FAULT indicates that the main supply input voltage is low

(V_SYS< VDD_FAULT_UPPER) and therefore informs the host processor that the power will shut

down soon. The event control E_VDD_WARN is asserted and the nIRQ line is asserted (if not

masked). During POWER_DOWN mode a wakeup is generated. After that the processor may

operate for a limited time from the remaining battery capacity or the processor may enter a standby

mode. As long as V_SYSdoes not recover, the host can re-enable the nIRQ line by asserting

M_VDD_WARN or clearing E_VDD_WARN. The DA9063 starts a fault power down sequence. If

V_SYSdrops below VDD_FAULT_LOWER, the DA9063 enters RESET mode. The

VDD_FAULT_LOWER threshold and the hysteresis on VDD_FAULT_UPPER are OTP configurable.

The nVDDFAULT port can alternatively be controlled by the state of the debounced V_SYSmonitor

inside the ADC (selected via GPIO12_PIN). The signal is asserted when the ADC detects three

consecutive results below the configurable threshold VSYS_MON (it becomes passive after three

consecutive results above VSYS_MON). This provides a variable power good signal to trigger boot

activities on external ICs.

The active level/debounce, wakeup, and IO supply voltage can be selected via the controls

GPIO12_MODE, GPIO12_WEN and GPIO12_TYPE, respectively.

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6.1.12 Interrupt Request (nIRQ)

The nIRQ is an output signal that can either be push-pull or open drain (selected via PM_O_TYPE).

If an active high IRQ signal is required, it can be achieved by asserting control IRQ_TYPE

(recommended for push-pull mode). This port indicates that an interrupt-causing event has occurred

and that event/status information is available in the EVENT and STATUS registers. Events are

triggered by a status change at the monitored signals. When an event bit is set, the nIRQ signal is

asserted (unless this interrupt is masked by a bit in the IRQ mask register). The nIRQ is not released

until all event registers with asserted bits have been read and cleared. New events that occur during

reading an event register are held until the event register is cleared, ensuring that the host processor

does not miss them. The same happens to all events occurring while the sequencer processes time

slots (that is, the generation of interrupts is delayed).

6.1.13 Real Time Clock Output (OUT_32K)

OUT_32K is a buffered output of the DA9063 32 kHz oscillator. If enabled via CRYSTAL, the 32 kHz

oscillator always runs on the DA9063 following the initial start-up from NO-POWER or DELIVERY

mode until the device has reached NO-POWER (or DELIVERY) mode again. The signal output buffer

can be disabled manually via EN_32KOUT and paused during POWERDOWN mode by setting

OUT32K_PAUSE. The 32K signal can additionally be made available at port GP_FB3.

6.1.14 IO Supply Voltage (VDD_IO1 and VDD_IO2)

VDD_IO1 and VDD_IO2 are two independent IO supply rail inputs of the DA9063 that can be

individually assigned to the power manager interfaces (see control bit GPI_V), power manager IOs

(see control bits PM_O_V, PM_I_V) and GPIOs (bits GPIOx_TYPE). The rail assignment determines

the IO voltage levels and logical thresholds, see Section 5.4. The selection of the supply rail for

GPIOs is also partially used for their alternate functions, see Table 2 and Table 3. As an example,

GPIO13_TYPE determines the supply rail when this pin is configured as the GP_FB1 output.

Note

Maximum speed at 4-WIRE interface is only available if the selected supply rail is greater than 1.6 V, see Table

44.

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6.2 Operating Modes

6.2.1

ACTIVE Mode

A running application is typically in ACTIVE mode. The DA9063 transitions to ACTIVE mode after the

host processor performs at least one initial ‘alive’ watchdog write (or alternatively an initial assertion

of the KEEP_ACT port) inside the target time window. If the WATCHDOG function is disabled by

setting TWDSCALE to zero, the DA9063 transitions to ACTIVE mode when all of the sequencer IDs

in the POWER domain are complete.

In ACTIVE mode, the PMIC core functions as LDOCORE, calendar counter and internal oscillator are

running. Typically additional features are enabled, such as the GPADC. The DA9063 can send

interrupt requests to the host via a dedicated interrupt port (nIRQ) and status information can be read

from the host processor via the power manager interface. Temperature and voltages inside and

outside the DA9063 can be monitored and fault conditions can be flagged to the host processor.

6.2.2

POWERDOWN Mode

The DA9063 is in POWERDOWN mode when the power domain SYSTEM is disabled (even

partially). This can be achieved when progressing from NO-POWER/DELIVERY/RTC mode or by

returning from ACTIVE mode. A return from ACTIVE mode is initiated by low power mode

instructions from the host (for example, releasing signal SYS_EN or clearing register bit

SYSTEM_EN), from the user by asserting nONKEY (if nONKEY_PIN=‘1x’) or as an interim state

during a shutdown to RESET mode.

During POWERDOWN mode LDOCORE, VREF reference voltage, the nONKEY pin, CHG_WAKE

port, and the calendar counter are active. Dedicated power supplies can be kept enabled during

POWERDOWN mode if their xxx_CONF bits are asserted (supply voltage settings are taken from the

respective Vxxx_B registers).

GPIO ports, the GPADC, and the control interfaces also remain active in POWERDOWN mode if not

configured otherwise via register PD_DIS. Disabling these blocks during POWERDOWN mode

reduces quiescent current, especially if all blocks that require an oscillator clock are disabled

(CLDR_PAUSE, HS2WIRE_DIS, PMIF_DIS, GPADC_PAUSE,GPI_DIS, PMCONT_DIS). If required,

the application supervision by the WATCHDOG timer can be continued in POWERDOWN mode via

WATCHDOG_PD. If the host will not communicate with the DA9063 during POWERDOWN mode,

then the control interfaces may also be temporarily disabled (see controls

PMIF_DIS/HS2WIRE_DIS).

If the sequencer pointer has stopped at position PART_DOWN (inside domain SYSTEM) it results in

a partial power down. When on the way down the sequencer pointer reaches position 0, relevant

regulators/rail switches with corresponding position 0 IDs that have cleared control

Bxxx_CONF/LDOxx_CONF/xxx_SW_CONF are disabled, otherwise the regulator voltages change to

the values defined in VBxxx_B/VLDOxx_B when control DEF_SUPPLY is asserted. When

DEF_SUPPLY is released, slot 0 is not processed by the sequencer, hence regulators/rail switches

with an ID pointing to slot 0 remain unchanged. Following the next wakeup event Vxxx_A voltage

levels and the sequencer power domain controls/timers are set to their default OTP values if

OTPREAD_EN is asserted.

Position 0 also allows an automatic transition into a dedicated RTC mode, where all features of the

DA9063 (including LDOCORE) are disabled except for the RTC oscillator and calendar. This mode is

armed via control RTC_MODE_PD and terminated by an RTC alarm/tick asserting

nONKEY/CHG_WAKE, or if V_DDREFrises above 2.6 V, this automatically re-enables LDOCORE and

the full-power manager logic.

If POWERDOWN mode is reached in response to a long nONKEY press, RTC mode is not entered

until the key is released. When nONKEY_SD is asserted and the key is continuously pressed for

longer than the time selected by KEY_DELAY + SHUT_DELAY, it asserts KEY_RESET to indicate

that the transition to RESET mode was triggered by a long nONKEY, see Section 6.1.1.

When the device is in POWERDOWN or RESET mode, asserting ECO_MODE enables low power.

This is achieved internally by using a pulsed mode for VDDCORE and reference voltage generation.

This maintains basic functionality but full parametric compliance is no longer guaranteed (as it affects

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ADC precision, buck performance, LDO voltage resolution, and so on). When the DA9063 is

connected to a 32 kHz crystal (and enabled via control CRYSTAL), the pulsed mode timing is

generated from this source. Otherwise the pulsed mode is driven from a (free-running) low-power on-

chip oscillator.

6.2.3

RESET Mode

The DA9063 is in RESET mode when a complete application shutdown is required. The RESET

mode can be triggered by the user, a host processor or by an action on the DA9063, as outlined

below:

●

By the user:

○

from a long press of nONKEY (interruptible by host)

from a long parallel assertion of GPIO14 and GPIO15 (interruptible by host)

●

By pressing a reset switch connected to port nSHUTDOWN (non-interruptible)

Forced from the host processor (non-interruptible) by:

○

asserting port nSHUTDOWN (falling edge)

writing to register bit SHUTDOWN

●

By an error condition that forces a RESET mode (non-interruptible):

○

no WATCHDOG write (KEEP_ACT signal assertion) from the host inside the watchdog time

window (if watchdog was enabled)

○

an under-voltage detected at V_SYS(V_SYS< VDD_FAULT_LOWER)

an internal die over-temperature

●

Forced by the error detection line (non-interruptible):

by asserting port nOFF (falling edge)

○

The controls INT_SD_MODE, HOST_SD_MODE, and KEY_SD_MODE can be used to individually

configure the shutdown sequences from an internal fault, host or user trigger. In each case, the

sequence can be configured to implement either the reverse timing of the power-up sequence or an

immediate transition into RESET mode, skipping any delay from the sequencer or dummy slot timers.

Asserting nOFF always triggers a fast emergency shutdown. To allow the host to determine the

reason for the reset, the source is recorded in FAULT_LOG (as either the KEY_RESET or

nSHUT_DOWN bit). The host processor clears FAULT_LOG by writing asserted bits with a 1.

Note

●

KEY_SD_MODE = 1 enables a full POR following a long press of ONKEY or a long assertion of GPIO14

and 15.

In the case of an aborted OTP read, the DA9063 enters RESET mode without asserting any bits in

FAULT_LOG.

A shutdown to RESET mode begins with the DA9063 asserting the nRESET port. Then domain

SYSTEM is completely powered down (sequencer position 0) at which time the device has reached

RESET mode: this is a low current consumption state. The only circuits in RESET mode remaining

active are LDOCORE (at a reduced level of 2.2 V), the control interfaces and GPIOs, the calendar

counter, the VREF reference, and the comparators for over-temperature and V_SYSlevel. Except for

LDO1 and the backup battery charger, other regulators and blocks are automatically disabled to

avoid draining the battery. During the DA9063 RESET mode, the host processor can be held in a

RESET state via port nRESET.

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When entering RESET mode, all user and system events are cleared. When leaving RESET mode,

the complete DA9063 register configuration is reloaded from OTP (with the exception of

AUTO_BOOT in case of a VDD_START fault).

Note

FAULT_LOG, GP_ID_10 to GP_ID_19 and other non-OTP loaded registers (for example, RTC calendar and

alarm) remain unchanged when leaving RESET mode.

nRESET is always asserted low after a cold start from NO-POWER, RTC, or DELIVERY mode and can also be

asserted (depending on configuration of nRES_MODE) before the sequencer starts to power down towards

POWERDOWN mode.

Some reset conditions such as shutdown via register write, watchdog error, or over-temperature

automatically expire (that is, are automatically cleared by the device as it shuts down). Other RESET

triggers such as via port nOFF or nSHUTDOWN need to be released before the DA9063 can move

from RESET to POWERDOWN mode. In the case that the application requires regulators to

discharge in advance of a consecutive power-up sequence, a minimum duration of the RESET mode

can be selected via RESET_DUR.

If the reset was initiated by user action from a long nONKEY key-press (or GPI14 and GPI15), bit

KEY_RESET is set and the nIRQ port asserted. After 1 s the shutdown sequence is started, unless

this is inhibited by the host clearing KEY_RESET within this 1 s period (by writing a 1 to the related

bit in register FAULT_LOG). When the RESET condition has been removed, the DA9063 requires

the presence of a good supply (V_SYS> VDD_FAULT_UPPER and able to provide enough power)

before it can start-up again and move into POWERDOWN mode.

RESET mode is also used during an automatic transition by the device into RTC mode, as described

in Section 6.2.4.

6.2.4

RTC Mode

The RTC mode is an ultra-low power mode intended to maintain only the application’s system time

inside the RTC block. It can be armed by asserting control RTC_EN from OTP or host register write.

With RTC_MODE_PD enabled, the device enters RTC mode when the power sequencer reaches

slot 0 in a power down sequence. All regulators (including LDOCORE) and most features on the

DA9063 are disabled. Only the FAULT_LOG register, calendar counter, and their related registers

(including the alarms) are maintained. With RTC_EN = 1, the DA9063 automatically enters RTC

mode when a VDD_FAULT condition is present, when RTC_MODE_SD is asserted, or when V_DDREF

drops below the POR threshold.

RTC mode is automatically terminated when asserting nONKEY or CHG_WAKE, or from an RTC

tick/alarm. The same occurs when V_DDREFhas risen above 2.6 V (for example, from insertion of an

external supply or a pre-charged battery). LDOCORE is then switched on and a start-up sequence is

triggered.

6.2.5

DELIVERY Mode

The DELIVERY mode provides the lowest possible quiescent current, allowing connected pre-

charged batteries (backup or main battery) to maintain charge prior to the end-user starting the

device for the first time. It is armed by setting RTC_EN = 0 and then entered by the same conditions

as RTC mode. During DELIVERY mode, only the nONKEY, CHG_WAKE, and the V_DDREFdetection

circuitry is enabled. Connecting only a backup battery results in DELIVERY mode.

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6.2.6

NO-POWER Mode

In the absence of a (charged) backup battery, the DA9063 enters NO-POWER mode when

VDDCORE drops below the VPOR_LOWER threshold. As long as VDDCORE stays below the

VPOR_UPPER threshold, an internal power-on-reset (nPOR) signal remains asserted. In this mode,

only the VDDCORE threshold comparator is active. This comparator simply checks for a condition

that allows the DA9063 to turn on again. When a good supply is subsequently available again on

V_DDREF(> 2.4 V), VDDCORE is able to rise above VPOR_UPPER and the DA9063 leaves NO-

POWER mode.

6.2.7

Power Commander Mode

This is a special mode for evaluation and configuration development. In Power Commander mode,

the DA9063 is configured to load the control register default values from the HS 2-WIRE interface,

instead of from the OTP cells, so that un-programmed DA9063 samples will power up, allowing

evaluation and verification of a proposed user configuration.

Power Commander mode is enabled by connecting TP to a 3.3 V to 5.0 V voltage.

Note

In Power Commander mode, GPI14 and 15 are configured for HS-2-WIRE interface operation (with VDDCORE

as the supply) and GPO12 is configured as an output for nVDD_FAULT. Any register writes or OTP loads which

can change this configuration are ignored until DA9063 has exited from Power Commander mode.

After leaving the POR state, the DA9063 informs the system that it is waiting for a programming

sequence by driving nVDD_FAULT low. The software running on the PC monitors nVDD_FAULT and

responds by downloading the values into the configuration registers within DA9063. nVDD_FAULT is

automatically released after the download is complete.

There are two programming sequences performed in Power Commander mode. The first takes place

between RESET and POWERDOWN mode and the second between POWERDOWN and SYSTEM

mode.

Note

To correctly configure DA9063, addresses 0x0A to 0x36, 0x82 to 0xCF, and 0x104 to 0x12E should be

programmed during the first sequence. Registers 0x0E, 0x82, and 0xA3 to 0xB3 should be programmed during

the second sequence.

When the first programming sequence is complete, DA9063 will be in POWERDOWN mode.

Progression from this mode is determined by the values programmed for SYS_EN and

AUTO_BOOT. If DA9063 has been directed to progress from POWERDOWN mode then it drives pin

nVDD_FAULT low for a second time to request that the SW performs the second programming

sequence.

Once the second programming sequence is complete, the progress of the power-up sequence is

controlled by the values loaded during the programming sequence.

The programmed configuration can be identified by reading the fuse register CONFIG_ID.

Note

During Power Commander mode, the fault detection status bit VDD_FAULT and the level at the related pin

nVDD-FAULT do not match and do not indicate a low voltage level at VDDOUT. An enabled shutdown from a

5 s assertion of GPIO14/15 will be ignored during POWER Commander mode. Any nIRQ and event assertion

when accessing the HS 2-WIRE interface (E_GPI14) is suppressed in this mode.

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6.3 Start-Up from NO-POWER Mode

6.3.1

Power-On-Reset (nPOR)

The DA9063 generates an internal power-on-reset nPOR (active low) following the initial connection

of a supply to V_DDREF

.

While the VDDCORE voltage is below the threshold VPOR_UPPER, the internal signal nPOR is

driven low and the DA9063 will not start-up. This is NO-POWER mode. When the VDDCORE voltage

rises above VPOR_UPPER, the following occur:

●

The nPOR is driven high (flagged by the POR bit being set in register FAULT_LOG).

The oscillator is enabled.

The VREF reference is enabled.

The complete OTP block is read and stored in the register bank.

The DA9063 progresses into POWERDOWN mode.

From POWERDOWN mode, the DA9063 continues through the power-up sequence if either:

●

the power domain SYSTEM was enabled by the input port, SYS_EN, or,

the power domain SYSTEM was enabled in OTP settings and AUTO_BOOT was enabled.

With AUTO_BOOT disabled and the power domain SYSTEM enabled in OTP settings, a non-

suppressed wakeup event allows the DA9063 to continue through the power-up sequence.

6.4 Exiting Reset Mode and Application Wakeup

DA9063 offers two types of wakeup event, user events and system events (see Table 40). Non-

suppressed user events (for example, nONKEY, CHG_WAKE or from GPIOs) are always processed

and trigger a wakeup.

To exit RESET mode, the DA9063 requires either V_SYSto rise above the threshold

VDD_FAULT_UPPER, or a user event. However, if the previous power-up sequence terminated with

a shutdown to RESET mode that was caused by a VDD_START fault, V_SYSmust rise instead above

the higher threshold of VDD_FAULT_UPPER + 250 mV. If the consecutive power-up sequence is

also terminated with an under-voltage error, this threshold increases further to

VDD_FAULT_UPPER + 500 mV. From then on, AUTO_BOOT and wakeup from non-user events are

temporarily disabled. AUTO_BOOT and wakeup from non-user events are re-enabled after the

application has successfully powered up to ACTIVE mode for a time > 16 s: this also resets the start-

up threshold (to VDD_FAULT_UPPER + 0 mV).

During a VDD_START fault with V_SYS> ~3.7 V, the DA9063 requires a user event to leave the

RESET mode. Until the host has been booted, an OTP-enabled flashing LED may be driven from

GPIO11, 14, or 15 to indicate to the user that the device is supplied with (insufficient) power. When

CHG_WAKE is connected to a charger, the VDDSTART-triggered LED flashing continues as long as

an external supply is charging the battery. The flashing LED can be configured via controls

RESET_BLINKING, BLINK_DUR, and BLINK_FRQ. After the application is running, the blinking LED

can be stopped via a host register write.

Wakeup events can be individually suppressed by setting the related nIRQ mask bit. When

nONKEY_LOCK is asserted a wakeup requires the debounced signal from nONKEY to be low for a

time longer than the configured KEY_DELAY. It is not recommended to mask system events, instead

disable the unwanted event sources (for example, GPIs, GPADC, 1.2 V comparator). The wakeup

from GPIOs (or selected alternate features that use a shared GPI event) has to be enabled via

GPI<x>_WEN.

After a valid wakeup condition is detected, a subset of the OTP configuration is read and the values

are used to reconfigure the regulator voltage registers Vxxx_A, the power domain enable settings (if

not suppressed via SYSTEM_EN_RD) and the sequencer timer.

DA9063 then asserts the EXT_WAKEUP signal towards the host processors and configures

regulators with an ID pointing at slot 0 to their target state. If the power domains are not pre-enabled

from OTP settings, the host processor must control further application start-up (via the power domain

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enable ports, SYS_EN, PWR_EN and PWR1_EN). Alternatively the DA9063 continues powering-up

the OTP-enabled domains via the power domain sequencer, but the power sequencer will not start to

enable the system supplies unless SYSTEM_EN is asserted.

Progression to ACTIVE mode requires assertion of POWER_EN from the host via port PWR_EN, a

register write, or enabled in OTP. After starting the WATCHDOG timer the host processor must

assert the WATCHDOG bit within the configured time window. If this does not happen, the state-

machine terminates ACTIVE mode and returns to RESET mode.

Table 40: Wakeup Events

Signal : Event

Wakeup

User

Event

System

Event

IRQ

V_SYSmonitor : E_VDD_MON

VDD_FAULT pre-warning : E_VDD_WARN

RTC alarm : E_ALARM

X

RTC periodic tick : E_TICK

Voltage comparator flipped : E_COMP1V2

Pressed On key : E_nONKEY

X

Wakeup from companion charger : E_WAKE

LDO over current detect : E_LDO_LIM

Regulator voltage out-of-range : E_REG_UVOV

Critical junction temperature : E_TEMP

Power sequencing ready : E_SEQ_RDY

Voltage ramping ready : E_DVC_RDY

Manual ADC result ready : E_ADC_RDY

GPIOs passive to active transition : E_GPIx

ADC 1, 2, 3 threshold : via GPI0, 1, 2

X

SYS_EN, PWR_EN, PWR1_EN (passive to active transition) :

via GPIO8, 9, 10

HS-2-WIRE interface : via GPIO14

X

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6.5 Power Supply Sequencer

The DA9063 power supplies are enabled with a sequencer that contains a programmable step timer,

a programmable ID array of slot pointers, and four predefined pointers (SYSTEM_END,

POWER_END, MAX_COUNT, and PART_DOWN), as illustrated by Figure 16. The sequencer is

able to control up to 32 IDs (six bucks, 11 LDOs, 7 external FET/IC controls, a Wait ID (GPI10), an

EN_32K enable, and an ID to activate power down settings), which can be grouped to three power

domains.

The power domains have configurable size and their borders are described by the location pointers

SYSTEM_END, POWER_END, and MAX_COUNT.

The lowest level power domain SYSTEM starts at step 1 and ends at the step that is described by

the location pointer SYSTEM_END. The second level domain POWER starts at the successive step

and ends at POWER_END. The third level domain POWER1 starts at the consecutive step and ends

at MAX_COUNT. The values of pointer SYSTEM_END, POWER_END, and MAX_COUNT are

predefined in OTP registers and should be configured as SYSTEM_END < POWER_END <

MAX_COUNT.

The domain system can be thought of as the minimum set of supplies required to enable the core of

the target system.

If the control OTPREAD_EN is enabled, the regulator voltages, sequence domain enables (if not

suppressed via control SYSTEM_EN_RD), and the sequence timer are reset to their OTP values

during the transition from power down to system.

The second level domain POWER includes supplies that are required on top to trigger the application

and set the DA9063 into ACTIVE mode. POWER1 can be understood as one of the POWER

domains that can be used for further sequenced control of supply blocks during ACTIVE mode (for

example, for a sub-application like WLAN or a baseband chipset).

Note

It is recommended that the system is configured to reach ACTIVE mode before running applications.

6.5.1

Powering Up

All buck converters and 11 LDOs of DA9063 have a unique sequencer ID. The power-up sequence is

defined by an OTP register bank that contains a series of supplies (and other features), each of

which point to a selected sequencer time slot. Several supplies can point to the same time slot which

is therefore enabled in parallel by the sequencer. Time slots that have no IDs pointing at them are

dummy steps that do nothing but insert a configurable time delay (marked in Figure 16 as D).

Supplies/IDs that do not point to a sequencer time slot between 1 and MAX_COUNT are not enabled

by the power sequencer but can be controlled individually by the host (via the power manager

interface).

During power-up, the sequencer starts at slot 0. If DEF_SUPPLY is asserted, it checks all

regulators/rail switches for an ID pointing to slot 0. Cleared LDOxx_AUTO/

BUCKxxx_AUTO/xxx_SW_AUTO bits are configured by setting the related control

Bxxx_CONF/LDOxx_CONF/xxx_SW_CONF, otherwise the regulator is enabled. To minimize inrush

currents, it is recommended to enable no more than a single default regulator via DEF_SUPPLY.

During power-up, the regulator output voltage is taken from the VBxxx_A/VLDOxx_A registers.

During power-down, regulators/rail switches with a cleared control in Bxxx_CONF/LDOxx_CONF/

xxx_SW_CONF are disabled, otherwise the regulator voltage is changed to VBxxx_B/VLDOxx_B

when entering slot 0. When DEF_SUPPLY is released, slot 0 is not processed by the sequencer

(regulators/rail switches with an ID pointing at slot 0 remain unchanged).

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The progression of the sequencer to slot 1 is dependent on certain conditions:

●

If AUTO_BOOT and SYSTEM_EN are both asserted (via port, by register write or in OTP), the

sequencer asserts the READY signal (if GP_FB1 is so configured) and then continues by

processing slot 1.

●

If AUTO_BOOT is not asserted, the sequencer remains in a holding start state, waiting for either:

○

the assertion of SYSTEM_EN, or,

any other wakeup event if SYSTEM_EN is already enabled.

All supplies (and other sequenced features) that are pointing at slot 1 are then processed. This is

similar to the processing of slot 0 with the exception that DEF_SUPPLY has no effect on slots apart

from slot 0. From slot 1, the sequencer progresses until it reaches the position of pointer

SYSTEM_END. At this point, all IDs of the first power domain SYSTEM are enabled and, if

POWER_EN is not asserted, the DA9063 releases the READY signal (in combination with optional

assertion of E_SEQ_RDY).

Power Domain

Slot Timer

Programmable

4 bit OTP

Start/Stop

SYSTEM

POWER

POWER1

SYSTEM_END

PART_DOWN

POWER_END

MAX_COUNT

STAND_BY

Sequencer

Slot ID

counter

2

3

1

D

0

5

D

7

D

10

D

13

D

14 15

Slot ID

definition

...

Figure 16: Assignment of Actions to Sequencer Slot IDs

Table 41: Power Sequencer Controlled Actions

Action

Sequencer Time Slot

LDO1_STEP

Control LDO1

Control LDO2

LDO2_STEP

Control LDO3

LDO3_STEP

Control LDO4

LDO4_STEP

Control LDO5

LDO5_STEP

Control LDO6

LDO6_STEP

Control LDO7

LDO7_STEP

Control LDO8

LDO8_STEP

Control LDO9

LDO9_STEP

Control LDO10

LDO10_STEP

LDO11_STEP

BUCKCORE1_STEP

BUCKCORE2_STEP

BUCKPRO_STEP

BUCK_IO_STEP

Control LDO11

Control BUCKCORE1

Control BUCKCORE2

Control BUCKPRO

Control BUCKIO

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Action

Sequencer Time Slot

BUCKMEM_STEP

BUCKPERI_STEP

CORE_SW_STEP

BUCKPERI_STEP

GP_RISE1_STEP

GP_FALL1_STEP

GP_RISE2_STEP

GP_FALL2_STEP

GP_RISE3_STEP

GP_FALL3_STEP

GP_RISE4_STEP

GP_FALL4_STEP

GP_RISE5_STEP

GP_FALL5_STEP

WAIT_STEP

Control BUCKMEM

Control BUCKPERI

Control CORE_SW

Control PERI_SW

Assert/Release GPIO2

Release/Assert GPIO2

Assert/Release GPIO7

Release/Assert GPIO7

Assert/Release GPIO8

Release/Assert GPIO8

Assert/Release GPIO9

Release/Assert GPIO9

Assert/Release GPIO11

Release/Assert GPIO11

Wait for active state at GPI 10

Wait for stable oscillator signal

PD_DIS

EN32K_STEP

PD_DIS_STEP

On completion of domain SYSTEM, the sequencer waits for POWER_EN to be asserted (via the

PWR_EN port, a register write or in OTP). When POWER_EN is asserted, the signal READY is

asserted (if not already asserted) and regulators/IDs of domain POWER are enabled sequentially.

The sequencer stops at the position of pointer POWER_END. At this point it also: releases the

READY signal (if POWER1_EN is not asserted); optionally asserts E_SEQ_RDY; enables the initial

WATCHDOG timer and waits for the first associated alive feedback from the host processor. After

this, the start-up of the DA9063 progresses into ACTIVE mode.

A third power domain, POWER1, can be enabled via POWER1_EN (asserted by PWR1_EN port,

register write or in OTP). It enables all consecutive IDs until the position of pointer MAX_COUNT has

been reached. The READY signal is asserted as long as IDs are processed (if enabled) and

E_SEQ_RDY is asserted when reaching MAX_COUNT.

On start-up, and if OUT_CLOCK is asserted, the sequencer waits at a slot containing ID

EN32K_STEP until the 32 kHz clock stabilizes, see Section 6.14.1.1.

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6.5.2

Power-Up Timing

nPOR_UPPER

VDDREF

VDD_FAULT_UPPER

VSYS

Registers Loaded From OTP

VDDCORE

nVDD_FAULT

nONKEY

Debouncing

(10ms

default)

EXT_WAKEUP

SYSTEM_EN

POWER_EN

POWER1_EN

Wait for PWR_EN

SEQ1

Wait for PWR1_EN

SEQ2

Wait for SYS_EN

SEQ1+SEQ2+SEQ3=15step

POWER-UP

SEQ3

SYS_UP (int)

PWR_UP (int)

1ms to 1s

nRESET

Start Reset Time

Figure 17: Power-Up Timing

6.5.3

Programmable Slot Delays

The delay between the slots of a sequence is controlled via the programmable value of SEQ_TIME in

register SEQ_TIMER. This has a default delay of 128 µs per slot (min. 32 µs, max. 8 ms). The delay

time between individual supplies can be extended by leaving a consecutive slot(s) with no IDs

pointing to it: these are dummy slots. The dummy slots have an independent delay configured by

SEQ_DUMMY. These delay times, in register SEQ_TIMER, are (re-)loaded from OTP every time

domain SYSTEM begins to power-up.

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6.5.4

Powering Down

When the DA9063 is powering down, the sequencer disables the supplies in reverse order and

timing, asserts READY during sequencing, and triggers E_SEQ_RDY on reaching the target

sequencer slot. Supplies that are configured to stay on (LDO<x>_CONF, B<x>_CONF,

xxx_SW_CONF bit is set) are not disabled and are configured with the voltage setting from register

VB<x>_B/VLDO<x>_B when the related time slot/ID is processed. The state of the regulators that

are enabled for GPI control will not be changed by the sequencer when processing the related ID.

This also applies for the selection of the related V<x>_A or V<x>_B voltage control register in case a

regulator is enabled for GPI voltage selection.

If powering down is initiated by clearing POWER1_EN, the sequencer stops controlling IDs before

the domain pointer POWER_END is reached. If POWER_EN is cleared, the domain POWER1 is

powered down followed by POWER before the sequencer reaches pointer SYSTEM_END. These

modes are used to temporarily disable optional features of a running application for reduced power

(sleep mode).

If SYSTEM_EN is cleared the sequencer processes all IDs lower than the pointer position down to

slot 0. The sequencer can be forced to stop the intended power down sequence prior to maturity at

pointer position PART_DOWN via an asserted control STANDBY (PART_DOWN has to point into

domain SYSTEM). In these cases the power sequencer has reached the application’s

POWERDOWN mode (hibernate/standby), which enables the option to reset regulator settings for

the consecutive power-up sequence from OTP (enabled by OTPREAD_EN).

Wakeup events are enabled when the sequencer reaches slot 0 or pointer PART_DOWN (ignored

outside of POWERDOWN mode). The assertion of nIRQ from events during POWERDOWN mode

may be delayed until ACTIVE mode is reached the next time if configured by nIRQ_MODE. During

processing slot 0, all supplies pointing into this step with a cleared control

Bxxx_CONF/LDOxx_CONF/xxx_SW_CONF are disabled, otherwise the regulator voltage is changed

to VBxxx_B/VLDOxx_B (if bit DEF_SUPPLY is asserted). Asserting control register bit SHUTDOWN

first powers down to slot 0 and then forces the DA9063 into RESET mode. Autonomous features

such as the 32K output buffer or the Auto-ADC measurement can be disabled temporarily for

POWERDOWN mode via register PD_DIS. The timing for processing PD_DIS can be defined by

selecting a step inside the sequence. Features asserted in PD_DIS are (re-)enabled when PD_DIS is

processed during a power-up sequence.

Control nRES_MODE enables the assertion of nRESET before executing a power-down sequence

and starting the reset timer during the consecutive powering up. This is also true for partial

POWERDOWN mode, when the sequencer powers down to pointer position PART_DOWN. The

reset timer starts to run from the selected RESET_EVENT and releases the nRESET port after the

reset timer expires.

6.5.5

User Programmable Delay

A conditional mode transition can be achieved using ID WAIT_STEP. If pointing into the power

sequence the progress of an initiated mode transition can be synchronized, for example with the

state of a host. This is indicated by toggling the signal at GPI10 to its configured active state. A safety

timeout of 500 ms can be selected in TIME_OUT to trigger a power-down to RESET mode (including

the assertion of WAIT_SHUT inside register FAULT_LOG) if E_GPI10 is not asserted in time. The ID

WAIT_STEP provides an alternate timer mode, selected by WAIT_MODE and configured by

WAIT_TIME, which provides a delay timer for a selected sequencer step. To enable symmetric

sequence behavior, ID WAIT_STEP should not share a sequencer slot with other IDs. In the case of

a shutdown sequence to RESET mode any waiting/delay at ID WAIT_STEP is skipped.

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Figure 18: Power Mode Transitions

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6.6 System Monitor (Watchdog)

After powering up domain POWER, the DA9063 can initiate a watchdog monitor function. The host

processor must write a 1 within a configured TWDMAX time into control WATCHDOG, thereby

indicating that the host is alive. If the host does not write 1 to this watchdog bit within the TWDMAX

time, the DA9063 asserts TWD_ERROR in the FAULT_LOG register and powers down to RESET

mode.

After this first write, the host must continue to write to this watchdog bit within the configured time or

DA9063 powers down as described above. The time window has a minimum time TWDMIN fixed at

256 ms and a maximum time TWDMAX, nominally 2.048 s. The TWDMAX value can be extended by

multiplying the nominal TWDMAX by the value of register bits TWDSCALE. TWDSCALE is used to

extend the TWDMAX time by x1, x2, x4, x8, x16, x32, or x64.

Once in the ACTIVE state, the DA9063 continues to monitor the system unless it is disabled by

setting TWDSCALE to zero. When powering down from ACTIVE mode, the watchdog monitor is

stopped unless it enters POWERDOWN mode via WATCHDOG_PD.

If the WATCHDOG register bit is set to a 1 within the time window, the watchdog monitor resets the

timer, sets the watchdog bit back to zero (this bit is always read as zero) and waits for the next

watchdog signal. The watchdog trigger can also be asserted from the host by asserting KEEP_ACT

in hardware. This mode is selected with control PM_FB2_PIN and removes the above requirement

for the periodic setting of the watchdog bit.

The watchdog feature can be disabled by setting TWDSCALE to zero.

6.7 GPIO Extender

The DA9063 includes a GPIO extender that provides up to 16 V_DDREF-tolerant general purpose

input/output ports, each controlled via registers from the host, see Table 42 and Figure 19.

The GPIO ports are pin-shared with ports from GPADC, HS-2-WIRE-interface and signals from the

power manager. Configuration settings and events from GPIx ports are also shared with alternative

features. For example, if GPIO1_PIN is configured to be ADCIN2, exceeding the configured ADC

thresholds triggers a GPI1 event that generates a maskable GPI1 interrupt. The GPI active High/Low

setting from the GPIOx_TYPE register and the selection of pull-up resistor is also applicable to the

alternative port functions selected via GPIOx_PIN (for example, SYS_EN, PWR_EN and

PWR1_EN). This is also true for GPIOx_WEN, which is used to enable triggering of a wakeup event

(ADCIN1, ADCIN2, ADCIN3, SYS_EN, PWR_EN, PWR1_EN, HS-2-WIRE interface). When GPI

ports are enabled (including being enabled by changing the setting of GPIOx_PIN), the GPI status

bits are set to their non-active state. This ensures that any signals that are already active are

detected and immediately generate any appropriate events.

In ACTIVE and POWERDOWN mode, the GPIO extender can continuously monitor the level of ports

that are selected as general purpose inputs. GPIs are supplied from the internal rail VDDCORE or

VDD_IO2 (selected via GPI_V) and can be configured to trigger events in active-high or active-low

mode. The input signals can optionally be debounced (configurable via control DEBOUNCING,

10 ms default) and the resulting signal level is reflected by the status register GPIx. When the status

has changed to its configured active state (edge sensitive) the assigned event register is set and the

nIRQ signal is asserted (unless this nIRQ is masked). GPIs can be individually configured to

generate a system wakeup via GPIxx_WEN.

If enabled via regulator controls LDOx_GPI/Bxxx_GPI, the ports GPI1, GPI2, and GPI13 can be used

to enable/disable regulators or rail switches (that is, controlling LDOx_EN/Bxxx_EN/xxx_SW_EN).

The GPI active level is selected via the related GPIxx_TYPE control. GPI ports that are selected for

this hardware control of one or more regulators do not generate events (nIRQ). GPI1, 2, and 13 can

alternatively be selected to toggle the VLDOx_SEL/VBxxxx_SEL. Apart from changing the regulator

output voltage, this feature also allows hardware control of regulator mode (sync/sleep mode) via

selection of the settings contained in xxxx_SL_A and xxxx_SL_B (but only for those bucks configured

with Bxxxx_MODE = 00). When a regulator is controlled via GPI, its enable and voltage register

selection are no longer controlled by the power sequencer (processing the related ID only affects

non-GPI controlled functionality). However, these settings can still be changed via register writes

from the control interface.

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Events on GPI10 can be used to control the progress of the power sequencer. Processing ID

WAIT_STEP causes the sequencer to wait until GPI10 changes into its active state.

Note

Supplies directly enabled/disabled from GPI1, 2, or 13 have to be excluded from the power sequencer control

(IDs of these supplies should point into a slot higher than MAX_COUNT)

If defined as an output, GPO0, 1, 3 to 6, 10 to 11, and 13 to 15 can be configured to be open-drain

instead of push-pull. The supply rail can be individually selected from either VDD_IO1 or VDD_IO2.

By disabling the internal 120 kΩ pull-up resistor when in open-drain mode, the GPO can also be

supplied from an external rail (see registers CONFIG_K and CONFIG_L). The GPO output state

reflects the respective register bit GPIOx_MODE.

When configured as outputs, GPO 2, 7, 8, 9, and 11 can be controlled by the DA9063 power

sequencer. Five pairs of level asserting and level releasing IDs (GP_RISE1_STEP/

GP_FALL1_STEP to GP_RISE5_STEP/GP_FALL5_STEP) may be assigned individually to slots of

the power sequencer, which trigger the configured level transition on the GPOs when processing the

related ID during powering up (see Table 41 for assignments). The configured level change is

inverted when processing the IDs during powering down. These are intended for use as enable

signals either for external regulators or other devices in the system.

When the GPIO unit is off (POR), all ports are configured as open drain output with high level (pass

device switched off, high impedance state). When leaving POR, the pull-up or pull-down resistors are

configured from registers CONFIG_K and CONFIG_L. When the GPIO unit is temporarily disabled by

the power sequencer (via GPI_DIS or PMCONT_DIS) level transitions on inputs are no longer

detected and I/O drivers keep their configuration and programmed levels.

GPO12 can be driven by the state of VDD_MON to provide an active high ‘Power good’ signal

(selected via GPIO12_PIN).

GPO10, 11, 14, and 15 are extended power GPO ports, where the maximum sink current is 11 mA

and the maximum source current is 4 mA. This enables driving LEDs. The output ports GPO11,

GPO14, and GPO15 can be toggled with a configurable periodic pulse configured via BLINK_FRQ

and BLINK_DUR and include an optional PWM control. The generated PWM signals have a duty

cycle from 0 % to 100 % with a repetition frequency of 21 kHz and 95 steps (using one 2 MHz clock

for each step). The duty cycle is set by the controls GPO11_PWM, GPO14_PWM, and

GPO15_PWM, with any value larger than 0 enabling the PWM mode of operation. The PWM control

can also be made to dim the brightness between its current value and a new value at a rate of 32 ms

per step. Selection of this mode is set by GPO11_DIM, GPO14_DIM, and GPO15_DIM. When set to

zero the PWM ratio immediately changes. This creates a common anode tricolor LED brightness

control. Flashing is driven from the crystal oscillator when control CRYSTAL has been asserted;

otherwise an auxiliary on-chip oscillator is used.

LEDs are recommended to be low-side driven (using the GPIOs in sink mode) which is configured by

setting GPIOx_MODE = 1.

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DA9063

System PMIC for Mobile Application Processors

Table 42: GPIO Overview

GPIO Alternate Port

Alternate Port Shared

Resources

GPI Wakeup

Remark

Auto measure ADC

Auto measure ADC/1.2V

0

1

ADCIN1

ADCIN2

E_GPI0, M_GPI0,

GPIO0_MODE

x

E_GPI1, M_GPI1,

GPIO1_MODE

Regulator control

x (in other modes) comparator, HW control of

regulator

2

ADCIN3

E_GPI2, M_GPI2,

GPIO2_MODE

Regulator control

x (in other modes) control of regulator/ power

sequencer controlled GPO

Auto measure ADC, HW

3

4

5

6

7

8

CORE_SWG

CORE_SWS

PERI_SWG

PERI_SWS

x

Power sequencer controlled

ext. FET

Power sequencer controlled

ext. FET voltage sense

Power sequencer controlled

ext. FET

Power sequencer controlled

ext. FET voltage sense

Power sequencer controlled

GPO

SYS_EN

PWR_EN

PWR1_EN

E_GPI8, M_GPI8,

GPIO8_TYPE, GPIO8_WEN,

GPIO8_MODE

Power sequencer controlled

GPO

9

E_GPI9, M_GPI9,

GPIO9_TYPE, GPIO9_WEN,

GPIO9_MODE

x

Power sequencer controlled

GPO

10

E_GPI10, M_GPI10,

GPIO10_TYPE,

GPIO10_WEN,

High power GPO, input signal

for ID WAIT

GPIO10_MODE

11

12

x

High power GPO (LED

flashing/PWM), Power

Sequencer controlled GPO

nVDD_FAULT

GPIO12_TYPE,

GPIO12_WEN,

GPIO12_MODE

VDD_MON state controlled

GPO (POWER_GOOD)

13

14

GP_FB1

DATA

GPIO13_TYPE,

GPIO13_MODE

Regulator control

x (in other modes)

HW control of regulator

E_GPI14, M_GPI14,

GPIO14_TYPE,

GPIO14_MODE

x

High power GPO (LED

flashing/PWM), Reset via long

assertion in parallel with

GPI15, 2nd 2-WIRE or DVC

Control Interface

15

CLK

x

High power GPO (LED

flashing/PWM), Reset via long

assertion in parallel with

GPI14, 2nd 2-WIRE or DVC

Control Interface

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DA9063

System PMIC for Mobile Application Processors

GPIO_0_WEN:

on/off

Interrupt mask:

M_GPI_0

GP-ADC_SEQ ADCIN4_I_EN

15 uA

Wake-up

OR

GPIO_0_MODE:

Debounce on/off

GPIO_0_TYPE:

Active high/low

AND

...

2x true

(same limit)

AUTO4_LOW

AUTO4_HIGH

GP-ADC

Status register

GPI_0

Event register

Comparator

NOR

OR

E_GPI_0

Reset

ADCIN4

Rising or

Falling edge

Debounce

GP-ADC_SEQ

nIRQ

NOR

GPI

VDDIO2

VDDIO1

GPIO_0_PIN

...

Event register write

GPIO_0_TYPE:

VDDIO selection

GPIO0_PUPD

100kΩ

120kΩ

GPO (Open drain)

VDDIO1

VDDIO2

GPO_0_MODE:

0 or 1

GPIO_0_TYPE:

VDDIO selection

GPO (Push-pull)

VDDIO1 VDDIO2

GPIO_13_TYPE:

...

VDDIO selection

GPIO13_PUPD

120kΩ

GPIO_13_WEN:

on/off

Interrupt mask:

M_GPI_13

VDDIO1 VDDIO2

Status of

GP_FB1:

GPIO_13_TYPE:

VDDIO selection

GPIO_13_TYPE:

Active high/low

AND

Event register

Status register

GPI_13

No regulator HW

control

NOR

E_GPI_13

Reset

GPIO_13_MODE:

Debounce on/off

GP_FB1

Rising or

Falling edge

Debounce

GPIO_13_PIN

Event register write

GPI

Regulator HW control

GPIO13_PUPD

Regulator

configure

100kΩ

GPI_13

XOR

xxxx_ EN

Rising and

Falling edge

VDDIO1 VDDIO2

GPIO_13_TYPE:

VDDIO selection

GPIO_13_TYPE:

Active high/low

GPO (Push-pull)

GPO_13_MODE

0 or 1

...

Figure 19: GPIO Principal Block Diagram (Example Paths)

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DA9063

System PMIC for Mobile Application Processors

6.8 Control Interfaces

The DA9063 is register controlled by the host software. The DA9063 offers two independent serial

control interfaces to access these registers (Figure 20). The communication via the main power

manager interface is selected via control IF_TYPE during the initial OTP read to be either a 2- or 4-

WIRE connection (I²C respective SPI compliant). The alternate interface is a fixed 2-WIRE bus. Data

is shifted into or out from DA9063 under the control of the host processor that also provides the serial

clock. The interfaces are usually only configured once from OTP values, which are loaded during the

initial start-up. The interface configuration can be changed by the host. However, care must be taken

that changes are not made while the interface is active. If enabled, IF_RESET forces a reset of all

control interfaces when port nSHUTDOWN is asserted.

6.8.1

Power Manager Interface (4- and 2-WIRE Control Bus)

This is the dedicated power control interface from the primary host processor. In 4-WIRE mode, the

interface uses a chip-select line (nCS/nSS), a clock line (SK), a data input (SI), and a data output line

(SO).

6.8.1.1

4-WIRE Communication

In 4-WIRE mode, the DA9063 register map is split into four pages with each page containing up to

128 registers. The register at address zero on each page is used as a page control register. The

default active page after reset includes registers 0x01 to 0x7F. Writing to the page control register

changes the active page for all subsequent read/write operations unless an automatic return to page

0 was selected by asserting control REVERT. Unless REVERT was asserted after modifying the

active page it is recommended to read back the page control register to ensure that future data

exchange accesses the intended registers.

The 4-WIRE interface features a half-duplex operation (data can be transmitted and received within a

single 16-bit frame) with an enhanced clock speed (up to 14 MHz). It operates at the provided host

clock frequencies.

VDDIO

SK

Host

processor

VDDIO

SK

SI

SO

SI

PMIC

(slave)

Host

processor

VDDIO

SK

SI Peripheral

device

nCS/nSS

SCL

SDA

SO

nCS/nSS

PMIC

VDDIO

SK

SI

SO

4-WIRE interface

2-WIRE interface

SCL

SDA

Slave device

Peripheral

device

nCS/nSS

Figure 20: Schematic of 4- and 2-WIRE Power Manager Bus

A transmission begins when initiated by the host. Reading and writing is accomplished using an 8-bit

command, which is sent by the host prior to the exchanged 8-bit data. The byte from the host begins

shifting in on the SI pin under the control of the serial clock SK provided from the host. The first 7 bits

specify the register address (0x01 to 0x7F) to be written or read by the host. The register address is

automatically decoded after receiving the seventh address bit. The command word ends with a R/W

bit which, together with the control bit R/W_POL, specifies the direction of the next data exchange.

During register writing, the host continues sending out data during the following 8 SK clocks. For

reading, the host stops transmitting and the 8-bit register is clocked out of the DA9063 during the

consecutive 8 SK clocks of the frame. Address and data are transmitted MSB first. The polarity

(active state) of nCS is defined by control bit nCS_POL. nCS resets the interface when inactive and it

must be released between successive cycles.

The SO output from DA9063 is normally in a high-impedance state and active only during the second

half of read cycles. A pull-up or pull-down resistor may be needed on the SO line if a floating logic

signal can cause unintended current consumption inside other circuits.

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DA9063

System PMIC for Mobile Application Processors

Table 43: 4-WIRE Clock Configurations

CPOL Clock Polarity

CPHA Clock Phase

Output Data is Updated Input Data is Registered

at SK Edge

0 (idle low)

1 (idle high)

0

1

0

1

falling

rising

falling

rising

falling

rising

The DA9063 4-WIRE interface offers two further configuration bits. Clock polarity (CPOL) and clock

phase (CPHA). CPOL determines whether SK idles high (CPOL = 1) or low (CPOL = 0). CPHA

determines on which SK edge, data is shifted in and out. With CPOL = 0 and CPHA = 0, the DA9063

latches data on the SK rising edge. If CPHA = 1, the data is latched on the SK falling edge. The

CPOL and CPHA states allow four different combinations of clock polarity and phase; each setting is

incompatible with the other three. The host and DA9063 must be set to the same CPOL and CPHA

states to communicate with each other.

4-WIRE WRITE

nCS

SK

A₆

A₅

A₄

A₃

A₂

A₁

A₀

R/Wn

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

SI

SO

4-WIRE READ

nCS

SK

SI

A₆

A₅

A₄

A₃

A₂

A₁

A₀

R/Wn

HI-Z

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

SO

latch data

Figure 21: 4-WIRE Host Write and Read Timing (Ncs_POL = 0, CPOL = 0, CPHA = 0)

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DA9063

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4-WIRE WRITE

nCS

SK

A₆

A₅

A₄

A₃

A₂

A₁

A₀

R/Wn

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

SI

SO

4-WIRE READ

nCS

SK

SI

A₆

A₅

A₄

A₃

A₂

A₁

A₀

R/Wn

HI-Z

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

SO

latch data

Figure 22: 4-WIRE Host Write and Read Timing (Ncs_POL = 0, CPOL = 0, CPHA = 1)

4-WIRE WRITE

nCS

SK

SI

A₆

A₅

A₄

A₃

A₂

A₁

A₀

R/Wn

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

SO

4-WIRE READ

nCS

SK

SI

A₆

A₅

A₄

A₃

A₂

A₁

A₀

R/Wn

HI-Z

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

SO

latch data

Figure 23: 4-WIRE Host Write and Read Timing (Ncs_POL = 0, CPOL = 1, CPHA = 0)

Datasheet

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DA9063

System PMIC for Mobile Application Processors

4-WIRE WRITE

nCS

SK

A₆

A₅

A₄

A₃

A₂

A₁

A₀

R/Wn

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

SI

SO

4-WIRE READ

nCS

SK

SI

A₆

A₅

A₄

A₃

A₂

A₁

A₀

R/Wn

HI-Z

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

SO

latch data

Figure 24: 4-WIRE Host Write and Read Timing (Ncs_POL = 0, CPOL = 1, CPHA = 1)

Table 44: 4-WIRE Interface Summary

Parameter

Description

Chip select

nCS

SI Serial input data

SO Serial output data

SK

Master out, Slave in

Master in, Slave out

Transmission clock

Signal Lines

Interface

Supply voltage

Data rate

Push-pull with tri-state

Selected from VDD_IO1 / VDD_IO2

Effective read/write data

Half-duplex

1.6 to 3.3 V

Up to 7 Mbps

MSB first

Transmission

16-bit cycles

7-bit address, 1-bit read/write, 8-bit data

clock polarity

CPOL

Configuration

CPHA

clock phase

nCS_POL

nCS active-low / -high

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DA9063

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6.8.1.2

2-WIRE Communication

With control IF_TYPE = 1, the DA9063 power manager interface is configured for 2-WIRE serial data

exchange. It has a configurable device address IF_BASE_ADDR (default read address: 0xB0, write

address 0xB1). For details of configurable addresses, see control IF_BASE_ADDR in Section A.4.2.

In 2-WIRE mode, SK is the clock (CLK) and SI is data (DATA). The 2-WIRE interface is open-drain,

supporting multiple devices on a single line. The bus lines must be pulled high by external pull-up

resistors (2 kΩ to 20 kΩ). The attached devices only drive the bus lines low by connecting them to

ground. As a result, two devices cannot conflict if they drive the bus simultaneously. In standard/fast

mode, the highest frequency of the bus is 400 kHz. The exact frequency can be determined by the

application and does not have any relation to the DA9063 internal clock signals. The DA9063 follows

the host clock speed within the described limitations and does not initiate any clock arbitration or

slow down. Control TWOWIRE_TO enables an automatic interface RESET that is triggered when the

clock signal ceases to toggle for >35 ms (compatible with SMBus T_TIMEOUT).

The interface supports operation compatible with Standard, Fast, Fast-Plus and High Speed modes

of the I²C-bus specification Rev 03 (UM10204_3). Bus clear, in the case of the DATA signal being

stuck low, is achieved after receiving 9 clock pulses. Operation in High Speed mode at 3.4 MHz

requires a minimum interface supply voltage of 1.8 V and a mode change in order to enable spike

suppression and slope control characteristics compatible with the I²C-bus specification. The high

speed mode can be enabled on a transfer-by-transfer basis by sending the master code

(0000 1XXX) at the beginning of the transfer. The DA9063 does not make use of clock stretching and

delivers read data without additional delay up to 3.4 MHz.

Alternatively, the interface can be configured to continuously use High Speed mode via PM_IF_HSM,

so that the master code is not required at the beginning of every transfer. This reduces

communication overhead on the bus, but limits the attachable slaves to the bus to compatible

devices.

Communication on the 2-WIRE bus always takes place between two devices, one acting as the

master and the other as the slave. The DA9063 only operates as a slave. Opposite to the 4-WIRE

mode, the 2-WIRE interface has direct access to two pages of the DA9063 register map (up to 256

addresses). The register at address zero on each page is used as a page control register (with the 2-

WIRE bus ignoring the LSB of control REG_PAGE). Writing to the page control register changes the

active page for all subsequent read/write operations unless an automatic return to page 0 was

selected by asserting control REVERT. Unless REVERT was asserted after modifying the active

page, a read-back of the page control register is recommended to ensure that future data exchange

is accessing the intended registers.

In 2-WIRE operation, the DA9063 offers an alternative method to access register pages 2 and 3.

These pages can be accessed directly by incrementing the device address by one (default read

address 0xB2; write address 0xB3). This removes the need to write to the page register before

access to pages 2 and 3, thus reducing the traffic on the 2-WIRE bus.

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DA9063

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6.8.1.3

Details of the 2-WIRE control bus protocol

All data is transmitted across the 2-WIRE bus in groups of 8 bits. To send a bit, the SI line is driven at

the intended state while the SK is LOW (a low on SI indicates a zero bit). Once the SI has settled, the

SK line is brought high and then low. This pulse on SK clocks the SI bit into the receiver’s shift

register, see Figure 25.

A two byte serial protocol is used containing one byte for address and one byte data. Data and

address transfer is MSB transmitted first for both read and write operations. Transmission begins

with the START condition from the master while the bus is idle. It is initiated by a high-to-low

transition on the SI line while the SK is in the high state (a STOP condition is indicated by a low-to-

high transition on the SI line while the SK is in the high state).

SK/

SLK

SI/

DATA

Figure 25: Timing of 2-WIRE START and STOP Condition

The 2-WIRE bus is monitored by the DA9063 for a valid slave address when the interface is enabled.

It responds immediately when it receives its own slave address. This ‘Acknowledge’ is done by

pulling the SI line low during the following clock cycle (see the white blocks marked A in Figure 27 to

Figure 30).

The protocol for a register write from master to slave consists of a start condition, a slave address

with read/write bit and the 8-bit register address followed by 8 bits of data terminated by a STOP

condition (all bytes responded by DA9063 with Acknowledge), as illustrated in Figure 26.

S

SLAVEadr

7 bits

W

A

REGadr

8 bits

A

DATA

8 bits

A

P

1 bit

Master to slave

Slave to master

S = START condition

P = STOP condition

A = Acknowledge (low)

W = Write (low)

Figure 26: 2-WIRE Byte Write (SI/DATA Line)

When the host reads data from a register, it first has to write access the DA9063 with the target

register address and then read access the DA9063 with a Repeated START or alternatively a second

START condition. After receiving the data, the host sends Not Acknowledge and terminates the

transmission with a STOP condition (Figure 27).

S

SLAVEadr

7 bits

W

A

REGadr

8 bits

A

Sr

SLAVEadr

7 bits

R

A

DATA

8 bits

A*

P

1 bit

S

SLAVEadr

7 bits

W

A

REGadr

8 bits

A

P

S

SLAVEadr

7 bits

R

A

DATA

8 bits

A*

P

1 bit

Master to slave

Slave to master

S = START condition

Sr = Repeated START condition

P = STOP condition

A = Acknowledge (low)

A* = No Acknowledge

W = Write (low)

R = Read (high)

Figure 27: Examples of 2-WIRE Byte Read (SI/DATA Line)

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DA9063

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Consecutive (page) read mode is initiated from the master by sending an Acknowledge instead of

Not Acknowledge after receipt of the data word. The 2-WIRE control block then increments the

address pointer to the next 2-WIRE address and sends the data to the master. This enables an

unlimited read of data bytes until the master sends a Not Acknowledge directly after the receipt of

data, followed by a subsequent STOP condition. If a non-existent 2-WIRE address is read then the

DA9063 returns code zero (Figure 28).

S

SLAVEadr

7 bits

W

A

REGadr

8 bits

A

Sr

SLAVEadr

7 bits

R

A

DATA

8 bits

A

DATA

8 bits

A

DATA

8 bits

A*

P

1 bit

S

SLAVEadr

7 bits

W

A

REGadr

8 bits

A

P

S

SLAVEadr

7 bits

R

A

DATA

8 bits

A

DATA

8 bits

A*

P

1 bit

Master to slave

Slave to master

S = START condition

Sr = Repeated START condition

P = STOP condition

A = Acknowledge (low)

A* = No Acknowledge

W = Write (low)

R = Read (high)

Figure 28: Examples of 2-WIRE Page Read (SI/DATA Line)

The slave address after the Repeated START condition must be the same as the previous slave

address.

For enhanced data transfer efficiency, the DA9063 supports two write modes: Page Write mode and

Repeated Write mode.

Page Write mode is used where the host has multiple bytes of data to be written to consecutive

register addresses. It is selected by setting the WRITE MODE control to 0. For Page Write mode the

master sends a device address followed by a register address then multiple data bytes. The 2-WIRE

interface automatically increments the register address pointer after each data byte is received. The

slave acknowledges each received byte of data until the master sends the STOP condition (Figure

29).

S

SLAVEadr

7 bits

W

A

REGadr

8 bits

A

DATA

8 bits

A

DATA

8 bits

A

DATA

8 bits

A

……...

A

P

1 bit

Repeated writes

Master to slave

Slave to master

S = START condition

P = STOP condition

A = Acknowledge (low)

W = Write (low)

Figure 29: 2-WIRE Page Write (SI/DATA Line)

Repeated Write mode is used where the host has multiple bytes of data to be sent to non-

consecutive registers. It is selected by setting the WRITE MODE control to 1. For Repeated Write

mode the master sends a device address followed by multiple address-data pairs. The slave

acknowledges each received byte until the master sends the STOP condition (Figure 30).

S

SLAVEadr

7 bits

W

A

REGadr

8 bits

A

DATA

8 bits

A

REGadr

8 bits

A

DATA

8 bits

A

……...

A

P

1 bit

Repeated writes

Master to slave

Slave to master

S = START condition

P = STOP condition

A = Acknowledge (low)

W = Write (low)

Figure 30: 2-WIRE Repeated Write (SI/DATA Line)

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DA9063

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6.8.2

High Speed 2-WIRE Interface

The high speed HS 2-WIRE interface is the alternate serial control bus. It consists of DATA (data

line) and CLK (clock line) and can be used as an independent control interface for data transactions

between the DA9063 and a second host processor. The DA9063 high speed 2-WIRE interface has a

configurable 8-bit write address (default 0xB4) and a configurable read address (default 0xB5). For

details of configurable addresses see control IF_BASE_ADDR in Section A.4.2 The interface is

enabled if HS2DATA was selected via configuration control GPIO14_PIN. The bus lines have to be

pulled high by external pull-up resistors (2 kΩ to 20 kΩ). GPIO14_TYPE defines the supply rail of the

interface (used for input logic levels and the internal pull-up resistors). The controls GPIO15_PIN and

GPIO15_WEN are disabled when enabling the interface via GPIO14_PIN.

When the interface receives a read or write command that includes a matching slave address, the

DA9063 can trigger the assertion of nIRQ and an optional wakeup event (enabled via

GPIO14_WEN). If the nIRQ assertion from interface access is enabled (E_GPI14), it should be

masked as long as the HS 2-WIRE is in use. This nIRQ cannot be cleared via the HS 2-WIRE

interface because every interface access triggers a re-assertion.

Except for the interface device addresses and the optional wakeup, the characteristics of the HS 2-

WIRE interface are identical to the power manager 2-WIRE interface, see Section 6.8.1. High speed

mode at 3.4 MHz can be enabled either via master code or continuously via PM_IF_HSM, but it does

not support slope control for minimum tfDA specification.

6.9 Voltage Regulators

Three types of low drop-out regulators (LDOs) are integrated on the DA9063: for sensitive analog

rails (for example, RF transceiver supply), the low noise regulators offer high PSRR across a wide

frequency range; the LDOs provide an optimized PSRR and noise performance with lowest

quiescent current. Quiescent current has been optimized for the always-on type regulators.

The regulators employ Dialog Semiconductor’s Smart Mirror™ dynamic biasing that guarantees

PSRR to be maintained across the full current range. Quiescent current consumption is dynamically

adjusted to the load, which improves efficiency at light load conditions. Furthermore, Dialog

Semiconductor’s Smart Mirror™ technology allows the capacitor to be placed close to the load.

Note

When placing an LDO capacitor remotely from the DA9063, the voltage drop (= load current * parasitic PCB

impedance) needs to be considered when configuring the LDO output voltage.

Table 45: Regulator Control

Regulator

Type

V_OUT

Steps

(mV)

Mode

Output

Voltage

(V)

Supplied

Max.

Current

(mA)

Current

Limit

LDO/

Bypass

(mA)

V_OUTControl

Notes

LDO1

Always-on

20

0.6 to 1.86

100

200

DVC variable

slew rate

Optional

voltage

tracking

LDO2

LDO3

LDO4

LDO5

Standard

20

50

0.6 to 1.86

0.9 to 3.44

0.9 to 3.6

200

100

400/300

400/200

400

DVC variable

slew rate

Bypass

DVC variable

slew rate

DVC variable

slew rate

200

V_OUT

programmable

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DA9063

System PMIC for Mobile Application Processors

Regulator

Type

V_OUT

Steps

(mV)

Mode

Output

Voltage

(V)

Supplied

Max.

Current

(mA)

Current

Limit

LDO/

Bypass

(mA)

V_OUTControl

Notes

LDO6

LDO7

LDO8

Low noise

Standard

50

0.9 to 3.6

200

400

V_OUT

programmable

Bypass

400/300

V_OUT

programmable

V_OUT

programmable

Switching

vibration

motor driver,

common

supply with

LDO7

LDO9

Low noise

50

0.95 to 3.6

0.9 to 3.6

200

300

400

V_OUT

programmable

Common

supply with

LDO10

V_OUT

programmable

Common

supply with

LDO9

LDO11

Standard

Bypass

300

4

400/300

V_OUT

programmable

LDOCORE

Always-on

2.5

±2%

V_OUTnon-

programmable

Internal LDO

accuracy

6.9.1

Regulators Controlled by Software

The regulators can be programmed via the power manager interface. All regulators can be enabled

or disabled by a write command to the enable bit LDOxx_EN. Each LDO has two voltage registers for

output voltage A and B. The appropriate values are stored in the registers VLDOxx_A and

VLDOxx_B. The specific output voltage is selected with the bit VLDOxx_SEL. Changes to this control

result in immediate output voltage changes on non-DVC regulators and ramped voltage transitions

on DVC-enabled regulators. The output voltage can also be changed by directly re-programming the

voltage control register. The sequencer also uses these registers and may write to them: their

contents can therefore be found to differ from previous write commands.

For security reasons, the re-programming of registers that may cause damage when being

incorrectly programmed (for example, voltage settings) can be disabled with control V_LOCK. This

disables write access to registers with an address higher than 0x7F.

6.9.2

Regulators Controlled by Hardware

All regulators can be enabled or disabled under hardware control using GPIO1, 2, or 13. The GPIO

port used is defined in register LDOxx_GPI. The output voltages can be switched by the GPIO port

between the A and B voltage. The specific GPIO port is defined in register VLDOxx_GPI. After

detecting a rising or falling edge at the GPI, the DA9063 configures the related regulators with the

status of GPI1, GPI2, or GPI13 (the event bit E_GPI1, E_GPI2, or E_GPI13 is automatically cleared).

A parallel write access to the regulator control registers is delayed and later overrides the hardware

configuration. The sequencer does not affect regulators controlled via GPIOs.

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6.9.3

Power Sequencer Control of LDOs

The power sequencer can control LDO1 to LDO11. The specific time slot of each LDO is defined with

bit LDOx_STEP in register bank starting at address 0x83. The sequencer enables and disables each

LDO individually depending on the setting of each LDO’s bit LDOx_CONF and LDOx_AUTO. To limit

the inrush current, it is recommended to enable a maximum of one regulator (including bucks) per

time slot.

If the control OTPREAD_EN is set, the regulator control registers are reloaded from OTP before

leaving POWERDOWN mode. During power-up, the sequencer always takes output voltage A

(defined in register VLDOxx_A). Therefore it also clears all VLDOxx_SEL bits.

When powering down, the sequencer disables all LDOs, but the LDOs can be configured to remain

on by setting bit LDOxx_CONF. In this case the output voltage B is always selected (value

programmed in register VLDOxx_B). The related bit VLDOxx_SEL is set by the sequencer

accordingly.

Table 46: LDO Power Sequence Voltage

LDO Output Voltage During Power-Up Sequencing

LDOx_CONF

LDOx_AUTO

LDO

Output Voltage

-

1

0

gets enabled

disabled

A

-

1

0

LDO Output Voltage During Power-Down Sequencing

LDOx_CONF

LDOx_AUTO

LDO

Output Voltage

1

0

-

remains enabled

gets disabled

B

-

The bit DEF_SUPPLY defines the sequencer action for time slot 0. If Bit DEF_SUPPLY is set, all

LDOs configured to time slot 0 are enabled or disabled during power-up according to Table 46. If bit

DEF_SUPPLY is not set, the LDOs configured to time slot 0 are disabled.

Note

When control bit LDOxx_SL_B is asserted, the LDO enters a forced sleep mode with the lowest quiescent

current, but with a reduced maximum output current. The maximum current is reduced because a smaller output

driver is used (a partial pass device). Asserting LDOxx_SL_A results in the same forced sleep mode for an LDO

when using the type A voltage register. Before wakeup from POWERDOWN mode (processing time slots from

domain SYSTEM), the sequencer can configure all regulators with default voltage values from OTP: this allows

any previously altered VLDOxx_A and LDOxx_SL_A settings to be reset.

Entering RESET mode automatically disables all regulators except LDO1. LDO1 stays enabled when

entering RESET mode and can be used as an always-on supply (staying on even when V_SYSdrops

below VDD_FAULT). However, LDO1 is disabled during NO-POWER, RTC and DELIVERY modes.

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6.9.4

Dynamic Voltage Control

LDO1 to 4 include DVC:

●

The output voltage can be programmed in 20 mV steps.

If the feedback signal GP_FB1 is configured to be READY (by asserting PM_FB1_PIN), this port

is asserted while slewing and asserts E_DVC_RDY after all voltage and buck regulators have

completed slewing.

DVC voltage transitions are handled by the following registers:

●

Output voltage setting registers VLDO1_A/VLDO1_B to VLDO4_A/VLDO4_B.

When writing into a selected voltage control register the output voltage is immediately ramped to

the new value. When writing into the non-selected voltage register the ramping is delayed until

this register is selected by toggling VLDOxx_SEL.

●

The voltage selection registers VLDOx_SEL activate a pre-configured transition to the alternate

output voltage. These controls have been grouped together in registers DVC_1 and DVC_2 to

better enable synchronized ramping of supply voltages.

The DVC slew rate for all DVC-enabled regulators can be configured as 10 mV per (0.5, 1.0, 2.0,

or 4.0) µs via control SLEW_RATE. Under light load conditions (< 10 mA), the slew rate is less

than the programmed value when the output is close to the start and end of the slope This is

especially the case for the fastest slew rate settings. The negative slew rate is load dependent

and might be lower than the one mentioned above.

6.9.5

Voltage Tracking Mode LDO1

LDO1 is able to follow the output voltage of buck converters BUCKCORE1, BUCKCORE2, or

BUCKPRO. The specific buck converter is selected and enabled with the bits LDO1_TRACK. The

initial voltage delta between LDO1 and the DC-DC converter is captured and any voltage transition of

the buck converter is mirrored to LDO1. Re-programming the LDO1 voltage register has no effect.

Although LDO1 shares the ramping speed with the buck converter, the real LDO1 output voltage is

also influenced by the load current. When the tracking mode is terminated via bit LDO1_TRACK or

the selected buck converter enters shutdown, LDO1 returns to its default output voltage (that is, to

the value set in register VLDO1_B or VLDO1_A).

When the buck converter ramping exceeds the maximum or minimum voltage capability of LDO1,

further steps below 0.6 V or above 1.86 V result in the temporary saturation of the LDO1 output

voltage. The tracked buck converter should not ramp to below 0.6 V while LDO1 tracking is enabled.

The minimum delta voltage between the output of LDO1 and BUCKCORE is achieved by connecting

the output of LDO1 to port CORE_SWS_GPIO4 and enabling the internal rail switch for the output of

BUCKCORE1 (or dual-phase BUCKCORE) through the assertion of control CORE_SW_INT. In this

case, the settings of the CORE_SW rail controller are used to configure the internal switch with the

result that this channel of the rail switch controller can no longer drive external switches (GPIO3 may

be used as a standard GPIO). The configured LDO1 output voltage should be equal to or slightly

lower than V_BUCKwhen closing the switch. DVC transitions on BUCKCORE1 (or BUCKCORE) during

this mode require LDO1_TRACK to be programmed to 10.

6.9.6

Pull-Down Resistor

All LDOs have a pull-down resistor at the output when they are disabled. The pull-down resistor can

be disabled with bit LDOxx_PD_DIS, and is required when LDOs are used in parallel with another

supply. Otherwise the output is pulled to GND.

If an over-voltage occurs (LDO1 to 4: V_OUT> 109 % of nominal V_OUT, LDO5 to 11: V_OUT> 106 % of

nominal V_OUT), the voltage regulators enable an internal load to discharge the output back to its

configured voltage. This can be disabled via LDOxx_PD_DIS.

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6.9.7

Bypass Mode and Current Limit

All LDOs feature a current limiting function. For LDOs with a bypass mode (LDO3, 4, 7, 8, and 11),

an over-current is indicated with an interrupt. When at least one of these LDOs reaches the current

limit for more than 10 ms, an interrupt is raised to the host (during POWERDOWN mode a wakeup

sequence is initiated) and the event bit E_LDO_LIM is set. The interrupt IRQ can be suppressed via

the mask bit M_LDO_LIM.

If the current limit condition persists for more than 200 ms (indicating a probable short circuit

condition), the related LDO is disabled and its LDOx_EN bit is de-asserted. The LDO remains

disabled until a new enable occurs (via hardware or software activation). The automatic shutdown of

the LDO can be disabled via bit LDO_SD. The host processor can distinguish if the IRQ is related to

a temporary over-current or to a permanent shutdown by polling the related bit LDOx_ILIM or

checking LDO3_EN, LDO4_EN, LDO7_EN, LDO8_EN, and LDO11_EN.

If the current limit is hit for more than 10 ms but less than 200 ms, the IRQ is generated but the

related LDO is not disabled. If the current limit is hit for more than 200 ms and the involved LDO is

shut down, the LDO<x>_EN bit is de-asserted. If the over-current spike has stopped before the host

is able to read the xx_LIM bits, the LDO that has been in current limit cannot be evaluated.

Changing from LDO to bypass mode and back triggers a change of the output voltage with some

over/undershoot during the transition phase.

6.9.8

LDO Supply from Buck Converter

LDO1 to LDO11 can optionally be supplied from a buck output (VDD < 2.8 V). In this mode some

specification parameters change:

●

at VDD = 1.8 V, the dropout voltage at I_maxincreases by 70 %

for a supply voltage less than 1.8 V, the LDO dropout voltage is valid only for 1/3 of the standard

I_maxand the current capability decreases with the provided supply voltage.

LDO5 and LDO11 may be supplied from a rail higher than V_SYS/CHG_WAKE (for example, the output

of a 5 V boost) as long as V_DD< 5.5 V.

6.9.9

LDO Sleep Mode for Reduced I_out

If the required output current is < 10 % of I_MAX, the quiescent power can be reduced by setting an

LDO into sleep mode. In this mode, the output driver current capability is reduced to 10 % of I_MAX

Sleep mode can be set independently for the output voltage A and B by setting bit LDOxx_SL_A or

bit LDOxx_SL_B. During LDO sleep mode, the over-current limit of the LDOs with a bypass function

(LDO3, 4, 7, 8, and 11) is reduced to 50 %. As a benefit of Dialog Semiconductor’s Smart Mirror™

technology, sleep mode is typically not required because the quiescent current taken by the regulator

is automatically minimized when operating at low current demands.

.

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6.9.10 Vibration Motor Driver

LDO8 provides a third mode dedicated to drive vibration motors selected via bit LDO8_MODE. In this

mode, the voltage regulation circuitry is disabled and no external stabilization capacitor is needed. In

comparison to LDO mode, the PWM control is more efficient and allows an instant on and off for the

vibrator signal.

VSUP

PWM

VLDO8

Vibrator

motor

BRAKE

GND

Figure 31: Vibration Motor Driver

The vibrator motor driver is a half-bridge PWM-controlled motor driver, with an automatic battery

supply correction of the PWM duty cycle (Figure 31). The PWM base frequency can be selected by

PWM_CLK to be either 1.0 MHz or 2.0 MHz (resulting in a PWM repetition rate of 15.6 kHz or

31.25 kHz). The vibration motor speed is determined by the effective output voltage which is set via

control VIB_SET (6 bits giving 64 programmable speeds). Setting the output voltage to 0 turns on a

braking NMOS transistor to stop the vibration motor immediately.

The motor can also be stopped and started by a level on port nVIB_BRAKE, if enabled via bit

PM_FB3_PIN.

The PWM duty cycle is corrected automatically before it is enabled and after each breaking period. It

is also automatically corrected every 10 s when it is running for longer periods. These corrections are

done via autonomous V_SYSmeasurement via the internal GPADC (overrides control setting of

AUTO_VSYS_EN). The duty cycle, D, is given by D = VIB_SET / V_SYS

.

Note

The half-bridge driver transistors have an internal current limit of approximately 400 mA

6.9.11 Core Regulator LDOCORE

The LDOCORE is a 2.5 V supply dedicated for the internal logic of DA9063. It is used for running the

state machine, GPIO pins with comparators, bias, reference, GPADC, OTP, and power manager

registers. It is supplied from internal rail V_DDREF, powered from either CHG_WAKE or V_SYS. When

LDOCORE is supplied in RESET mode, its output voltage is temporarily reduced to 2.2 V. In general,

LDOCORE is an always-on supply (remaining enabled during RESET mode), but for lowest

dissipation power LDOCORE can also be disabled when progressing towards RTC or DELIVERY

mode.

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6.10 DC/DC Buck Converters

DA9063 includes six DC/DC buck converters with DVC.

VDD (2.8 ... 5.5V)

Isense

DCDC CONVERTER

1.0uH

(3 MHz )

VBUCK

DRV

V _FB

CNTRL

DAC

CTRL

REF

C_OUT

SLEEP_EN

POWER-EN

Figure 32: DC-DC Buck Converter

The converters are high efficiency synchronous step-down regulators, operating at a high frequency

(3 MHz), supplying individual output voltages with ± 3 % accuracy. The default output voltage is

loaded from OTP and can be set in 10 mV steps. To limit in-rush current from V_SYS, the buck

converters perform a soft-start for up to 3 ms, when enabled via control SOFT_START. During this

3 ms period, the output current of the buck is limited.

The DVC controller allows the following features:

●

The buck converter output voltage is programmable over the power manager bus in 10 mV steps.

If the feedback port GP_FB1 is configured as READY, this port is asserted while slewing and

asserts E_DVC_RDY after all voltage and buck regulators have stopped slewing.

●

Output voltages below 0.7 V are only supported in Pulse Frequency Modulation (PFM) mode.

During a voltage reduction below 0.7 V, the slew rate control ends at 0.7 V and the buck mode is

automatically changed to PFM mode.

The DVC control is handled by the following registers:

●

Output voltage setting register VBxxxx_A/VBxxxx_B.

When writing to the voltage control register that is in use by an enabled buck, the output

immediately ramps to the new setting. When writing to the voltage control register that is not in

use, the ramping is delayed until this register is selected by toggling VBxxxx_SEL.

The voltage register selection VBxxxx_SEL.

This activates a pre-configured transition to the alternate output voltage. These controls are

grouped into registers DVC_1 and DVC_2 to better enable synchronized ramping of supply

voltages.

The DVC slew rate is programmable as at 10 mV per (4, 2, 1, or 0.5) µs via control SLEW_RATE.

During PFM mode, the negative slew rate is load-dependent and might be lower than the

programmed rate.

The supply current during PWM (synchronous) operation is in the order of 3.5 mA (quiescent current

and charge/discharge current) and drops to <1 µA in shutdown. Switching frequency is chosen to be

high enough (3 MHz) to allow the use of a small 1.0 µH inductor.

The operating mode of the buck converter is selected via the buck control register bits B<x>_MODE.

The buck converter can be forced to operate in either PWM or PFM mode. Additionally, the buck

converter has an automatic mode where it switches between PWM and PFM modes depending on

the load current.

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The switching converters can be enabled/disabled/configured via the power manager and HS 2-

WIRE interface. Writing to Bxxxx_EN/VBxxxx_SEL unconditionally configures the regulator to the

selected mode (enabled/disabled). Reading Bxxxx_EN/VBxxxx_SEL provides the actual state, which

may differ from a previous write (in the case where the regulator state is changed from GPIO or

power sequencer control). All bucks can be controlled with an ID from the power sequencer. If

enabled in DEF_SUPPLY, supplies can be configured to default settings when the sequencer passes

slot 0.

To limit the inrush current, it is recommended to select individual regulators (including LDOs) only

with xxxx_DEF settings.

When powering up, the power sequencer clears VBxxxx_SEL for a buck when it has an ID pointing

to the time slot being processed. This forces the regulator to ramp the output voltage to the value

programmed inside the related register VBxxxx_A.

When powering down (for example, to POWERDOWN mode), sequencer-controlled supplies are

usually disabled but can be configured to remain on by setting Bxxxx_CONF. In the latter case, the

sequencer sets VBxxxx_SEL so that the regulator output voltage is ramped to the value programmed

inside the related register VBxxxx_B. Disabled bucks can switch off their pull-down resistor, see

Section 6.9.5. Before wakeup from POWERDOWN mode (processing time slots from domain

SYSTEM), the sequencer can configure the bucks with default voltage values from OTP and reset

any changed VBxxxx_A settings.

All buck converters provide an optional hardware enable/disable via GPIO1, 2, and 13. A regulator

that has to be enabled/disabled from a GPI port selects this feature via its control Bxxxx_GPI. A

change of the output voltage from the state of a GPI is enabled via control VBxxxx_GPI. After

detecting a rising or falling edge at the GPI, the DA9063 configures the enabled regulators with the

status of GPI1, GPI2, or GPI13 (the event bit E_GPI1, E_GPI2 or E_GPI13 is automatically cleared).

A parallel write access to the regulator control registers is delayed and later overrides the HW

configuration. The sequencer does not change regulator settings enabled for GPI control. Powering

down to RESET mode automatically disables all buck converters. When the output of a buck

converter is combined with a parallel low power LDO, its pull-down resistor needs to be disabled via

Bxxxx_PD_DIS. Otherwise its output is discharged to GND when being disabled.

To allow DVC transitions under load, the buck current limit should be configured at least 40% higher

than the required maximum continuous output current. See Table 47 as a guide to determining this

limit.

Table 47: Selection of Buck Current Limit from Coil Parameters

Min. ISAT

(mA)

Frequency

(MHz)

Buck Current Limit

(mA)

Max. Output Current

(mA)

3800

3100

2400

1700

3

3400

2800

2100

1700

2400

2000

1500

1200

To ensure correct regulation, the buck converters require the supply voltage to be 0.7 V higher than

the output voltage. As this is not always possible at higher output voltage settings, the converters

BUCKMEM, BUCKIO, and BUCKPERI provide a follower mode where the electrical characteristics of

the DC-DC converter no longer apply, but instead the PMOS output driver is fully-on and the output

voltage simply follows the dropping input voltage. There will be a voltage drop between the buck

VDD supply and the output which results from the on-resistance of the buck PMOS driver and the

coil, with the voltage drop magnitude being depending on load current. Bucks running in follower

mode will temporarily stop switching and by that process will generate PWM mode 3 MHz sub-

harmonics.

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6.10.1 BUCKCORE1, BUCKCORE2, and BUCKPRO

BUCKCORE1, BUCKCORE2, and BUCKPRO include a full-current (previously overdrive) mode,

individually enabled via control BCORE1_OD, BCORE2_OD, and BPRO_OD.

In full-current mode:

●

The maximum current capability is 2500 mA

The selected current limits are automatically doubled

The quiescent current increases due to the increased switching losses

For full-current mode, the application requires two 47 µF output capacitors and an appropriate

inductor that can sustain higher currents without heating up or suffering from inductance degradation.

BUCKCORE1 and 2 can also be merged as a dual-phase BUCKCORE with up to 5000 mA

maximum output current. If enabled in OTP via BCORE_MERGE, the register controls of

BUCKCORE2 (except BCORE2_PD_DIS) are automatically disabled and the output from both coils

must be routed together. The feedback signal for both phases is taken from the sense node switch

matrix of BUCKCORE1 (the VBUCKCORE2 pin may be left floating if the internal pull-down resistor

is enabled by setting BCORE2_PD_DIS = 0). With BCORE1_FB programmed in OTP to 0b000, a

differential remote sensing at the point-of-load can be enabled, using VBUCKCORE2 as a GND

sense port. In this mode, the BUCKCORE output capacitor voltage has to be routed to port

CORE_SWS or GP_FB_2 (selected via control MERGE_SENSE). Depending on the settings of

BCORE1_OD, the dual-phase buck provides a maximum 2500 mA or 5000 mA, requiring two or four

47 µF output capacitors, respectively.

BUCKCORE2 always runs on the inverted clock (anti-phase) of BUCKCORE1. The switching node

output of both phases must be connected symmetrically on the PCB (with matched routing

inductances and resistances).

GP_FB2 or CORE_SWS

VSYS

VBUCK_CORE1

BUCK

CORE1

1µH

Z_T

VSYS

3x22/47µF

Z_T

VBUCK_CORE2

1µH

Load

BUCK

CORE2

1x22/47µF

Z_{T = resistance of PCB traces}

Figure 33: BUCKCORE1 and BUCKCORE2 in Dual-Phase Remote Sense Mode

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6.10.2 BUCKPRO in DDR Memory Bus Termination Mode

If enabled via BPRO_VTT_EN, BUCKPRO offers an alternative mode to provide VTT bus termination

for DDR memory. In this mode, its output voltage tracks 50 % of the VDDQ sense port voltage

(Figure 34). In this mode, BUCKPRO must be set to sync mode either by the host or by OTP

configuration. If enabled via BPRO_VTTR_EN, a second VTTR output provides the same voltage for

a DDR VTTR reference rail, buffered with ± 10 mA source/sink capability (requires 0.1 µF

stabilization capacitor). With BPRO_VTTR_EN being asserted in combination with BPRO_VTT_EN

released, the DA9063 provides a VTTR reference buffer with BUCKPRO running in a normal output

voltage control mode. If memory termination is not required (BPRO_VTTR_EN = 0), port VDDQ

provides the state of event E_GPI2 and port VTTR provides the state of the 1.2 V comparator.

-

VTT = VBUCKPRO

+

VSYS

BUCK

SWBUCKPRO

PRO

VSS

Figure 34: BUCKPRO Memory Bus Termination Mode

6.10.3 BUCKMEM and BUCKIO in Merged Mode

The converter BUCKMEM can be merged with BUCKIO via control BUCK_MERGE to form a single

DC-DC converter with a maximum output current of 3000 mA (Figure 35). The routing of the switcher

output pins to the common inductor must be symmetrical. The VBUCKIO feedback pin may be left

floating in merged mode if its internal pull-down resistor is enabled by setting BIO_PD_DIS = 0. The

inductor (1.0 µH) and the output capacitor have to be selected according to the increased output

current configuration controls of BUCKIO are disabled by asserting the bit BUCK_MERGE; the

selected current limits of BUCKMEM are automatically doubled.

SWBUCKIO

Symmetrical

wiring required

40uF

SWBUCKMEM

VBUCKMEM

Figure 35: BUCKMEM Merged With BUCKIO

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6.11 Buck Rail Switches

BUCKCORE and BUCKPERI offer a gate driver for an external NMOS that allows an output rail

shutdown and re-enable independently from the state of the buck (Figure 36). If a switch is open, the

associated pin is discharged to VSS by a pull-down resistor. All switch outputs require 100 nF

decoupling. All switches provide a soft-start in the form of a slew-rate limit which can be programmed

via control SWITCH_SR. The input surge current is therefore linearly proportional to the capacitance

connected to the output of the switch.

When the switch is closed, the buck can be configured by control Bxxx_FB to select the switch output

signal as a voltage sense node (instead of the buck output voltage) to compensate for losses in the

switch. Otherwise, Bxxx_FB should be programmed as 0b001 (setting 0b000 is invalid).

Where a buck does not require a rail switch, it can be routed to the output of another buck. In this

case, the feedback control should be programmed to 0b001. The feedback of the buck using both

switches may be programmed to be taken from the output of CORE_SW (CORE_SWS) or the output

of PERI_SW (PERI_SWS), or even from a mix of both (averaged). When a switch is opened, its

signal is automatically disconnected from the feedback path. When all switches selected for the

feedback signal mix are open, the buck automatically switches the feedback back to its output.

Before any of the rail switches can be closed, a charge pump must be enabled via control CP_EN.

Depending on the setting of CP_EN_MODE, it may be automatically disabled when all buck rail

switches are opened. During charge pump automatic mode, closing the first switch is delayed until

the charge pump has stabilized its output voltage (< 700 µs).

The state of each switch is controlled via its control xxx_SW_EN. These bits can be modified by a

register write or via GPI1, 2, or 13 if enabled by register SWITCH_CONT. Alternatively, they can be

controlled from the power sequencer by programming controls xxx_SW_STEP into the intended time

slot (which closes the switches on power-up and opens the switches on power-down). By asserting

xxx_SW_CONF, the sequencer can be forced to leave the switch closed when powering down.

If a buck rail switch is not required, its ports can instead be used as a GPIO (selected via

GPIOxx_TYPE).

Additional rail switches are available by using LDOs 3, 4, 7, 8, and 11 in bypass mode.

C

Figure 36: Buck Rail Switches

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6.12 Backup Battery Charger/RTC Supply Rail Generator

The backup battery charger provides a constant charge current with a programmable top-up charging

voltage for charging of Lithium-Manganese coin cell batteries and super capacitors. Charging current

is programmable via BCHG_ISET from 100 to 1000 µA (in 100 µA steps) and from 1 mA to 6 mA (in

1 mA steps). End-of-charge termination voltage is programmable in 100 mV/200 mV steps from 1.1 V

to 3.1 V. The backup battery charger is enabled by setting BCHG_VSET and BCHG_ISET to a non-

zero value. When enabled, the charger aims to maintain the backup battery at its target voltage. The

backup battery charger can be temporarily disabled in POWERDOWN mode via control bit

BBAT_DIS and it switches off automatically during a POR.

The backup battery charger includes reverse current protection and can also be used as an ultra-low

quiescent always-on supply for low voltage/power rails (may stay on during RESET mode).

The backup battery rail follower provides the internal supply voltage VDDRTC for the 32 kHz

oscillator and RTC digital whenever being powered from V_DDREF(V_DDREF> 2.4 V) or from a backup

battery (VBBAT > 2.0 V), depending on the following conditions:

●

If only the backup battery is applied (for example, in case of a deep discharged or removed main

battery) the switch automatically connects the RTC block to the backup battery.

If both the system rail V_DDREFand the backup battery are present, the RTC block is powered by

the higher of these two voltage sources. This implementation allows for maximum utilization of

the energy left in the main battery, thus extending the life of the lower capacity backup battery. A

seamless transition is achieved by the VDDRTC follower by generating a replica of the backup

battery voltage from V_DDREF(min. 1.45 V). To limit the oscillation while switching between VBBAT

and the internal replica voltage, the backup battery switch has a built-in hysteresis of 75 mV.

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6.13 General Purpose ADC

6.13.1 ADC Overview

The Analog to Digital Converter (ADC) uses a sample and hold successive approximation switched

capacitor architecture. It is supplied from VDDCORE (2.5 V). Configured via control ADC_MODE, it

can be used either in high-speed mode with measurement sequences repeated every 1 ms or in

economy mode with sequences repeated every 10 ms.

6.13.2 ADC Input MUX

The DA9063 provides an ADC with 10-bit resolution and track and hold circuitry combined with an

analog input multiplexer (Figure 37). The analog input multiplexer allows conversion of up to nine

different inputs. The track and hold circuit ensures stable input voltages at the input of the ADC

during the conversion.

The ADC is used to measure the following inputs:

●

Channel 0: VSYS_RES – measurement of the system VDD (2.5 to 5.5 V)

Channel 1: ADCIN1_RES – high impedance input (0 to 2.5 V)

Channel 2: ADCIN2_RES – high impedance input (0 to 2.5 V)

Channel 3: ADCIN3_RES – high impedance input (0 to 2.5 V)

Channel 4: T_J– measurement of internal temperature sensor

Channel 5: VBBAT – measurement of the backup battery voltage (0 to 5.0 V)

Channel 8: MON_A8_RES – group 1 internal regulators voltage (0 to 5.0 V)

Channel 9: MON_A9_RES – group 2 internal regulators voltage (0 to 5.0 V)

Channel 10: MON_A10_RES – group 3 internal regulators voltage (0 to 5.0 V)

Figure 37: ADC Block Diagram

The MUX selects from and isolates the nine inputs, and presents the channel to be measured to the

ADC input. When selected, an input amplifier on the V_SYSchannel subtracts the VDDCORE reference

voltage and scales the signal to the correct value for the ADC.

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6.13.3 Manual Conversion Mode

Manual measurements by the ADC are initiated by an ADC_MAN bit register write. The ADC powers

up, one conversion is done on the channel specified by ADC_MUX and the 10-bit result is stored in

the ADC_RES_H and ADC_RES_L registers. After the conversion is completed, the ADC powers

down again, ADC_MAN bit is reset and an IRQ event flag is set (E_ADC_RDY). The generation of

this IRQ can be masked by the IRQ mask M_ADC_RDY.

6.13.4 Automatic Measurements Scheduler

The automatic measurement scheduler allows monitoring of the system voltage V_SYS, the auxiliary

channels ADCIN1 to 3 and the output voltage supervision of embedded regulators. The results are

automatically compared with upper and lower thresholds set by power manager registers to give an

nIRQ event if a measurement is outside these levels. All measurements are handled by the

scheduler system detailed below.

The scheduler performs a sequence of 10 slots continually repeated according to the configured

mode. A slot requires 100 µs. The pattern of measurements over the 10 slots depends upon the

enabled automatic measurements. Additional manual measurement opportunities are available in

slots where automatic measurements have been disabled by control bits in ADC_CONT. Automatic

measurements only store the eight MSBs of the ADC measurement.

Figure 38 shows (with typical configurations) how the different measurements are scheduled.

Figure 38: ADC Sequence

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6.13.4.1

A0: V_SYSVoltage nIRQ Measurement Mode

V_SYSis measured, stored in VSYS_RES and compared with the VSYS_MON threshold. If the result

of the comparison is different to its previous state (being either lower or higher) for three consecutive

readings, an E_VDD_MON event is generated. Glitches of a duration less than three consecutive

measurements do not update the state; events are triggered at rising and falling edges of the state

signal. This multiple reading debounces the V_SYSvoltage before issuing an nIRQ. After the nIRQ

assertion, the automatic measurement of channel V_SYSis paused for reading. The host must clear the

associated event flag to re-enable the supervision of V_SYS. The event-causing value is kept in the

result register.

If selected via GPIO12_PIN, the debounced comparator state can be indicated via the GPO12 port,

representing a power good signal that can be used, for example, to trigger boot activities on external

ICs. If no action is taken to restore the V_SYSvoltage (that is, discharging of the battery continues), the

host may consider switching off optional ‘always-on’ blocks (for example, backup battery) to save

energy later on. V_SYSmeasurements are enabled via control AUTO_VSYS_EN.

Figure 39: V_SYSMonitor Persistence Behavior

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6.13.4.2

A1, A2, A3: Automatic Measurement and High/Low Threshold Warning nIRQ Mode

The automatic measurement result of channel ADC_IN1 is stored in the ADCIN1_RES register. If a

reading of A1 is less than AUTO1_LOW or greater than AUTO1_HIGH, then the event flag E_GPI0 is

set. If nIRQ is asserted, the automatic measurement of channel ADC_IN1 is paused until the host

has cleared the associated event flag (the event-causing value is kept in the result register). The

assertion of nIRQ can be masked by IRQ mask M_GPI0, which also disables the pausing of

automatic measurements. If debouncing is selected via ADCIN1_DEB the event is only asserted if

two consecutive measurements override the same threshold. The automatic measurement is

enabled by register AUTO_AD1_EN. In addition, it is possible to use ADCIN_1 with a 1 μA to 40 μA

current source that allows automatic measurement of a resistor value (programmed via

ADCIN1_CUR). The current source is enabled by AD1_ISRC_EN. During automatic measurements

the enabled current source is dynamically switched off at the end of the conversion and switched on

one slot prior to the next ADCIN_1 measurement (to enable minimum current consumption, and

allow any external capacitance voltage to settle); otherwise its status is static.

A similar functionality is available at ADC_IN2 and ADC_IN3. ADC_IN2 provides notification to the

processor via a fixed voltage comparator (also available when ADC is powered down) but the

ADCIN2 current source is static (no dynamic switch-off at the end of automatic conversion). The

input selection switch of ADC_IN2 provides an enhanced isolation (80 dB typ.) between the

externally-connected circuit and the internal ADC block (for example, allowing the DC supervision of

noise sensitive audio lines).

Figure 40: A1, A2, A3 Persistence Behavior

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6.13.4.3

A8, A9, A10: Automatic Regulator Monitor with Under- Or Over-Voltage Shutdown

DA9063 provides the capability to monitor the output voltage of internal regulators. In case of a

catastrophic failure, the related regulator is disabled. This feature is enabled using control

MON_MODE. Each internal regulator is assigned to a GPADC input channel and can be individually

enabled for monitoring via controls BCORE1_MON_EN to LDO11_MON_EN. For example, if ADC

channel A8 is connected to an enabled regulator and it is also enabled for monitoring, the ADC

automatically measures the regulator output voltage every 1 ms (10 ms in ADC economy mode).

Simultaneously, two relative thresholds are calculated from the regulator nominal output voltage

(supporting DVC). If the regulator is out of range, the voltage measurement is stored inside

MON_A8_RES, the regulator ID is recorded inside the index MON_A8_IDX and the event flag

E_REG_UVOV is set. To secure a stable output voltage, the monitoring is delayed after regulators

are switched on and when changing their voltage level to a new target (that is, during DVC slewing,

after writing into the active regulator voltage register, or when the active voltage control register is

changing between Vxxx_A and Vxxx_B). This delay is programmable using control UVOV_DELAY.

If debouncing is selected via MON_DEB, an event is only created if two consecutive measurements

exceed the same threshold. The feature is also available for channels A9 and A10.

Table 48: Assignment of Regulators for Voltage Monitoring

ADC channel

Regulator

Enable

A8

BUCKCORE1

BCORE1_MON_EN

BCORE2_MON_EN

BPRO_MON_EN

LDO3_MON_EN

LDO4_MON_EN

LDO11_MON_EN

BUCKCORE2

BUCKPRO

LDO3

LDO4

LDO11

A9

BUCKIO

BUCKMEM

BUCKPERI

LDO1

LDO2

LDO5

BIO_MON_EN

BMEM_MON_EN

BPERI_MON_EN

LDO1_MON_EN

LDO2_MON_EN

LDO5_MON_EN

A10

LDO6

LDO7

LDO8

LDO9

LDO10

LDO6_MON_EN

LDO7_MON_EN

LDO8_MON_EN

LDO9_MON_EN

LDO10_MON_EN

If more than one regulator is assigned to A8, A9, or A10, the regulator measurements are

sequentially multiplexed on this channel (elongates the measurement period of 1 ms or 10 ms by

each additional assigned regulator). In the case of an E_REG_UVOV event, the regulator monitoring

continues and shuts down rails facing catastrophic failure (voltage and IDX controls contain

information for determining the cause of the most recently detected under- or over-voltage). When

clearing E_REG_UVOV via a host write, the related regulator index controls are reset. In the unlikely

case in which several regulators from a sequenced ADC channel have triggered an under- or over-

voltage condition before the host was able to read the related controls, all monitored supplies may be

checked for their actual state (enabled or shutdown) to detect if further supplies have also been shut

down in addition to the one captured by the index control.

The assertion of nIRQ can be masked by IRQ mask M_REG_UVOV. With a masked nIRQ from

regulator supervision, the setting of MON_RES determines whether an out-of-range detection

disables the related regulator or triggers the assertion of port nRESET. In the latter case, nRESET is

asserted for 1 ms and continues to be asserted until the regulator returns to being in range

(regulators that are not enabled but are selected for monitoring do not trigger the assertion of

nRESET). With a masked nIRQ, GP_FB2 can be configured to flag PWR_OK, indicating that all

monitored regulator voltages are in-range. Selecting disabled regulators for monitoring suppresses

the assertion of PWR_OK.

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The regulator monitor unit provides alternative modes selected via MON_MODE. In measurement-

only mode, the event flag E_REG_UVOV is set for every automatic measurement result being

available on either A8, A9, or A10 (with a maximum of one regulator per channel being enabled for

measurements). When enabled, an auto-measurement on A8, A9, or A10 allows the host to get its

actual output voltage from registers MON_A8_RES to MON_A10_RES. When multiple ADC

channels are enabled for automatic regulator voltage measurements, the burst measurement mode

may reduce the control interface traffic and number of nIRQ assertions. When the ADC time slot of

A10 has finished, the event flag E_REG_UVOV is set (independent of A10 being enabled for auto-

measurements). The host can then read the measurement results stored inside MON_A8_RES -

MON_A10_RES as a block. During measurement modes, there are no threshold comparisons or

regulator shutdowns. If the nIRQ line was asserted, automatic measurements on channels A8 (A9

and A10) are paused until the host has cleared the associated event flag (the event-causing value is

kept in the result registers). During measurement modes, E_REG_UVOV is cleared by writing the

read value into register EVENT_B. To sequentially measure other regulators on ADC input channels

A8, A9, and A10, the host has to set the monitor enable for the next measurement slot to the

required regulator before clearing the event. The assertion of nIRQ can be masked by IRQ mask

M_REG_UVOV, which also disables the pausing of automatic measurements. For further information

about voltage monitoring, please see DA9063 Voltage Monitoring [2].

Note

Voltage monitoring function cannot be used for any LDO in bypass mode.

6.13.4.4

A4 and A5: Manual Measurement T_Jand V_BBAT

The 10-bit result of manual measurements is stored in the registers ADC_RES_L and ADC_RES_H.

Channel 4 (T_J) is used to measure the output of the internal temperature sensor (generated from a

proportional to absolute temperature (PTAT) current using a bandgap reference circuit). The ADC

measurement result and the T_OFFSET value can be used by the host to calculate the internal

junction temperature, defined by the following formula:

T_J[°C] = -0.398 * (ADC - T_OFFSET) + 330

Channel 5 can be used to measure the voltage of the backup battery.

Manual measurements on A8 to A10 are possible, but require disabling the automatic measurements

on these channels and also ensuring that only one regulator is connected to each of these ADC

channels.

NOTE

The T_OFFSET value is stored in the T_OFFSET register at address 0x104 during manufacture.

6.13.5 Fixed Threshold Comparator

A comparator with a threshold of 1.2 V is connected to the input of ADC channel 2. The comparator

is asserted when the input voltage exceeds or drops below 1.2 V for at least 10 ms (debouncing).

After being enabled via COMP1V2_EN, the status flag COMP1V2 indicates the actual state and a

maskable interrupt request E_COMP1V2 is generated at the falling and rising edge state transitions.

The comparator may be disabled via COMP1V2_EN when auto-measurements with high resolution

are executed on ADCIN2.

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6.14 Real Time Clock

The RTC circuit maintains the real time clock and alarm functions. The variable RTC supply voltage,

VDDRTC, is derived from VBBAT. Generally, the RTC block is powered from V_DDREF, but with

RTC_EN asserted, the DA9063 enters a special low-power RTC mode under the following

conditions:

●

Unconditionally, when the VBBAT (the backup battery supply) is the only available voltage source

in the system (no external charger or main battery). DA9063 enters RTC mode automatically

since all the other supply domains are down (V_DDREF< VPOR_LOWER).

If the RTC_MODE_PD control bit is set (from OTP or host) and the power sequencer reaches

slot 0 during a power transition from ACTIVE to POWERDOWN mode. The above condition

disables LDOCORE and powers down all blocks (that are unrelated to the RTC circuit operation).

Similar to the above case, the device goes in to RTC mode if RTC_MODE_SD control bit is set

(from OTP or host) and the main PM control logic reaches RESET mode in the presence of a

V_SYSfault.

The following conditions (edge sensitive) that re-enable the DA9063’s full control logic (terminating

RTC mode):

●

V_DDREFrising to > 2.6 V (unconditionally)

There is no dedicated event bit. A start-up with POR asserted but no asserted E_WAKE,

E_nONKEY, E_TICK, or E_ALARM event bit indicates main battery insertion. Depending on the

V_SYSrise timing and final level, an E_VDD_WARN or E_VDD_MON wakeup event may be

triggered which, if not masked via M_VDD_WARN and M_VDD_MON in OTP, will cause an

application power-up, even when AUTO_BOOT is cleared in OTP.

●

External charger insertion via CHG_WAKE in the presence of a valid V_DDREFsupply (V_DDREF

2.6 V)

>

●

Assertion of nONKEY in the presence of a valid V_DDREFsupply (V_DDREF> 2.6 V)

Alarm/tick event when there is a valid V_DDREFsupply (V_DDREF> 2.6 V; alarm event is otherwise

stored in case this condition later becomes true)

The above assertions from nONKEY or CHG_WAKE must remain until LDOCORE is able to leave

the POR state, otherwise the DA9063 relapses back into RTC mode.

6.14.1 32K Oscillator

The clock oscillator circuit is used to drive the RTC. It works with an external piezoelectric oscillator

crystal at 32.768 kHz and is enabled via control CRYSTAL. If enabled, the DA9063 biases the crystal

when leaving DELIVERY or NO-POWER mode, which starts up the oscillator. By asserting RTC_EN,

the crystal remains biased (the RTC continues to run).

Note

When the 32 kHz oscillator is disabled, an external oscillator signal may be applied to port XOUT (the signal is

forwarded phase-inverted).

In order to achieve the desired crystal frequency, an external capacitor (10 pF to 20 pF, depending

on the parasitic capacitance of the board) should be connected to ground from each of the crystal

pins. The start-up time of the oscillator is typically 0.5 s to 1 s. The XTAL pins should be grounded

when the crystal is not mounted and when not being driven by an external oscillator signal. The

32 kHz clock signal is available at the OUT_32K port and the buffer can be enabled/disabled from

the host via control EN_32KOUT. The 32 kHz signal can also be made available at GP_FB3

(enabled via control PM_FB3_PIN).

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6.14.1.1

First Power-Up Sequencing after Enable of 32 kHz Oscillator (ID EN32K_STEP)

When the oscillator is enabled (when asserting control CRYSTAL, or when leaving DELIVERY or

NO-POWER mode with CRYSTAL already asserted), OUT_CLOCK determines whether the clock

provision at OUT_32K (GP_FB3) is gated by a timer. This enables the clock output only when the

oscillator signal has become stable. The control RTC_CLOCK provides a similar gating function prior

to the clock signal being fed into the internal RTC counter. The stabilization timer (configured via

STABILISATION_TIME) can either be started immediately or be configured to wait until the clock’s

duty cycle is within the range 30-70% (selected via DELAY_MODE). When powering up before the

stabilization timer has expired, ID EN32K_STEP forces the sequencer to wait for timer expiry, which

allows a correlation of the 32 kHz signal being provided to outputs with other power up actions

following the enable of the 32 kHz oscillator. When reaching ID EN32K_STEP with OUT_CLOCK

being released, the gating of the 32 kHz signal is terminated immediately. ID EN32K_STEP is not

processed by the sequencer powering-down, nor during consecutive sequencing powering-up.

6.14.1.2

Other Power-Up and -Down Sequencing (ID PD_DIS_STEP)

If the power sequence does not contain the sequencer ID EN32K_STEP, the control

OUT_32K_PAUSE from ID PD_DIS_STEP can be used to control the dedicated clock output port

OUT_32K in relation to other sequencer actions when powering up and down. The same is true for

any sequencing following the first signal provision to port OUT_32K in case the power sequence

contains ID EN32K_STEP.

Clearing control crystal enables the provision of the 32 kHz signal from an external clock source

connected to the XOUT pin, see Table 49. The provision of external clock signals is not timing

controlled and the sequencer ID EN_32K immediately progresses in this case. The crystal input pins

can withstand leakage currents corresponding to connected resistances at least as low as 10 MΩ,

connected between the pin and any signal level between V_DDREFand GND.

Table 49: 32 kHz Oscillator Modes

Power Mode

Conditions

NO-POWER

DELIVERY

No operation, supplies < ~2V

No operation, though powered

0

1

0

x

-

0

1

x

0

1

x

-

Note 1

1

x

1

x

1

x

1

Only RTC and Alarm operating from

external clock

0

EXT

Note 1

RTC

Only RTC and Alarm operating from

internal crystal oscillator

0

1

OSC

-

Note 1

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Power Mode

Conditions

Half-current operation, RTC and alarm off

using external clock

1

x

0

1

0

1

0

1

-

EXT

Note 2

Half-current operation, RTC and alarm on

using external clock

1

EXT

-

Note 3

ACTIVE

Half-current operation, RTC and alarm off

using internal crystal oscillator

1

OSC

Note 4

Note 2

Half-current operation, RTC and alarm on

using internal crystal oscillator

1

OSC

Note 3

Note 1 Requires nOFF or nSHUTDOWN to be asserted during V_DDREFrising, or a power-down transition from

ACTIVE mode with RTC_MODE_PD or RTC_MODE_SD being enabled

Note 2 Triggered from nONKEY press, assertion of CHG_WAKE or V_DDREFrising towards > 2.6 V

Note 3 Triggered from nONKEY press, assertion of CHG_WAKE, alarm/tick event or V_DDREFrising towards

> 2.6 V

Note 4 RTC_EN = 0 causes an initially unstable clock signal when entering half-current mode

The timekeeping error from the frequency variance of crystal oscillators (typ. ±20 ppm) can be

trimmed individually during the application end test via the OTP-programmable register TRIM_CLDR

by ± 242 ppm with a resolution of 1.9 ppm (1/[32768 * 16]). More advanced solutions can

dynamically correct even the temperature related oscillator frequency drift (> 100 ppm) using a

periodic temperature measurement located close to the crystal. The timekeeping correction is applied

only to the RTC calendar counter. Because of potential clock jitter issues, the 32 kHz clock signal at

the OUT_32K pin provides the original frequency of the crystal.

6.14.2 RTC Counter and Alarm

The RTC counter counts the number of 32 kHz clock periods, providing a sec, min, hrs, day, month,

and year output. Year 0 corresponds to 2000. It is able to count up to 63 years. The value of the RTC

calendar is read-/write-able via the power manager communication. A read of COUNT_S (seconds)

latches the current RTC calendar count into the registers COUNT_S through to COUNT_Y (coherent

for approx. 0.5 s), so to obtain an updated calendar value requires a read of COUNT_S. Registers

are only valid when RTC_READ status bit is asserted (assertion may take several milliseconds from

leaving POR).

There is an alarm register containing min, hrs, day, month, and year. When the RTC counter register

value corresponds to the value set in the alarm, an IRQ event is triggered and a wakeup is triggered

if the DA9063 is in POWERDOWN mode. The trigger also sets a bit in an event register to notify that

an alarm has occurred. The alarm can alternatively be asserted from a periodic ‘tick’ signal that,

depending on control TICK_TYPE, is either asserted every second or minute.

Note

After modifying TICK_TYPE or TICK_WAKE, a write to register ALARM_Y is required to activate the new

settings.

The power manager controls, ALARM_ON and TICK_ON, enable/disable the alarm and tick.

The power manager register bit MONITOR is set to 0 each time the RTC is powered up. Software

should set this bit to 1 when setting the time and date which allows software to detect a subsequent

loss of the clock. Values written into the RTC calendar and alarm registers must be valid for the

associated units of calendar time, for example less than 60 for second and minute registers, see

register description for further details.

The RTC registers SECOND_A to SECOND_D define a 32-bit seconds counter (approx. 136 years)

that can only be reset after powering up from NO-POWER mode. A read of SECOND_A (seconds

counter LSBs) latches the full 32-bit counter into the registers SECOND_A to SECOND_D (coherent

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for approx. 0.5 s), so that receiving an updated counter value requires a read of SECOND_A. After

MONITOR has been set, any host write to CRYSTAL and RTC_EN is prohibited to ensure that the

SECOND_A to SECOND_D counters are never stopped.

6.15 Adjustable Frequency Internal Oscillator

An internal oscillator provides a nominal 6.0 MHz clock that is divided down to 3.0 MHz for the buck

converters. It is divided down to 2.0 MHz to control the digital core, timers, PWM units, charge pump

and ADC. The frequency of the internal oscillator is adjusted during the initial start-up sequence of

the DA9063 to within 5% of the nominal 6.0 MHz. It can be adjusted further within ±10% via register

control OSC_FRQ. The tolerance of this frequency affects most absolute timer values and PWM

repetition rates (for example, LED and vibrator mode drivers) of the DA9063.

6.16 Reference Voltage Generation: VREF, VLNREF

The DA9063 includes a temperature-independent voltage reference circuit which is derived from an

internal band-gap reference and OTP-trimmed buffer amplifier. The output voltage on VREF is

trimmed to 1.2 V and the reference is decoupled by an external capacitor on the VREF pin. A lower

voltage instance of VREF is provided at VLNREF (0.9 V) and used for the LDOs. These pins must

not be loaded. The IREF pin provides the internally used accurate current bias and requires an

external 200 kΩ precision resistor.

6.17 Thermal Supervision

The application must ensure that the DA9063 junction temperature does not exceed 125 °C. To

protect the DA9063 from damage due to excessive power dissipation, the internal temperature is

continuously monitored. Whenever the junction temperature is higher than TEMP_WARN = 125 °C,

an E_TEMP event is asserted and an IRQ is generated for the host. If this occurs during

POWERDOWN mode, a wakeup is triggered.

The host may then check the exact junction temperature by a manual measurement on GPADC

channel 4. An 8-bit OTP register (T_OFFSET) can be used to store its offset at a known temperature

(for example 50 °C) to improve the absolute accuracy, which should then be ±7 °C of the measured

silicon die junction temperature. This T_OFFSET can be used by the host to calculate the absolute

die temperature.

The absolute die junction temperature can be calculated by the host using the result from the ADC

channel 4 measurement result and the T_OFFSET trim values.

When the junction temperature exceeds 125 °C, it is recommended to shut down optional functions

of the application allowing the DA9063 to cool. When the junction temperature increases further,

exceeding TEMP_CRIT = 140 °C, the fault flag TEMP_CRIT is asserted in the FAULT_LOG register

and the DA9063 immediately shuts down to RESET mode. The fault condition remains as long as the

junction temperature is higher than TEMP_WARN. The TEMP_CRIT flag can be evaluated by the

application after the next power up. Whenever the junction temperature exceeds TEMP_POR =

150 °C, a POR to the digital core is immediately asserted and this stops all functions of the DA9063

except for the RTC. This is necessary to prevent the possibility of permanent device damage.

6.18 Main System Rail Voltage Supervision

The supervision of the system supply V_SYSis performed by two comparators. One monitors the

under-voltage level VDD_FAULT_LOWER (fault condition indicator); the other,

VDD_FAULT_UPPER, indicates a good (valid) battery/external supply. The high-to-low transition of

the VDD_FAULT_UPPER signal is also used as a low system supply warning indicator, informing the

host via event E_VDD_WARN (or the assertion of port nVDDFAULT) that the system rail may soon

drop below the under-voltage threshold.

The VDD_FAULT_LOWER threshold is OTP-configurable and can be set via the VDD_FAULT_ADJ

control bits from 2.5 V to 3.25 V in steps of 50 mV. The VDD_FAULT_UPPER level is also OTP-

configurable and can be set via the VDD_HYST_ADJ from 100 to 450 mV higher than the

programmed VDD_FAULT_LOWER threshold.

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7

Register Map

This section provides an overview of the registers. A description of each register is provided in

Appendix A.

PAGE 0

(Hex)

REG_PAGE

PAGE_CON

Revert

WRITE_MODE

Reserved

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

System Control and Event Registers (SYSMON)

Reserved

STATUS_A

STATUS_B

STATUS_C

STATUS_D

FAULT_LOG

EVENT_A

Reserved

GPI7

Reserved

GPI6

Reserved

COMP1V2

DVC_BUSY

GPI2

WAKE

GPI1

nONKEY

GPI0

GPI5

GPI13

GPI4

GPI3

GPI11

GPI15

GPI14

GPI12

GPI10

GPI9

GPI8

LDO11_LIM

LDO8_LIM

nSHUTDOWN

EVENTS_C

E_VDD_MON

E_GPI6

LDO7_LIM

KEY_RESET

EVENTS_B

E_DVC_RDY

E_GPI5

LDO4_LIM

LDO3_LIM

Reserved

TWD_ERROR

E_nONKEY

E_WAKE

WAIT_SHUT

EVENTS_D

E_VDD_WARN

E_GPI7

TEMP_CRIT

E_SEQ_RDY

E_REG_UVOV

E_GPI4

VDD_START

E_ADC_RDY

E_LDO_LIM

E_GPI3

VDD_FAULT

E_TICK

POR

E_ALARM

E_TEMP

EVENT_B

E_COMP_1V2

E_GPI2

EVENT_C

E_GPI1

E_GPI0

EVENT_D

E_GPI15

E_GPI14

E_GPI13

E_GPI12

E_GPI11

E_GPI10

E_GPI9

E_GPI8

IRQ_MASK_A

IRQ_MASK_B

IRQ_MASK_C

IRQ_MASK_D

CONTROL_A

CONTROL_B

CONTROL_C

CONTROL_D

CONTROL_E

CONTROL_F

PD_DIS

Reserved

M _VDD_WARN

M _GP I7

Reserved

M _VDD_M ON

M _GP I6

Reserved

M _DVC_RDY

M _GP I5

M _SEQ_RDY

M _REG_UVOV

M _GP I4

M _ADC_RDY

M _LDO_LIM

M _GP I3

M _TICK

M _ALARM

M _TEM P

M _GP I1

M _nONKEY

M _WAKE

M _GP I0

M _GP I8

SYSTEM _EN

CHG_SEL

M _COM P _1V2

M _GP I2

M _GP I15

M _GP I14

M_POWER1_EN

Reserved

M _GP I13

M_POWER_EN

Reserved

M _GP I12

M _GP I11

M _GP I10

P OWER1_EN

RESET_BLINKING

M _GP I9

CP _EN

M_SYSTEM_EN

nONKEY_LOCK

OTP READ_EN

BLINK_FRQ

STANDBY

nRES_M ODE

AUTO_BOOT

P OWER_EN

WATCHDOG_DIS

DEBOUNCING

TWDSCALE

BUCK_SLOWSTART

DEF_SUP P LY

SLEW_RATE

BLINK_DUR

V_LOCK

Reserved

P M _FB3_P IN

Reserved

P M _FB2_P IN

Reserved

P M _FB1_P IN

Reserved

ECO_M ODE

Reserved

RTC_EN

WAKE_UP

P M IF_DIS

RTC_M ODE_SD

SHUTDOWN

RTC_M ODE_P D

WATCHDOG

GP I_DIS

P M CONT_DIS

OUT32K_P AUSE

BBAT_DIS

Reserved

HS2IF_DIS

GP ADC_P AUSE

GPIO Control Registers (GPIO)

GP IO1_P IN

GP IO0_P IN

GPIO0-1

GPIO2-3

GP IO1_WEN

GP IO3_WEN

GP IO5_WEN

GP IO7_WEN

GP IO9_WEN

GP IO11_WEN

GP IO13_WEN

GP IO15_WEN

GP IO7_ M ODE

GP IO15_ M ODE

CP _EN_M ODE

GP IO1_TYP E

GP IO3_TYP E

GP IO5_TYP E

GP IO7_TYP E

GP IO9_TYP E

GP IO11_TYP E

GP IO13_TYP E

GP IO15_TYP E

GP IO6_ M ODE

GP IO14_ M ODE

CORE_SW_INT

GP IO0_WEN

GP IO2_WEN

GP IO4_WEN

GP IO6_WEN

GP IO8_WEN

GP IO10_WEN

GP IO12_WEN

GP IO14_WEN

GP IO3_ M ODE

GP IO11_ M ODE

GP IO0_TYP E

GP IO2_TYP E

GP IO4_TYP E

GP IO6_TYP E

GP IO8_TYP E

GP IO10_TYP E

GP IO12_TYP E

GP IO14_TYP E

GP IO2_M ODE

GP IO10_ M ODE

GP IO3_P IN

GP IO5_P IN

GP IO7_P IN

GP IO9_P IN

GP IO11_P IN

GP IO2_P IN

GP IO4_P IN

GP IO6_P IN

GP IO8_P IN

GP IO10_P IN

GP IO12_P IN

GP IO14_P IN

GPIO4-5

GPIO6-7

GPIO8-9

GPIO10-11

GP IO13_P IN

GP IO15_P IN

GPIO12-13

GPIO14-15

GPIO_MODE0-7

GPIO_MODE8-15

SWITCH_CONT

GP IO5_ M ODE

GP IO13_ M ODE

SWITCH_SR

GP IO4_ M ODE

GP IO1_ M ODE

GP IO9_ M ODE

GP IO0_ M ODE

GP IO8_ M ODE

GP IO12_ M ODE

P ERI_SW_GP I

CORE_SW_GP I

Regulator Control Registers (REG)

VBCORE2_GP I

BCORE2_GP I

BCORE2_CONT

BCORE1_CONT

BPRO_CONT

BMEM_CONT

BIO_CONT

Reserved

CORE_SW_CONF

Reserved

CORE_SW_EN

Reserved

BCORE2_CONF

BCORE2_EN

BCORE1_EN

BPRO_EN

BMEM_EN

BIO_EN

VBCORE1_GP I

VBP RO_GP I

VBM EM _GP I

VBIO_GP I

BCORE1_GP I

BP RO_GP I

BM EM _GP I

BIO_GP I

BCORE1_CONF

BP RO_CONF

BM EM _CONF

BIO_CONF

Reserved

VBP ERI_GP I

VLDO1_GP I

VLDO2_GP I

VLDO3_GP I

VLDO4_GP I

VLDO5_GP I

VLDO6_GP I

VLDO7_GP I

VLDO8_GP I

VLDO9_GP I

VLDO10_GP I

VLDO11_GP I

BP ERI_GP I

LDO1_GP I

LDO2_GP I

LDO3_GP I

LDO4_GP I

LDO5_GP I

LDO6_GP I

LDO7_GP I

LDO8_GP I

LDO9_GP I

LDO10_GP I

LDO11_GP I

BPERI_CONT

LDO1_CONT

LDO2_CONT

LDO3_CONT

LDO4_CONT

LDO5_CONT

LDO6_CONT

LDO7_CONT

LDO8_CONT

LDO9_CONT

LDO10_CONT

LDO11_CONT

VIB

P ERI_SW_CONF

LDO1_CONF

LDO2_CONF

LDO3_CONF

LDO4_CONF

LDO5_CONF

LDO6_CONF

LDO7_CONF

LDO8_CONF

LDO9_CONF

LDO10_CONF

LDO11_CONF

Reserved

PERI_SW_EN

Reserved

BP ERI_CONF

LDO1_P D_DIS

LDO2_P D_DIS

LDO3_P D_DIS

LDO4_P D_DIS

LDO5_P D_DIS

LDO6_P D_DIS

LDO7_P D_DIS

LDO8_P D_DIS

LDO9_P D_DIS

LDO10_P D_DIS

LDO11_P D_DIS

BPERI_EN

LDO1_EN

Reserved

LDO2_EN

LDO3_EN

LDO4_EN

LDO5_EN

LDO6_EN

LDO7_EN

LDO8_EN

LDO9_EN

LDO10_EN

LDO11_EN

Reserved

VLDO5_SEL

VLDO6_SEL

VLDO7_SEL

VLDO8_SEL

VLDO9_SEL

VLDO10_SEL

VLDO11_SEL

VIB_SET

Reserved

DVC_1

VLDO3_SEL

VLDO2_SEL

Reserved

VLDO1_SEL

Reserved

VBPERI_SEL

Reserved

VBMEM_SEL

Reserved

VBPRO_SEL

Reserved

VBCORE2_SEL

VBCORE1_SEL

VBIO_SEL

DVC_2

VLDO4_SEL

Reserved

GP-ADC Control Registers (GPADC)

ADC_MAN

ADC_CONT

VSYS_MON

ADC_RES_L

ADC_RES_H

VSYS_RES

Reserved

ADC_M ODE

ADC_MAN

ADC_M UX

COM P 1V2_EN

AD3_ISRC_EN

AD2_ISRC_EN

AD1_ISRC_EN

AUTO_AD3_EN

AUTO_AD2_EN

AUTO_AD1_EN

AUTO_VSYS_EN

VSYS_M ON

ADC_RES_LSB

Reserved

ADC_RES_MSB

VSYS_RES

ADCIN1_RES

ADCIN2_RES

ADCIN3_RES

MON1_RES

MON2_RES

MON3_RES

ADCIN1_RES

ADCIN2_RES

ADCIN3_RES

MON1_RES

MON2_RES

MON3_RES

RTC Calendar and Alarm Registers (RTC)

COUNT_SEC

COUNT_MIN

COUNT_S

COUNT_MI

COUNT_H

RTC_READ

Reserved

MONITOR

COUNT_HOUR

COUNT_DAY

Reserved

COUNT_D

Reserved

COUNT_MONTH

COUNT_MO

COUNT_Y

Reserved

COUNT_YEAR

ALARM_SEC

ALARM_MIN

ALARM_TYPE

ALARM_S

ALARM_MI

ALARM_H

ALARM_D

ALARM_MO

ALARM_Y

SECOND_A

SECOND_B

SECOND_C

SECOND_D

Reserved

TICK_ON

Reserved

ALARM_HOUR

ALARM_DAY

ALARM_MONTH

Reserved

TICK_WAKE

TICK_TYPE

ALARM_YEAR

ALARM_ON

SECONDS_A

SECONDS_B

SECONDS_C

SECONDS_D

Datasheet

DA9063_2v1

23-Mar-2017

CFR0011-120-00

113 of 219

DA9063

System PMIC for Mobile Application Processors

PAGE 1

REG_PAGE

PAGE_CON

Revert

WRITE_MODE

Reserved

80

Sequencer Control Registers (SEQ)

NXT_SEQ_START

SEQ_POINTER

SEQ_TIM E

SEQ

SEQ_TIMER

ID_2_1

81

SEQ_DUM M Y

LDO2_STEP

LDO4_STEP

LDO6_STEP

LDO8_STEP

LDO10_STEP

P D_DIS_STEP

82

LDO1_STEP

LDO3_STEP

LDO5_STEP

LDO7_STEP

LDO9_STEP

LDO11_STEP

83

ID_4_3

84

ID_6_5

85

ID_8_7

86

ID_10_9

ID_12_11

ID_14_13

ID_16_15

ID_18_17

ID_20_19

ID_22_21

ID_24_23

ID_26_25

ID_28_27

ID_30_29

ID_32_31

Reserved

SEQ_A

87

88

BUCKCORE2_STEP

BUCKIO_STEP

BUCKP ERI_STEP

P ERI_SW_STEP

GP _FALL1_STEP

GP _FALL2_STEP

GP _FALL3_STEP

GP _FALL4_STEP

GP _FALL5_STEP

EN32K_STEP

BUCKCORE1_STEP

BUCKP RO_STEP

BUCKM EM _STEP

CORE_SW_STEP

GP _RISE1_STEP

GP _RISE2_STEP

GP _RISE3_STEP

GP _RISE4_STEP

GP _RISE5_STEP

WAIT_STEP

89

8A

8B

8C

8D

8E

8F

90

91

92

Reserved

93

Reserved

94

P OWER_END

SYSTEM _END

M AX_COUNT

95

P ART_DOWN

SEQ_B

96

WAIT_DIR

WAIT_TIM E

STABILISATION_TIM E

WAIT

TIM E_OUT

OUT_CLOCK

WAIT_M ODE

WAIT_TIM E

CRYSTAL

97

EN_32K

RESET

OUT_32K_EN

RTC_CLOCK

DELAY_M ODE

98

RESET_EVENT

RESET_TIM ER

99

Regulator Setting Registers (REG)

BM EM _ILIM

BP ERI_ILIM

BIO_ILIM

BUCK_ILIM_A

BUCK_ILIM_B

BUCK_ILIM_C

BCORE2_CONF

BCORE1_CONF

BPRO_CONF

BIO_CONF

BMEM_CONF

BPERI_CONF

VBCORE2_A

VBCORE1_A

VBPRO_A

VBMEM_A

VBIO_A

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

AA

AB

AC

AD

AE

AF

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

BA

BB

BC

BD

BE

BF

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

BP RO_ILIM

BCORE2_ILIM

BCORE2_P D_DIS

BCORE1_P D_DIS

BCORE1_ILIM

BCORE2_M ODE

BCORE1_M ODE

BP RO_M ODE

BIO_M ODE

BCORE2_FB

BCORE1_FB

BP RO_FB

BIO_FB

Reserved

BP RO_P D_DIS

BIO_P D_DIS

BP RO_VTT_EN

Reserved

BP RO_VTTR_EN

Reserved

BM EM _ M ODE

BP ERI_ M ODE

BM EM _FB

BP ERI_FB

BM EM _P D_DIS

BP ERI_P D_DIS

Reserved

VBCORE2_A

VBCORE1_A

VBP RO_A

VBM EM _A

VBIO_A

BCORE2_SL_A

BCORE1_SL_A

BCP RO_SL_A

BM EM _SL_A

BIO_SL_A

VBP ERI_A

VBPERI_A

VLDO1_A

BP ERI_SL_A

LDO1_SL_A

LDO2_SL_A

LDO3_SL_A

LDO4_SL_A

LDO5_SL_A

LDO6_SL_A

LDO7_SL_A

LDO8_SL_A

LDO9_SL_A

LDO10_SL_A

LDO11_SL_A

BCORE2_SL_B

BCORE1_SL_B

BCP RO_SL_B

BM EM _SL_B

BIO_SL_B

VLDO1_A

Reserved

VLDO2_A

VLDO3_A

VLDO4_A

VLDO3_A

VLDO4_A

VLDO5_A

VLDO6_A

VLDO7_A

VLDO8_A

VLDO9_A

VLDO10_A

VLDO11_A

VLDO5_A

Reserved

VLDO6_A

VLDO7_A

VLDO8_A

VLDO9_A

VLDO10_A

VLDO11_A

VBCORE2_B

VBCORE1_B

VBP RO_B

VBM EM _B

VBIO_B

VBCORE2_B

VBCORE1_B

VBPRO_B

VBMEM_B

VBIO_B

VBP ERI_B

VBPERI_B

VLDO1_B

BP ERI_SL_B

LDO1_SL_B

LDO2_SL_B

LDO3_SL_B

LDO4_SL_B

LDO5_SL_B

LDO6_SL_B

LDO7_SL_B

LDO8_SL_B

LDO9_SL_B

LDO10_SL_B

LDO11_SL_B

VLDO1_B

VLDO2_B

Reserved

VLDO2_B

VLDO3_B

VLDO4_B

VLDO3_B

VLDO4_B

VLDO5_B

VLDO6_B

VLDO7_B

VLDO8_B

VLDO9_B

VLDO10_B

VLDO11_B

VLDO5_B

Reserved

VLDO6_B

VLDO7_B

VLDO8_B

VLDO9_B

VLDO10_B

VLDO11_B

Backup Battery Charger Control Registers (BBAT)

GPIO PWM (LED)

BCHG_ISET

BCHG_VSET

BBAT_CONT

GP O11_P WM

GPO11_LED

GPO14_LED

GPO15_LED

GP O11_DIM

GP O14_DIM

GP O15_DIM

GP O14_P WM

GP O15_P WM

GP-ADC Threshold Registers (GPADC)

ADCIN1_CUR

ADC_CONT

AUTO1_HIGH

AUTO1_LOW

AUTO2_HIGH

AUTO2_LOW

AUTO3_HIGH

AUTO3_LOW

ADCIN3_DEB

ADCIN2_DEB

ADCIN1_DEB

ADCIN3_CUR

AUTO1_HIGH

AUTO1_LOW

AUTO2_HIGH

AUTO2_LOW

AUTO3_HIGH

AUTO3_LOW

Datasheet

DA9063_2v1

23-Mar-2017

CFR0011-120-00

114 of 219

DA9063

System PMIC for Mobile Application Processors

PAGE 2

REG_PAGE

PAGE_CON

Revert

WRITE_MODE

Reserved

100

101

102

103

04F

104

105

106

107

108

109

10A

10B

10C

10D

10E

10F

110

111

112

113

114

115

116

117

118

119

11A

11B

11C

11D

11E

11F

11E

11F

120

121

122

123

124

125

126

127

128

129

12A

12B

12C

12D

12E

12F

130

131

132

133

134

135

136

137

138

139

13A

13B

13C

13D

OTP (OTP)

OTP _GP _LOCK

OTP_CONT

OTP_ADDR

OTP_DATA

GP _WRITE_DIS

OTP _CONF_LOCK

OTP _AP P S_LOCK

PC_DONE

OTP_APPS_RD

OTP_GP_RD

OTP_TIM

OTP_ADDR

OTP_DATA

Customer Trim and Configuration Registers (APPS)

T_OFFSET

INTERFACE

CONFIG_A

CONFIG_B

CONFIG_C

CONFIG_D

CONFIG_E

CONFIG_F

CONFIG_G

CONFIG_H

CONFIG_I

IF_BASE_ADDR

R/W_P OL

CP HA

CP OL

nCS_P OL

P M _I_V

IF_TYP E

CHG_CLK_M ODE

BP ERI_CLK_INV

GP _FB3_TYP E

P ERI_SW_AUTO

LDO11_BYP

P M _IF_HSM

P M _IF_FM P

P M _IF_V

IRQ_TYP E

P M _O_TYP E

P M _O_V

VDD_HYST_ADJ

VDD_FAULT_ADJ

LDO1_TRACK

BIO_CLK_INV

GP _FB2_TYP E

CORE_SW_AUTO

LDO8_BYP

BM EM _CLK_INV

FORCE_RESET

BP ERI_AUTO

LDO7_BYP

BP RO_CLK_INV

HS_IF_HSM

BIO_AUTO

BCORE1_CLK_INV

HS_IF_FM P

BUCK_DISCHG

SYSTEM _EN_RD

BP P RO_AUTO

LDO11_AUTO

nIRQ_M ODE

GP I_V

BM EM _AUTO

LDO3_BYP

BCORE2_AUTO

LDO10_AUTO

LDO2_AUTO

LDO8_M ODE

BCORE1_AUTO

LDO9_AUTO

LDO1_AUTO

P WM _CLK

LDO4_BYP

LDO8_AUTO

BUCK_M ERGE

LDO_SD

LDO7_AUTO

BCORE1_OD

INT_SD_M ODE

IF_TO

LDO6_AUTO

LDO5_AUTO

BP RO_OD

LDO4_AUTO

LDO3_AUTO

BCORE2_OD

BCORE_M ERGE

GP I14_15_SD

M ERGE_SENSE

nONKEY_SD

nONKEY_P IN

KEY_DELAY

GP IO0_P UP D

HOST_SD_M ODE

KEY_SD_M ODE

RESET_DURATION

SHUT_DELAY

CONFIG_J

CONFIG_K

CONFIG_L

CONFIG_M

CONFIG_N

MON_REG_1

MON_REG_2

MON_REG_3

MON_REG_4

Reserved

IF_RESET

GP I7_P UP D

GP I6_P UP D

GP I5_P UP D

GP IO13_P UP D

Reserved

GP I4_P UP D

GP IO12_P UP D

Reserved

GP I3_P UP D

GP IO11_P UP D

Reserved

M ON_DEB

LDO4_M ON_EN

Reserved

BIO_M ON_EN

Reserved

GP IO2_P UP D

GP IO10_P UP D

Reserved

GP IO1_P UP D

GP IO9_P UP D

Reserved

GP IO15_P UP D

GP IO14_P UP D

GP IO8_P UP D

Reserved

OSC_FREQ

Reserved

UVOV_DELAY

M ON_M ODE

M ON_THRES

M ON_RES

LDO3_M ON_EN

LDO11_M ON_EN

BP RO_M ON_EN

Reserved

LDO8_M ON_EN

Reserved

LDO7_M ON_EN

Reserved

LDO6_M ON_EN

Reserved

BP ERI_M ON_EN

Reserved

LDO5_M ON_EN

Reserved

BM EM _M ON_EN

Reserved

LDO2_M ON_EN

LDO10_M ON_EN

BCORE2_M ON_EN

Reserved

LDO1_M ON_EN

LDO9_M ON_EN

BCORE1_M ON_EN

Reserved

MONA9_IDX

MONA8_IDX

MONA10_IDX

MON_REG_5

MON_REG_6

TRIM_CLDR

Reserved

TRIM _CLDR

General Purpose Registers (GP)

GP _0

GP_ID_0

GP_ID_1

GP_ID_2

GP_ID_3

GP_ID_4

GP_ID_5

GP_ID_6

GP_ID_7

GP_ID_8

GP_ID_9

GP_ID_10

GP_ID_11

GP_ID_12

GP_ID_13

GP_ID_14

GP_ID_15

GP_ID_16

GP_ID_17

GP_ID_18

GP_ID_19

GP _1

GP _2

GP _3

GP _4

GP _5

GP _6

GP _7

GP _8

GP _9

GP _10

GP _11

GP _12

GP _13

GP _14

GP _15

GP _16

GP _17

GP _18

GP _19

Debug Registers (DEB)

Reserved

MISC_SUPP

Reserved

CRYSTAL_OK

Reserved

OTP_CLK_ON

Reserved

Most register bits are reset to defaults (zero in most cases) when powering up from RESET mode.

An exceptions is for example FAULT_LOG that is not loaded from OTP. Register fields shown in

BOLD are loaded from OTP.

PAGE 3

REG_PAGE

PAGE_CON

Revert

WRITE_MODE

Reserved

180

181

182

183

184

Chip ID, Trim and Production Test (PROD)

DEV_ID

DEVICE_ID

VARIANT_ID

CUSTOMER_ID

CONFIG_ID

MRC

VRC

CUST_ID

CONFIG_REV

Datasheet

DA9063_2v1

23-Mar-2017

CFR0011-120-00

115 of 219

DA9063

System PMIC for Mobile Application Processors

8

Application Information

The following recommended components are examples selected from requirements of a typical

application. The electrical characteristics (for example, supported voltage/current range) have to be

cross-checked and component types may need to be adapted from the individual needs of the target

circuitry.

8.1 Capacitor Selection

Ceramic capacitors are used as bypass capacitors at all VDD and output rails. When selecting a

capacitor, especially for types with high capacitance at smallest physical dimension, the DC bias

characteristic has to be taken into account. On the V_SYSmain supply rail a minimum distributed

capacitance of 40 μF (actual capacitance after voltage and temperature derating) is required. For

example, a typical design might use:

●

22 μF within 1.5 mm of each BUCKCORE1, BUCKCORE2 and BUCKPRO supply pin.

10 μF within 1.5 mm of each BUCKPERI, BUCKIO and BUCKMEM supply pin or 1 μF x 22 μF if

all are attached to a PCB power/split plane.

●

2 μF x 1 μF shared by all VDD_LDOx pins if they are all close together, for example, all attached

to a power/split plane.

●

1 μF close to the V_SYSpin.

Buck output capacitors should be close to the buck inductors.

The amount of decoupling required will be dependent on the specific application.

Table 50: Recommended Capacitor Types

Rated

Tol.

(%)

Height

(mm)

Temp.

Char.

Application

Value

Size

Voltage

(V)

Type (Murata/Samsung)

VLDO1, VLDO5

1.0 µF

± 10

± 20

0402

0.55

X5R ±15 %

10

GRM155R61A105KE15

VDDCORE,

VLDOA,

VLDOB,

VLDOC,

2.2 µF

0402

6.3

GRM155R60J225ME95

VLDOD,

VLDOE, VREF,

VLNREF, VSYS

± 20

0805

0402

0805

0603

0.95

0.5

X5R ±15 %

6.3

4.0

GRM219R60J226M***

CL05A226MR5NZNC

GRM219R60G476M***

CL10A476MR8NZN

22 µF

47 µF

VBUCKPER,

VBUCKIO,

VBUCKMEM,

VSYS

0.95

0.8

GRM188R60J226MEA0

Note 1

± 20

0603

1.0

X5R ±15 %

6.3

22 µF

47 µF

VBUCKCORE1

and 2,

VBUCKPRO

(using full-

± 20

± 10

0402

0805

0603

0402

0.5

0.95

1.45

0.8

X5R ±15 %

4.0

6.3

10

CL05A226MR5NZNC

GRM219R60G476M***

GRM21BR60G476ME15

CL10A476MR8NZN

current mode)

10 µF

1.0 µF

470 nF

0.95

0.55

GRM188R60J106ME84

GRM155R61A105KE15

GRM155R61A474KE15

VSYS

VBBAT

10

VDDCORE,

VREF, VLNREF

2.2 µF

± 20

0402

0.55

X5R ±15 %

6.3

GRM155R60J225ME95

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Rated

Voltage

(V)

Tol.

(%)

Height

(mm)

Temp.

Char.

Application

Value

Size

Type (Murata/Samsung)

XIN, XOUT

V_CP

12 pF

47 nF

± 5

0402

0.55

U2J

50

10

GRM1557U1H120JZ01

GRM155R71A473KA01

± 10

X7R ±15 %

Note 1 For output voltages > 1.4 V Murata GRM219R60J226M*** is recommended.

8.2 Backup Device

The backup battery charger supports Lithium coin cells as well as Supercaps/Goldcaps. The RTC will

require approximately 1.5 µA between 3.1 V and 2 V for each hour that the RTC should stay alive

with the main supply removed. The choice of backup device is dependent on application

requirements.

Table 51: Example Backup Devices

Type

Size (mm)

4.8 (dia.) x 2.1

4.8 (dia.) x 1.4

6.8 (dia.) x 1.4

Manufacturer

Panasonic

Korchip

Lithium Battery (rechargeable) ML421, 2.3 mAh, 3.0 V

Starcap SC SM 2R8, 0.1 F, 2.8 V

Lithium Battery (rechargeable) ML614, 3.4 mAh, 3.0 V

Panasonic

8.3 Inductor Selection

Inductors should be selected based upon the following parameters:

●

Rated maximum current: Usually a coil provides two current limits: ISAT of an Inductor specifies

the current required to cause a reduction in the Inductance by a specified amount, typically 30%,

IRMS of an Inductor specifies the current required to affect a temperature rise of a maximum

specified amount.

●

DC resistance: Critical to converter efficiency at high current and should therefore be minimised.

ESR at the buck switching frequency: Critical to converter efficiency in PFM mode and should

therefore be minimised.

●

Inductance: Given by converter electrical characteristics; 1.0 µH for all DA9063 switched-mode

step-down converters.

Table 52: Recommended Inductor Types

Application

Value Tol.

ISAT

(A)

IRMS

(A)

DCR

(Typ.)

(mΩ)

Size (mm)

Type

(µH)

(%)

±30

±20

Toko

1285AS-H-1R0N

2.7

2.3

55

60

2.0x1.6x1.0

BUCKPERI,

BUCKMEM,

BUCKIO,

BUCKCORE1,

BUCKCORE2

Tayo Yuden

MAKK2016T1R0M

(Reference)

1.0

2.65

2.45

TDK

±20

±30

±20

2.9

3.4

3.6

2.2

3.0

3.1

60

45

2.0x1.6x1.0

2.5x2.0x1.0

2.5x2.0x1.2

TFM201610A-1R0M

Toko

1269AS-H-1R0N

BUCKPRO,

BUCKCORE1

and 2 using full-

current mode or

merged

Tayo Yuden

MAMK2520T1R0M

1.0

Toko

1239AS-H-1R0N

(Reference)

BUCKMEM/

BUCKIO

±20

3.8

3.5

45

2.5x2.0x1.2

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Application

Value Tol.

ISAT

(A)

IRMS

(A)

DCR

(Typ.)

(mΩ)

Size (mm)

Type

(µH)

(%)

Toko

1276AS-H-1R0N

±30

±20

3.9

3.5

3.1

2.5

48

54

52

3.2x2.5x1.0

2.5x2.0x1.0

3.0x3.0x1.2

TDK

TFM252010A-1R0M

Cyntec

PST031B-1R0MS

3.35

Coilcraft

±20

5.4

11.0

11

4.0x4.0x2.1

XFL4020-102ME (Ref.high

current)

8.4 Resistors

Table 53: Recommended Resistor Types

Application

Value

Size

Tolerance

±1%

P_MAX

Type

IREF bias current reference

200 kΩ

0402

100 mW

Panasonic

ERJ2RKF2003x

8.5 External Pass Transistors

Table 54: Recommended External Pass Transistor Types

Application

Package

Type

BUCK Rail Switches

WLCSP 1.6x1.6x0.55 mm

Fairchild FDME410NZT

8.6 Crystal

The Real Time Clock module requires an external 32.768 kHz crystal. For correct component

selection, the effective load capacitance must to be taken into account: this includes both external

capacitors on pins XIN and XOUT in series combination, plus the PCB and DA9063 stray

capacitances. For example, if two 12 pF external capacitors are used, giving a series combination of

6 pF, and the stray capacitances are 3 pF, then a crystal type that specifies a load capacitance of

9 pF should be chosen. Different stray capacitances may require different external capacitors and/or

a different crystal type. Furthermore, the series resistance of the crystal must not exceed 100 kΩ.

Table 55: Example Crystal Type

Type

Size

Manufacturer

CC7V-T1A 32.768 kHz 9.0 pF ±30 ppm

3.2x1.5x0.9 mm

Micro Crystal

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8.7 Layout Guidelines

8.7.1

●

General Recommendations

Appropriate trace width and quantity of vias should be used for all power supply paths.

Too high trace resistances can prevent the system from achieving the best performance, for

example, the efficiency and the current ratings of switch-mode converters and charger might be

degraded. Furthermore, the PCB may be exposed to thermal hot spots, which can lead to critical

overheating due to the positive temperature coefficient of copper.

Special care must be taken with the DA9063 pad connections. The traces of the outer row should

be connected with the same width as the pads and should become wider as soon as possible.

For supply pins in the second row, connection to an inner board layer is recommended

(depending on the maximum current two or more vias might be required).

●

A common ground plane should be used, which allows proper electrical and thermal

performance. Noise sensitive references such as the VREF/VLNREF capacitors and IREF

resistor should be referred to a silent ground which is connected at a star point underneath or

close to the DA9063 main ground connection.

●

Generally, all power tracks with discontinuous/high currents should be kept as short as possible.

Noise sensitive analog signals such as feedback lines or crystal connections should be kept

away from traces carrying pulsed analog or digital signals. This can be achieved by separation

(distance) or shielding with quiet signals or ground traces.

8.7.2

LDOs and Switched Mode Supplies

●

The placement of the distributed capacitors on the V_SYSrail must ensure that all VDD inputs –

and especially to the V_SYSpin, the buck converters and LDOs – are connected to a bypass

capacitor close to the pads. It is recommended placing at least two 1 µF capacitors close to the

LDO supply pads and at least one 10 µF close to the buck VDD rail.

Using a local power plane underneath the chip for V_SYSmight be considered.

●

Transient current loops in the area of the switched mode converters should be minimised.

The common references (IREF resistor, VREF/VLNREF capacitors) should be placed close to

the DA9063 and cross coupling to any noisy digital or analog trace must be avoided.

●

Output capacitors of the LDOs can be placed close to the input pins of the supplied devices

(remote from the DA9063) .

Care must be taken with trace routing to ensure that no current is carried on feedback lines of the

buck output voltages V_BUCK

.

The inductor placement is less critical since parasitic inductances have negligible effect.

8.7.3

Crystal Oscillator

●

The crystal and its load capacitors should be placed as close as possible to the IC with short and

symmetric traces.

●

The traces must be isolated from noisy signals, especially from clocked digital ones. Ideally the

lines should be buried between two ground layers, surrounded by additional ground traces.

8.7.4

Thermal Connection, Land Pad, and Stencil Design

●

The DA9063 provides a central ground area of balls, which are soldered to the PCB’s central

ground pad. This PCB ground pad must be connected with as many vias and as direct as

possible to the PCB’s main ground plane in order to achieve good thermal performance.

●

Solder mask openings for the ball landing pads must be arranged to prohibit solder balls flowing

into vias.

For further PCB layout guidance, see PCB Layout Guidelines [3].

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9

Definitions

9.1 Power Dissipation and Thermal Design

When designing with the DA9063, consideration must be given to power dissipation as the level of

integration of the device can result in high power when all functions are operating with high battery

voltages. Exceeding the package power dissipation capabilities results in the internal thermal sensor

shutting down the device until it has sufficiently cooled.

The package includes a thermal management paddle to improve heat spreading into the PCB.

For Linear Regulators:

Linear regulators operating with a high current and high differential voltage between input and output

dissipate the following power:

(

)

ꢄꢋꢄꢌ_ꢈꢉꢊ

ꢀꢁꢂꢂ

ꢃꢄ ꢅ ꢇꢄꢅ

ꢁꢆ

ꢈꢉꢊ

Example: a regulator supplying 150 mA at 2.8 V from a fully-charged lithium battery (VDD=4.1 V):

( )

ꢃꢄ ꢍꢎꢏꢅ ꢇ ꢄꢐꢎꢑꢅ ꢄꢋ ꢄꢒꢎꢏꢓꢔꢄ ꢃ ꢏꢕꢓꢖꢗ

ꢀꢁꢂꢂ

For Switching Regulators:

ꢈꢉꢊ

ꢃ _ꢁꢆꢋ ꢘꢙꢙꢚꢛꢚꢜꢝꢛꢞ

Therefore,

ꢀꢁꢂꢂ

ꢃ _ꢁꢆꢇ

ꢈꢉꢊ

ꢃ

ꢇ

ꢈꢉꢊ

ꢀꢁꢂꢂ

ꢘꢙꢙꢚꢛꢚꢜꢝꢛꢞ

ꢏ

ꢃ ꢋ ꢟ

ꢇ ꢏꢠ

ꢀꢁꢂꢂ

ꢈꢉꢊ

ꢘꢙꢙꢚꢛꢚꢜꢝꢛꢞ

ꢏ

ꢃ ꢌ_ꢈꢉꢊꢋ ꢅ_ꢈꢉꢊꢋ ꢟ

ꢇ ꢏꢠ

ꢀꢁꢂꢂ

ꢘꢙꢙꢚꢛꢚꢜꢝꢛꢞ

Example: an 85 % efficient buck converter supplying 1.2 V at 400 mA:

ꢏ

ꢀꢁꢂꢂ

ꢃ ꢏꢎꢐꢅ ꢋ ꢒꢎꢍꢔ ꢋ ꢟ

ꢇ ꢏꢠ ꢃ ꢑꢓꢖꢗ

ꢒꢎꢑꢓ

As the DA9063 has multiple regulators, each supply must be separately considered and their powers

summed to give the total device dissipation (current drawn from the reference and control circuitry

can be considered negligible in these calculations).

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9.2 Regulator Parameter - Dropout Voltage

In the DA9063, a regulator’s dropout voltage is defined as the minimum voltage differential between

the input and output voltages whilst regulation still takes place. Within the regulator, voltage control

takes place across a PMOS pass transistor and, when entering the dropout condition, the transistor

is fully turned on and therefore cannot provide any further voltage control. When the transistor is fully

turned on, the output voltage tracks the input voltage and regulation ceases. As the DA9063 is a

CMOS device and uses a PMOS pass transistor, the dropout voltage is directly related to the on-

resistance of the device. In the device, the pass transistors are sized to provide the optimum balance

between required performance and silicon area. By employing a 0.25 µm process, Dialog

Semiconductor is able to achieve very small pass transistor sizes for superior performance.

ꢅ_{ꢀꢡꢈꢢꢈꢉꢊ}ꢃ ꢅ ꢇ ꢅ ꢃ ꢣ_ꢀꢂꢈꢆꢋ ꢌ_ꢈꢉꢊ

ꢁꢆ

ꢈꢉꢊ

When defining dropout voltage, it is specified in relation to a minimum acceptable change in output

voltage. For example, all Dialog Semiconductor regulators have dropout voltage defined as the point

at which the output voltage drops 10 mV below the output voltage at the minimum guaranteed

operating voltage. The worst case conditions for dropout are high temperature (highest on-resistance

for the internal pass device) and maximum current load.

9.3 Regulator Parameter - Power Supply Rejection

Power supply rejection (PSRR) is especially important in the supplies to the RF and audio parts of

the telephone. In a TDMA system such as GSM, the 217 Hz transmit burst from the power amplifier

results in significant current pulses being drawn from the battery. These can peak at up to 2 Amps

before reaching a steady state of 1.4 Amps (see below). Due to the battery having a finite internal

resistance (typically 0.5 Ω), these current peaks induce ripple on the battery voltage of up to 500 mV.

Since the supplies to the audio and RF are derived from this supply, it is essential that this ripple is

removed otherwise it would show as a 217 Hz tone in the audio and could also affect the transmit

signal. Power supply rejection should always be specified under worst case conditions – when the

battery is at its minimum operating voltage and when there is minimum headroom available due to

dropout.

9.4 Regulator Parameter - Line Regulation

Static line regulation is a measurement that indicates a change in the regulator output voltage, ∆Vreg

(regulator operating with a constant load current), in response to a change in the input voltage, ∆Vin.

Transient line regulation is a measurement of the peak change, ∆Vreg, in regulated voltage seen

when the line input voltage changes.

4.6ms TDMA frame rate

V_bat

577µS

V_reg

Figure 41: Line Regulation

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9.5 Regulator Parameter - Load Regulation

Static load regulation is a measurement that indicates a change in the regulator output voltage,

∆Vreg, in response to a change in the regulator loading, ∆load, whilst the regulator input voltage

remains constant. Transient load regulation is a measurement of the peak change in regulated

voltage, ∆Vreg, seen when the regulator load changes.

I_{load max}

I_{load min}

V_reg

Figure 42: Load Regulation

Please contact Dialog Semiconductor for latest application information on the DA9063 and other

power management devices.

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10 Ordering Information

The ordering number consists of the part number followed by a suffix indicating the packing method.

For details and availability, please consult Dialog Semiconductor’s customer portal or your local sales

representative.

Table 56: Ordering Information

Part Number

Package

Shipment Form

Pack Quantity

Consumer: 0.30 mm ball diameter, RT production testing

DA9063-xxHK1

DA9063-xxHK2

100 VFBGA, 8.0 mm x 8.0 mm x 1.0 mm,

0.8 mm pitch, Pb-free/green

Tray

T&R

260

100 VFBGA, 8.0 mm x 8.0 mm x 1.0 mm,

0.8 mm pitch, Pb-free/green

3000

Automotive AEC-Q100 Grade 3: 0.30 mm ball diameter, RT production testing

DA9063-xxHK1-A

100 VFBGA, 8.0 mm x 8.0 mm x 1.0 mm,

0.8 mm pitch, Pb-free/green

Tray

260

DA9063-xxHK2-A

100 VFBGA, 8.0 mm x 8.0 mm x 1.0 mm,

0.8 mm pitch, Pb-free/green

T&R

3000

Automotive AEC-Q100 Grade 3: 0.45 mm ball diameter, RT production testing

DA9063-xxHO1-A

100 TFBGA, 8.0 mm x 8.0 mm x 1.2 mm,

0.8 mm pitch, Pb-free/green

Tray

260

DA9063-xxHO2-A

100 TFBGA, 8.0 mm x 8.0 mm x 1.2 mm,

0.8 mm pitch, Pb-free/green

T&R

3000

Automotive AEC-Q100 Grade 3: 0.45 mm ball diameter, HT production testing

DA9063-xxHO1-AT

100 TFBGA, 8.0 mm x 8.0 mm x 1.2 mm,

0.8 mm pitch, Pb-free/green

Tray

260

DA9063-xxHO2-AT

100 TFBGA, 8.0 mm x 8.0 mm x 1.2 mm,

0.8 mm pitch, Pb-free/green

T&R

3000

Variants Ordering Information

DA9063 supports delivery of variants indicated by xx in the Part number above, please contact your

local Dialog Semiconductor office or representative to discuss requirements.

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Appendix A Register Descriptions

This appendix describes the registers summarized in Section 7.

A.1 Register Page Control

Table 57: PAGE_CON

Register Address

Bit

Type

Label

Description

0x00 PAGE_CON

7

RW

REVERT

Resets REG_PAGE to 00 after read/write

access has finished

6

RW

WRITE_MODE

2-WIRE multiple write mode

0: Page Write Mode

1: Repeated Write Mode

5:3

2:0

RW

Reserved

REG_PAGE

000: Selects Register 0x01 to 0x3F

001: Selects Register 0x81 to 0xCF

010: Selects Register 0x101 to 0x13F

011: Reserved for production and test

The PAGE_CON register is located at address 0x00 of each register page (0x00 and 0x80). Each of

the control interfaces (4-WIRE and the two 2-WIRE) provides an individual instance of the

PAGE_CON register.

A.2 Register Page 0

A.2.1

Power Manager Control and Monitoring

The STATUS register reports the current value of the various signals at the time that it is read out. All

the status bits have the same polarity as their corresponding signals.

Table 58: STATUS_A

Register Address

Bit

7:4

3

Type

R

Label

Reserved

COMP1V2

DVC

Description

0x01 STATUS_A

R

Output state of 1.2 V comparator

2

R

Asserted as long as at least one DVC supply

performs voltage ramping

1

0

R

WAKE

CHG_WAKE level

nONKEY

Asserted as long nONKEY is pressed (low

level)

Table 59: STATUS_B

Register Address

Bit

Type

R

Label

GPI7

GPI6

GPI5

GPI4

GPI3

GPI2

Description

GPI7 level

0x02 STATUS_B

7

6

5

4

3

2

R

GPI6 level

R

GPI5 level

R

GPI4 level

R

GPI3 level

R

GPI2 level or ADCIN3 threshold indicator (1

when overriding high limit)

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Register Address

Bit

Type

Label

Description

1

R

GPI1

GPI1 level or ADCIN2 threshold indicator (1

when overriding high limit)

0

R

GPI0

GPI0 level or ADCIN1 threshold indicator (1

when overriding high limit)

Table 60: STATUS_C

Register Address

Bit

Type

R

Label

GPI15

GPI14

GPI13

GPI12

GPI11

GPI10

GPI9

Description

GPI15 level

0x03 STATUS_C

7

6

5

4

3

2

1

0

R

GPI14 level

R

GPI13/ EXT_WAKEUP/READY level

GPI12/nVDD_FAULT/VDD_MON level

GPI11 level

R

GPI10/PWR1_EN level

GPI9/PWR_EN level

GPI8/SYS_EN level

R

GPI8

Table 61: STATUS_D

Register Address

Bit

Type

Label

Description

0x04 STATUS_D

7

R/W

LDO11_LIM

Asserted as long LDO11 hits its over-current

limit

6

R/W

LDO8_LIM

LDO7_LIM

LDO4_LIM

LDO3_LIM

Reserved

Asserted as long LDO8 hits its over-current

limit

5

Asserted as long LDO7 hits its over-current

limit

4

Asserted as long LDO4 hits its over-current

limit

3

Asserted as long LDO3 hits its over-current

limit

2:0

Table 62: FAULT_LOG

Register Address

Bit

Type

Label

Description

Note 1

0x05 FAULT_LOG

7

6

R

WAIT_SHUT

Power down by time out of ID WAIT

nSHUT_DOWN Power down by assertion of port nOFF,

nSHUTDOWN

5

R

KEY_RESET

Power down from a long press of nONKEY or

GPIO14/15

4

3

R

TEMP_CRIT

VDD_START

Junction over-temperature detected

Power down by V_SYSunder-voltage detect before or

within 16 seconds after entering ACTIVE mode

2

1

R

VDD_FAULT

POR

Power down by V_SYSunder-voltage detect

DA9063 starts up from no power or RTC/DELIVERY

mode

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Register Address

Bit

Type

Label

Description

Note 1

0

R

TWD_ERROR

Watchdog time violated

Note 1 Cleared from the host by writing back the read value.

The EVENT registers hold information about events that have occurred in the DA9063. Events are

triggered by a change in the status registers that contains the status of monitored signals. When an

EVENT bit is set in the event register the nIRQ signal is asserted (unless the nIRQ is to be masked

by a bit in the IRQ mask register). The nIRQ is also masked during the power-up sequence and is

not released until the event registers have been cleared. The IRQ triggering event register is cleared

from the host by writing back its read value. The event registers may be read in page/repeated mode.

New events that occur during clearing are delayed before they are passed to the event register,

ensuring that the host controller does not miss them.

Table 63: EVENT_A

Register Address

Bit

Type

Label

Description

0x06

EVENT_A

7

6

5

4

R

EVENTS_D

EVENTS_C

EVENTS_B

Asserted when register EVENT_B to EVENT_D have

at least one event bit asserted

Asserted when register EVENT_B to EVENT_C have

at least one event bit asserted

Asserted when register EVENT_B has at least one

event bit asserted

R

E_SEQ_RDY Sequencer reached final position caused event

E_ADC_RDY ADC manual conversion result ready caused event

Note 1

3

2

1

0

R

Note 1

R

E_TICK

E_ALARM

E_nONKEY

RTC tick caused event

RTC alarm caused event

nONKEY caused event

Note 1

R

Note 1

R

Note 1

Note 1 Cleared from the host by writing back the read value.

Table 64: EVENT_B

Register Address

Bit

Type

Label

Description

Note 1

0x07

EVENT_B

7

6

R

E_VDD_WARN

E_VDD_MON

V_SYSdropped below VDD_FAULT_UPPER

threshold

R

V_SYSless or higher than VSYS_MON threshold

caused event

5

4

R

E_DVC_RDY

Finish of all DVC voltage ramping event

E_REG_UVOV

Event triggered from a monitored regulator

voltage being out of selected range or from

new regulator voltage measurement being

available (depends on settings of

MON_MODE)

3

R

E_LDO_LIM

LDO3, 4, 7, 8 or 11 current limit exceeded for

more than 10 ms

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Register Address

Bit

Type

Label

Description

Note 1

2

1

0

R

E_COMP1V2

E_TEMP

1.2 V comparator caused event

Junction high temp caused event

Detected rising edge on CHG_WAKE

E_WAKE

Note 1 Cleared from the host by writing back the read value.

Table 65: EVENT_C

Register Adress

Bit

Type

Label

Description

Note 1

0x08

EVENT_C

7

6

5

4

3

2

R

E_GPI7

E_GPI6

E_GPI5

E_GPI4

E_GPI3

E_GPI2

GPI event according to active state setting

GPI event according to active state setting /

ADCIN3 high / low threshold exceeded caused

event

1

0

R

E_GPI1

E_GPI0

GPI event according to active state setting /

ADCIN2 high / low threshold exceeded caused

event

GPI event according to active state setting /

ADCIN1 high / low threshold exceeded caused

event

Note 1 Cleared from the host by writing back the read value.

Table 66: EVENT_D

Register Address

Bit

Type

Label

Description

Note 1

0x09

EVENT_D

7

6

R

E_GPI15

E_GPI14

GPI event according to active state setting

GPI event according to active state

setting/Event caused from host addressing

HS-2-WIRE interface

5

4

3

2

R

E_GPI13

E_GPI12

E_GPI11

E_GPI10

GPI event according to active state setting

GPI/PWR1_EN event according to active state

setting

1

0

R

E_GPI9

E_GPI8

GPI/PWR_EN event according to active state

setting

GPI/SYS_EN event according to active state

setting

Note 1 Cleared from the host by writing back the read value.

The nIRQ line is released only when all events have been cleared from the host processor by writing

the read value into all registers with an asserted event bit.

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System PMIC for Mobile Application Processors

Table 67: IRQ_MASK_A

Register Address

Bit

7:5

4

Type

R/W

Label

Description

Reserved

0x0A

IRQ_MASK_A

M_SEQ_RDY

M_ADC_RDY

Mask nIRQ from finishing power sequencing

3

Mask ADC manual conversion result ready

caused nIRQ

M_TICK

M_ALARM

M_nONKEY

2

1

0

R/W

Mask RTC tick caused nIRQ

Mask RTC alarm caused nIRQ

Mask nONKEY caused nIRQ

Table 68: IRQ_MASK_B

Register Address

Bit

Type

Label

Description

M_VDD_WARN

0x0B

IRQ_MASK_B

7

R/W

Mask VDDFAULT _UPPER comparator

triggered event

M_VDD_MON

M_DVC_RDY

M_REG_UVOV

6

5

4

R/W

Mask V_SYScaused nIRQ

Mask DVC voltage ramping triggered event

Mask events generated from regulator output

voltage monitoring

M_LDO_LIM

3

R/W

Mask LDO current limit exceeded caused

nIRQ

M_COMP1V2

M_TEMP

2

1

0

R/W

Mask 1.2 V comparator caused nIRQ

Mask junction over temp caused nIRQ

Mask companion charger caused event

M_WAKE

Table 69: IRQ_MASK_E

Register Address

Bit

7

Type

R/W

Label

Description

Mask GPI caused nIRQ

M_GPI7

M_GPI6

M_GPI5

M_GPI4

M_GPI3

M_GPI2

0x0C

IRQ_MASK_E

6

5

4

3

2

Mask GPI caused / ADCIN3 high / low

threshold exceeded caused nIRQ

M_GPI1

M_GPI0

1

0

R/W

Mask GPI caused / ADCIN2 high / low

threshold exceeded caused nIRQ

Mask GPI caused / ADCIN1 high / low

threshold exceeded caused nIRQ

Table 70: IRQ_MASK_F

Register Address

Bit

7

Type

R/W

Label

Description

Mask GPI caused nIRQ

M_GPI15

M_GPI14

M_GPI13

0x0D

IRQ_MASK_F

6

Mask GPI/HS-2-WIRE caused nIRQ

Mask GPI caused nIRQ

5

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System PMIC for Mobile Application Processors

Register Address

Bit

4

Type

R/W

Label

Description

Mask GPI caused nIRQ

M_GPI12

M_GPI11

M_GPI10

M_GPI9

M_GPI8

3

Mask GPI caused nIRQ

2

Mask GPI/PWR1_EN caused nIRQ

Mask GPI/PWR_EN caused nIRQ

Mask GPI/SYS_EN caused nIRQ

1

0

Table 71: CONTROL_A

Register Address

Bit

Type

Label

Description

CP_EN

0xE CONTROL_A

7

R/W

When asserted charge pump for rail switches

is enabled

6

5

4

3

R/W

M_POWER1_EN

M_POWER_EN

M_SYSTEM_EN

STANDBY

Mask the update of POWER1_EN when

writing to CONTROL_A

Mask the update of POWER_EN when writing

to CONTROL_A

Mask the update of SYSTEM_EN when

writing to CONTROL_A

Clearing SYSTEM_EN/releasing port

SYS_EN press will

0: completely power down to Slot 0

(Hibernate)

1: stop powering down at pointer

PART_DOWN (Standby)

POWER1_EN

POWER_EN

SYSTEM_EN

2

1

0

R/W

Target status of power domain POWER1:

controlled from OTP/PM interface and port

PWR1_EN

Target status of power domain POWER:

controlled from OTP/PM interface and port

PWR_EN

Target status of power domain SYSTEM:

controlled from OTP/PM interface and port

SYS_EN

Table 72: CONTROL_B

Register Address

Bit

Type

Label

Description

BUCK_SLOWSTART

Enables soft-start for buck converters

(recommended for application instant-on

with discharged battery and weak external

supply)

0xF CONTROL_B

7

R/W

Note 1

Reserved

6:5

4

R/W

nONKEY_LOCK

0: Half-current POWERDOWN mode

1: Wakeup from POWERDOWN mode

requires the nONKEY signal being low for

longer than selected in KEY_DELAY

(automatically cleared during power-up

sequence)

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DA9063

System PMIC for Mobile Application Processors

Register Address

Bit

Type

Label

Description

nRES_MODE

3

R/W

0: No assertion of nRESET for power down

sequence

1: Assert nRESET before starting power

down sequence (release after leaving

POWERDOWN mode in case

RESET_EVENT < ‘11’)

RES_BLINKING

WATCHDOG_PD

2

1

R/W

Enables (time limited) VDD_START triggered

GPO11/4/15 flashing in case of no connected

external supply

0: Discontinue Watchdog timer during

POWERDOWN mode

1: Watchdog timer continues during

POWERDOWN mode

CHG_SEL

Port CHG_WAKE is connected to

0

R/W

0: Dialog charger WAKE port

1: Charger SAFE_OUT

Note 1 Increases buck start-up time up to 3 ms.

Table 73: CONTROL_C

Register Address

Bit

Type

Label

Description

DEF_SUPPLY

0x10

7

R/W

When asserted all supplies (except

CONTROL_C

LDOCORE) are enabled/disabled from OTP

default mode when entering sequencer Slot 0.

SLEW_RATE

6:5

R/W

DVC slewing (bucks and LDOs) is executed

at

00: 10 mV every 4.0 µs

01: 10 mV every 2.0 µs

10: 10 mV every 1.0 µs

11: 10 mV every 0.5 µs

OTPREAD_EN

AUTO_BOOT

4

3

R/W

0: OTP read after POWERDOWN mode

disabled

1: Power supplies are configured with OTP

values when leaving POWERDOWN mode

0: Start-up of power sequencer after

progressing from RESET mode requires a

valid wakeup event

1: PMIC automatically starts power sequencer

after progressing from RESET mode

DEBOUNCING

2:0

R/W

GPI, nONKEY and nSHUTDOWN debounce

time

000: no debounce time

001: 0.1 ms

010: 1.0 ms

011: 10.2 ms

100: 51.2 ms

101: 256 ms

110: 512 ms

111: 1024 ms

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System PMIC for Mobile Application Processors

Table 74: CONTROL_D

Register Address

Bit

Type

Label

Description

BLINK_DUR

0x11

7:6

R/W

GPO10/GPO11 flashing on-time

CONTROL_D

00: 10 ms

01: 20 ms

10: 40 ms

11: 20 ms double stroke (180 ms period)

BLINK_FRQ

5:3

R/W

GPO11/4/15 flashing frequency

000: no blinking (GPO11/14/15 state selected

via GPIOxx_MODE)

001: every second

010: every two seconds

011: every four seconds

100: every 180 ms (flicker mode)

101: every two seconds enabled by

VDD_START

110: every four seconds enabled by

VDD_START

111: every 180 ms enabled by VDD_START

Note 1

TWDSCALE

000: Watchdog disabled

2:0

R/W

001: 1x scaling applied to TWDMAX period

010: 2x

011: 4x

100: 8x

101: 16x

110: 32x

111: 64x

Note 1 Blinking from OTP settings 001 to 100 continues as long as an active charger is connected to port

CHG_WAKE. In the absence of a battery charger a time limited blinking can be enabled via

RES_BLINKING.

Table 75: CONTROL_E

Register Address

Bit

Type

Label

Description

V_LOCK

0: Allows host writes into registers 0x81 to

0x120

0x12

CONTROL_E

7

R/W

1: Disables register 0x81 to 0x120 re-

programming from host interfaces

PM_FB3_PIN

PM_FB2_PIN

0: 2nd 32K signal output

6

5

R/W

1: Feedback pin is used as an input signal to

stop and start the vibration motor (active low

nVIB_BRAKE)

0: Feedback pin indicates the status of

regulators being selected for voltage

supervision (PWR_OK)

1: Feedback pin is used as KEEP_ACT signal

for the Watchdog unit

PM_FB1_PIN

ECO_MODE

0: Feedback pin indicates the detection of

a wakeup event (EXT_WAKEUP)

1: Feedback pin is used as an indicator,

signaling via low level ongoing power mode

transitions (power sequencer and DVC)

(READY)

4

3

R/W

When asserted DA9063 is armed for the

pulsed mode when entering RESET

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DA9063

System PMIC for Mobile Application Processors

Register Address

Bit

Type

Label

Description

RTC_EN

2

R/W

Enables the power supply of the 32K

oscillator and RTC (for DA9063 the

DELIVERY mode if cleared under certain pre-

conditions, locked from the assertion of

control MONITOR

RTC_MODE_SD

RTC_MODE_PD

1

0

R/W

When asserted all supplies (including

LDOCORE) and functional blocks except of

the RTC are disabled when reaching RESET

mode with a VDDFAULT condition

When asserted all supplies (including

LDOCORE) and functional blocks except of

the RTC are disabled when reaching

POWERDOWN mode

Table 76: CONTROL_F

Register Address

Bit

7:3

2

Type

R/W

Label

Description

0x13

CONTROL_F

Reserved

WAKE_UP

If set to 1 PMU wakes up from

POWERDOWN mode. The bit is cleared back

to 0 automatically 16 sec after entering

ACTIVE mode

1

0

R/W

SHUTDOWN

WATCHDOG

If set to 1 the sequencer powers down to

RESET mode. The bit is cleared back to 0

automatically when entering the RESET mode

If set to 1 watchdog timer is reset. The bit is

cleared back to 0 automatically.

Table 77: PD_DIS

Register Address

Bit

Type

Label

Description

PMCONT_DIS

0: SYS_EN, PWR_EN, PWR1_EN enabled

during power down

0x14

PD_DIS

7

R/W

1: Auto-Disable of SYS_EN, PWR_EN and

PWR1_EN during POWERDOWN mode and

force the detection hidden transition when re-

enabling the control from ports

OUT_32K_PAUSE

BBAT_DIS

0: Enables OUT_32K during power down

1: Auto-Disable OUT_32K output buffer

during POWERDOWN mode

6

5

R/W

0: Enables Backup battery charger during

POWERDOWN mode

1: Auto-disable backup battery charger during

power down

CLDR_PAUSE

HS2WIRE_DIS

4

3

R/W

0: Calendar/Clock readout registers are

updated during POWERDOWN mode

1: Update of Calendar/Clock readout

registers is paused during POWERDOWN

mode

0: HS-2-WIRE not disabled during power

down

1: Auto-disable of HS-2-WIRE interface during

POWERDOWN mode

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DA9063

System PMIC for Mobile Application Processors

Register Address

Bit

Type

Label

Description

PMIF_DIS

0: Power manager interface not disabled

during power down

2

R/W

1: Auto-disable of power manager interface

during POWERDOWN mode

GPADC_PAUSE

1

0

R/W

0: ADC measurements continue during power

down as configured

1: Auto-PAUSE auto measurements on A0,

A1, A2 and A3 and manual measurement

during POWERDOWN mode; if no

autonomous auto-measurements are

required (V_SYSfrom vibration motor driver)

switch off the ADC completely

GPI_DIS

0: GPIO extender enabled during power

down

1: Auto-disable of features configured as GPI

pins during POWERDOWN mode and force

the detection hidden transition when re-

enabling the pin

Note 1 When the related ID is configured to be 1 < PD_DIS_STEP ≤ MAX_COUNT the value of the above

controls define whether functions are switched on when entering POWERDOWN mode from POR or

wait until ID PD_DIS_STEP is processed.

A.2.2

GPIO Control

Table 78: GPIO0 to 1

Register Address

Bit

Type

Label

Description

GPIO1_WEN

0: Passive to active transition triggers a

wakeup

0x15

GPIO0 to 1

7

R/W

1: Wakeup suppressed

GPIO1_TYPE

GPIO1_PIN

0: GPI: active low

GPO: supplied from VDD_IO1

6

R/W

1: GPI: active high

GPO: supplied from VDD_IO2

5:4

PIN assigned to

00: ADCIN2/1.2 V comparator

01: GPI (optional regulator HW control)

10: GPO mode controlled (Open drain)

11: GPO mode controlled (Push-pull)

GPIO0_WEN

GPIO0_TYPE

3

2

R/W

0: Passive to active transition triggers a

wakeup

1: Wakeup suppressed

0: GPI: active low

GPO: supplied from VDD_IO1

1: GPI: active high

GPO: supplied from VDD_IO2

GPIO0_PIN

1:0

R/W

PIN assigned to

00: ADCIN1

01: GPI

10: GPO mode controlled (Open drain)

11: GPO mode controlled (Push-pull)

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System PMIC for Mobile Application Processors

Table 79: GPIO2 to 3

Register Address

Bit

Type

Label

Description

GPIO3_WEN

0x16

GPIO2 to 3

7

R/W

0: Passive to active transition triggers a

wakeup

1: Wakeup suppressed

GPIO3_TYPE

GPIO3_PIN

6

R/W

0: GPI: active low

GPO: supplied from VDD_IO1

1: GPI: active high

GPO: supplied from VDD_IO2

5:4

PIN assigned to

00: CORE_SWG

01: GPI

10: GPO mode controlled (Open drain)

11: GPO mode controlled (Push-pull)

GPIO2_WEN

GPIO2_TYPE

3

2

R/W

0: Passive to active transition triggers a

wakeup

1: Wakeup suppressed

0: GPI: active low

GPO: supplied from VDD_IO1

1: GPI: active high

GPO: supplied from VDD_IO2

GPIO2_PIN

1:0

R/W

PIN assigned to

00: ADCIN3

01: GPI (optional regulator HW control)

10: GPO Sequencer controlled (Push-pull)

11: GPO mode controlled (Push-pull)

Table 80: GPIO4 to 5

Register Address

Bit

Type

Label

Description

GPIO5_WEN

0x17

GPIO4 to 5

7

R/W

0: Passive to active transition triggers a

wakeup

1: Wakeup suppressed

GPIO5_TYPE

GPIO5_PIN

6

R/W

0: GPI: active low

GPO: supplied from VDD_IO1

1: GPI: active high

GPO: supplied from VDD_IO2

5:4

PIN assigned to

00: PERI_SWG

01: GPI

10: GPO mode controlled (Open drain)

11: GPO mode controlled (Push-pull)

GPIO4_WEN

GPIO4_TYPE

3

2

R/W

0: Passive to active transition triggers a

wakeup

1: Wakeup suppressed

0: GPI: active low

GPO: supplied from VDD_IO1

1: GPI: active high

GPO: supplied from VDD_IO2

GPIO4_PIN

1:0

R/W

PIN assigned to

00: CORE_SWS

01: GPI

10: GPO mode controlled (Open drain)

11: GPO mode controlled (Push-pull)

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System PMIC for Mobile Application Processors

Table 81: GPIO6 to 7

Register Address

Bit

Type

Label

Description

GPIO7_WEN

0x18

GPIO6 to 7

7

R/W

0: Passive to active transition triggers a

wakeup

1: Wakeup suppressed

GPIO7_TYPE

GPIO7_PIN

6

R/W

0: GPI: active low

GPO: supplied from VDD_IO1

1: GPI: active high

GPO: supplied from VDD_IO2

5:4

PIN assigned to

00: Reserved

01: GPI

10: GPO Sequencer controlled (Push-pull)

11: GPO mode controlled (Push-pull)

GPIO6_WEN

GPIO6_TYPE

3

2

R/W

0: Passive to active transition triggers a

wakeup

1: Wakeup suppressed

0: GPI: active low

GPO: supplied from VDD_IO1

1: GPI: active high

GPO: supplied from VDD_IO2

GPIO6_PIN

1:0

R/W

PIN assigned to

00: PERI_SWS

01: GPI

10: GPO mode controlled (Open drain)

11: GPO mode controlled (Push-pull)

Table 82: GPIO8 to 9

Register Address

Bit

Type

Label

Description

GPIO9_WEN

0: Passive to active transition triggers a

wakeup

0x19

GPIO8 to 9

7

R/W

1: Wakeup suppressed

GPIO9_TYPE

GPIO9_PIN

0: GPI/PWR_EN: active low

GPO: supplied from VDD_IO1

6

R/W

1: GPI/PWR_EN: active high

GPO: supplied from VDD_IO2

5:4

PIN and status register bit assigned to

00: GPI with PWR_EN

01: GPI

10: GPO Sequencer controlled (Push-pull)

11: GPO mode controlled (Push-pull)

GPIO8_WEN

GPIO8_TYPE

0: Passive to active transition triggers a

wakeup

1: Wakeup suppressed

3

2

R/W

0: GPI/SYS_EN: active low

GPO: supplied from external/VDD_IO1

1: GPI/SYS_EN: active high

GPO: supplied from VDD_IO2

GPIO8_PIN

1:0

R/W

PIN and status register bit assigned to

00: GPI with SYS_EN

01: GPI

10: GPO Sequencer controlled (Push-pull)

11: GPO mode controlled (Push-pull)

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System PMIC for Mobile Application Processors

Table 83: GPIO10 to 11

Register Address

Bit

Type

Label

Description

0x1A

GPIO10 to 11

7

R/W

GPIO11_WEN

0: Passive to active transition triggers a

wakeup

1: Wakeup suppressed

0: GPI: active low

GPO: supplied from external/VDD_IO1

6

R/W

GPIO11_TYPE

GPIO11_PIN

1: GPI: active high

GPO: supplied from VDD_IO2

5:4

PIN assigned to

00: GPO (Open drain, with optional blinking)

01: GPI

10: GPO GPO Sequencer controlled (Push-

pull)

11: GPO mode controlled (Push-pull)

0: Passive to active transition triggers a

wakeup

1: Wakeup suppressed

3

2

R/W

GPIO10_WEN

GPIO10_TYPE

0: GPI/PWR1_EN: active low

GPO: supplied from external/VDD_IO1

1: GPI/PWR1_EN: active high

GPO: supplied from VDD_IO2

1:0

R/W

GPIO10_PIN

PIN and status register bit assigned to

00: GPI with PWR1_EN

01: GPI

10: GPO (Open drain)

11: GPO mode controlled (Push-pull )

Table 84: GPIO12 to 13

Register Address

Bit

Type

Label

Description

GPIO13_WEN

0x1B

GPIO12 to 13

7

6

R/W

0: Passive to active transition triggers a

wakeup

1: Wakeup suppressed

GPIO13_TYPE

GPIO13_PIN

0: GPI: active low

GPO/GP_FB1: supplied from

external/VDD_IO1

R/W

1: GPI: active high

GPO/GP_FB1: supplied from VDD_IO2

5:4

PIN and status register bit assigned to

00: GPO controlled by state of GP_FB1

(EXT_WAKEUP/READY) (Push-pull)

01: GPI (optional regulator HW control)

10: GPO controlled by state of GP_FB1

(EXT_WAKEUP/READY) (Open drain)

11: GPO mode controlled (Push-pull)

GPIO12_WEN

GPIO12_TYPE

3

2

R/W

0: Passive to active transition triggers a

wakeup

1: Wakeup suppressed

0: GPI: active low

GPO/ nVDD_FAULT/V_SYSmonitor:

supplied from VDD_IO1

1: GPI: active high

GPO/DD_FAULT/V_SYSmonitor: supplied

from VDD_IO2

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DA9063

System PMIC for Mobile Application Processors

Register Address

Bit

Type

Label

Description

GPIO12_PIN

1:0

R/W

PIN assigned to

00: nVDD_FAULT (Push-pull)

01: GPI

10: GPO controlled by the state of V_SYS

monitor (Push-pull)

11: GPO mode controlled (Push-pull)

Table 85: GPIO14 to 15

Register Address

Bit

Type

Label

Description

GPIO15_WEN

0: Passive to active transition triggers a

wakeup

1: Wakeup suppressed

0x1C

GPIO14 to 15

7

6

R/W

GPIO15_TYPE

GPIO15_PIN

0: GPI: active low

GPO: supplied from external/VDD_IO1

R/W

1: GPI: active high

GPO: supplied from VDD_IO2

5:4

PIN assigned to

00: GPO (Open drain, with optional blinking)

01: GPI

10: CLK (configured via GPIO14_PIN)

11: GPO mode controlled (Open drain)

GPIO14_WEN

GPIO14_TYPE

0: Passive to active transition triggers a

wakeup

1: Wakeup suppressed

3

2

R/W

0: GPI: active low

GPO: supplied from external/VDD_IO1

DATA/CLK supplied from VDD_IO1

(Note 1)

1: GPI: active high

GPO: supplied from VDD_IO2

DATA/CLK supplied from VDD_IO2

(Note 1)

GPIO14_PIN

1:0

R/W

PIN assigned to

00: GPO(Open drain, with optional blinking)

01: GPI

10: DATA (assigns GPIO15_PIN to CLK)

11: GPO mode controlled (Push-pull)

Note 1 When using as HS-2-WIRE IF input logic levels are derived from VDDCORE.

Table 86: GPIO_MODE0_7

Register Address

Bit

Type

Label

Description

0: GPI: debouncing off

GPIO7_ MODE

0x1D

7

R/W

GPIO_MODE0_7

GPO: Sets output to low level (active low for

sequencer control)

1: GPI: debouncing on

GPO: Sets output to high level (active high

for sequencer control)

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DA9063

System PMIC for Mobile Application Processors

Register Address

Bit

Type

Label

Description

0: GPI: debouncing off

GPIO6_ MODE

6

R/W

GPO: Sets output to low level (active low for

sequencer control)

1: GPI: debouncing on

GPO: Sets output to high level (active high

for sequencer control)

GPIO5_ MODE

GPIO4_ MODE

5

4

R/W

0: GPI: debouncing off

GPO: Sets output to low level

1: GPI: debouncing on

GPO: Sets output to high level

0: GPI: debouncing off

GPO: Sets output to low level(active low for

sequencer control)

1: GPI: debouncing on

GPO: Sets output to high level (active high

for sequencer control)

GPIO3_ MODE

3

R/W

0: GPI: debouncing off

GPO: Sets output to low level (active low for

sequencer control)

1: GPI: debouncing on

GPO: Sets output to high level (active high

for sequencer control)

GPIO2_MODE

GPIO1_ MODE

GPIO0_ MODE

2

1

0

R/W

0: GPI: debouncing off

GPO: Sets output to low level

1: GPI: debouncing on

GPO: Sets output to high level

0: GPI: debouncing off

GPO: Sets output to low level

1: GPI: debouncing on

GPO: Sets output to high level

0: GPI: debouncing off

GPO: Sets output to low level

1: GPI: debouncing on

GPO: Sets output to high level

Table 87: GPIO_MODE8_15

Register Address

Bit

Type

Label

Description

GPIO15_ MODE

0x1E

7

R/W

0: GPI: debouncing off

GPIO_MODE8_15

GPO: Sets output to low level (active high for

blinking)

1: GPI: debouncing on

GPO: Sets output to high level (active low for

blinking)

GPIO14_ MODE

6

R/W

0: GPI: debouncing off

GPO: Sets output to low level (active high for

blinking)

1: GPI:debouncing on

GPO: Sets output to high level (active low for

blinking)

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DA9063

System PMIC for Mobile Application Processors

Register Address

Bit

Type

Label

Description

0: GPI: debouncing off

GPIO13_ MODE

5

R/W

GPO: Sets output to low level (active low for

GP_FB1)

1: GPI: debouncing on

GPO: Sets output to high level (active high

for GP_FB1)

GPIO12_ MODE

GPIO11_ MODE

4

3

R/W

0: GPI: debouncing off

GPO: Sets output to low level (active low for

nVDD_FAULT, V_SYSmonitor state)

1: GPI: debouncing on

GPO: Sets output to high level (active high

for nVDD_FAULT, V_SYSmonitor state)

0: GPI: : debouncing off

GPO: Sets output to low level (active high for

blinking)

1: GPI: : debouncing on

GPO: Sets output to high level (active low for

blinking)

GPIO10_ MODE

GPIO9_ MODE

2

1

R/W

0: GPI/PWR1_EN: debouncing off

GPO: Sets output to low level

1: GPI/PWR1_EN: debouncing on

GPO: Sets output to high level

0: GPI/PWR_EN: debouncing off

GPO: Sets output to low level (active low for

sequencer control)

1: GPI/PWR_EN debouncing on

GPO: Sets output to high level (active high

for sequencer control)

GPIO8_ MODE

0

R/W

0: GPI/SYS_EN: debouncing off

GPO: Sets output to low level

1: GPI/SYS_EN: debouncing on

GPO: Sets output to high level

Table 88: SWITCH_CONT

Register Address

Bit

Type

Label

Description

CP_EN_MODE

0x1F SWITCH_CONT

7

R/W

Rail switch charge pump is enabled

0: static (does not shut down, when all

switches are open)

1: auto, CP enabled before closing the first

switch, CP disabled after last switch was

opened

CORE_SW_INT

SWITCH_SR

6

R/W

Changes the CORE external switch controller

into an internal switch between the output of

BUCKCORE1 and port CORE_SWS/GPIO4

5:4

Maximum slew rate when closing the rail

switch:

00: 1 mV/µs

01: 5 mV/µs

10: 10 mV/µs

11: as fast as possible

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System PMIC for Mobile Application Processors

Register Address

Bit

Type

Label

Description

PERI_SW_GPI

3:2

R/W

GPIO closes PERI_SW on passive to active

state transition, opens PERI_SW on active to

passive state transition

00: Not controlled by GPIO

01: GPIO1 controlled

10: GPIO2 controlled

11: GPIO13 controlled

CORE_SW_GPI

1:0

R/W

GPIO closes CORE_SW on passive to active

state transition, opens CORE_SW on active

to passive state transition

00: Not controlled by GPIO

01: GPIO1 controlled

10: GPIO2 controlled

11: GPIO13 controlled

A.2.3

Regulator Control

Table 89: BCORE2_CONT

Register Address

Bit

7

Type

R/W

Label

Description

Reserved

0x20

BCORE2_CONT

Note 1

VBCORE2_GPI

6:5

GPIO select target voltage VBCORE2_A on

passive to active transition, selects target

voltage VBCORE2_B on active to passive

transition (ramping)

00: Not controlled by GPIO (sequencer

control)

01: GPIO1 controlled

10: GPIO2 controlled

11: GPIO13 controlled

4

3

R/W

Reserved

BCORE2_CONF

BCORE2_GPI

Sequencer target state of BCORE2_EN

2:1

GPIO enables BUCKCORE2 on passive to

active state transition, disables

BUCKCORE2 on active to passive state

transition

00: Not controlled by GPIO (sequencer

control)

01: GPIO1 controlled

10: GPIO2 controlled

11: GPIO13 controlled

0: BUCKCORE2 disabled

0

R/W

BCORE2_EN

1: BUCKCORE2 enabled

Note 1 Disabled in BUCKCORE dual-phase mode.

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System PMIC for Mobile Application Processors

Table 90: BCORE1_CONT

Register Address

Bit

7

Type

R/W

Label

Description

CORE_SW_CONF

VBCORE1_GPI

0x21

BCORE1_CONT

Sequencer target state of CORE_SW_EN

6:5

GPIO select target voltage VBCORE1_A on

passive to active transition, selects target

voltage VBCORE1_B on active to passive

transition (ramping)

00: Not controlled by GPIO (sequencer

control)

01: GPIO1 controlled

10: GPIO2 controlled

11: GPIO13 controlled

0: CORE_SW opened

4

R/W

CORE_SW_EN

1: CORE_SW closed

BCORE1_CONF

BCORE1_GPI

3

R/W

Sequencer target state of BCORE1_EN

2:1

GPIO enables BUCKCORE1 on passive to

active state transition, disables

BUCKCORE1 on active to passive state

transition

00: Not controlled by GPIO (sequencer

control)

01: GPIO1 controlled

10: GPIO2 controlled

11: GPIO13 controlled

0: BUCKCORE1 disabled

0

R/W

BCORE1_EN

1: BUCKCORE1 enabled

Table 91: BPRO_CONT

Register Address

Bit

Type

R/W

Label

Description

Reserved

VBPRO_GPI

0x22

BPRO_CONT

7

6:5

GPIO select target voltage VBPRO_A on

passive to active transition, selects target

voltage VBPRO_B on active to passive

transition (ramping)

00: Not controlled by GPIO (sequencer

control)

01: GPIO1 controlled

10: GPIO2 controlled

11: GPIO13 controlled

4

3

R/W

Reserved

BPRO_CONF

BPRO_GPI

Sequencer target state of BPRO_EN

2:1

GPIO enables BUCKPRO on passive to

active state transition, disables BUCKPRO

on active to passive state transition

00: Not controlled by GPIO (sequencer

control)

01: GPIO1 controlled

10: GPIO2 controlled

11: GPIO13 controlled

0: BUCKPRO disabled

0

R/W

BPRO_EN

1: BUCKPRO enabled

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System PMIC for Mobile Application Processors

Table 92: BMEM_CONT

Register Address

Bit

7

Type

R/W

Label

Description

Reserved

VBMEM_GPI

0x23

BMEM_CONT

6:5

GPIO select target voltage VBMEM_A on

passive to active transition, selects target

voltage VBMEM_B on active to passive

transition (ramping)

00: Not controlled by GPIO (sequencer

control)

01: GPIO1 controlled

10: GPIO2 controlled

11: GPIO13 controlled

4

3

R/W

Reserved

BMEM_CONF

Sequencer target state of BMEM_EN in

case of being a default supply)

BMEM_GPI

2:1

R/W

GPIO enables BUCKMEM on passive to

active state transition, disables BUCKMEM

on active to passive state transition

00: Not controlled by GPIO (sequencer

control)

01: GPIO1 controlled

10: GPIO2 controlled

11: GPIO13 controlled

0: BUCKMEM disabled

0

R/W

BMEM_EN

1: BUCKMEM enabled

Table 93: BIO_CONT

Register Address

Bit

7

Type

R/W

Label

Description

Reserved

VBIO_GPI

0x24

BIO_CONT

6:5

GPIO select target voltage VBIO_A on

passive to active transition, selects target

voltage VBIO_B on active to passive

transition (ramping)

00: Not controlled by GPIO (sequencer

control)

01: GPIO1 controlled

10: GPIO2 controlled

11: GPIO13 controlled

4

3

R/W

Reserved

BIO_CONF

BIO_GPI

Sequencer target state of BIO_EN

2:1

GPIO enables BUCKIO on passive to active

state transition, disables BUCKIO on active

to passive state transition

00: Not controlled by GPIO (sequencer

control)

01: GPIO1 controlled

10: GPIO2 controlled

11: GPIO13 controlled

0: BUCKIO disabled

0

R/W

BIO_EN

1: BUCKIO enabled

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System PMIC for Mobile Application Processors

Table 94: BPERI_CONT

Register Address

Bit

7

Type

R/W

Label

Description

PERI_SW_CONF

VBPERI_GPI

0x25

BPERI_CONT

Sequencer target state of PERI_SW_EN

6:5

GPIO select target voltage VBPERI_A on

passive to active transition, selects target

voltage VBPERI_B on active to passive

transition (ramping)

00: Not controlled by GPIO (sequencer

control)

01: GPIO1 controlled

10: GPIO2 controlled

11: GPIO13 controlled

0: PERI_SW opened

4

R/W

PERI_SW_EN

1: PERI_SW closed

BPERI_CONF

BPERI_GPI

3

R/W

Sequencer target state of BPERI_EN

2:1

GPIO enables BUCKPERI on passive to

active state transition, disables BUCKPERI

on active to passive state transition

00: Not controlled by GPIO (sequencer

control)

01: GPIO1 controlled

10: GPIO2 controlled

11: GPIO13 controlled

BPERI_EN

0: BUCKPERI disabled

0

R/W

1: BUCKPERI enabled

Table 95: LDO1_CONT

Register Address

Bit

Type

R/W

Label

Description

LDO1_CONF

VLDO1_GPI

0x26

LDO1_CONT

7

Sequencer target state of LDO1_EN

6:5

GPIO select target voltage VLDO1_A on

passive to active transition, selects target

voltage VLDO1_B on active to passive

transition (ramping)

00: Not controlled by GPIO (sequencer

control)

01: GPIO1 controlled

10: GPIO2 controlled

11: GPIO13 controlled

4

3

R/W

Reserved

LDO1_PD_DIS

0: Enable pull-down resistor

1: No pull-down resistor in disabled mode

LDO1_GPI

2:1

R/W

GPIO enables LDO1 on passive to active

state transition, disables LDO1 on active to

passive state transition

00: Not controlled by GPIO (sequencer

control)

01: GPIO1 controlled

10: GPIO2 controlled

11: GPIO13 controlled

0: LDO1 disabled

0

R/W

LDO1_EN

1: LDO1 enabled

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System PMIC for Mobile Application Processors

Table 96: LDO2_CONT

Register Address

Bit

7

Type

R/W

Label

Description

LDO2_CONF

VLDO2_GPI

0x27

LDO2_CONT

Sequencer target state of LDO2_EN

6:5

GPIO select target voltage VLDO2_A on

passive to active transition, selects target

voltage VLDO2_B on active to passive

transition (ramping)

00: Not controlled by GPIO (sequencer

control)

01: GPIO1 controlled

10: GPIO2 controlled

11: GPIO13 controlled

4

3

R/W

Reserved

LDO2_PD_DIS

0: Enable pull-down resistor

1: No pull-down resistor in disabled mode

LDO2_GPI

2:1

R/W

GPIO enables LDO2 on passive to active

state transition, disables LDO2 on active to

passive state transition

00: Not controlled by GPIO (sequencer

control)

01: GPIO1 controlled

10: GPIO2 controlled

11: GPIO13 controlled

0: LDO2 disabled

0

R/W

LDO2_EN

1: LDO2 enabled

Table 97: LDO3_CONT

Register Address

Bit

Type

R/W

Label

Description

LDO3_CONF

VLDO3_GPI

0x28

LDO3_CONT

7

Sequencer target state of LDO3_EN

6:5

GPIO select target voltage VLDO3_A on

passive to active transition, selects target

voltage VLDO3_B on active to passive

transition (ramping)

00: Not controlled by GPIO (sequencer

control)

01: GPIO1 controlled

10: GPIO2 controlled

11: GPIO13 controlled

4

3

R/W

Reserved

LDO3_PD_DIS

0: Enable pull-down resistor

1: No pull-down resistor in disabled mode

LDO3_GPI

2:1

R/W

GPIO enables LDO3 on passive to active

state transition, disables LDO3 on active to

passive state transition

00: Not controlled by GPIO (sequencer

control)

01: GPIO1 controlled

10: GPIO2 controlled

11: GPIO13 controlled

0: LDO3 disabled

0

R/W

LDO3_EN

1: LDO3 enabled

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System PMIC for Mobile Application Processors

Table 98: LDO4_CONT

Register Address

Bit

7

Type

R/W

Label

Description

LDO4_CONF

VLDO4_GPI

0x29

LDO4_CONT

Sequencer target state of LDO4_EN

6:5

GPIO select target voltage VLDO4_A on

passive to active transition, selects target

voltage VLDO4_B on active to passive

transition (ramping)

00: Not controlled by GPIO (sequencer

control)

01: GPIO1 controlled

10: GPIO2 controlled

11: GPIO13 controlled

4

3

R/W

Reserved

LDO4_PD_DIS

0: Enable pull-down resistor

1: No pull-down resistor in disabled mode

LDO4_GPI

2:1

R/W

GPIO enables LDO4 on passive to active

state transition, disables LDO4 on active to

passive state transition

00: Not controlled by GPIO (sequencer

control)

01: GPIO1 controlled

10: GPIO2 controlled

11: GPIO13 controlled

0: LDO4 disabled

0

R/W

LDO4_EN

1: LDO4 enabled

Table 99: LDO5_CONT

Register Address

Bit

Type

R/W

Label

Description

LDO5_CONF

VLDO5_GPI

0x2A

LDO5_CONT

7

Sequencer target state of LDO5_EN

6:5

GPIO select target voltage VLDO5_A on

passive to active transition, selects target

voltage VLDO5_B on active to passive

transition (immediate voltage change)

00: Not controlled by GPIO (sequencer

control)

01: GPIO1 controlled

10: GPIO2 controlled

11: GPIO13 controlled

4

R/W

VLDO5_SEL

LDO5 voltage is selected from (immediate

change):

0: VLDO5_A

1: VLDO5_B

LDO5_PD_DIS

LDO5_GPI

0: Enable pull-down resistor

1: No pull-down resistor in disabled mode

3

R/W

2:1

GPIO enables LDO5 on passive to active

state transition, disables LDO6 on active to

passive state transition

00: Not controlled by GPIO (sequencer

control)

01: GPIO1 controlled

10: GPIO2 controlled

11: GPIO13 controlled

0: LDO5 disabled

0

R/W

LDO5_EN

1: LDO5 enabled

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System PMIC for Mobile Application Processors

Table 100: LDO6_CONT

Register Address

Bit

7

Type

R/W

Label

Description

LDO6_CONF

VLDO6_GPI

0x2B

LDO6_CONT

Sequencer target state of LDO6_EN

6:5

GPIO select target voltage VLDO6_A on

passive to active transition, selects target

voltage VLDO6_B on active to passive

transition (immediate voltage change)

00: Not controlled by GPIO (sequencer

control)

01: GPIO1 controlled

10: GPIO2 controlled

11: GPIO13 controlled

4

R/W

VLDO6_SEL

LDO6 voltage is selected from (immediate

change):

0: VLDO6_A

1: VLDO6_B

LDO6_PD_DIS

LDO6_GPI

0: Enable pull-down resistor

1: No pull-down resistor in disabled mode

3

R/W

2:1

GPIO enables LDO6 on passive to active

state transition, disables LDO6 on active to

passive state transition

00: Not controlled by GPIO (sequencer

control)

01: GPIO1 controlled

10: GPIO2 controlled

11: GPIO13 controlled

0: LDO6 disabled

0

R/W

LDO6_EN

1: LDO6 enabled

Table 101: LDO7_CONT

Register Address

Bit

Type

R/W

Label

Description

LDO7_CONF

VLDO7_GPI

0x2C

LDO7_CONT

7

Sequencer target state of LDO7_EN

6:5

GPIO select target voltage VLDO7_A on

passive to active transition, selects target

voltage VLDO7_B on active to passive

transition (immediate voltage change)

00: Not controlled by GPIO (sequencer

control)

01: GPIO1 controlled

10: GPIO2 controlled

11: GPIO13 controlled

4

3

R/W

VLDO7_SEL

LDO7 voltage is selected from (immediate

change):

0: VLDO7_A

1: VLDO7_B

LDO7_PD_DIS

0: Enable pull-down resistor

1: No pull-down resistor in disabled mode

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DA9063

System PMIC for Mobile Application Processors

Register Address

Bit

Type

Label

Description

LDO7_GPI

2:1

R/W

GPIO enables LDO7 on passive to active

state transition, disables LDO7 on active to

passive state transition

00: Not controlled by GPIO (sequencer

control)

01: GPIO1 controlled

10: GPIO2 controlled

11: GPIO13 controlled

0: LDO7 disabled

0

R/W

LDO7_EN

1: LDO7 enabled

Table 102: LDO8_CONT

Register Address

Bit

Type

R/W

Label

Description

LDO8_CONF

VLDO8_GPI

0x2D

LDO8_CONT

7

Sequencer target state of LDO8_EN

6:5

GPIO select target voltage VLDO8_A on

passive to active transition, selects target

voltage VLDO8_B on active to passive

transition (immediate voltage change)

00: Not controlled by GPIO (sequencer

control)

01: GPIO1 controlled

10: GPIO2 controlled

11: GPIO13 controlled

4

R/W

VLDO8_SEL

LDO8 voltage is selected from (immediate

change):

0: VLDO8_A

1: VLDO8_B

LDO8_PD_DIS

LDO8_GPI

0: Enable pull-down resistor

1: No pull-down resistor in disabled mode

3

R/W

2:1

GPIO enables LDO8 on passive to active

state transition, disables LDO8 on active to

passive state transition

00: Not controlled by GPIO (sequencer

control)

01: GPIO1 controlled

10: GPIO2 controlled

11: GPIO13 controlled

0: LDO8 disabled

0

R/W

LDO8_EN

1: LDO8 enabled

Table 103: LDO9_CONT

Register Address

Bit

Type

R/W

Label

Description

LDO9_CONF

VLDO9_GPI

0x2E

LDO9_CONT

7

Sequencer target state of LDO9_EN

6:5

GPIO select target voltage VLDO9_A on

passive to active transition, selects target

voltage VLDO9_B on active to passive

transition (immediate voltage change)

00: Not controlled by GPIO (sequencer

control)

01: GPIO1 controlled

10: GPIO2 controlled

11: GPIO13 controlled

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System PMIC for Mobile Application Processors

Register Address

Bit

Type

Label

Description

4

R/W

VLDO9_SEL

LDO9 voltage is selected from (immediate

change):

0: VLDO9_A

1: VLDO9_B

LDO9_PD_DIS

LDO9_GPI

0: Enable pull-down resistor

1: No pull-down resistor in disabled mode

3

R/W

2:1

GPIO enables LDO9 on passive to active

state transition, disables LDO9 on active to

passive state transition

00: Not controlled by GPIO (sequencer

control)

01: GPIO1 controlled

10: GPIO2 controlled

11: GPIO13 controlled

0: LDO9 disabled

0

R/W

LDO9_EN

1: LDO9 enabled

Table 104: LDO10_CONT

Register Address

Bit

7

Type

R/W

Label

Description

LDO10_CONF

VLDO10_GPI

0x2F LDO10_CONT

Sequencer target state of LDO10_EN

6:5

GPIO select target voltage VLDO10_A on

passive to active transition, selects target

voltage VLDO10_B on active to passive

transition (immediate voltage change)

00: Not controlled by GPIO (sequencer

control)

01: GPIO1 controlled

10: GPIO2 controlled

11: GPIO13 controlled

4

R/W

VLDO10_SEL

LDO10 voltage is selected from (immediate

change):

0: VLDO10_A

1: VLDO10_B

LDO10_PD_DIS

LDO10_GPI

0: Enable pull-down resistor

1: No pull-down resistor in disabled mode

3

R/W

2:1

GPIO enables LDO10 on passive to active

state transition, disables LDO10 on active to

passive state transition

00: Not controlled by GPIO (sequencer

control)

01: GPIO1 controlled

10: GPIO2 controlled

11: GPIO13 controlled

0: LDO10 disabled

0

R/W

LDO10_EN

1: LDO10 enabled

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System PMIC for Mobile Application Processors

Table 105: LDO11_CONT

Register Address

Bit

7

Type

R/W

Label

Description

LDO11_CONF

VLDO11_GPI

0x30 LDO11_CONT

Sequencer target state of LDO11_EN

6:5

GPIO select target voltage VLDO11_A on

passive to active transition, selects target

voltage VLDO11_B on active to passive

transition (immediate voltage change)

00: Not controlled by GPIO (sequencer

control)

01: GPIO1 controlled

10: GPIO2 controlled

11: GPIO13 controlled

VLDO11_SEL

4

R/W

LDO11 voltage is selected from (immediate

change):

0: VLDO11_A

1: VLDO11_B

LDO11_PD_DIS

LDO11_GPI

0: Enable pull-down resistor

1: No pull-down resistor in disabled mode

3

R/W

2:1

GPIO enables LDO11 on passive to active

state transition, disables LDO11 on active to

passive state transition

00: Not controlled by GPIO (sequencer

control)

01: GPIO1 controlled

10: GPIO2 controlled

11: GPIO13 controlled

LDO11_EN

0: LDO11 disabled

0

R/W

1: LDO11 enabled

Table 106: VIB

Register Address

Bit

7:6

5:0

Type

R/W

Label

Description

Reserved

VIB_SET

0x31

VIB

000000: OFF-BREAK, NMOS on, PMOS off

000001: 47.55 mV

000010: 95.1 mV

…

Average output level set in a range of 0 to

3 V in steps of 3 V/63

…

111111: 3.0 V

Table 107: DVC_1

Register Address

Bit

Type

Label

Description

0x32

DVC_1

7

R/W

VLDO3_SEL

LDO3 voltage is selected from (ramping):

0: VLDO3_A

1: VLDO3_B

6

R/W

VLDO2_SEL

LDO2 voltage is selected from (ramping):

0: VLDO2_A

1: VLDO2_B

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System PMIC for Mobile Application Processors

Register Address

Bit

Type

Label

Description

5

R/W

VLDO1_SEL

LDO1 voltage is selected from (ramping):

0: VLDO1_A

1: VLDO1_B

4

3

2

1

0

R/W

VBPERI_SEL

VBMEM_SEL

VBPRO_SEL

BUCKPERI voltage is selected from

(ramping):

0: VBPERI_A

1: VBPERI_B

BUCKMEM voltage is selected from

(ramping):

0: VBMEM_A

1: VBMEM_B

BUCKPRO voltage is selected from

(ramping):

0: VBPRO_A

1: VBPRO_B

VBCORE2_SEL

VBCORE1_SEL

BUCKCORE2 voltage is selected from

(ramping):

0: VBCORE2_A

1: VBCORE2_B

BUCKCORE1 voltage is selected from

(ramping):

0: VBCORE1_A

1: VBCORE1_B

Table 108: DVC_2

Register Address

Bit

Type

Label

Description

0x33

DVC_2

7

R/W

VLDO4_SEL

LDO4 voltage is selected from (ramping):

0: VLDO4_A

1: VLDO4_B

6:1

0

R/W

Reserved

VBIO_SEL

BUCKIO voltage is selected from (ramping):

0: VBIO_A

1: VBIO_B

A.2.4

GPADC

Table 109: ADC_MAN

Register Address

Bit

7:6

5

Type

R/W

Label

Description

Reserved

ADC_MODE

0x34

ADC_MAN

0: Measurement sequence interval 10 ms

(economy mode)

1: Measurement sequence interval 1 ms

4

R/W

ADC_MAN

Perform manual conversion. Bit is reset to 0

when conversion is complete.

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DA9063

System PMIC for Mobile Application Processors

Register Address

Bit

Type

Label

Description

ADC_MUX

3:0

R/W

Manual measurement selects:

0000: VSYS port

0001: ADCIN1

0010: ADCIN2

0011: ADCIN3

0100: internal T-Sense

0101: VBBAT-voltage

0110: reserved

0111: reserved

1000: Group 1 regulators voltage

1001: Group 2 regulators voltage

1010: Group 3 regulators voltage

> 1010: reserved

Table 110: ADC_CONT

Register Address

Bit

Type

Label

Description

COMP1V2_EN

0: Disable 1.2 V comparator at ADCIN2

1: Enable 1.2 V comparator

0x35

ADC_CONT

7

6

5

4

3

2

1

0

R/W

AD3_ISRC_EN

AD2_ISRC_EN

AD1_ISRC_EN

AUTO_AD3_EN

AUTO_AD2_EN

AUTO_AD1_EN

AUTO_VSYS_EN

0: Disable ADCIN3 current source

1: Enable ADCIN3 current source

R/W

0: Disable ADCIN2 current source

1: Enable ADCIN2 current source

0: Disable ADCIN1 current source

1: Enable ADCIN1 current source

0: ADCIN3 auto-measurements disabled

1: ADCIN3 auto-measurements enabled

0: ADCIN2 auto-measurements disabled

1: ADCIN2 auto-measurements enabled

0: ADCIN1 auto-measurements disabled

1: ADCIN1 auto-measurements enabled

0: VSYS auto-measurements disabled

when charger/vibration motor driver is

off

1: VSYS auto-measurements enabled

Table 111: VSYS_MON

Register Address

Bit

Type

Label

Description

0x36

7:0

R/W

VSYS_MON

VSYS_MON threshold setting (8-bit).

VSYS_MON

00000000 corresponds to 2.5 V

11111111 corresponds to 5.5 V

A.2.5

ADC Results

Table 112: ADC_RES_L

Register Address

Bit

7:6

5:0

Type

R

Label

Description

0x37 ADC_RES_L

ADC_RES_LSB

Reserved

10-bit manual conversion result (2 LSBs)

R

Datasheet

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23-Mar-2017

CFR0011-120-00

151 of 219

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System PMIC for Mobile Application Processors

Table 113: ADC_RES_H

Register Address

Bit

Type

Label

Description

0x38 ADC_RES_H

7:0

R

ADC_RES_MSB

10-bit manual conversion result (8 MSBs)

Table 114: VSYS_RES

Register Address

Bit

Type

Label

Description

0x39 VSYS_RES

7:0

R

VSYS_RES

0x00 – 0xFF: Auto VSYS conversion result

(A0)

0x00 corresponds to 2.5 V

0xFF corresponds to 5.5 V

Table 115: ADCIN1_RES

Register Address

Bit

Type

Label

Description

0x3A

7:0

R

ADCIN1_RES

0x00 – 0xFF: Auto ADC ADCIN1 conversion

ADCIN1_RES

result

Table 116: ADCIN2_RES

Register Address

Bit

Type

Label

Description

0x3B

7:0

R

ADCIN2_RES

0x00 – 0xFF: Auto ADC ADCIN2 conversion

ADCIN2_RES

result

Table 117: ADCIN3_RES

Register Address

Bit

Type

Label

Description

0x3C

7:0

R

ADCIN3_RES

0x00 – 0xFF: Auto ADC ADCIN3 conversion

ADCIN3_RES

result

Table 118: MON_A8_RES

Register Address

Bit

Type

Label

Description

0x3D

7:0

R

MON_A8_RES

0x00 – 0xFF: Regulator output voltage

MON_A8_RES

monitor 1 (A8) conversion result

0x00 corresponds to 0.0 V

0xFF corresponds to 5.0 V

Table 119: MON_A9_RES

Register Address

Bit

Type

Label

Description

0x3E

7:0

R

MON_A9_RES

0x00 – 0xFF: Regulator output voltage

MON_A9_RES

monitor 2 (A9) conversion result

0x00 corresponds to 0.0 V

0xFF corresponds to 5.0 V

Table 120: MON_A10_RES

Register Address

Bit

Type

Label

Description

0x3F

7:0

R

MON_A10_RES

0x00 – 0xFF: Regulator output voltage

MON_A10_RES

monitor 3 (A10) conversion result

0x00 corresponds to 0.0 V

0xFF corresponds to 5.0 V

Datasheet

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23-Mar-2017

CFR0011-120-00

152 of 219

DA9063

System PMIC for Mobile Application Processors

A.2.6

RTC Calendar and Alarm

Table 121: COUNT_S

Register Address

Bit

Type

Label

Description

0x40

COUNT_S

7

R

RTC_READ

Asserted when below registers have been

transferred from RTC logic into host readable

registers (for example, after leaving POR)

6

R

Reserved

5:0

R/W

COUNT_SEC

0x00 – 0x3B: RTC seconds read-out. A read

of this register latches the current RTC

calendar count into the registers COUNT_S

to COUNT_Y cohererent for approx 0.5 s).

Table 122: COUNT_MI

Register Address

Bit

7:6

5:0

Type

R

Label

Description

0x41 COUNT_MI

Reserved

R/W

COUNT_MIN

0x00 – 0x3B: RTC minutes read-out

Table 123: COUNT_H

Register Address

Bit

Type

R

Label

Description

0x42

COUNT_H

7:5

4:0

Reserved

R/W

COUNT_HOUR

0x00 – 0x17: RTC hours read-out

Table 124: COUNT_D

Register Address

Bit

Type

R

Label

Description

0x43

COUNT_D

7:5

4:0

Reserved

R/W

COUNT_DAY

0x01 – 0x1F: RTC days read-out

Table 125: COUNT_MO

Register Address

Bit

7:4

3:0

Type

R

Label

Description

0x44 COUNT_MO

Reserved

R/W

COUNT_MONTH

0x01 – 0x0C: RTC months read-out

Table 126: COUNT_Y

Register Address

Bit

Type

R

Label

Description

0x45

COUNT_Y

7

6

Reserved

MONITOR

R/W

Read-out 0 indicates that the power was lost.

Read-out of 1 indicates that the clock is OK

Set to 1 when setting time to arm RTC

monitor function. Cannot be cleared via

register write.

5:0

R/W

COUNT_YEAR

0x00 – 0x3F: RTC years read-out (0

corresponds to year 2000). A write to this

register latches the registers COUNT_S to

COUNT_Y into the current RTC calendar

counters.

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23-Mar-2017

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System PMIC for Mobile Application Processors

Table 127: ALARM_S

Register Address

Bit

Type

Label

Description

Alarm event caused by:

0x46

7:6

R

ALARM_TYPE

ALARM_S

00: No alarm

01: Tick

10: Timer alarm

11: Both

5:0

R/W

ALARM_SEC

0x00 – 0x3B: Alarm seconds setting

Table 128: ALARM_MI

Register Address

Bit

7:6

5:0

Type

R

Label

Description

0x47 ALARM_MI

Reserved

R/W

ALARM_MIN

0x00 – 0x3B: Alarm minutes setting

Table 129: ALARM_H

Register address

Bit

Type

R

Label

Description

0x48

ALARM_H

7:5

4:0

Reserved

R/W

ALARM_HOUR

0x00 – 0x17: Alarm hours setting

Table 130: ALARM_D

Register Address

Bit

Type

R

Label

Description

0x49

ALARM_D

7:5

4:0

Reserved

R/W

ALARM_DAY

0x01 – 0x1F: Alarm days setting

Table 131: ALARM_MO

Register Address

Bit

7:6

5

Type

R

Label

Description

0x4A ALARM_MO

Reserved

R/W

TICK_WAKE

Tick alarm wakeup

0: disabled

1: enabled

4

R/W

TICK_TYPE

Tick alarm interval is:

0: one second

1: one minute

3:0

ALARM_MONTH

0x01 – 0x0C: Alarm months setting

Table 132: ALARM_Y

Register Address

Bit

Type

Label

Description

0x4B

7

R/W

TICK_ON

0: Tick function is disabled

ALARM_Y

1: Periodic tick alarm enabled

6

R/W

ALARM_ON

0: Alarm function is disabled

1: Alarm enabled

5:0

ALARM_YEAR

0x00 – 0x3F: Alarm years setting (0

corresponds to year 2000). A write to this

register latches the registers ALARM_MI to

ALARM_Y

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23-Mar-2017

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DA9063

System PMIC for Mobile Application Processors

Table 133: SECOND_A

Register Address

Bit

Type

Label

Description

0x4C SECOND_A

7:0

R

SECONDS_A

RTC seconds counter A (LSBs). A read of

this register latches the current 32-bit counter

into the registers SECOND_A to SECOND_D

(cohererent for approx 0.5 s).

Table 134: SECOND_B

Register Address

Bit

Type

Label

Description

0x4D SECOND_B

7:0

R

SECONDS_B

RTC seconds counter B

Table 135: SECOND_C

Register Address

Bit

Type

Label

Description

0x4E SECOND_C

7:0

R

SECONDS_C

RTC seconds counter C

Table 136: SECOND_D

Register Address

Bit

Type

Label

Description

0x4F SECOND_D

7:0

R

SECONDS_D

RTC seconds counter D (MSBs)

Table 137: Copmic_S to Copmic_E

Register Address

0x50 CoPMIC_S

0x67 CoPMIC_E

Bit

7:0

Type

R

Label

Description

Reserved for Co-PMIC

Reserved

R

Table 138: CHG_Co_S to CHG_Co_E

Register Address

0x68 CHG_Co_S

0x7F CHG_Co_E

Bit

7:0

Type

R

Label

Description

Reserved for companion charger

Reserved

R

A.3 Register Page 1

Table 139: PAGE_CON

Register Address

Bit

7

Type

RW

Label

REVERT

Description

0x80 PAGE_CON

See register 0x00, Table 57

6

WRITE_MODE

Reserved

5:3

2:0

REG_PAGE

Datasheet

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23-Mar-2017

CFR0011-120-00

155 of 219

DA9063

System PMIC for Mobile Application Processors

A.3.1

Power Sequencer

Table 140: SEQ

Register Address

Bit

Type

Label

Description

0x81

SEQ

7:4

R/W

NXT_SEQ_START

Start time slot for first sequencing after being

modified via register write

3:0

R

SEQ_POINTER

Actual pointer position (time slot) of power

sequencer

Table 141: SEQ_TIMER

Register Address

Bit

Type

Label

Description

SEQ_DUMMY

0x82 SEQ_TIMER

7:4

R/W

0000: 32 µs

0001: 64 µs

0010: 96 µs

0011: 128 µs

0100: 160 µs

0101: 192 µs

0110: 224 µs

0111: 256 µs

1000: 288 µs

1001: 384 µs

1010: 448 µs

1011: 512 µs

1100: 1.024 ms

1101: 2.048 ms

1110: 4.096 ms

1111: 8.192 ms

SEQ_TIME

3:0

R/W

0000: 32 µs

0001: 64 µs

0010: 96 µs

0011: 128 µs

0100: 160 µs

0101: 192 µs

0110: 224 µs

0111: 256 µs

1000: 288 µs

1001: 384 µs

1010: 448 µs

1011: 512 µs

1100: 1.024 ms

1101: 2.048 ms

1110: 4.096 ms

1111: 8.192 ms

Table 142: ID_2_1

Register Address

Bit

7:4

3:0

Type

R/W

Label

Description

LDO2_STEP

LDO1_STEP

0x83

ID_2_1

Power sequencer time slot for LDO2 control

Power sequencer time slot for LDO1 control

Table 143: ID_4_3

Register Address

Bit

7:4

3:0

Type

R/W

Label

Description

LDO4_STEP

LDO3_STEP

0x84

ID_4_3

Power sequencer time slot for LDO4 control

Power sequencer time slot for LDO3 control

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DA9063

System PMIC for Mobile Application Processors

Table 144: ID_6_5

Register Address

Bit

7:4

3:0

Type

R/W

Label

Description

LDO6_STEP

LDO5_STEP

0x85

ID_6_5

Power sequencer time slot for LDO6 control

Power sequencer time slot for LDO5 control

Table 145: ID_8_7

Register Address

Bit

7:4

3:0

Type

R/W

Label

Description

LDO8_STEP

LDO7_STEP

0x86

ID_8_7

Power sequencer time slot for LDO8 control

Power sequencer time slot for LDO7 control

Table 146: ID_10_9

Register Address

Bit

7:4

3:0

Type

R/W

Label

Description

LDO10_STEP

LDO9_STEP

0x87

ID_10_9

Power sequencer time slot for LDO10 control

Power sequencer time slot for LDO9 control

Table 147: ID_12_11

Register Address

Bit

Type

Label

Description

PD_DIS_STEP

0x88

ID_12_11

7:4

3:0

R/W

Power sequencer time slot for control of

blocks to be disabled/paused during

POWERDOWN mode

LDO11_STEP

R/W

Power sequencer time slot for LDO11 control

Table 148: ID_14_13

Register Address

Bit

Type

Label

Description

BUCKCORE2_STEP

0x89

ID_14_13

7:4

3:0

R/W

Power sequencer time slot for control of

BUCKCORE2 (disabled in BUCKCORE dual

phase mode)

BUCKCORE1_STEP

R/W

Power sequencer time slot for control of

BUCKCORE1

Table 149: ID_16_15

Register Address

Bit

Type

Label

Description

BUCK_IO_STEP

0x8A

ID_16_15

7:4

R/W

Power sequencer time slot for control of

BUCKPRO

BUCKPRO_STEP

3:0

R/W

Power sequencer time slot for control of

BUCKPRO

Table 150: ID_18_17

Register Address

Bit

Type

Label

Description

BUCKPERI_STEP

0x8B

ID_18_17

7:4

R/W

Power sequencer time slot for control of

BUCKPERI

BUCKMEM_STEP

3:0

R/W

Power sequencer time slot for control of

BUCKMEM

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23-Mar-2017

CFR0011-120-00

157 of 219

DA9063

System PMIC for Mobile Application Processors

Table 151: ID_20_19

Register Address

Bit

Type

Label

Description

PERI_SW_STEP

0x8C

ID_20_19

7:4

R/W

Power sequencer time slot for control of

PERI rail switch

CORE_SW_STEP

3:0

R/W

Power sequencer time slot for control of

CORE rail switch

Table 152: ID_22_21

Register Address

Bit

Type

Label

Description

GP_FALL1_STEP

0x8D

ID_22_21

7:4

R/W

Power sequencer time slot for falling edge

control of GPO2

GP_RISE1_STEP

3:0

R/W

Power sequencer time slot for rising edge

control of GPO2

Table 153: ID_24_23

Register Address

Bit

Type

Label

Description

GP_FALL2_STEP

0x8E

ID_24_23

7:4

R/W

Power sequencer time slot for falling edge

control of GPO7

GP_RISE2_STEP

3:0

R/W

Power sequencer time slot for rising edge

control of GPO7

Table 154: ID_26_25

Register Address

Bit

Type

Label

Description

GP_FALL3_STEP

0x8F

ID_26_25

7:4

R/W

Power sequencer time slot for falling edge

control of GPO8

GP_RISE3_STEP

3:0

R/W

Power sequencer time slot for rising edge

control of GPO8

Table 155: ID_28_27

Register Address

Bit

Type

Label

Description

GP_FALL4_STEP

0x90

ID_28_27

7:4

R/W

Power sequencer time slot for falling edge

control of GPO9

GP_RISE4_STEP

3:0

R/W

Power sequencer time slot for rising edge

control of GPO9

Table 156: ID_30_29

Register Address

Bit

Type

Label

Description

GP_FALL5_STEP

0x91

ID_30_29

7:4

R/W

Power sequencer time slot for falling edge

control of GPO11

GP_RISE5_STEP

3:0

R/W

Power sequencer time slot for rising edge

control of GPO11

Datasheet

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23-Mar-2017

CFR0011-120-00

158 of 219

DA9063

System PMIC for Mobile Application Processors

Table 157: ID_32_31

Register Address

Bit

Type

Label

Description

EN32K_STEP

0x92

ID_32_31

7:4

R/W

Power sequencer time slot for enable/disable

of 32K output signals

WAIT_STEP

3:0

R/W

Power sequencer time slot that gates the

progress with state of GPI10 (or used a

dedicated delay timer)

Table 158: Reserved

Register Address

Bit

Type

Label

Description

Reserved

0x93

7:0

R/W

Table 159: SEQ_A

Register Address

Bit

Type

Label

Description

POWER_END

0x95

SEQ_A

7:4

R/W

OTP pointer to last supply of domain

POWER

SYSTEM_END

3:0

R/W

OTP pointer to last supply of domain

SYSTEM

Table 160: SEQ_B

Register Address

Bit

7:4

3:0

Type

R/W

Label

Description

PART_DOWN

MAX_COUNT

0x96

SEQ_B

OTP pointer for partial POWERDOWN mode

OTP pointer to last supply of domain

POWER1

Table 161: WAIT

Register Address

Bit

Type

Label

Description

WAIT_DIR

00: No wait during power sequencing

01: Wait during power-up sequence

10:: Wait during power-down sequence

11: Wait during power-up and power-down

sequence

0x97

WAIT

7:6

R/W

TIME_OUT

0: No time limit

1: 500 ms time out for waiting GPIO10 to get

active

5

4

R/W

WAIT_MODE

0: Wait for GPIO10 to be active

1: Timer mode (start timer and wait for

expire)

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System PMIC for Mobile Application Processors

Register Address

Bit

Type

Label

Description

WAIT_TIME

3:0

R/W

0000: 0.0 µs

0001: 512 µs

0010: 1.0 ms

0011: 2.0 ms

0100: 4.1 ms

0101: 8.2 ms

0110: 16.4 ms

0111: 32.8 ms

1000: 65.5 ms

1001: 128 ms

1010: 256 ms

1011: 512 ms

1100: 1.0 s

1101: 2.1 s

1110: 4.2 s

1111: 8.4 s

Table 162: EN_32K

Register Address

Bit

Type

Label

Description

EN_32KOUT

0x98

7

R/W

0: 32K clock buffer off (OUT_32K)

1: 32K clock buffer enabled (OUT_32K),

when powering up with a power sequence

including EN32K_STEP the buffer is enabled

when reaching EN32K_STEP, in case the

power sequence includes PD_DIS_STEP

with OUT_32K_PAUSE asserted the buffer

enable is delayed until reaching

EN_32K

PD_DIS_STEP on the way up

Note: with OUT_CLOCK being asserted the

buffer enable is delayed until 32K oscillator

signal is stable

RTC_CLOCK

OUT_CLOCK

6

5

R/W

0: No gating of RTC calendar clock

1: Clock to RTC counter is gated until 32K

oscillator stabilisation timer has expired

0: No gating of OUT_32K and clock signals

at GP_FB3

1: Clock to buffers is gated until 32K

oscillation stabilisation timer has expired

(indicating stable 32K oscillator signal)

DELAY_MODE

0: Start stabilisation timer when duty

cycle of oscillator signal is in between

30% and 70%

1: Start stabilisation timer when CRYSTAL is

asserted, RTC_EN changed or when leaving

DELIVERY/NO-POWER mode with

CRYSTAL asserted

4

3

R/W

CRYSTAL

0: No 32 kHz crystal connected (bypass via

XOUT)

1: 32 kHz crystal connected

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160 of 219

DA9063

System PMIC for Mobile Application Processors

Register Address

Bit

Type

Label

Description

STABILISATION_TIME

2:0

R/W

Time to allow crystal oscillator to stabilize:

000: 0.0 s (delay off)

001: 0.52 s

010: 1.0 s

011: 1.5 s

100: 2.1 s

101: 2.6 s

110: 3.1 s

111: 3.6 s

Table 163: RESET

Register Address

Bit

Type

Label

Description

RESET_EVENT

0x99

7:6

R/W

RESET timer started by

RESET

00: EXT_WAKEUP

01: SYS_UP

10: PWR_UP

11: leaving PMIC RESET state (do not use

in combination with nRES_MODE = 1)

RESET_TIMER

5:0

R/W

000000: 0.000 ms

000001: 1.024 ms

000010: 2.048 ms

000011: 3.072 ms

000100: 4.096 ms

000101: 5.120 ms

….

011110: 30.720 ms

011111: 31.744 ms

100000: 32.768 ms

100001: 65.536 ms

100010: 98.304 ms

…..

111101: 983.040 ms

111110: 1015.808 ms

111111: 1048.576 ms

A.3.2

Regulator Settings

Table 164: BUCK_ILIM_A

Register Address

Bit

Type

Label

Description

BMEM_ILIM

0x9A

BUCK_ILIM_A

7:4

R/W

BUCKMEM current limit (all limits x2 in

MERGE mode)

0000:1500 mA

0001:1600 mA

0010:1700 mA

0011:1800 mA

0100:1900 mA

0101:2000 mA

0110:2100 mA

0111:2200 mA

1000:2300 mA

1001:2400 mA

1010:2500 mA

1011:2600 mA

1100:2700 mA

1101:2800 mA

1110:2900 mA

1111:3000 mA

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DA9063

System PMIC for Mobile Application Processors

Register Address

Bit

Type

Label

Description

BUCKIO current limit

BIO_ILIM

3:0

R/W

0000:1500 mA

0001:1600 mA

0010:1700 mA

0011:1800 mA

0100:1900 mA

0101:2000 mA

0110:2100 mA

0111:2200 mA

1000:2300 mA

1001:2400 mA

1010:2500 mA

1011:2600 mA

1100:2700 mA

1101:2800 mA

1110:2900 mA

1111:3000 mA

Table 165: BUCK_ILIM_B

Register Address

Bit

Type

Label

Description

BPERI_ILIM

0x9B

7:4

R/W

BUCKPERI current limit

BUCK_ILIM_B

0000:1500 mA

0001:1600 mA

0010:1700 mA

0011:1800 mA

0100:1900 mA

0101:2000 mA

0110:2100 mA

0111:2200 mA

1000:2300 mA

1001:2400 mA

1010:2500 mA

1011:2600 mA

1100:2700 mA

1101:2800 mA

1110:2900 mA

1111:3000 mA

BPRO_ILIM

3:0

R/W

BUCKPRO current limit (all limits x2 in full-

current mode)

0000:500 mA

0001:600 mA

0010:700 mA

0011:800 mA

0100:900 mA

0101:1000 mA

0110:1100 mA

0111:1200 mA

1000:1300 mA

1001:1400 mA

1010:1500 mA

1011:1600 mA

1100:1700 mA

1101:1800 mA

1110:1900 mA

1111:2000 mA

Datasheet

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162 of 219

DA9063

System PMIC for Mobile Application Processors

Table 166: BUCK_ILIM_C

Register Address

Bit

Type

Label

Description

BCORE2_ILIM

0x9C

BUCK_ILIM_C

7:4

R/W

BUCKCORE2 current limit (all limits x2 in

full-current mode)

0000:500 mA

0001:600 mA

0010:700 mA

0011:800 mA

0100:900 mA

0101:1000 mA

0110:1100 mA

0111:1200 mA

1000:1300 mA

1001:1400 mA

1010:1500 mA

1011:1600 mA

1100:1700 mA

1101:1800 mA

1110:1900 mA

1111:2000 mA

BCORE1_ILIM

3:0

R/W

BUCKCORE1 current limit (all limits x2 in

full-current mode)

0000:500 mA

0001:600 mA

0010:700 mA

0011:800 mA

0100:900 mA

0101:1000 mA

0110:1100 mA

0111:1200 mA

1000:1300 mA

1001:1400 mA

1010:1500 mA

1011:1600 mA

1100:1700 mA

1101:1800 mA

1110:1900 mA

1111:2000 mA

Table 167: BCORE2_CONF

Register Address

Bit

Type

Label

Description

BCORE2_MODE

0x9D

BCORE2_CONF

7:6

R/W

00: Sleep/Synchronous mode controlled via

voltage A and B registers

01: BUCKCORE2 always operates in Sleep

mode

10: BUCKCORE2 always operates in

Synchronous mode

11: BUCKCORE2 operates in Automatic

mode

BCORE2_PD_DIS

Reserved

0: Enable pull-down resistor

(automatically disabled in dual-phase

mode)

5

R/W

1: No pull-down resistor in disabled mode

4:3

Datasheet

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163 of 219

DA9063

System PMIC for Mobile Application Processors

Register Address

Bit

Type

Label

Description

BCORE2_FB

2:0

R/W

BUCKCORE2 feedback signal is created

out of:

xx1: VBUCKCORE2

x1x: CORE_SWS

1xx: PERI_SWS

Each switch connected to the output of the

buck may be selected; setting 0b000 is

invalid

Table 168: BCORE1_CONF

Register Address

Bit

Type

Label

Description

BCORE1_MODE

0x9E

BCORE1_CONF

7:6

R/W

00: Sleep/Synchronous mode controlled via

voltage A and B registers

01: BUCKCORE1 always operates in Sleep

mode

10: BUCKCORE1 always operates in

Synchronous mode

11: BUCKCORE1 operates in Automatic

mode

BCORE1_PD_DIS

0: Enable pull-down resistor

1: No pull-down resistor in disabled mode

5

R/W

Reserved

4:3

2:0

BCORE1_FB

BUCKCORE feedback signal is created out

of:

000:

BCORE_MERGE= 0: VBUCKCORE1

BCORE_MERGE= 1: Differential remote

sensing via VBUCKCORE1 –

VBUCKCORE2 and output capacitor

voltage sense via port CORE_SWS or

GP_FB_2

xx1: VBUCKCORE1

x1x: CORE_SWS

1xx: PERI_SWS

Each switch connected to the output of the

buck may be selected; setting 0b000

disables sense voltage mixer for

BUCKCORE

Table 169: BPRO_CONF

Register Address

Bit

Type

Label

Description

BPRO_MODE

0x9F BPRO_CONF

7:6

R/W

00: Sleep/Synchronous mode controlled via

voltage A and B registers

10: BUCKPRO always operates in Sleep

mode

10: BUCKPRO always operates in

Synchronous

11: BUCKPRO operates in Automatic

mode

BPRO_PD_DIS

0: Enable pull-down resistor

5

R/W

1: No pull-down resistor in disabled mode

Datasheet

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23-Mar-2017

CFR0011-120-00

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DA9063

System PMIC for Mobile Application Processors

Register Address

Bit

Type

Label

Description

0: Buck voltage mode

BPRO_VTT_EN

4

R/W

1: VTT mode, buck target voltage tracks

50% of VDDQ sense port (requires

BPRO_VTTR_EN to be asserted as well)

BPRO_VTTR_EN

BPRO_FB

0: VTTR port is assigned to E_CMP1V2,

port VDDQ provides status of E_GPI2

1: VTTR port provides 50% of VDDQ

voltage

3

R/W

2:0

BUCKPRO feedback signal is created out

of:

xx1: VBUCKPRO

x1x: CORE_SWS

1xx: PERI_SWS

Each switch connected to the output of the

buck may be selected; setting 0b000 is

invalid

Table 170: BIO_CONF

Register Address

Bit

Type

Label

Description

BIO_MODE

0xA0

BIO_CONF

7:6

R/W

00: Sleep/Synchronous mode controlled via

voltage A and B registers

10: BUCKIO always operates in Sleep

mode

10: BUCKIO always operates in

Synchronous

11: BUCKIO operates in Automatic mode

BIO_PD_DIS

0: Enable pull-down resistor

1: No pull-down resistor in disabled mode

5

R/W

Reserved

BIO_FB

4:3

2:0

BUCKIO feedback signal is created out of:

xx1: VBUCKBIO

x1x: CORE_SWS

1xx: PERI_SWS

Each switch connected to the output of the

buck may be selected; setting 0b000 is

invalid

Table 171: BMEM_CONF

Register Address

Bit

Type

Label

Description

BMEM_ MODE

0xA1

BMEM_CONF

7:6

R/W

00: Sleep/Synchronous mode controlled via

voltage A and B registers

01: BUCKMEM always operates in Sleep

mode

10: BUCKMEM always operates in

Synchronous mode

11: BUCKMEM operates in Automatic

mode

BMEM_PD_DIS

Reserved

0: Enable pull-down resistor

1: No pull-down resistor in disabled mode

5

R/W

4:3

Datasheet

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DA9063

System PMIC for Mobile Application Processors

Register Address

Bit

Type

Label

Description

BMEM_FB

2:0

R/W

BUCKMEM feedback signal is created out

of:

xx1: VBUCKMEM

x1x: CORE_SWS

1xx: PERI_SWS

Each switch connected to the output of the

buck may be selected; setting 0b000 is

invalid

Table 172: BPERI_CONF

Register Address Bit

0xA2 BPERI_CONF 7:6

Type

Label

Description

BPERI_ MODE

R/W

00: Sleep/Synchronous mode controlled via

voltage A and B registers

01: BUCKPERI always operates in Sleep

mode

10: BUCKPERI always operates in

Synchronous mode

11: BUCKPERI operates in Automatic

mode

BPERI_PD_DIS

0: Enable pull-down resistor

1: No pull-down resistor in disabled mode

5

R/W

Reserved

BPERI_FB

4:3

2:0

BUCKPERI feedback signal is created out

of:

xx1: VBUCKPERI

x1x: CORE_SWS

1xx: PERI_SWS

Each switch connected to the output of the

buck may be selected; setting 0b0000 is

invalid

Table 173: VBCORE2_A

Register Address

Bit

Type

Label

Description

BCORE2_SL_A

0: Configures BUCKCORE2 to

Synchronous mode, when selecting A

voltage settings

0xA3 VBCORE2_A

57

7

R/W

1: Configures BUCKCORE2 to Sleep mode,

when selecting A voltage settings

VBCORE2_A

6:0

R/W

0000000: 0.30 V

0000001: 0.31 V

0000010: 0.32 V

0000011: 0.33 V

0000100: 0.34 V

0000101: 0.35 V

…

0100101: 0.67 V

0100110: 0.68 V

0100111: 0.69 V

Datasheet

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23-Mar-2017

CFR0011-120-00

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DA9063

System PMIC for Mobile Application Processors

Register Address

Bit

Type

Label

Description

0101000: 0.70 V

0101001: 0.71 V

…

1010000: 1.10 V

…

1110011: 1.45 V

1110100: 1.46 V

1110101: 1.47 V

1110110: 1.48 V

1110111: 1.49 V

1111000: 1.50 V

1111001: 1.51 V

1111010: 1.52 V

1111011: 1.53 V

1111100: 1.54 V

1111101: 1.55 V

1111110: 1.56 V

1111111: 1.57 V

PWM mode voltage

range

Table 174: VBCORE1_A

Register Address

Bit

Type

Label

Description

BCORE1_SL_A

0: Configures BUCKCORE1 to

Synchronous mode, when selecting A

voltage settings

0xA4 VBCORE1_A

7

R/W

1: Configures BUCKCORE1 to Sleep mode,

when selecting A voltage settings

VBCORE1_A

6:0

R/W

0000000: 0.30 V

0000001: 0.31 V

0000010: 0.32 V

0000011: 0.33 V

0000100: 0.34 V

0000101: 0.35 V

…

0100101: 0.67 V

0100110: 0.68 V

0100111: 0.69 V

0101000: 0.70 V

0101001: 0.71 V

…

1010000: 1.10 V

…

1110011: 1.45 V

1110100: 1.46 V

1110101: 1.47 V

1110110: 1.48 V

1110111: 1.49 V

1111000: 1.50 V

1111001: 1.51 V

1111010: 1.52 V

1111011: 1.53 V

1111100: 1.54 V

1111101: 1.55 V

1111110: 1.56 V

1111111: 1.57 V

PWM mode voltage

range

Datasheet

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23-Mar-2017

CFR0011-120-00

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DA9063

System PMIC for Mobile Application Processors

Table 175: VBPRO_A

Register Address

Bit

Type

Label

Description

BPRO_SL_A

0: Configures BUCKPRO to Synchronous

mode, when selecting A voltage settings

1: Configures BUCKPRO to Sleep mode,

when selecting A voltage settings

0xA5

VBPRO_A

7

R/W

VBPRO_A

6:0

R/W

0000000: 0.53 V

0000001: 0.54 V

0000010: 0.55 V

0000011: 0.56 V

0000100: 0.57 V

0000101: 0.58 V

…

0010000: 0.69 V

0010001: 0.70 V

0010010: 0.71 V

0010011: 0.72 V

0010100: 0.73 V

0010101: 0.74 V

0010110: 0.75 V

…

1000011: 1.20 V

…

1110011: 1.68 V

1110100: 1.69 V

1110101: 1.70 V

1110110: 1.71 V

1110111: 1.72 V

1111000: 1.73 V

1111001: 1.74 V

1111010: 1.75 V

1111011: 1.76 V

1111100: 1.77 V

1111101: 1.78 V

1111110: 1.79 V

1111111: 1.80 V

PWM mode voltage

range

Table 176: VBMEM_A

Register Address

Bit

Type

Label

Description

BMEM_SL_A

0: Configures BUCKMEM to Synchronous

mode, when selecting A voltage settings

1: Configures BUCKMEM to Sleep mode,

when selecting A voltage settings

0xA6

VBMEM_A

7

R/W

VBMEM_A

6:0

R/W

0000000: 0.80 V

0000001: 0.82 V

0000010: 0.84 V

…

0010100: 1.20 V

...

0111100: 2.00 V

0111101: 2.02 V

0111110: 2.04 V

0111111: 2.06 V

…

1111111: 3.34 V

Datasheet

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23-Mar-2017

CFR0011-120-00

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DA9063

System PMIC for Mobile Application Processors

Table 177: VBIO_A

Register Address

Bit

Type

Label

Description

0: Configures BUCKIO to Synchronous

mode, when selecting A voltage settings

1: Configures BUCKIO to Sleep mode, when

selecting A voltage settings

0xA7

VBIO_A

7

R/W

VBIO_A

6:0

R/W

0000000: 0.80 V

0000001: 0.82 V

0000010: 0.84 V

…

0010100: 1.20 V

...

0111100: 2.00 V

0111101: 2.02 V

0111110: 2.04 V

0111111: 2.06 V

…

1111111: 3.34 V

Table 178: VBPERI_A

Register Address

Bit

Type

Label

Description

BPERI_SL_A

0: Configures BUCKPERI to Synchronous

mode, when selecting A voltage settings

1: Configures BUCKPERI to Sleep mode,

when selecting A voltage settings

0xA8

VBPERI_A

7

R/W

VBPERI_A

6:0

R/W

0000000: 0.80 V

0000001: 0.82 V

0000010: 0.84 V

…

0110010: 1.80 V

...

0111100: 2.00 V

0111101: 2.02 V

0111110: 2.04 V

0111111: 2.06 V

…

1111111: 3.34 V

Table 179: VLDO1_A

Register Address

Bit

Type

Label

Description

LDO1_SL_A

0: Configures LDO to half-current mode,

when selecting A voltage settings

1: Configures LDO to Sleep mode, when

selecting A voltage settings

0xA9

VLDO1_A

7

R/W

Reserved

6

R/W

Datasheet

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23-Mar-2017

CFR0011-120-00

169 of 219

DA9063

System PMIC for Mobile Application Processors

Register Address

Bit

Type

Label

Description

VLDO1_A

5:0

R/W

000000: 0.60 V

000001: 0.62 V

000010: 0.64 V

000011: 0.66 V

000100: 0.68 V

000101: 0.70 V

000110: 0.72 V

000111: 0.74 V

001000: 0.76 V

001001: 0.78 V

001010: 0.80 V

001011: 0.82 V

001100: 0.82 V

001101: 0.86 V

001110: 0.88 V

001111: 0.90 V

010000: 0.92 V

010001: 0.94 V

010010: 0.96 V

010011: 0.98 V

010100: 1.00 V

010101: 1.02 V

010110: 1.04 V

010111: 1.06 V

011000: 1.08 V

011001: 1.10 V

011010: 1.12 V

011011: 1.14 V

011100: 1.16 V

011101: 1.18 V

011110: 1.20 V

011111: 1.22 V

100000: 1.24 V

100001: 1.26 V

…

111000: 1.72 V

111001: 1.74 V

111010: 1.76 V

111011: 1.78 V

111100: 1.80 V

111101: 1.82 V

111110: 1.84 V

111111: 1.86 V

Table 180: VLDO2_A

Register Address

Bit

Type

Label

Description

LDO2_SL_A

0: Configures LDO to half-current mode,

when selecting A voltage settings

1: Configures LDO to Sleep mode, when

selecting A voltage settings

0xAA

VLDO2_A

7

R/W

Reserved

6

R/W

Datasheet

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CFR0011-120-00

170 of 219

DA9063

System PMIC for Mobile Application Processors

Register Address

Bit

Type

Label

Description

VLDO2_A

5:0

R/W

000000: 0.60 V

000001: 0.62 V

000010: 0.64 V

000011: 0.66 V

000100: 0.68 V

000101: 0.70 V

000110: 0.72 V

000111: 0.74 V

001000: 0.76 V

001001: 0.78 V

001010: 0.80 V

001011: 0.82 V

001100: 0.82 V

001101: 0.86 V

001110: 0.88 V

001111: 0.90 V

010000: 0.92 V

010001: 0.94 V

010010: 0.96 V

010011: 0.98 V

010100: 1.00 V

010101: 1.02 V

010110: 1.04 V

010111: 1.06 V

011000: 1.08 V

011001: 1.10 V

011010: 1.12 V

011011: 1.14 V

011100: 1.16 V

011101: 1.18 V

011110: 1.20 V

011111: 1.22 V

100000: 1.24 V

100001: 1.26 V

…

111000: 1.72 V

111001: 1.74 V

111010: 1.76 V

111011: 1.78 V

111100: 1.80 V

111101: 1.82 V

111110: 1.84 V

111111: 1.86 V

Datasheet

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23-Mar-2017

CFR0011-120-00

171 of 219

DA9063

System PMIC for Mobile Application Processors

Table 181: VLDO3_A

Register Address

Bit

Type

Label

Description

LDO3_SL_A

0: Configures LDO to half-current mode,

when selecting A voltage settings

1: Configures LDO to Sleep mode, when

selecting A voltage settings

0xAB

VLDO3_A

7

R/W

VLDO3_A

6:0

R/W

0000000: 0.90 V

0000001: 0.92 V

0000010: 0.94 V

0000011: 0.96 V

0000100: 0.98 V

0000101: 1.00 V

0000110: 1.02 V

0000111: 1.04 V

0001000: 1.06 V

0001001: 1.08 V

0001010: 1.10 V

0001011: 1.12 V

0001100: 1.14 V

0001101: 1.16 V

0001110: 1.18 V

0001111: 1.20 V

0010000: 1.22 V

0010001: 1.24 V

0010010: 1.26 V

0010011: 1.28 V

0010100: 1.30 V

0010101: 1.32 V

...

1110000: 3.14 V

1110001: 3.16 V

1110010: 3.18 V

1110011: 3.20 V

1110100: 3.22 V

1110101: 3.24 V

1110110: 3.26 V

1110111: 3.28 V

1111000: 3.30 V

1111001: 3.32 V

1111010: 3.34 V

1111011: 3.36 V

1111100: 3.38 V

1111101: 3.40 V

1111110: 3.42 V

1111111: 3.44 V

Datasheet

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23-Mar-2017

CFR0011-120-00

172 of 219

DA9063

System PMIC for Mobile Application Processors

Table 182: VLDO4_A

Register Address

Bit

Type

Label

Description

LDO4_SL_A

0: Configures LDO to half-current mode,

when selecting A voltage settings

1: Configures LDO to Sleep mode, when

selecting A voltage settings

0xAC

VLDO4_A

7

R/W

VLDO4_A

6:0

R/W

0000000: 0.90 V

0000001: 0.92 V

0000010: 0.94 V

0000011: 0.96 V

0000100: 0.98 V

0000101: 1.00 V

0000110: 1.02 V

0000111: 1.04 V

0001000: 1.06 V

0001001: 1.08 V

0001010: 1.10 V

0001011: 1.12 V

0001100: 1.14 V

0001101: 1.16 V

0001110: 1.18 V

0001111: 1.20 V

0010000: 1.22 V

0010001: 1.24 V

0010010: 1.26 V

0010011: 1.28 V

0010100: 1.30 V

0010101: 1.32 V

...

1110000: 3.14 V

1110001: 3.16 V

1110010: 3.18 V

1110011: 3.20 V

1110100: 3.22 V

1110101: 3.24 V

1110110: 3.26 V

1110111: 3.28 V

1111000: 3.30 V

1111001: 3.32 V

1111010: 3.34 V

1111011: 3.36 V

1111100: 3.38 V

1111101: 3.40 V

1111110: 3.42 V

1111111: 3.44 V

Datasheet

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23-Mar-2017

CFR0011-120-00

173 of 219

DA9063

System PMIC for Mobile Application Processors

Table 183: VLDO5_A

Register Address

Bit

Type

Label

Description

LDO5_SL_A

0: Configures LDO to half-current mode,

when selecting A voltage settings

1: Configures LDO to Sleep mode, when

selecting A voltage settings

0xAD

VLDO5_A

7

R/W

Reserved

VLDO5_A

6

R/W

5:0

000000: 0.90 V

000001: 0.90 V

000010: 0.90 V

000011: 0.95 V

000100: 1.00 V

000101: 1.05 V

000110: 1.10 V

000111: 1.15 V

001000: 1.20 V

001001: 1.25 V

001010: 1.30 V

001011: 1.35 V

001100: 1.40 V

001101: 1.45 V

001110: 1.50 V

001111: 1.55 V

010000: 1.60 V

010001: 1.65 V

010010: 1.70 V

010011: 1.75 V

010100: 1.80 V

010101: 1.85 V

...

100010: 2.50 V

100011: 2.55 V

100100: 2.60 V

100101: 2.65 V

100110: 2.70 V

100111: 2.75 V

101000: 2.80 V

101001: 2.85 V

101010: 2.90 V

101011: 2.95 V

101100: 3.00 V

101101: 3.05 V

101110: 3.10 V

101111: 3.15 V

110000: 3.20 V

110001: 3.25 V

110010: 3.30 V

110011: 3.35 V

110100: 3.40 V

110101: 3.45 V

110110: 3.50 V

110111: 3.55 V

111000: 3.60 V

>111000: 3.60 V

Datasheet

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23-Mar-2017

CFR0011-120-00

174 of 219

DA9063

System PMIC for Mobile Application Processors

Table 184: VLDO6_A

Register Address

Bit

Type

Label

Description

LDO6_SL_A

0: Configures LDO to half-current mode,

when selecting A voltage settings

1: Configures LDO to Sleep mode, when

selecting A voltage settings

0xAE

VLDO6_A

7

R/W

Reserved

VLDO6_A

6

R/W

5:0

000000: 0.90 V

000001: 0.90 V

000010: 0.90 V

000011: 0.95 V

000100: 1.00 V

000101: 1.05 V

000110: 1.10 V

000111: 1.15 V

001000: 1.20 V

001001: 1.25 V

001010: 1.30 V

001011: 1.35 V

001100: 1.40 V

001101: 1.45 V

001110: 1.50 V

001111: 1.55 V

010000: 1.60 V

010001: 1.65 V

010010: 1.70 V

010011: 1.75 V

010100: 1.80 V

010101: 1.85 V

...

100010: 2.50 V

100011: 2.55 V

100100: 2.60 V

100101: 2.65 V

100110: 2.70 V

100111: 2.75 V

101000: 2.80 V

101001: 2.85 V

101010: 2.90 V

101011: 2.95 V

101100: 3.00 V

101101: 3.05 V

101110: 3.10 V

101111: 3.15 V

110000: 3.20 V

110001: 3.25 V

110010: 3.30 V

110011: 3.35 V

110100: 3.40 V

110101: 3.45 V

110110: 3.50 V

110111: 3.55 V

111000: 3.60 V

>111000: 3.60 V

Datasheet

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23-Mar-2017

CFR0011-120-00

175 of 219

DA9063

System PMIC for Mobile Application Processors

Table 185: VLDO7_A

Register Address

Bit

Type

Label

Description

LDO7_SL_A

0: Configures LDO to half-current mode,

when selecting A voltage settings

1: Configures LDO to Sleep mode, when

selecting A voltage settings

0xAF

VLDO7_A

7

R/W

Reserved

VLDO7_A

6

R/W

5:0

000000: 0.90 V

000001: 0.90 V

000010: 0.90 V

000011: 0.95 V

000100: 1.00 V

000101: 1.05 V

000110: 1.10 V

000111: 1.15 V

001000: 1.20 V

001001: 1.25 V

001010: 1.30 V

001011: 1.35 V

001100: 1.40 V

001101: 1.45 V

001110: 1.50 V

001111: 1.55 V

010000: 1.60 V

010001: 1.65 V

010010: 1.70 V

010011: 1.75 V

010100: 1.80 V

010101: 1.85 V

...

100010: 2.50 V

100011: 2.55 V

100100: 2.60 V

100101: 2.65 V

100110: 2.70 V

100111: 2.75 V

101000: 2.80 V

101001: 2.85 V

101010: 2.90 V

101011: 2.95 V

101100: 3.00 V

101101: 3.05 V

101110: 3.10 V

101111: 3.15 V

110000: 3.20 V

110001: 3.25 V

110010: 3.30 V

110011: 3.35 V

110100: 3.40 V

110101: 3.45 V

110110: 3.50 V

110111: 3.55 V

111000: 3.60 V

>111000: 3.60 V

Datasheet

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23-Mar-2017

CFR0011-120-00

176 of 219

DA9063

System PMIC for Mobile Application Processors

Table 186: VLDO8_A

Register Address

Bit

Type

Label

Description

LDO8_SL_A

0: Configures LDO to half-current mode,

when selecting A voltage settings

1: Configures LDO to Sleep mode, when

selecting A voltage settings

0xB0

VLDO8_A

7

R/W

Reserved

VLDO8_A

6

R/W

5:0

000000: 0.90 V

000001: 0.90 V

000010: 0.90 V

000011: 0.95 V

000100: 1.00 V

000101: 1.05 V

000110: 1.10 V

000111: 1.15 V

001000: 1.20 V

001001: 1.25 V

001010: 1.30 V

001011: 1.35 V

001100: 1.40 V

001101: 1.45 V

001110: 1.50 V

001111: 1.55 V

010000: 1.60 V

010001: 1.65 V

010010: 1.70 V

010011: 1.75 V

010100: 1.80 V

010101: 1.85 V

...

100010: 2.50 V

100011: 2.55 V

100100: 2.60 V

100101: 2.65 V

100110: 2.70 V

100111: 2.75 V

101000: 2.80 V

101001: 2.85 V

101010: 2.90 V

101011: 2.95 V

101100: 3.00 V

101101: 3.05 V

101110: 3.10 V

101111: 3.15 V

110000: 3.20 V

110001: 3.25 V

110010: 3.30 V

110011: 3.35 V

110100: 3.40 V

110101: 3.45 V

110110: 3.50 V

110111: 3.55 V

111000: 3.60 V

>111000: 3.60 V

Datasheet

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23-Mar-2017

CFR0011-120-00

177 of 219

DA9063

System PMIC for Mobile Application Processors

Table 187: VLDO9_A

Register Address

Bit

Type

Label

Description

LDO9_SL_A

0: Configures LDO to half-current mode,

when selecting A voltage settings

1: Configures LDO to Sleep mode, when

selecting A voltage settings

0xB1

VLDO9_A

7

R/W

Reserved

VLDO9_A

6

R/W

5:0

000000: not used

000001: 0.95 V

000010: 0.95 V

000011: 0.95 V

000100: 1.00 V

000101: 1.05 V

000110: 1.10 V

000111: 1.15 V

001000: 1.20 V

001001: 1.25 V

001010: 1.30 V

001011: 1.35 V

001100: 1.40 V

001101: 1.45 V

001110: 1.50 V

001111: 1.55 V

010000: 1.60 V

010001: 1.65 V

010010: 1.70 V

010011: 1.75 V

010100: 1.80 V

010101: 1.85 V

...

100010: 2.50 V

100011: 2.55 V

100100: 2.60 V

100101: 2.65 V

100110: 2.70 V

100111: 2.75 V

101000: 2.80 V

101001: 2.85 V

101010: 2.90 V

101011: 2.95 V

101100: 3.00 V

101101: 3.05 V

101110: 3.10 V

101111: 3.15 V

110000: 3.20 V

110001: 3.25 V

110010: 3.30 V

110011: 3.35 V

110100: 3.40 V

110101: 3.45 V

110110: 3.50 V

110111: 3.55 V

111000: 3.60 V

>111000: 3.60 V

Datasheet

DA9063_2v1

23-Mar-2017

CFR0011-120-00

178 of 219

DA9063

System PMIC for Mobile Application Processors

Table 188: VLDO10_A

Register Address

Bit

Type

Label

Description

LDO10_SL_A

0: Configures LDO to half-current mode,

when selecting A voltage settings

1: Configures LDO to Sleep mode, when

selecting A voltage settings

0xB2

VLDO10_A

7

R/W

Reserved

6

R/W

VLDO10_A

5:0

000000: 0.90 V

000001: 0.90 V

000010: 0.90 V

000011: 0.95 V

000100: 1.00 V

000101: 1.05 V

000110: 1.10 V

000111: 1.15 V

001000: 1.20 V

001001: 1.25 V

001010: 1.30 V

001011: 1.35 V

001100: 1.40 V

001101: 1.45 V

001110: 1.50 V

001111: 1.55 V

010000: 1.60 V

010001: 1.65 V

010010: 1.70 V

010011: 1.75 V

010100: 1.80 V

010101: 1.85 V

...

100010: 2.50 V

100011: 2.55 V

100100: 2.60 V

100101: 2.65 V

100110: 2.70 V

100111: 2.75 V

101000: 2.80 V

101001: 2.85 V

101010: 2.90 V

101011: 2.95 V

101100: 3.00 V

101101: 3.05 V

101110: 3.10 V

101111: 3.15 V

110000: 3.20 V

110001: 3.25 V

110010: 3.30 V

110011: 3.35 V

110100: 3.40 V

110101: 3.45 V

110110: 3.50 V

110111: 3.55 V

111000: 3.60 V

>111000: 3.60 V

Datasheet

DA9063_2v1

23-Mar-2017

CFR0011-120-00

179 of 219

DA9063

System PMIC for Mobile Application Processors

Table 189: VLDO11_A

Register Address

Bit

Type

Label

Description

LDO11_SL_A

0: Configures LDO to half-current mode,

when selecting A voltage settings

1: Configures LDO to Sleep mode, when

selecting A voltage settings

0xB3

VLDO11_A

7:4

R/W

Reserved

6

R/W

VLDO11_A

5:0

000000: 0.90 V

000001: 0.90 V

000010: 0.90 V

000011: 0.95 V

000100: 1.00 V

000101: 1.05 V

000110: 1.10 V

000111: 1.15 V

001000: 1.20 V

001001: 1.25 V

001010: 1.30 V

001011: 1.35 V

001100: 1.40 V

001101: 1.45 V

001110: 1.50 V

001111: 1.55 V

010000: 1.60 V

010001: 1.65 V

010010: 1.70 V

010011: 1.75 V

010100: 1.80 V

010101: 1.85 V

...

100010: 2.50 V

100011: 2.55 V

100100: 2.60 V

100101: 2.65 V

100110: 2.70 V

100111: 2.75 V

101000: 2.80 V

101001: 2.85 V

101010: 2.90 V

101011: 2.95 V

101100: 3.00 V

101101: 3.05 V

101110: 3.10 V

101111: 3.15 V

110000: 3.20 V

110001: 3.25 V

110010: 3.30 V

110011: 3.35 V

110100: 3.40 V

110101: 3.45 V

110110: 3.50 V

110111: 3.55 V

111000: 3.60 V

>111000: 3.60 V

Datasheet

DA9063_2v1

23-Mar-2017

CFR0011-120-00

180 of 219

DA9063

System PMIC for Mobile Application Processors

Table 190: VBCORE2_B

Register Address

Bit

Type

Label

Description

BCORE2_SL_B

0: Configures BUCKCORE2 to

Synchronous mode, when selecting B

voltage settings

0xB4 VBCORE2_B

7

R/W

1: Configures BUCKCORE2 to Sleep mode,

when selecting B voltage settings

VBCORE2_B

6:0

R/W

0000000: 0.30 V

0000001: 0.31 V

0000010: 0.32 V

0000011: 0.33 V

0000100: 0.34 V

0000101: 0.35 V

…

0100101: 0.67 V

0100110: 0.68 V

0100111: 0.69 V

0101000: 0.70 V

0101001: 0.71 V

…

0111100: 0.90 V

…

1110011: 1.45 V

1110100: 1.46 V

1110101: 1.47 V

1110110: 1.48 V

1110111: 1.49 V

1111000: 1.50 V

1111001: 1.51 V

1111010: 1.52 V

1111011: 1.53 V

1111100: 1.54 V

1111101: 1.55 V

1111110: 1.56 V

1111111: 1.57 V

PWM mode voltage

range

Datasheet

DA9063_2v1

23-Mar-2017

CFR0011-120-00

181 of 219

DA9063

System PMIC for Mobile Application Processors

Table 191: VBCORE1_B

Register Address

Bit

Type

Label

Description

BCORE1_SL_B

0xB5 VBCORE1_B

7

R/W

0: Configures BUCKCORE1 to Synchronous

mode, when selecting B voltage settings

1: Configures BUCKCORE1 to Sleep

mode, when selecting B voltage settings

VBCORE1_B

6:0

R/W

0000000: 0.30 V

0000001: 0.31 V

0000010: 0.32 V

0000011: 0.33 V

0000100: 0.34 V

0000101: 0.35 V

…

0100101: 0.67 V

0100110: 0.68 V

0100111: 0.69 V

0101000: 0.70 V

0101001: 0.71 V

…

0111100: 0.90 V

…

1110011: 1.45 V

1110100: 1.46 V

1110101: 1.47 V

1110110: 1.48 V

1110111: 1.49 V

1111000: 1.50 V

1111001: 1.51 V

1111010: 1.52 V

1111011: 1.53 V

1111100: 1.54 V

1111101: 1.55 V

1111110: 1.56 V

1111111: 1.57 V

PWM mode voltage

range

Datasheet

DA9063_2v1

23-Mar-2017

CFR0011-120-00

182 of 219

DA9063

System PMIC for Mobile Application Processors

Table 192: VBPRO_B

Register Address

Bit

Type

Label

Description

BPRO_SL_B

0xB6

VBPRO_B

7

R/W

0: Configures BUCKPRO to Synchronous

mode, when selecting B voltage settings

1: Configures BUCKPRO to Sleep mode,

when selecting B voltage settings

VBPRO_B

6:0

R/W

0000000: 0.53 V

0000001: 0.54 V

0000010: 0.55 V

0000011: 0.56 V

0000100: 0.57 V

0000101: 0.58 V

…

0010000: 0.69 V

0010001: 0.70 V

0010010: 0.71 V

0010011: 0.72 V

0010100: 0.73 V

0010101: 0.74 V

0010110: 0.75 V

…

1000011: 1.20 V

…

1110011: 1.68 V

1110100: 1.69 V

1110101: 1.70 V

1110110: 1.71 V

1110111: 1.72 V

1111000: 1.73 V

1111001: 1.74 V

1111010: 1.75 V

1111011: 1.76 V

1111100: 1.77 V

1111101: 1.78 V

1111110: 1.79 V

1111111: 1.80 V

PWM mode voltage

range

Datasheet

DA9063_2v1

23-Mar-2017

CFR0011-120-00

183 of 219

DA9063

System PMIC for Mobile Application Processors

Table 193: VBMEM_B

Register Address

Bit

Type

Label

Description

BMEM_SL_B

0xB7

VBMEM_B

7

R/W

0: Configures BUCKMEM to Synchronous

mode, when selecting B voltage settings

1: Configures BUCKMEM to Sleep mode,

when selecting B voltage settings

VBMEM_B

6:0

R/W

0000000: 0.80 V

0000001: 0.82 V

0000010: 0.84 V

…

0010100: 1.20 V

...

0111100: 2.00 V

0111101: 2.02 V

0111110: 2.04 V

0111111: 2.06 V

…

1111111: 3.34 V

Table 194: VBIO_B

Register Address

Bit

Type

Label

Description

BIO_SL_B

0: Configures BUCKIO to Synchronous

mode, when selecting B voltage settings

1: Configures BUCKIO to Sleep mode, when

selecting B voltage settings

0xB8

VBIO_B

7

R/W

VBIO_B

6:0

R/W

0000000: 0.80 V

0000001: 0.82 V

0000010: 0.84 V

…

0010100: 1.20 V

...

0111100: 2.00 V

0111101: 2.02 V

0111110: 2.04 V

0111111: 2.06 V

…

1111111: 3.34 V

Table 195: VBPERI_B

Register Address

Bit

Type

Label

Description

BPERI_SL_B

0xB9

VBPERI_B

7

R/W

0: Configures BUCKPERI to Synchronous

mode, when selecting A voltage settings

1: Configures BUCKPERI to Sleep mode,

when selecting B voltage settings

VBPERI_B

6:0

R/W

0000000: 0.80 V

0000001: 0.82 V

0000010: 0.84 V

…

0110010: 1.80 V

...

0111100: 2.00 V

0111101: 2.02 V

0111110: 2.04 V

0111111: 2.06 V

…

1111111: 3.34 V

Datasheet

DA9063_2v1

23-Mar-2017

CFR0011-120-00

184 of 219

DA9063

System PMIC for Mobile Application Processors

Table 196: VLDO1_B

Register Address

Bit

Type

Label

Description

LDO1_SL_B

0: Configures LDO to half-current mode,

when selecting B voltage settings

1: Configures LDO to Sleep mode, when

selecting B voltage settings

0xBA

VLDO1_B

7

R/W

Reserved

VLDO1_B

6

R/W

5:0

000000: 0.60 V

000001: 0.62 V

000010: 0.64 V

000011: 0.66 V

000100: 0.68 V

000101: 0.70 V

000110: 0.72 V

000111: 0.74 V

001000: 0.76 V

001001: 0.78 V

001010: 0.80 V

001011: 0.82 V

001100: 0.82 V

001101: 0.86 V

001110: 0.88 V

001111: 0.90 V

010000: 0.92 V

010001: 0.94 V

010010: 0.96 V

010011: 0.98 V

010100: 1.00 V

010101: 1.02 V

010110: 1.04 V

010111: 1.06 V

011000: 1.08 V

011001: 1.10 V

011010: 1.12 V

011011: 1.14 V

011100: 1.16 V

011101: 1.18 V

011110: 1.20 V

011111: 1.22 V

100000: 1.24 V

100001: 1.26 V

…

111000: 1.72 V

111001: 1.74 V

111010: 1.76 V

111011: 1.78 V

111100: 1.80 V

111101: 1.82 V

111110: 1.84 V

111111: 1.86 V

Datasheet

DA9063_2v1

23-Mar-2017

CFR0011-120-00

185 of 219

DA9063

System PMIC for Mobile Application Processors

Table 197: VLDO2_B

Register Address

Bit

Type

Label

Description

LDO2_SL_B

0: Configures LDO to half-current mode,

when selecting B voltage settings

1: Configures LDO to Sleep mode, when

selecting B voltage settings

0xBB

VLDO2_B

7

R/W

Reserved

VLDO2_B

6

R/W

5:0

000000: 0.60 V

000001: 0.62 V

000010: 0.64 V

000011: 0.66 V

000100: 0.68 V

000101: 0.70 V

000110: 0.72 V

000111: 0.74 V

001000: 0.76 V

001001: 0.78 V

001010: 0.80 V

001011: 0.82 V

001100: 0.82 V

001101: 0.86 V

001110: 0.88 V

001111: 0.90 V

010000: 0.92 V

010001: 0.94 V

010010: 0.96 V

010011: 0.98 V

010100: 1.00 V

010101: 1.02 V

010110: 1.04 V

010111: 1.06 V

011000: 1.08 V

011001: 1.10 V

011010: 1.12 V

011011: 1.14 V

011100: 1.16 V

011101: 1.18 V

011110: 1.20 V

011111: 1.22 V

100000: 1.24 V

100001: 1.26 V

…

111000: 1.72 V

111001: 1.74 V

111010: 1.76 V

111011: 1.78 V

111100: 1.80 V

111101: 1.82 V

111110: 1.84 V

111111: 1.86 V

Datasheet

DA9063_2v1

23-Mar-2017

CFR0011-120-00

186 of 219

DA9063

System PMIC for Mobile Application Processors

Table 198: VLDO3_B

Register Address

Bit

Type

Label

Description

LDO3_SL_B

0: Configures LDO to half-current mode,

when selecting B voltage settings

1: Configures LDO to Sleep mode, when

selecting B voltage settings

0xBC

VLDO3_B

7

R/W

VLDO3_B

6:0

R/W

0000000: 0.90 V

0000001: 0.92 V

0000010: 0.94 V

0000011: 0.96 V

0000100: 0.98 V

0000101: 1.00 V

0000110: 1.02 V

0000111: 1.04 V

0001000: 1.06 V

0001001: 1.08 V

0001010: 1.10 V

0001011: 1.12 V

0001100: 1.14 V

0001101: 1.16 V

0001110: 1.18 V

0001111: 1.20 V

0010000: 1.22 V

0010001: 1.24 V

0010010: 1.26 V

0010011: 1.28 V

0010100: 1.30 V

0010101: 1.32 V

...

1110000: 3.14 V

1110001: 3.16 V

1110010: 3.18 V

1110011: 3.20 V

1110100: 3.22 V

1110101: 3.24 V

1110110: 3.26 V

1110111: 3.28 V

1111000: 3.30 V

1111001: 3.32 V

1111010: 3.34 V

1111011: 3.36 V

1111100: 3.38 V

1111101: 3.40 V

1111110: 3.42 V

1111111: 3.44 V

Datasheet

DA9063_2v1

23-Mar-2017

CFR0011-120-00

187 of 219

DA9063

System PMIC for Mobile Application Processors

Table 199: VLDO4_B

Register Address

Bit

Type

Label

Description

LDO4_SL_B

0: Configures LDO to half-current mode,

when selecting B voltage settings

1: Configures LDO to Sleep mode, when

selecting B voltage settings

0xBD

VLDO4_B

7

R/W

VLDO4_B

6:0

R/W

0000000: 0.90 V

0000001: 0.92 V

0000010: 0.94 V

0000011: 0.96 V

0000100: 0.98 V

0000101: 1.00 V

0000110: 1.02 V

0000111: 1.04 V

0001000: 1.06 V

0001001: 1.08 V

0001010: 1.10 V

0001011: 1.12 V

0001100: 1.14 V

0001101: 1.16 V

0001110: 1.18 V

0001111: 1.20 V

0010000: 1.22 V

0010001: 1.24 V

0010010: 1.26 V

0010011: 1.28 V

0010100: 1.30 V

0010101: 1.32 V

...

1110000: 3.14 V

1110001: 3.16 V

1110010: 3.18 V

1110011: 3.20 V

1110100: 3.22 V

1110101: 3.24 V

1110110: 3.26 V

1110111: 3.28 V

1111000: 3.30 V

1111001: 3.32 V

1111010: 3.34 V

1111011: 3.36 V

1111100: 3.38 V

1111101: 3.40 V

1111110: 3.42 V

1111111: 3.44 V

Datasheet

DA9063_2v1

23-Mar-2017

CFR0011-120-00

188 of 219

DA9063

System PMIC for Mobile Application Processors

Table 200: VLDO5_B

Register Address

Bit

Type

Label

Description

LDO5_SL_B

0: Configures LDO to half-current mode,

when selecting B voltage settings

1: Configures LDO to Sleep mode, when

selecting B voltage settings

0xBE

VLDO5_B

7

R/W

Reserved

VLDO5_B

6

R/W

5:0

000000: 0.90 V

000001: 0.90 V

000010: 0.90 V

000011: 0.95 V

000100: 1.00 V

000101: 1.05 V

000110: 1.10 V

000111: 1.15 V

001000: 1.20 V

001001: 1.25 V

001010: 1.30 V

001011: 1.35 V

001100: 1.40 V

001101: 1.45 V

001110: 1.50 V

001111: 1.55 V

010000: 1.60 V

010001: 1.65 V

010010: 1.70 V

010011: 1.75 V

010100: 1.80 V

010101: 1.85 V

...

100010: 2.50 V

100011: 2.55 V

100100: 2.60 V

100101: 2.65 V

100110: 2.70 V

100111: 2.75 V

101000: 2.80 V

101001: 2.85 V

101010: 2.90 V

101011: 2.95 V

101100: 3.00 V

101101: 3.05 V

101110: 3.10 V

101111: 3.15 V

110000: 3.20 V

110001: 3.25 V

110010: 3.30 V

110011: 3.35 V

110100: 3.40 V

110101: 3.45 V

110110: 3.50 V

110111: 3.55 V

111000: 3.60 V

>111000: 3.60 V

Datasheet

DA9063_2v1

23-Mar-2017

CFR0011-120-00

189 of 219

DA9063

System PMIC for Mobile Application Processors

Table 201: VLDO6_B

Register Address

Bit

Type

Label

Description

LDO6_SL_B

0: Configures LDO to half-current mode,

when selecting B voltage settings

1: Configures LDO to Sleep mode, when

selecting B voltage settings

0xBF

VLDO6_B

7

R/W

Reserved

VLDO6_B

6

R/W

5:0

000000: 0.90 V

000001: 0.90 V

000010: 0.90 V

000011: 0.95 V

000100: 1.00 V

000101: 1.05 V

000110: 1.10 V

000111: 1.15 V

001000: 1.20 V

001001: 1.25 V

001010: 1.30 V

001011: 1.35 V

001100: 1.40 V

001101: 1.45 V

001110: 1.50 V

001111: 1.55 V

010000: 1.60 V

010001: 1.65 V

010010: 1.70 V

010011: 1.75 V

010100: 1.80 V

010101: 1.85 V

...

100010: 2.50 V

100011: 2.55 V

100100: 2.60 V

100101: 2.65 V

100110: 2.70 V

100111: 2.75 V

101000: 2.80 V

101001: 2.85 V

101010: 2.90 V

101011: 2.95 V

101100: 3.00 V

101101: 3.05 V

101110: 3.10 V

101111: 3.15 V

110000: 3.20 V

110001: 3.25 V

110010: 3.30 V

110011: 3.35 V

110100: 3.40 V

110101: 3.45 V

110110: 3.50 V

110111: 3.55 V

111000: 3.60 V

>111000: 3.60 V

Datasheet

DA9063_2v1

23-Mar-2017

CFR0011-120-00

190 of 219

DA9063

System PMIC for Mobile Application Processors

Table 202: VLDO7_B

Register Address

Bit

Type

Label

Description

LDO7_SL_B

0: Configures LDO to half-current mode,

when selecting B voltage settings

1: Configures LDO to Sleep mode, when

selecting B voltage settings

0xC0

VLDO7_B

7

R/W

Reserved

VLDO7_B

6

R/W

5:0

000000: 0.90 V

000001: 0.90 V

000010: 0.90 V

000011: 0.95 V

000100: 1.00 V

000101: 1.05 V

000110: 1.10 V

000111: 1.15 V

001000: 1.20 V

001001: 1.25 V

001010: 1.30 V

001011: 1.35 V

001100: 1.40 V

001101: 1.45 V

001110: 1.50 V

001111: 1.55 V

010000: 1.60 V

010001: 1.65 V

010010: 1.70 V

010011: 1.75 V

010100: 1.80 V

010101: 1.85 V

...

100010: 2.50 V

100011: 2.55 V

100100: 2.60 V

100101: 2.65 V

100110: 2.70 V

100111: 2.75 V

101000: 2.80 V

101001: 2.85 V

101010: 2.90 V

101011: 2.95 V

101100: 3.00 V

101101: 3.05 V

101110: 3.10 V

101111: 3.15 V

110000: 3.20 V

110001: 3.25 V

110010: 3.30 V

110011: 3.35 V

110100: 3.40 V

110101: 3.45 V

110110: 3.50 V

110111: 3.55 V

111000: 3.60 V

>111000: 3.60 V

Datasheet

DA9063_2v1

23-Mar-2017

CFR0011-120-00

191 of 219

DA9063

System PMIC for Mobile Application Processors

Table 203: VLDO8_B

Register Address

Bit

Type

Label

Description

LDO8_SL_B

0: Configures LDO to half-current mode,

when selecting B voltage settings

1: Configures LDO to Sleep mode, when

selecting B voltage settings

0xC1

VLDO8_B

7

R/W

Reserved

VLDO8_B

6

R/W

5:0

000000: 0.90 V

000001: 0.90 V

000010: 0.90 V

000011: 0.95 V

000100: 1.00 V

000101: 1.05 V

000110: 1.10 V

000111: 1.15 V

001000: 1.20 V

001001: 1.25 V

001010: 1.30 V

001011: 1.35 V

001100: 1.40 V

001101: 1.45 V

001110: 1.50 V

001111: 1.55 V

010000: 1.60 V

010001: 1.65 V

010010: 1.70 V

010011: 1.75 V

010100: 1.80 V

010101: 1.85 V

...

100010: 2.50 V

100011: 2.55 V

100100: 2.60 V

100101: 2.65 V

100110: 2.70 V

100111: 2.75 V

101000: 2.80 V

101001: 2.85 V

101010: 2.90 V

101011: 2.95 V

101100: 3.00 V

101101: 3.05 V

101110: 3.10 V

101111: 3.15 V

110000: 3.20 V

110001: 3.25 V

110010: 3.30 V

110011: 3.35 V

110100: 3.40 V

110101: 3.45 V

110110: 3.50 V

110111: 3.55 V

111000: 3.60 V

>111000: 3.60 V

Datasheet

DA9063_2v1

23-Mar-2017

CFR0011-120-00

192 of 219

DA9063

System PMIC for Mobile Application Processors

Table 204: VLDO9_B

Register Address

Bit

Type

Label

Description

LDO9_SL_B

0: Configures LDO to half-current mode,

when selecting B voltage settings

1: Configures LDO to Sleep mode, when

selecting B voltage settings

0xC2

VLDO9_B

7

R/W

Reserved

VLDO9_B

6

R/W

5:0

000000: 0.95 V

000001: 0.95 V

000010: 0.95 V

000011: 0.95 V

000100: 1.00 V

000101: 1.05 V

000110: 1.10 V

000111: 1.15 V

001000: 1.20 V

001001: 1.25 V

001010: 1.30 V

001011: 1.35 V

001100: 1.40 V

001101: 1.45 V

001110: 1.50 V

001111: 1.55 V

010000: 1.60 V

010001: 1.65 V

010010: 1.70 V

010011: 1.75 V

010100: 1.80 V

010101: 1.85 V

...

100010: 2.50 V

100011: 2.55 V

100100: 2.60 V

100101: 2.65 V

100110: 2.70 V

100111: 2.75 V

101000: 2.80 V

101001: 2.85 V

101010: 2.90 V

101011: 2.95 V

101100: 3.00 V

101101: 3.05 V

101110: 3.10 V

101111: 3.15 V

110000: 3.20 V

110001: 3.25 V

110010: 3.30 V

110011: 3.35 V

110100: 3.40 V

110101: 3.45 V

110110: 3.50 V

110111: 3.55 V

111000: 3.60 V

>111000: 3.60 V

Datasheet

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23-Mar-2017

CFR0011-120-00

193 of 219

DA9063

System PMIC for Mobile Application Processors

Table 205: VLDO10_B

Register Address

Bit

Type

Label

Description

LDO10_SL_B

0: Configures LDO to half-current mode,

when selecting B voltage settings

1: Configures LDO to Sleep mode, when

selecting B voltage settings

0xC3

VLDO10_B

7

R/W

Reserved

6

R/W

VLDO10_B

5:0

000000: 0.90 V

000001: 0.90 V

000010: 0.90 V

000011: 0.95 V

000100: 1.00 V

000101: 1.05 V

000110: 1.10 V

000111: 1.15 V

001001: 1.25 V

001010: 1.30 V

001011: 1.35 V

001100: 1.40 V

001101: 1.45 V

001110: 1.50 V

001111: 1.55 V

010000: 1.60 V

010001: 1.65 V

010010: 1.70 V

010011: 1.75 V

010100: 1.80 V

010101: 1.85 V

...

100010: 2.50 V

100011: 2.55 V

100100: 2.60 V

100101: 2.65 V

100110: 2.70 V

100111: 2.75 V

101000: 2.80 V

101001: 2.85 V

101010: 2.90 V

101011: 2.95 V

101100: 3.00 V

101101: 3.05 V

101110: 3.10 V

101111: 3.15 V

110000: 3.20 V

110001: 3.25 V

110010: 3.30 V

110011: 3.35 V

110100: 3.40 V

110101: 3.45 V

110110: 3.50 V

110111: 3.55 V

111000: 3.60 V

>111000: 3.60 V

Datasheet

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23-Mar-2017

CFR0011-120-00

194 of 219

DA9063

System PMIC for Mobile Application Processors

Table 206: VLDO11_B

Register Address

Bit

Type

Label

Description

LDO1_SL_B

0: Configures LDO to half-current mode,

when selecting B voltage settings

1: Configures LDO to Sleep mode, when

selecting B voltage settings

0xC4

VLDO11_B

7:4

R/W

Reserved

6

R/W

VLDO11_B

5:0

000000: 0.90 V

000001: 0.90 V

000010: 0.90 V

000011: 0.95 V

000100: 1.00 V

000101: 1.05 V

000110: 1.10 V

000111: 1.15 V

001001: 1.25 V

001010: 1.30 V

001011: 1.35 V

001100: 1.40 V

001101: 1.45 V

001110: 1.50 V

001111: 1.55 V

010000: 1.60 V

010001: 1.65 V

010010: 1.70 V

010011: 1.75 V

010100: 1.80 V

010101: 1.85 V

...

100010: 2.50 V

100011: 2.55 V

100100: 2.60 V

100101: 2.65 V

100110: 2.70 V

100111: 2.75 V

101000: 2.80 V

101001: 2.85 V

101010: 2.90 V

101011: 2.95 V

101100: 3.00 V

101101: 3.05 V

101110: 3.10 V

101111: 3.15 V

110000: 3.20 V

110001: 3.25 V

110010: 3.30 V

110011: 3.35 V

110100: 3.40 V

110101: 3.45 V

110110: 3.50 V

110111: 3.55 V

111000: 3.60 V

>111000: 3.60 V

Datasheet

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23-Mar-2017

CFR0011-120-00

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DA9063

System PMIC for Mobile Application Processors

A.3.3

Backup Battery Charger

Table 207: BBAT_CONT

Register Address

Bit

Type

Label

Description

BCHG_ISET

0000: disabled

0001: 100 µA

0010: 200 µA

0011: 300 µA

0100: 400 µA

0101: 500 µA

0110: 600 µA

0111: 700 µA

1000: 800 µA

1001: 900 µA

1010: 1 mA

0xC5

BBAT_CONT

7:4

R/W

1011: 2 mA

1100: 3 mA

1101: 4 mA

1110: 5 mA

1111: 6 mA

BCHG_VSET

3:0

R/W

0000: disabled

0001: 1.1 V

0010: 1.2 V

0011: 1.4 V

0100: 1.6 V

0101: 1.8 V

0110: 2.0 V

0111: 2.2 V

1000: 2.4 V

1001: 2.5 V

1010: 2.6 V

1011: 2.7 V

1100: 2.8 V

1101: 2.9 V

1110: 3.0 V

1111: 3.1 V

Datasheet

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CFR0011-120-00

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System PMIC for Mobile Application Processors

A.3.4

High Power GPO PWM

Table 208: GPO11_LED

Register Address

Bit

Type

Label

Description

GPO11_DIM

0: PWM ratio changes instantly

1: GPO ramps between changes in PWM

ratio with 32 ms per step

0xC6 GPO11_LED

7

R/W

GPO11_PWM

6:0

R/W

GPO11 LED on-time (low level at GPIO 11,

period 21 kHz = 95 cycles of 0.5 µs)

0000000: off

0000001: 1%

0000010: 2% (1 µs bursts)

0000011: 3%

0000100: 4%

0000101: 5%

0000110: 6%

0000111: 7%

0001000: 8%

0001001: 9%

0001010: 10%

0001011: 11%

0001100: 12%

0001101: 13%

0001110: 14%

0001111: 15%

0010000: 16%

....

1011111: 100%

>1011111: 100%

Table 209: GPO14_LED

Register Address

Bit

Type

Label

Description

GPO14_DIM

0: PWM ratio changes instantly

1: GPO ramps between changes in PWM

ratio with 32 ms per step

0xC7 GPO14_LED

7

R/W

GPO14_PWM

6:0

R/W

GPO14 LED on-time (low level at GPIO 14,

period 21 kHz = 95 cycles of 0.5 µs)

0000000: off

0000001: 1%

0000010: 2% (1 µs bursts)

0000011: 3%

0000100: 4%

0000101: 5%

0000110: 6%

0000111: 7%

0001000: 8%

0001001: 9%

0001010: 10%

0001011: 11%

0001100: 12%

0001101: 13%

0001110: 14%

0001111: 15%

0010000: 16%

....

1011111: 100%

>1011111: 100%

Datasheet

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CFR0011-120-00

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DA9063

System PMIC for Mobile Application Processors

Table 210: GPO15_LED

Register Address

Bit

Type

Label

Description

GPO15_DIM

0: PWM ratio changes instantly

1: GPO ramps between changes in PWM

ratio with 32 ms per step

0xC8 GPO15_LED

7

R/W

GPO15_PWM

6:0

R/W

GPO15 LED on-time (low level at GPIO 15,

period 21 kHz = 95 cycles of 0.5 µs)

0000000: off

0000001: 1%

0000010: 2% (1 µs bursts)

0000011: 3%

0000100: 4%

0000101: 5%

0000110: 6%

0000111: 7%

0001000: 8%

0001001: 9%

0001010: 10%

0001011: 11%

0001100: 12%

0001101: 13%

0001110: 14%

0001111: 15%

0010000: 16%

....

1011111: 100%

>1011111: 100%

Datasheet

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23-Mar-2017

CFR0011-120-00

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DA9063

System PMIC for Mobile Application Processors

A.3.5

GPADC Thresholds

Table 211: ADC_CFG

Register Address

Bit

Type

Label

Description

ADCIN3_DEB

0xC9

7

R/W

0: ADCIN3: debouncing off

1: ADCIN3: debouncing on

ADC_CFG

ADCIN2_DEB

ADCIN1_DEB

ADCIN3_CUR

6

5

4

R/W

0: ADCIN2: debouncing off

1: ADCIN2: debouncing on

0: ADCIN1: debouncing off

1: ADCIN1: debouncing on

ADCIN3 current source:

0: 10 µA

1: 40 µA

ADCIN2_CUR

ADCIN1_CUR

3:2

1:0

R/W

ADCIN2 current source:

00: 1 µA

01: 2.5 µA

10: 10 µA

11: 40 µA

ADCIN1 current source:

00: 1 µA

01: 2.5 µA

10: 10 µA

11: 40 µA

Table 212: AUTO1_HIGH

Register Address

Bit

Type

Label

Description

AUTO1_HIGH

0xCA AUTO1_HIGH

7:0

R/W

00000000 – 11111111: ADCIN1 high level

threshold

Table 213: AUTO1_LOW

Register Address

Bit

Type

Label

Description

AUTO1_LOW

0xCB AUTO1_LOW

7:0

R/W

00000000 – 11111111: ADCIN1 low level

threshold

Table 214: AUTO2_HIGH

Register Address

Bit

Type

Label

Description

AUTO2_HIGH

0xCC AUTO2_HIGH

7:0

R/W

00000000 – 11111111: ADCIN2 high level

threshold

Table 215: AUTO2_LOW

Register Address

Bit

Type

Label

Description

AUTO2_LOW

0xCD AUTO2_LOW

7:0

R/W

00000000 – 11111111: ADCIN2 low level

threshold

Table 216: AUTO3_HIGH

Register Address

Bit

Type

Label

Description

AUTO3_HIGH

0xCE AUTO3_HIGH

7:0

R/W

00000000 – 11111111: ADCIN3 high level

threshold

Datasheet

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23-Mar-2017

CFR0011-120-00

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DA9063

System PMIC for Mobile Application Processors

Table 217: AUTO3_LOW

Register Address

Bit

Type

Label

Description

AUTO3_LOW

0xCF AUTO3_LOW

7:0

R/W

00000000 – 11111111: ADCIN3 low level

threshold

Table 218: Copmic_S to Copmic_E

Register Address

Bit

Type

Label

Description

0xD0

7:0

R

Reserved

Reserved for Co-PMIC

CoPMIC_S

0xDF

7:0

R

Reserved

Reserved for Co-PMIC

CoPMIC_E

Table 219: CHG_Co_S to CHG_Co_E

Register Address

Bit

Type

Label

Description

0xE0

7:0

R

Reserved

Reserved for companion charger

CHG_Co_S

0xFF CHG_Co_E

7:0

R

Reserved

Reserved for companion charger

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23-Mar-2017

CFR0011-120-00

200 of 219

DA9063

System PMIC for Mobile Application Processors

A.4 Register Page 2

Table 220: PAGE_CON

Register

Address

Bit

Type

Label

Description

0x100

PAGE_CON

7

RW

REVERT

WRITE_MODE

Reserved

See register 0x00, Table 57

6

5:3

2:0

REG_PAGE

A.4.1

OTP

Table 221: OTP_CONT

Register

Address

Bit

Type

R

Label

Description

GP_WRITE_DIS

OTP_CONF_LOCK

0: Enables write access to GP_ID registers

1: GP_ID_0to GP_ID_9 registers are ‘read only’

0x101

OTP_CONT

7

6

R

0: Registers 0x0A to 0x36 and 0x82 to 0xCF are not

locked for OTP programming (only for evaluation

samples)

1: OTP registers 0x0A to 0x36 and 0x82 to 0xCF

are locked in OTP (set for all mass production

parts, no further fusing possible)

OTP_APPS_LOCK

5

R

0: Registers 0x104 to 0x117are not locked for OTP

programming (only for evaluation samples)

1: OTP registers 0x104 to 0x117 are locked in OTP

(set for all mass production parts, no further

fusing possible)

OTP_GP_LOCK

PC_DONE

0: Registers 0x120 to 0x134 are not locked for

OTP programming

1: Registers 0x120 to 0x134 are locked in OTP (no

further fusing possible if once fused with 1)

4

3

R

R/W

Asserted from PowerCommander SW after emulated

OTP read has finished (control shared with Co-PMIC),

automatically cleared when leaving emulated OTP

read

OTP_APPS_RD

OTP_GP_RD

2

1

R/W

Reads on assertion application specific registers

(0x104 to 0x117 and OTP_APPS_LOCK) from OTP

Reads on assertion device specific registers 0x120 to

0x134 (plus GP_WRITE_DIS and OTP_GP_LOCK)

from OTP

OTP_TIM

0

R/W

OTP read timing

0: normal read

1: marginal read (for OTP fuse verification)

Datasheet

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23-Mar-2017

CFR0011-120-00

201 of 219

DA9063

System PMIC for Mobile Application Processors

Table 222: OTP_ADDR

Register Address

Bit

Type

Label

Description

0x102 OTP_ADDR

7:0

R/W

OTP_ADDR

OTP Array address (shared with Companion

ICs)

Table 223: OTP_DATA

Register Address

Bit

Type

Label

Description

0x103 OTP_DATA

7:0

R/W

OTP_DATA

OTP read/write data (shared with Companion

ICs)

OTP_DATA written to OTP_ADDR selects

the IC and accepts unlock sequence (1 + 3

bytes)

A.4.2

Customer Trim and Configuration

Table 224: T_OFFSET

Register Address

Bit

Type

Label

Description

T_OFFSET

0x104 T_OFFSET

7:0

R

10000000 – 01111111: signed two’s

complement calibration offset for junction

temperature measurement (loaded from the

OTP memory, must be programmed during

production)

Table 225: INTERFACE

Register Address

Bit

Type

Label

Description

Note 1

IF_BASE_ADDR

0x105

INTERFACE

7:4

R

4 MSB of 2-WIRE control interfaces base

address

XXXX0000

10110000 = 0xB0 write address of PM 2-

WIRE interface (page 0 and 1)

10110001 = 0xB1 read address of PM 2-

WIRE interface (page 0 and 1)

10110010 = 0xB2 write address of PM-2-

WIRE interface (page 2 and 3)

10110011 = 0xB3 read address of PM-2-

WIRE interface (page 2 and 3)

10110100 = 0xB4 write address of HS 2-

WIRE interface (page 0 and 1)

10110101 = 0xB5 read address of HS 2-

WIRE interface (page 0 and 1)

10110110 = 0xB6 write address of HS-2-

WIRE interface (page 2 and 3)

10110111 = 0xB7 read address of HS-2-

WIRE interface (page 2 and 3)

Code ‘0000’ is reserved for unprogrammed

OTP (triggers start-up with hardware default

interface address)

R/W_POL

CPHA

3

2

R

4-WIRE: Read/Write bit polarity

0: Host indicates reading access via R/W bit

= 0

1: Host indicates reading access via R/W

bit = 1

4-WIRE IF clock phase (see Table 43)

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23-Mar-2017

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DA9063

System PMIC for Mobile Application Processors

Register Address

Bit

Type

Label

CPOL

Description

Note 1

1

R

4-WIRE IF clock polarity

0: SK is low during idle

1: SK is high during idle

nCS_POL

0

R

4-WIRE chip select polarity

0: nCS is active low

1: nCS is active high

Note 1 The interface configuration can be written/modified only for unmarked samples which do not have the

control OTP_APPS_LOCK asserted/fused.

Table 226: CONFIG_A

Register Address

Bit

Type

Label

Description

IF_TYPE

0x106 CONFIG_A

7

R

0: Power manager IF is 4-WIRE

1: Power manager IF is 2-WIRE

Note 1

PM_IF_HSM

6

R/W

Enables continuous High Speed mode on PM

2-WIRE IF if asserted (no master code

required)

PM_IF_FMP

PM_IF_V

5

4

R/W

Selects fast-mode+ timings for PM 2-WIRE IF

if asserted

0: Power manager IF in 4-WIRE mode is

supplied from VDD_IO1, in 2-WIRE mode

from VDDCORE

1: Power manager IF (4-WIRE/2-WIRE)

supplied from VDD_IO2

IRQ_TYPE

3

2

R/W

nIRQ output is:

0: Active low

1: Active high (invert signal)

PM_O_TYPE

nRESET, nIRQ output are:

0: Push-pull

1: Open drain (requires external pull-up

resistor)

PM_O_V

PM_I_V

1

0

R/W

OUT_32K, OUT_32K_2, E_GPI_2,

COMP1V2, nRESET, nIRQ are supplied

from:

0: VDD_IO1

1: VDD_IO2

nONKEY, nOFF, nSHUTDOWN, SYS_EN,

PWR_EN, PWR1_EN, KEEP_ACT,

nVIB_BRAKE are supplied from:

0: VDDCORE

1: VDD_IO2

Note 1 The interface configuration can be written/modified only for unmarked samples which do not have the

control OTP_APPS_LOCK asserted/fused.

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CFR0011-120-00

203 of 219

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System PMIC for Mobile Application Processors

Table 227: CONFIG_B

Register Address

Bit

7

Type

R/W

Label

Description

Reserved

0x107 CONFIG_B

VDD_HYST_ADJ

6:4

Hysteresis adjust of VDD_FAULT comparator

(VDD_FAULT_UPPER) in 50 mV steps

000: 100 mV

001: 150 mV

…

111: 450 mV

VDD_FAULT_ADJ

3:0

R/W

Setting of VDD_FAULT_LOWER comparator

in 50 mV steps

0000: 2.50 V

0001: 2.55 V

…

0110: 2.80 V

…

1110: 3.20 V

1111: 3.25 V

Table 228: CONFIG_C

Register Address

Bit

Type

Label

Description

BPERI_CLK_INV

0x108 CONFIG_C

7

R/W

BUCKPERI clock polarity

0: Normal

1: Inverted

BIO_CLK_INV

BMEM_CLK_INV

BPRO_CLK_INV

6

5

4

R/W

BUCKIO clock polarity

0: Normal

1: Inverted

BUCKMEM clock polarity

0: Normal

1: Inverted

BUCKPRO clock polarity (should be

configured opposite to BUCKMEM clock

polarity)

0: Normal

1: Inverted

BCORE1_CLK_INV

3

R/W

BUCKCORE1 clock polarity (BUCKCORE2

always runs on opposite clock polarity)

0: Normal

1: Inverted

BUCK_DISCHG

LDO1_TRACK

2

R/W

Enable active discharge of buck rails

1:0

LDO1 follows voltage transitions of

00: none

01:VBUCK_PRO

10:VBUCK_CORE1

11:VBUCK_CORE2

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204 of 219

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System PMIC for Mobile Application Processors

Table 229: CONFIG_D

Register Address

Bit

Type

Label

Description

GP_FB3 output is:

GP_FB3_TYPE

0x109 CONFIG_D

7

R/W

0: Active low

1: Active high (invert signal)

GP_FB2_TYPE

6

R/W

GP_FB2 output is:

0: Active low (invert signal, push-pull for

PWR_OK)

1: Active high (open drain for PWR_OK)

FORCE_RESET

HS_IF_HSM

5

4

R/W

Asserts port nRESET in case of being set

Enables continuous High Speed mode on HS

2-WIRE IF (no master code required)

HS_IF_FMP

3

2

R/W

Selects fast-mode+ timings for HS 2-WIRE IF

if asserted

SYSTEM_EN_RD

During second OTP read control

SYSTEM_EN is

0: updated from OTP

1: not changed

nIRQ_MODE

GPI_V

1

0

R/W

nIRQ will be asserted from events during

POWERDOWN mode (and modes lower than

ACTICE)

0: immediately

1: after powering up to ACTIVE mode

GPIs (not configured as Power Manager

control inputs) and HS-2-WIRE IF are

supplied from:

0: VDDCORE

1: VDD_IO2

Table 230: CONFIG_E

Register Address

Bit

Type

Label

Description

PERI_SW_AUTO

0x10A CONFIG_E

7

R/W

Selects PERI_SW (during powering up):

0: configured from PERI_SW_CONF

1: enabled

CORE_SW_AUTO

BPERI_AUTO

BIO_AUTO

6

5

4

3

2

R/W

Selects CORE_SW (during powering up):

0: configured from CORE_SW_CONF

1: enabled

Selects BUCKPERI (during powering up):

0: configured from BPERI_CONF

1: enabled

Selects BUCKIO (during powering up):

0: configured from BIO_CONF

1: enabled

BMEM_AUTO

BPRO_AUTO

Selects BUCKMEM (during powering up):

0: configured from BMEM_CONF

1: enabled

Selects BUCKPRO (during powering up):

0: configured from BPRO_CONF

1: enabled

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23-Mar-2017

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DA9063

System PMIC for Mobile Application Processors

Register Address

Bit

Type

Label

Description

BCORE2_AUTO

1

R/W

Selects BUCKCORE2 (during powering up):

0: configured from BCORE2_CONF

1: enabled

BCORE1_AUTO

0

R/W

Selects BUCKCORE1 (during powering up):

0: configured from BCORE1_CONF

1: enabled

Table 231: CONFIG_F

Register Address

Bit

Type

Label

Description

LDO11_BYP

0: LDO11 is configured for regulator mode

0x10B CONFIG_F

7

R/W

1: LDO11 bypass mode enabled

LDO8_BYP

LDO7_BYP

LDO4_BYP

LDO3_BYP

LDO11_AUTO

0: LDO8 is configured for regulator mode

1: LDO8 bypass mode enabled

6

5

4

3

2

R/W

0: LDO7 is configured for regulator mode

1: LDO7 bypass mode enabled

0: LDO4 is configured for regulator mode

1: LDO4 bypass mode enabled

0: LDO3 is configured for regulator mode

1: LDO3 bypass mode enabled

Selects LDO11 (during powering up):

0: configured from LDO11_CONF

1: enabled

LDO10_AUTO

LDO9_AUTO

1

0

R/W

Selects LDO10 (during powering up):

0: configured from LDO10_CONF

1: enabled

Selects LDO9 (during powering up):

0: configured from LDO9_CONF

1: enabled

Table 232: CONFIG_G

Register Address

Bit

Type

Label

Description

LDO8_AUTO

0x10C CONFIG_G

7

R/W

Selects LDO8 (during powering up):

0: configured from LDO8_CONF

1: enabled

LDO7_AUTO

LDO6_AUTO

LDO5_AUTO

LDO4_AUTO

6

5

4

3

R/W

Selects LDO7 (during powering up):

0: configured from LDO7_CONF

1: enabled

Selects LDO6 (during powering up):

0: configured from LDO6_CONF

1: enabled

Selects LDO5 (during powering up):

0: configured from LDO5_CONF

1: enabled

Selects LDO4 (during powering up):

0: configured from LDO4_CONF

1: enabled

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23-Mar-2017

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DA9063

System PMIC for Mobile Application Processors

Register Address

Bit

Type

Label

Description

LDO3_AUTO

2

R/W

Selects LDO3 (during powering up):

0: configured from LDO3_CONF

1: enabled

LDO2_AUTO

LDO1_AUTO

1

0

R/W

Selects LDO2 (during powering up):

0: configured from LDO2_CONF

1: enabled

Selects LDO1 (during powering up):

0: configured from LDO1_CONF

1: enabled

Table 233: CONFIG_H

Register Address

Bit

Type

Label

Description

BUCK_MERGE

0x10D CONFIG_H

7

R/W

Has to be set if the outputs of BUCKMEM

and BUCKIO are merged towards a single

coil; the control from BUCKIO registers is

disabled

BCORE1_OD

BCORE2_OD

BPRO_OD

6

5

4

3

R/W

If set, BUCKCORE1 changes to full-current

mode (double pass device and current limit)

If set, BUCKCORE2 changes to full-current

mode (double pass device and current limit)

If set, BUCKPRO changes to full-current

mode (double pass device and current limit)

BCORE_MERGE

Has to be set if the outputs of BUCKCORE1

and BUCKCORE2 are merged towards a

dual phase buck; the control from

BUCKCORE2 registers is disabled

MERGE_SENSE

2

R/W

In case BUCKCORE is merged and

configured for remote sensing the output

capacitor voltage rail is routed to port:

0: GP_FB_2 (setting disables normal

GP_FB_2 functionality)

1: CORE_SWS (setting disables CORE rail

switch pull-down functionality)

Note: In case MERGE_SENSE is asserted all

Bxxx_FB control settings 0bx1x are invalid

LDO8_MODE

PWM_CLK

0: LDO mode (external capacitor required)

1: Vibration motor driver (no external

capacitor)

1

0

R/W

0: 2.0 MHz (31.25 kHz repetition frequency)

1: 1.0 MHz (15.6 kHz repetition frequency)

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Table 234: CONFIG_I

Register Address

Bit

Type

Label

Description

LDO_SD

0x10E CONFIG_I

7

R/W

If asserted LDO3, 4, 7, 8 and 11 will shut

down after current limit was hit for more than

200 ms

INT_SD_MODE

6

5

R/W

Shut down sequence from internal fault

condition is:

0: Normal

1: Fast (skipping seq and dummy slot timers)

HOST_SD_MODE

Shut down sequence from SHUTDOWN

(register bit or port nSHUTDOWN) is:

0: Normal

1: Fast (skipping seq and dummy slot

timers)

KEY_SD_MODE

4

R/W

User triggered (nONKEY, GPIO14/15)

shutdown sequence is:

0: Normal

1: PMU POR: triggers an instant disable of all

regulators incl. LDOCORE (RTC and

FAULTLOG registers remain unchanged).

After leaving POR automatically the

RESET_DURATION timer must expire before

starting a power-up sequence.

GPI14_15_SD

nONKEY_SD

0: Disables shutdown via parallel

assertion of GPI14 and GPI15

1: Enables shutdown via GPI14 & GPI15

3

2

R/W

nONKEY is configured

0: without shutdown via long press of

nONKEY

1: with shutdown via long press of nONKEY

nONKEY_PIN

1:0

R/W

nONKEY is configured to

00: Port mode

01: Key mode with key lock during SW

triggered POWERDOWN mode

10: Key mode with key locked autonomous

powering down (multi-functional key)

11: Key mode with autonomous powering

down to partial or key locked full

POWERDOWN mode (dedicated power key)

Details: see Section 6.1.1

Table 235: CONFIG_J

Register Address

Bit

Type

Label

Description

IF_RESET

0x10F CONFIG_J

7

R/W

Enables automatic reset of all control

interfaces when port nSHUTDOWN is

asserted

IF_TO

6

R/W

Enables automatic reset of 2-WIRE-IF in

case of clock ceases to toggle for >19 ms

RESET_DURATION

5:4

Power controller stays in RESET mode for

minimum duration of

00: 20 ms

01: 100 ms

10: 500 ms

11: 1000 ms

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Register Address

Bit

Type

Label

Description

SHUT_DELAY

3:2

R/W

Long press time threshold for shutdown

feature from nONKEY and GPIO14/15:

00: KEY_DELAY + 0 s

01: KEY_DELAY + 4 s

10: KEY_DELAY + 5 s

11: KEY_DELAY + 6 s

KEY_DELAY

1:0

R/W

Long press threshold for nONKEY lock:

00: nONKEY_LOCK after 1 s

01: nONKEY_LOCK after 1.5 s

10: nONKEY_LOCK after 2 s

11: nONKEY_LOCK after 7 s

Note 1 This setting may trigger glidges on regulator outputs and disable the automatic RESET/POR of slave

PMUs).

Table 236: CONFIG_K

Register Address

Bit

Type

Label

Description

GPIO7_PUPD

0: GPI: pull-down resistor disabled

GPO (open drain): pull-up resistor

disabled (external pull-up resistor)

0x110 CONFIG_K

7

R/W

1: GPI: pull-down resistor enabled

GPO (open drain): pull-up resistor enabled

(supply rail selected via GPIOx_TYPE)

GPIO6_PUPD

GPIO5_PUPD

GPIO4_PUPD

GPIO3_PUPD

GPIO2_PUPD

0: GPI: pull-down resistor disabled

GPO (open drain): pull-up resistor

disabled (external pull-up resistor)

6

5

4

3

2

R/W

1: GPI: pull-down resistor enabled

GPO (open drain): pull-up resistor enabled

(supply rail selected via GPIOx_TYPE)

0: GPI: pull-down resistor disabled

GPO (open drain): pull-up resistor

disabled (external pull-up resistor)

1: GPI: pull-down resistor enabled

GPO (open drain): pull-up resistor enabled

(supply rail selected via GPIOx_TYPE)

0: GPI: pull-down resistor disabled

GPO (open drain): pull-up resistor

disabled (external pull-up resistor)

1: GPI: pull-down resistor enabled

GPO (open drain): pull-up resistor enabled

(supply rail selected via GPIOx_TYPE)

0: GPI: pull-down resistor disabled

GPO (open drain): pull-up resistor

disabled (external pull-up resistor)

1: GPI: pull-down resistor enabled

GPO (open drain): pull-up resistor enabled

(supply rail selected via GPIOx_TYPE)

0: GPI: pull-down resistor disabled

GPO (open drain): pull-up resistor

disabled (external pull-up resistor)

1: GPI: pull-down resistor enabled

GPO (open drain): pull-up resistor enabled

(supply rail selected via GPIOx_TYPE)

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Register Address

Bit

Type

Label

Description

GPIO1_PUPD

0: GPI: pull-down resistor disabled

GPO (open drain): pull-up resistor

disabled (external pull-up resistor)

1

R/W

1: GPI: pull-down resistor enabled

GPO (open drain): pull-up resistor enabled

(supply rail selected via GPIOx_TYPE)

GPIO0_PUPD

0: GPI: pull-down resistor disabled

GPO (open drain): pull-up resistor

disabled (external pull-up resistor)

0

R/W

1: GPI: pull-down resistor enabled

GPO (open drain): pull-up resistor enabled

(supply rail selected via GPIOx_TYPE)

Table 237: CONFIG_L

Register Address

Bit

Type

Label

Description

GPIO15_PUPD

0: GPI: pull-down resistor disabled

GPO (open drain): pull-up resistor

disabled (external pull-up resistor)

0x111 CONFIG_L

7

R/W

1: GPI: pull-down resistor enabled

GPO (open drain): pull-up resistor enabled

(supply rail selected via GPIOx_TYPE)

GPIO14_PUPD

GPIO13_PUPD

GPIO12_PUPD

GPIO11_PUPD

GPIO10_PUPD

0: GPI: pull-down resistor disabled

GPO (open drain): pull-up resistor

disabled (external pull-up resistor)

6

5

4

3

2

R/W

1: GPI: pull-down resistor enabled

GPO (open drain): pull-up resistor enabled

(supply rail selected via GPIOx_TYPE)

0: GPI: pull-down resistor disabled

GPO (open drain): pull-up resistor

disabled (external pull-up resistor)

1: GPI: pull-down resistor enabled

GPO (open drain): pull-up resistor enabled

(supply rail selected via GPIOx_TYPE)

0: GPI: pull-down resistor disabled

GPO (open drain): pull-up resistor

disabled (external pull-up resistor)

1: GPI: pull-down resistor enabled

GPO (open drain): pull-up resistor enabled

(supply rail selected via GPIOx_TYPE)

0: GPI: pull-down resistor disabled

GPO (open drain): pull-up resistor

disabled (external pull-up resistor)

1: GPI: pull-down resistor enabled

GPO (open drain): pull-up resistor enabled

(supply rail selected via GPIOx_TYPE)

0: GPI: pull-down resistor disabled

GPO (open drain): pull-up resistor

disabled (external pull-up resistor)

1: GPI: pull-down resistor enabled

GPO (open drain): pull-up resistor enabled

(supply rail selected via GPIOx_TYPE)

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Register Address

Bit

Type

Label

Description

GPIO9_PUPD

0: GPI: pull-down resistor disabled

GPO (open drain): pull-up resistor

disabled (external pull-up resistor)

1

R/W

1: GPI: pull-down resistor enabled

GPO (open drain): pull-up resistor enabled

(supply rail selected via GPIOx_TYPE)

GPIO8_PUPD

0: GPI: pull-down resistor disabled

GPO (open drain): pull-up resistor

disabled (external pull-up resistor)

0

R/W

1: GPI: pull-down resistor enabled

GPO (open drain): pull-up resistor enabled

(supply rail selected via GPIOx_TYPE)

Table 238: CONFIG_M

Register Address

Bit

Type

Label

Description

OSC_FRQ

0x112 CONFIG_M

7:4

R/W

Offset for internal HF oscillator frequency

0x8: -10.67%

…

0xF: -1.33%

0x0: 0.00%

0x1: 1.33%

…

0x7: 9.33%

Reserved

3:0

R/W

Table 239: Reserved

Register Address

Bit

7:0

Type

Label

Description

Reserved

0x113

R/W

Table 240: MON_REG_1

Register Address

Bit

Type

Label

UVOV_DELAY

0x114

MON_REG_1

7:6

R/W

Range comparison is enabled after regulator

enable:

00: immediately

01: with one measurement delay

10: with two measurements delay

11: with four measurements delay

MON_MODE

5:4

R/W

Regulator monitor executes

00: Under-voltage/Over-voltage lockout

with an E_REG_UVOV event (nIRQ

assertion) and regulator shutdown from

an output voltage being out of the

selected range

01: Normal auto measurement with an

E_REG_UVOV event (nIRQ assertion) from

any finished auto measurement on A8, A9

and A10

10: Burst auto measurement with an

E_REG_UVOV event (nIRQ assertion)

generated after the time slot of A10 has been

processed

11: reserved

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Register Address

Bit

Type

Label

Description

MON_DEB

3

R/W

0: Regulator monitor (A8, 9, 10): debouncing

off

1: Regulator monitor (A8, 9, 10):

debouncing on

MON_RES

2

R/W

Control requires M_REG_UVOV = 1:

1: Enables assertion of nRESET from out-of-

range detection

Note: It is not recommended to assert this

control inside OTP

MON_THRES

1:0

Regulator Monitor Threshold

00: Approx = 25 %

01: Approx = 12.5 %

10: Approx = 6.25 %

11: Approx = 3.125 %

Table 241: MON_REG_2

Register Address

Bit

7

Type

R/W

Label

Description

LDO8_MON_EN

LDO7_MON_EN

LDO6_MON_EN

LDO5_MON_EN

LDO4_MON_EN

LDO3_MON_EN

LDO2_MON_EN

LDO1_MON_EN

0x115

MON_REG_2

Enable LDO8 regulator monitoring

Enable LDO7 regulator monitoring

Enable LDO6 regulator monitoring

Enable LDO5 regulator monitoring

Enable LDO4 regulator monitoring

Enable LDO3 regulator monitoring

Enable LDO2 regulator monitoring

Enable LDO1 regulator monitoring

6

5

4

3

2

1

0

Table 242: MON_REG_3

Register Address

Bit

7:3

2

Type

R/W

Label

Description

Reserved

0x116

MON_REG_3

LDO11_MON_EN

LDO10_MON_EN

LDO9_MON_EN

Enable LDO11 regulator monitoring

Enable LDO10 regulator monitoring

Enable LDO9 regulator monitoring

1

0

Table 243: MON_REG_4

Register Address

Bit

7

Type

R/W

Label

Description

BPERI_MON_EN

BMEM_MON_EN

BIO_MON_EN

0x117

MON_REG_4

Enable BUCKPERI regulator monitoring

Enable BUCKMEM regulator monitoring

Enable BUCKIO regulator monitoring

Enable BUCKPRO regulator monitoring

Enable BUCKCORE2 regulator monitoring

Enable BUCKCORE1 regulator monitoring

6

5

BPRO_MON_EN

BCORE2_MON_EN

BCORE1_MON_EN

Reserved

4

3

2

1:0

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Table 244: MON_REG_5

Register Address

Bit

7

Type

R

Label

Description

0x11E

Reserved

MON_REG_5

6:4

R

MON_A9_IDX

Latest measurement at channel A9 was:

000: none

001: BUCKIO

010: BUCKMEM

011: BUCKPERI

100: LDO1

101: LDO2

101: LDO5

> 110: reserved

3

R

Reserved

2:0

MON_A8_IDX

Latest measurement at channel A8 was:

000: none

001: BUCKCORE1

010: BUCKCORE2

011: BUCKPRO

100: LDO3

101: LDO4

110: LDO11

> 110: reserved

Table 245: MON_REG_6

Register Address

Bit

7:3

2:0

Type

R

Label

Description

0x11F

MON_REG_6

Reserved

R

MON_A10_IDX

Latest measurement at channel A10 was:

000: none

001: LDO6

010: LDO7

011: LDO8

100: LDO9

101: LDO10

> 101: reserved

Table 246: TRIM_CLDR

Register Address

Bit

Type

Label

Description

TRIM_32K

0x120

TRIM_CLDR

7:0

R/W

Bits for correction of the 32K oscillator

frequency for internal calendar:

10000000: -244.1 ppm

…

11111111: -1.9 ppm

00000000: off

00000001: 1.9 ppm (1/(32768*16))

…

01111111: 242.2 ppm

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Table 247: GP_ID_0

Register Address

Bit

Type

Label

GP_0

Description

0x121

7:0

R/W

Data from fuse array (OTP)

GP_ID_0

Note 1

Note 1 Write access can be disabled by OTP if required.

Table 248: GP_ID_1

Register Address

Bit

Type

Label

GP_1

Description

0x122

7:0

R/W

Data from fuse array (OTP)

GP_ID_1

Note 1

Note 1 Write access can be disabled by OTP if required.

Table 249: GP_ID_2

Register Address

Bit

Type

Label

GP_2

Description

0x123

7:0

R/W

Data from fuse array (OTP)

GP_ID_2

Note 1

Note 1 Write access can be disabled by OTP if required.

Table 250: GP_ID_3

Register Address

Bit

Type

Label

GP_3

Description

0x124

7:0

R/W

Data from fuse array (OTP)

GP_ID_3

Note 1

Note 1 Write access can be disabled by OTP if required.

Table 251: GP_ID_4

Register Address

Bit

Type

Label

GP_4

Description

0x125

7:0

R/W

Data from fuse array (OTP)

GP_ID_4

Note 1

Note 1 Write access can be disabled by OTP if required.

Table 252: GP_ID_5

Register Address

Bit

Type

Label

GP_5

Description

0x126

7:0

R/W

Data from fuse array (OTP)

GP_ID_5

Note 1

Note 1 Write access can be disabled by OTP if required.

Table 253: GP_ID_6

Register Address

Bit

Type

Label

GP_6

Description

0x127

7:0

R/W

Data from fuse array (OTP)

GP_ID_6

Note 1

Note 1 Write access can be disabled by OTP if required.

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Table 254: GP_ID_7

Register Address

Bit

Type

Label

GP_7

Description

0x128

7:0

R/W

Data from fuse array (OTP)

GP_ID_7

Note 1

Note 1 Write access can be disabled by OTP if required.

Table 255: GP_ID_8

Register Address

Bit

Type

Label

GP_8

Description

0x129

7:0

R/W

Data from fuse array (OTP)

GP_ID_8

Note 1

Note 1 Write access can be disabled by OTP if required.

Table 256: GP_ID_9

Register Address

Bit

Type

Label

GP_9

Description

0x12A

7:0

R/W

Data from fuse array (OTP)

GP_ID_9

Note 1

Note 1 Write access can be disabled by OTP if required.

Table 257: GP_ID_10

Register Address

Bit

Type

Label

Description

GP_10

0x12B GP_ID_10

7:0

R/W

Data from fuse array (OTP), no OTP reload

after powering up from NO-POWER mode

Table 258: GP_ID_11

Register Address

Bit

7:0

Type

Label

Description

GP_11

0x12C GP_ID_11

R/W

Data from fuse array (OTP)

Table 259: GP_ID_12

Register Address

Bit

7:0

Type

Label

Description

GP_12

0x12D GP_ID_12

R/W

Data from fuse array (OTP)

Table 260: GP_ID_13

Register Address

Bit

7:0

Type

Label

Description

GP_13

0x12E GP_ID_13

R/W

Data from fuse array (OTP)

Table 261: GP_ID_14

Register Address

Bit

7:0

Type

Label

Description

GP_14

0x12F GP_ID_14

R/W

Data from fuse array (OTP)

Table 262: GP_ID_15

Register Address

Bit

7:0

Type

Label

Description

GP_15

0x130 GP_ID_15

R/W

Data from fuse array (OTP)

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Table 263: GP_ID_16

Register Address

Bit

Type

Label

Description

GP_16

0x131 GP_ID_16

7:0

R/W

Data from fuse array (OTP)

Table 264: GP_ID_17

Register Address

Bit

7:0

Type

Label

Description

GP_17

0x132 GP_ID_17

R/W

Data from fuse array (OTP)

Table 265: GP_ID_18

Register Address

Bit

7:0

Type

Label

Description

GP_18

0x133 GP_ID_18

R/W

Data from fuse array (OTP)

Table 266: GP_ID_19

Register Address

Bit

7:0

Type

Label

Description

GP_19

0x134 GP_ID_19

R/W

Data from fuse array (OTP)

Table 267: Copmic_S to Copmic_E

Register Address

0x140 CoPMIC_S

0x14F CoPMIC_E

Bit

7:0

Type

R

Label

Description

Reserved for Co-PMIC

Reserved

R

Table 268: CHG_Co_S to CHG_Co_E

Register Address

0x150 CHG_Co_S

0x17F CHG_Co_E

Bit

7:0

Type

R

Label

Description

Reserved for companion charger

Reserved

R

A.5 Register Page 3

Table 269: PAGE_CON

Register Address

Bit

7

Type

RW

Label

REVERT

Description

0x180 PAGE_CON

See register 0x00, Table 57

6

WRITE_MODE

Reserved

5:3

2:0

REG_PAGE

Table 270: DEVICE_ID

Register Address

Bit

Type

Label

Description

0x181 DEVICE_ID

7:0

R

DEVICE_ID

Read back of chip ID

Table 271: VARIANT_ID

Register Address

Bit

7:4

3:0

Type

R

Label

MRC

VRC

Description

0x182

VARIANT_ID

Read back of mask revision code (MRC)

Read back of package variant code (VRC)

R

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Table 272: CUSTOMER_ID

Register Address

Bit

Type

Label

Description

CUSTOMER_ID

0x183

7:0

R

ID for customer and target application

CUSTOMER_ID

platform, written during production of variant

Table 273: CONFIG_ID

Register Address

Bit

Type

Label

Description

CONFIG_REV

0x184 CONFIG_ID

7:0

R

ID for revision of OTP settings, written during

production of variant

00000000 – OTP unprogrammed

(RESERVED)

> 00000000 – OTP configuration revision xxx

Table 274: PMIC_STATUS

Register Address

Bit

7

Type

R

Label

Description

PC_DONE

Reserved

STATUS

0x1A8

PMIC_STATUS

Power Commander download complete

6:5

4:0

R/W

R

Decimal Decode:

03=Reset (Shutdown)

28= System

25=Power

23=Power Down

20=Power1

17=Active

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Status Definitions

Revision

Datasheet Status

Product Status

Definition

1.<n>

Target

Development

This datasheet contains the design specifications for product

development. Specifications may be changed in any manner without

notice.

2.<n>

3.<n>

Preliminary

Final

Qualification

Production

This datasheet contains the specifications and preliminary

characterization data for products in pre-production. Specifications

may be changed at any time without notice in order to improve the

design.

This datasheet contains the final specifications for products in

volume production. The specifications may be changed at any time

in order to improve the design, manufacturing and supply. Major

specification changes are communicated via Customer Product

Notifications. Datasheet changes are communicated via

www.dialog-semiconductor.com.

4.<n>

Obsolete

Archived

This datasheet contains the specifications for discontinued products.

The information is provided for reference only.

Disclaimer

Information in this document is believed to be accurate and reliable. However, Dialog Semiconductor does not give any

representations or warranties, expressed or implied, as to the accuracy or completeness of such information. Dialog

Semiconductor furthermore takes no responsibility whatsoever for the content in this document if provided by any information

source outside of Dialog Semiconductor.

Dialog Semiconductor reserves the right to change without notice the information published in this document, including without

limitation the specification and the design of the related semiconductor products, software and applications.

Applications, software, and semiconductor products described in this document are for illustrative purposes only. Dialog

Semiconductor makes no representation or warranty that such applications, software and semiconductor products will be

suitable for the specified use without further testing or modification. Unless otherwise agreed in writing, such testing or

modification is the sole responsibility of the customer and Dialog Semiconductor excludes all liability in this respect.

This Dialog Semiconductor product has been qualified for use in automotive applications. Unless otherwise agreed in writing,

the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems

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System PMIC for Mobile Application Processors

The Netherlands

Taiwan

Korea

Dialog Semiconductor B.V.

Phone: +31 73 640 8822

Dialog Semiconductor Taiwan

Phone: +886 281 786 222

Dialog Semiconductor Korea

Phone: +82 2 3469 8200

Email:

Web site:

enquiry@diasemi.com

www.dialog-semiconductor.com

Datasheet

DA9063_2v1

23-Mar-2017

CFR0011-120-00

219 of 219


型号：	DA9063-xxHO2-A
厂家：	Dialog Semiconductor
描述：	System PMIC for Mobile Application Processors 集成电源管理电路
文件：	总219页 (文件大小：2882K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DA9063-xxHO2-A [DIALOG]

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