DA9121-XXV76 [DIALOG]
High-Performance, 10 A, Dual-Phase DC-DC Converter;
| 型号： | DA9121-XXV76 |
| 厂家： | 
Dialog Semiconductor |
| 描述： | High-Performance, 10 A, Dual-Phase DC-DC Converter |
| 文件： | 总50页 (文件大小：1421K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
General Description
DA9121 is a power management unit (PMU) suitable for supplying CPUs, GPUs, DDR memory rails
in single in-line pin package (SIPP) modules, smartphones, tablets, and other handheld applications.
DA9121 operates as a single-channel dual-phase buck converter, each phase requiring a small
external 0.10 µH inductor. It is capable of delivering up to 10 A output current at a 0.3 V to 1.9 V
output voltage range. The 2.5 V to 5.5 V input voltage range is suitable for a wide variety of low-
voltage systems, including, but not limited to, all Li-Ion battery supplied applications.
With remote sensing, the DA9121 guarantees the highest accuracy and supports multiple PCB
routing scenarios without loss of performance.
The pass devices are fully integrated, so no external FETs or Schottky diodes are needed.
A programmable soft start-up can be enabled, which limits the inrush current from the input node and
secures a slope-controlled rail activation.
The dynamic voltage control (DVC) supports adaptive adjustment of the supply voltage dependent on
the processor load, via either a direct register write using the communication interface (I2C-
compatible) or with a programmable input pin.
A configurable GPI allows multiple I2C address selection for multiple instances of DA9121 in the
same application.
DA9121 has integrated over-temperature and over-current protection for increased system reliability,
without the need for external sensing components.
Key Features
■
■
■
■
■
■
■
■
2.5 V to 5.5 V input voltage
0.3 V to 1.9 V output voltage
4 MHz nominal switching frequency
±1 % accuracy (static)
■
■
■
■
Voltage, current, and temperature
supervision
-40 °C to +85 ºC ambient temperature
range
Package:
±5 % accuracy (dynamic)
I2C-compatible interface (FM+)
Programmable GPIOs
24WLCSP 2.5 mm x 1.7 mm (0.4 mm pitch)
24WLP 2.7 mm x 1.9 mm (0.4 mm pitch)
Programmable soft-start
Applications
■
■
■
■
SIPP modules (SoC, DRAM)
Smartphones
■
■
■
Ultrabooks™
Wi-Fi Modules
Game Consoles
Tablet PCs
Infotainment
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
1 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
System Diagrams
DDR
1.1 V
1.8 V
CPU
GPU
IC_EN
PVDD
IC_EN
CONF
PVDD
IC_EN
CONF
PVDD
DA9122AVDD
DA9121AVDD
DA9121AVDD
SoC
VR_
HOT
AGND
AGND
AGND
GPIO
VR_CPU_HOT
VR_GPU_HOT
PG (DVS ready)
CPU_LP
GPU_EN
GPU_LP
IO_LP
DDR_LP
VR_DDR_HOT
Figure 1: Typical Application Diagram (Port Control)
DDR
1.1 V
1.8 V
CPU
GPU
IC_EN
CONF
PVDD
IC_EN
CONF
PVDD
IC_EN
CONF
PVDD
DA9122AVDD
DA9121AVDD
DA9121AVDD
SoC
AGND
AGND
AGND
I2C
GPIO
I2C CLK
I2C DATA
Faults
PG (ENx/DVS ready)
GPU_EN
Figure 2: Typical Application Diagram (I2C Control)
VDD = 2.5 V to 5.5 V
1 µF
2x 10 µF
PVDD1
FB1P
100 nH
100 nH
VOUT1 = 0.3 V to 1.9 V
Buck1
4 x 10 µF
PGND
FB1N
Digital Core
OTP Memory
Register Map
IC_EN
CONF/GPIO0
GPIO1
GPIO2
SCL/GPIO3
SDA/GPIO4
DA9121
Bias Supervision
Oscillator
NC
NC
I2C
GPIO
AGND
Figure 3: Simplified Schematic Diagram
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
2 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
Contents
General Description ............................................................................................................................ 1
Key Features ........................................................................................................................................ 1
Applications ......................................................................................................................................... 1
System Diagrams ................................................................................................................................ 2
1
2
3
Terms and Definitions................................................................................................................... 5
Pinout ............................................................................................................................................. 6
Characteristics .............................................................................................................................. 8
3.1 Absolute Maximum Ratings .................................................................................................. 8
3.2 Recommended Operating Conditions................................................................................... 8
3.3 Thermal Characteristics ........................................................................................................ 9
3.3.1
3.3.2
Thermal Ratings .................................................................................................... 9
Power Dissipation.................................................................................................. 9
3.4 ESD Characteristics............................................................................................................ 10
3.5 Buck Characteristics ........................................................................................................... 10
3.6 Performance and Supervision Characteristics.................................................................... 12
3.7 Digital IO Characteristics..................................................................................................... 12
3.8 Timing Characteristics......................................................................................................... 14
3.9 Typical Performance ........................................................................................................... 15
4
Functional Description ............................................................................................................... 19
4.1 DC-DC Buck Converter....................................................................................................... 19
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
Switching Frequency ........................................................................................... 19
Operation Modes and Phase Selection............................................................... 19
Output Voltage Selection..................................................................................... 20
Soft Start-Up and Shutdown................................................................................ 20
Current Limit ........................................................................................................ 20
Thermal Protection .............................................................................................. 21
4.2 Internal Circuits ................................................................................................................... 22
4.2.1
4.2.2
4.2.3
IC_EN/Chip Enable/Disable................................................................................. 22
nIRQ/Interrupt...................................................................................................... 22
GPIO.................................................................................................................... 25
4.3 Operating Modes................................................................................................................. 27
4.3.1
4.3.2
ON........................................................................................................................ 27
OFF...................................................................................................................... 27
4.4 I2C Communication ............................................................................................................. 27
4.4.1
I2C Protocol.......................................................................................................... 27
5
6
Register Definitions .................................................................................................................... 30
5.1 Register Map....................................................................................................................... 30
5.1.1
5.1.2
5.1.3
System................................................................................................................. 32
Buck1................................................................................................................... 40
Serialization ......................................................................................................... 44
Package Information................................................................................................................... 45
6.1 Package Outlines................................................................................................................ 45
6.2 Moisture Sensitivity Level.................................................................................................... 47
6.3 Package Handling............................................................................................................... 47
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
3 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
6.4 Soldering Information.......................................................................................................... 47
7
8
Ordering Information .................................................................................................................. 48
Application Information.............................................................................................................. 48
8.1 Capacitor Selection............................................................................................................. 48
8.2 Inductor Selection ............................................................................................................... 49
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
4 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
1
Terms and Definitions
ATE
CPU
DDR
DVC
FET
Automated test equipment
Central processing unit
Dual data rate
Dynamic voltage control
Field effect transistor
Fast mode plus
FM+
GBD
GBQ
Guaranteed by design
Guaranteed by qualification
GBSPC
GPI
Guaranteed by statistical process characterization
General purpose input
General purpose input/output
Graphics processing unit
Integrated circuit
GPIO
GPU
IC
HW
Hardware
Li-Ion
OTP
PCB
PRS
SCL
SDA
SIPP
SW
Lithium-ion
One time programmable
Printed circuit board
Product requirements specification
Serial clock
Serial data
Single in-line pin package
Software
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
5 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
2
Pinout
Figure 4: DA9121 Pinout Diagram (Top View)
Table 1: Pin Description
Type
Drive
Reset
State
Pin No. Pin Name
Description
(Table 2) (mA)
Supply voltage for buck power stage, decouple
with 10 µF and connect to same source as
AVDD
A1, B1
A2, B2
PVDD1
LX1
PWR
AIO
5000
5000
Switch node of buck, connect a 100 nH inductor
between LX1 and output capacitor
A3, B3
A4, B4
PGND1
PGND2
GND
GND
5000
5000
Buck power stage VSS rail
Buck power stage VSS rail
Switch node of buck, connect a 100 nH inductor
between LX1 and output capacitor
A5, B5
A6, B6
LX2
AIO
5000
5000
Supply voltage for buck power stage, decouple
with 10 µF and connect to same source as
AVDD
PVDD2
PWR
C1
C2
SCL/GPIO3
SDA/GPIO4
DIO
DIO
15
15
I2C clock or general purpose I/O
I2C data or general purpose I/O
Powers up SW control interface and auxiliary
circuitry (including bandgap, oscillator, and
references).
C3
IC_EN
AI
10
C4
C5
C6
CONF/GPIO0 AI/DIO
10
10
10
Chip configuration or general purpose I/O
General purpose I/O
GPIO1
GPIO2
DIO
DIO
General purpose I/O
Buck negative node of differential voltage
feedback, connect to VSS at point of load
D1
D2
D3
FB1N
FB1P
AVDD
AI
10
10
10
Buck positive node of differential voltage
feedback, connect to VOUT1 at point of load
AI
Supply rail for analog control circuitry, decouple
with 1 µF and connect to same source as PVDD
PWR
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
6 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
Type
(Table 2) (mA)
Drive
Reset
State
Pin No. Pin Name
Description
D4
D5
D6
AGND
NC
GND
AI
10
Analog control and auxiliary circuitry VSS
Not used
Not used
NC
AI
Table 2: Pin Type Definition
Pin Type
DI
Description
Digital input
Digital output
Digital input/output
Power
Pin Type
AI
Description
Analog input
Analog output
Analog input/output
Ground
DO
AO
DIO
AIO
GND
PWR
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
7 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
3
Characteristics
3.1 Absolute Maximum Ratings
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to
the device. These are stress ratings only, so functional operation of the device at these or any other
conditions beyond those indicated in the operational sections of the specification are not implied.
Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Table 3: Absolute Maximum Ratings
Parameter Description
Conditions
Min
-65
Max
150
150
6.0
Unit
°C
°C
V
TSTG
TJ
Storage temperature
Junction temperature
System supply voltage
Voltage on pins
-40
VSYS
VPIN
-0.3
-0.3
6.0
V
3.2 Recommended Operating Conditions
Table 4: Recommended Operating Conditions
Parameter Description
Conditions (Note 1)
Min
Typ
Max
Unit
VSYS
VPIN
System supply voltage
2.5
5.5
V
V
VSYS
0.3
+
Voltage on pins
-0.3
TJ
Junction temperature
Ambient temperature
-40
-40
125
85
°C
°C
TA
Note 1 Within the specified limits, a lifetime of 10 years is guaranteed. If operating outside of these
recommended conditions, please consult with Dialog Semiconductor.
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
8 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
3.3 Thermal Characteristics
3.3.1
Thermal Ratings
Table 5: Package Ratings
Parameter
Description
Conditions
Min
Typ
Max
Unit
WLCSP Package thermal
resistance
Note 1
32.7
°C/W
JA_WLCSP
WLP Package thermal
resistance
Note 1
34.8
°C/W
JA_WLP
Note 1 Obtained from package thermal simulation, 2S2P4L board (JEDEC), influenced by PCB technology
and layout.
3.3.2
Power Dissipation
Table 6: Power Dissipation
Parameter Description
Conditions
Min
Typ
Max
Unit
Derating factor above TA
70°C : 30.6 mW/°C (1/θJA)
=
PD
Power dissipation
2140
mW
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
PD = (TJ - TA) / θJA
θJA = 32.7 °C/W
Still air (0 m/s)
▲TJ(WARN) = 125 °C
◆TJ(CRIT) = 140 °C
20
30
40
50
60
70
80
90 100 110 120 130 140
TA (°C)
Figure 5: 24WLCSP Power Derating Curve
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
9 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
Figure 6: 24WLP Power Derating Curve
3.4 ESD Characteristics
Table 7: ESD Characteristics
Parameter Description
ESD protection, human
Conditions
Min
Typ
Max
Unit
VESD_HBM
2
kV
body model (HBM)
3.5 Buck Characteristics
Unless otherwise noted, the following is valid for TJ = -40 °C to +125 °C, VSYS = 2.5 V to 5.5 V.
Table 8: Buck Electrical Characteristics
Parameter Description
Conditions
Min
Typ
Max
Unit
External Electrical Conditions
VIN
Input voltage
VIN = VSYS
2.5
5.5
V
Output capacitance, per
phase, including voltage and
temperature coefficient
COUT
-40 % 2 x 10 +30 %
μF
Output capacitor series
resistance, per phase
ESRCOUT
f > 100 kHz
2
mΩ
Inductor value, per phase,
including current and
temperature dependence
L
-50 %
0.1
30
+20 %
50
μH
DCRL
Inductor DC resistance
mΩ
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
10 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
Parameter Description
Electrical Performance
Output voltage,
Conditions
Min
Typ
Max
Unit
IOUT = 0 mA to IMAX
VIN = 2.5 V to 5.5 V
VOUT
programmable in 10 mV
0.3
0.3
1.57
1.9
V
V
steps
Output voltage,
programmable in 10 mV
steps
IOUT = 0 mA to IMAX
VIN = 3.0 V to 5.5 V
VOUT_LIM
Current limit, programmable
per phase
ILIM
CHx_ILIM = 1010
-20 %
-1
8
+20 %
1
A
Note 1
Output voltage accuracy,
including static line and load
regulation
VOUT_ACC
VOUT ≥ 1 V
%
Output voltage accuracy,
including static line and load
regulation
VOUT_ACC
VOUT < 1 V
-10
-80
10
mV
mV
Power good voltage
threshold for rising
VTHR_PG_RISE
VOUT = VBUCK
-50
-20
Power good voltage
threshold for falling
VTHR_PG_DWN
VTHR_HV
VOUT = VBUCK
VOUT = VBUCK
-160
100
-130
150
-100
200
mV
mV
High VOUT voltage threshold
VIN = 3 V to 3.6 V
IOUT = 0.5 * IMAX
dt = 10 μs
VOUT_TR_LINE Line transient response
15
mV
Switching frequency, post-
trim
fSW
4
MHz
Minimum turn-on pulse
tON_MIN
20
ns
0 % duty is also supported
tBUCK_EN
Turn-on time
CHx_EN = high
20
μs
Output pull-down resistance
for each phase at the LX
node, see
VIN = 3.7 V
RPD
100
150
200
Ω
VOUT = 0.5 V
BUCK<x>_PD_DIS
On resistance of switching
PMOS, per phase
RON_PMOS
VIN = 3.7 V
VIN = 3.7 V
36
17
mΩ
mΩ
On resistance of switching
NMOS, per phase
RON_NMOS
AUTO Mode
VOUT = 1 V
VOUT_TR_LD_2 Load transient response,
IOUT = 0 A to 10 A
dl/dt = 10 A/μs
±5
%
phase shedding enabled
PH
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
11 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
Parameter Description
PFM Mode
Conditions
Min
Typ
Max
Unit
VIN = 3.7 V
No load
IQ_PFM_2PH
Quiescent current in PFM
164
μA
No switching
Note 1 tON > 40 ns
3.6 Performance and Supervision Characteristics
Table 9: Electrical Characteristics
Parameter Description
Electrical Performance
Conditions
Min
Typ
Max
Unit
VTHR_POR
Power-on-reset threshold
Threshold for AVDD falling
2.1
2.25
V
VTHR_POR_HY
S
Power-on-reset hysteresis
200
mV
Thermal warning
temperature threshold
TWARN
115
130
125
140
135
150
°C
°C
Thermal shutdown
temperature threshold
TCRIT
OFF state
TA = 27 °C
IC_EN = 0
IIN_OFF
Supply current
Supply current
0.1
10
1
μA
μA
ON state
TA = 27 °C
IC_EN = 1
Buck off
IIN_ON
5
20
3.7 Digital IO Characteristics
Table 10: Digital I/O Electrical Characteristics
Parameter Description
Electrical Performance
Conditions
Min
Typ
Max
Unit
VIH_EN
VIL_EN
tIC_EN
Input high voltage, IC enable
1.2
AVDD
0.4
V
V
Input low voltage, IC enable
IC enable time
1000
μs
Input high voltage
GPIO, SCL, SDA
VIH_GPIO_SCL
_SDA
1.2
AVDD
V
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
12 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
Parameter Description
Conditions
Min
Typ
Max
Unit
Input low voltage
VIL_GPIO_SCL_
SDA
0.4
V
GPIO, SCL, SDA
Output high voltage
GPIO
Push-pull mode
IOUT = 1 mA
0.8*AV
DD
VOH_GPIO
VOL_GPIO
VOL_SDA
AVDD
V
V
V
Output low voltage
GPIO
Push-pull mode
IOUT = 1 mA
0.2*AV
DD
Output low voltage
SDA
IOUT = 3 mA
0.24
RPD
RPU
GPIO pull-down resistor
GPIO pull-up resistor
2
2
10
10
120
120
kΩ
kΩ
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
13 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
3.8 Timing Characteristics
Table 11: I2C Electrical Characteristics
Parameter Description
Electrical Performance
Conditions
Min
Typ
Max
Unit
Bus free time between a
STOP and START condition
tBUS
0.5
μs
CBUS
Bus line capacitive load
150
pF
20
fSCL
SCL clock frequency
1000
kHz
Note 1
tLO_SCL
tHI_SCL
tRISE
SCL low time
0.5
μs
μs
ns
ns
μs
μs
μs
μs
μs
ns
ns
SCL high time
0.26
SCL and SDA rise time
SCL and SDA fall time
Requirement for input
Requirement for input
1000
300
tFALL
tSETUP_START Start condition setup time
0.26
0.26
0.26
tHOLD_START
tSETUP_STOP
tDATA
Start condition hold time
Stop condition setup time
Data valid time
0.45
0.45
tDATA_ACK
tSETUP_DATA
tHOLD_DATA
Data valid acknowledge time
Data setup time
50
0
Data hold time
Note 1 Minimum clock frequency is limited to 20 kHz if I2C_TIMEOUT is enabled
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
14 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
3.9 Typical Performance
Unless otherwise noted, VIN = 3.7 V, VOUT = 1.0 V, TA = 25 °C, 2.0 mm x 1.6 mm 0.1 μH per-phase
output inductors (DCR = typ. 11.5 mΩ) and 4 x 10 μF output capacitors.
Figure 7: Efficiency v Load, VOUT = 0.7 V
Figure 8: Efficiency vs Load, VOUT = 1.0 V
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
15 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
Figure 9: Efficiency vs Load, VOUT = 1.2 V
Figure 10: Efficiency vs Load, VOUT = 1.8 V
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
16 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
Figure 11: Buck Soft Start-up at 20 mV/µs Slew Rate
Figure 12: Buck Active Shutdown at 20 mV/µs Slew Rate
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
17 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
Figure 13: Buck Load Transient Response in PWM Mode, 0 A to 10 A at 10 A/μs
Figure 14: Buck Load Transient Response in AUTO Mode, 0 A to 10 A at 10 A/μs
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
18 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
4
Functional Description
4.1 DC-DC Buck Converter
DA9121 operates as a single-channel dual-phase buck converter capable of delivering up to 10 A
output current at a 0.3 V to 1.9 V output voltage range.
The buck converter has two voltage registers. One defines the normal output voltage, while the other
offers an alternative retention voltage. In this way, different application power modes can easily be
supported. The voltage selection can be operated either via GPI or via control interface to guarantee
the maximum flexibility according to the specific host processor status in the application.
When a buck is enabled, its output voltage is monitored and a power good signal indicates that the
buck output voltage has reached a level higher than the VTHR_PG_RISE threshold. The power good
status is lost when the voltage drops below VTHR_PG_DWN or increases above VTHR_HV. The status of the
power good indicator can be read back via I2C from the PG1 status bit. It can be also individually
assigned to any of the GPIOs by setting the GPIO mode registers to PG1 output.
The buck converter is capable of supporting DVC transitions that occur when:
●
●
the active and selected A- or B-voltage is updated to a new target value
the voltage selection is changed from the A- to B-voltage (or B- to A-voltage) using CH1_VSEL
The DVC controller operates in pulse width modulation (PWM) mode with synchronous rectification.
The slew rate of the DVC transition is programmed at 10 mV per 8 µs, 4 µs, 2 µs, 1 µs, or 0.5 µs in
register bits CH1_SR_DVC.
A pull-down resistor (typically 150 Ω) for each phase is always activated unless it is disabled by
setting register bits CH1_PD_DIS to 1.
4.1.1
Switching Frequency
The buck switching frequency can be tuned using register bit OSC_TUNE. The internal 8 MHz
oscillator frequency is tuned in ±160 kHz steps. This impacts the buck converter frequency in steps of
80 kHz and helps to mitigate possible disturbances to other high frequency systems in the
application.
4.1.2
Operation Modes and Phase Selection
The buck converters can operate in PWM and PFM modes. The operating mode is selected using
register bits CH1_<A or B>_MODE.
Phase shedding automatically changes between 1- and 2-phase operation at a typical current of
2.0 A.
If the automatic operation mode is selected on CH1_<A or B>_MODE, the buck converter
automatically changes between synchronous PWM mode and PFM depending on the load current.
This improves the efficiency across the whole range of output load currents.
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
19 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
4.1.3
Output Voltage Selection
The switching converter can be configured using the I2C interface.
Two output voltages can be pre-configured in registers CH1_<A or B>_VOUT. The output voltage
can be selected by either toggling register bit CH1_VSEL or by re-programming the selected voltage
control register. Both changes will result in ramped voltage transitions. After being enabled, the buck
converter will, by default, use the register settings in CH1_A_VOUT unless the output voltage
selection is configured via the GPI port.
Registers CH1_VMAX limit the output voltage that can be set for each of the respective buck
converters.
Figure 15: Buck Output Voltage Control Concept
4.1.4
Soft Start-Up and Shutdown
To limit in-rush current from VSYS, the buck converter can perform a soft-start after being enabled.
The start-up behavior is a compromise between acceptable inrush current from the battery and turn-
on time. Ramp times can be configured in register CH1_SR_STARTUP. Rates higher than 20 mV/µs
may produce overshoot during the start-up phase, so it should be considered carefully.
A ramped power down can be selected in register bits CH1_SR_SHDN. When no ramp is selected
(immediate power down), the output node will be discharged only by the pull-down resistor, if
enabled in register CH1_PD_DIS.
4.1.5
Current Limit
The integrated current limit protects the power stages and external coil from excessive current. The
buck current limit should be configured to at least 40 % higher than the required maximum output
current.
When the current limit is reached, the buck converter generates an event and an interrupt to the host
processor unless the interrupt has been masked using register M_OC1 in SYS_MASK_1. Register
bit OC_DVC_MASK is used to mask over-current events during DVC transitions.
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
20 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
4.1.6
Thermal Protection
DA9121 is protected from internal overheating by thermal shutdown.
There are two kinds of flags concerning thermal protection, thermal warning and thermal critical. The
warning flag is asserted when TJ > TWARN and the critical flag is asserted when TJ > TCRIT. When the
critical flag is asserted, Buck1 is shut down immediately.
Table 12: Thermal Protection Control Registers
Category
Register name
TEMP_WARN
TEMP_CRIT
Description
Asserted as long as the thermal warning threshold is reached
Asserted as long as the thermal shutdown threshold is reached
TEMP_WARN caused event
Status
E_TEMP_WARN
E_TEMP_CRIT
M_TEMP_WARN
M_TEMP_CRIT
M_VR_HOT
IRQ event
IRQ mask
TEMP_CRIT caused event
TEMP_WARN event IRQ mask
TEMP_CRIT event IRQ mask
TEMP_WARN status IRQ mask
Buck1 Shutdown
IRQ
IRQ
TCRIT
TWARN
Junction
Temperature
Warning Flag
Critical Flag
I2C Bus
Write
1
to CH<x>_EN
Buck Enable
Figure 16: Thermal Protection Operation
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
21 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
4.2 Internal Circuits
4.2.1
IC_EN/Chip Enable/Disable
IC_EN is chip enable/disable control input. When IC_EN = 0, all blocks except for low IQ POR are
powered-down and buck output is pulled-down.
4.2.2
nIRQ/Interrupt
The interrupt triggers events. Trigger conditions and control registers for each interrupt event are
listed in Table 13.
Some of these events are categorized as fault events and affect device operation (for example, buck
disable), see Section 4.1.6.
Table 13: Interrupt List
Polarity
(Note 1)
IRQ Status
Register
IRQ Mask
Register
Deglitch
Period
Name
Trigger
Thermal
warning
N
N
P
TJ rising above TWARN
E_TEMP_WARN M_TEMP_WARN
0 s
0 s
0 s
(event)
Thermal
critical
TJ rising above TCRIT
E_TEMP_CRIT
E_PG1
M_TEMP_CRIT
M_PG1
(event)
Buck1
power-good
Buck1 VOUT is in power-good
voltage range
(event)
(not under- or over-voltage)
Buck1 VOUT rising above
over-voltage
Buck1
over-voltage
Rise:8 µs
Fall:8 µs
N
E_OV1
M_OV1
threshold (target voltage +
150 mV)
(event)
Buck1
under-
voltage
Buck1 VOUT falling below
under-voltage
N
N
P
E_UV1
E_OC1
PG1
M_UV1
M_OC1
0 s
0 s
0 s
threshold (target voltage -
VTH_PG)
(event)
Buck1
over-current
Buck1 current rising above
over-current threshold
(event)
Buck1
power-good
Buck1 VOUT is in power-good
voltage range
M_PG1_STAT
(Note 3)
(status)
(Note 2)
(not under- or over-voltage)
Thermal
warning
M_VR_HOT
(Note 3)
N
N
N
TJ rising above TWARN
TEMP_WARN
E_GPIO0
0 s
(status)
(Note 2)
Detect GPIO0 change for
active trigger
GPIO0
change
100 µs/
1 ms/
M_GPIO0
M_GPIO1
selected GPIO0_TRIG
register
(event)
10 ms/
100 ms
Detect GPIO1 change for
active trigger
GPIO1
change
E_GPIO1
selected GPIO1_TRIG
register
(event)
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
22 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
Polarity
(Note 1)
IRQ Status
Register
IRQ Mask
Register
Deglitch
Period
Name
Trigger
Detect GPIO2 change for
active trigger
GPIO2
change
N
E_GPIO2
M_GPIO2
selected GPIO2_TRIG
register
(event)
Note 1 Polarity at the source of the flag: P = active-high, N = active-low.
General rule is: normal system state is high, and abnormal system state is low (for example,
PG = high means power-good, TEMP_CRIT = low when TEMP critical state).
Note 2 Interrupt outputs the status as is. I2C write is not required for interrupt clear.
Note 3 OTP load value defined by CONF pin setting if CONF_EN = 1.
Table 14: Interrupt Registers Except for Power Good Status
Register
Description
E_<name>
Read-only interrupt event register
0: No interrupt
1: Interrupt occurred
Cleared after being written to I2C. Set until IRQ is removed.
M_<name>
Interrupt mask register
0: Not masked
1: Masked. No IRQ signal sent. Event register (E_<name>) is updated.
Table 15: Interrupt Registers for Power Good and Temp Warning Status
Register
Description
PG<x>
Buck<x> power good status. Asserted as long as the buck<x> output voltage is in range
(under-voltage threshold < buck output voltage < over-voltage threshold)
0: Not power good
1: Power good
M_PG<x>_STAT
TEMP_WARN
M_VR_HOT
Power good status interrupt mask register
0: Not masked
1: Masked. No IRQ signal sent. Power good status register (PG<x>) is updated
Asserted as long as the thermal warning threshold (TWARN) is reached
0: Junction temperature is below TWARN
1: Junction temperature is above TWARN
Temperature warning status (TEMP_WARN) interrupt mask register
0: Not masked
1: Masked. No IRQ signal sent. Temperature warning status register (TEMP_WARN) is
updated
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
23 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
I2C
Write
Clear
Condition
TJ > TWARN TJ < TWARN
·
·
·
GPIO is cofigured as nIRQ
M_TEMP_WARN = 0
M_PG#_STAT = 0
Over-voltage
Target Voltage
Under-voltage
VOUT
Status Reg
TEMP_WARN
Event Reg
0
1
0
E_TEMP_WARN
IRQ Not
Masked
Status Reg
PG#
Active-High Setting
(GPIO#_POL = 0)
GPIO (nIRQ)
Active-Low Setting
(GPIO#_POL = 1)
Figure 17: Interrupt Operation Example
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
24 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
4.2.3
GPIO
4.2.3.1
GPIO Pin Assignment
The DA9121 provides up to five GPIO pins, three if the I2C is enabled, see Table 16. These registers
are OTP programmable. When CONF_EN = 1 GPIO0 can be used for chip configuration.
Any register settings for GPIO3 and GPIO4 are ignored and GPIO3 and GPIO4 function as SCL and
SDA respectively if I2C_EN = 1.
Table 16: GPIO Pin Assignment
OTP Option
GPIO Pin
GPIO2
Available
GPIOs
CONF/
GPIO0
SCL/
GPIO3
SDA/
GPIO4
I2C_EN
CONF_EN
GPIO1
1’b0
1’b1
1’b0
1’b1
GPIO0
CONF
GPIO0
CONF
GPIO1
GPIO1
GPIO1
GPIO1
GPIO2
GPIO2
GPIO2
GPIO2
GPIO3
GPIO3
SCL
GPIO4
GPIO4
SDA
5
4
3
2
1’b0
1’b1
SCL
SDA
4.2.3.2
GPIO Function
The GPIOs pins are configurable as the following functions in register GPIO<x>_MODE (x = 0 to 4):
●
●
●
●
●
Buck1 enable input (EN1)
Buck1 DVC control input (DVC1)
Buck1 OTP setting reload input (RELOAD)
Buck1 power good output (PG1)
Interrupt output (nIRQ)
Table 17: GPIO Function Configuration
GPIO<x>_MODE[3:0]
Function
GPIO disable
EN1
IO Condition
4’h0
4’h1
4’h2
4’h3
4’h4
4’h5
4’h6
4’h7
4’h8
4’h9
4’hA
4’hB
4’hC
4’hD
4’hE
4’hF
HiZ
In
Reserved
Reserved
DVC1
In
In
In
Reserved
Reserved
RELOAD
PG1
In
In
In
Out
Out
Out
Out
Out
HiZ
Out
Out
Reserved
Reserved
Reserved
nIRQ
Reserved
Low level
High level
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
25 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
4.2.3.3
Chip Configuration Select (CONF)
GPIO0 functions as chip configuration select (CONF) input when CONF_EN = 1.
Three different chip configurations can be selected according to the CONF pin level, whether it is
HIGH, LOW, or Hi-Z.
Table 18: GPIO0-Configurable Registers when CONF_EN = 1
Register Name
IF_SLAVE_ADDR[6:0]
CH1_A_MODE[1:0]
CH1_B_MODE[1:0]
CH1_VSEL
Description
I2C slave address
CH1_A Operation mode select
CH1_B Operation mode select
CH1 output voltage and operation selection
CH1 enable
CH1_EN
CH1_A_VOUT[7:0]
CH1_B_VOUT[7:0]
M_PG1_STAT
CH1 output voltage setting A
CH1 output voltage setting B
IRQ mask setting for CH1 power good status
IRQ mask setting for temp warning status
GPIO1 mode setting
M_VR_HOT
GPIO1_MODE[3:0]
GPIO2_MODE[3:0]
GPIO1_OBUF
GPIO2 mode setting
GPIO1 output buffer select
GPIO2_OBUF
GPIO2 output buffer select
GPIO1_TRIG[1:0]
GPIO1_POL
GPIO1 input trigger select
GPIO1 polarity select
GPIO1_PUPD
GPIO1 pull-up/pull-down enable
GPIO1 input debounce time setting
GPIO1 input debounce rising edge enable
GPIO1 input debounce falling edge enable
GPIO2 input trigger select
GPIO1_DEB[1:0]
GPIO1_DEB_RISE
GPIO1_DEB_FALL
GPIO2_TRIG[1:0]
GPIO2_POL
GPIO2 polarity select
GPIO2_PUPD
GPIO2 pull-up/pull-down enable
GPIO2 input debounce time setting
GPIO2 input debounce rising edge enable
GPIO2 input debounce falling edge enable
GPIO2_DEB[1:0]
GPIO2_DEB_RISE
GPIO2_DEB_FALL
4.2.3.4
OTP Reload (RELOAD)
Buck settings listed in Table 19 are reloaded from CONF registers by triggering GPIO configured as
RELOAD input.
The OTP reload happens at the same time for Buck1 settings. During reloading, Buck1 keeps
operating as configured without shut-down.
Table 19: OTP Reload Registers
Register Name
Description
CH#_VSEL
CH# output voltage and operation selection.
0: A, 1: B
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
26 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
Register Name
Description
CH#_A_VOUT[7:0]
CH# output voltage setting A : CH#_A_VOUT * 10 mV
Setting under 0.3V is clamped to 0.3V, and setting over 1.9V is clamped to 1.9 V
CH#_B_VOUT[7:0]
CH#_A_MODE[1:0]
CH# output voltage setting B : CH#_A_VOUT * 10 mV
Setting under 0.3 V is clamped to 0.3 V, and setting over 1.9V is clamped to 1.9 V
Operation mode selection
0: Force PFM
1: Force PWM. full phase
2: Force PWM with phase shedding
3: Auto mode
CH#_B_MODE[1:0]
Operation mode selection
0: Force PFM
1: Force PWM. full phase
2: Force PWM with phase shedding
3: Auto mode
4.3 Operating Modes
4.3.1 ON
DA9121 is ON when the IC_EN port is higher than VIH_EN and the supply voltage is higher than
VTHR_POR. Once enabled, the host processor can start communicating with DA9121 using the control
interface, after the tIC_EN delay.
4.3.2
OFF
DA9121 is OFF when the IC_EN port is lower than VIL_EN. In OFF, the bucks are always disabled and
LX nodes are pulled down by (typically 150 Ω) internal pull-down resistors.
4.4 I2C Communication
All features of DA9121 can be controlled with the I2C interface which is enabled or disabled in
register I2C_EN.
I2C_EN
Description
0
I2C disable: SCL/GPIO3 and SDA/GPIO4 pins can be used as GPIO
I2C enable: SCL/GPIO3 and SDA/GPIO4 pins are used as I2C clock input and I2C data
input/output.
1
GPIO3 functions as the I2C clock and GPIO4 carries all the power manager bidirectional I2C data.
The I2C interface is open-drain supporting multiple devices on a single line. The bus lines have to be
pulled high by external pull-up resistors (2 kΩ to 20 kΩ). The standard frequency of the I2C bus is
1 MHz in fast-mode plus (FM+), 400 kHz in fast-mode, or 100 kHz in standard mode.
4.4.1
I2C Protocol
All data is transmitted across the I2C bus in eight-bit groups. To send a bit, the SDA line is driven
towards the intended state while the SCL is low (a low SDA indicates a zero bit). Once the SDA has
settled, the SCL line is brought high and then low. This pulse on SCL clocks the SDA bit into the
receiver’s shift register.
A two-byte serial protocol is used containing one byte for address and one byte data. Data and
address transfer are transmitted MSB first for both read and write operations. All transmissions begin
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
27 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
with the START condition from the master while the bus is in idle state (the bus is free). It is initiated
by a high to low transition on the SDA line while the SCL is in the high state (a STOP condition is
indicated by a low to high transition on the SDA line while the SCL is in the high state).
SCL
SDA
Figure 18: I2C START and STOP Condition Timing
The I2C bus is monitored for a valid slave address whenever the interface is enabled. It responds
immediately when it receives its own slave address. The acknowledge is done by pulling the SDA
line low during the following clock cycle (white blocks marked with A in Figure 19 and Figure 20).
The protocol for a register write from master to slave consists of a START condition, a slave address
with read/write bit, and the eight-bit register address followed by eight bits of data, terminated by a
STOP condition. DA9121 responds to all bytes with acknowledge (A), see Figure 19.
P
S
SLAVEadr
7-bits
W
A
REGadr
8-bits
A
DATA
8-bits
A
1-bit
Master to Slave
Slave to Master
S = START condition
P = STOP condition
A = Acknowledge (low)
W = Write (low)
Figure 19: I2C Byte Write (SDA Line)
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
28 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
When the host reads data from a register it first has to write to DA9121 with the target register
address and then read from DA9121 with a repeated START, or alternatively a second START,
condition. After receiving the data, the host sends no acknowledge (A*) and terminates the
transmission with a STOP condition, see Figure 20.
A*
P
S
SLAVEadr W A REGadr A Sr SLAVEadr
R
A
DATA
8-bits
1-bit
7-bits 1-bit
8-bits
7-bits
S
SLAVEadr W A REGadr
A
P
S
SLAVEadr
R
A
DATA
8-bits
A*
P
7-bits 1-bit
8-bits
7-bits 1-bit
Master to Slave
Slave to Master
S = START condition
Sr = Repeated START condition
P = STOP condition
A = Acknowledge (low)
A* = No Acknowledge
W = Write (low)
R = Read (high)
Figure 20: I2C Byte Read (SDA Line) Examples
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
29 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
5
Register Definitions
5.1 Register Map
Table 20: Register Map
Addr
Register
7
6
5
4
3
2
1
0
System Module
System
TEMP_WA
RN
0x0001
SYS_STATUS_0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TEMP_CRIT
0x0002
0x0003
SYS_STATUS_1
SYS_STATUS_2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PG1
OV1
UV1
OC1
Reserved
GPIO2
GPIO1
GPIO0
E_TEMP_C
RIT
E_TEMP_
WARN
0x0004
SYS_EVENT_0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x0005
0x0006
SYS_EVENT_1
SYS_EVENT_2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
E_PG1
E_OV1
E_UV1
E_OC1
Reserved
E_GPIO2
E_GPIO1
E_GPIO0
M_TEMP_C
RIT
M_TEMP_
WARN
0x0007
SYS_MASK_0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x0008
0x0009
SYS_MASK_1
SYS_MASK_2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
M_PG1
M_OV1
M_UV1
M_OC1
Reserved
M_GPIO2
M_GPIO1
M_GPIO0
M_VR_HO
T
M_PG1_ST
AT
0x000A
SYS_MASK_3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x000B
0x000C
SYS_CONFIG_0
SYS_CONFIG_1
Reserved
Reserved
Reserved
Reserved
OC_DVC_
MASK
0x000D
0x000E
0x0010
0x0011
0x0012
0x0013
0x0014
0x0015
SYS_CONFIG_2
SYS_CONFIG_3
SYS_GPIO0_0
SYS_GPIO0_1
SYS_GPIO1_0
SYS_GPIO1_1
SYS_GPIO2_0
SYS_GPIO2_1
Reserved
Reserved
Reserved
OC_LATCHOFF<1:0>
OSC_TUNE<2:0>
PG_DVC_MASK<1:0>
Reserved
Reserved
Reserved
I2C_TIMEO
UT
Reserved
Reserved
GPIO0_OB
UF
Reserved
Reserved
GPIO0_MODE<3:0>
GPIO0_P
GPIO0_D
EB_FALL
GPIO0_D
EB_RISE
GPIO0_DEB<1:0>
GPIO0_POL
GPIO1_POL
GPIO2_POL
GPIO0_TRIG<1:0>
UPD
GPIO1_OB
Reserved
Reserved
Reserved
GPIO1_MODE<3:0>
UF
GPIO1_D
EB_FALL
GPIO1_D
EB_RISE
GPIO1_P
UPD
GPIO1_DEB<1:0>
GPIO1_TRIG<1:0>
GPIO2_OB
Reserved
Reserved
Reserved
GPIO2_MODE<3:0>
UF
GPIO2_D
EB_FALL
GPIO2_D
EB_RISE
GPIO2_P
UPD
GPIO2_DEB<1:0>
GPIO2_TRIG<1:0>
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
30 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
Addr
Register
7
6
5
4
3
2
1
0
Buck Control
Buck1
0x0020
0x0021
BUCK_BUCK1_0
Reserved
Reserved
Reserved
CH1_SR_DVC_DWN<2:0>
CH1_SR_SHDN<2:0>
CH1_SR_DVC_UP<2:0>
CH1_SR_STARTUP<2:0>
CH1_ILIM<3:0>
CH1_EN
CH1_PD_D
IS
BUCK_BUCK1_1
0x0022
0x0023
BUCK_BUCK1_2
BUCK_BUCK1_3
Reserved
Reserved
Reserved
CH1_VMAX<7:0>
CH1_VSE
L
0x0024
BUCK_BUCK1_4
Reserved
Reserved
Reserved
CH1_B_MODE<1:0>
CH1_A_MODE<1:0>
0x0025
0x0026
0x0027
BUCK_BUCK1_5
BUCK_BUCK1_6
BUCK_BUCK1_7
CH1_A_VOUT<7:0>
CH1_B_VOUT<7:0>
Reserved
Reserved
Reserved
Reserved
Reserved
VRC<3:0>
Reserved
Reserved
Serialization
0x0048
0x0049
0x004A
0x004B
OTP_DEVICE_ID
DEV_ID<7:0>
MRC<3:0>
OTP_VARIANT_ID
OTP_CUSTOMER_ID
OTP_CONFIG_ID
CUST_ID<7:0>
CONFIG_REV<7:0>
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
31 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
5.1.1
System
Table 21: SYS_STATUS_0 (0x0001)
Bit
[1]
[0]
Symbol
Description
TEMP_CRIT
TEMP_WARN
Asserted as long as the thermal shutdown threshold is reached
Asserted as long as the thermal warning threshold is reached
Table 22: SYS_STATUS_1 (0x0002)
Bit
[3]
[2]
[1]
[0]
Symbol
PG1
Description
Asserted as long as the Buck1 output voltage is in range
Asserted as long as Buck1 hitting over-voltage
Asserted as long as Buck1 hitting under-voltage
Asserted as long as Buck1 hitting over-current
OV1
UV1
OC1
Table 23: SYS_STATUS_2 (0x0003)
Bit
[2]
[1]
[0]
Symbol
GPIO2
GPIO1
GPIO0
Description
GPIO2 status
GPIO1 status
GPIO0 status
Table 24: SYS_EVENT_0 (0x0004)
Bit
Symbol
Description
TEMP_CRIT caused event. Writing 1 action clear this bit into 0 if
event source has been released.
[1]
E_TEMP_CRIT
TEMP_WARN caused event. Writing 1 action clear this bit into 0
if event source has been released.
[0]
E_TEMP_WARN
Table 25: SYS_EVENT_1 (0x0005)
Bit
Symbol
Description
PG1 caused event. Writing 1 action clear this bit into 0 if event
source has been released.
[3]
E_PG1
OV1 caused event. Writing 1 action clear this bit into 0 if event
source has been released.
[2]
[1]
[0]
E_OV1
E_UV1
E_OC1
UV1 caused event. Writing 1 action clear this bit into 0 if event
source has been released.
OC1 caused event. Writing 1 action clear this bit into 0 if event
source has been released.
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
32 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
Table 26: SYS_EVENT_2 (0x0006)
Bit
Symbol
Description
GPIO2 event. Writing 1 action clear this bit into 0 if event source
has been released.
[2]
E_GPIO2
GPIO1 event. Writing 1 action clear this bit into 0 if event source
has been released.
[1]
[0]
E_GPIO1
E_GPIO0
GPIO0 event. Writing 1 action clear this bit into 0 if event source
has been released.
Table 27: SYS_MASK_0 (0x0007)
Bit
[1]
[0]
Symbol
Description
M_TEMP_CRIT
TEMP_CRIT IRQ mask
M_TEMP_WARN TEMP_WARN IRQ mask
Table 28: SYS_MASK_1 (0x0008)
Bit
[3]
[2]
[1]
[0]
Symbol
M_PG1
M_OV1
M_UV1
M_OC1
Description
PG1 event IRQ mask
OV1 event IRQ mask
UV1 event IRQ mask
OC1 event IRQ mask
Table 29: SYS_MASK_2 (0x0009)
Bit
[2]
[1]
[0]
Symbol
Description
M_GPIO2
M_GPIO1
M_GPIO0
GPIO2 IRQ mask
GPIO1 IRQ mask
GPIO0 IRQ mask
Table 30: SYS_MASK_3 (0x000A)
Bit
Symbol
Description
Temp warning status IRQ mask. Initial value is determined by
CONF pin setting at the start-up in CONF_EN = 1
[3]
M_VR_HOT
PG1 status IRQ mask. Initial value is determined by CONF pin
setting at the start-up in CONF_EN = 1
[0]
M_PG1_STAT
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
33 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
Table 31: SYS_CONFIG_2 (0x000D)
Bit
Symbol
Description
Over-current latch-off setting. BUCK shut-down after OCP for
8 µs/1 ms/3 ms unless disable setting. IRQ is generated unless
IRQ is masked.
Value
0x0
0x1
Description
[6:5]
OC_LATCHOFF
Latch off disable
Latch off after 8 µs of OCP signal
Latch off after 1 ms of OCP signal
Latch off after 3 ms of OCP signal
0x2
0x3
Over-current event (IRQ and latch-off feature) mask during DVC
ramp-up and ramp-down
[4]
OC_DVC_MASK
PG_DVC_MASK
Power-good mask during DVC
Value
0x0
0x1
Description
No mask
[3:2]
Mask as not power good during DVC
Mask as power good during DVC
Reserved
0x2
0x3
Table 32: SYS_CONFIG_3 (0x000E)
Bit
Symbol
Description
Tune oscillator frequency, tuned frequency = Current +
OSC_TUNE * 160 kHz
Value
0x3
0x2
0x1
0x0
0x7
0x6
0x5
0x4
Description
3
2
1
[6:4]
OSC_TUNE
0
-1
-2
-3
-4
Enable automatic reset of 2-wire interface (if SDA stays low for
>50 ms).
[1]
I2C_TIMEOUT
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
34 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
Table 33: SYS_GPIO0_0 (0x0010)
Bit
Symbol
Description
GPIO function mode select
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
Description
GPIO disable
EN1 input
Reserved
Reserved
DVC1 input
Reserved
Reserved
[4:1]
GPIO0_MODE
RELOAD input
PG1 output
Reserved
Reserved
Reserved
nIRQ output
Reserved
Low output
High output
GPIO output buffer select
Value
0x0
Description
[0]
GPIO0_OBUF
open-drain output
push-pull output
0x1
Table 34: SYS_GPIO0_1 (0x0011)
Bit
[7]
[6]
Symbol
Description
GPIO0_DEB_FALL
GPIO0_DEB_RISE
GPI debouce falling edge
GPI debounce rising edge
GPI debounce time
Value
0x0
0x1
Description
100 µs debouce
1 ms debouce
[5:4]
GPIO0_DEB
0x2
10 ms debounce
100 ms debounce
0x3
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
35 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
Bit
Symbol
Description
GPIO pull-up/pull-down enable
Value
0x0
Description
GPI: pull-down disabled, GPO: pull-up to
AVDD disabled
[3]
GPIO0_PUPD
GPI: pull-down enabled, GPO: pull-up to AVDD
enabled
0x1
GPIO polarity
Value
0x0
Description
[2]
GPIO0_POL
GPIO is active-high
0x1
GPIO is active-low
GPI trigger type
Value
0x0
0x1
Description
Dual-edge triggered
Pos-edge triggered
Neg-edge triggered
Reserved (No trigger)
[1:0]
GPIO0_TRIG
0x2
0x3
Table 35: SYS_GPIO1_0 (0x0012)
Bit
Symbol
Description
GPIO function mode select. Initial value is determined by
CONF pin setting at the start-up in CONF_EN = 1
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
Description
GPIO disable
EN1 input
Reserved
Reserved
DVC1 input
Reserved
Reserved
[4:1]
GPIO1_MODE
RELOAD input
PG1 output
Reserved
Reserved
Reserved
nIRQ output
Reserved
Low output
High output
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
36 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
Bit
Symbol
Description
GPIO output buffer select. Initial value is determined by
CONF pin setting at the start-up in CONF_EN = 1
Value
0x0
Description
[0]
GPIO1_OBUF
open-drain output
push-pull output
0x1
Table 36: SYS_GPIO1_1 (0x0013)
Bit
Symbol
Description
GPI debouce falling edge. Initial value is determined by
CONF pin setting at the start-up in CONF_EN = 1
[7]
GPIO1_DEB_FALL
GPI debounce rising edge. Initial value is determined by
CONF pin setting at the start-up in CONF_EN = 1
[6]
GPIO1_DEB_RISE
GPIO1_DEB
GPI debounce time. Initial value is determined by CONF
pin setting at the start-up in CONF_EN = 1
Value
0x0
0x1
Description
100 µs debouce
1 ms debouce
[5:4]
0x2
10 ms debounce
100 ms debounce
0x3
GPIO pull-up/pull-down enable. Initial value is determined
by CONF pin setting at the start-up in CONF_EN = 1
Value
0x0
Description
[3]
GPIO1_PUPD
GPI: pull-down disabled, GPO: pull-up to
AVDD disabled
GPI: pull-down enabled, GPO: pull-up to AVDD
enabled
0x1
GPIO polarity. Initial value is determined by CONF pin
setting at the start-up in CONF_EN = 1
Value
0x0
Description
[2]
GPIO1_POL
GPIO is active-high
GPIO is active-low
0x1
GPI trigger type. Initial value is determined by CONF pin
setting at the start-up in CONF_EN = 1
Value
0x0
0x1
Description
Dual-edge triggered
Pos-edge triggered
Neg-edge triggered
Reserved (No trigger)
[1:0]
GPIO1_TRIG
0x2
0x3
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
37 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
Table 37: SYS_GPIO2_0 (0x0014)
Bit
Symbol
Description
GPIO function mode select. Initial value is determined by
CONF pin setting at the start-up in CONF_EN = 1
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
Description
GPIO disable
EN1 input
Reserved
Reserved
DVC1 input
Reserved
Reserved
[4:1]
GPIO2_MODE
RELOAD input
PG1 output
Reserved
Reserved
Reserved
nIRQ output
Reserved
Low output
High output
GPIO output buffer select. Initial value is determined by
CONF pin setting at the start-up in CONF_EN = 1
Value
0x0
Description
[0]
GPIO2_OBUF
open-drain output
push-pull output
0x1
Table 38: SYS_GPIO2_1 (0x0015)
Bit
Symbol
Description
GPI debouce falling edge. Initial value is determined by
CONF pin setting at the start-up in CONF_EN = 1
[7]
GPIO2_DEB_FALL
GPI debounce rising edge. Initial value is determined by
CONF pin setting at the start-up in CONF_EN = 1
[6]
GPIO2_DEB_RISE
GPIO2_DEB
GPI debounce time. Initial value is determined by CONF
pin setting at the start-up in CONF_EN = 1
Value
0x0
0x1
Description
100 µs debouce
1 ms debouce
[5:4]
0x2
10 ms debounce
100 ms debounce
0x3
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
38 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
Bit
Symbol
Description
GPIO pull-up/pull-down enable. Initial value is determined
by CONF pin setting at the start-up in CONF_EN = 1
Value
0x0
Description
[3]
GPIO2_PUPD
GPI: pull-down disabled, GPO: pull-up to
AVDD disabled
GPI: pull-down enabled, GPO: pull-up to AVDD
enabled
0x1
GPIO polarity. Initial value is determined by CONF pin
setting at the start-up in CONF_EN = 1
Value
0x0
Description
[2]
GPIO2_POL
GPIO is active-high
GPIO is active-low
0x1
GPI trigger type. Initial value is determined by CONF pin
setting at the start-up in CONF_EN = 1
Value
0x0
0x1
Description
Dual-edge triggered
Pos-edge triggered
Neg-edge triggered
Reserved (No trigger)
[1:0]
GPIO2_TRIG
0x2
0x3
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
39 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
5.1.2
Buck1
Table 39: BUCK_BUCK1_0 (0x0020)
Bit
Symbol
Description
Voltage slew-rate for DVC ramp-down
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Description
10 mV/8 µs
10 mV/4 µs
10 mV/2 µs
10 mV/µs
[6:4]
CH1_SR_DVC_DWN
20 mV/µs
Reserved
Reserved
Reserved
Voltage slew-rate for DVC ramp-up
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Description
10 mV/8 µs
10 mV/4 µs
10 mV/2 µs
10 mV/µs
[3:1]
CH1_SR_DVC_UP
20 mV/µs
40 mV/µs
Reserved
Reserved
Channel enable. Initial value is determined by CONF pin
setting at the start-up in CONF_EN = 1
[0]
CH1_EN
Table 40: BUCK_BUCK1_1 (0x0021)
Bit
Symbol
Description
Voltage slew-rate during shut-down
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Description
10 mV/8 µs
10 mV/4 µs
10 mV/2 µs
10 mV/µs
[6:4]
CH1_SR_SHDN
20 mV/µs
Reserved
Reserved
Immediate power-down
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
40 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
Bit
Symbol
Description
Voltage slew-rate during startup
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Description
10 mV/8 µs
10 mV/4 µs
10 mV/2 µs
10 mV/µs
[3:1]
CH1_SR_STARTUP
20 mV/µs
40 mV/µs
Reserved
Reserved
[0]
CH1_PD_DIS
Pull-down while buck is disabled. 0: enable, 1: disable
Table 41: BUCK_BUCK1_2 (0x0022)
Bit
Symbol
Description
Select OCP threshold (A)
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
Description
Reserved
3.5
4.0
4.5
5.0
5.5
6.0
[3:0]
CH1_ILIM
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
Disable
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
41 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
Table 42: BUCK_BUCK1_3 (0x0023)
Bit
Symbol
Description
VOUT max setting (V):
From 0.30 V (0x1E) to 1.90 V (0xBE) in 10 mV steps.
This is a read-only register.
Value
0x1E
0x1F
0x20
Description
0.3
0.31
[7:0]
CH1_VMAX
0.32
Continuing through…
0x99
To…
0xBD
0xBE
1.53
1.89
1.9
Table 43: BUCK_BUCK1_4 (0x0024)
Bit
Symbol
Description
Output voltage and operation selection: 0: A, 1: B.
Initial value is determined by CONF pin setting at the start-
up in CONF_EN = 1
[4]
CH1_VSEL
Operation mode selection.
Initial value is determined by CONF pin setting at the start-
up in CONF_EN = 1
Value
0x0
Description
[3:2]
CH1_B_MODE
Force PFM operation
0x1
Force PWM operation (full phase)
Force PWM operation (with phase shedding)
Auto mode
0x2
0x3
Operation mode selection.
Initial value is determined by CONF pin setting at the start-
up in CONF_EN = 1
Value
0x0
Description
[1:0]
CH1_A_MODE
Force PFM operation
0x1
Force PWM operation (full phase)
Force PWM operation (with phase shedding)
Auto mode
0x2
0x3
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
42 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
Table 44: BUCK_BUCK1_5 (0x0025)
Bit
Symbol
Description
Output voltage setting A: Initial value is determined by
CONF pin setting at the start-up in CONF_EN = 1
From 0.30 V (0x1E) to 1.90 V (0xBE) in steps of 10 mV
(default 1.0 V)
Write-protected when value is written below 0.30 V or
above 1.90 V
Value
0x1E
0x1F
0x20
Description
0.3
0.31
[7:0]
CH1_A_VOUT
0.32
Continuing through…
0x64
To…
0xBC
0xBD
0xBE
1
1.88
1.89
1.9
Table 45: BUCK_BUCK1_6 (0x0026)
Bit
Symbol
Description
Output voltage setting B: Initial value is determined by
CONF pin setting at the start-up in CONF_EN = 1
From 0.30 V (0x1E) to 1.90 V (0xBE) in steps of 10 mV
(default 1.0 V)
Write-protected when value is written below 0.30 V or
above 1.90 V
Value
0x1E
0x1F
0x20
Description
0.3
0.31
[7:0]
CH1_B_VOUT
0.32
Continuing through…
0x64
To…
0xBC
0xBD
0xBE
1
1.88
1.89
1.9
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
43 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
5.1.3
Serialization
Table 46: OTP_DEVICE_ID (0x0048)
Bit
Symbol
Description
[7:0]
DEV_ID
Device ID
Table 47: OTP_VARIANT_ID (0x0049)
Bit
Symbol
MRC
Description
[7:4]
[3:0]
Mask Revision Code
Chip Variant Code
VRC
Table 48: OTP_CUSTOMER_ID (0x004A)
Bit
Symbol
Description
[7:0]
CUST_ID
Customer ID
Table 49: OTP_CONFIG_ID (0x004B)
Bit
Symbol
Description
[7:0]
CONFIG_REV
OTP Variant
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
44 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
6
Package Information
6.1 Package Outlines
Figure 21: WLCSP Package Outline Drawing
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
45 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
Figure 22: WLP Package Outline Drawing
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
46 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
6.2 Moisture Sensitivity Level
The moisture sensitivity level (MSL) is an indicator for the maximum allowable time period (floor
lifetime) in which a moisture sensitive plastic device, once removed from the dry bag, can be
exposed to an environment with a specified maximum temperature and a maximum relative humidity
before the solder reflow process. The MSL classification is defined in Table 50.
For detailed information on MSL levels refer to the IPC/JEDEC standard J-STD-020, which can be
downloaded from http://www.jedec.org.
The DA9121 package is qualified for MSL1.
Table 50: MSL Classification
MSL Level
Floor Lifetime
Conditions
MSL 1
Unlimited
≤30 °C / 85 % RH
6.3 Package Handling
Manual handling of WLCSP packages should be reduced to the absolute minimum. In cases where it
is still necessary, a vacuum pick-up tool should be used. In extreme cases plastic tweezers could be
used, but metal tweezers are not acceptable, since contact may easily damage the silicon chip.
Removal of a WLP or WLCSP package will cause damage to the solder balls. Therefore a removed
sample cannot be reused.
WLCSP packages are sensitive to visible and infrared light. For light sensitive applications, the WLP
package should be used.
6.4 Soldering Information
Refer to the IPC/JEDEC standard J-STD-020 for relevant soldering information. This document can
be downloaded from http://www.jedec.org.
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
47 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
7
Ordering Information
The ordering number consists of the part number followed by a suffix indicating the packing method.
For details and availability, please consult Dialog Semiconductor’s customer support portal or your
local sales representative.
Table 51: Ordering Information
Part Number
DA9121-xxV72
DA9121-xxV76
Package
24 WLCSP
24 WLCSP
Size (mm)
2.5 x 1.7
2.5 x 1.7
Shipment Form
T&R
Pack Quantity
4500
Waffle Tray
140
DA9121-B0V72
Standard OTP Variant
VOUT1 = 1.0 V
24 WLCSP
24 WLCSP
2.5 x 1.7
2.5 x 1.7
T&R
4500
140
DA9121-B0V76
Standard OTP Variant
VOUT1 = 1.0 V
Waffle Tray
DA9121-xxOZ2
DA9121-xxOZ6
24 WLP
24 WLP
2.7 x 1.9
2.7 x 1.9
T&R
TBD
TBD
Waffle Tray
DA9121-B0OZ2
Standard OTP Variant
VOUT1 = 1.0 V
24 WLP
2.7 x 1.9
T&R
TBD
8
Application Information
The following recommended components are examples selected from requirements of a typical
application.
8.1 Capacitor Selection
Ceramic capacitors are used as bypass capacitors at all VDD and output rails. When selecting a
capacitor, especially for types with high capacitance at smallest physical dimension, the DC bias
characteristic has to be taken into account.
Table 52: Recommended Capacitor Types
Application
Value
Size
Temp. Char.
Tol. (%)
V-Rate
Type
Murata
VOUT
output bypass
10 µF
0402
X5R ±15 %
±20
6.3 V
GRM155R60J106ME15
Murata
PVDDx
bypass
10 µF
0603
0402
X5R ±15 %
X5R ±15 %
±20
±10
25 V
10 V
GRM188R61E106MA73
Murata
GRM155R61A105KE15
AVDD bypass 1 µF
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
48 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
8.2 Inductor Selection
Inductors should be selected based on the following parameters:
●
Rated maximum current
Usually a coil provides two current limits: ISAT specifies the maximum current at which the
inductance drops by 30 % of the nominal value, and IMAX is defined by the maximum power
dissipation and is applied to the effective current.
●
DC resistance
Critical for the converter efficiency and should therefore be minimized.
Table 53: Recommended Inductor Types
DC
Tol. (%) Resistance Type
(mΩ)
Value
(µH)
IMAX (DC)
(A)
Size (mm)
ISAT (A)
Cyntec
0.1
0.1
2.0 x 1.6 x 1.0
1.6 x 0.8 x 1.0
1.6 x 0.8 x 0.8
2.0 x 1.25 x 0.8
2.5 x 2.0 x 1.2
1.6 x 0.8 x 0.95
2.0 x 1.6 x 0.6
6.5
5.2
4.1
5.8
12
9.0
6.5
9.4
6.9
13
±20
±20
±20
±20
±20
±20
±20
11.5
17
19
9.1
4
HTEN20161T-R10MDR
Taiyo Yuden
MEKK1608TR10M
Taiyo Yuden
0.1
MCHK1608TR10MJN
Taiyo Yuden
0.11
0.1
MCHK2012TR11MKG
TDK
TFM252012ALMAR10MT
Tokyo Coil Engineering
TFP160810M-R10N
0.1
3.8
3.0
4.3
6.0
15
24
Wurth Elektronik
0.11
WE-PMMI 744 799 771 11
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
49 of 50
© 2020 Dialog Semiconductor
DA9121
High-Performance, 10 A, Dual-Phase DC-DC Converter
Status Definitions
Revision
Datasheet Status
Product Status
Definition
This datasheet contains the design specifications for product development.
Specifications may be changed in any manner without notice.
1.<n>
Target
Development
This datasheet contains the specifications and preliminary characterization
data for products in pre-production. Specifications may be changed at any
time without notice in order to improve the design.
2.<n>
3.<n>
Preliminary
Qualification
This datasheet contains the final specifications for products in volume
production. The specifications may be changed at any time in order to
improve the design, manufacturing and supply. Major specification changes
are communicated via Customer Product Notifications. Datasheet changes
are communicated via www.dialog-semiconductor.com.
Final
Production
Archived
This datasheet contains the specifications for discontinued products. The
information is provided for reference only.
4.<n>
Obsolete
Disclaimer
Unless otherwise agreed in writing, the Dialog Semiconductor products (and any associated software) referred to in this document are not
designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications
where failure or malfunction of a Dialog Semiconductor product (or associated software) can reasonably be expected to result in personal injury,
death or severe property or environmental damage. Dialog Semiconductor and its suppliers accept no liability for inclusion and/or use of Dialog
Semiconductor products (and any associated software) in such equipment or applications and therefore such inclusion and/or use is at the
customer’s own risk.
Information in this document is believed to be accurate and reliable. However, Dialog Semiconductor does not give any representations or
warranties, express or implied, as to the accuracy or completeness of such information. Dialog Semiconductor furthermore takes no
responsibility whatsoever for the content in this document if provided by any information source outside of Dialog Semiconductor.
Dialog Semiconductor reserves the right to change without notice the information published in this document, including, without limitation, the
specification and the design of the related semiconductor products, software and applications. Notwithstanding the foregoing, for any automotive
grade version of the device, Dialog Semiconductor reserves the right to change the information published in this document, including, without
limitation, the specification and the design of the related semiconductor products, software and applications, in accordance with its standard
automotive change notification process.
Applications, software, and semiconductor products described in this document are for illustrative purposes only. Dialog Semiconductor makes
no representation or warranty that such applications, software and semiconductor products will be suitable for the specified use without further
testing or modification. Unless otherwise agreed in writing, such testing or modification is the sole responsibility of the customer and Dialog
Semiconductor excludes all liability in this respect.
Nothing in this document may be construed as a license for customer to use the Dialog Semiconductor products, software and applications
referred to in this document. Such license must be separately sought by customer with Dialog Semiconductor.
All use of Dialog Semiconductor products, software and applications referred to in this document is subject to Dialog Semiconductor’s Standard
Terms and Conditions of Sale, available on the company website (www.dialog-semiconductor.com) unless otherwise stated.
Dialog, Dialog Semiconductor and the Dialog logo are trademarks of Dialog Semiconductor Plc or its subsidiaries. All other product or service
names and marks are the property of their respective owners.
© 2020 Dialog Semiconductor. All rights reserved.
RoHS Compliance
Dialog Semiconductor’s suppliers certify that its products are in compliance with the requirements of Directive 2011/65/EU of the European
Parliament on the restriction of the use of certain hazardous substances in electrical and electronic equipment. RoHS certificates from our
suppliers are available on request.
Contacting Dialog Semiconductor
United Kingdom (Headquarters)
Dialog Semiconductor (UK) LTD
Phone: +44 1793 757700
North America
Hong Kong
China (Shenzhen)
Dialog Semiconductor Inc.
Phone: +1 408 845 8500
Dialog Semiconductor Hong Kong
Phone: +852 2607 4271
Dialog Semiconductor China
Phone: +86 755 2981 3669
Germany
Japan
Korea
China (Shanghai)
Dialog Semiconductor GmbH
Phone: +49 7021 805-0
Dialog Semiconductor K. K.
Phone: +81 3 5769 5100
Dialog Semiconductor Korea
Phone: +82 2 3469 8200
Dialog Semiconductor China
Phone: +86 21 5424 9058
The Netherlands
Taiwan
Dialog Semiconductor B.V.
Phone: +31 73 640 8822
Dialog Semiconductor Taiwan
Phone: +886 281 786 222
Email:
Web site:
enquiry@diasemi.com
www.dialog-semiconductor.com
Datasheet
Revision 2.3
18-Sep-2020
CFR0011-120-00
50 of 50
© 2020 Dialog Semiconductor
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明