DA9224-A_技术文档

DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

General Description

DA9223-A and DA9224-A are PMICs optimized for the supply of CPUs, GPUs, and DDR memory

rails in automotive in-vehicle infotainment systems, Advanced Driver Assistance Systems (ADAS),

navigation and telematics applications. The fast transient response (10 A/µs) and load regulation are

optimized for the latest generation of multi core application processors.

DA9223-A operates as a single four-phase buck converter delivering up to 16 A output current.

DA9224-A integrates two dual-phase buck converters, capable of delivering 2 x 8 A output current.

Each buck regulates a programmable output voltage in the range of 0.3 V to 1.57 V. With an external

resistor divider the output voltage can be set to any voltage between 1.57 V and 4.3 V. The input

voltage range of 2.8 V to 5.5 V makes it suited for a wide variety of low voltage systems, including all

Li-Ion battery powered applications.

To guarantee the highest accuracy and to support multiple PCB routing scenarios without loss of

performance, a remote sensing capability is implemented in both the DA9223-A and DA9224-A.

The power devices are fully integrated, so no external FETs or Schottky diodes are needed.

A programmable soft start-up can be enabled, which limits the inrush current from the input node and

secures a slope controlled activation of the rail.

The Dynamic Voltage Control (DVC) supports adaptive adjustment of the supply voltage depending

on the processor load, either via direct register writes through the communication interface (I²C or

SPI compatible) or via an input pin.

DA9223-A and DA9224-A feature integrated over-temperature and over-current protection for

increased system reliability without the need for external sensing components. The safety feature set

is completed by a VDDIO under voltage lockout.

The configurable I²C address selection via GPI allows multiple instances of DA9223-A and DA9224-

A to be placed in an application sharing the same communication interface with different addresses.

Key Features

■

2.8 V to 5.5 V input voltage

1 x 16 A DA9223-A

■

Dynamic Voltage Control (DVC)

Automatic phase shedding

Integrated power switches

Remote sensing at point of load

I²C/SPI compatible interface

Adjustable soft start

2 x 8 A DA9224-A

3 MHz nominal switching frequency (allows

use of low profile [1 mm] inductors)

■

±1 % accuracy (static)

±3 % accuracy (dynamic)

-40 °C to +105 ºC temperature range

AEC-Q100 grade 2 qualified

66 TFBGA 0.8 mm pitch

0.3 V to 1.57 V output voltage

1.57 V to 4.3 V with resistor divider

Applications

■

In-car infotainment

■

Navigation and telematics

Mobile computing

Automotive display clusters

Advanced Driver Assistance Systems (ADAS)

Industrial embedded systems

Datasheet

Revision 2.6

23-Apr-2021

CFR0011-120-00

1 of 60

DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

System Diagrams

1µF

4x 10µF

FBAP

IC_EN

OTP

DIGITAL

MEMORY

CORE

GPI

GPI0

GPI1

4x 0.22µH

CTRL

+

DRIVE

BIAS

SUPERV

OSC

GPIO

GPIO2

REGISTER

SPACE

PoL

4x 47µF

OUT

nIRQ

VDDIO

DVS

2/4-WIRE INTERFACE

100nF

VSS_ANA

FBAN

FBBP

FBBN

Figure 1: DA9223-A System Diagram

1µF

4x 10µF

Buck A

FBAP

IC_EN

2x 0.22µH

OTP

MEMORY

DIGITAL

CORE

CTRL

+

GPI

GPI0

GPI1

PoL

DRIVE

GPI

2x 47µF

BIAS

SUPERV

OSC

GPIO

GPIO2

REGISTER

SPACE

DVS

DAC

FBAN

FBBP

Buck B

OUT

nIRQ

2x 0.22µH

VDDIO

CTRL

+

2/4-WIRE INTERFACE

PoL

DRIVE

100nF

2x 47µF

VSS_ANA

DVS

DAC

FBBN

Figure 2: DA9224-A System Diagram

Datasheet

Revision 2.6

23-Apr-2021

CFR0011-120-00

2 of 60

DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

Contents

General Description ............................................................................................................................ 1

Key Features ........................................................................................................................................ 1

Applications ......................................................................................................................................... 1

System Diagrams ................................................................................................................................ 2

1

2

3

4

5

6

7

Terms and Definitions................................................................................................................... 5

Pinout ............................................................................................................................................. 6

Absolute Maximum Ratings ......................................................................................................... 9

Recommended Operating Conditions......................................................................................... 9

Electrical Characteristics ........................................................................................................... 11

Efficiency Measurements ........................................................................................................... 17

Functional Description ............................................................................................................... 19

7.1 DC-DC Buck Converter....................................................................................................... 21

7.1.1

7.1.2

7.1.3

7.1.4

7.1.5

7.1.6

Switching Frequency ........................................................................................... 22

Operation Modes and Phase Selection............................................................... 22

Output Voltage Selection..................................................................................... 23

Soft Start Up ........................................................................................................ 24

Current Limit ........................................................................................................ 24

Variable VOUT above 1.57 V .............................................................................. 24

7.2 Ports Description................................................................................................................. 26

7.2.1

7.2.2

7.2.3

7.2.4

VDDIO.................................................................................................................. 26

IC_EN .................................................................................................................. 26

nIRQ..................................................................................................................... 26

GPIO Extender .................................................................................................... 27

7.3 Operating Modes................................................................................................................. 29

7.3.1

7.3.2

ON Mode ............................................................................................................. 29

OFF Mode............................................................................................................ 29

7.4 Control Interfaces................................................................................................................ 29

7.4.1

7.4.2

7.4.3

4-WIRE Communication ...................................................................................... 29

2-WIRE Communication ...................................................................................... 33

Details of the 2-WIRE Control Bus Protocol........................................................ 34

7.5 Internal Temperature Supervision....................................................................................... 36

8

Register Definitions .................................................................................................................... 37

8.1 Register Map....................................................................................................................... 37

8.2 Register Definitions............................................................................................................. 39

8.2.1

8.2.2

8.2.3

8.2.4

8.2.5

Register Page Control ......................................................................................... 39

Register Page 0................................................................................................... 39

Register Page 1................................................................................................... 44

Register Page 2................................................................................................... 49

Register Page 4................................................................................................... 55

9

Application Information.............................................................................................................. 56

9.1 Capacitor Selection............................................................................................................. 56

9.2 Inductor Selection ............................................................................................................... 57

10 Package Information................................................................................................................... 58

Datasheet

Revision 2.6

23-Apr-2021

CFR0011-120-00

3 of 60

DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

10.1 Package Outlines................................................................................................................ 58

10.2 Package Marking ................................................................................................................ 59

11 Ordering Information .................................................................................................................. 59

Figures

Figure 1: DA9223-A System Diagram................................................................................................... 2

Figure 2: DA9224-A System Diagram................................................................................................... 2

Figure 3: 66 TFBGA 0.8 mm Pitch Ball Map ......................................................................................... 6

Figure 4: 66 TFBGA 0.8 mm Pitch Power Derating Curve.................................................................. 10

Figure 5: 2-WIRE Bus Timing.............................................................................................................. 16

Figure 6: 4-WIRE Bus Timing.............................................................................................................. 16

Figure 7: DA9223-A Efficiency vs Load, V_OUT= 1.0 V, 0-16 A............................................................ 17

Figure 8: DA9223-A Efficiency vs Load, V_IN= 3.6 V, 0-16 A............................................................... 17

Figure 9: DA9224-A Efficiency vs Load, V_OUT= 1.0 V, 0-8 A.............................................................. 18

Figure 10: DA9224-A Efficiency vs Load, V_IN= 3.6 V, 0-8 A............................................................... 18

Figure 11: Interface of DA9223-A/24-A with DA9063 and the Host Processor................................... 19

Figure 12: Typical Application of DA9223-A........................................................................................ 20

Figure 13: Typical Application of DA9224-A........................................................................................ 21

Figure 14: Concept of Control of the Buck’s Output Voltage .............................................................. 23

Figure 15: Resistive Divider from VOUT to FBAN .............................................................................. 24

Figure 16: GPIO Principle of Operation (Example Paths)................................................................... 28

Figure 17: Schematic of 4-WIRE and 2-WIRE Power Manager Bus .................................................. 30

Figure 18: 4-WIRE Host Write and Read Timing (nCS_POL = ‘0’, CPOL = ‘0’, CPHA = ‘0’) ............. 31

Figure 19: 4-WIRE Host Write and Read Timing (nCS_POL= ‘0’, CPOL = ‘0’, CPHA = ‘1’) .............. 31

Figure 20: 4-WIRE Host Write and Read Timing (nCS_POL = ‘0’, CPOL = ‘1’, CPHA = ‘0’) ............. 32

Figure 21: 4-WIRE Host Write and Read Timing (nCS_POL = ‘0’, CPOL = ‘1’, CPHA = ‘1’) ............. 32

Figure 22: Timing of 2-WIRE START and STOP Condition................................................................ 34

Figure 23: 2-WIRE Byte Write (SDA Line) .......................................................................................... 34

Figure 24: Examples of 2-WIRE Byte Read (SDA Line) ..................................................................... 35

Figure 25: Examples of 2-WIRE Page Read (SDA Line).................................................................... 35

Figure 26: 2-WIRE Page Write (SDA Line) ......................................................................................... 35

Figure 27: 2-WIRE Repeated Write (SDA Line).................................................................................. 36

Figure 28: DA9223-A/24-A 66 TFBGA 0.8 mm Pitch Package Outline Drawing................................ 58

Tables

Table 1: Pin Description ........................................................................................................................ 7

Table 2: Pin Type Definition .................................................................................................................. 8

Table 3: Absolute Maximum Ratings..................................................................................................... 9

Table 4: Recommended Operating Conditions ..................................................................................... 9

Table 5: Buck Converters Characteristics........................................................................................... 11

Table 6: IC Performance and Supervision .......................................................................................... 13

Table 7: Digital I/O Characteristics...................................................................................................... 14

Table 8: 2-WIRE Control Bus Characteristics ..................................................................................... 15

Table 9: 4-WIRE Control Bus Characteristics ..................................................................................... 16

Table 10: 4-WIRE Clock Configurations.............................................................................................. 30

Table 11: 4-WIRE Interface Summary ................................................................................................ 33

Table 12: Over-Temperature Thresholds............................................................................................ 36

Table 13: Register Map ....................................................................................................................... 38

Table 14: Recommended Capacitor Types......................................................................................... 56

Table 15: Recommended Inductor Types ........................................................................................... 57

Table 16: Package Marking................................................................................................................. 59

Table 17: Ordering Information ........................................................................................................... 59

Datasheet

Revision 2.6

23-Apr-2021

CFR0011-120-00

4 of 60

DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

1

Terms and Definitions

AP

Application Processor

Central Processing Unit

Dual Data Rate

CPU

DDR

DVC

FET

GPI

Dynamic Voltage Control

Field Effect Transistor

General Purpose Input

Graphic Processing Unit

Integrated Circuit

GPU

IC

OTP

PCB

PMIC

POL

PWM

One Time Programmable memory

Printed Circuit Board

Power Management Integrated Circuit

Point Of Load

Pulse Width Modulation

Datasheet

Revision 2.6

23-Apr-2021

CFR0011-120-00

5 of 60

DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

2

Pinout

Figure 3: 66 TFBGA 0.8 mm Pitch Ball Map

Datasheet

Revision 2.6

23-Apr-2021

CFR0011-120-00

6 of 60

DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

Table 1: Pin Description

Type

Signal

Name

Second

Function

Pin Name

Description

(See Table 2)

B1, B2, B3, B4

E1, E2, E3, E4

B8, B9, B10, B11

E8, E9, E10, E11

LX_A1

LX_A2

LX_B1

LX_B2

AO

Switching node for Buck A phase 1

Switching node for Buck A phase 2

Switching node for Buck B phase 1

Switching node for Buck B phase 2

Supply voltage for Buck A phase 1

To be connected to VSYS

A1, A2, A3, A4

F1, F2, F3, F4

VDD_A1

VDD_A2

VDD_B1

VDD_B2

PS

Supply voltage for Buck A phase 2

To be connected to VSYS

Supply voltage for Buck B phase 1

To be connected to VSYS

A8, A9, A10, A11

F8, F9, F10, F11

Supply voltage for Buck B phase 2

To be connected to VSYS

F7

D7

E7

B6

C6

IC_EN

nIRQ

DI

Integrated Circuit (IC) Enable Signal

Interrupt line towards the host

I/O Voltage Rail

DO

PS

AI

VDDIO

FBAP

FBAN

Positive sense node for Buck A

Negative sense node for Buck A

AI

Positive sense node for Buck B of

DA9224-A

FBBP

NC

AI

D6

E6

AO

AI

Do not connect for DA9223-A

Negative sense node for Buck B of

DA9224-A

FBBN

NC

AO

Do not connect for DA9223-A

General purpose input, input track

General purpose input

A7

B7

B5

GPI0

GPI1

GPIO2

TRK

DI/AI

DI

DIO

General purpose input/output

2-WIRE data, 4-WIRE data

input/output

A5

A6

D5

SDA

SCL

nCS

SI

DIO

DI

SK

2-WIRE clock, 4-WIRE clock

4-WIRE chip select, general purpose

input

GPI4

DI

4-WIRE data output, general

purpose input/output

C7

C5

F6

SO

GPIO3

DIO

AO

PS

Regulated supply for internal

circuitry. Decouple with 150 nF (or

220 nF)

VDDCORE

VSYS

Supply for IC and input for voltage

supervision

E5

F5

VSS

VSS_ANA

Datasheet

Revision 2.6

23-Apr-2021

CFR0011-120-00

7 of 60

DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

Type

Signal

Name

Second

Function

Pin Name

Description

(See Table 2)

C1, C2, C3, C4,

D1, D2, D3, D4,

C8, C9, C10, C11,

D8, D9, D10, D11

VSS_A1,

VSS_A2

VSS_B1

VSS_B2

VSS

Connect together

Table 2: Pin Type Definition

Pin Type

DI

Description

Pin Type

AI

Description

Digital Input

Analogue Input

Analogue Output

Analogue Input/Output

Ground

DO

Digital Output

Digital Input/Output

Power Supply

AO

DIO

AIO

PS

VSS

Datasheet

Revision 2.6

23-Apr-2021

CFR0011-120-00

8 of 60

DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

3

Absolute Maximum Ratings

Table 3: Absolute Maximum Ratings

Parameter Description Conditions (Note 1)

Min

-65

-40

-0.3

Typ

Max

+150

6.0

Unit

°C

V

T_STG

T_J

Storage temperature

Junction temperature

Limiting supply voltage

V_{DD_LIM}

V_DD+ 0.3

(max 6.0)

Limiting voltage at all

pins except above

V_PIN

-0.3

V

Electrostatic discharge

voltage

V_{ESD_HBM}

Human Body Model

2

kV

Note 1 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the

device. These are stress ratings only, so functional operation of the device at these or any other

conditions beyond those indicated in the operational sections of the specification are not implied.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

4

Recommended Operating Conditions

Table 4: Recommended Operating Conditions

Parameter Description Conditions (Note 1)

Min

Typ

Max

Unit

V_DD

Supply voltage

2.8

5.5

V

Operating junction

temperature

T_{J_OP}

T_A

-40

1.2

125

105

°C

V

Ambient temperature

Input/output supply

voltage

3.6

(Note 2)

V_DDIO

TFBGA 0.8 mm pitch

Derating factor above

T_A= 70 °C: 29.3 mW/°C

Total power dissipation

(Note 3)

P_TOT

1620

34.2

mW

Thermal resistance

junction to ambient

TFBGA 0.8 mm pitch

°C/W

_JA

(Note 3)

Note 1 Within the specified limits, a lifetime of 10 years is guaranteed. If operating outside of these

recommended conditions, please consult with Dialog Semiconductor.

Note 2 V_DDIOis not allowed to be higher than V_DD

.

Note 3 Obtained from measurement on a 6-layer evaluation board. Influenced by PCB technology and layout.

Datasheet

Revision 2.6

23-Apr-2021

CFR0011-120-00

9 of 60

DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

P_D= (T_J- T_A) / θ_JA

θ_JA= 34.2 °C/W

Still air (0 m/s)

▲T_J(WARN)= 125 °C

◆T_J(CRIT)= 140 °C

20

30

40

50

60

70

80

90 100 110 120 130 140

T_A(°C)

Figure 4: 66 TFBGA 0.8 mm Pitch Power Derating Curve

Datasheet

Revision 2.6

23-Apr-2021

CFR0011-120-00

10 of 60

DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

5

Electrical Characteristics

Unless otherwise noted, the following is valid for T_J= -40 to +125 ºC, V_DD= 2.8 V to 5.5 V,

C_OUT= 47 μF per phase, local sensing.

Table 5: Buck Converters Characteristics

Parameter Description

Conditions

Min

Typ

Max

Unit

External Component Electrical Conditions

Output capacitance (per

phase)

Including voltage and

temperature coefficient

C_OUT

23

47

62

10

µF

Equivalent series resistance

(per phase)

ESR_COUT

f > 100 kHz

mΩ

Including current and

temperature dependence

L_PHASE

Inductance (per phase)

0.11

0.22

0.29

100

µH

DCR_LPHASEInductor resistance

mΩ

Electrical Characteristics

V_DD

Supply voltage

VDD_x = VSYS

I_O= 0 to I_{O_MAX}

2.8

0.3

5.5

V

V_BUCK

Buck output voltage (Note 1)

1.57

Incl. static line/load reg

and voltage ripple

-2.0

+2.0

%

V_BUCK≥ 1 V

Incl. static line/load reg

and voltage ripple

±20

mV

Output voltage accuracy

PWM mode

V_OACC

V_BUCK< 1 V

V_BUCK= 1 V

V_DD= 3.8 V

no load

-1.0

-0.5

+1.0

+0.5

%

V_BUCK= 1 V

V_DD= 3.8 V

no load

T_A= 27 ºC

DA9223-A

I_O= 0 to 5 A, tr = 500 ns

PWM 4-phase

V_BUCK≥ 1 V

V_{TR_LOAD}

Load regulation transient

voltage

±2

%

(Note 2)

V_BUCK< 1 V

±20

mV

DA9223-A

IO = 0 to 5 A, tr = 500 ns

auto mode, ph shedding

V_BUCK= 1 V

±3.5

15

%

DA9224-A

Load regulation transient

voltage

I_O= 0 to 5 A, tr = 500 ns

PWM 2-phase

V_BUCK= 1 V

(Note 2)

V_DD= 3 to.3.6 V

dt =10 µs

Line regulation transient

voltage

V_{TR_LINE}

mV

mA

I_O= IO(MAX)/2

I_{O_MAX}

Maximum output current

Per phase

4000

Datasheet

Revision 2.6

23-Apr-2021

CFR0011-120-00

11 of 60

DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

Parameter Description

Minimum current limit

Conditions

Min

Typ

Max

Unit

BUCKA_ILIM

BUCKB_ILIM

= 0000

I_{LIM_MIN}

per phase (programmable)

(Note 3)

-20%

4000

20%

mA

BUCKA_ILIM

BUCKB_ILIM

= 1111

Maximum current limit

I_{LIM_MAX}

-20%

7000

20%

mA

per phase (programmable)

(Note 3)

Per phase

No load

Quiescent current

synchronous rectification

mode

I_{Q_PWM}

17

3

mA

V_DD= 3.7 V

f_SW

Switching frequency

MHz

V_OUT= 1.0 V

BUCKA_UP_CTRL

50

(Note 4)

t_STUP

Startup time

µs

BUCKB_UP_CTRL

= 100

For each phase at the LX

node at 0.5 V,

R_{O_PD}

Output pull-down resistance

PMOS on-resistance

150

29

200

Ω

(see BUCKx_PD_DIS)

Incl. pin and routing

V_DD= 3.7 V

R_{ON_PMOS}

mΩ

per phase

Incl. pin and routing

V_DD= 3.7 V

R_{ON_NMOS}

NMOS on-resistance

21

per phase

PFM Mode

V_{BUCK_PFM}

Buck output voltage in PFM

I_O= 0 mA to I_{O_MAX}

0.3

2

1.57

V

Minimum output current in

PFM

Static output voltage,

no DVC

I_{MIN_PFM}

mA

DA9224-A quiescent current

Buck A enabled

No switching

V_DD= 3.7 V

(Note 5)

I_{Q_PFM_A2}

58

72

µA

DA9223-A quiescent current

Buck enabled

No switching

V_DD= 3.7 V

(Note 5)

I_{Q_PFM_A4}

DA9224-A quiescent current

Buck A enabled

No switching

V_DD= 3.7 V

(Note 5)

I_{Q_PFM_A2B2}

106

µA

Buck B enabled

Note 1 Programmable in 10 mV increments.

Note 2 Additional to the dc accuracy. Inductor value 0.22 uH. The value is measured directly at C_OUT(EXT). In

case of remote sensing, parasitics of PCB and external components may affect this value.

Note 3 On-time > 50 ns.

Datasheet

Revision 2.6

23-Apr-2021

CFR0011-120-00

12 of 60

DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

Note 4 Time from beginning to end of the voltage ramp. Additional 10 µs typical delay, plus internal sync to

the enable port.

Note 5 For the total quiescent current of the IC, the I_{DD_ON}should be added.

Table 6: IC Performance and Supervision

Parameter

Description

Conditions

Min

Typ

Max

Unit

IC_EN = 0

T_A= 27 °C

I_{DD_OFF}

Off state supply current

0.1

1

µA

IC_EN = 1

Buck A/B off

T_A= 27 °C

I_{DD_ON}

On state supply current

14

µA

Power good threshold

voltage

V_{TH_PG}

referred to VBUCK

-50

50

mV

Power good hysteresis

voltage

V_{HYS_PG}

BUCK_EN = 0

BUCK_EN = 1

2.0

V

Under voltage lockout

threshold at VDD

V_{TH_UVLO_VDD}

2.55

Under voltage lockout

threshold at VDDIO

V_{TH_UVLO_IO}

V_{HYS_UVLO_IO}

T_{TH_WARN}

T_{TH_CRIT}

T_{TH_POR}

1.315

1.45

70

1.55

V

mV

°C

Under voltage lockout

hysteresis at VDDIO

Thermal warning

threshold temperature

110

125

135

-7%

125

140

150

6.0

140

155

165

+7%

Thermal critical

threshold temperature

ºC

Thermal power on reset

threshold temperature

°C

Internal oscillator

frequency

f_OSC

MHz

Datasheet

Revision 2.6

23-Apr-2021

CFR0011-120-00

13 of 60

DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

Table 7: Digital I/O Characteristics

Parameter

Description

Conditions

Min

Typ

Max

Unit

HIGH level input voltage

at pin IC_EN

V_{IH_EN}

1.1

V

LOW level input voltage

at pin IC_EN

V_{IL_EN}

t_EN

R_{O_PU_GPO}

0.35

V

Enable time

I/F operating

750

100

µs

V_DDIO= 1.8 V

V_GPO= 0 V

Pull up resistor at GPO

k

V_DDIO= 1.8 V

V_GPI= VDDIO

R_{I_PD_GPI}

Pull down resistor at GPI

150

GPI0-4, SCL, SDA,

(2-WIRE mode)

VDDCORE mode

VDDIO mode

1.75

V_IH

0.7*V_DDIO

V

HIGH level input voltage

GPI0-4, SCL, SDA,

(2-WIRE mode)

VDDCORE mode

VDDIO mode

0.75

V_IL

0.3*V_DDIO

LOW level input voltage

SK, nCS, SI

V_{IH_4WIRE}

(4-WIRE Mode)

0.7*V_DDIO

HIGH level input voltage

SK, nCS, SI

V_{IL_4WIRE}

(4-WIRE Mode)

LOW level input voltage

0.3*V_DDIO

GPO2-3, SO (4-WIRE

mode)

push-pull mode

at 1 mA

V_OH

0.8*V_DDIO

V

HIGH level output

voltage

V_DDIO≥ 1.5 V

GPO2-3, SDA (2-WIRE

mode) SO (4-WIRE

mode)

V_OL1

0.3

LOW level output voltage

at I_OL= 1 mA

SDA (2-WIRE Mode)

V_OL3

0.24

0.4

V

LOW level output voltage

at I_OL= 3 mA

SDA (2-WIRE Mode)

V_OL20

LOW level output voltage

at I_OL= 20 mA

CLK, SDA

C_IN

(2-WIRE Mode)

input capacitance

2.5

10

pF

ns

CLK, SDA

Fast/Fast+ mode

High Speed mode

0

50

10

(2-WIRE Mode)

t_SP

spike suppression pulse

width

Fast at C_B< 550 pF

20+0.1 C_B

120

80

Fall time of SDA signal

(2-WIRE Mode)

HS at 10 < C_B<100

pF

t_fDA

10

20

ns

160

HS at C_B< 400 pF

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Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

Table 8: 2-WIRE Control Bus Characteristics

Parameter

Description

Conditions

Min

Typ

Max

Unit

Bus free time from

STOP to START

condition

t_BUF

0.5

µs

Bus line capacitive

load

C_B

150

pF

Standard/Fast/Fast+ Mode

Clock frequency at pin

SCL

0

f_SCL

1000

kHz

µs

(Note 1)

START condition set-

up time

t_{SU_STA}

t_{H_STA}

0.26

START condition hold

time

µs

t_{W_CL}

t_{W_CH}

Clock LOW duration

Clock HIGH duration

0.5

µs

0.26

Rise time

t_R

Input requirement

1000

300

ns

at pin CLK and DATA

Fall time

t_F

at pin CLK and DATA

t_{SU_D}

t_{H_D}

Data set-up time

Data hold time

50

0

ns

High Speed Mode

Clock frequency at pin

SCL

0

f_{SCL_HS}

3400

kHz

ns

(Note 1)

START condition set-

up time

t_{SU_STA_HS}

t_{H_STA_HS}

160

START condition hold

time

ns

t_{W_CL_HS}

t_{W_CH_HS}

Clock LOW duration

Clock HIGH duration

160

60

ns

Rise time

t_{R_HS}

Input requirement

160

ns

at pin CLK and DATA

Fall time

t_{F_HS}

at pin CLK and DATA

t_{SU_D_HS}

t_{H_D_HS}

Data set-up time

Data hold time

10

0

ns

STOP condition set-

up time

t_{SU_STO_HS}

160

ns

Note 1 Minimum clock frequency is 10 kHz if 2WIRE_TO is enabled.

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Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

Figure 5: 2-WIRE Bus Timing

Table 9: 4-WIRE Control Bus Characteristics

Parameter

Description

Label in Plot

Min

Typ

Max

Unit

pF

Bus line capacitive

load

C_B

100

t_C

Cycle time

1

70

20

ns

2, from CS active to first

SK edge

t_{SU_CS}

Chip select setup time

ns

3, from last SK edge to

CS idle

t_{H_CS}

Chip select hold time

20

ns

t_{W_CL}

t_{W_CH}

t_{SU_SI}

t_{H_SI}

Clock LOW duration

Clock HIGH duration

Data input setup time

Data input hold time

Data output valid time

Data output hold time

4

5

6

7

8

9

0.4 x t_C

10

ns

10

t_{V_SO}

t_{H_SO}

22

6

Chip select HIGH

duration

t_{W_CS}

10

20

ns

(2) t_{SU_CS}

(3) t_{H_CS}(10) t_{W_CS}

70%

nCS

30%

(5) t_{W_CH}

(4) t_{W_CL}

(1) t_C

70%

30%

SK

SI

(7) t_{H_SI}

(6) t_{SU_SI}

70%

30%

(8) t_{V_SO}

(9) t_{H_SO}

70%

30%

SO

Figure 6: 4-WIRE Bus Timing

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Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

6

Efficiency Measurements

The efficiency measurements for DA9223-A and DA9224-A (in TFBGA 0.8 mm pitch package) are shown with

phase shedding enabled in each plot and were measured using 2520 size inductor with typ. 8 mΩ DCR.

Figure 7: DA9223-A Efficiency vs Load, V_OUT= 1.0 V, 0-16 A

Figure 8: DA9223-A Efficiency vs Load, V_IN= 3.6 V, 0-16 A

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DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

Figure 9: DA9224-A Efficiency vs Load, V_OUT= 1.0 V, 0-8 A

Figure 10: DA9224-A Efficiency vs Load, V_IN= 3.6 V, 0-8 A

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Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

7

Functional Description

Flexible configurability and the availability of different control schemes make both DA9223-A and

DA9224-A the ideal single/dual buck companion ICs to expand the existing capabilities of a system

PMIC such as DA9063.

Due to the advanced compatibility between both DA9223-A and DA9224-A and the DA9063, they

offer several advantages when they are operated together. These advantages include:

●

DA9223-A and DA9224-A can be enabled and controlled by DA9063 during the power up

sequence, thanks to DA9063’s dedicated output signals during power-up, and compatible input

controls in both DA9223-A and DA9224-A.

●

DA9223-A and DA9224-A can be used in a completely transparent way for the host processor

and can share the same Control Interface (same SPI chip select or I²C address), thanks to the

compatible registers map. DA9223-A and DA9224-A have a dedicated register space for

configuration and control which doesn’t conflict with DA9063.

●

DA9223-A and DA9224-A support a power-good configurable port for enhanced communication

to the host processor and improved power-up sequencing.

DA9223-A and DA9224-A can both share the same interrupt line with DA9063.

In addition, the 2-WIRE / 4-WIRE interfaces allow DA9223-A and DA9224-A to fit to many standard

PMU parts and power applications.

Vdd

nIRQ

nSHUTDOWN

SYS_EN

nOFF

PWR_EN

Host

Processor

PWR1_EN

OUT_32K

nRESET

nONKEY

LID

DA9063

GPIOs

VCharger

Control IF

GPIO9

IC_EN

Control IF

DA9223-A/

DA9224-A

nIRQ

GPI1 (voltage set)

GPI0 (enable)

Figure 11: Interface of DA9223-A/24-A with DA9063 and the Host Processor

As shown in Figure 11, a typical application case includes a host processor, a main PMIC (for

example, DA9063) and DA9223-A or DA9224-A used as companion IC for the high power core

supply.

The easiest way of controlling DA9223-A and DA9224-A is through the Control Interface. The master

initiating the communication must always be the host processor that reads and writes to the main

PMIC, and to the DA9223-A and DA9224-A registers. To poll the status of DA9223-A or DA9224-A,

the host processor must access the dedicated register area through the Control Interface. DA9223-A

and DA9224-A can additionally be controlled by means of hardware inputs.

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Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

CORE

VDDIO

DA9223-A

SCL

SDA

nIRQ

VSEL (GPI1)

EN (GPI0)

LP_MODE

DA9063

(PMIC)

IC_EN

GPIO9 (seq)

VIN

VDD_A1

VDD_A2

VDD_B1

VDD_B2

SENSE+

LX_A1

LX_A2

CPU /

GPU /

DDR

VSYS

LX_B1

LX_B2

VSS_ANA

SENSE-

VDDIO

FBAP

FBAN

I2C_ADDR_SEL (GPI4)

Power Good (GPIO3)

Ext Supply

Figure 12: Typical Application of DA9223-A

Figure 12 shows a typical use case of DA9223-A for the supply of CPU, GPU, or DDR rails. The IC is

enabled and disabled by the main PMIC via IC_EN port as part of its sequencer. Once the IC is

enabled, the CORE application processor enables the buck converter with the EN1 signal and

manages the output voltage selection with the VSEL signal.

The VSEL signal can be shared between the main PMIC and the DA9223-A. Three GPI/GPIOs

embedded in DA9223-A are used in this case:

●

GPIO2 signals the insertion of an external charger in the application (through interrupt to the host

processor)

GPIO3 indicates a power-good-condition, either to proceed with the power up sequence or to

enable an external supply connected to the port

GPI4 is used for the I²C interface address hardware selection

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DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

DA9224-A

VDDIO

CORE

SCL

SDA

nIRQ

EN_A (GPI0)

EN_B (GPI1)

VIN

VDD_A1

VDD_A2

VDD_B1

VDD_B2

SENSE+

CPU/

GPU

LX_A1

LX_A2

SENSE-

VSYS

FBAP

FBAN

VSS_ANA

SENSE+

DDR

LX_B1

LX_B2

(LX_A3 in DA9215)

SENSE-

VDDIO

FBBP

FBBN

I2C_ADDR_SEL (GPI4)

IC_EN

VSYS

Figure 13: Typical Application of DA9224-A

Figure 13 shows a typical use case of DA9224-A for the simultaneous supply of a CPU and a GPU

rail. The IC is always enabled because IC_EN is shorted to the battery voltage. The CORE

application processor enables and disables the CPU/GPU and the DDR individually via dedicated

ports on DA9224-A.

7.1 DC-DC Buck Converter

DA9223-A is a four-phase 16 A high efficiency synchronous step-down DVC regulator, operating at a

high frequency of typically 3 MHz. It supplies an output voltage of typically 1.0 V for a CPU rail,

configurable in the range 0.3 – 1.57 V, with high accuracy in steps of 10 mV.

DA9224-A contains two buck converters, Buck A and Buck B, each capable of delivering 8 A.

To improve the accuracy of the delivered voltage, each buck converter can support a differential se

nsing of the configured voltage directly at the point of load via dedicated positive and negative sense

pins.

Both Buck A and Buck B have two voltage registers each. One defines the normal output voltage,

while the other offers an alternative retention voltage. In this way different application power modes

can easily be supported. The voltage selection can be operated either via GPI or via control interface

to guarantee the maximum flexibility according to the specific host processor status in the

application.

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Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

When a buck is enabled, its output voltage is monitored and a power-good signal indicates that the

buck output voltage has reached a level higher than the VTH(PG) threshold. The power-good is lost

when the voltage drops below VTH(PG) - VHYS(PG), which is the level at which the signal is de-

asserted. The power good signaling should not be used in conjunction with fast start up rates,

configured in BUCKx_UP_CTRL register fields and can be individually masked during DVC

transitions using the PGA_DVC_MASK and PGB_DVC_MASK bits. For each of the buck converters

the status of the power-good indicator can be read back via I²C from the PWRGOOD_A and

PWRGOOD_B status bits. It can be also individually assigned to either GPIO2 or GPIO3 using

BUCKA_PG_SEL and BUCKB_PG_SEL. For correct functionality, the GPIO ports need to be

configured as output. An I²C write in GPIOx_MODE can overwrite the internal configuration so that a

new update will be automatically done only when the internal power-good indicator changes status.

The buck converters are capable of supporting DVC transitions that occur:

●

When they are active and the selected A-voltage or B-voltage is updated to a new target value.

When the voltage selection is changed from the A-voltage to the B-voltage (or B-voltage to the

A-voltage) using VBUCKA_SEL and VBUCKB_SEL.

The DVC controller operates in Pulse Width Modulation (PWM) mode with synchronous rectification.

When the host processor changes the output voltage, the voltage transition of each buck converter

can be individually signaled with a READY signal routed to either GPIO2 or GPIO3. The port has to

be configured as GPO and selected for the functionality via READYA_CONF or READYB_CONF. In

contrast to the power-good signal, the READY only informs the host processor about the completion

of the digital DVC ramp without confirming that the target voltage has actually been reached.

The slew rate of the DVC transition is individually programmed for each buck converter at 10mV per

(4, 2, 1 or 0.5 µs) via control bit SLEW_RATE_A and SLEW_RATE_B.

The typical supply current in PWM mode is in the order of 17 mA per phase (quiescent current and

charge/discharge current) and drops to <1 µA when the buck is turned off.

When the buck is disabled, a pull-down resistor (typically 150 Ω) for each phase is activated

depending on the value stored in register bits BUCKA_PD_DIS and BUCKB_PD_DIS. Phases

disabled using PHASE_SEL_A and PHASE_SEL_B will not have any pull-down. The pull-down

resistor is always disabled at all phases when DA9223-A and DA9224-A are OFF.

7.1.1

Switching Frequency

The switching frequency is chosen to be high enough to allow the use of a small 0.22 µH inductor

(see a complete list of coils in the Application Information, Section 9). The buck switching frequency

can be tuned using register bit OSC_TUNE. The internal 6 MHz oscillator frequency is tuned in steps

of 180 kHz. This impacts the buck converter frequency in steps of 90 kHz and helps to mitigate

possible disturbances to other HF systems in the application.

7.1.2

Operation Modes and Phase Selection

The buck converters can operate in synchronous PWM mode and PFM mode. The operating mode is

selected using register bits BUCKA_MODE and BUCKB_MODE.

An automatic phase shedding can be enabled for each buck converter in PWM mode via

EF PH_SH_EN_A \h \* MERGEFORMAT PH_SH_EN_A, PH_SH_EN_B, thereby automatically

reducing or increasing the number of active phases depending on the output load current. For

DA9224-A the phase shedding will automatically change between 1-phase and 2-phase operation at

a typical current of 2.0 A. For DA9223-A the phase shedding will automatically change between 1-

phase and 4-phase operation at a typical current of 2.5 A. The PHASE_SEL_A and PHASE_SEL_B

register fields limit the maximum number of active phases under any conditions.

If the automatic operation mode is selected on BUCKA_MODE or BUCKB_MODE, the buck

converters will automatically change between synchronous PWM mode and PFM depending on the

load current. This improves the efficiency of the converters across the whole range of output load

currents.

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DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

7.1.3

Output Voltage Selection

The switching converter can be configured using either a 2-WIRE or a 4-WIRE interface. For security

reasons, the re-programming of registers that can cause damage when wrongly programmed (for

example, the voltage settings) can be disabled by asserting the control V_LOCK. When V_LOCK is

asserted, reprogramming the registers 0xD0 to 0x14F from control interfaces is disabled.

For each buck converter two output voltages can be pre-configured inside registers VBUCKA_A and

VBUCKB_A, and registers VBUCKA_B and VBUCKB_B. The output voltage can be selected by

either toggling register bits VBUCKA_SEL and VBUCKB_SEL or by re-programming the selected

voltage control register. Both changes will result in ramped voltage transitions, during which the

READY signal is asserted. After being enabled, the buck converter will by default use the register

settings in VBUCKA_A and VBUCKB_A unless the output voltage selection is configured via the GPI

port.

If “00” has been selected in BUCKA_MODE or BUCKB_MODE, A-/B- voltage selection registers

VBUCKx_x control the operation of the PWM and PFM modes.

Regardless of the values programmed in the VBUCKx_A and VBUCKx_B registers, the registers

VBUCKA_MAX, VBUCKB_MAX will individually limit the maximum output voltage that can be set for

each of the buck converters.

The buck converter provides an optional hardware enable/disable via selectable GPI, and configured

via control register bits BUCKA_GPI and BUCKB_GPI. A change of the output voltage controlled by

the state of a GPI is enabled via control register bits VBUCKA_GPI and VBUCKB_GPI. A rising or

falling edge at the related GPI, DA9223-A and DA9224-A will configure the buck converters

according to the status of the GPI.

In addition to selecting between the A/B voltages, a track mode can be activated for Buck A to set the

output voltage. In the DA9223-A, the track mode is applied to the 4-phase buck converter. This

feature can be enabled on GPI0 via GPI0_PIN. The output voltage will be configured to follow the

voltage applied at a selected GPI pin. The voltage applied at GPI0 must be in the same range as the

nominal output voltage selectable for the buck rail (see VBUCKA_A and VBUCKA_B registers). In

Track Mode, only single ended remote sensing is possible.

In Track Mode, the content of the VBUCKA_SEL bit is ignored, as well as VBUCKA_A and

VBUCKA_B bits. They will become active again once the voltage track mode is disabled. The GPI0

does not generate any event in this case.

Figure 14: Concept of Control of the Buck’s Output Voltage

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DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

7.1.4

Soft Start Up

To limit in-rush current from VSYS, the buck converters can perform a soft-start after being enabled.

The start-up behavior is a compromise between acceptable inrush current from the battery and

turn-on time. In DA9223-A and DA9224-A different ramp times can be individually configured for

each buck converter on register BUCKA_UP_CTRL and BUCKB_UP_CTRL. Rates higher than 20

mV/µs may produce overshoot during the start-up phase, so they should be considered carefully. It is

also recommended to place a decoupling capacitor on the feedback lines if slow ramp-up slew rate;

slower than 2.5 mV/µs is used.

A ramped power-down can be selected on register bits BUCKA_DOWN_CTRL and

BUCKB_DOWN_CTRL. When no ramp is selected, the output node will only be discharged by the

pull-down resistor, if enabled via BUCKA_PD_DIS and BUCKB_PD_DIS.

7.1.5

Current Limit

The integrated current limit is meant to protect DA9223-A and DA9224-A power stages and the

external coil from excessive current. The bucks’ current limit should be configured to be at least 40%

higher than the required maximum continuous output current.

When reaching the current limit, each buck converter generates an event and an interrupt to the host

processor unless the interrupt has been masked using the OCx_MASK controls. These OCA_MASK

and OCB_MASK control bits can be used to mask the generation of over-current events during DVC

transitions. An extra masking time as defined in OCx_MASK will be automatically added to the DVC

interval after the DVC has finished in order to ensure that the possible high current levels needed for

DVC do not influence the event generation.

7.1.6

Variable VOUT above 1.57 V

The whole product family is also available with an adjustable output voltage up to 4.3V. A resistive

divider from VOUT to FBAN (or FBBN) can be used to set the output voltage higher than 1.57 V, see

Figure 15.

The value of the output voltage VOUT is set by the selection of the resistive divider shown in

equation 1. The total resistance of the divider resistors (R1+R2) should be less than 40 k.

푅1

푉푂푈푇 = (1 + ) ∙ 푉푅퐸퐹

푅2

Equation 1

Figure 15: Resistive Divider from VOUT to FBAN

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DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

For example, to program the output voltage VOUT to 1.8 V, with VREF set to 1.2 V, suggest 10 kΩ

on R1 and 20 kΩ on R2.

Note 1 The resistors need to be properly selected since the output voltage accuracy will be directly affected

by any errors on the resistors. The voltage across FBAP and FBAN (VREF) is guaranteed, but not the

output voltage accuracy.

Note 2 For best accuracy and tracking R1 = R2 and VREF is adjusted to be 1/2 x Vout.

Note 3 Capacitor C1 is used to provide feed forward control to improve transient response. The value of C1

should be between 1 nF and 10 nF.

CAUTION

The followings are important notes that need to be considered before using resistive divider on DA9223-A

and DA9224-A:

1. Please contact your region's Dialog representative when adopting the resistive divider technique. Dialog

need to prepare a special OTP because incorrect OTP settings may result in a different output voltage

than expected.

2. The voltage difference between input voltage and output voltage needs to be:

above 1.2 V, VIN-VOUT > 1.2 V.

3. The total resistance (R1+R2) is less than 40 k.

4. It is recommended that the device is operated in PWM mode only.

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Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

7.2 Ports Description

This section describes the functionality of each input / output port.

7.2.1

VDDIO

VDDIO is an independent IO supply rail input to DA9223-A and DA9224-A that can be assigned to

the power manager interface and to the GPIOs (see control PM_IF_V and GPI_V). The rail

assignment determines the IO voltage levels and logical thresholds (see also the Digital I/O

Characteristics in Table 7).

An integrated under voltage lockout circuit for the VDDIO prevents internal errors by disabling the I²C

communication when the voltage drops below VULO_IO. In that case the buck converters are also

disabled and cannot be re-enabled (even via input port) until the VDDIO under-voltage condition has

been resolved. At the exit of the VDDIO under voltage condition an event E_UVLO_IO is generated

and the nIRQ line is driven active if the event is not masked.

The VDDIO under-voltage circuit monitors voltages relative to a nominal voltage of 1.8V. If a different

rail voltage is being used, the under-voltage circuit can be disabled via UVLO_IO_DIS.

Note that the maximum speed at 4-WIRE interface is only available if the selected supply rail is

greater than 1.6 V.

7.2.2

IC_EN

IC_EN is a general enable signal for DA9223-A and DA9224-A turning on and off the internal circuitry

(for example, the reference, the digital core, etc.). Correct control of this port has a direct impact on

the quiescent current of the whole application. A low level of IC_EN allows the device to reach the

minimum quiescent current. The voltage at this pin is continuously sensed by a dedicated analogue

circuit.

The host processor can begin to start communication with DA9223-A and DA9224-A through the

Control Interface and, for example to turn on the buck converters, a delay time of t_ENafter assertion

of the IC_EN pin. If the bucks are enabled via OTP (see BUCKA_EN and BUCKB_EN controls), they

will start up automatically after assertion of IC_EN.

The IC_EN activation threshold is defined with a built-in hysteresis to avoid glitching transitions that

take place with unstable rising or falling edges.

7.2.3

nIRQ

The nIRQ port indicates that an interrupt-causing event has occurred and that the event/status

information is available in the related registers. The nIRQ is an output signal that can either be

push-pull or open drain (selected via IRQ_TYPE). If an active high IRQ signal is required, it can be

achieved by asserting control IRQ_LEVEL (recommended for push-pull mode).

Examples of this type of information can be critical temperature and voltage, fault conditions, status

changes at GPI ports, and so forth. The event registers hold information about the events that have

occurred. Events are triggered by a status change at the monitored signals. When an event bit is set,

the nIRQ signal is asserted unless this interrupt is masked by a bit in the IRQ mask register. The

nIRQ will not be released until all event registers with asserted bits have been read and cleared. New

events that occur during reading an event register are held until the event register has been cleared,

ensuring that the host processor does not miss them.

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Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

7.2.4

GPIO Extender

DA9223-A and DA9224-A include a GPIO extender that offers up to five 5 V-tolerant general purpose

input/output ports. Each port is controlled via registers from the host processor.

The GPIO3 and GPI4 ports are pin-shared with the 4-WIRE Control Interface. For instance, if

GPIO3_PIN = 01, GPI4_PIN = 01 (Interface selected), the GPIO3 and GPI4 ports will be exclusively

dedicated to output and chip-select signaling for 4-WIRE purposes. If the alternative function is

selected, all GPIOs configuration as per registers 0x58 to 0x5A and 0x145 will be ignored.

GPIs are supplied from the internal rail VDDCORE or VDDIO (selected via GPI_V) and can be

configured to be active high or active low (selected via GPIOx_TYPE). The input signals can be

debounced or immediately change the state of the assigned status register GPIx to high or low,

according to the setting of GPIOx_MODE. The debouncing time is configurable via control

DEBOUNCE (10 ms default).

Whenever the status has changed to its configured active state (edge sensitive), the assigned event

register is set and the nIRQ signal is asserted (unless this nIRQ is masked, see also Figure 16).

Whenever DA9223-A and DA9224-A is enabled and enters ON mode (also when enabled changing

the setting of GPIOx_PIN) the GPI status bits are initiated towards their configured passive state.

This ensures that already active signals are detected, and that they create an event immediately after

the GPI comparators are enabled.

The buck enable signal (BUCKx_EN) can be controlled directly via a GPI, if so configured in the

BUCKA_GPI and BUCKB_GPI registers. If it is required that GPI ports do not generate an event

when configured for the HW control of the switching regulator, the relative mask bit should be set.

GPIs can alternatively be selected to toggle the VBUCKA_SEL and VBUCKB_SEL from rising and

falling edges at these inputs. Apart from changing the regulator output voltage this also provides

hardware control of the regulator mode (normal/low power mode) from the settings of BUCKA_SL_A,

BUCKA_SL_B, BUCKB_SL_A, and BUCKB_SL_B (enabled if BUCKA_MODE or BUCKB_MODE =

‘00’).

All GPI ports have the additional option of activating a 100 kΩ pull-down resistor via GPIOx_PUPD,

which ensures a well-defined level in case the input is not actively driven.

If enabled via ADDR_SEL_CONF, the I²C address selection can be assigned to a specific GPI. An

active voltage level at the selected GPI configures the slave address of DA9223-A and DA9224-A to

IF_BASE_ADDR1 while a passive voltage level configures the slave address to IF_BASE_ADDR2. If

no GPI is selected then the IF_BASE_ADDR1 is automatically used.

If defined as an output, GPIOs can be configured to be open-drain or push-pull. If configured as

push-pull, the supply rail is VDDIO. By disabling the internal 120 kΩ pull-up resistor in open-drain

mode, the GPO can also be supplied from an external rail. The output state will be assigned as

configured by the GPIO register bit GPIOx_MODE.

A specific power-good port for each of the buck converters can be configured via BUCKA_PG_SEL

and BUCKB_PG_SEL. The respective port must be configured as GPO for correct operation. If

assigned to the same GPO, it is necessary that the power-good indicators for Buck A and Buck B are

both active (supply voltages in range) to assert the overall power-good. The signal will be released

as soon as one of the single power-good signals is not active (that is, at least one supply is out of

range).

The power good signaling should not be used in conjunction with fast start up rates, configured in

BUCKx_UP_CTRL register fields.

Once enabled via RELOAD_FUNC_EN the GPI0 can be used as input port to operate a partial OTP

download. When the input level is changed to active, the registers 0x5D, 0x5E, 0xD1 to 0xDA are

updated to their OTP default. This allows a complete buck re-configuration that resets all the

changes done to those registers previously (soft reset). If the buck should be kept on during the soft

reset, the OTP values for the enable bits should be asserted because they are also part of the re-

load.

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DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

Whenever the GPIO unit is off (POR or OFF Mode) all ports are configured as open drain active high

(pass device switched off, high impedance state). When leaving POR the pull-up or pull-down

resistors will be configured from register GPIOx_PUPD.

Interrupt mask:

M_GPI0

Track Mode

Input

Reference

Buffer

GPI0_TYPE:

Active high/low

Buck

GPI0_MODE:

Debounce on/off

Status register

GPI0

Event register

Debounce

GPI

NOR

E_GPI0

Reset

Rising or

Falling edge

GPI0_PIN

GPI0_PUPD

nIRQ

Reserved

NOR

Reserved

Event register write

150 kΩ

Regulator

configure

BUCK_ EN

...

VBUCK_SEL

VDD_IO

4-WIRE

SO

Interrupt mask:

M_GPI3

GPIO3_TYPE:

Active high/low

GPIO3_MODE:

Debounce on/off

Interface

Status register

GPI3

Event register

Debounce

GPI

NOR

E_GPI3

Reset

Rising or

Falling edge

GPIO3_PIN

GPIO3_PUPD

VDD_IO

Event register write

GPIO3_PUPD

150 kΩ

100 kΩ

GPO (Open drain)

READY_EN

READY signal

asserted during

DVC

VDD_IO

GPO3_MODE:

0 or 1

GPO (Push-pull)

Figure 16: GPIO Principle of Operation (Example Paths)

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DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

7.3 Operating Modes

7.3.1

ON Mode

DA9223-A and DA9224-A are in ON Mode when the IC_EN port is higher than EN_ON and the

supply voltage is higher than V_{TH(UVLO)(VDD)}. Once enabled, the host processor can start the

communication with DA9223-A and DA9224-A via Control Interface after the t_ENdelay needed for

internal circuit start up.

If BUCKA_EN or BUCKB_EN is asserted when DA9223-A and DA9224-A are in ON Mode the power

up of the related buck converter is initiated. If the bucks are controlled via GPI, the level of the

controlling ports is checked when entering ON mode, so that an active level will immediately have

effect on the buck. If BUCKA_EN or BUCKB_EN are not asserted and all controlling GPI ports are

inactive, the buck converter will stay off with the output pull-down resistor enabled/disabled according

to the setting of BUCKA_PD_DIS and BUCKB_PD_DIS.

7.3.2

OFF Mode

DA9223-A and DA9224-A are in OFF Mode when the IC_EN port is lower than EN_OFF. In OFF

Mode, the bucks are always disabled and the output pull-down resistors are disabled independently

of BUCKA_PD_DIS and BUCKB_PD_DIS. All I/O ports of DA9223-A and DA9224-A are configured

as high impedance.

7.4 Control Interfaces

All the features of DA9223-A and DA9224-A can be controlled by SW through a serial control

interfaces. The communication is selectable to be either a 2-WIRE (I²C compliant) or a 4-WIRE

connection (SPI compliant) via control IF_TYPE, which will be selected during the initial OTP read. If

4-WIRE is selected, the GPIO3 and GPI4 are automatically configured as interface pins. Data is

shifted into or out of DA9223-A and DA9224-A under the control of the host processor, which also

provides the serial clock. In a normal application case the interface is only configured once from OTP

values, which are loaded during the initial start-up of DA9223-A and DA9224-A.

DA9223-A and DA9224-A react only on read/write commands where the transmitted register address

(using the actual page bits as a MSB address range extensions) is within 0x50 to 0x67, 0xD0 to DF,

0x140 to 0x14F and (read only) 0x200 to 0x27F. Host access to registers outside these ranges will

be ignored. This means there will be no acknowledge after receiving the register address in 2-WIRE

Mode, and SO stays HI-Z in 4-WIRE Mode. During debug and production modes write access is

available to page 4 (0x200 to 0x27F). DA9223-A and DA9224-A react only on write commands

where the transmitted register address is 0x00, 0x80, 0x100 to0x106. The host processor must read

the content of those registers before writing, thereby changing only the bit fields that are not marked

as reserved (the content of the read back comes from the compatible PMIC, for example DA9063).

If the STAND_ALONE bit is asserted (OTP bit), DA9223-A and DA9224-A also react to read

commands.

7.4.1

4-WIRE Communication

In 4-WIRE Mode the interface uses a chip-select line (nCS/nSS), a clock line (SK), data input (SI)

and data output line (SO).

The DA9223-A and DA9224-A register map is split into four pages that each contain up to 128

registers. The register at address zero on each page is used as a page control register. The default

active page after turn-on includes registers 0x50 to 0x6F. Writing to the page control register

changes the active page for all subsequent read/write operations unless an automatic return to page

0 was selected by asserting bit REVERT. Unless the REVERT bit was asserted after modifying the

active page, it is recommended to read back the page control register to ensure that future data

exchange is accessing the intended registers.

All registers outside the DA9223-A and DA9224-A range are write only, that is, the DA9223-A and

DA9224-A will not answer to a read command and the data bus is tri-state (they are implicitly

directed to DA9063). In particular the information contained in registers 0x105 and 0x106 is used by

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DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

DA9223-A and DA9224-A to configure the control interface. They must be the same as the main

PMIC (DA9063), so that a write to those registers configures both the main PMIC and DA9223-A and

DA9224-A at the same time. The default OTP settings also need to be identical for a correct

operation of the system.

The 4-WIRE interface features a half-duplex operation, that is, data can be transmitted and received

within a single 16-bit frame at enhanced clock speed (up to 14 MHz). It operates at the clock

frequencies provided by the host.

VDDIO

SK

Host

processor

VDDIO

SK

SI

SO

SI

PMIC

(slave)

Host

processor

VDDIO

SK

SI Peripheral

device

nCS/nSS

SCL

SDA

SO

nCS/nSS

PMIC

VDDIO

SK

4-WIRE interface

2-WIRE interface

SCL

SDA

Slave device

SI

SO

Peripheral

device

nCS/nSS

Figure 17: Schematic of 4-WIRE and 2-WIRE Power Manager Bus

A transmission begins when initiated by the host. Reading and writing is accomplished by the use of

an 8-bit command, which is sent by the host prior to the exchanged 8-bit data. The byte from the host

begins shifting in on the SI pin under the control of the serial clock SK provided from the host. The

first seven bits specify the register address (0x01 to 0x07) that will be written or read by the host. The

register address is automatically decoded after receiving the seventh address bit. The command

word ends with an R/W bit, which together with the control bit R/W_POL specifies the direction of the

following data exchange. During register writing the host continues sending out data during the

following eight SK clocks. For reading, the host stops transmitting and the 8-bit register is clocked out

of DA9223-A and DA9224-A during the consecutive eight SK clocks of the frame. Address and data

are transmitted with MSB first. The polarity (active state) of nCS is defined by control bit nCS_POL.

nCS resets the interface when inactive and it has to be released between successive cycles.

The SO output from DA9223-A and DA9224-A is normally in high-impedance state and active only

during the second half of read cycles. A pull-up or pull-down resistor may be needed at the SO line if

a floating logic signal can cause unintended current consumption inside other circuits.

Table 10: 4-WIRE Clock Configurations

Configurations

CPHA Clock

Polarity

CPOL Clock

Output Data is Updated at SK

Edge

Input Data is Registered at SK

Edge

Phase

0 (idle low)

1 (idle high)

0

1

0

1

Falling

Rising

Falling

Rising

Falling

Rising

DA9223-A and DA9224-A’s 4-WIRE interface offers two further configuration bits. Clock polarity

(CPOL) and clock phase (CPHA) define when the interface will latch the serial data bits. CPOL

determines whether SK idles high (CPOL = 1) or low (CPOL = 0). CPHA determines on which SK

edge data is shifted in and out. With CPOL = 0 and CPHA = 0, DA9223-A and DA9224-A latch data

on the SK rising edge. If the CPHA is set to 1 the data is latched on the SK falling edge. CPOL and

CPHA states allow four different combinations of clock polarity and phase. Each setting is

incompatible with the other three. The host and DA9223-A and DA9224-A must be set to the same

CPOL and CPHA states to communicate with each other.

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DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

4-WIRE WRITE

nCS

SK

A₆

A₅

A₄

A₃

A₂

A₁

A₀

R/Wn

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

SI

SO

4-WIRE READ

nCS

SK

SI

A₆

A₅

A₄

A₃

A₂

A₁

A₀

R/Wn

HI-Z

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

SO

latch data

Figure 18: 4-WIRE Host Write and Read Timing (nCS_POL = ‘0’, CPOL = ‘0’, CPHA = ‘0’)

4-WIRE WRITE

nCS

SK

SI

A₆

A₅

A₄

A₃

A₂

A₁

A₀

R/Wn

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

SO

4-WIRE READ

nCS

SK

SI

A₆

A₅

A₄

A₃

A₂

A₁

A₀

R/Wn

HI-Z

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

SO

latch data

Figure 19: 4-WIRE Host Write and Read Timing (nCS_POL= ‘0’, CPOL = ‘0’, CPHA = ‘1’)

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DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

4-WIRE WRITE

nCS

SK

A₆

A₅

A₄

A₃

A₂

A₁

A₀

R/Wn

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

SI

SO

4-WIRE READ

nCS

SK

SI

A₆

A₅

A₄

A₃

A₂

A₁

A₀

R/Wn

HI-Z

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

SO

latch data

Figure 20: 4-WIRE Host Write and Read Timing (nCS_POL = ‘0’, CPOL = ‘1’, CPHA = ‘0’)

4-WIRE WRITE

nCS

SK

SI

A₆

A₅

A₄

A₃

A₂

A₁

A₀

R/Wn

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

SO

4-WIRE READ

nCS

SK

SI

A₆

A₅

A₄

A₃

A₂

A₁

A₀

R/Wn

HI-Z

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

SO

latch data

Figure 21: 4-WIRE Host Write and Read Timing (nCS_POL = ‘0’, CPOL = ‘1’, CPHA = ‘1’)

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DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

Table 11: 4-WIRE Interface Summary

Parameters

nCS

Chip select

SI Serial input data

SO Serial output data

SK

Master out Slave in

Master in Slave out

Transmission clock

Signal Lines

Interface

Push-pull with tristate

Selected from VDDIO

Effective read/write data

Half-duplex

Supply voltage

Data rate

1.6 V to 3.3 V

Up to 7 Mbps

MSB first

Transmission

16 bit cycles

CPOL

7-bit address, 1 bit read/write, 8-bit data

Clock polarity

Configuration

CPHA

Clock phase

nCS_POL

nCS is active low/high

Note that reading the same register at high clock rates directly after writing it does not guarantee a

correct value. It is recommended to keep a delay of one frame until re-accessing a register that has

just been written (for example, by writing/reading another register address in between).

7.4.2

2-WIRE Communication

The IF_TYPE bit in the INTERFACE2 register can be used to configure the DA9223-A and DA9224-

A control interface as a 2-WIRE serial data interface. In this case the GPIO3 and GPI4 are free for

regular input/output functions. DA9223-A and DA9224-A has a configurable device write address

(default: 0xD0) and a configurable device read address (default: 0xD1). See control

IF_BASE_ADDR1 for details of configurable addresses. The ADDR_SEL_CONF bit is used to

configure the device address as IF_BASE_ADDR1 or IF_BASE_ADDR2 depending on the voltage

level applied at a configurable GPI port (see Section 7.2.4).

The SK port functions as the 2-WIRE clock and the SI port carries all the power manager

bi-directional 2-WIRE data. The 2-WIRE interface is open-drain supporting multiple devices on a

single line. The bus lines have to be pulled HIGH by external pull-up resistors (in the 2 kΩ to 20 kΩ

range). The attached devices only drive the bus lines LOW by connecting them to ground. As a result

two devices cannot conflict if they drive the bus simultaneously. In standard/fast mode the highest

frequency of the bus is 400 kHz. The exact frequency can be determined by the application and does

not have any relation to the DA9223-A and DA9224-A internal clock signals. DA9223-A and DA9224-

A will follow the host clock speed within the described limitations, and does not initiate any clock

arbitration or slow down. An automatic interface reset can be triggered using control 2WIRE_TO if

the clock signal stops to toggle for more than 35 ms.

The interface supports operation compatible to Standard, Fast, Fast-Plus and High Speed mode of

the I²C-bus specification Rev 4. Operation in high speed mode at 3.4 MHz requires mode changing in

order to set spike suppression and slope control characteristics to be compatible with the I²C-bus

specification. The high speed mode can be enabled on a transfer by transfer basis by sending the

master code (0000 1XXX) at the beginning of the transfer. DA9223-A and DA9224-A do not make

use of clock stretching, and deliver read data without additional delay up to 3.4 MHz.

Alternatively, PM_IF_HSM configures the interface to use high speed mode continuously. In this

case, the master code is not required at the beginning of every transfer. This reduces the

communication overhead on the bus but limits the slaves attachable to the bus to compatible

devices.

The communication on the 2-WIRE bus always takes place between two devices, one acting as the

master and the other as the slave. The DA9223-A and DA9224-A will only operate as a SLAVE.

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DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

In contrast to the 4-WIRE mode, the 2-WIRE interface has direct access to two pages of the register

map (up to 256 addresses). The register at address zero on each page is used as a page control

register (with the 2-WIRE bus ignoring the LSB of control REG_PAGE). Writing to the page control

register changes the active page for all subsequent read/write operations unless an automatic return

to page 0 was selected by asserting control REVERT. Unless REVERT was asserted after modifying

the active page, it is recommended to read back the page control register to ensure that future data

exchange is accessing the intended registers.

In 2-WIRE operation DA9223-A and DA9224-A offer an alternative way to access register page 2

and page 3. It removes the need for preceding page selection writes by incrementing the device

write/read address by one (default 0xD2/0xD3) for any direct access of page 2 and page 3 (page 0

and 1 access requires the basic write/read device address with the MSB of REG_PAGE to be ‘0’).

7.4.3

Details of the 2-WIRE Control Bus Protocol

All data is transmitted across the 2-WIRE bus in groups of eight bits. To send a bit the SDA line is

driven towards the intended state while the SCL is LOW (a low on SDA indicates a zero bit). Once

the SDA has settled, the SCL line is brought HIGH and then LOW. This pulse on SCL clocks the

SDA bit into the receiver’s shift register.

A two-byte serial protocol is used containing one byte for address and one byte data. Data and

address transfer are transmitted MSB first for both read and write operations. All transmissions begin

with the START condition from the master while the bus is in IDLE state (the bus is free). It is initiated

by a high to low transition on the SDA line while the SCL is in the high state (a STOP condition is

indicated by a low to high transition on the SDA line while the SCL is in the high state).

SCL

SDA

Figure 22: Timing of 2-WIRE START and STOP Condition

The 2-WIRE bus is monitored by DA9223-A and DA9224-A for a valid SLAVE address whenever the

interface is enabled. It responds immediately when it receives its own slave address. The

acknowledge is done by pulling the SDA line low during the following clock cycle (white blocks

marked with ‘A’ in Figure 23 to Figure 27).

The protocol for a register write from master to slave consists of a start condition, a slave address

with read/write bit and the 8-bit register address followed by eight bits of data terminated by a STOP

condition. DA9223-A and DA9224-A respond to all bytes with Acknowledge. This is illustrated in

Figure 23.

P

S

SLAVEadr

7-bits

W

A

REGadr

8-bits

A

DATA

8-bits

A

1-bit

Master to Slave

Slave to Master

S = START condition

P = STOP condition

A = Acknowledge (low)

W = Write (low)

Figure 23: 2-WIRE Byte Write (SDA Line)

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DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

When the host reads data from a register it first has to write to DA9223-A and DA9224-A with the

target register address and then read from DA9223-A and DA9224-A with a Repeated START or

alternatively a second START condition. After receiving the data, the host sends No Acknowledge

and terminates the transmission with a STOP condition. This is illustrated in Figure 24.

A^*

P

S

SLAVEadr W A REGadr A Sr SLAVEadr

R

A

DATA

8-bits

1-bit

7-bits 1-bit

8-bits

7-bits

S

SLAVEadr W A REGadr

A

P

S

SLAVEadr

R

A

DATA

8-bits

A^*

P

7-bits 1-bit

8-bits

7-bits 1-bit

Master to Slave

Slave to Master

S = START condition

Sr = Repeated START condition

P = STOP condition

A = Acknowledge (low)

A^*= No Acknowledge

W = Write (low)

R = Read (high)

Figure 24: Examples of 2-WIRE Byte Read (SDA Line)

Consecutive (page) read out mode is initiated from the master by sending an Acknowledge instead of

Not acknowledge after receipt of the data word. The 2-WIRE control block then increments the

address pointer to the next 2-WIRE address and sends the data to the master. This enables an

unlimited read of data bytes until the master sends a Not acknowledge directly after the receipt of

data, followed by a subsequent STOP condition. If a non-existent 2-WIRE address is read out, the

DA9223-A and DA9224-A will return code zero. This is illustrated in Figure 25.

A^*

P

S

SLAVEadr

W

A

REGadr

8-bits

A

Sr SLAVEadr

R

A

DATA

8-bits

A

DATA

8-bits

A

DATA

8-bits

7-bits

1 bit

7-bits 1-bit

S

SLAVEadr

W

A

REGadr

A

P

S

SLAVEadr

R

A

DATA

8-bits

A

DATA

8-bits

A^*

P

7-bits

8-bits

7-bits 1-bit

1-bit

Master to Slave

Slave to Master

A

S = START condition

= Acknowledge (low)

Sr = Repeat START condition

P = STOP condition

A^*= No Acknowledge

W = Write (low)

R = Read (high)

Figure 25: Examples of 2-WIRE Page Read (SDA Line)

Note that the slave address after the Repeated START condition must be the same as the previous

slave address.

Consecutive (page) write mode is supported if the Master sends several data bytes following a slave

register address. The 2-WIRE control block then increments the address pointer to the next 2-WIRE

address, stores the received data and sends an Acknowledge until the master sends the STOP

condition. This is illustrated in Figure 26.

S

SLAVEadr

W

A

REGadr

8-bits

A

DATA

A

DATA

8-bits

A

DATA

8-bits

A

……….

Repeated writes

A

P

7-bits 1 bit

8-bits 1-bit

Master to Slave

Slave to Master

A

S = START condition

= Acknowledge (low)

Sr = Repeat START condition

P = STOP condition

A^*= No Acknowledge

W = Write (low)

R = Read (high)

Figure 26: 2-WIRE Page Write (SDA Line)

Via control WRITE_MODE an alternate write mode can be configured. Register addresses and data

are sent in alternation like in Figure 27 to support host repeated write operations that access several

non-consecutive registers. Data will be stored at the previously received register address.

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DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

An update of WRITE_MODE cannot be done without interruption within a transmission frame. Thus,

if not previously selected or not set as OTP default, the activation of Repeated Write must be done

with a regular write on WRITE_MODE followed by a stop condition. The next frame after a start

condition can be written in Repeated Write.

S

SLAVEadr

W

A

REGadr

8-bits

A

DATA

A

REGadr

8-bits

A

DATA

8-bits

A

……….

Repeated writes

A

P

7-bits 1 bit

8-bits 1-bit

Master to Slave

Slave to Master

A

S = START condition

= Acknowledge (low)

Sr = Repeat START condition

P = STOP condition

A^*= No Acknowledge

W = Write (low)

R = Read (high)

Figure 27: 2-WIRE Repeated Write (SDA Line)

If a new START or STOP condition occurs within a message, the bus will return to IDLE-mode.

7.5 Internal Temperature Supervision

To protect DA9223-A and DA9224-A from damage due to excessive power dissipation, the internal

temperature is continuously monitored. There are three temperature thresholds:

Table 12: Over-Temperature Thresholds

Typical

Temperature

Setting

Temperature

Threshold

Interrupt Event

Status Bit

Masking Bit

TEMP_WARN

TEMP_CRIT

TEMP_POR

125 °C

140 °C

150 °C

E_TEMP_WARN

E_TEMP_CRIT

TEMP_WARN

TEMP_CRIT

M_TEMP_WARN

M_TEMP_CRIT

When the junction temperature reaches the TEMP_WARN threshold, DA9223-A and DA9224-A will

assert the bit TEMP_WARN and will generate the event E_TEMP_WARN. If not masked using bit

M_TEMP_WARN, the output port nIRQ will be asserted. The status bit TEMP_WARN will remain

asserted as long as the junction temperature remains higher than TEMP_WARN.

When the junction temperature increases further to TEMP_CRIT, DA9223-A and DA9224-A will

immediately disable the buck converter, assert the bit TEMP_CRIT, and will generate the event

E_TEMP_CRIT. If not masked via bit M_TEMP_CRIT, the output port nIRQ will be asserted. The

status bit TEMP_CRIT will remain asserted as long as the junction temperature remains higher than

TEMP_CRIT. The buck converter will be kept disabled as long as the junction temperature is above

TEMP_CRIT. It will not be automatically re-enabled even after the temperature drops below the valid

threshold (even if the controlling GPI is asserted). A direct write into BUCKA_EN or BUCKB_EN, or a

toggling of the controlling GPI, is needed to enable the buck converter.

Whenever the junction temperature exceeds TEMP_POR, a power on reset to the digital core is

immediately asserted, which will stops all functionalities of DA9223-A and DA9224-A. This is needed

to prevent possible permanent damage in the case of a rapid temperature increase.

Datasheet

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23-Apr-2021

CFR0011-120-00

36 of 60

DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

8

Register Definitions

8.1 Register Map

Table 13 displays the register map, where all bits loaded from OTP are marked in bold.

Datasheet

Revision 2.6

23-Apr-2021

CFR0011-120-00

37 of 60

DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

8.2 Register Definitions

8.2.1

Register Page Control

Register

Bit

Type Label

Description

Resets REG_PAGE to 000 after read/write access

has finished

7

R/W

REVERT

2-WIRE multiple write mode (Note 1)

0: Page Write Mode

6

R/W

WRITE_MODE

(reserved)

1: Repeated Write Mode

5:3

I²C

0x00

00x: Selects Register 0x00 to 0xFF

01x: Selects Register 0x100 to 0x17F

10x: Selects Register 0x200 to 0x27F

SPI

PAGE_CON

2:0

R/W

REG_PAGE

000: Selects Register 0x00 to 0x7F

001: Selects Register 0x80 to 0xFF

010: Selects Register 0x100 to 0x17F

100: Selects Register 0x200 to 0x27F

Note 1 Not used for 4-WIRE-IF.

8.2.2

Register Page 0

8.2.2.1

System Control and Event

The STATUS registers report the current value of the various signals at the time that it is read out.

Register

Bit

7:5

4

Type Label

Description

R

(reserved)

GPI4

GPI3

GPI2

GPI1

GPI0

GPI4 level

GPI3 level

GPI2 level

GPI1 level

GPI0 level

3

0x50

STATUS_A

2

1

0

Register

Bit

Type Label

Description

De-asserted during Buck A DVC, power up and

power down

7

R

RAMP_READY_B

De-asserted during Buck B DVC, power up and

power down

6

RAMP_READY_A

5

4

R

OV_CURR_B

OV_CURR_A

Asserted as long as the current limit for Buck B is hit

Asserted as long as the current limit for Buck A is hit

0x51

STATUS_B

Asserted as long as the thermal shutdown threshold

is reached

3

2

R

TEMP_CRIT

Asserted as long as the thermal warning threshold is

reached

TEMP_WARN

Datasheet

Revision 2.6

23-Apr-2021

CFR0011-120-00

39 of 60

DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

Register

Bit

Type Label

Description

Asserted as long as the Buck B output voltage is in

range

1

R

PWRGOOD_B

PWRGOOD_A

Asserted as long as the Buck A output voltage is in

range

0

The EVENT registers hold information about events that have occurred in DA9223-A and DA9224-A.

Events are triggered by a change in the status register which contains the status of monitored

signals. When an EVENT bit is set in the event register, the IRQ signal is asserted unless the event

is masked by a bit in the mask register. The IRQ triggering event register will be cleared from the

host by writing back its read value. New events occurring during clearing will be delayed before

they are passed to the event register, ensuring that the host controller does not miss them.

Register

Bit

7

Type Label

Description

R

(reserved)

6

E_UVLO_IO

(reserved)

E_GPI4

UVLO_IO caused event

5

4

GPI4 event according to active state setting

GPI3 event according to active state setting

GPI2 event according to active state setting

GPI1 event according to active state setting

GPI0 event according to active state setting

0x52

EVENT_A

3

E_GPI3

2

E_GPI2

1

E_GPI1

0

E_GPI0

Register

Bit

7:6

5

Type Label

Description

R

(reserved)

E_OV_CURR_B

E_OV_CURR_A

E_TEMP_CRIT

E_TEMP_WARN

E_PWRGOOD_B

E_PWRGOOD_A

OV_CURR Buck B caused event

OV_CURR Buck A caused event

TEMP_CRIT caused event

4

0x53

3

EVENT_B

2

TEMP_WARN caused event

1

PWRGOOD loss at Buck B caused event

PWRGOOD loss at Buck A caused event

0

Register

Bit

7

Type Label

Description

R/W

(reserved)

6

M_UVLO_IO

(reserved)

M_GPI4

Mask UVLO_IO caused nIRQ

5

4

Mask nIRQ interrupt at GPI4

Mask nIRQ interrupt at GPI3

Mask nIRQ interrupt at GPI2

Mask nIRQ interrupt at GPI1

Mask nIRQ interrupt at GPI0

0x54

MASK_A

3

M_GPI3

2

M_GPI2

1

M_GPI1

0

M_GPI0

Datasheet

Revision 2.6

23-Apr-2021

CFR0011-120-00

40 of 60

DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

Register

Bit

7:6

5

Type Label

Description

R/W

(reserved)

M_OV_CURR_B

M_OV_CURR_A

M_TEMP_CRIT

M_TEMP_WARN

M_PWRGOOD_B

M_PWRGOOD_A

Mask OV_CURR Buck B caused nIRQ and event

Mask OV_CURR Buck A caused nIRQ and event

Mask TEMP_CRIT caused nIRQ

4

0x55

3

MASK_B

2

Mask TEMP_WARN caused nIRQ

1

Mask PWRGOOD Buck B caused nIRQ

Mask PWRGOOD Buck A caused nIRQ

0

Register

Bit

Type Label

Description

0: Allows host writes into registers 0xD0 to 0x14F

7

R/W

V_LOCK

1: Disables register 0xD0 to 0x14F re-

programming from control interfaces

Buck B DVC slewing is executed at

00: 10mV every 4.0 µs

6:5

4:3

R/W

SLEW_RATE_B

SLEW_RATE_A

01: 10mV every 2.0 µs

10: 10mV every 1.0 µs

11: 10mV every 0.5 µs

Buck A DVC slewing is executed at

00: 10mV every 4.0 µs

0x56

R/W

01: 10mV every 2.0 µs

CONTROL_A

10: 10mV every 1.0 µs

11: 10mV every 0.5 µs

Input signals debounce time:

000: no debounce time

001: 0.1 ms

010: 1.0 ms

0:2

R/W

DEBOUNCE

011: 10 ms

100: 50 ms

101: 250 ms

110: 500 ms

111: 1000 ms

8.2.2.2

GPIO Control

Register

Bit

Type Label

Description

0: GPI: debouncing off

1: GPI: debouncing on

7

R/W

GPI1_MODE

GPI1_TYPE

0: GPI: active low

1: GPI: active high

6

0x58

PIN assigned to:

00: GPI

GPI0-1

5:4

3

R/W

GPI1_PIN

>00: Reserved

0: GPI: debouncing off

1: GPI: debouncing on

GPI0_MODE

Datasheet

Revision 2.6

23-Apr-2021

CFR0011-120-00

41 of 60

DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

Register

Bit

Type Label

Description

0: GPI: active low

1: GPI: active high

2

R/W

GPI0_TYPE

PIN assigned to:

00: GPI

1:0

GPI0_PIN

01: Track enable

1x: Reserved

Register

Bit

Type Label

Description

0: GPI: debouncing off

GPO: Sets output to passive level

7

R/W

GPIO3_MODE

1: GPI: debouncing on

GPO: Sets output to active level

0: GPI/GPO: active low

1: GPI/GPO: active high

6

GPIO3_TYPE

GPIO3_PIN

PIN assigned to:

00: GPI

5:4

R/W

01: Reserved

10: GPO (Open drain)

11: GPO (Push-pull)

0x59

GPIO2-3

0: GPI: debouncing off

GPO: Sets output to passive level

3

2

R/W

GPIO2_MODE

GPIO2_TYPE

1: GPI: debouncing on

GPO: Sets output to active level

0: GPI/GPO: active low

1: GPI/GPO: active high

PIN assigned to:

00: GPI

1:0

R/W

GPIO2_PIN

01: Reserved

10: GPO (Open drain)

11: GPO (Push-pull)

Register

Bit

Type Label

Description

7:4

R/W

(reserved)

0: GPI: debouncing off

1: GPI: debouncing on

3

2

GPI4_MODE

GPI4_TYPE

0: GPI: active low

1: GPI: active high

0x5A

GPI4

R/W

PIN assigned to:

00: GPI

1:0

GPI4_PIN

01: Reserved

1x: Reserved

Datasheet

Revision 2.6

23-Apr-2021

CFR0011-120-00

42 of 60

DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

8.2.2.3

Regulators Control

Register

Bit

Type Label

Description

7

R/W

(reserved)

Selects the GPI that specifies the target voltage of

VBUCKA. This is VBUCKA_A on active to passive

transition, VBUCKA_B on passive to active

transition.

Active high/low is controlled by GPIx_TYPE.

00: Not controlled by GPIO

01: GPI1 controlled

6:5

VBUCKA_GPI

10: GPIO2 controlled

11: GPI4 controlled

Buck A voltage is selected from (ramping):

0: VBUCKA_A

4

3

R/W

VBUCKA_SEL

0x5D

1: VBUCKA_B

BUCKA_CON

T

0: Enable pull-down resistor of Buck A when the

buck is disabled

BUCKA_PD_DIS

1: Disable pull-down resistor of Buck A when the

buck is disabled

GPI enables the Buck A on passive to active state

transition, disables the Buck A on active to passive

state transition

00: Not controlled by GPIO

01: GPI0 controlled

2:1

R/W

BUCKA_GPI

BUCKA_EN

10: GPI1 controlled

11: GPIO3 controlled

0: Buck A disabled

1: Buck A enabled

0

Register

Bit

Type Label

Description

7

R/W

(reserved)

Selects the GPI that specifies the target voltage of

VBUCKB. This is VBUCKB_A on active to passive

transition, VBUCKB_B on passive to active

transition.

Active high/low is controlled by GPIx_TYPE

00: Not controlled by GPIO

01: GPI1 controlled

6:5

VBUCKB_GPI

0x5E

10: GPIO2 controlled

BUCKB_CON

T

11: GPI4 controlled

Buck A voltage is selected from (ramping):

0: VBUCKB_A

4

3

R/W

VBUCKB_SEL

1: VBUCKB_B

0: Enable pull-down resistor of Buck B when the

buck is disabled

BUCKB_PD_DIS

1: Disable pull-down resistor of Buck B when the

buck is disabled

Datasheet

Revision 2.6

23-Apr-2021

CFR0011-120-00

43 of 60

DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

Register

Bit

Type Label

Description

GPI enables the Buck B on passive to active state

transition, disables the Buck B on active to passive

state transition

00: Not controlled by GPIO

01: GPI0 controlled

2:1

R/W

BUCKB_GPI

10: GPI1 controlled

11: GPIO3 controlled

0: Buck B disabled

1: Buck B enabled

0

BUCKB_EN

8.2.3

Register Page 1

Register

Bit

Type Label

Description

Resets REG_PAGE to 000 after read/write access

has finished

7

R/W

REVERT

2-WIRE multiple write mode

0: Page Write Mode

6

R/W

WRITE_MODE

(reserved)

1: Repeated Write Mode

5:3

I²C

0x80

00x: Selects Register 0x00 to 0xFF

01x: Selects Register 0x100 to 0x17F

10x: Selects Register 0x200 to 0x27F

SPI

PAGE_CON

2:0

R/W

REG_PAGE

000: Selects Register 0x00 to 0x7F

001: Selects Register 0x80 to 0xFF

010: Selects Register 0x100 to 0x17F

100: Selects Register 0x200 to 0x27F

8.2.3.1

Regulators Settings

Register

Bit

Type Label

Description

Current limit per phase:

0000: 4000 mA

0001: 4200 mA

0010: 4400 mA

0xD0

7:4

R/W

BUCKB_ILIM

continuing through…

1001: 5800 mA

to…

BUCK_ILIM

1110: 6800 mA

1111: 7000 mA

Datasheet

Revision 2.6

23-Apr-2021

CFR0011-120-00

44 of 60

DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

Register

Bit

Type Label

Description

Current limit per phase:

0000: 4000 mA

0001: 4200 mA

0010: 4400 mA

3:0

R/W

BUCKA_ILIM

continuing through…

1001: 5800 mA

to…

1110: 6800 mA

1111: 7000 mA

Register

Bit

Type Label

Description

Buck A voltage ramping during power down

000: 1.25 mV/µs

001: 2.5 mV/µs

010: 5 mV/µs

BUCKA_DOWN_

CTRL

7:5

R/W

011: 10 mV/µs

100: 20 mV/µs

101: 30 mV/µs

110: 40 mV/µs

111: Reserved

Buck A voltage ramping during start up

000: 1.25 mV/µs

0xD1

BUCKA_CON

F

001: 2.5 mV/µs

010: 5 mV/µs

BUCKA_UP_CT

RL

4:2

R/W

011: 10 mV/µs

100: 20 mV/µs (Note 1)

101: 30 mV/µs

110: 40 mV/µs

111: target voltage applied immediately (no soft start)

00: PFM/PWM mode controlled via voltage A and B

registers

01: Automatic mode (1-phase)

10: Buck A always operates in PWM mode

11: Automatic mode

1:0

R/W

BUCKA_MODE

Note 1 Settings higher than 20 mV/µs may cause significant overshoot.

Datasheet

Revision 2.6

23-Apr-2021

CFR0011-120-00

45 of 60

DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

Register

Bit

Type Label

Description

Buck B voltage ramping during power down

000: 1.25 mV/µs

001: 2.5 mV/µs

010: 5 mV/µs

BUCKB_DOWN_

CTRL

7:5

R/W

011: 10 mV/µs

100: 20 mV/µs

101: 30 mV/µs

110: 40 mV/µs

111: Reserved

Buck B voltage ramping during start up

000: 1.25 mV/µs

0xD2

BUCKB_CON

F

001: 2.5 mV/µs

010: 5 mV/µs

BUCKB_UP_CT

RL

4:2

R/W

011: 10 mV/µs

100: 20 mV/µs (Note 1)

101: 30 mV/µs

110: 40 mV/µs

111: target voltage applied immediately (no soft start)

00: PFM/PWM mode controlled via voltage A and B

registers

01: Automatic mode (1-phase)

10: Buck B always operates in PWM mode

11: Automatic mode

1:0

R/W

BUCKB_MODE

Note 1 Settings higher than 20mV/µs may cause significant overshoot.

Register

Bit

Type Label

Description

7:5

R/W

(reserved)

Enable current dependent phase shedding in PWM for

Buck B

4

3

PH_SH_EN_B

PH_SH_EN_A

Enable current dependent phase shedding in PWM for

Buck A

R/W

Phase selection for Buck B in PWM

0: 1 phase is selected

2

PHASE_SEL_B

0xD3

1: 2 phases are selected

BUCK_CONF

Phase selection for Buck A in PWM mode. Settings

>01 apply only for DA9223-A otherwise the number of

phases is limited to max 2

00: 1 phase is selected

1:0

R/W

PHASE_SEL_A

01: 2 phases are selected

10: 3 phases are selected (uneven 0/90/180 phase

shift)

11: 4 phases are selected

Datasheet

Revision 2.6

23-Apr-2021

CFR0011-120-00

46 of 60

DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

Register

Bit

Type Label

R/W (reserved)

Description

7

Sets the maximum voltage allowed for Buck A (OTP

programmed, access only in test mode)

0000000: 0.30 V

0000001: 0.31 V

0000010: 0.32 V

0xD5

VBUCKA_MA

X

6:0

R

VBUCKA_MAX

Continuing through…

1000110: 1.0 V

to…

1111101: 1.55 V

1111110: 1.56 V

1111111: 1.57 V

Register

Bit

Type Label

R/W (reserved)

Description

7

Sets the maximum voltage allowed for Buck B (OTP

programmed, access only in test mode)

0000000: 0.30 V

0000001: 0.31 V

0000010: 0.32 V

0xD6

VBUCKB_MA

X

6:0

R

VBUCKB_MAX

Continuing through…

1000110: 1.0 V

to…

1111101: 1.55 V

1111110: 1.56 V

1111111: 1.57 V

Datasheet

Revision 2.6

23-Apr-2021

CFR0011-120-00

47 of 60

DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

Register

Bit

Type Label

Description

0: Configures Buck A to PWM mode whenever

selecting A voltage setting

7

R/W

BUCKA_SL_A

1: Configures Buck A to automatic mode whenever

selecting A voltage setting

0000000: 0.30 V

0000001: 0.31 V

0000010: 0.32 V

0xD7

VBUCKA_A

Continuing through…

1000110: 1.0 V

to…

6:0

R/W

VBUCKA_A

1111101: 1.55 V

1111110: 1.56 V

1111111: 1.57 V

Register

Bit

Type Label

Description

0: Configures Buck A to PWM mode, whenever

selecting B voltage setting

7

R/W

BUCKA_SL_B

1: Configures Buck A to automatic mode, whenever

selecting B voltage setting

0000000: 0.30 V

0000001: 0.31 V

0000010: 0.32 V

0xD8

VBUCKA_B

Continuing through…

1000110: 1.0 V

to…

6:0

R/W

VBUCKA_B

1111101: 1.55 V

1111110: 1.56 V

1111111: 1.57 V

Register

Bit

Type Label

Description

0: Configures Buck B to PWM mode, whenever

selecting A voltage setting

7

R/W

BUCKB_SL_A

1: Configures Buck B to automatic mode, whenever

selecting A voltage setting

0000000: 0.30 V

0000001: 0.31 V

0000010: 0.32 V

0xD9

VBUCKB_A

Continuing through…

1000110: 1.0 V

to…

6:0

R/W

VBUCKB_A

1111101: 1.55 V

1111110: 1.56 V

1111111: 1.57 V

Datasheet

Revision 2.6

23-Apr-2021

CFR0011-120-00

48 of 60

DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

Register

Bit

Type Label

Description

0: Configures Buck B to PWM mode, whenever

selecting B voltage setting

7

R/W

BUCKB_SL_B

1: Configures Buck B to automatic mode, whenever

selecting B voltage setting

0000000: 0.30 V

0000001: 0.31 V

0000010: 0.32 V

0xDA

VBUCKB_B

Continuing through…

1000110: 1.0 V

to…

6:0

R/W

VBUCKB_B

1111101: 1.55 V

1111110: 1.56 V

1111111: 1.57 V

8.2.4

Register Page 2

Register

Bit

Type Label

Description

Resets REG_PAGE to 000 after read/write access

has finished

7

R/W

REVERT

2-WIRE multiple write mode

0: Page Write Mode

6

R/W

WRITE_MODE

(reserved)

1: Repeated Write Mode

5:3

I²C

0x100

00x: Selects Register 0x00 to 0xFF

01x: Selects Register 0x100 to 0x17F

10x: Selects Register 0x200 to 0x27F

SPI

PAGE_CON

2:0

R/W

REG_PAGE

000: Selects Register 0x00 to 0x7F

001: Selects Register 0x80 to 0xFF

010: Selects Register 0x100 to 0x17F

100: Selects Register 0x200 to 0x27F

Datasheet

Revision 2.6

23-Apr-2021

CFR0011-120-00

49 of 60

DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

8.2.4.1

Interface and OTP Settings (Shared with DA9063)

Register

Bit

Type Label

Description

4 MSB of 2-WIRE control interfaces base address

XXXX0000

11010000 = 0xD0 write address of PM 2-WIRE

interface (page 0 and 1)

11010001 = 0xD1 read address of PM 2-WIRE

interface (page 0 and 1)

11010010 = 0xD2 write address of PM-2-WIRE

interface (page 2 and 3)

IF_BASE_ADDR

1

7:4

R/W

11010011 = 0xD3 read address of PM-2-WIRE

interface (page 2 and 3)

11010101 = 0xD5 read address of PM-2-WIRE

interface (page 4 and 5)

Code ‘0000’ is reserved for unprogrammed OTP

(triggers start-up with hardware default interface

address)

0x105

INTERFACE

4-WIRE: Read/Write bit polarity

3

2

1

R/W

R/W_POL

CPHA

0: Host indicates reading access via R/W bit = ‘0’

1: Host indicates reading access via R/W bit = ‘1’

4-WIRE interface clock phase (see Table 10)

4-WIRE interface clock polarity

0: SK is low during idle

CPOL

1: SK is high during idle

4-WIRE chip select polarity

0: nCS is low active

0

R/W

nCS_POL

1: nCS is high active

Datasheet

Revision 2.6

23-Apr-2021

CFR0011-120-00

50 of 60

DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

Register

Bit

Type Label

Description

0: Power manager interface is 4-WIRE. Automatically

configures GPIO3 and GPI4 as interface signals. The

GPIO configuration is overruled.

7

R/W

IF_TYPE

1: Power manager interface is 2-WIRE

Enables continuous high speed mode on 2-WIRE

interface if asserted (no master code required)

6

5

R/W

PM_IF_HSM

PM_IF_FMP

0x106

Enables 2-WIRE interface operating with fast mode+

timings if asserted

INTERFACE2

0: Power manager interface in 2-WIRE mode is

supplied from VDDCORE (4-WIRE always from

VDDIO)

4

R/W

PM_IF_V

(reserved)

1: Power manager interface in 2-WIRE mode is

supplied from VDDIO (4-WIRE always from VDDIO)

0:3

8.2.4.2

Application Configuration Settings

Register

Bit

Type Label

Description

7:5

R/W

(reserved)

Enables automatic reset of 2-WIRE interface if the

clock stays low for >35 ms

4

2WIRE_TO

0: Disabled

1: Enabled

GPIs are supplied from:

0: VDDCORE

3

2

1

R/W

GPI_V

0x143

1: VDDIO

CONFIG_A

(reserved)

IRQ_TYPE

nIRQ output port is:

0: Push-pull

1: Open drain (requires external pull-up resistor)

nIRQ output port is:

0: Active low

0

R/W

IRQ_LEVEL

1: Active high

Register

Bit

Type Label

Description

Disable the UVLO for the VDDIO rail and its

comparator (suggested for rail voltages different to

1.8 V and to save quiescent current)

7

R/W

UVLO_IO_DIS

Power-good configuration for Buck B

0: Power-good signal not masked during DVC

transitions

PGB_DVC_MAS

K

6

5

R/W

0x144

1: Power-good signal masked during DVC transitions

(keep previous status)

CONFIG_B

Power-good configuration for Buck A

0: Power-good signal not masked during DVC

transitions

PGA_DVC_MAS

K

R/W

1: Power-good signal masked during DVC transitions

(keep previous status)

Datasheet

Revision 2.6

23-Apr-2021

CFR0011-120-00

51 of 60

DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

Register

Bit

Type Label

Description

Over Current configuration for Buck B

00: Event generation due to over current hit is always

active during DVC transitions of the Buck converter

01: Event generation due to over current hit is masked

during DVC transitions of the buck converter + 2 µs

extra masking at the end

4:3

R/W

OCB_MASK

10: Event generation due to over current hit is masked

during DVC transitions of the buck converter + 10 µs

extra masking at the end

11: Event generation due to over current hit is masked

during DVC transitions of the buck converter + 50 µs

extra masking at the end

Over Current configuration for Buck A

00: Event generation due to over current hit is always

active during DVC transitions of the buck converter

01: Event generation due to over current hit is masked

during DVC transitions of the buck converter + 2 µs

extra masking at the end

2:1

R/W

OCA_MASK

10: Event generation due to over current hit is masked

during DVC transitions of the buck converter + 10 µs

extra masking at the end

11: Event generation due to over current hit is masked

during DVC transitions of the buck converter + 50 µs

extra masking at the end

RELOAD_FUNC

_EN

Enable the OTP re-load function for GPI0 when

configured as input port

0

Register

Bit

Type Label

Description

7:5

R/W

(reserved)

0: GPI: pull-down resistor disabled

1: GPI: pull-down resistor enabled

4

3

GPI4_PUPD

0: GPI: pull-down resistor disabled

GPO (open drain): pull up resistor disabled

(external pull-up resistor)

R/W

GPIO3_PUPD

1: GPI: pull-down resistor enabled

GPO (open drain): pull up resistor

0x145

0: GPI: pull-down resistor disabled

GPO (open drain): pull up resistor disabled

(external pull-up resistor)

CONFIG_C

2

GPIO2_PUPD

1: GPI: pull-down resistor enabled

GPO (open drain): pull up resistor enabled

0: GPI: pull-down resistor disabled

1: GPI: pull-down resistor enabled

1

0

R/W

GPI1_PUPD

GPI0_PUPD

0: GPI: pull-down resistor disabled

1: GPI: pull-down resistor enabled

Datasheet

Revision 2.6

23-Apr-2021

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DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

Register

Bit

Type Label

Description

Selection of the PG signal for Buck B

00: none

7:6

R/W

BUCKB_PG_SEL 01: GPO2

10: GPO3

11: reserved

Selection of the PG signal for Buck A

00: none

5:4

3:2

1:0

BUCKA_PG_SEL 01: GPO2

10: GPO3

11: reserved

0x146

CONFIG_D

Selection of the READY signal for Buck B

00: none

READYB_CONF

READYA_CONF

01: GPO2

10: GPO3

11: reserved

Selection of the READY signal for Buck A

00: none

01: GPO2

10: GPO3

11: reserved

Register

Bit

Type Label

Description

0: DA9223-A and DA9224-A is used as companion IC

to DA9063 or DA9063-compliant

7

R/W

STAND_ALONE

1: DA9223-A and DA9224-A is stand alone or as

companion IC with another PMU not

DA9063-compliant

6:5

4:3

R/W

(reserved)

0x147

Tune the main 6 MHz oscillator frequency:

000: no tune

CONFIG_E

001: +180 kHz

010: +360 kHz

2:0

R/W

OSC_TUNE

011: +540 kHz

100: +720 kHz

101: +900 kHz

110: +1080 kHz

111: +1260 kHz

Datasheet

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23-Apr-2021

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DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

Register

Bit

Type Label

Description

If a second I²C address is to be selected on

ADR_SEL_CONF, this field configures the second

address.

4 MSB of 2-WIRE control interfaces base address

XXXX0000

11010000 = 0xD0 write address of PM 2-WIRE

interface (page 0 and 1)

11010001 = 0xD1 read address of PM 2-WIRE

interface (page 0 and 1)

IF_BASE_ADDR

2

7:4

R/W

11010010 = 0xD2 write address of PM-2-WIRE

interface (page 2 and 3)

11010011 = 0xD3 read address of PM-2-WIRE

interface (page 2 and 3)

0x148

11010101 = 0xD5 read address of PM-2-WIRE

interface (page 4 and 5)

CONFIG_F

Code ‘0000’ is reserved for unprogrammed OTP

(triggers start-up with hardware default interface

address)

3:2

1

R

(reserved)

Selects the GPI for the alternative I²C address

selection:

00: none

01: GPI0

10: GPI1

11: GPI4

ADDR_SEL_CO

NF

R/W

Datasheet

Revision 2.6

23-Apr-2021

CFR0011-120-00

54 of 60

DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

8.2.5

Register Page 4

Register

Bit

Type Label

Description

Resets REG_PAGE to 000 after read/write access

has finished

7

R/W

REVERT

2-WIRE multiple write mode

0: Page Write Mode

6

R/W

WRITE_MODE

(reserved)

1: Repeated Write Mode

5:3

I²C

0x200

00x: Selects Register 0x00 to 0xFF

01x: Selects Register 0x100 to 0x17F

10x: Selects Register 0x200 to 0x27F

SPI

PAGE_CON

2:0

R/W

REG_PAGE

000: Selects Register 0x00 to 0x7F

001: Selects Register 0x80 to 0xFF

010: Selects Register 0x100 to 0x17F

100: Selects Register 0x200 to 0x27F

8.2.5.1

Chip and OTP IDs

Register

Bit

Type Label

DEV_ID

Description

0x201

7:0

R

Device ID

DEVICE_ID

Register

Bit

7:4

3:0

Type Label

Description

R

MRC

VRC

Mask Revision Code

Chip Variant Code

0x202

VARIANT_ID

Register

Bit

Type Label

Description

0x203

7:0

R

CUST_ID

Customer ID

CUSTOMER_

ID

Register

Bit

Type Label

Description

0x204

7:0

R

CONFIG_REV

OTP Variant

CONFIG_ID

Datasheet

Revision 2.6

23-Apr-2021

CFR0011-120-00

55 of 60

DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

9

Application Information

The following recommended components are examples selected from requirements of a typical

application.

9.1 Capacitor Selection

Ceramic capacitors are used as bypass capacitors at all VDD and output rails. When selecting a

capacitor, especially for types with high capacitance at smallest physical dimension, the DC bias

characteristic has to be taken into account.

Table 14: Recommended Capacitor Types

Application

Value

Size

Temp Char

Tol

V-Rate

Type

VOUT

Murata

GCM32ER70J476KE19

47 uF

1210

X7R ±15 %

±10 %

6.3 V

output

bypass

Murata

GCM31CR70J226KE23

22 uF

10 uF

1 uF

1206

0805

0603

0402

X7R ±15 %

±10 %

6.3 V

10 V

16 V

50 V

Murata

GCM21BR70J106KE22

VDDx

bypass

Murata

GCM21BR71A106KE22

VSYS

bypass

Murata

GCM188R71C105KA64

VDDIO

bypass

Murata

GCM155R71H104KE02

100 nF

Datasheet

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23-Apr-2021

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DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

9.2 Inductor Selection

Inductors should be selected based upon the following parameters:

●

Rated max. current: usually a coil provides two current limits: The Isat specifies the maximum

current at which the inductance drops by 30 % of the nominal value. The Imax is defined by the

maximum power dissipation and is applied to the effective current.

●

DC resistance: critical for the converter efficiency and should therefore be minimized.

The typical recommended output inductance is 0.22 µH per phase. Use of larger output

inductance degrades the load transient performance of the buck converter.

Table 15: Recommended Inductor Types

Application

Value

Size

Imax(dc)

Isat

Tol

DC res

Type

2.5 mm x

2.0 mm x

1.0 mm

TDK

BUCK

0.22 uH

7.1 A

8.0 A

±20%

12 mΩ TFM252010ALMAR22M

TAA

2.5 mm x

2.0 mm x

1.2 mm

TDK

0.22 uH

0.24 uH

0.47 uH

0.24 uH

0.47 uH

0.24 uH

0.47 uH

8.5 A

7.0 A

4.8 A

5.4 A

5.6 A

4.7 A

5.0 A

3.8 A

5.0 A

3.8 A

5.9 A

4.7 A

10 A

±20%

8 mΩ

TFM252012ALMAR22M

TAA

2.0 mm x

1.6 mm x

1.0 mm

TDK

7.5 A

5.9 A

6.5 A

6.1 A

5.8 A

4.5 A

7.7 A

5.5 A

8.5 A

6.2 A

15 mΩ TFM201610ALMAR24M

TAA

2.0 mm x

1.6 mm x

1.2 mm

TOKO DFE201612PD-

R24M

16 mΩ

2.5 mm x

2.0 mm x

1.0 mm

TDK

20 mΩ TFM252010ALMAR47M

TAA

2.5 mm x

2.0 mm x

1.2 mm

TDK

19 mΩ TFM252012ALMAR47M

TAA

2.5 mm x

2.0 mm x

1.2 mm

TOKO DFE252012PD-

R47M

21 mΩ

2.0 mm x

1.6 mm x

1.0 mm

TDK

28 mΩ TFM201610ALMAR47M

TAA

2.0 mm x

1.6 mm x

1.2 mm

TOKO DFE201612PD-

R47M

26 mΩ

2.0 mm x

1.6 mm x

1.2 mm

Taiyo Yuden

16 mΩ

MEMK2016TR24MV

2.0 mm x

1.6 mm x

1.2 mm

Taiyo Yuden

28 mΩ

MEMK2016TR47MV

2.5 mm x

2.0 mm x

1.2 mm

Taiyo Yuden

13 mΩ

MEMK2520TR24MV

2.5 mm x

2.0 mm x

1.2 mm

Taiyo Yuden

21 mΩ

MEMK2520TR47MV

Datasheet

Revision 2.6

23-Apr-2021

CFR0011-120-00

57 of 60

DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

10 Package Information

10.1 Package Outlines

Figure 28: DA9223-A/24-A 66 TFBGA 0.8 mm Pitch Package Outline Drawing

Datasheet

Revision 2.6

23-Apr-2021

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58 of 60

DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

10.2 Package Marking

Table 16: Package Marking

11 Ordering Information

The ordering number consists of the part number followed by a suffix indicating the packing method.

For details and availability, please consult Dialog Semiconductor’s website or your local sales

representative.

Table 17: Ordering Information

Package

Description

Package

Outline

Part Number

Package

Comment

DA9223-xxFT1BB-A

66 TFBGA

Tray

Auto Grade 2

DA9223-xxFT2BB-A, Note 1

DA9223-xxFTDBB-A

T&R, 3000pcs

T&R, 2200pcs

Tray

DA9224-xxFT1BB-A

DA9224-xxFT2BB-A, Note 1

DA9224-xxFTDBB-A

T&R, 3000pcs

T&R, 2200pcs

Auto Grade 2

with High Temp screening

DA9223-xxFT1BB-AT

66 TFBGA

Tray

Figure 28

Auto Grade 2

with High Temp screening

DA9223-xxFT2BB-AT, Note 1

DA9223-xxFTDBB-AT

T&R, 3000pcs

T&R, 2200pcs

Tray

Auto Grade 2

with High Temp screening

Auto Grade 2

with High Temp screening

DA9224-xxFT1BB-AT

Auto Grade 2

with High Temp screening

DA9224-xxFT2BB-AT, Note 1

DA9224-xxFTDBB-AT

T&R, 3000pcs

T&R, 2200pcs

Auto Grade 2

with High Temp screening

Note 1 Large reel sizes are no longer supported, contact sales for further information

Datasheet

Revision 2.6

23-Apr-2021

CFR0011-120-00

59 of 60

DA9223-A and DA9224-A

Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter

Status Definitions

Revision

Datasheet Status

Product Status

Definition

This datasheet contains the design specifications for product development.

Specifications may be changed in any manner without notice.

1.<n>

Target

Development

This datasheet contains the specifications and preliminary characterization

data for products in pre-production. Specifications may be changed at any

time without notice in order to improve the design.

2.<n>

3.<n>

Preliminary

Qualification

This datasheet contains the final specifications for products in volume

production. The specifications may be changed at any time in order to

improve the design, manufacturing and supply. Major specification changes

are communicated via Customer Product Notifications. Datasheet changes

are communicated via www.dialog-semiconductor.com.

Final

Production

Archived

This datasheet contains the specifications for discontinued products. The

information is provided for reference only.

4.<n>

Obsolete

Disclaimer

Unless otherwise agreed in writing, the Dialog Semiconductor products (and any associated software) referred to in this document are not

designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications

where failure or malfunction of a Dialog Semiconductor product (or associated software) can reasonably be expected to result in personal injury,

death or severe property or environmental damage. Dialog Semiconductor and its suppliers accept no liability for inclusion and/or use of Dialog

Semiconductor products (and any associated software) in such equipment or applications and therefore such inclusion and/or use is at the

customer’s own risk.

Information in this document is believed to be accurate and reliable. However, Dialog Semiconductor does not give any representations or

warranties, express or implied, as to the accuracy or completeness of such information. Dialog Semiconductor furthermore takes no

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Dialog Semiconductor reserves the right to change without notice the information published in this document, including, without limitation, the

specification and the design of the related semiconductor products, software and applications. Notwithstanding the foregoing, for any automotive

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Contacting Dialog Semiconductor

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Datasheet

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23-Apr-2021

CFR0011-120-00

60 of 60


型号：	DA9224-A
厂家：	Dialog Semiconductor
描述：	Auto Grade 0.8 mm Pitch Multi-Phase Buck Converter 多相元件
文件：	总60页 (文件大小：1412K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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