SLG46585 [DIALOG]
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous State Machine, LDOs, and DC/DC Converter;
| 型号： | SLG46585 |
| 厂家： | 
Dialog Semiconductor |
| 描述： | GreenPAK Programmable Mixed-Signal Matrix with Asynchronous State Machine, LDOs, and DC/DC Converter |
| 文件： | 总210页 (文件大小：4742K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
General Description
The SLG46585 is a small, low power component commonly used to integrate Mixed-Signal functions under control of an
asynchronous state machine. The user creates the circuit design by programming the one time Non-Volatile Memory (NVM) to
configure the interconnect logic, the IO Pins, and the macrocells of the SLG46585. In addition, the device contains one 1 A DC/
DC buck converter operating from 1 MHz to 2 MHz and four 150 mA configurable LDOs. This highly versatile device allows a
wide variety of functions and control logic to be designed within a very small, low power monolithic integrated circuit.
Serial Communications
I2C Slave Protocol Interface
Programmable Delay with Edge Detector Output
Additional Logic Functions
Key Features
Four Analog Comparators
Voltage Reference for Analog Comparators
Analog Temperature Sensor
2 Deglitch Filters with Edge Detectors
Fifteen Combination Function Macrocells
Two Oscillators
Three Selectable DFF/LATCH or 2-bit LUTs
Six Selectable DFF/LATCH or 3-bit LUTs
One Selectable Pipe Delay or Ripple Counter, or 3-bit
LUT
Configurable 25 kHz/2 MHz
1.73 kHz Low Power Oscillator
Eight Byte RAM + OTP User Memory
RAM with I2C interface
Five 8-bit Delays/Counters or 3-bit LUTs
User Defined Initial Values Transferred from OTP
Combinatorial Logic
One 4-bit LUT with Two Outputs
Programmable Asynchronous State Machine
Power-On Reset
Highly Versatile Macrocells
Read Back Protection (Read Lock)
2.5 V to 5.5 V Supply
Operating Temperature Range: -40 °C to 85 °C
RoHS Compliant/Halogen-Free
29-pin MSTQFN: 3 mm x 3 mm x 0.55 mm, 0.4 mm pitch
Eight States
Flexible Input Logic from State Transitions
Real Time Clock Binary Counter
Four Tri-Mode 150 mA LDO Regulators
High Power Mode (HP Mode): 150 mA Output
Low Power Mode (LP Mode): 100 µA Output
Power Switch Mode: Acts like a Load Switch
1 A Synchronous Constant-on-Time DC/DC Step Down
Converter
Applications
Personal Computers and Servers
PC Peripherals
Consumer Electronics
Data Communications Equipment
Handheld and Portable Electronics
Smartphones and Fitness Bands
Notebook and Tablet PCs
Power Management Switches
Power Sequencing with Complex Analog Control
Power Plane Component Size Reduction Project
LED Driver
Haptic Motor Driver
Datasheet
18-Sep-2019
Revision 3.3
1 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Contents
General Description.................................................................................................................................................................1
Key Features.............................................................................................................................................................................1
Applications .............................................................................................................................................................................1
1 Block Diagram ....................................................................................................................................................................10
2 Pinout ..................................................................................................................................................................................11
2.1 Pin Configuration - MSTQFN- 29L ......................................................................................................................11
3 Characteristics ...................................................................................................................................................................15
3.1 Absolute Maximum Ratings .................................................................................................................................15
3.2 Electrostatic Discharge Ratings ...........................................................................................................................15
3.3 Recommended Operating Conditions .................................................................................................................15
3.4 Electrical Characteristics ......................................................................................................................................15
3.5 Timing Characteristics ..........................................................................................................................................27
3.6 OSC Characteristics .............................................................................................................................................30
3.7 Analog Comparator Characteristics .....................................................................................................................32
3.8 Low Drop Out “LDO” Regulator Electrical Characteristics ...................................................................................34
3.9 DC/DC Converter Electrical Characteristics .........................................................................................................36
4 User Programmability ........................................................................................................................................................38
5 IO Pins .................................................................................................................................................................................39
5.1 Input Modes .........................................................................................................................................................39
5.2 Output Modes .......................................................................................................................................................40
5.3 Pull-Up/Down Resistors .......................................................................................................................................40
5.4 IO Register Settings .............................................................................................................................................40
5.5 GPI Structure .......................................................................................................................................................44
5.6 Matrix OE IO Structure .........................................................................................................................................45
5.7 IO Structure ..........................................................................................................................................................47
6 Connection Matrix ..............................................................................................................................................................48
6.1 Matrix Input Table ...............................................................................................................................................49
6.2 Matrix Output Table .............................................................................................................................................51
6.3 Connection Matrix Virtual Inputs ..........................................................................................................................54
6.4 Connection Matrix Virtual Outputs .......................................................................................................................54
7 Combination Function Macrocells ....................................................................................................................................55
7.1 2-Bit LUT or D Flip-Flop Macrocells .....................................................................................................................55
7.2 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells .............................................................................................59
7.3 3-Bit LUT or Pipe Delay/Ripple Counter Macrocell ..............................................................................................67
7.4 3-Bit LUT or 8-Bit Counter/Delay Macrocells .......................................................................................................71
7.5 CNT/DLY Timing Diagrams ..................................................................................................................................80
7.6 Wake and Sleep Controller ..................................................................................................................................87
8 Combinatorial Logic ...........................................................................................................................................................89
8.1 4-bit LUT with Two Outputs ..................................................................................................................................89
9 Analog Comparators ..........................................................................................................................................................91
9.1 ACMP0 Block Diagram and Register Settings .....................................................................................................92
9.2 ACMP1 Block Diagram and Register Settings .....................................................................................................94
9.3 ACMP2 Block Diagram and Register Settings .....................................................................................................96
9.4 ACMP3 Block Diagram and Register Settings .....................................................................................................98
9.5 ACMPs Typical Performance .............................................................................................................................100
10 Pipe Delay .......................................................................................................................................................................101
11 Programmable Delay/Edge Detector ............................................................................................................................101
11.1 Programmable Delay Timing Diagram - Edge Detector Output ......................................................................101
12 Additional Logic Functions ...........................................................................................................................................103
12.1 Deglitch Filter/Edge Detector ...........................................................................................................................103
13 RTC Binary Counter .......................................................................................................................................................104
13.1 RTC Binary Counter Shadow Buffer ................................................................................................................105
14 Voltage Reference ..........................................................................................................................................................106
14.1 Voltage Reference Overview ...........................................................................................................................106
14.2 Vref Selection Table ........................................................................................................................................106
15 Analog Temperature Sensor .........................................................................................................................................107
Datasheet
18-Sep-2019
Revision 3.3
2 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
16 Clocking ..........................................................................................................................................................................109
16.1 OSC General Description .................................................................................................................................109
16.2 Low Power OSC (1.73 kHz) .............................................................................................................................109
16.3 Configurable OSC(25 kHz/2MHz) ....................................................................................................................110
16.4 Oscillator Power-On Delay ...............................................................................................................................110
16.5 Oscillator Accuracy ..........................................................................................................................................113
17 Power-On Reset ..............................................................................................................................................................115
17.1 General Operation ............................................................................................................................................115
17.2 POR Sequence ................................................................................................................................................116
17.3 Macrocells Output States During POR Sequence ...........................................................................................116
17.4 External Reset ..................................................................................................................................................118
18 Asynchronous State Machine Macrocell .....................................................................................................................122
18.1 ASM Macrocell Overview .................................................................................................................................122
18.2 ASM Inputs .......................................................................................................................................................123
18.3 ASM Outputs ....................................................................................................................................................125
18.4 Basic ASM Timing ............................................................................................................................................127
18.5 Asynchronous State Machines vs. Synchronous State Machines ...................................................................127
18.6 ASM Power Consideration ...............................................................................................................................127
18.7 ASM Logical vs. Physical Design .....................................................................................................................128
18.8 ASM Special Case Timing Considerations ......................................................................................................128
19 I2C Serial Communications Macrocell .........................................................................................................................133
19.1 I2C Serial Communications Macrocell Overview .............................................................................................133
19.2 I2C Serial Communications Device Addressing ...............................................................................................133
19.3 I2C Serial General Timing ................................................................................................................................134
19.4 I2C Serial Communications Commands ..........................................................................................................134
19.5 I2C Serial Command Register Map .................................................................................................................138
20 Low Dropout Regulators ...............................................................................................................................................141
20.1 LDO Regulator Description ..............................................................................................................................141
20.2 Over-Current Limit and Short-Circuit Detection ...............................................................................................146
20.3 LDO Efficiency .................................................................................................................................................146
20.4 LDO Thermal Considerations ...........................................................................................................................146
20.5 Soft Start Function (SS) ...................................................................................................................................147
20.6 ACMPs: Under Voltage Lockout Capability, Power Good ................................................................................147
20.7 Regulator Stability Considerations ...................................................................................................................148
20.8 LDO Regulator Cold Start up ...........................................................................................................................148
20.9 LDO Regulator Hot Start up .............................................................................................................................148
20.10 Discharge Resistors .......................................................................................................................................148
20.11 Typical Application Circuit ..............................................................................................................................148
20.12 Typical Application Performance ....................................................................................................................149
21 1 A Synchronous DC/DC Step Down Converter ..........................................................................................................152
21.1 DC/DC Buck Converter Description .................................................................................................................152
21.2 Synchronous DC/DC Step Down Converter Block Diagram ............................................................................152
21.3 Typical Application Circuit ................................................................................................................................152
21.4 DC/DC Buck Converter Pinout Description ......................................................................................................153
21.5 Configurable Parameters .................................................................................................................................153
21.6 Output Voltage Selection .................................................................................................................................154
21.7 Switching Frequency Selection ........................................................................................................................154
21.8 Over-Current Protection Level Selection ..........................................................................................................154
21.9 DC/DC Thermal Shutdown ...............................................................................................................................155
21.10 DC/DC Under Voltage Lockout ......................................................................................................................155
21.11 Fault Signals ..................................................................................................................................................155
21.12 DC/DC Soft Start ............................................................................................................................................155
21.13 Constant-On-Time ..........................................................................................................................................155
21.14 DC/DC Continuous Conduction Mode (CCM) ................................................................................................156
21.15 DC/DC Discontinuous Conduction Mode (DCM) ...........................................................................................156
21.16 DC/DC Power Dissipation ..............................................................................................................................156
21.17 Layout Consideration .....................................................................................................................................158
Datasheet
18-Sep-2019
Revision 3.3
3 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
21.18 Typical Performance Characteristics .............................................................................................................166
22 Register Definitions .......................................................................................................................................................171
22.1 Register Map ....................................................................................................................................................171
23 Package Top Marking System Definition .....................................................................................................................201
23.1 MSTQFN 29L 3 mm x 3 mm x 0.55 mm 0.4P Package ...................................................................................201
24 Package Information ......................................................................................................................................................202
24.1 Package Outlines for MSTQFN 29L 3 mm x 3 mm 0.4P FC Package .............................................................202
24.2 MSTQFN Handling ...........................................................................................................................................203
24.3 Soldering Information .......................................................................................................................................203
25 Ordering Information .....................................................................................................................................................203
25.1 Tape and Reel Specifications ..........................................................................................................................203
25.2 Carrier Tape Drawing and Dimensions ..........................................................................................................203
26 Layout Guidelines ..........................................................................................................................................................205
26.1 MSTQFN 29L 3 mm x 3 mm x 0.55 mm 0.4P Package ...................................................................................205
Glossary................................................................................................................................................................................206
Revision History...................................................................................................................................................................209
Datasheet
18-Sep-2019
Revision 3.3
4 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Figures
Figure 1: Block Diagram...........................................................................................................................................................10
Figure 2: Steps to Create a Custom GreenPAK Device...........................................................................................................38
Figure 3: IO3 GPI Structure Diagram.......................................................................................................................................44
Figure 4: Matrix OE IO Structure Diagram...............................................................................................................................45
Figure 5: Matrix OE IO Structure Diagram...............................................................................................................................46
Figure 6: IO Structure Diagram................................................................................................................................................47
Figure 7: Connection Matrix.....................................................................................................................................................48
Figure 8: Connection Matrix Example......................................................................................................................................48
Figure 9: 2-bit LUT0 or DFF0...................................................................................................................................................55
Figure 10: 2-bit LUT1 or DFF1.................................................................................................................................................56
Figure 11: 2-bit LUT2 or DFF2.................................................................................................................................................56
Figure 12: DFF Polarity Operations..........................................................................................................................................59
Figure 13: 3-bit LUT0 or DFF3.................................................................................................................................................60
Figure 14: 3-bit LUT1 or DFF4.................................................................................................................................................60
Figure 15: 3-bit LUT2 or DFF5.................................................................................................................................................61
Figure 16: 3-bit LUT3 or DFF6.................................................................................................................................................61
Figure 17: 3-bit LUT4 or DFF7.................................................................................................................................................62
Figure 18: 3-bit LUT5 or DFF8.................................................................................................................................................62
Figure 19: DFF Polarity Operations with nReset......................................................................................................................66
Figure 20: DFF Polarity Operations with nSet..........................................................................................................................67
Figure 21: 3-bit LUT11/Pipe Delay/Ripple Counter..................................................................................................................69
Figure 22: Example: Ripple Counter Functionality...................................................................................................................70
Figure 23: 3-bit LUT6 or CNT/DLY0.........................................................................................................................................72
Figure 24: 3-bit LUT7 or CNT/DLY1.........................................................................................................................................73
Figure 25: 3-bit LUT8 or CNT/DLY2.........................................................................................................................................73
Figure 26: 3-bit LUT9 or CNT/DLY3.........................................................................................................................................74
Figure 27: 3-bit LUT10 or CNT/DLY4.......................................................................................................................................74
Figure 28: Delay Mode Timing Diagram...................................................................................................................................80
Figure 29: Counter Mode Timing Diagram with Reset Signal..................................................................................................80
Figure 30: Counter Mode Timing Diagram with SET Signal (only for DLY/CNT0)...................................................................81
Figure 31: One-Shot Function Timing Diagram........................................................................................................................82
Figure 32: Frequency Detection Mode Timing Diagram...........................................................................................................83
Figure 33: Edge Detection Mode Timing Diagram (Except DLY/CNT0) ..................................................................................84
Figure 34: Delay Mode Timing Diagram (Except DLY/CNT0)..................................................................................................85
Figure 35: Delay Mode Timing Diagram...................................................................................................................................86
Figure 36: Wake/Sleep Controller............................................................................................................................................87
Figure 37: Wake/Sleep Timing Diagram ..................................................................................................................................88
Figure 38: 4-bit LUT0 with Two Outputs...................................................................................................................................89
Figure 39: ACMP0 Block Diagram ...........................................................................................................................................92
Figure 40: ACMP1 Block Diagram ...........................................................................................................................................94
Figure 41: ACMP2 Block Diagram ...........................................................................................................................................96
Figure 42: ACMP3 Block Diagram ...........................................................................................................................................98
Figure 43: ACMPs Power-On Delay vs. VDD..........................................................................................................................................................100
Figure 44: Programmable Delay ............................................................................................................................................101
Figure 45: Edge Detector Output ...........................................................................................................................................101
Figure 46: Deglitch Filter/Edge Detector................................................................................................................................103
Figure 47: RTC Counter Macrocell.........................................................................................................................................104
Figure 48: RTC Counter Shadow Buffer Bits .........................................................................................................................105
Figure 49: Analog Temperature Sensor Structure Diagram...................................................................................................108
Figure 50: Low Power Oscillator Block Diagram....................................................................................................................109
Figure 51: Configurable OSC Block Diagram.........................................................................................................................110
Figure 52: Oscillator Startup Diagram....................................................................................................................................110
Figure 53: Oscillator Maximum Power-On Delay vs. VDD, T = +25 °C, OSC0 = 2 MHz .......................................................111
Figure 54: Oscillator Maximum Power-On Delay vs. VDD at T = 25 °C, OSC0 = 25 kHz......................................................112
Figure 55: Oscillator Maximum Power-On Delay vs. VDD at T = 25 °C, OSC1 = 1.73 kHz...................................................112
Figure 56: Oscillator Frequency vs. Temperature, OSC0 = 2 MHz........................................................................................113
Datasheet
18-Sep-2019
Revision 3.3
5 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Figure 57: Oscillator Frequency vs. Temperature, OSC0 = 25 kHz ....................................................................................... 113
Figure 58: Oscillator Frequency vs. Temperature, OSC1 = 1.73 kHz .................................................................................... 114
Figure 59: POR Sequence.....................................................................................................................................................116
Figure 60: Internal Macrocell States during POR Sequence..................................................................................................117
Figure 61: Power-Down..........................................................................................................................................................118
Figure 62: External Reset Sequence (Level Sensitive)..........................................................................................................119
Figure 63: External Reset Sequence (Rising Edge Detect)...................................................................................................120
Figure 64: External Reset Sequence (Falling Edge Detect)...................................................................................................121
Figure 65: Asynchronous State Machine State Transitions ...................................................................................................122
Figure 66: Asynchronous State Machine ...............................................................................................................................123
Figure 67: Asynchronous State Machine Inputs.....................................................................................................................124
Figure 68: Rising Edge State Transition Selection (for Each State X)...................................................................................124
Figure 69: Maximum 3 State Transitions into Given State.....................................................................................................125
Figure 70: Maximum 7 State Transitions out of a Given State...............................................................................................125
Figure 71: Connection Matrix Output RAM ............................................................................................................................126
Figure 72: State Transition.....................................................................................................................................................127
Figure 73: State Transition Timing.........................................................................................................................................127
Figure 74: State Transition.....................................................................................................................................................127
Figure 75: State Transition Timing and Power Consumption.................................................................................................128
Figure 76: State Transition.....................................................................................................................................................128
Figure 77: State Transition Pulse Input Timing......................................................................................................................129
Figure 78: State Transition - Competing Inputs......................................................................................................................129
Figure 79: State Transition Timing - Competing Inputs Indeterminate...................................................................................129
Figure 80: State Transition Timing - Competing Inputs Determinable ...................................................................................130
Figure 81: State Transition - Sequential.................................................................................................................................130
Figure 82: State Transition - Sequential Timing.....................................................................................................................130
Figure 83: State Transition - Closed Cycling..........................................................................................................................131
Figure 84: State Transition - Closed Cycling Timing..............................................................................................................131
Figure 85: State Transition - Rising Edge Transition..............................................................................................................131
Figure 86: State Transition - Rising Edge Transition Timing..................................................................................................132
Figure 87: Basic Command Structure....................................................................................................................................134
Figure 88: I2C General Timing Characteristics ......................................................................................................................134
Figure 89: Byte Write Command, R/W = 0.............................................................................................................................135
Figure 90: Sequential Write Command, R/W = 0...................................................................................................................135
Figure 91: Current Address Read Command, R/W = 1..........................................................................................................136
Figure 92: Random Read Command .....................................................................................................................................136
Figure 93: Sequential Read Command..................................................................................................................................137
Figure 94: Reset Command Timing .......................................................................................................................................140
Figure 95: LDO0 Regulator Block Diagram............................................................................................................................141
Figure 96: LDO1 Regulator Block Diagram............................................................................................................................142
Figure 97: LDO2 Regulator Block Diagram............................................................................................................................143
Figure 98: LDO3 Regulator Block Diagram............................................................................................................................144
Figure 99: LDO Typical Application Circuit.............................................................................................................................148
Figure 100: LDO Load Regulation, HIGH POWER Mode, T = 25 °C, VDD = 5 V, VOUT = 4.35 V........................................149
Figure 101: LDO Load Regulation, LOW POWER Mode, T = 25 °C, VDD = 5 V, VOUT = 4.35 V.........................................149
Figure 102: LDO Dropout Voltage vs. VIN .............................................................................................................................150
Figure 103: LDO High Power Mode VOUT vs. VIN, T = 25 °C, VDD = 5 V ............................................................................150
Figure 104: LDO P-Channel ON Resistance RDSon vs. VIN, Power Switch Mode, T = 25 °C .............................................151
Figure 105: DC/DC Block Diagram ........................................................................................................................................152
Figure 106: DC/DC Typical Application Circuit.......................................................................................................................153
Figure 107: DC/DC Recommended PCB Layout...................................................................................................................157
Figure 108: DC/DC Converter Current Loops........................................................................................................................158
Figure 109: DC/DC Converter AC and DC Loops..................................................................................................................159
Figure 110: AC Loop..............................................................................................................................................................160
Figure 111: DC Switch and Inductor ......................................................................................................................................160
Figure 112: DC Switch and Inductor ......................................................................................................................................161
Figure 113: LDO_VIN and LDO_VOUT Current Flow............................................................................................................162
Datasheet
18-Sep-2019
Revision 3.3
6 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Figure 114: LDO Decoupling..................................................................................................................................................162
Figure 115: LDO_AGND Layout.............................................................................................................................................163
Figure 116: Ground Source for LDO and Buck......................................................................................................................164
Figure 117: SLG46585 Ground Layout..................................................................................................................................165
Figure 118: Digital Signals PCB Recommendation................................................................................................................166
Figure 119: Efficiency vs. Output Current ..............................................................................................................................166
Figure 120: Output Voltage vs. Load Current.........................................................................................................................167
Figure 121: Load Transient Response...................................................................................................................................167
Figure 122: VIN Power Up without Load................................................................................................................................168
Figure 123: VIN Power Up with 400 mA Load........................................................................................................................168
Figure 124: VIN Power Up with 1A Load................................................................................................................................169
Figure 125: Low IQ Current vs. Input Voltage........................................................................................................................169
Figure 126: Output Ripple vs. IOUT = 100 mA ......................................................................................................................170
Figure 127: Output Ripple vs. IOUT = 1 A .............................................................................................................................170
Datasheet
18-Sep-2019
Revision 3.3
7 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Tables
Table 1: Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 2: Pin Type Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4: Electrostatic Discharge Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5: Recommended Operating Conditions for SLG46585 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6: EC at T = -40 °C to +85 °C, VDD = 2.5 V to 5.5 V Unless Otherwise Noted . . . . . . . . . . . . . . . . . . . . 15
Table 7: EC of the I2C Pins at T = -40 °C to +85 °C, VDD = 2.5 V to 5.5 V Unless Otherwise Noted. . . . . . . . . . . . . 24
Table 8: I2C Pins Timing Characteristics at T = -40 °C to +85 °C, VDD = 2.5 V to 5.5 V Unless Otherwise Noted . . . . . . 25
Table 9: Asynchronous State Machine EC at T = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 10: Typical Current Estimated for Each Macrocell at T = -40 °C to +85 °C . . . . . . . . . . . . . . . . . . . . . . 26
Table 11: Typical Delay Estimated for Each Macrocell at T = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 12: Typical Propagations Delays and Pulse Widths at T = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 13: Typical Filter Rejection Pulse Width at T = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 14: Typical Counter/Delay Offset Measurements at T = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 15: 25 kHz RC OSC0 Frequency Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 16: 25 kHz RC OSC0 Frequency Error (Error Calculated Relative to Nominal Value) . . . . . . . . . . . . . . . . . 30
Table 17: 2 MHz RC OSC0 Frequency Limits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 18: 2 MHz RC OSC0 Frequency Error (Error Calculated Relative to Nominal Value) . . . . . . . . . . . . . . . . . 30
Table 19: 1.73 kHz RC OSC1 Frequency Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 20: 1.73 kHz RC OSC1 Frequency Error (Error Calculated Relative to Nominal Value) . . . . . . . . . . . . . . . . 31
Table 21: Oscillators Power-On Delay at T = 25 °C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 22: OSC Power-On Delay, at T = 25 °C, Fast Start-up Time Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 23: Analog Comparator EC at T = -40 °C to +85 °C, VDD = 2.5 V to 5.5 V Unless Otherwise Noted . . . . . . . . . 32
Table 24: LDO Current Consumption at T = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 25: LDO Regulator Thermal Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 26: LDO HP MODE EC at T = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 27: LDO LP MODE EC at T = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 28: LDO Power Switch Mode EC at T = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 29: DC/DC Converter EC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 30: IO0 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 31: IO1 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 32: IO2 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 33: IO3 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 34: SCL Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 35: SDA Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 36: IO4 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 37: IO5 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 38: IO6 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 39: Matrix Input Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 40: Matrix Output Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 41: Connection Matrix Virtual Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 42: 2-bit LUT0 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 43: 2-bit LUT1 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 44: 2-bit LUT2 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 45: 2-bit LUT Standard Digital Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 46: DFF0 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 47: DFF1 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 48: DFF2 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 49: 3-bit LUT0 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 50: 3-bit LUT1 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 51: 3-bit LUT2 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 52: 3-bit LUT3 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 53: 3-bit LUT4 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 54: 3-bit LUT5 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 55: 3-bit LUT Standard Digital Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 56: DFF3 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 57: DFF4 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 58: DFF5 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 59: DFF6 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 60: DFF7 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 61: DFF8 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Datasheet
18-Sep-2019
Revision 3.3
8 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 62: 3-bit LUT11 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 63: Pipe Delay Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 64: 3-bit LUT6 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 65: 3-bit LUT7 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 66: 3-bit LUT8 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 67: 3-bit LUT9 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 68: 3-bit LUT10 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 69: 3-bit LUT Standard Digital Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 70: CNT/DLY0 Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 71: CNT/DLY1 Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 72: CNT/DLY2 Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 73: CNT/DLY3 Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 74: CNT/DLY4 Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 75: DLY/CNT Polarity Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 76: 4-bit LUT0 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 77: 4-bit LUT Standard Digital Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 78: Gain Divider Input Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 79: ACMP0 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 80: ACMP1 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 81: ACMP2 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 82: ACMP3 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 83: Programmable Delay Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 84: Deglitch Filter Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 85: Shadow Buffer Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 86: Vref Selection Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 87: Temperature Sensor Voltage for VDD = 2.5 V to 5.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 88: Oscillator Operation Mode Configuration Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 89: External Reset Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 90: ASM Editor - Connection Matrix Output RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 91: Read/Write Protection Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 92: RAM Array Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 93: LDO Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 94: LDO0 Ramp Rate Selection Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 95: LDO1 Ramp Rate Selection Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 96: LDO2 Ramp Rate Selection Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 97: LDO3 Ramp Rate Selection Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 98: DC/DC Output Voltage Bit Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 99: DC/DC Switching Frequency Bit Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 100: DC/DC Current Limit Bit Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 101: DC/DC Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 102: DC/DC Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 103: Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Datasheet
18-Sep-2019
Revision 3.3
9 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
1
Block Diagram
IO3
DC_CCM
DC_VIN
DC_INT
DC_SW
DC_VOSNS
IO0
Combination Function
Macrocells
1 A
150 mA
LDO3
DC/DC Converter
AGND0
LDO3_VOUT
LDO2/3_VIN
LDO2_VOUT
LDO1_VOUT
LDO0/1_VIN
LDO0_VOUT
2-bit
LUT2_0
or DFF0
2-bit
LUT2_1
or DFF1
Additional Logic Functions
ACMP0
IO5
FILTER_0
with Edge Detect
FILTER_1
2-bit
LUT2_2
or DFF2
3-bit
LUT3_0
or DFF3
with Edge Detect
3-bit
LUT3_2
or DFF5
3bit
LUT3_1
or DFF4
Oscillators
25kHz/2 MHz
1.73 kHz
IO6
150 mA
LDO2
ACMP1
3-bit
LUT3_4
or DFF7
3-bit
LUT3_3
or DFF6
Programmable
Delay with
Edge Detector
RTC
CNT
POR
3-bit
LUT3_6 or
CNT/DLY0
3-bit
LUT3_5
or DFF8
150 mA
LDO1
GND
ACMP2
Analog
Temperature
Sensor
Asynchronous
State Machine
8 states
3-bit
LUT3_7 or
CNT/DLY1
3-bit
LUT3_8 or
CNT/DLY2
IO1
I2C Serial
Communication
3-bit
LUT3_10or
CNT/DLY4
3-bit
LUT3_9 or
CNT/DLY3
4-bit
LUT4x2_0
ACMP3
3-bit
LUT3_11 or
Pipe Delay/
Ripple CNT
150 mA
LDO0
8 Byte RAM +
OTP Memory
Internal
Vref
AGND1
IO4
PGND
PGND
IO2
VDD
SCL
SDA
Figure 1: Block Diagram
Datasheet
18-Sep-2019
Revision 3.3
10 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
2
Pinout
2.1 PIN CONFIGURATION - MSTQFN- 29L
Pin #
1
Signal Name
Pin Functions
AGND0 (Note 3) Analog Ground for LDOs
2
IO5
IO6
GPIO/ACMP2+
25
IO0
3
GPIO with OE (Note 1)/ACMP3+
Ground
26
27
28
29
DC_CCM
NC
IO3
4
GND (Note 3)
IO1
5
GPIO/ACMP0+
6
AGND1 (Note 3) Analog Ground for DC/DC Converter
LDO1_VOUT
7
DC_INT
NC (Note 2)
NC (Note 2)
DC_VOSNS
DC_SW
Interrupt Output
No Connect
8
1
2
3
4
5
6
7
19
18
17
16
15
AGND0
IO5
IO4
24 23 22 21 20
29
9
No Connect
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Input Sense Pin
Switch Output
SDA
SCL
IO6
PGND (Note 3) DC/DC Power Ground
PGND (Note 3) DC/DC Power Ground
25
28
GND
VDD
DC_VIN (Note 4) Power Supply Input for DC/DC Converter
IO2
GPIO with OE (Note 1)/ACMP1+
Power Supply
IO1
IO2
VDD (Note 4)
SCL
26
8
27
10
I2C_SCL
14
12
AGND1
DC_INT
DC_VIN
PGND
11
SDA
I2C_SDA
9
13
IO4
GPIO with OE (Note 1)/EXT_Vref
LDO0 Output Voltage
LDO0/LDO1 Input Voltage
LDO2 Output Voltage
LDO2/LDO3 Input Voltage
LDO3 Output Voltage
GPIO with OE (Note 1)/EXT_CLK
CCM Output Indicator
No Connect
LDO0_VOUT
LDO0/1_VIN
LDO2_VOUT
LDO2/3_VIN
LDO3_VOUT
IO0
MSTQFN-29
(Top View)
DC_CCM
NC (Note 2)
IO3
GPI
LDO1_VOUT
LDO1 Output Voltage
Note 1 General Purpose IO's with OE can be used to implement bidirec-
tional signals under user control via Connection Matrix to OE signal in
IO structure.
Note 2 Manufacture test pin, do not connect.
Note 3 All GND, AGND0, AGND1, and PGND pins must be connected
together externally.
Note 4 DC_VIN and VDD pins must be connected together externally.
Table 1: Functional Pin Description
STQFN
29L Pin #
Pin
Name
Signal
Name
Input
Options
Output
Options
Function
Analog ground for LDO. All GND, AGND0, AGND1, and PGND pins must be connected together
externally.
1
AGND0
DigitalInputwithoutSchmitt
Push-Pull (1x) (2x)
Trigger
General Purpose IO
Digital Input
with Schmitt Trigger
Open-Drain NMOS
(1x) (2x)
IO5
2
IO5
Low Voltage
Digital Input
Open-Drain PMOS
(1x) (2x)
Analog Comparator 2
Positive Input
ACMP2+
Analog
--
Datasheet
18-Sep-2019
Revision 3.3
11 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 1: Functional Pin Description (Continued)
STQFN
29L Pin #
Pin
Name
Signal
Name
Input
Options
Output
Options
Function
Digital Input without
Schmitt Trigger
Push-Pull (1x) (2x)
General Purpose IO
with OE (Note 1)
IO6
Digital Input
with Schmitt Trigger
Open-Drain NMOS
(1x) (2x)
3
4
IO6
Low Voltage Digital Input
--
Analog Comparator 3
Positive Input
ACMP3+
Analog
--
GND
Logic Ground. All GND, AGND0, AGND1, and PGND pins must be connected together externally.
Digital Input without
Push-Pull (1x) (2x)
Schmitt Trigger
General Purpose IO
Digital Input
with Schmitt Trigger
Open-Drain NMOS
(1x) (2x)
IO1
5
IO1
Open-Drain PMOS
(1x) (2x)
Low Voltage Digital Input
Analog
Analog Comparator 0
Positive Input
ACMP0+
--
Analog ground for internal control circuit. Connect this pin to Power GND plane on PCB. All GND,
AGND0, AGND1, and PGND pins must be connected together externally
6
7
AGND1
DC_INT
DC/DC Converter Interrupt Output. INT is an Open-Drain, asserted logic high digital output that be-
comes asserted within TINT(HIGH) when an over-current condition has been detected at the output.
INT becomes deasserted within TINT(LOW) when the over-current condition no longer persists.
8
9
NC
NC
Manufacture test pin, do not connect
Manufacture test pin, do not connect
10
DC_VOSNS DC/DC Converter Input sense pin for output voltage
DC/DC Converter Switch Output. Connect this pin to an external, low DCR inductor – seeApplications
Information for additional details
11
12
13
DC_SW
DC/DC Converter Power ground. Connect this pin to Power GND plane. All GND, AGND0, AGND1,
and PGND pins must be connected together externally
PGND
DC/DC Converter Power ground. Connect this pin to Power GND plane. All GND, AGND0, AGND1,
and PGND pins must be connected together externally
PGND
DC/DC Converter Supply input. Connect a 10 µF (or larger) low ESR capacitor from this pin to Power
GND plane. Capacitors used at VIN should be rated at 10 V or higher. DC_VIN and VDD pins must be
connected together externally.
14
DC_VIN
IO2
Digital Input without
Push-Pull (1x) (2x)
Schmitt Trigger
General Purpose IO
with OE (Note 1)
IO2
Digital Input
Open-Drain NMOS
(1x) (2x)
with Schmitt Trigger
15
Low Voltage Digital Input
--
Analog Comparator 1
Positive Input
ACMP1+
Analog
--
Datasheet
18-Sep-2019
Revision 3.3
12 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 1: Functional Pin Description (Continued)
STQFN
29L Pin #
Pin
Name
Signal
Name
Input
Options
Output
Options
Function
VDD
Power Supply
--
--
Analog Comparator 0
Positive Input
ACMP0+
Analog
--
Analog Comparator 0
Negative Input
ACMP0-
ACMP1-
ACMP2-
ACMP3-
SCL
Analog
Analog
Analog
Analog
--
--
--
--
--
16
VDD
Analog Comparator 1
Negative Input
Analog Comparator 2
Negative Input
Analog Comparator 3
Negative Input
Digital Input without
Schmitt Trigger
I2C Serial Clock
17
18
SCL
SDA
Digital Input
with Schmitt Trigger
SCL
SCL
SDA
I2C Serial Clock
I2C Serial Clock
I2C Serial Data
--
Low Voltage Digital Input
--
Digital Input without
Schmitt Trigger
Open-Drain NMOS
Digital Input
with Schmitt Trigger
SDA
SDA
I2C Serial Data
I2C Serial Data
--
Low Voltage Digital Input
--
Digital Input without
Schmitt Trigger
Push-Pull (1x) (2x)
General Purpose IO
with OE (Note 1)
IO4
Digital Input
with Schmitt Trigger
Open-Drain NMOS
(1x) (2x)
19
IO4
Low Voltage Digital Input
--
--
--
--
All Analog Comparators
Negative Input
EXT_Vref
LDO0_VOUT
ACMP3+
Analog
--
LDO0 Output Voltage
20
21
22
LDO0_VOUT
LDO0/1_VIN
LDO2_VOUT
Analog Comparator 3
Positive Input
Analog
LDO0/LDO1 Input
Voltage
LDO0/1_VIN
--
--
Analog Comparator 0
Positive Input
ACMP0+
LDO2_VOUT
ACMP3+
Analog
--
--
--
--
LDO2 Output Voltage
Analog Comparator 3
Positive Input
Analog
LDO2/LDO3 Input
Voltage
LDO2/3_VIN
--
--
23
24
LDO2/3_VIN
LDO3_VOUT
Analog Comparator 1
Positive Input
ACMP1+
Analog
--
--
--
LDO3_VOUT
LDO3 Output Voltage
Datasheet
18-Sep-2019
Revision 3.3
13 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 1: Functional Pin Description (Continued)
STQFN
29L Pin #
Pin
Name
Signal
Name
Input
Options
Output
Options
Function
Digital Input without
Schmitt Trigger
Push-Pull (1x) (2x)
General Purpose IO
with OE (Note 1)
Digital Input
with Schmitt Trigger
Open-Drain NMOS
(1x) (2x)
Low Voltage Digital Input
--
25
IO0
IO0
Digital Input without
Schmitt Trigger
--
EXT_CLK
Digital Input
with Schmitt Trigger
--
--
Low Voltage Digital Input
DC/DC Converter Continuous Conduction Mode Indicator Output. CCM is anOpen-Drain digitaloutput
thatbecomes LowwithinTCCM(Low) whentheloadingconditions ontheoutput of theconverter switches
into continuous conduction mode(ccm). The CCM output continues to toggle when the converter is in
non-ccm mode.
26
27
DC_CCM
NC
Manufacture test pin, do not connect
Digital Input without
--
Schmitt Trigger
28
29
IO3
IO3
General Purpose Input
LDO1 Output Voltage
Digital Input
with Schmitt Trigger
--
Low Voltage Digital Input
--
--
--
LDO1_VOUT
LDO1_VOUT
Note 1 General Purpose IO's with OE can be used to implement bidirectional signals under user control via Connection Matrix
to OE signal in IO structure.
Table 2: Pin Type Definitions
Pin Type
AGND0
AGND1
IO
Description
Analog Ground for LDO
Analog Ground for DC/DC Converter
Input/Output
GND
Ground
NC
No Connect
DC_INT
DC_VOSNS
DC_SW
DC_VIN
DC_CCM
PGND
DC/DC Converter Interrupt Output
DC/DC Converter Input Sense Pin for Output Voltage
DC/DC Converter Switch Output
DC/DC Converter Supply Input
DC/DC Converter Continuous Conduction Mode Indicator Output
DC/DC Converter Power Ground
Power Supply
VDD
SCL
I2C Serial Clock
SDA
I2C Serial Data
LDO_VIN
LDO_VOUT
LDO Input Voltage
LDO Output Voltage
Datasheet
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© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
3
Characteristics
3.1 ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, so functional operation of the device at these or any other conditions beyond those indicated in the operational
sections of the specification are not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect
device reliability.
Table 3: Absolute Maximum Ratings
Parameter
Supply Voltage on VDD relative to GND
DC Input Voltage
Condition
Min
Max
Unit
V
-0.3
7
GND - 0.5 V VDD + 0.5 V
V
--
TJ = 85 °C
TJ = 110 °C
TJ = 85 °C
TJ = 110 °C
73
mA
mA
mA
mA
Maximum Average or DC
Current Through VDD Pin (Per chip side)
(Note 1)
--
35
--
152
Maximum Average or DC
Current ThroughGNDPin(Per chipside)
(Note 1)
--
72
Current at Input Pin
Input leakage (Absolute Value)
Storage Temperature Range
Junction Temperature
-1.0
--
1.0
1000
150
mA
nA
°C
-65
--
150
°C
Moisture Sensitivity Level
1
Note 1 The GreenPAK’s power rails are divided in two sides. IOs 0, 1, 2, 3, 4, and 5 are connected to one side, IO 6, SCL, and
SDA to another.
3.2 ELECTROSTATIC DISCHARGE RATINGS
Table 4: Electrostatic Discharge Ratings
Parameter
Min
2000
1300
Max
--
Unit
V
ESD Protection (Human Body Model)
ESD Protection (Charged Device Model)
--
V
3.3 RECOMMENDED OPERATING CONDITIONS
Table 5: Recommended Operating Conditions for SLG46585
Parameter
Condition
Min
2.5
-40
Max
5.5
85
Unit
V
Supply Voltage (VDD
)
Operating Temperature
°C
Maximal Voltage Applied to any PIN in High
Impedance State
VDD+
0.3
--
0.1
0
V
µF
V
Capacitor Value at VDD
--
Allowable Input Voltage at Analog
Pins
Analog Input Voltage HIGH-Level
VDD
3.4 ELECTRICAL CHARACTERISTICS
Table 6: EC at T = -40 °C to +85 °C, VDD = 2.5 V to 5.5 V Unless Otherwise Noted
Parameter Description Condition
Min
Typ
3.3
Max
Unit
VDD
Supply Voltage (Note 1)
2.5
5.5
V
Datasheet
CFR0011-120-00
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Revision 3.3
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© 2019 Dialog Semiconductor
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 6: EC at T = -40 °C to +85 °C, VDD = 2.5 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
Unit
VPP
Programming Voltage
7.25
7.50
7.75
V
Analog Input Common Mode
Range
VAIR
Negative ACMP Input
0
--
--
--
--
--
--
--
1.2
V
V
V
V
V
V
V
0.7x
VDD
VDD
+
Logic Input (Note 2)
0.3
0.8x
VDD
VDD
+
VIH
HIGH-Level Input Voltage
LOW-Level Input Voltage
Logic Input with Schmitt Trigger
Low-Level Logic Input (Note 2)
Logic Input (Note 2)
0.3
VDD
+
1.25
0.3
GND-
0.3
0.3x
VDD
GND-
0.3
0.2x
VDD
VIL
Logic Input with Schmitt Trigger
Low-Level Logic Input (Note 2)
GND-
0.3
0.5
VDD = 2.5 V +/- 8%
VDD = 3.3 V +/- 10%
VDD = 5 V +/- 10%
0.4
0.5
0.7
0.6
0.7
1.0
0.8
0.9
1.2
V
V
V
Schmitt Trigger Hysteresis
Voltage
VHYS
Datasheet
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© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 6: EC at T = -40 °C to +85 °C, VDD = 2.5 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
Unit
Push-Pull, 1x Drive, IOH = 1 mA,
2.39
--
--
V
VDD = 2.5 V (Note 3)
Push-Pull, 1x Drive, IOH = 1 mA,
2.60
2.72
3.04
3.36
4.16
4.69
5.20
2.44
2.65
2.86
3.17
3.48
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
V
V
V
V
V
V
V
V
V
V
V
V
VDD = 2.7 V (Note 3)
Push-Pull, 1x Drive, IOH = 3 mA,
VDD = 3 V (Note 3)
Push-Pull, 1x Drive, IOH = 3 mA,
VDD = 3.3 V (Note 3)
Push-Pull, 1x Drive, IOH = 3 mA,
VDD = 3.6 V (Note 3)
Push-Pull, 1x Drive, IOH = 5 mA,
VDD = 4.5 V (Note 3)
VOH
HIGH-Level Output Voltage
Push-Pull, 1x Drive, IOH = 5 mA,
VDD = 5 V (Note 3)
Push-Pull, 1x Drive, IOH = 5 mA,
VDD = 5.5 V (Note 3)
Push-Pull, 2x Drive, IOH = 1 mA,
V
DD = 2.5 V (Note 3)
Push-Pull, 2x Drive, IOH = 1 mA,
DD = 2.7 V (Note 3)
V
Push-Pull, 2x Drive, IOH = 3 mA,
VDD = 3 V (Note 3)
Push-Pull, 2x Drive, IOH = 3 mA,
VDD = 3.3 V (Note 3)
Push-Pull, 2x Drive, IOH = 3 mA,
VDD = 3.6 V (Note 3)
Datasheet
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Revision 3.3
17 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 6: EC at T = -40 °C to +85 °C, VDD = 2.5 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
Unit
Push-Pull, 2x Drive, IOH = 5 mA,
4.32
--
--
V
VDD = 4.5 V (Note 3)
Push-Pull, 2x Drive, IOH = 5 mA,
4.83
5.34
2.39
2.60
2.72
3.05
3.36
4.16
4.69
5.21
2.44
2.65
2.86
3.17
3.48
4.32
4.83
5.34
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VDD = 5 V (Note 3)
Push-Pull, 2x Drive, IOH = 5 mA,
VDD = 5.5 V (Note 3)
PMOS OD, 1x Drive, IOH = 1 mA,
VDD = 2.5 V (Note 3)
PMOS OD, 1x Drive, IOH = 1 mA,
VDD = 2.7 V (Note 3)
PMOS OD, 1x Drive, IOH = 3 mA,
VDD = 3 V (Note 3)
PMOS OD, 1x Drive, IOH = 3 mA,
VDD = 3.3 V (Note 3)
PMOS OD, 1x Drive, IOH = 3 mA,
VDD = 3.6 V (Note 3)
PMOS OD, 1x Drive, IOH = 5 mA,
V
DD = 4.5 V (Note 3)
PMOS OD, 1x Drive, IOH = 5 mA,
DD = 5 V м
VOH
HIGH-Level Output Voltage
V
PMOS OD, 1x Drive, IOH = 5 mA,
VDD = 5.5 V (Note 3)
PMOS OD, 2x Drive, IOH=1 mA,
VDD = 2.5 V (Note 3)
PMOS OD, 2x Drive, IOH=1 mA,
VDD = 2.7 V (Note 3)
PMOS OD, 2x Drive, IOH = 3 mA,
VDD = 3 V (Note 3)
PMOS OD, 2x Drive, IOH = 3 mA,
VDD = 3.3 V (Note 3)
PMOS OD, 2x Drive, IOH = 3 mA,
VDD = 3.6 V (Note 3)
PMOS OD, 2x Drive, IOH = 5 mA,
VDD = 4.5 V (Note 3)
PMOS OD, 2x Drive, IOH = 5 mA,
VDD = 5 V (Note 3)
PMOS OD, 2x Drive, IOH = 5 mA,
VDD = 5.5 V (Note 3)
Datasheet
18-Sep-2019
Revision 3.3
18 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 6: EC at T = -40 °C to +85 °C, VDD = 2.5 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
Unit
Push-Pull, 1x Drive, IOL =1 mA,
--
--
0.10
V
VDD = 2.5 V (Note 3)
Push-Pull, 1x Drive, IOL =1 mA,
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
0.09
0.26
0.24
0.22
0.33
0.31
0.29
0.05
0.05
0.13
0.12
0.11
0.16
0.15
0.15
0.05
0.05
0.13
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VDD = 2.7 V (Note 3)
Push-Pull, 1x Drive, IOL = 3 mA,
VDD = 3 V (Note 3)
Push-Pull, 1x Drive, IOL =3 mA,
VDD = 3.3 V (Note 3)
Push-Pull, 1x Drive, IOL = 3 mA,
VDD = 3.6 V (Note 3)
Push-Pull, 1x Drive, IOL = 5 mA,
VDD = 4.5 V (Note 3)
Push-Pull, 1x Drive, IOL = 5 mA,
VDD = 5 V (Note 3)
Push-Pull, 1x Drive, IOL = 5 mA,
VDD = 5.5 V (Note 3)
Push-Pull, 2x Drive, IOL = 1 mA,
V
DD = 2.5 V (Note 3)
Push-Pull, 2x Drive, IOL = 1 mA,
DD = 2.7 V (Note 3)
LOW-Level Output Voltage
VOL
V
Push-Pull, 2x Drive, IOL = 3 mA,
VDD = 3 V (Note 3)
Push-Pull, 2x Drive, IOL = 3 mA,
VDD = 3.3 V (Note 3)
Push-Pull, 2x Drive, IOL = 3 mA,
VDD = 3.6 V (Note 3)
Push-Pull, 2x Drive, IOL = 5 mA,
VDD = 4.5 V (Note 3)
Push-Pull, 2x Drive, IOL = 5 mA,
VDD = 5 V (Note 3)
Push-Pull, 2x Drive, IOL = 5 mA,
VDD = 5.5 V (Note 3)
NMOS OD, 1x Drive, IOL=1 mA,
VDD = 2.5 V (Note 3)
NMOS OD, 1x Drive, IOL= 1 mA,
VDD = 2.7 V (Note 3)
NMOS OD, 1x Drive, IOL= 3 mA,
VDD = 3 V (Note 3)
Datasheet
18-Sep-2019
Revision 3.3
19 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 6: EC at T = -40 °C to +85 °C, VDD = 2.5 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
Unit
NMOS OD, 1x Drive, IOL= 3 mA,
--
--
0.12
V
VDD = 3.3 V (Note 3)
NMOS OD, 1x Drive, IOL=3 mA,
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
0.11
0.17
0.16
0.16
0.03
0.03
0.08
0.07
0.07
0.12
0.12
0.11
V
V
V
V
V
V
V
V
V
V
V
V
VDD = 3.6 V (Note 3)
NMOS OD, 1x Drive, IOL= 5 mA,
VDD = 4.5 V (Note 3)
NMOS OD, 1x Drive, IOL=5 mA,
VDD = 5 V (Note 3)
NMOS OD, 1x Drive, IOL=5 mA,
VDD = 5.5 V (Note 3)
NMOS OD, 2x Drive, IOL=1 mA,
VDD = 2.5 V (Note 3)
NMOS OD, 2x Drive, IOL=1 mA,
VOL
LOW-Level Output Voltage
VDD = 2.7 V (Note 3)
NMOS OD, 2x Drive, IOL= 3 mA,
VDD = 3 V (Note 3)
NMOS OD, 2x Drive, IOL= 3 mA,
V
DD = 3.3 V (Note 3)
NMOS OD, 2x Drive, IOL= 3 mA,
DD = 3.6 V (Note 3)
V
NMOS OD, 2x Drive, IOL= 5 mA,
VDD = 4.5 V (Note 3)
NMOS OD, 2x Drive, IOL= 5 mA,
VDD = 5 V (Note 3)
NMOS OD, 2x Drive, IOL= 5 mA,
VDD = 5.5 V (Note 3)
Push-Pull, 1x Drive,
VOH = VDD - 0.2
1.81
1.97
--
--
--
--
mA
mA
VDD = 2.5 V (Note 3)
Push-Pull, 1x Drive,
V
OH = VDD - 0.2
VDD = 2.7 V (Note 3)
Push-Pull, 1x Drive,
VOH = 2.4 V, VDD = 3 V (Note 3)
HIGH-Level Output Current
IOH
5.78
8.76
--
--
--
--
--
--
--
--
mA
mA
mA
mA
Push-Pull, 1x Drive,
VOH = 2.4 V, VDD = 3.3 V (Note 3)
Push-Pull, 1x Drive,
VOH = 2.4 V, VDD = 3.6 V (Note 3)
11.75
20.77
Push-Pull, 1x Drive,
VOH = 2.4 V, VDD = 4.5 V (Note 3)
Datasheet
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Revision 3.3
20 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 6: EC at T = -40 °C to +85 °C, VDD = 2.5 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
Unit
Push-Pull, 1x Drive,
VOH = 2.4 V, VDD = 5 V (Note 3)
25.45
--
--
mA
Push-Pull, 1x Drive,
VOH = 2.4V, VDD = 5.5 V (Note 3)
29.65
3.48
--
--
--
--
mA
mA
Push-Pull, 2x Drive,
V
OH = VDD - 0.2
VDD = 2.5 V (Note 3)
Push-Pull, 2x Drive,
V
OH = VDD - 0.2
3.77
--
--
mA
VDD = 2.7 V (Note 3)
Push-Pull, 2x Drive,
VOH = 2.4 V, VDD = 3 V (Note 3)
11.05
16.74
22.44
39.54
48.25
55.92
--
--
--
--
--
--
--
--
--
--
--
--
mA
mA
mA
mA
mA
mA
Push-Pull, 2x Drive,
VOH = 2.4 V, VDD = 3.3 V (Note 3)
Push-Pull, 2x Drive,
VOH = 2.4 V, VDD = 3.6 V (Note 3)
Push-Pull, 2x Drive,
VOH = 2.4 V, VDD = 4.5 V (Note 3)
Push-Pull, 2x Drive,
VOH = 2.4 V, VDD = 5 V (Note 3)
IOH
HIGH-Level Output Current
Push-Pull, 2x Drive,
VOH = 2.4 V, VDD = 5.5 V (Note 3)
PMOS OD, 1x Drive,
VOH = VDD - 0.2
1.81
1.97
--
--
--
--
mA
mA
VDD = 2.5 V (Note 3)
PMOS OD, 1x Drive,
VOH = VDD - 0.2
VDD = 2.7 V (Note 3)
PMOS OD, 1x Drive,
5.79
8.76
--
--
--
--
--
--
--
--
--
--
--
--
mA
mA
mA
mA
mA
mA
V
OH = 2.4 V, VDD = 3 V (Note 3)
PMOS OD, 1x Drive,
VOH = 2.4 V, VDD = 3.3 V (Note 3)
PMOS OD, 1x Drive,
VOH = 2.4 V, VDD = 3.6 V (Note 3)
11.76
20.78
25.45
29.65
PMOS OD, 1x Drive,
VOH = 2.4 V, VDD = 4.5V (Note 3)
PMOS OD, 1x Drive,
VOH = 2.4 V, VDD = 5V (Note 3)
PMOS OD, 1x Drive,
VOH = 2.4 V, VDD = 5.5 V (Note 3)
Datasheet
18-Sep-2019
Revision 3.3
21 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 6: EC at T = -40 °C to +85 °C, VDD = 2.5 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
Unit
PMOS OD, 2x Drive,
VOH = VDD - 0.2
3.47
--
--
mA
VDD = 2.5 V (Note 3)
PMOS OD, 2x Drive,
V
OH = VDD - 0.2
3.76
--
--
mA
VDD = 2.7 V (Note 3)
PMOS OD, 2x Drive,
11.05
16.73
22.46
39.54
48.25
55.92
1.52
--
--
--
--
--
--
--
--
--
--
--
--
--
--
mA
mA
mA
mA
mA
mA
mA
V
OH = 2.4V, VDD = 3 V (Note 3)
PMOS OD, 2x Drive,
VOH = 2.4 V, VDD = 3.3 V (Note 3)
IOH
HIGH-Level Output Current
PMOS OD, 2x Drive,
VOH = 2.4 V, VDD = 3.6 V (Note 3)
PMOS OD, 2x Drive,
VOH = 2.4 V, VDD = 4.5 V (Note 3)
PMOS OD, 2x Drive,
VOH = 2.4 V, VDD = 5 V (Note 3)
PMOS OD, 2x Drive,
VOH = 2.4 V, VDD = 5.5 V (Note 3)
Push-Pull, 1x Drive, VOL = 0.15 V
VDD = 2.5 V (Note 3)
Push-Pull, 1x Drive, VOL = 0.15 V
1.63
4.45
4.82
5.16
6.02
6.40
6.74
3.05
3.26
8.87
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
VDD = 2.7 V (Note 3)
Push-Pull, 1x Drive, VOL = 0.4 V
VDD = 3 V (Note 3)
Push-Pull, 1x Drive, VOL = 0.4 V
VDD = 3.3 V (Note 3)
Push-Pull, 1x Drive, VOL = 0.4 V
VDD = 3.6 V (Note 3)
Push-Pull, 1x Drive, VOL = 0.4 V
IOL
LOW-Level Output Current
VDD = 4.5 V (Note 3)
Push-Pull, 1x Drive, VOL = 0.4 V
VDD = 5 V (Note 3)
Push-Pull, 1x Drive, VOL = 0.4 V
VDD = 5.5 V (Note 3)
Push-Pull, 2x Drive, VOL = 0.15 V
VDD = 2.5 V (Note 3)
Push-Pull, 2x Drive, VOL = 0.15 V
VDD = 2.7 V (Note 3)
Push-Pull, 2x Drive, VOL = 0.4 V
VDD = 3 V (Note 3)
Datasheet
18-Sep-2019
Revision 3.3
22 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 6: EC at T = -40 °C to +85 °C, VDD = 2.5 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
Unit
Push-Pull, 2x Drive, VOL = 0.4 V
9.58
--
--
mA
VDD = 3.3 V (Note 3)
Push-Pull, 2x Drive, VOL = 0.4 V
10.23
11.82
12.52
13.11
3.03
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
VDD = 3.6 V (Note 3)
Push-Pull, 2x Drive, VOL = 0.4 V
VDD = 4.5 V (Note 3)
Push-Pull, 2x Drive, VOL= 0.4 V
VDD = 5 V (Note 3)
Push-Pull, 2x Drive, VOL = 0.4 V
VDD = 5.5 V (Note 3)
NMOS OD, 1x Drive, VOL = 0.15 V
VDD = 2.5 V (Note 3)
NMOS OD, 1x Drive, VOL = 0.15 V
3.24
VDD = 2.7 V (Note 3)
NMOS OD, 1x Drive, VOL = 0.4 V
8.83
VDD = 3 V (Note 3)
NMOS OD, 1x Drive, VOL = 0.4 V
9.54
V
DD = 3.3 V (Note 3)
NMOS OD, 1x Drive, VOL = 0.4 V
DD = 3.6 V (Note 3)
IOL
LOW-Level Output Current
10.17
11.75
12.38
12.82
5.59
V
NMOS OD, 1x Drive, VOL = 0.4 V
VDD = 4.5 V (Note 3)
NMOS OD, 1x Drive, VOL = 0.4 V
VDD = 5 V (Note 3)
NMOS OD, 1x Drive, VOL = 0.4 V
VDD = 5.5 V (Note 3)
NMOS OD, 2x Drive, VOL = 0.15 V
VDD = 2.5 V (Note 3)
NMOS OD, 2x Drive, VOL = 0.15 V
5.76
VDD = 2.7 V (Note 3)
NMOS OD, 2x Drive, VOL = 0.4 V
16.1
VDD = 3 V (Note 3)
NMOS OD, 2x Drive, VOL = 0.4 V
16.6
VDD = 3.3 V (Note 3)
NMOS OD, 2x Drive, VOL = 0.4 V
16.95
VDD = 3.6 V (Note 3)
Datasheet
18-Sep-2019
Revision 3.3
23 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 6: EC at T = -40 °C to +85 °C, VDD = 2.5 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
Unit
NMOS OD, 2x Drive, VOL = 0.4 V
17.64
--
--
mA
VDD = 4.5 V (Note 3)
NMOS OD, 2x Drive, VOL = 0.4 V
IOL
LOW-Level Output Current
17.34
18.36
--
--
--
--
mA
mA
VDD = 5 V (Note 3)
NMOS OD, 2x Drive, VOL = 0.4 V
VDD = 5.5 V (Note 3)
TSU
Startup Time
From VDD rising past PONTHR
--
1.3
--
ms
V
PONTHR
Power-On Threshold
VDD Level Required to Start Up the Chip
1.34
1.55
1.74
VDD Level Required to Switch Off the
Chip
POFFTHR Power-Off Threshold
1.05
1.25
1.45
V
1 M Pull-up
748
85
8
1039
105
11
1378
130
14
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
pF
RPUP
Pull-up Resistance
100 k Pull-up
10 k Pull-up
1 M Pull-down
100 k Pull-down
10 k Pull-down
855
85
8
1046
105
11
1333
131
14
RPDWN
Pull-down Resistance
Input Capacitance
CIN
--
4
--
Minimum Pulse Width for the RTC‘s
Clock Input
TPW_RTC RTC Clock Pulse Width
1
--
--
µs
Note 1 DC or average current through any pin should not exceed value given in Absolute Maximum Conditions.
Note 2 No hysteresis.
Note 3 The GreenPAK’s power rails are divided in two sides. IOs 0, 1, 2, 3, 4, and 5 are connected to one side, IO 6, SCL, and
SDA to another.
Table 7: EC of the I2C Pins at T = -40 °C to +85 °C, VDD = 2.5 V to 5.5 V Unless Otherwise Noted
Fast-Mode
Fast-Mode Plus
Parameter Description
Condition
Unit
Min
Max
Min
Max
LOW-level Input
Voltage
VIL
-0.5
0.3xVDD
-0.5
0.3xVDD
V
V
V
HIGH-level Input
Voltage
VIH
0.7xVDD
0.05xVDD
5.5
--
0.7xVDD
5.5
--
HysteresisofSchmitt
VHYS
0.05xVDD
Trigger Inputs
(Open-Drain or open
collector) at 3mA sink
current
LOW-Level Output
Voltage 1
VOL1
0
0
0.4
0
0
0.4
V
V
VDD > 2 V
(Open-Drain or open
collector) at 2 mA sink
current
LOW-Level Output
Voltage 2
VOL2
0.2xVDD
0.2xVDD
V
DD ≤ 2 V
Datasheet
18-Sep-2019
Revision 3.3
24 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 7: EC of the I2C Pins at T = -40 °C to +85 °C, VDD = 2.5 V to 5.5 V Unless Otherwise Noted(Continued)
Fast-Mode
Fast-Mode Plus
Parameter Description
Condition
Unit
Min
Max
--
Min
12.6
16.1
17.6
--
Max
--
VOL = 0.4 V, VDD = 2.5 V
VOL = 0.4 V, VDD = 3.0 V
VOL = 0.4 V, VDD = 4.5 V
VOL = 0.6 V
3
3
3
6
mA
mA
mA
mA
--
--
LOW-Level Output
IOL
Current (Note 1)
--
--
--
--
Output Fall Time
from VIHmin to VILmax
(Note 1)
14x
(VDD/5.5 V)
10x
(VDD/5.5 V)
tof
250
50
120
50
ns
ns
Pulse Width of
Spikes that must be
suppressed by the
Input Filter
tSP
0
0
Input Current each
IO Pin
Ii
0.1xVDD < VI < 0.9xVDDmax
-10
--
+10
10
-10
--
+10
10
µs
Capacitance for
each IO Pin
Ci
pF
Note 1 Does not meet standard I2C specifications: tof = 20x(VDD/5.5 V) (min); For Fast-mode Plus IOL = 20 mA (min) at
VOL = 0.4 V.
Note 2 For Fast-mode Plus SDA pin must be configured as NMOS 2x Open-Drain, see Table 34.
Table 8: I2C Pins Timing Characteristics at T = -40 °C to +85 °C, VDD = 2.5 V to 5.5 V Unless Otherwise Noted
Fast-Mode
Fast-Mode
Plus
Parameter Description
Condition
Unit
Min
--
Max
400
--
Min
--
Max
1000
--
FSCL
tLOW
tHIGH
Clock Frequency, SCL
kHz
ns
Clock Pulse Width Low
Clock Pulse Width High
1300
600
--
500
260
--
--
--
ns
V
DD = 2.5 V
95
168
157
156
450
Input Filter Spike Suppression
(SCL, SDA)
tI
VDD = 3.3 V
VDD = 5.0 V
--
95
--
ns
--
111
900
--
tAA
Clock Low to Data Out Valid
--
--
ns
ns
Bus Free Time between Stop and
Start
tBUF
1300
--
500
--
tHD_STA
tSU_STA
tHD_DAT
tSU_DAT
tR
Start Hold Time
Start Set-up Time
Data Hold Time
Data Set-up Time
Inputs Rise Time
Inputs Fall Time
Stop Set-up Time
Data Out Hold Time
600
600
0
--
--
260
260
0
--
--
ns
ns
ns
ns
ns
ns
ns
ns
--
--
100
--
--
50
--
--
300
300
--
120
120
--
tF
--
--
tSU_STD
tDH
600
50
260
50
--
--
Note 1 Timing diagram can be found in the Figure 88.
Datasheet
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Revision 3.3
25 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 9: Asynchronous State Machine EC at T = 25 °C
Parameter Description
Condition
Min
82
57
40
--
Typ
--
Max
108
74
49
89
61
39
--
Unit
VDD = 2.5 V
VDD = 3.3 V
VDD = 5.0 V
VDD = 2.5 V
VDD = 3.3 V
VDD = 5.0 V
VDD = 2.5 V
VDD = 3.3 V
VDD = 5.0 V
VDD = 2.5 V
VDD = 3.3 V
VDD = 5.0 V
Asynchronous State Machine
Output Delay Time
tst_out_delay
--
ns
--
--
Asynchronous State Machine
Output Transition Time
tst_out
--
--
ns
ns
ns
--
--
12
9
--
Asynchronous State Machine
Input Pulse Acceptance Time
tst_pulse
--
--
6
--
--
--
--
13
9
Asynchronous State Machine
Input Compete Time
tst_comp
--
--
--
--
6
Table 10: Typical Current Estimated for Each Macrocell at T = -40 °C to +85 °C
Parameter
Description Note
Chip Quiescent (POR, BG auto Power-On)
VDD = 2.5 V VDD = 3.3 V VDD = 5.0 V
Unit
µA
µA
µA
µA
µA
µA
µA
0.06
12.85
0.28
0.08
14.07
0.35
0.13
17.15
0.61
BG Force On
LP OSC (1.73 kHz)
Configurable OSC (25 kHz), pre-divider = 1
Configurable OSC (25 kHz), pre-divider = 8
Configurable OSC (2 MHz), pre-divider = 1
Configurable OSC (2 MHz), pre-divider = 8
5.12
5.32
6.14
4.98
5.13
5.83
34.66
22.23
42.18
25.26
61.05
34.01
Real Time Clock (RTC), RTC Clocked by
Counter Divider Clock (see Note)
0.18
0.24
0.40
µA
IDD
Current
1st ACMP used with LB enabled
1st ACMP used (includes Vref)
Each additional ACMP add
53.22
56.50
3.35
66.93
71.99
62.94
40
46.60
49.89
3.35
60.47
65.37
56.38
47
56.37
59.65
3.35
µA
µA
µA
µA
µA
µA
µA
µA
ACMP0 or ACMP1 used with Input Buffer
ACMP1 used with 100 µA enabled
ACMP2 used with Temp Sensor
Push-Pull 1x + 4 pF @ 2 MHz
Push-Pull 1x + 4 pF @ 25 kHz
70.59
75.13
66.26
106
4.5
5
16
Note 1 The RTC current measurements were taken with an external 32.768 kHz clock with the GPIO current consumption
extracted.
Datasheet
18-Sep-2019
Revision 3.3
26 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
3.5 TIMING CHARACTERISTICS
Table 11: Typical Delay Estimated for Each Macrocell at T = 25 °C
VDD = 2.5 V
VDD = 3.3 V
VDD = 5.0 V
Unit
Parameter Description Condition
rising falling rising falling rising falling
tpd
tpd
Delay
Delay
Digital Input to PP 1x
Digital Input to PP 2x
26
25
28
27
19
18
20
19
14
13
14
14
ns
ns
Digital Input with Schmitt Trigger to
PP 1x
tpd
Delay
25
27
18
20
13
14
ns
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Width
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Low Voltage Digital Input to PP 1x
Digital input to NMOS 1x
Digital input to NMOS 2x
Digital input to PMOS 1x
Digital input to PMOS 2x
Output enable from pin, OE Hi-Z to 1
Output enable from pin, OE Hi-Z to 0
1x3 State Hi-Z to 1
33
--
307
46
42
--
25
--
207
31
28
--
19
--
131
20
18
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
--
--
--
26
25
28
--
19
18
20
--
14
13
15
--
--
--
--
--
-
-
27
--
20
--
14
--
28
--
20
--
15
--
1x3 State Hi-Z to 0
27
--
20
--
14
--
2x3 State Hi-Z to 1
27
--
20
--
14
--
2x3 State Hi-Z to 0
26
54
39
38
38
36
--
19
38
28
27
27
25
--
14
27
20
19
19
18
--
CNT/DLY Counter Mode
CNT/DLY Freq. Detect
CNT/DLY One Shot
54
39
38
36
36
40
19
20
20
21
21
22
17
20
18
27
214
182
21
29
29
21
26
31
25
24
38
28
27
26
26
28
14
14
15
15
15
16
13
14
13
19
158
136
15
21
21
15
19
23
18
17
27
20
19
18
18
20
10
10
11
11
10
11
9
CNT/DLY Delay Mode
CNT/DLY Edge Detect
CNT/DLY High Level Reset
LATCH Q
20
20
21
21
22
22
17
20
18
27
212
182
20
25
31
20
26
26
48
54
14
14
15
15
15
15
12
14
12
19
156
136
14
18
22
15
19
19
34
39
9
LATCH nQ
10
10
11
11
10
8
LATCH nRESET Q
LATCH nRESET nQ
LATCH nSET Q
LATCH nSET nQ
LUT2bit
LUT3bit
10
9
9
LUT4bit
8
EDGE DETECT
13
117
101
11
15
15
11
13
16
13
12
13
115
101
10
13
16
10
13
14
25
28
EDGE DETECT Delayed
EDGE DETECT
Ripple CLK DOWN CNT Q0
Ripple CLK DOWN CNT Q1
Ripple CLK DOWN CNT Q2
Ripple CLK UP CNT Q0
Ripple CLK UP CNT Q1
Ripple CLK UP CNT Q2
Ripple nRESET DOWN CNT Q0
Ripple nRESET DOWN CNT Q1
Datasheet
18-Sep-2019
Revision 3.3
27 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 11: Typical Delay Estimated for Each Macrocell at T = 25 °C(Continued)
VDD = 2.5 V
VDD = 3.3 V
VDD = 5.0 V
Unit
Parameter Description Condition
rising falling rising falling rising falling
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Ripple nRESET DOWN CNT Q2
Ripple nRESET UP CNT Q0
Ripple nRESET UP CNT Q1
Ripple nRESET UP CNT Q2
DFF Q
24
25
24
25
19
20
--
54
48
52
57
20
19
21
--
17
18
17
18
13
14
--
39
34
38
41
14
14
15
--
13
13
12
13
10
10
--
28
25
27
30
10
10
10
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DFF nQ
DFF nRESET Q
DFF nRESET nQ
DFF nSET Q
21
21
--
15
15
--
11
11
--
--
--
--
DFF nSET nQ
22
23
26
112
15
17
19
77
10
12
13
50
Pipe Delay Out
24
25
111
17
18
77
13
13
50
Pipe Delay nRESET Out
Filter
ACMP (100 mV overdrive,
low bandwidth disabled,
input gain = 1, IN- = 600 mV)
tpd
tpd
tpd
Delay
Delay
Delay
0.49
1.26
3.89
0.45
1.16
3.55
0.42
1.17
3.82
0.38
1.08
3.48
0.40
1.14
3.78
0.36
1.06
3.44
µs
µs
µs
ACMP (10 mV overdrive,
low bandwidth disabled, input gain =
1,
IN- = 600 mV)
ACMP (100 mV overdrive,
low bandwidth enabled, input gain =
1, IN- = 600 mV)
ACMP (10 mV overdrive,
low bandwidth enabled, input gain =
1, IN- = 600 mV)
tpd
tw
Delay
Width
10.04 10.82
79 78
9.88
55
10.76
55
9.77
35
10.68
35
µs
filter (min transmitted)
ns
Table 12: Typical Propagations Delays and Pulse Widths at T = 25 °C
Parameter Description
Note
VDD = 2.5 V VDD = 3.3 V VDD = 5.0 V
Unit
Pulse Width,
tw
mode: (any)edge detect, edge detect output
185
373
561
748
137
277
417
556
101
205
308
411
ns
ns
ns
ns
1 cell
Pulse Width,
tw
mode: (any)edge detect, edge detect output
mode: (any)edge detect, edge detect output
mode: (any)edge detect, edge detect output
2 cell
Pulse Width,
tw
3 cell
Pulse Width,
tw
4 cell
time1
time1
time1
time1
time2
Delay, 1 cell
Delay, 2 cell
Delay, 3 cell
Delay, 4 cell
Delay, 1 cell
mode: (any)edge detect, edge detect output
mode: (any)edge detect, edge detect output
mode: (any)edge detect, edge detect output
mode: (any)edge detect, edge detect output
mode: both edge delay, edge detect output
28
28
20
20
15
15
ns
ns
ns
ns
ns
28
20
15
28
20
15
218
161
119
Datasheet
18-Sep-2019
Revision 3.3
28 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 12: Typical Propagations Delays and Pulse Widths at T = 25 °C(Continued)
Parameter Description
Note
VDD = 2.5 V VDD = 3.3 V VDD = 5.0 V
Unit
ns
time2
time2
time2
Delay, 2 cell
Delay, 3 cell
Delay, 4 cell
mode: both edge delay, edge detect output
mode: both edge delay, edge detect output
mode: both edge delay, edge detect output
405
593
780
300
440
579
222
325
427
ns
ns
Table 13: Typical Filter Rejection Pulse Width at T = 25 °C
Parameter
VDD = 2.5 V VDD = 3.3 V VDD = 5.0 V
< 75 < 55 < 35
Unit
Filtered Pulse Width
ns
Table 14: Typical Counter/Delay Offset Measurements at T = 25 °C
RC OSC
Parameter
RC OSC Power VDD = 2.5 V VDD = 3.3 V VDD = 5.0 V
Unit
Freq
offset
25 kHz
auto
auto
16
1
2.5
0.6
2.5
0.4
µs
µs
µs
µs
µs
µs
µs
µs
ms
ns
offset
2 MHz
offset
1.73 kHz
25 kHz
auto
247
16
232
14
198
12
frequency settling time
frequency settling time
frequency settling time
variable (CLK period)
variable (CLK period)
variable (CLK period)
tpd (non-delayed edge)
auto
2 MHz
auto
14
14
14
1.73 kHz
25 kHz
auto
250
0-40
0-0.5
0-0.5
25
200
0-40
0-0.5
0-0.5
14
150
0-40
0-0.5
0-0.5
10
forced
forced
forced
either
2 MHz
1.73 kHz
25kHz/2MHz
Datasheet
CFR0011-120-00
18-Sep-2019
Revision 3.3
29 of 210
© 2019 Dialog Semiconductor
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
3.6 OSC CHARACTERISTICS
Table 15: 25 kHz RC OSC0 Frequency Limits
Temperature Range
Power Supply Range
(VDD), V
+25 °C
Minimum
0 °C to +85 °C
-40 °C to +85 °C
Maximum
Value, kHz
Minimum
Maximum
Value, kHz
Minimum
Maximum
Value, kHz
Value, kHz
Value, kHz
Value, kHz
2.5 V ±8%
3.3 V ±10%
5 V ±10%
24.705
25.342
25.289
25.801
25.334
25.801
23.724
25.932
25.932
26.249
25.932
26.249
23.357
26.888
26.836
26.987
26.879
26.987
24.710
23.690
23.334
24.650
23.661
23.376
2.5 V to 4.5 V
2.5 V to 5.5 V
24.650
23.659
23.334
24.650
23.659
23.335
Table 16: 25 kHz RC OSC0 Frequency Error (Error Calculated Relative to Nominal Value)
Temperature Range
Power Supply Range
(VDD), V
+25 °C
0 °C to +85 °C
-40 °C to +85 °C
Error (% at
Error (% at
Maximum)
Error (% at
Error (% at
Maximum)
Error (% at
Minimum)
Error (% at
Maximum)
Minimum)
-1.18%
-1.16%
-1.40%
-1.40%
-1.40%
Minimum)
-5.10%
-5.24%
-5.36%
-5.36%
-5.36%
2.5 V ±8%
3.3 V ±10%
5 V ±10%
1.37%
1.16%
3.20%
1.34%
3.20%
3.73%
3.73%
5.00%
3.73%
5.00%
-6.57%
-6.66%
-6.50%
-6.66%
-6.66%
7.55%
7.34%
7.95%
7.52%
7.95%
2.5 V to 4.5 V
2.5 V to 5.5 V
Table 17: 2 MHz RC OSC0 Frequency Limits
Temperature Range
0 °C to +85 °C
Power Supply Range
(VDD), V
+25 °C
-40 °C to +85 °C
Minimum
Maximum
Minimum
Maximum
Minimum
Maximum
Value, MHz
Value, MHz
Value, MHz
Value, MHz
Value, MHz
Value, MHz
2.5 V ±8%
3.3 V ±10%
5 V ±10%
1.916
1.967
1.947
1.935
1.935
2.082
2.032
2.262
2.066
2.262
1.859
2.128
2.082
2.268
2.117
2.268
1.859
1.828
1.820
1.814
1.814
2.128
2.125
2.268
2.125
2.268
1.908
1.897
2.5 V to 4.5 V
2.5 V to 5.5 V
1.873
1.873
Table 18: 2 MHz RC OSC0 Frequency Error (Error Calculated Relative to Nominal Value)
Temperature Range
Power Supply Range
(VDD), V
+25 °C
Error (% at
0 °C to +85 °C
-40 °C to +85 °C
Error (% at
Maximum)
Error (% at
Error (% at
Maximum)
Error (% at
Minimum)
Error (% at
Maximum)
Minimum)
Minimum)
2.5 V ±8%
-4.22%
4.09%
-7.06%
6.40%
-7.06%
6.40%
Datasheet
CFR0011-120-00
18-Sep-2019
Revision 3.3
30 of 210
© 2019 Dialog Semiconductor
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 18: 2 MHz RC OSC0 Frequency Error (Error Calculated Relative to Nominal Value)(Continued)
Temperature Range
Power Supply Range
(VDD), V
+25 °C
Error (% at
0 °C to +85 °C
-40 °C to +85 °C
Error (% at
Maximum)
Error (% at
Error (% at
Maximum)
Error (% at
Error (% at
Maximum)
Minimum)
-1.64%
-2.67%
-3.26%
-3.26%
Minimum)
-4.62%
-5.14%
-6.37%
-6.37%
Minimum)
-8.62%
-9.01%
-9.31%
-9.31%
3.3 V ±10%
5 V ±10%
1.60%
13.09%
3.31%
4.10%
13.39%
5.84%
6.24%
13.39%
6.24%
2.5 V to 4.5 V
2.5 V to 5.5 V
13.09%
13.39%
13.39%
Table 19: 1.73 kHz RC OSC1 Frequency Limits
Temperature Range
0 °C to +85 °C
Power Supply Range
(VDD), V
+25 °C
-40 °C to +85 °C
Minimum
Maximum
Minimum
Maximum
Minimum
Maximum
Value, MHz
Value, MHz
Value, MHz
Value, MHz
Value, MHz
Value, MHz
2.5 V ±8%
3.3 V ±10%
5 V ±10%
1.390
2.017
2.011
2.034
2.016
2.034
1.330
2.020
2.017
2.037
2.019
2.037
1.180
1.125
1.099
1.099
1.099
2.022
2.021
2.037
2.022
2.037
1.339
1.276
1.318
1.255
2.5 V to 4.5 V
2.5 to 5.5 V
1.318
1.255
1.318
1.255
Table 20: 1.73 kHz RC OSC1 Frequency Error (Error Calculated Relative to Nominal Value)
Temperature Range
Power Supply Range
(VDD), V
+25 °C
0 °C to +85 °C
-40 °C to +85 °C
Error (% at
Error (% at
Maximum)
Error (% at
Error (% at
Maximum)
Error (% at
Minimum)
Error (% at
Maximum)
Minimum)
-19.65%
-22.57%
-23.79%
-23.79%
-23.79%
Minimum)
-23.12%
-26.21%
-27.44%
-27.44%
-27.44%
2.5 V ±8%
3.3 V ±10%
5 V ±10%
16.58%
16.23%
17.54%
16.51%
17.54%
16.77%
16.58%
17.73%
16.73%
17.73%
-31.75%
-34.93%
-36.47%
-36.47%
-36.47%
16.85%
16.85%
17.73%
16.85%
17.73%
2.5 V to 4.5 V
2.5 V to 5.5 V
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
3.6.1 OSC Power-On Delay
Note: DLY/CNT Counter Data = 100, RC OSC Power Setting: "Auto Power-On", RC OSC Clock to Matrix Input: "Enable"
Table 21: Oscillators Power-On Delay at T = 25 °C
RC OSC0 2 MHz
RC OSC0 25 kHz
RC OSC1 1.73 kHz
Power Supply
Range
Typical
Value, ns
Maximum
Value, ns
Typical
Maximum
Value, µs
Typical
Maximum
Value, µs
(VDD) V
Value, µs
14.35
13.76
12.94
9.67
Value, µs
222.53
217.52
210.43
203.51
196.79
183.73
177.64
169.40
165.60
2.50
2.70
3.00
3.30
3.60
4.20
4.50
5.00
5.50
619
905
813
709
638
582
510
484
454
428
17.57
16.98
16.61
36.51
19.46
2.70
296.85
293.04
287.82
283.89
280.17
272.25
267.27
258.96
248.45
563
500
454
419
1.82
370
1.79
352
1.89
2.94
328
2.09
3.28
309
2.21
3.45
Table 22: OSC Power-On Delay, at T = 25 °C, Fast Start-up Time Mode
RC OSC0 2 MHz
Power Supply
RC OSC1 25 kHz
Range
Typical
Value, ns
Maximum
Value, ns
Typical
Maximum
(VDD) V
Value, µs
20.61
20.58
20.52
20.49
20.46
20.39
20.32
20.20
19.97
Value, µs
22.61
22.47
22.43
22.28
22.42
22.20
22.12
21.83
21.33
2.50
2.70
3.00
3.30
3.60
4.20
4.50
5.00
5.50
216
197
178
166
158
150
147
142
138
313
286
254
234
222
209
207
201
194
3.7 ANALOG COMPARATOR CHARACTERISTICS
Table 23: Analog Comparator EC at T = -40 °C to +85 °C, VDD = 2.5 V to 5.5 V Unless Otherwise Noted
Parameter
Description
Note
Conditions
Min
Typ
Max
Unit
Positive Input set to
GPIO or VDD
0
--
VDD
V
ACMP Input Voltage
Range
VACMP
Positive Input set to
LDO VIN
VDD
0.4
-
0
0
--
--
V
V
Negative Input
1.2
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 23: Analog Comparator EC at T = -40 °C to +85 °C, VDD = 2.5 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter
Description
Note
Conditions
Min
Typ
Max
Unit
Low Bandwidth -
Enable, Vhys = 0 mV,
Gain = 1,
Vref = 50 mV to 1200
mV
T = 25 °C
-9.0
--
9.4
mV
-12.3
-12.6
-9.2
--
--
--
12.8
8.0
mV
mV
mV
µs
ACMP Input Offset
Voltage
Voffset
Low Bandwidth -
Disable, Vhys = 0 mV,
Gain =1,
Vref = 50 mV to 1200
mV
T = 25 °C
T = 25 °C
--
9.9
ACMP Power-On
delay, Minimal required
wake time for the
“Wake and Sleep
function”
140
143
667
1369
tstart
ACMP Start Time
--
µs
LB - Enabled,
T = 25 °C
3.48
14.6
--
--
--
--
--
--
38.4
36.7
mV
mV
mV
mV
mV
mV
VHYS = 25 mV
VIL = Vin - VHYS/2
LB - Disabled,
T = 25 °C
V
IH = Vin + VHYS/2
LB - Enabled,
T = 25 °C
43.9
57.1
V
HYS = 50 mV
VIL = Vin - VHYS
VIH = VHYS
LB - Disabled,
T = 25 °C
44.1
53.7
LB - Enabled,
T = 25 °C
194.0
194.4
206.8
203.3
VHYS = 200 mV
V
IL = Vin - VHYS
VHYS
Built-in Hysteresis
LB - Disabled,
T = 25 °C
VIH = VHYS
V
HYS = 25 mV
LB - Enabled
LB - Disabled
LB - Enabled
LB - Disabled
LB - Enabled
LB - Disabled
0.0
2.4
--
--
--
--
--
--
41.1
41.4
mV
mV
mV
mV
mV
mV
VIL = Vin - VHYS/2
V
V
VIL = Vin - VHYS
VIH = VHYS
IH = Vin + VHYS/2
HYS = 50 mV
37.7
43.6
187.5
192.4
64.9
55.4
VHYS = 200 mV
VIL = Vin - VHYS
VIH = VHYS
214.0
205.1
Gain = 1x
--
--
--
--
100.0
1.0
--
--
--
--
ΜΩ
ΜΩ
ΜΩ
ΜΩ
Gain = 0.5x
Gain = 0.33x
Gain = 0.25x
Series Input
Resistance
Rsin
0.8
1.0
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 23: Analog Comparator EC at T = -40 °C to +85 °C, VDD = 2.5 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter
Description
Note
Conditions
Min
Typ
Max
Unit
Low Bandwidth -
Enable, Gain = 1,
Overdrive =10 mV
Low to High
--
11.2
51.9
µs
High to Low
Low to High
High to Low
Low to High
High to Low
Low to High
High to Low
--
--
--
--
--
--
--
12.2
1.0
1.0
4.8
4.4
0.4
0.4
58
4.2
µs
µs
µs
µs
µs
µs
µs
Low Bandwidth -
Disable, Gain = 1,
Overdrive =10 mV
Propagation Delay,
Response Time
3.7
PROP
Low Bandwidth -
Enable, Gain = 1,
Overdrive =100 mV
22.8
22.4
2.2
for ACMP0 to ACMP3
Low Bandwidth -
Disable, Gain = 1,
Overdrive =100 mV
0.7
G = 1
--
1
--
--
--
--
Gain error (including
threshold and internal
Vref error)
G = 0.5
G = 0.33
G = 0.25
-0.81%
-1.33%
-1.43%
0.76%
1.4%
1.63%
G
3.8 LOW DROP OUT “LDO” REGULATOR ELECTRICAL CHARACTERISTICS
All four LDO regulators within SLG46585 have the same electrical specification. Some circuits are common to all LDOs and so
the current consumption varies depending on the number of Active LDOs. Each LDO has three modes – HP MODE is a typical
150 mA LDO regulator mode, and LP MODE is an ultra-low current regulator mode. The LDO also has an LDO Power Switch
Mode when the LDO MOSFET simply turns into a load switch passing VIN to VOUT.
Table 24: LDO Current Consumption at T = 25 °C
Parameter Description
Condition
Min
--
Typ
32
48
64
80
2
Max
--
Unit
µA
µA
µA
µA
µA
µA
µA
µA
One LDO Regulator in HP Mode
Two LDO Regulators in HP Mode
Three LDO Regulators in HP Mode
Four LDO Regulators in HP Mode
One LDO Regulator in LP Mode
Two LDO Regulators in LP Mode
Three LDO Regulators in LP Mode
Four LDO Regulators in LP Mode
--
--
IQ
Quiescent Current
--
--
--
--
--
--
--
3
--
IQ
Quiescent Current
--
4
--
--
5
--
Note 1 Typ means under VDD = VIN = 3.3 V, VOUT = 2.0 V, no load.
Table 25: LDO Regulator Thermal Limitations
Parameter Description
Condition
Min
--
Typ
--
Max
0.6
Unit
W
TC = 85 °C
ICTL
Thermal Limitation
TC = 70 °C
--
--
0.8
W
Max Watt per LDO (Note 1)
--
--
0.5
W
Thermal Shutdown (Note 2)
115
90
125
100
135
110
°C
°C
Shutdown
Thermal Shutdown Recovery
Note 1 Max Watt LDO multiplied by number of LDOs can easily exceed the Max Watt for the total IC package.
Note 2 Lower Thermal shutdown levels may be achieved by using the temperature sensor and comparator.
Datasheet
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© 2019 Dialog Semiconductor
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 26: LDO HP MODE EC at T = 25 °C
Parameter
IOUT
Description
Condition
Min
--
Typ
--
Max
150
VDD
300
+3
Unit
mA
V
Output Current Rating
Voltage Input
per LDO
VIN
2.5
--
--
VDO
Voltage Dropout
250
--
mV
%
over PVT of VOUT > 1.5 V
over PVT of VOUT ≤ 1.5 V
10 Hz to 100 kHz
-3
Output Voltage Accuracy
(Note 1)
∆VOUT
-60
--
--
+60
--
mV
µV
eN
Noise Voltage (rms)
75
Power Supply Rejection Ratio 100 Hz to 100 kHz
(Note 2)
PSRR
--
--
50
50
--
--
dB
dB
LDO0 to LDO1 regulation perturba-
tion, and LDO2 to LDO3 perturbation
at 0 to 150 mA at 1 kHz at 1.8 V VOUT
CTRR
Crosstalk Rejection Ratio
∆VLINE
∆VLOAD
∆VTC
Line Regulation
VOUT + 0.5 V < VIN ≤ 5.5 V
1 mA < IOUT < 150 mA
-1%
--
--
--
+1%
0.3
--
%/V
Load Regulation
mV/mA
ppm/C
VOUT Temp Coefficient
--
100
External Input Capacitance
(Note 2)
per LDO
CIN
2
2
--
--
--
--
µF
µF
External Output Capacitance per LDO
(Note 2)
COUT
SS0
SS1
SS2
SS3
SC
SS Slew Rate 0
SS Slew Rate 1
SS Slew Rate 2
SS Slew Rate 3
Short Circuit Protection
Wait Time
VOUT = 5% to 95%
--
--
--
--
--
--
10
20
--
--
--
--
--
--
V/ms
V/ms
V/ms
V/ms
mA
VOUT = 5% to 95%
VOUT = 5% to 95%
VOUT = 5% to 95%
1.25
2.50
189
500
tWAIT
Time from EN = 1 to
EN = 0, Dis_EN = 1
V
OUT start rise
µs
Output Discharge Pull-down
Resistance
RD
--
300
--
Ω
Note1Accuracy specifies all the effects of line regulation (∆VLINE), load regulation (∆VLOAD), and temperature coefficient (∆VTC).
Note 2 X7R-type and X5R-type capacitors are recommended.
Table 27: LDO LP MODE EC at T = 25 °C
Parameter
IOUT
Description (Note 2)
Output Current Rating
Voltage Input
Condition
Min
--
Typ
--
Max
100
VDD
750
+10
Unit
µA
V
per LDO
VIN
2.5
--
--
VDO
Voltage Dropout
500
--
mV
%
∆VOUT
Output Voltage Accuracy
over PVT
per LDO
-10
External Input Capacitance
(Note 1)
CIN
2
2
--
--
--
--
--
--
µF
µF
Ω
External Output Capacitance per LDO
(Note 1)
COUT
Output Discharge Pull-down
Resistance
EN = 0, Dis_EN = 1
R
300
D
Datasheet
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© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 27: LDO LP MODE EC at T = 25 °C(Continued)
Parameter
Description (Note 2)
Condition
Min
Typ
Max
Unit
Note 1 X7R-type and X5R-type capacitors are recommended.
Note 2 Soft Start and Short Circuit protection circuits are not available in LDO LP MODE.
Table 28: LDO Power Switch Mode EC at T = 25 °C
Parameter Description (Note 1)
Condition
Min
--
Typ
--
Max
150
VDD
--
Unit
mA
V
IOUT
VIN
Output Current Rating
Voltage Input
per LDO
2.5
--
--
RDSON
IQ
MOSFET ON resistance
Quiescent Current
P-Channel with VIN at 2.5, per LDO
No load, per LDO
1
Ω
--
--
1
µA
Note 1 Soft Start and Short Circuit protection circuits are not available in LDO Power Switch Mode.
3.9 DC/DC CONVERTER ELECTRICAL CHARACTERISTICS
Table 29: DC/DC Converter EC
Parameter Description
Condition
Min
Typ
Max
Unit
Typical values are at TA = 25 °C
VIN
Operating Input Voltage
2.5
--
--
5.5
--
V
when OFF
0.17
79
µA
µA
IDD
Power Supply Current
when ON, No load
--
--
sel_vo [2:0] = 000;
VIN = 2.7 to 5.5 V, fSW = 1.5 MHz
1.16
1.46
1.75
2.41
2.89
3.20
1.20
1.50
1.80
2.50
3.00
3.30
1.24
1.55
1.85
2.58
3.105
3.40
V
V
V
V
V
V
sel_vo [2:0] = 001;
VIN = 2.7 to 5.5 V, fSW = 1.5 MHz
sel_vo [2:0] = 010;
V
IN = 2.7 to 5.5 V, fSW = 1.5 MHz
VOUT
Output Voltage
sel_vo [2:0] = 011;
VIN = 3.125 to 5.5 V, fSW = 1.5 MHz
sel_vo [2:0] = 100;
VIN = 3.75 to 5.5 V, fSW = 1.5 MHz
sel_vo [2:0] = 101;
VIN = 4.125 to 5.5 V, fSW = 1.5 MHz
VRIPPLE
RDSON_P
RDSON_N
ILIMIT
Output Voltage Ripple
VIN = 3.3 V; VOUT = 1.2 V; in CCM Mode
--
--
--
--
10
90
51
2.5
--
--
--
--
mV
mΩ
mΩ
A
HS Switch ON Resistance
LS Switch ON Resistance
Current Limit Threshold
Default sel_ocp[1:0] = 00
VIN = 5 V, VOUT = 1.2 V;
ILOAD = 0.5 A; Temp = 27˚C,
fSW = 1.5 MHz;
ηEF
Efficiency
--
88
--
%
Inductor DCR =10 mΩ
Default sel_fsw[1:0] = 00
Default sel_fsw[1:0] = 01
--
--
1.5
2
--
--
MHz
MHz
fSW
TTotal_ON
TSS
Switching Frequency
Total Turn-on Time
from Enable to DC_VOUT
--
--
0.6
0.5
--
--
ms
ms
Soft Start Time
Datasheet
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© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 29: DC/DC Converter EC(Continued)
Parameter Description
Condition
Min
--
Typ
80
Max
--
Unit
%
VOUT = 3.3 V, fSW = 1.5 MHz
VOUT = 3.3 V, fSW = 2.0 MHz
DCMAX
Maximum Duty Cycle
--
75
--
%
DCMIN
Minimum Duty Cycle
SW Leakage Current
--
20
--
%
Set on/off = 0, VIN = 5.5 V, VSW = 0 V
and 5.5 V
ISW(LKG)
--
0
--
µA
TINT(Low)
TINT(High)
INT De-assertion Time
INT Assertion Time
VIN = 3.3 V, Temp = 27˚C
VIN = 3.3 V, Temp = 27˚C
--
--
60
2
--
--
ns
µs
Thermal Protection
Restart Threshold
THERMON
THERMOFF
--
--
125
100
--
--
˚C
˚C
Thermal Protection
Shutdown Threshold
Note1 INTInterruptis anOpen-Drain output. Logic highlevelbecomes asserted withinTINT(HIGH) whenan over-currentcondition
has been detected. After the over-current event no longer persist the INT becomes de-asserted after TINT(LOW)
.
Note 2 CCM - Continuous Conduction Mode Indicator Output. CCM is an Open-Drain digital output that becomes Low when
the load is high and the converter switches to the continuous conduction mode (CCM). The CCM output continues to toggle
when the converter is in non-CCM mode. Customers might use LP filter to convert the toggling signal to a DC signal, and based
on DC level to identify the converter operation mode.
Datasheet
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© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
4
User Programmability
The SLG46585 is a user programmable device with one time programmable (OTP) memory elements that are able to configure
the connection matrix and macrocells. A programming development kit allows the user the ability to create initial devices. Once
the design is finalized, the programming code (.gpx file) is forwarded to Dialog Semiconductor to integrate into a production
process.
Product
Definition
E-mail Product Idea, Definition, Drawing or
Customer creates their own design in
Schematic to
GreenPAK Designer
CMBUGreenPAK@diasemi.com
Dialog Semiconductor Applications
Engineer will review design specifications
Program Engineering Samples with
GreenPAK Programmer
with customer
Samples, Design and Characterization
Report send to customer
Customer verifies GreenPAK in system
design
GreenPAK Design
approved
GreenPAK Design
approved
E-mail .gpx to
CMBUGreenPAK@diasemi.com
Customers verifies GreenPAK design
GreenPAK Design
Approved in system test
Custom GreenPAK part enters production
Figure 2: Steps to Create a Custom GreenPAK Device
Datasheet
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CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
5
IO Pins
The SLG46585 has a total of 9 multi-function IO pins which can function as either a user defined Input or Output, as well as serving
as a special function (such as outputting the voltage reference), or serving as a signal for programming of the on-chip Non-Volatile
Memory (NVM).
Refer to Section 2 for normal and programming mode pin definitions.
Normal Mode pin definitions are as follows:
IO0: General Purpose Input or Output with OE
IO1 General Purpose Input or Output or Analog Comparator 0(+)
IO2: General Purpose Input or Output with OE or Analog Comparator 1(+)
IO3: General Purpose Input
VDD: VDD Power supply
SCL: I2C_SCL
SDA: I2C_SDA
IO4: General Purpose Input or Output with OE or Analog Comparator (-)
LDO Pins:
LDO0 VOUT: LDO0 Output or Analog Comparator 3(+)
LDO0/1 VIN: LDO0 & LDO1 Input or Analog Comparator 0(+)
LDO1 VOUT: LDO1 Output
LDO2 VOUT: LDO2 Output or Analog Comparator 3(+)
LDO2/3 VIN: LDO2 & LDO3 Input or Analog Comparator 1(+)
LDO3 VOUT: LDO3 Output
AGND: LDO Ground
IO5: General Purpose Input or Output or Analog Comparator 2(+)
IO6: General Purpose Input or Output with OE or Analog Comparator 3(+)
GND: Ground
Programming Mode pin definitions are as follows:
IO3: VPP Programming voltage
VDD: VDD Power supply
SCL: Programming SCL
SDA: Programming SDA
IO5: Programming Mode Control
GND: Ground
Of the 9 user defined IO pins on the SLG46585, all but one of the pins (IO3) can serve as both digital input and digital output. IO3
can only serve as a digital input pin with RESET function, which has settings as follows:
Level polarity:
Non-inverted
Inverted
Reset mode:
Level sensitive
Edge triggered
Edge detection:
Rising edge
Falling edge
5.1 INPUT MODES
Each IO pin can be configured as a digital input pin with/without Schmitt Trigger and low voltage input. IO1, IO2, IO5, and IO6
can also be configured to serve as analog inputs to the on-chip comparators. IO4 can also be configured as ACMP reference
voltage input.
Datasheet
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© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
5.2 OUTPUT MODES
Pins IO0, IO1, IO2, IO4, IO5, and IO6 can all be configured as digital output pins.
5.3 PULL-UP/DOWN RESISTORS
All IO pins have the option for user selectable resistors connected to the input structure. The selectable values on these resistors
are 10 kΩ, 100 kΩ, and 1 MΩ. In the case of IO3, the resistors are fixed to a Pull-down configuration. In the case of all other IO
pins, the internal resistors can be configured as either Pull-up or Pull-downs.
5.4 IO REGISTER SETTINGS
Table 30: IO0 Register Settings
Register Bit
Address
Signal Function
Register Definition
IO0 Pull-up/down
Resistor Selection
[1025]
0: Pull-down Resistor
1: Pull-up Resistor
IO0 Pull-up/down
Resistor Value
Selection
[1027:1026]
[1029:1028]
[1031:1030]
00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
IO0 Mode Control
(sig_io0_oe = 0)
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
11: Reserved
IO0 Mode Control
(sig_io0_oe = 1)
00: Push-Pull 1x
01: Push-Pull 2x
10: Open-Drain NMOS 1x
11: Open-Drain NMOS 2x
Table 31: IO1 Register Settings
Register Bit
Address
Signal Function
Register Definition
IO1 Driver Strength
Selection
[1033]
0: 1x
1: 2x
IO1 Pull-up/down
Resistor Selection
[1034]
0: Pull-down Resistor
1: Pull-up Resistor
IO1 Pull-down
Resistor Value
Selection
[1036:1035]
00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
IO1 Mode Control
[1039:1037]
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Analog Input/Output
100: Push-Pull
101: Open-Drain NMOS
110: Open-Drain PMOS
111: Analog Input and Open-Drain
Table 32: IO2 Register Settings
Register Bit
Address
Signal Function
Register Definition
IO2 Pull-up/down
Resistor Selection
[1057]
0: Pull-down Resistor
1: Pull-up Resistor
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 32: IO2 Register Settings(Continued)
Register Bit
Address
Signal Function
Register Definition
IO2 Pull-up/down
Resistor Value
Selection
[1059:1058]
00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
IO2 Mode Control
(sig_IO2_oe = 0)
[1061:1060]
[1063:1062]
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
11: Analog Input/Output
IO2 Mode Control
(sig_IO2_oe = 1)
00: Push-Pull 1x
01: Push-Pull 2x
10: Open-Drain NMOS 1x
11: Open-Drain NMOS 2x
Table 33: IO3 Register Settings
Register Bit
Address
Signal Function
Register Definition
IO3 Pull-down
Resistor Value
Selection
[1069:1068]
00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
IO3 Mode Control
[1071:1070]
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
11: Reserved
IO3 reset level
polarity selection
[1304]
[1305]
[1306]
[1307]
0: Non-inverted
1: Inverted
IO3 reset bypass
selection
0: Edge selection
1: Level selection
IO3 reset edge
selection
0: Rising edge
1: Falling edge
IO3 reset enable
0: Disable
1: Enable
Table 34: SCL Register Settings
Register Bit
Address
Signal Function
Register Definition
SCL Mode Control
[1078:1077]
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
11: Reserved
Table 35: SDA Register Settings
Register Bit
Address
Signal Function
Register Definition
SDADriverStrength
Selection
[1081]
0: 1x
1: 2x
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 35: SDA Register Settings(Continued)
Register Bit
Address
Signal Function
Register Definition
SDA Mode Control
[1086:1085]
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
11: Reserved
Table 36: IO4 Register Settings
Register Bit
Address
Signal Function
Register Definition
IO4 Pull-up/down
Resistor Selection
[1089]
0: Pull-down Resistor
1: Pull-up Resistor
IO4 Pull-up/down
Resistor Value
Selection
[1091:1090]
[1093:1092]
[1095:1094]
00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
IO4 Mode Control
(sig_IO4_oe = 0)
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
11: Analog Input/Output
IO4 Mode Control
(sig_IO4_oe = 1)
00: Push-Pull 1x
01: Push-Pull 2x
10: Open-Drain NMOS 1x
11: Open-Drain NMOS 2x
Table 37: IO5 Register Settings
Register Bit
Address
Signal Function
Register Definition
IO5 Driver Strength
Selection
[1097]
0: 1x
1: 2x
IO5 Pull-up/down
Resistor Selection
[1098]
0: Pull-down Resistor
1: Pull-up Resistor
IO5 Pull-up/down
Resistor Value
Selection
[1100:1099]
00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
IO5 Mode Control
[1103:1101]
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Analog Input/Output
100: Push-Pull
101: Open-Drain NMOS
110: Open-Drain PMOS
111: Analog Input and Open-Drain
Table 38: IO6 Register Settings
Register Bit
Address
Signal Function
Register Definition
IO6 Pull-up/down
Resistor Selection
[1105]
0: Pull-down Resistor
1: Pull-up Resistor
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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Table 38: IO6 Register Settings(Continued)
Register Bit
Address
Signal Function
Register Definition
IO6 Pull-up/down
Resistor Value
Selection
[1107:1106]
00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
IO6 Mode Control
(sig_IO6_oe = 0)
[1109:1108]
[1111:1110]
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
11: Analog Input/Output
IO6 Mode Control
(sig_IO6_oe = 1)
00: Push-Pull 1x
01: Push-Pull 2x
10: Open-Drain NMOS 1x
11: Open-Drain NMOS 2x
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
5.5 GPI STRUCTURE
5.5.1 GPI Structure (for IO3)
Input Mode [1:0]
00: Digital In without Schmitt Trigger, wosmt_en = 1, OE=0
01: Digital In with Schmitt Trigger, smt_en = 1, OE = 0
10: Low Voltage Digital In mode, lv_en = 1, OE = 0
11: Reserved
10 kΩ
Note 1: OE cannot be selected by user
Note 2: OE is GND, Digital In is Matrix input
90 kΩ
900 kΩ
Res_sel[1:0]
00: floating
01: 10 kΩ
10: 100 kΩ
11: 1 MΩ
Non-Schmitt
Trigger Input
PAD
wosmt_en
OE
Schmitt Trigger
Input
Digital In
smt_en
lv_en
OE
Low Voltage
Input
OE
Figure 3: IO3 GPI Structure Diagram
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
5.6 MATRIX OE IO STRUCTURE
5.6.1 Matrix OE IO Structure (for IO0, IO2, IO4, IO6)
Non-Schmitt
Trigger Input
Input Mode [1:0]
00: Digital In without Schmitt Trigger, wosmt_en = 1
01: Digital In with Schmitt Trigger, smt_en = 1
10: Low Voltage Digital In mode, lv_en = 1
11: Analog IO mode
wosmt_en
Output Mode [1:0]
00: Push-Pull 1x mode, pp1x_en = 1
OE
01: Push-Pull 2x mode, pp2x_en = 1, pp1x_en = 1
10: NMOS 1x Open-Drain mode, od1x_en = 1
11: NMOS 2x Open-Drain mode, od2x_en = 1, od1x_en = 1
Schmitt Trigger
Input
Digital In
Note: Digital Out and OE are Matrix output, Digital In is Matrix input
smt_en
lv_en
OE
Low Voltage
Input
OE
Analog IO
(For IO2, IO4, and IO6 only)
Digital Out
Digital Out
OE
S1
S0
OE
od1x_en
10 kΩ
pp1x_en
90 kΩ
pull_up_en
900 kΩ
PAD
Res_sel[1:0]
00: floating
01: 10 kΩ
10: 100 kΩ
11: 1 MΩ
Digital Out
Digital Out
OE
OE
od2x_en
pp2x_en
Figure 4: Matrix OE IO Structure Diagram
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
5.6.2 Matrix OE IO Structure (for SCL and SDA)
Non-Schmitt
SCL, SDA Mode[1:0]
Trigger Input
00: Digital Input without Schmitt Trigger, wosmt_en = 1
01: Digital Input with Schmitt Trigger, smt_en = 1
10: Low Voltage Digital Input, lv_en = 1
11: Reserved
wosmt_en
smt_en
Note 1: Digital Out and OE are Matrix output, Digital In is Matrix input
Note 2: Output mode is fixed as OD for SDA only
GND
GND
Schmitt Trigger
Input
Digital In
Low Voltage
Input
lv_en
GND
Analog IO
Digital Out
od1x_en
Only for SDA
PAD
Digital Out
od2x_en
Only for SDA
Figure 5: Matrix OE IO Structure Diagram
Datasheet
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
5.7 IO STRUCTURE
5.7.1 IO Structure (for IO1 and IO5)
Mode [2:0]
Non-Schmitt
Trigger Input
000: Digital In without Schmitt Trigger, wosmt_en = 1, OE = 0
001: Digital In with Schmitt Trigger, smt_en = 1, OE = 0
010: Low Voltage Digital In mode, lv_en = 1, OE = 0
011: analog IO mode
wosmt_en
100: Push-Pull mode, pp_en = 1, OE = 1
101: NMOS Open-Drain mode, odn_en = 1, OE = 1
OE
OE
110: PMOS Open-Drain mode, odp_en = 1, OE = 1
111: analog IO and NMOS Open-Drain mode, odn_en = 1 and AIO_en=1
Schmitt Trigger
Input
Note 1: OE cannot be selected by user
Note 2: OE are Matrix output, Digital Out and Digital In is Matrix input
Digital In
smt_en
lv_en
Low Voltage
Input
OE
Analog IO
(For IO1 and IO5)
odp_en
Digital Out
Digital Out
S1
S0
OE
odn_en
OE
VDD
10 kΩ
pp_en
pull_up_en
90 kΩ
900 kΩ
PAD
Res_sel[1:0]
00: floating
01: 10 kΩ
10: 100 kΩ
11: 1 MΩ
odp_en
Digital Out
Digital Out
OE
OE
2x_en
2x_en
pp_en
odn_en
Figure 6: IO Structure Diagram
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
6
Connection Matrix
The Connection Matrix in the SLG46585 is used to create the internal routing for internal functional macrocells of the device once
it is programmed. The registers are programmed from the one-time NVM cell during Test Mode Operation. The output of each
functional macrocell within the SLG46585 has a specific digital bit code assigned to it that is either set to active “High” or inactive
“Low”, based on the design that is created. Once the 2048 register bits within the SLG46585 are programmed a fully custom
circuit will be created.
The Connection Matrix has 64 inputs and 104 outputs. Each of the 64 inputs to the Connection Matrix is hard-wired to the digital
output of a particular source macrocell, including IO pins, LUTs, analog comparators, other digital resources, such as VDD and
GND. The input to a digital macrocell uses a 6-bit register to select one of these 64 input lines.
For a complete list of the SLG46585’s register table, see Section 22
.
Matrix Input Signal
N
Functions
GND
0
1
2
3
IO0 Digital In
IO1 Digital In
IO2 Digital In
nRST_core (POR)
VDD
62
63
Matrix Inputs
0
1
2
104
N
Registers
[5:0]
[13:8]
[21:16]
[839:832]
Matrix OUT:
ASM-state0-EN0
Matrix OUT:
ASM-state0-EN1
Matrix OUT:
ASM-state0-EN2
Function
Reserved
Matrix Outputs
Figure 7: Connection Matrix
Function
Connection Matrix
IO1
IO0
LUT
IO0
IO1
IO2
LUT
IO2
Figure 8: Connection Matrix Example
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
6.1 MATRIX INPUT TABLE
Table 39: Matrix Input Table
Matrix Decode
Matrix Input
Matrix Input Signal Function
Number
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
GND
IO0 Digital Input
2
IO1 Digital Input
3
Synchronous DC/DC Step Down Converter Fault
GND
4
5
IO2 Digital Input
6
LUT2_0/DFF0 Output
7
LUT2_1/DFF1 Output
8
LUT2_2/DFF2 Output
9
LUT3_0/DFF3 Output
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
LUT3_1/DFF4 Output
LUT3_2/DFF5 Output
LUT3_3/DFF6 Output
LUT3_4/DFF7 Output
LUT3_6/CNT_DLY0(8bit) Output
LUT3_7/CNT_DLY1(8bit) Output
LUT3_8/CNT_DLY2(8bit) Output
LUT3_9/CNT_DLY3(8bit) Output
LUT3_10/CNT_DLY4(8bit) Output
LUT3_11/Pipe Delay (1st stage) Output/Ripple CNT Output0
LUT3_5/DFF8 Output
LUT4X2_0 Output0
LUT4X2_0 Output1
RTC CNT 1 second Output
RTC DCOMP Output
Pipe Delay Output0/Ripple CNT Output1
Pipe Delay Output1/Ripple CNT Output2
Internal OSC Post-Divided by 1/2/3/4/8/12/24/64 Output (25KHz/
2MHz)
27
28
Internal OSC Post-Divided by 1/2/3/4/8/12/24/64 Output (25KHz/
2MHz)
0
1
1
1
0
0
29
30
31
32
33
34
35
36
LPOSC Output
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
1
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
Filter0/Edge Detect0 Output
Filter1/Edge Detect1 Output
I2C_virtual_0 Input
I2C_virtual_1 Input
I2C_virtual_2 Input
I2C_virtual_3 Input
I2C_virtual_4 Input
Datasheet
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 39: Matrix Input Table(Continued)
Matrix Decode
Matrix Input
Matrix Input Signal Function
Number
5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
I2C_virtual_5 Input
I2C_virtual_6 Input
I2C_virtual_7 Input
ASM-stateX-dout0
ASM-stateX-dout1
ASM-stateX-dout2
ASM-stateX-dout3
ASM-stateX-dout4
ASM-stateX-dout5
ASM-stateX-dout6
ASM-stateX-dout7
BG_OK Output
LDO0 nFault
LDO1 nFault
LDO2 nFault
LDO3 nFault
IO3 Digital Input (GPI)
IO4 Digital Input
IO5 Digital Input
IO6 Digital Input
ACMP_0 Output
ACMP_1 Output
ACMP_2 Output
ACMP_3 Output
Programmable Delay with Edge Detector Output
nRST_core (POR) as matrix input
VDD
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
6.2 MATRIX OUTPUT TABLE
Table 40: Matrix Output Table
Register Bit
Matrix Output
Number
Matrix Output Signal Function
Address
7:0
Matrix OUT: ASM-state0-EN0
0
15:8
Matrix OUT: ASM-state0-EN1
1
23:16
Matrix OUT: ASM-state0-EN2
2
31:24
Matrix OUT: ASM-state1-EN0
3
39:32
Matrix OUT: ASM-state1-EN1
4
47:40
Matrix OUT: ASM-state1-EN2
5
55:48
Matrix OUT: ASM-state2-EN0
6
63:56
Matrix OUT: ASM-state2-EN1
7
71:64
Matrix OUT: ASM-state2-EN2
8
79:72
Matrix OUT: ASM-state3-EN0
9
87:80
Matrix OUT: ASM-state3-EN1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
95:88
Matrix OUT: ASM-state3-EN2
103:96
111:104
119:112
127:120
135:128
143:136
151:144
159:152
167:160
175:168
183:176
191:184
199:192
207:200
215:208
223:216
231:224
239:232
247:240
255:248
263:256
271:264
279:272
287:280
295:288
303:296
Matrix OUT: ASM-state4-EN0
Matrix OUT: ASM-state4-EN1
Matrix OUT: ASM-state4-EN2
Matrix OUT: ASM-state5-EN0
Matrix OUT: ASM-state5-EN1
Matrix OUT: ASM-state5-EN2
Matrix OUT: ASM-state6-EN0
Matrix OUT: ASM-state6-EN1
Matrix OUT: ASM-state6-EN2
Matrix OUT: ASM-state7-EN0
Matrix OUT: ASM-state7-EN1
Matrix OUT: ASM-state7-EN2
Matrix OUT: ASM-state-nRST
Matrix OUT: IN0 of LUT3_6 or Delay0 Input (or Counter0 RST Input)
Matrix OUT: IN1 of LUT3_6 or External Clock Input of Delay0 (or Counter0)
Matrix OUT: IN2 of LUT3_6
Matrix OUT: IN0 of LUT3_7 or Delay1 Input (or Counter1 RST Input)
Matrix OUT: IN1 of LUT3_7 or External Clock Input of Delay1 (or Counter1)
Matrix OUT: IN2 of LUT3_7
Matrix OUT: IN0 of LUT3_8 or Delay2 Input (or Counter2 RST Input)
Matrix OUT: IN1 of LUT3_8 or External Clock Input of Delay2 (or Counter2)
Matrix OUT: IN2 of LUT3_8
Matrix OUT: IN0 of LUT3_9 or Delay3 Input (or Counter3 RST Input)
Matrix OUT: IN1 of LUT3_9 or External Clock Input of Delay3 (or Counter3)
Matrix OUT: IN2 of LUT3_9
Matrix OUT: IN0 of LUT3_10 or Delay4 Input (or Counter4 RST Input)
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 40: Matrix Output Table(Continued)
Register Bit
Matrix Output
Number
Matrix Output Signal Function
Address
311:304
319:312
327:320
335:328
343:336
351:344
359:352
367:360
375:368
383:376
391:384
399:392
407:400
415:408
423:416
431:424
439:432
447:440
455:448
463:456
471:464
479:472
487:480
495:488
503:496
511:504
519:512
527:520
535:528
543:536
551:544
559:552
567:560
575:568
583:576
591:584
599:592
607:600
615:608
Matrix OUT: IN1 of LUT3_10 or External Clock Input of Delay4 (or Counter4)
Matrix OUT: IN2 of LUT3_10
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
Matrix OUT: IO0 Digital Output Source
Matrix OUT: IO0 Output Enable
Matrix OUT: IO1 Digital Output Source
Reserved
Reserved
Matrix OUT: IO2 Digital Output Source
Matrix OUT: IO2 Output Enable
Matrix OUT: IO4 Digital Output Source
Matrix OUT: IO4 Output Enable
Matrix OUT: IO5 Digital Output Source
Matrix OUT: IO6 Digital Output Source
Matrix OUT: IO6 Output Enable
Matrix OUT: ACMP0 PWR UP
Matrix OUT: ACMP1 PWR UP
Matrix OUT: ACMP2 PWR UP
Matrix OUT: ACMP3 PWR UP
Matrix OUT: Input of Filter_0 with fixed time edge detector
Matrix OUT: Input of Filter_1 with fixed time edge detector
Matrix OUT: Input of Programmable Delay & Edge Detector
Matrix OUT: OSC 25KHz/2MHz PD (Power-Down)
Matrix OUT: LPOSC PD (Power-Down)
Matrix OUT: IN0 of LUT2_0 or Clock Input of DFF0
Matrix OUT: IN1 of LUT2_0 or Data Input of DFF0
Matrix OUT: IN0 of LUT2_1 or Clock Input of DFF1
Matrix OUT: IN1 of LUT2_1 or Data Input of DFF1
Matrix OUT: IN0 of LUT2_2 or Clock Input of DFF2
Matrix OUT: IN1 of LUT2_2 or Data Input of DFF2
Matrix OUT: IN0 of LUT3_0 or Clock Input of DFF3
Matrix OUT: IN1 of LUT3_0 or Data Input of DFF3
Matrix OUT: IN2 of LUT3_0 or nRST (nSET) of DFF3
Matrix OUT: IN0 of LUT3_1 or Clock Input of DFF4
Matrix OUT: IN1 of LUT3_1 or Data Input of DFF4
Matrix OUT: IN2 of LUT3_1 or nRST (nSET) of DFF4
Matrix OUT: IN0 of LUT3_2 or Clock Input of DFF5
Matrix OUT: IN1 of LUT3_2 or Data Input of DFF5
Matrix OUT: IN2 of LUT3_2 or nRST (nSET) of DFF5
Matrix OUT: IN0 of LUT3_3 or Clock Input of DFF6
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 40: Matrix Output Table(Continued)
Register Bit
Matrix Output
Number
Matrix Output Signal Function
Address
623:616
631:624
639:632
647:640
655:648
Matrix OUT: IN1 of LUT3_3 or Data Input of DFF6
Matrix OUT: IN2 of LUT3_3 or nRST (nSET) of DFF6
Matrix OUT: IN0 of LUT3_4 or Clock Input of DFF7
Matrix OUT: IN1 of LUT3_4 or Data Input of DFF7
Matrix OUT: IN2 of LUT3_4 or nRST (nSET) of DFF7
77
78
79
80
81
Matrix OUT: IN0 of LUT3_11 or Input of Pipe Delay or Up/Down selection of Ripple
Counter
663:656
82
671:664
679:672
687:680
695:688
703:696
711:704
719:712
727:720
735:728
Matrix OUT: IN1 of LUT3_11 or nRST of Pipe Delay or nRST of Ripple Counter
Matrix OUT: IN2 of LUT3_11 or Clock of Pipe Delay or Clock of Ripple Counter
Matrix OUT: IN0 of LUT3_5 or Clock Input of DFF8
Matrix OUT: IN1 of LUT3_5 or Data Input of DFF8
Matrix OUT: IN2 of LUT3_5 or nRST (nSET) of DFF8
Matrix OUT: IN0 of LUT4X2_0
83
84
85
86
87
88
89
90
91
Matrix OUT: IN1 of LUT4X2_0
Matrix OUT: IN2 of LUT4X2_0
Matrix OUT: IN3 of LUT4X2_0
Matrix OUT: LDO LP Mode Enable
for LDO0/1/2/3
743:736
751:744
92
93
Matrix OUT:
LDO0_EN
759:752
767:760
775:768
Matrix OUT: LDO1_EN
Matrix OUT: LDO2_EN
Matrix OUT: LDO3_EN
94
95
96
Matrix OUT:
LDO0 2nd VOUT Selection Enable
783:776
97
791:784
799:792
807:800
815:808
823:816
831:824
839:832
Matrix OUT: LDO1 2nd VOUT Selection Enable
Matrix OUT: LDO2 2nd VOUT Selection Enable
Matrix OUT: LDO3 2nd VOUT Selection Enable
Matrix OUT: RTC Clock
98
99
100
101
102
103
104
Matrix OUT: RTC Trigger signal to read/write RTC CNT values
Matrix OUT: ON/OFF command for Synchronous DC/DC Step Down Converter
Reserved
Note 1 For each Address, the two most significant bits are unused.
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
6.3 CONNECTION MATRIX VIRTUAL INPUTS
As mentioned previously, the Connection Matrix inputs come from the outputs of various digital macrocells on the device. Eight
of the Connection Matrix inputs have the special characteristic that the state of these signal lines comes from a corresponding
data bit written as a register value via I2C. This gives the user the ability to write data via the serial channel, and have this
information translated into signals that can be driven into the Connection Matrix and from the Connection Matrix to the digital
inputs of other macrocells on the device. The I2C address for reading and writing these register values is at 0xF4 (0244).
Eight Connection Matrix Virtual Inputs are dedicated to this virtual input function. An I2C write command to these register bits will
set the signal values going into the Connection Matrix to the desired state. A read command to these register bits will read either
the original data values coming from the NVM memory bits (that were loaded during the initial device startup), or the values from
a previous write command (if that has happened).
See Table 41 for Connection Matrix Virtual Inputs.
Table 41: Connection Matrix Virtual Inputs
Matrix Input
Number
Register Bit
Addresses (d)
Matrix Input Signal Function
32
33
34
35
36
37
38
39
I2C_virtual_0 Input
I2C_virtual_1 Input
I2C_virtual_2 Input
I2C_virtual_3 Input
I2C_virtual_4 Input
I2C_virtual_5 Input
I2C_virtual_6 Input
I2C_virtual_7 Input
[1952]
[1953]
[1954]
[1955]
[1956]
[1957]
[1958]
[1959]
6.4 CONNECTION MATRIX VIRTUAL OUTPUTS
The digital outputs of the various macrocells are routed to the Connection Matrix to enable interconnections to the inputs of other
macrocells in the device. At the same time, it is possible to read the state of each of the macrocell outputs as a register value via
I2C. This option, called Connection Matrix Virtual Outputs, allows the user to remotely read the values of each macrocell output.
The I2C addresses for reading these register values are 0x70 (0112) to 0x71 (0113). Write commands to these same register
values will be ignored (with the exception of the Virtual Input register bits at 0xF4 (0244)).
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
7
Combination Function Macrocells
The SLG46585 has 15 combination function macrocells that can serve more than one logic or timing function. In each case, they
can serve as a Look Up Table (LUT), or as another logic or timing function. See the list below for the functions that can be
implemented in these macrocells.
Three macrocells that can serve as either 2-bit LUTs or as D Flip-Flops
Six macrocells that can serve as either 3-bit LUTs or as D Flip-Flops with Set/Reset Input
One macrocell that can serve as either 3-bit LUT or as Pipe Delay or as a Ripple Counter
Five macrocells that can serve as either 3-bit LUTs or as 8-Bit Counter/Delays
Inputs/Outputs for the 15 combination function macrocells are configured from the connection matrix with specific logic functions
being defined by the state of NVM bits.
When used as a LUT to implement combinatorial logic functions, the outputs of the LUTs can be configured to any user defined
function, including the following standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR).
7.1 2-BIT LUT OR D FLIP-FLOP MACROCELLS
There are three macrocells that can serve as either 2-bit LUTs or as D Flip-Flops. When used to implement LUT functions, the
2-bit LUTs each take in two input signals from the connection matrix and produce a single output, which goes back into the
connection matrix. When used to implement D Flip-Flop function, the two input signals from the connection matrix go to the data
(D) and clock (CLK) inputs for the Flip-Flop, with the output going back to the connection matrix.
The operation of the D Flip-Flop and LATCH will follow the functional descriptions below:
DFF: CLK is rising edge triggered, then Q = D; otherwise Q will not change
LATCH: if CLK = 0, then Q = D
register [1151] DFF or LATCH Select
register [1150] Output Select (Q or nQ)
register [1149] DFF Initial Polarity Select
IN1
S0
From Connection Matrix Output [62]
OUT
2-bit LUT0
0: 2-bit LUT0 IN1
1: DFF0 Data
S1
IN0
LUT Truth
Table
To Connection Matrix
S0
Input [6]
4-bits NVM
registers [1151:1148]
0: 2-bit LUT0 OUT
1: DFF0 OUT
S1
DFF
Registers
D
S0
S1
From Connection Matrix Output [61]
Q/nQ
DFF0
0: 2-bit LUT0 IN0
1: DFF0 CLK
CLK
1-bit NVM
register [1135]
Figure 9: 2-bit LUT0 or DFF0
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
register [1147] DFF or LATCH Select
register [1146] Output Select (Q or nQ)
register [1145] DFF Initial Polarity Select
IN1
S0
From Connection Matrix Output [64]
OUT
2-bit LUT1
0: 2-bit LUT1 IN1
1: DFF1 Data
S1
IN0
LUT Truth
Table
To Connection Matrix
S0
Input [7]
4-bits NVM
registers [1147:1144]
0: 2-bit LUT1 OUT
1: DFF1 OUT
S1
DFF
Registers
D
S0
S1
From Connection Matrix Output [63]
Q/nQ
DFF1
0: 2-bit LUT1 IN0
1: DFF1 clk
CLK
1-bit NVM
register [1134]
Figure 10: 2-bit LUT1 or DFF1
register [1159] DFF or LATCH Select
register [1158] Output Select (Q or nQ)
register [1157] DFF Initial Polarity Select
IN1
S0
S1
From Connection Matrix Output [66]
OUT
2-bit LUT2
0: 2-bit LUT2 IN1
1: DFF2 Data
IN0
LUT Truth
Table
To Connection Matrix
S0
Input [8]
4-bits NVM
registers [1159:1156]
0: 2-bit LUT2 OUT
1: DFF2 OUT
S1
DFF
Registers
D
S0
From Connection Matrix Output [65]
Q/nQ
DFF2
0: 2-bit LUT2 IN0
1: DFF2 clk
S1
CLK
1-bit NVM
register [1133]
Figure 11: 2-bit LUT2 or DFF2
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
7.1.1 2-Bit LUT or D Flip-Flop Macrocell Used as 2-Bit LUT
Table 42: 2-bit LUT0 Truth Table
Table 44: 2-bit LUT2 Truth Table
IN1
0
IN0
0
OUT
IN1
0
IN0
0
OUT
register [1148]
register [1149]
register [1150]
register [1151]
LSB
register [1156]
register [1157]
register [1158]
register [1159]
LSB
0
1
0
1
1
0
1
0
1
1
MSB
1
1
MSB
Table 43: 2-bit LUT1 Truth Table
IN1
0
IN0
0
OUT
register [1144]
register [1145]
register [1146]
register [1147]
LSB
0
1
1
0
1
1
MSB
Each macrocell, when programmed for a LUT function, uses a 4-bit register to define their output function:
2-Bit LUT0 is defined by registers [1151:1148]
2-Bit LUT1 is defined by registers [1147:1144]
2-Bit LUT2 is defined by registers [1159:1156]
Table 45 shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be created
within each of the three 2-bit LUT logic cells.
Table 45: 2-bit LUT Standard Digital Functions
Function
AND-2
MSB
LSB
1
0
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
1
0
1
NAND-2
OR-2
NOR-2
XOR-2
XNOR-2
7.1.2 2-Bit LUT or D Flip-Flop Macrocells Used as D Flip-Flop Register Settings
Table 46: DFF0 Register Settings
Register Bit
Address
Signal Function
Register Definition
LUT2_0 or DFF0
Select
[1135]
0: LUT2_0
1: DFF0
DFF0 Initial Polarity
Select
[1149]
[1150]
[1151]
0: Low
1: High
DFF0 Output Select
0: Q output
1: nQ output
DFF0 or LATCH
Select
0: DFF function
1: LATCH function
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 47: DFF1 Register Settings
Register Bit
Signal Function
Address
Register Definition
LUT2_1 or DFF1
Select
[1134]
0: LUT2_1
1: DFF1
DFF1 Initial Polarity
Select
[1145]
[1146]
[1147]
0: Low
1: High
DFF1 Output Select
0: Q output
1: nQ output
DFF1 or LATCH
Select
0: DFF function
1: LATCH function
Table 48: DFF2 Register Settings
Register Bit
Signal Function
Address
Register Definition
LUT2_2 or DFF2
Select
[1133]
0: LUT2_2
1: DFF2
DFF2 Initial Polarity
Select
[1157]
[1158]
[1159]
0: Low
1: High
DFF2 Output Select
0: Q output
1: nQ output
DFF2 or LATCH
Select
0: DFF function
1: LATCH function
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
7.1.3 Initial Polarity Operations
VDD
Data
Clock
POR
Initial Polarity: High
Q
Initial Polarity: Low
Q
Figure 12: DFF Polarity Operations
7.2 3-BIT LUT OR D FLIP-FLOP WITH SET/RESET MACROCELLS
There are six macrocells that can serve as either 3-bit LUTs or as D Flip-Flops with Set/Reset inputs. When used to implement
LUT functions, the 3-bit LUTs each take in three input signals from the connection matrix and produce a single output, which goes
back into the connection matrix. When used to implement D Flip-Flop function, the three input signals from the connection matrix
go to the data (D) and clock (CLK), and Reset/Set (nRST/nSET) inputs for the Flip-Flop, with the output going back to the
connection matrix.
DFF3 has a user selectable option to allow the macrocell output to either come from the Q/nQ output of one D Flip-Flop, or two
D Flip-Flops in series, with the first D Flip-Flop triggering on the rising clock edge, and the second D Flip-Flop triggering on the
falling clock edge.
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
register [1167] DFF or LATCH Select
register [1166] Output Select (Q or nQ)
register [1165] DFF nRST or nSET Select
register [1164] DFF Initial Polarity Select
IN2
From Connection
Matrix Output [69]
S0
IN1
IN0
OUT
3-bit LUT0
S1
LUT Truth
Table
From Connection
Matrix Output [68]
To Connection Matrix
S0
S1
S0
S1
Input [9]
8-bits NVM
registers [1167:1160]
register [1431]
DFF3
nRST/nSET
From Connection
Matrix Output [67]
S0
S1
D
Q/nQ
Q
D
D
Q
CLK
register [1166]
register [1431] Selects output from one or two DFF
1-bit NVM
register [1132]
Figure 13: 3-bit LUT0 or DFF3
register [1175] DFF or LATCH Select
register [1174] Output Select (Q or nQ)
register [1173] DFF nRST or nSET Select
register [1172] DFF Initial Polarity Select
IN2
From Connection
Matrix Output [72]
S0
S1
IN1
OUT
3-bit LUT1
IN0
LUT Truth
Table
From Connection
Matrix Output [71]
To Connection Matrix
S0
S1
S0
S1
Input [10]
8-bits NVM
registers [1175:1168]
DFF
Registers
D
From Connection
Matrix Output [70]
S0
S1
nRST/nSET
CLK
DFF4
Q/nQ
1-bit NVM
register [1131]
Figure 14: 3-bit LUT1 or DFF4
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
register [1183] DFF or LATCH Select
register [1182] Output Select (Q or nQ)
register [1181] DFF nRST or nSET Select
register [1180] DFF Initial Polarity Select
IN2
From Connection
Matrix Output [75]
S0
S1
IN1
IN0
OUT
3-bit LUT2
LUT Truth
Table
From Connection
Matrix Output [74]
To Connection Matrix
S0
S1
S0
Input [11]
8-bits NVM
registers [1183:1176]
S1
DFF
Registers
D
From Connection
Matrix Output [73]
S0
S1
nRST/nSET
CLK
DFF5
Q/nQ
1-bit NVM
register [1130]
Figure 15: 3-bit LUT2 or DFF5
register [1191] DFF or LATCH Select
register [1190] Output Select (Q or nQ)
register [1189] DFF nRST or nSET Select
register [1188] DFF Initial Polarity Select
IN2
From Connection
Matrix Output [78]
S0
S1
IN1
OUT
3-bit LUT3
IN0
LUT Truth
Table
From Connection
Matrix Output [77]
To Connection Matrix
S0
S1
Input [12]
S0
8-bits NVM
registers [1191:1184]
S1
DFF
Registers
D
From Connection
Matrix Output [76]
S0
S1
nRST/nSET
CLK
DFF6
Q/nQ
1-bit NVM
register [1129]
Figure 16: 3-bit LUT3 or DFF6
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
register [1199] DFF or LATCH Select
register [1198] Output Select (Q or nQ)
register [1197] DFF nRST or nSET Select
register [1196] DFF Initial Polarity Select
IN2
From Connection
Matrix Output [81]
S0
S1
IN1
IN0
OUT
3-bit LUT4
LUT Truth
Table
From Connection
Matrix Output [80]
To Connection Matrix
S0
S1
S0
Input [13]
8-bits NVM
registers [1199:1192]
S1
DFF
Registers
D
From Connection
Matrix Output [79]
S0
S1
nRST/nSET
CLK
DFF7
Q/nQ
1-bit NVM
register [1128]
Figure 17: 3-bit LUT4 or DFF7
register [1207] DFF or LATCH Select
register [1206] Output Select (Q or nQ)
register [1205] DFF nRST or nSET Select
register [1204] DFF Initial Polarity Select
IN2
From Connection
Matrix Output [87]
S0
S1
IN1
OUT
3-bit LUT5
IN0
LUT Truth
Table
From Connection
Matrix Output [86]
To Connection Matrix
S0
S1
S0
Input [20]
8-bits NVM
registers [1207:1200]
S1
DFF
Registers
D
From Connection
Matrix Output [85]
S0
S1
nRST/nSET
CLK
DFF8
Q/nQ
1-bit NVM
register [1138]
Figure 18: 3-bit LUT5 or DFF8
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
7.2.1 3-Bit LUT or D Flip-Flop Macrocells Used as 3-Bit LUT
Table 49: 3-bit LUT0 Truth Table
Table 52: 3-bit LUT3 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
register [1160]
register [1161]
register [1162]
register [1163]
register [1164]
register [1165]
register [1166]
register [1167]
LSB
register [1184]
register [1185]
register [1186]
register [1187]
register [1188]
register [1189]
register [1190]
register [1191]
LSB
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
MSB
LSB
1
1
1
MSB
LSB
Table 50: 3-bit LUT1 Truth Table
Table 53: 3-bit LUT4 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
register [1168]
register [1169]
register [1170]
register [1171]
register [1172]
register [1173]
register [1174]
register [1175]
register [1192]
register [1193]
register [1194]
register [1195]
register [1196]
register [1197]
register [1198]
register [1199]
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
MSB
LSB
1
1
1
MSB
LSB
Table 51: 3-bit LUT2 Truth Table
Table 54: 3-bit LUT5 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
register [1176]
register [1177]
register [1178]
register [1179]
register [1180]
register [1181]
register [1182]
register [1183]
register [1200]
register [1201]
register [1202]
register [1203]
register [1204]
register [1205]
register [1206]
register [1207]
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
MSB
1
1
1
MSB
Each macrocell, when programmed for a LUT function, uses a 8-bit register to define their output function:
3-Bit LUT0 is defined by registers [1167:1160]
3-Bit LUT1 is defined by registers [1175:1168]
3-Bit LUT2 is defined by registers [1183:1176]
3-Bit LUT3 is defined by registers [1191:1184]
3-Bit LUT4 is defined by registers [1199:1192]
3-Bit LUT5 is defined by registers [1207:1200]
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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Table 55 shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be created
within each of the six 3-bit LUT logic cells.
Table 55: 3-bit LUT Standard Digital Functions
Function
AND-3
MSB
LSB
1
0
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
1
0
1
NAND-3
OR-3
NOR-3
XOR-3
XNOR-3
7.2.2 3-BIT LUT OR D FLIP-FLOP MACROCELLS USED AS D FLIP-FLOP REGISTER SETTINGS
Table 56: DFF3 Register Settings
Register Bit
Address
Signal Function
Register Definition
LUT3_0 or DFF3
Select
[1132]
0: LUT3_0
1: DFF3
DFF3 Initial Polarity
Select
[1164]
[1165]
[1166]
[1167]
0: Low
1: High
DFF3 nRST/nSET
Select
0: nRST from matrix out
1: nSET from matrix out
DFF3 Output Select
0: Q output
1: nQ output
DFF3 or LATCH
Select
0: DFF function
1: LATCH function
Table 57: DFF4 Register Settings
Register Bit
Signal Function
Address
Register Definition
LUT3_1 or DFF4
Select
[1131]
0: LUT3_1
1: DFF4
DFF4 Initial Polarity
Select
[1172]
[1173]
[1174]
[1175]
0: Low
1: High
DFF4 nRST/nSET
Select
0: nRST from matrix out
1: nSET from matrix out
DFF4 Output Select
0: Q output
1: nQ output
DFF4 or LATCH
Select
0: DFF function
1: LATCH function
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Table 58: DFF5 Register Settings
Register Bit
Signal Function
Address
Register Definition
LUT3_2 or DFF5
Select
[1130]
0: LUT3_2
1: DFF5
DFF5 Initial Polarity
Select
[1180]
[1181]
[1182]
[1183]
0: Low
1: High
DFF5 nRST/nSET
Select
0: nRST from matrix out
1: nSET from matrix out
DFF5 Output Select
0: Q output
1: nQ output
DFF5 or LATCH
Select
0: DFF function
1: LATCH function
Table 59: DFF6 Register Settings
Register Bit
Signal Function
Address
Register Definition
LUT3_3 or DFF6
Select
[1129]
0: LUT3_3
1: DFF6
DFF6 Initial Polarity
Select
[1188]
[1189]
[1190]
[1191]
0: Low
1: High
DFF6 nRST/nSET
Select
0: nRST from matrix out
1: nSET from matrix out
DFF6 Output Select
0: Q output
1: nQ output
DFF6 or LATCH
Select
0: DFF function
1: LATCH function
Table 60: DFF7 Register Settings
Register Bit
Signal Function
Address
Register Definition
LUT3_4 or DFF7
Select
[1128]
0: LUT3_4
1: DFF7
DFF7 Initial Polarity
Select
[1196]
[1197]
[1198]
[1199]
0: Low
1: High
DFF7 nRST/nSET
Select
0: nRST from matrix out
1: nSET from matrix out
DFF7 Output Select
0: Q output
1: nQ output
DFF7 or LATCH
Select
0: DFF function
1: LATCH function
Table 61: DFF8 Register Settings
Register Bit
Signal Function
Address
Register Definition
LUT3_5 or DFF8
Select
[1138]
0: LUT3_5
1: DFF8
DFF8 Initial Polarity
Select
[1204]
0: Low
1: High
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Table 61: DFF8 Register Settings(Continued)
Register Bit
Address
Signal Function
Register Definition
DFF8 nRST/nSET
Select
[1205]
0: nRST from matrix out
1: nSET from matrix out
DFF8 Output Select
[1206]
[1207]
0: Q output
1: nQ output
DFF8 or LATCH
Select
0: DFF function
1: LATCH function
7.2.3 Initial Polarity Operations
VDD
Data
Clock
POR
Initial Polarity: High
nReset (Case 1)
Q with nReset (Case 1)
nReset (Case 2)
Q with nReset (Case 2)
Initial Polarity: Low
nReset (Case 1)
Q with nReset (Case 1)
nReset (Case 2)
Q with nReset (Case 2)
Figure 19: DFF Polarity Operations with nReset
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VDD
Data
Clock
POR
Initial Polarity: High
nSet (Case 1)
Q with nSet (Case 1)
nSet (Case 2)
Q with nSet (Case 2)
Initial Polarity: Low
nSet (Case 1)
Q with nSet (Case 1)
nSet (Case 2)
Q with nSet (Case 2)
Figure 20: DFF Polarity Operations with nSet
7.3 3-BIT LUT OR PIPE DELAY/RIPPLE COUNTER MACROCELL
There is one macrocell that can serve as either a 3-bit LUT or as a Pipe Delay/Ripple Counter.
When used to implement LUT functions, the 3-bit LUT takes in three input signals from the connection matrix and produces a
single output, which goes back into the connection matrix.
When used as a Pipe Delay, there are three inputs signals from the matrix, Input (IN), Clock (CLK), and Reset (RST). The Pipe
Delay cell is built from 16 D Flip-Flop logic cells that provide the three delay options, two of which are user selectable. The DFF
cells are tied in series where the output (Q) of each delay cell goes to the next DFF cell input (IN). Both of the two outputs (OUT0
and OUT1) provide user selectable options for 1 – 16 stages of delay. There are delay output points for each set of the OUT0 and
OUT1 outputs to a 16-input MUX that is controlled by registers [1227:1224] for OUT0 and registers [1231:1228] for OUT1. The
16-input MUX is used to select the amount of delay.
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The overall time of the delay is based on the clock used in the SLG46585 design. Each DFF cell has a time delay of the inverse
of the clock time (either external clock or the RC Oscillator within the SLG46585). The sum of the number of DFF cells used will
be the total time delay of the Pipe Delay logic cell. OUT1 Output can be inverted (as selected by register [1239]).
In the Ripple Counter mode there are 3 options for setting, which use 7 bits. There are 3 bits to set nSET value (SV) in range
from 0 to 7. It is a value, which will be set into the Ripple Counter outputs when nSET input goes LOW. End value (EV) will use
3 bits for setting outputs code, which will be last code in the cycle. After reaching the EV, the Ripple Counter goes to the first code
by the rising edge on CLK input. The Functionality mode option uses 1 bit. This setting defines how exactly Ripple Counter will
operate.
We can select one of the functionality modes by the register: RANGE or FULL. If the RANGE option is selected, the count starts
from SV. If UP input is LOW the count goes down: SV→EV→EV-1 to SV+1→SV and others. (if SV is smaller than EV) or SV→SV-1
to EV+1→EV→SV (if SV is bigger than EV). If UP input is HIGH, count starts from SV up to EV and others.
In the FULL range configuration the Ripple Counter functions as follows. If UP input is LOW, the count starts from SV and goes
down to 0. Then current counter value jumps to EV and goes down to 0 etc.
If UP input is HIGH, count goes up starting from SV. Then current counter value jumps to 0 and counts up to EV etc. Please see
Ripple counter functionality example in Figure 22.
Every step is executed by the rising edge on CLK input.
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registers [1231:1224]
From Connection
Matrix Output [82]
IN0
From Connection
Matrix Output [83]
IN1
IN2
OUT
3-bit LUT11
From Connection
Matrix Output [84]
registers [1231:1228]
Pipe Delay
register [1239]
0
0
1
OUT2
OUT1
To Connection
Matrix Input [26]
1
register [1238]
From Connection
Matrix Output [82]
IN
From Connection
Matrix Output [83]
nRST
16 Flip-Flops
0
1
OUT1
From Connection
Matrix Output [84]
CLK
To Connection
Matrix Input [25]
register [1238]
OUT0
0
OUT0
To Connection
Matrix Input [19]
0
1
1
registers [1227:1224]
register [1238]
Ripple Counter
3 Flip-Flops
UP
From Connection
Matrix Output [82]
UP/DOWN
Control
OUT0
D
Q
DFF1
CLK
From Connection
Matrix Output [84]
clk
nQ
nSET
From Connection
Matrix Output [83]
SET
OUT1
OUT2
Control
D
Q
DFF2
clk
nQ
Mode & SET/END
Value Control
D
Q
DFF3
nQ
clk
registers [1231:1224]
Figure 21: 3-bit LUT11/Pipe Delay/Ripple Counter
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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Figure 22: Example: Ripple Counter Functionality
7.3.1 3-Bit LUT or Pipe Delay Macrocells Used as 3-Bit LUT
Table 62: 3-bit LUT11 Truth Table
IN2
0
IN1
0
IN0
0
OUT
register [1224]
register [1225]
register [1226]
register [1227]
register [1228]
register [1229]
register [1230]
register [1231]
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
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Each macrocell, when programmed for a LUT function, uses a 8-bit register to define their output function:
3-Bit LUT11 is defined by registers [1231:1224]
7.3.2 3-Bit LUT or Pipe Delay Macrocells Used as Pipe Delay Register Settings
Table 63: Pipe Delay Register Settings
Register Bit Ad-
Signal Function
OUT0 select
dress
[1227:1224]
[1231:1228]
[1237]
Register Definition
OUT1 select
PipeDelayorRipple
Counter select
0: Pipe Delay
1: Ripple Counter
LUT3_11 or Pipe
Delay Output select
[1238]
[1239]
0: LUT3_11
1: Pipe Delay/Ripple Counter by register [1237]
Pipe delay OUT1
Polarity Select Bit
0: Non-inverted
1: Inverted
7.4 3-BIT LUT OR 8-BIT COUNTER/DELAY MACROCELLS
There are five macrocells that can serve as either 3-bit LUTs or as Counter/Delays. When used to implement LUT function, the
3-bit LUT takes in three input signals from the connection matrix and produces a single output, which goes back into the
connection matrix. When used to implement 8-Bit Counter/Delay function, two of the three input signals from the connection matrix
go to the external clock (EXT_CLK) and reset (DLY_IN/CNT Reset) for the counter/delay, with the output going back to the
connection matrix.
These macrocells can also operate in a one-shot mode, which will generate an output pulse of user-defined width.
These macrocells can also operate in a frequency detection or edge detection mode.
Two of the five macrocells can have their active count value read via I2C (CNT2 and CNT4). See Section 19.5.2 for further
details.
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7.4.1 3-Bit LUT or 8-Bit CNT/DLY Block Diagrams
From Connection
Matrix Output [27]
S0
IN2
S1
3-bit LUT6
IN1
IN0
From Connection
Matrix Output [26]
S0
S1
OUT
LUT Truth
Table
To Connection
Matrix Input [14]
S0
S1
8-bits NVM
registers [1543:1536]
CNT
Data
CLK
From Connection
Matrix Output [25]
S0
S1
OUT
CNT/DLY0
DLY_IN/CNT Reset
1-bit NVM
register [1143]
Figure 23: 3-bit LUT6 or CNT/DLY0
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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From Connection
Matrix Output [30]
S0
IN2
S1
3-bit LUT7
IN1
IN0
From Connection
Matrix Output [29]
S0
S1
OUT
LUT Truth
Table
To Connection
Matrix Input [15]
S0
S1
8-bits NVM
registers [1551:1544]
CNT
Data
CLK
From Connection
Matrix Output [28]
S0
S1
OUT
CNT/DLY1
DLY_IN/CNT Reset
1-bit NVM
register [1142]
Figure 24: 3-bit LUT7 or CNT/DLY1
From Connection
Matrix Output [33]
S0
S1
IN2
3-bit LUT8
IN1
From Connection
Matrix Output [32]
S0
S1
OUT
IN0
LUT Truth
Table
To Connection
Matrix Input [16]
S0
S1
8-bits NVM
registers [1559:1552]
CNT
Data
CLK
From Connection
Matrix Output [31]
S0
S1
OUT
CNT/DLY2
DLY_IN/CNT Reset
1-bit NVM
register [1141]
Figure 25: 3-bit LUT8 or CNT/DLY2
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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From Connection
Matrix Output [36]
S0
IN2
S1
3-bit LUT9
IN1
IN0
From Connection
Matrix Output [35]
S0
S1
OUT
LUT Truth
Table
To Connection
Matrix Input [17]
S0
S1
8-bits NVM
registers [1567:1560]
CNT
Data
CLK
From Connection
Matrix Output [34]
S0
S1
OUT
CNT/DLY3
DLY_IN/CNT Reset
1-bit NVM
register [1140]
Figure 26: 3-bit LUT9 or CNT/DLY3
From Connection
Matrix Output [39]
S0
S1
IN2
3-bit LUT10
IN1
From Connection
Matrix Output [38]
S0
S1
OUT
IN0
LUT Truth
Table
To Connection
Matrix Input [18]
S0
S1
8-bits NVM
registers [1575:1568]
CNT
Data
CLK
From Connection
Matrix Output [37]
S0
S1
OUT
CNT/DLY4
DLY_IN/CNT Reset
1-bit NVM
register [1139]
Figure 27: 3-bit LUT10 or CNT/DLY4
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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7.4.2 3-Bit LUT or CNT/DLYs Used as 3-Bit LUTs
Table 64: 3-bit LUT6 Truth Table
Table 67: 3-bit LUT9 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
register [1536]
register [1537]
register [1538]
register [1539]
register [1540]
register [1541]
register [1542]
register [1543]
register [1560]
register [1561]
register [1562]
register [1563]
register [1564]
register [1565]
register [1566]
register [1567]
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
Table 65: 3-bit LUT7 Truth Table
Table 68: 3-bit LUT10 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
register [1544]
register [1545]
register [1546]
register [1547]
register [1548]
register [1549]
register [1550]
register [1551]
register [1568]
register [1569]
register [1570]
register [1571]
register [1572]
register [1573]
register [1574]
register [1575]
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
Table 66: 3-bit LUT8 Truth Table
IN2
0
IN1
0
IN0
0
OUT
register [1552]
register [1553]
register [1554]
register [1555]
register [1556]
register [1557]
register [1558]
register [1559]
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Each macrocell, when programmed for a LUT function, uses a 8-bit register to define their output function:
3-Bit LUT6 is defined by registers [1543:1536]
3-Bit LUT7 is defined by registers [1551:1544]
3-Bit LUT8 is defined by registers [1559:1552]
3-Bit LUT9 is defined by registers [1567:1560]
3-Bit LUT10 is defined by registers [1575:1568]
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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Table 69 shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be created
within each of the six 3-bit LUT logic cells.
Table 69: 3-bit LUT Standard Digital Functions
Function
AND-3
MSB
LSB
1
0
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
1
0
1
NAND-3
OR-3
NOR-3
XOR-3
XNOR-3
7.4.3 3-Bit LUT or 8-Bit Counter/Delay Macrocells Used as 8-Bit Counter/Delay Register Settings
Table 70: CNT/DLY0 Register Settings
Register Bit
Address
Signal Function
Register Definition
LUT3_6 or
Counter0 Select
[1143]
0: LUT3_6
1: Counter0
Delay0 Mode Select
or asynchronous
counter reset
[1241:1240]
[1244:1242]
00: on both falling and rising edges (for delay & counter reset)
01: on falling edge only (for delay & counter reset)
10: on rising edge only (for delay & counter reset)
11: no delay on either falling or rising edges/high level reset
Counter/delay0
Clock Source Select
000: Internal OSC clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: LPOSC
110: External Clock
111: Counter4 Overflow
CNT0‘s Q are Set to
data or Reset to 0s
Selection (8 bits)
[1245]
0: Reset to 0s
1: Set to data (Register [1543:1536])
Counter/delay0
Mode Selection
[1247:1246]
00: Delay mode
01: One Shot
10: Freq. Detect
11: Counter mode
Counter/delay0
Control Data
[1543:1536]
1 – 256 (delay time = (counter control data +1)/freq)
Table 71: CNT/DLY1 Register Settings
Register Bit
Signal Function
Address
Register Definition
LUT3_7 or
Counter1 Select
[1142]
0: LUT3_7
1: Counter1
Delay1 Mode Select
or asynchronous
counter reset
[1249:1248]
00: on both falling and rising edges (for delay & counter reset)
01: on falling edge only (for delay & counter reset)
10: on rising edge only (for delay & counter reset)
11: no delay on either falling or rising edges/high level reset
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Table 71: CNT/DLY1 Register Settings(Continued)
Register Bit
Address
Signal Function
Register Definition
Counter/delay1
Clock Source Select
[1252:1250]
000: Internal OSC clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: LPOSC
110: External Clock
111: Counter0 Overflow
Counter/delay1
Output Selection for
Counter mode
[1253]
[1236]
0: Default Output
1: Edge Detector Output
Counter/delay1
Delayed Edge
Output Selection
0: Default Output from register [1253]
1: Delayed Edge Detect
Counter/delay1
Mode Selection
[1255:1254]
00: Delay mode
01: One Shot
10: Freq. Detect
11: Counter mode
Counter/delay1
Control Data
[1551:1544]
1 – 256 (delay time = (counter control data +1)/freq)
Table 72: CNT/DLY2 Register Settings
Register Bit
Signal Function
Address
Register Definition
LUT3_8 or
Counter2 Select
[1141]
0: LUT3_8
1: Counter2
Delay2 Mode Select
or asynchronous
counter reset
[1257:1256]
[1260:1258]
00: on both falling and rising edges (for delay & counter reset)
01: on falling edge only (for delay & counter reset)
10: on rising edge only (for delay & counter reset)
11: no delay on either falling or rising edges/high level reset
Counter/delay2
Clock Source Select
000: Internal OSC clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: LPOSC
110: External Clock
111: Counter1 Overflow
Counter/delay2
Output Selection for
Counter mode
[1261]
[1235]
0: Default Output
1: Edge Detector Output
Counter/delay2
Delayed Edge
Output Selection
0: Default Output from register [1261]
1: Delayed Edge Detect
Counter/delay2
Mode Selection
[1263:1262]
00: Delay mode
01: One Shot
10: Freq. Detect
11: Counter mode
Counter/delay2
Control Data
[1559:1552]
1 – 256 (delay time = (counter control data +1)/freq)
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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Table 73: CNT/DLY3 Register Settings
Register Bit
Signal Function
Address
Register Definition
LUT3_9 or
Counter3 Select
[1140]
0: LUT3_9
1: Counter3
Delay3 Mode Select
or asynchronous
counter reset
[1265:1264]
[1268:1266]
00: on both falling and rising edges (for delay & counter reset)
01: on falling edge only (for delay & counter reset)
10: on rising edge only (for delay & counter reset)
11: no delay on either falling or rising edges/high level reset
Counter/delay3
Clock Source Select
000: Internal OSC clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: LPOSC
110: External Clock
111: Counter2 Overflow
Counter/delay3
Output Selection for
Counter mode
[1269]
[1234]
0: Default Output
1: Edge Detector Output
Counter/delay3
Delayed Edge
Output Selection
0: Default Output from register [1269]
1: Delayed Edge Detect
Counter/delay3
Mode Selection
[1271:1270]
00: Delay mode
01: One Shot
10: Freq. Detect
11: Counter mode
Counter/delay3
Control Data
[1567:1560]
1 – 256 (delay time = (counter control data +1)/freq)
Table 74: CNT/DLY4 Register Settings
Register Bit
Signal Function
Address
Register Definition
LUT3_10 or
Counter4 Select
[1139]
0: LUT3_10
1: Counter4
Delay4 Mode Select
or asynchronous
counter reset
[1273:1272]
[1276:1274]
00: on both falling and rising edges (for delay & counter reset)
01: on falling edge only (for delay & counter reset)
10: on rising edge only (for delay & counter reset)
11: no delay on either falling or rising edges/high level reset
Counter/delay4
Clock Source Select
000: Internal OSC clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: LPOSC
110: External Clock
111: Counter1 Overflow
Counter/delay4
Output Selection for
Counter mode
[1277]
[1233]
0: Default Output
1: Edge Detector Output
Counter/delay4
Delayed Edge
Output Selection
0: Default Output from register [1277]
1: Delayed Edge Detect
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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Table 74: CNT/DLY4 Register Settings(Continued)
Register Bit
Address
Signal Function
Register Definition
Counter/delay4
Mode Selection
[1279:1278]
00: Delay mode
01: One Shot
10: Freq. Detect
11: Counter mode
Counter/delay4
Control Data
[1575:1568]
1 – 256 (delay time = (counter control data +1)/freq)
Table 75: DLY/CNT Polarity Select
Register Bit
Signal Function
Address
Register Definition
Select thepolarity of
DLY/CNT0’s output
[1287]
0: Default Output
1: Inverted Output
Select thepolarity of
DLY/CNT1’s output
[1286]
[1285]
[1284]
[1283]
0: Default Output
1: Inverted Output
Select thepolarity of
DLY/CNT2’s output
0: Default Output
1: Inverted Output
Select thepolarity of
DLY/CNT3’s output
0: Default Output
1: Inverted Output
Select thepolarity of
DLY/CNT4’s output
0: Default Output
1: Inverted Output
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
7.5 CNT/DLY TIMING DIAGRAMS
7.5.1 Delay Mode (Edge Select: Both, Counter Data:3)
delay_in
Asynchronous delay variable
Asynchronous delay variable
RC osc: force Power-On
(always running)
Delay output
delay = period x (counter data + 1) + variable
variable is from 0 to 1 clock period
delay = period x (counter data + 1) + variable
variable is from 0 to 1 clock period
delay_in
offset
offset
RC osc: auto Power-On
(powers up from delay in)
Delay output
delay = offset + period x (counter data + 1)
offset = approx. 4-22 µs at room temp.
delay = offset + period x (counter data + 1)
offset = approx. 4-22 µs at room temp.
Figure 28: Delay Mode Timing Diagram
7.5.2 Count Mode (Count Data:3), Counter Reset (Rising Edge Detect Reset by Reset_In Input)
RESET_IN
CLK
Counter OUT
4 clk period pulse
Count start in 2 CLK + variable after reset
Figure 29: Counter Mode Timing Diagram with Reset Signal
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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7.5.3 Count Mode (Count Data:3), Counter Set (Rising Edge Detect Set by Set_In Input)
SET_IN
CLK
Counter OUT
4 CLK period pulse
Figure 30: Counter Mode Timing Diagram with SET Signal (only for DLY/CNT0)
7.5.4 One-Shot Mode
This macrocell will generate a pulse whenever a selected edge is detected on its input. Register bits set the edge selection. The
pulse width determines by counter data and clock selection properties. The output pulse polarity (non-inverted or inverted) is
selected by register bit. There is also an option to ignore or detect selected edge during pulse is outputting. The following diagram
is showing one-shot function for non-inverted output.
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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Delay time
Delay time
Delay time
Delay time
Delay time
One-Shot/Freq. DET/Delay IN
t
t
Delay time
One-Shot Function
Rising Edge Detection
One-Shot Function
Falling Edge Detection
t
t
One-Shot Function
Both Edge Detection
Figure 31: One-Shot Function Timing Diagram
This macrocell generates a high level pulse with a set width (defined by counter data and clock selection properties) when
detecting the respective edge. It does not restart while pulse is high.
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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7.5.5 Frequency Detection Mode
Delay time
Delay time
Delay time
Delay time
Delay time
One-Shot/Freq. DET/Delay IN
t
t
Delay time
Frequency Detector Function
Rising Edge Detection
Frequency Detector Function
Falling Edge Detection
t
t
Frequency Detector Function
Both Edge Detection
Figure 32: Frequency Detection Mode Timing Diagram
Rising Edge: The output goes high if the time between two successive rising edges is less than the set time. The output goes low
if the second rising edge has not come after the last rising edge in specified time.
Falling Edge: The output goes high if the time between two successive falling edges is less than the set time. The output goes
low if the second falling edge has not come after the last falling edge in specified time.
Both Edge: The output goes high if the time between the rising and falling edges is less than the set time, which is equivalent to
the length of the pulse. The output goes low if after the last rising/falling edge and specified time, the second edge has not come.
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
7.5.6 Edge Detection Mode
The macrocell generates high level short pulse when detecting the respective edge. See Table 12.
Delay time
Delay time
Delay time
Delay time
Delay time
One-Shot/Freq. DET/Delay IN
t
t
Edge Detector Function
Rising Edge Detection
Edge Detector Function
Falling Edge Detection
t
t
Edge Detector Function
Both Edge Detection
Figure 33: Edge Detection Mode Timing Diagram (Except DLY/CNT0)
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
7.5.7 Delayed Edge Detection Mode
In Delayed Edge Detection Mode, High level short pulses are generated on the macrocell output after the configured delay time
if the corresponding edge was detected on the input.
If the input signal is changed during the set delay time, the pulse will not be generated. See Figure 34.
Delay time
Delay time
Delay time
Delay time
Delay time
One-Shot/Freq. DET/Delay IN
t
Delay time
Delay Function
Rising Edge Detection
t
Delay Function
Falling Edge Detection
t
Delay Function
Both Edge Detection
t
Figure 34: Delay Mode Timing Diagram (Except DLY/CNT0)
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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7.5.8 Delay Mode
The macrocell shifts the respective edge to a set time and restarts by appropriate edge. It works as a filter if the input signal is
shorter than the delay time.
Delay time
Delay time
Delay time
Delay time
Delay time
One-Shot/Freq. DET/Delay IN
t
Delay time
Delay Function
Rising Edge Detection
t
Delay Function
Falling Edge Detection
t
Delay Function
Both Edge Detection
t
Figure 35: Delay Mode Timing Diagram
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
7.6 WAKE AND SLEEP CONTROLLER
The SLG46585 has a Wake and Sleep function for all ACMPs. The macrocell CNT/DLY0 can be reconfigured for this purpose
registers [1247:1246] = 11 and register [1447] = 1. The WS serves for power saving, it allows to switch on and off selected ACMPs
on selected bit of 8-bit counter.
Power Control
From Connection Matrix Output[59] for configurable 25 kHz/2 MHz OSC
or From Connection Matrix Output[60] for 1.73 kHz Low Power Osc.
WS Controller
OSC
CNT0_out
cnt_end
CNT
ck
To Connection Matrix Input [14]
000:/1
001:/4
010:/12
011:/24
100:/64
CK_OSC
Analog Control Block
ACMP WS EN [3:0]
registers [1445:1442]
4
4
1 us
delay
bg/regulator
pdb
From Connection
Matrix Output [55:52]
WS_out
WS_PD
WS_PD
(from OSC PD)
ACMPs_PD
WS_out
WS_PD to W&S out
state selection
registers [1244:1242]
WS clock freq. selection
registers [1543:1536]
WS ratio control data
ACMPs
register [1446]
Wake Sleep Output State when WS
OSC is powered down
(if DLY/CNT0 Mode Selection is "11")
ACMP0..3 OUT
4
+
-
0
1
4
To Connection
Matrix Input
[60:57]
ACMPs_PD
WS_out
nRST
BG/Analog_Good
Note: WS_PD is High at WS OSC
(1.73 kHz Low Power OSC) powered
Figure 36: Wake/Sleep Controller
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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ACMP_PD is High
through the Connection
Matrix
CNT_out (to CM)
1 us
ACMP output is latched,
and BG/Analog is powered off
WS_out
(internal signal)
BG/Analog_Good
(internal signal)
BG/Analog ON Start
Sleep Mode
Normal ACMP
Operation
Sleep Mode (maintains latched ACMP output
BG/Analog
stabilization time*
Note: * Refer to Electrical Spec (ACMP Start Time)
Figure 37: Wake/Sleep Timing Diagram
To use any ACMP under WS controller the following settings must be done:
ACMP Power Up Input from matrix = 1 (for each ACMP separately).
CNT/DLY0 must be set to Wake and Sleep Controller function (for all ACMPs).
Register WS => enable (for each ACMP separately).
CNT/DLY0 set/reset input = 0 (for all ACMPs).
For the OSC, any oscillator with any pre-divider can be used. The user can select a period of time while the ACMPs are sleeping
in a range of 1 - 255 clock cycles. Before they are sent to sleep their outputs are latched so the ACMPs remain their state (High
or Low) while sleeping. When the WS signal is High, it takes a BG time (refer to electrical spec) to turn the ACMPs on. The wake
time must be longer than BG/Analog Power-On time.
Note: If 25 kHz/2 MHz Oscillator is used for WS, the 1.73 kHz Low Power OSC must be set to Force Power-On.
WS controller has the following settings:
Wake and Sleep Output State (High/Low)
If OSC is powered off (Power-Down option is selected; Power-Down input = 1) and Wake and Sleep Output State = High,
the ACMP is continuously on
If OSC is powered off (Power-Down option is selected; Power-Down input = 1) and Wake and Sleep Output State = Low, the
ACMP is continuously off
Both cases WS function is turned off
Counter Data (Range: 1 to 255)
User can select wake and sleep ratio of the ACMP; counter data = sleep time, one clock = wake time.
Q mode - defines the state of WS counter data when Set/Reset signal appears
Reset - when active signal appears, the WS counter will reset to zero and High level signal on its output will turn the ACMPs
on. When Reset signal goes out, the WS counter will go Low and turn the ACMPs off until the counter counts up to the end
Set - when active signal appears, the WS counter will stop and Low level signal on its output will turn the ACMPs off. When
Set signal goes out, the WS counter will go on counting and High level signal will turn the ACMPs on while counter is counting
up to the end.
Edge Select defines the edge for Q mode
High level Set/Reset - switches mode Set/Reset when level is High.
Note: Q mode operates only in case of "High Level Set/Reset”.
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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8
Combinatorial Logic
8.1 4-BIT LUT WITH TWO OUTPUTS
There is one 4-bit LUT with two outputs. The device also includes fifteen Combination Function Macrocells that can be used as
LUTs. For more details please see Section 8.
Inputs/Outputs for the nine LUTs are configured from the connection matrix with specific logic functions being defined by the
state of NVM bits. The outputs of the LUTs can be configured to any user defined function, including the following standard
digital logic devices (AND, NAND, OR, NOR, XOR, XNOR).
registers [1519:1504]
From Connection
Matrix Output [88]
LUT Truth
Table for OUT0
IN0
From Connection
Matrix Output [89]
From Connection
Matrix Input [21]
OUT0
OUT1
IN1
IN2
From Connection
Matrix Output [90]
4-bit LUT0
From Connection
Matrix Input [22]
From Connection
Matrix Output [91]
IN3
LUT Truth
Table for OUT1
registers [1535:1520]
Figure 38: 4-bit LUT0 with Two Outputs
Table 76: 4-bit LUT0 Truth Table
IN3
0
IN2
0
IN1
0
IN0
0
OUT0
OUT1
register [1504]
register [1505]
register [1506]
register [1507]
register [1508]
register [1509]
register [1510]
register [1511]
register [1512]
register [1513]
register [1514]
register [1515]
register [1516]
register [1517]
register [1518]
register [1519]
register [1520]
register [1521]
register [1522]
register [1523]
register [1524]
register [1525]
register [1526]
register [1527]
register [1528]
register [1529]
register [1530]
register [1531]
register [1532]
register [1533]
register [1534]
register [1535]
LSB
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
MSB
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
This macrocell uses a 16-bit register to define their output function. Table 77 shows the register bits for the standard digital logic
devices (AND, NAND, OR, NOR, XOR, XNOR) that can be created within the 4-bit LUT logic cell.
4-Bit LUT0 OUT0 is defined by registers [1519:1504]
4-Bit LUT0 OUT1 is defined by registers [1535:1520]
Table 77: 4-bit LUT Standard Digital Functions
Function
AND-4
MSB
LSB
1
0
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
1
0
1
NAND-4
OR-4
NOR-4
XOR-4
XNOR-4
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9
Analog Comparators
There are four Analog Comparator (ACMP) macrocells in the SLG46585. In order for the ACMP cells to be used in a GreenPAK
design, the power up signals (ACMP0 PWR UP, ACMP1 PWR UP, ACMP2 PWR UP, and ACMP3 PWR UP) need to be active.
By connecting to signals coming from the Connection Matrix, it is possible to have each ACMP be on continuously, off continu-
ously, or switched on periodically based on a digital signal coming from the Connection Matrix. When ACMP is powered down,
output is LOW.
Each of the ACMP cells has a positive input signal that can be provided by a variety of external sources, and can also have a
selectable gain stage before connection to the analog comparator. Each of the ACMP cells has a negative input signal that is
either created from an internal Vref or provided by way of the external sources.
PWR UP = 1 => ACMP is powered up.
PWR UP = 0 => ACMP is powered down.
During power-up, the ACMP output will remain low, and then become valid 2 ms (max) after ACMP power up signal goes HIGH.
If VDD is greater than 2.7 V, then power up time will decrease.
Vref accuracy is optimized near 1000 mV selection.
Input bias current < 1 nA (typ). The Gain divider is unbuffered and consists of 1 MΩ resistors. IN- voltage range: 0 to 1.2 V. Can
use Vref selection VDD/4 and VDD/3 to maintain this input range.
Table 78: Gain Divider Input Resistance
Gain
x1
x0.5
x0.33
x0.25
1 MΩ
Input Resistance
100 MΩ
1 MΩ
0.75 MΩ
To ensure proper chip startup operation, it is recommended to enable the ACMPs with the POR signal, and not the VDD signal.
Each of theACMP cells has a selection for the bandwidth of the input signal, which can be used to save power when low bandwidth
signals are input into the analog comparator.
Note that power supply control options have influence on Analog macrocells operation.
Note: Any ACMP powered ON enables the BandGap circuit as well, and an analog voltage will appear on Vref (even when Force
BandGap is disabled).
Each cell also has a hysteresis selection, to offer hysteresis of (0, 25, 50, 200) mV. ACMP2 and ACMP3 has additional hysteresis
options for 100 mV and 150 mV.
Note: the 25 mV hysteresis option works with either internal or external Vref, while all other options work with internal Vref only.
The (50, 100, 150, 200) mV hysteresis options are one way hysteresis. This means that actual thresholds will be Vref (high
threshold) and Vref - hysteresis (low threshold). The ACMP output will retain its output value if the input voltage is within the
threshold window (between Vref and Vref - hysteresis). The 25 mV hysteresis option threshold levels will be Vref + hysteresis/2
(high threshold) and Vref - hysteresis/2 (low threshold).
Hysteresis: Input signal hysteresis options are disable, 25 mV, 50 mV, 200 mV (and additionally 100 mV and 150 mV for ACMP2
and ACMP3).
ACMP0 IN+ options are IO1, buffered IO1, VDD, LDO0/1 VIN
ACMP1 IN+ options are IO2, buffered IO2, ACMP0 IN+, LDO2/3 VIN
ACMP2 IN+ options are IO5, ACMP0 IN+, Temp. Sensor
ACMP3 IN+ options are IO6, ACMP2 IN+, LDO0 VOUT and LDO2 VOUT
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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9.1 ACMP0 BLOCK DIAGRAM AND REGISTER SETTINGS
to ACMP1, ACMP2
register [1631]
MUX input
registers [1119:1118]
LBW
Selection
UVLO_0
Hysteresis
Selection
registers [1630:1629]
VDD (2.5 V to 5.5 V)
001
010
000
100
BG_ok
Selectable
Gain
+
-
IO1
To Connection
Matrix Input[57]
L/S
0
1
Vref
LDO VIN*(2.5 V to 5.5 V)
PWR UP
Latch
register [1495]; register [1117]; register [1116]
register [1442]
IO4: EXT_Vref/2
IO4: EXT_Vref
11011
11010
11001
11000
10111-
00000
VDD: ACMP0-/4
VDD: ACMP0-/3
From Connection
Matrix Output [52]
Internal
Vref
registers [1628:1624]
Note*: See Sections 2.2 to 2.4.
Figure 39: ACMP0 Block Diagram
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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Table 79: ACMP0 Register Settings
Register Bit
Signal Function
Address
Register Definition
ACMP0 Positive
Input Source Select
VDD
[1116]
0: Disable
1: Enable
Analog Buffer at
ACMP0 Enable
(Max. BW 1 MHz)
[1117]
0: Disable analog buffer
1: Enable analog buffer
ACMP0 Hysteresis
Enable
[1119:1118]
00: Disabled (0 mV)
01: Enabled (25 mV)
10: Enabled (50 mV)
11: Enabled (200 mV)
(01: for both external & internal Vref; 10 & 11: for only internal Vref; External Vref will
not have 50 mV & 200 mV hysteresis.)
ACMP0 Wake &
Sleep function
Enable
[1442]
[1495]
0: Disable
1: Enable
LDO0/1 VIN
connection enable
0: Default ACMP function
1: Enable UVLO0 function
to ACMP0
ACMP0 In Voltage
Select
[1628:1624]
00000: 50 mV
00010: 150 mV
00100: 250 mV
00110: 350 mV
01000: 450 mV
01010: 550 mV
01100: 650 mV
01110: 750 mV
10000: 850 mV
10010: 950 mV
10100: 1.05 V
10110: 1.15 V
00001: 100 mV
00011: 200 mV
00101: 300 mV
00111: 400 mV
01001: 500 mV
01011: 600 mV
01101: 700 mV
01111: 800 mV
10001: 900 mV
10011: 1 V
10101: 1.1 V
10111: 1.2 V
11000: VDD: ACMP0-/3
11001: VDD: ACMP0-/4
11010: IO4: EXT_Vref
11011: IO4: EXT_Vref/2
ACMP0 Positive
Input Divider
[1630:1629]
[1631]
00: 1.00x
01: 0.50x
10: 0.33x
11: 0.25x
ACMP0 Low
Bandwidth (Max: 1
0: Off
1: On
MHz) Enable
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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9.2 ACMP1 BLOCK DIAGRAM AND REGISTER SETTINGS
1.8 V
register [1639]
registers [1115:1114]
100 µA
LBW
Selection
UVLO_1
Hysteresis
Selection
register [1488]
registers [1638:1637]
From ACMP0’s MUX output
001
BG_ok
010
000
100
Selectable
Gain
+
-
IO2
LDO VIN* (2.5 V to 5.5 V)
To Connection
Matrix Input[58]
L/S
0
1
Vref
PWR UP
Latch
register [1494]; register [1113]; register [1112]
register [1443]
IO4: EXT_Vref/2
IO4: EXT_Vref
11011
11010
11001
11000
10111-
00000
VDD: ACMP1-/4
VDD: ACMP1-/3
From Connection
Matrix Output [53]
Internal
Vref
registers [1636:1632]
Note*: See Sections 2.2 to 2.4.
Figure 40: ACMP1 Block Diagram
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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Table 80: ACMP1 Register Settings
Register Bit
Signal Function
Address
Register Definition
ACMP1 Positive Input
Source Select -
[1112]
0: Disable
1: Enable
ACMP0 IN+ Source
Analog Buffer at
ACMP1 Enable (Max.
BW 1 MHz)
[1113]
0: Disable analog buffer
1: Enable analog buffer
ACMP1 Hysteresis
Enable
[1115:1114]
00: Disabled (0 mV)
01: Enabled (25 mV)
10: Enabled (50 mV)
11: Enabled (200 mV)
(01: for both external & internal Vref; 10 & 11: for only internal Vref; External Vref
will not have 50 mV & 200 mV hysteresis.)
ACMP1 Wake & Sleep
function Enable
[1443]
[1488]
[1494]
0: Disable
1: Enable
ACMP1 100 uA
Current Source Enable
0: Disable
1: Enable
LDO2/3 VIN
connection enable to
0: Default ACMP function
1: Enable UVLO1 function
ACMP1
ACMP1 In Voltage
Select
[1636:1632]
00000: 50 mV
00010: 150 mV
00100: 250 mV
00110: 350 mV
01000: 450 mV
01010: 550 mV
01100: 650 mV
01110: 750 mV
10000: 850 mV
10010: 950 mV
10100: 1.05 V
10110: 1.15 V
00001: 100 mV
00011: 200 mV
00101: 300 mV
00111: 400 mV
01001: 500 mV
01011: 600 mV
01101: 700 mV
01111: 800 mV
10001: 900 mV
10011: 1 V
10101: 1.1 V
10111: 1.2 V
11000: VDD: ACMP1-/3
11001: VDD: ACMP1-/4
11010: IO4: EXT_Vref
11011: IO4: EXT_Vref/2
ACMP1 Positive Input
Divider
[1638:1637]
[1639]
00: 1.00x
01: 0.50x
10: 0.33x
11: 0.25x
ACMP1 Low
Bandwidth (Max: 1
MHz) Enable
0: Off
1: On
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9.3 ACMP2 BLOCK DIAGRAM AND REGISTER SETTINGS
to ACMP3’s MUX input
register [1647]
registers [1127:1125]
LBW
Selection
Temp Sensor Out
Hysteresis
Selection
registers [1646:1645]
IO5
00
01
10
BG_ok
From ACMP0’s MUX output
Selectable
Gain
+
-
To Connection
Matrix Input[59]
L/S
0
1
Temp Sensor
Vref
PWR UP
Latch
register [1493]; register [1124]
register [1444]
IO4: EXT_VREF/2
IO4: EXT_VREF
11011
11010
11001
11000
10111-
00000
VDD: ACMP2-/4
0xB2: ACMP2-/3
From Connection
Matrix Output [54]
Internal
Vref
registers [1644:1640]
Figure 41: ACMP2 Block Diagram
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Table 81: ACMP2 Register Settings
Register Bit
Signal Function
Address
Register Definition
ACMP2 Positive Input
Source Select -
[1124]
0: Disable
1: Enable
ACMP0 IN+ Source
ACMP2 Hysteresis
Enable
[1127:1125]
000: 0 mV
001: 25 mV
010: 50 mV
011: 200 mV
100: Reserved
101: Reserved
110: 100 mV
111: 150 mV
(001: for both external & internal Vref, 010 & 011 & 110 & 111: for only internal Vref,
External Vref will not have (50, 100, 150, 200) mV hysteresis.)
ACMP2 Wake & Sleep
function Enable
[1444]
[1493]
0: Disable
1: Enable
TS output connection
enable to ACMP2
0: Default ACMP function
1: Enable TS function
ACMP2 In Voltage
Select
[1644:1640]
00000: 50 mV
00010: 150 mV
00100: 250 mV
00110: 350 mV
01000: 450 mV
01010: 550 mV
01100: 650 mV
01110: 750 mV
10000: 850 mV
10010: 950 mV
10100: 1.05 V
10110: 1.15 V
00001: 100 mV
00011: 200 mV
00101: 300 mV
00111: 400 mV
01001: 500 mV
01011: 600 mV
01101: 700 mV
01111: 800 mV
10001: 900 mV
10011: 1 V
10101: 1.1 V
10111: 1.2 V
11000: VDD: ACMP2-/3
11001: VDD: ACMP2-/4
11010: IO4: EXT_Vref
11011: IO4: EXT_Vref/2
ACMP2 Positive Input
Divider
[1646:1645]
[1647]
00: 1.00x
01: 0.50x
10: 0.33x
11: 0.25x
ACMP2 Low
Bandwidth (Max: 1
MHz) Enable
0: Off
1: On
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9.4 ACMP3 BLOCK DIAGRAM AND REGISTER SETTINGS
register [1655]
registers [1123:1121]
LBW
Selection
Hysteresis
Selection
registers [1654:1653]
IO6
LDO VOUT*
000
100
010
001
BG_ok
Selectable
Gain
+
-
LDO VOUT*
To Connection
Matrix Input[60]
L/S
0
1
From ACMP2’s MUX output
Vref
PWR UP
Latch
registers [1492:1491], [1120]
register [1445]
IO4: EXT_Vref/2
IO4: EXT_Vref
11011
11010
11001
11000
10111-
00000
VDD: ACMP3-/4
VDD: ACMP3-/3
From Connection
Matrix Output [55]
Internal
Vref
registers [1652:1648]
Note*: See Sections 2.2 to 2.4.
Figure 42: ACMP3 Block Diagram
Register Definition
Table 82: ACMP3 Register Settings
Register Bit
Signal Function
Address
ACMP3 Positive Input
Source Select -
[1120]
0: Disable
1: Enable
ACMP2 IN+ Source
ACMP3 Hysteresis
Enable
[1123:1121]
000: 0 mV
001: 25 mV
010: 50 mV
011: 200 mV
100: Reserved
101: Reserved
110: 100 mV
111: 150 mV
(001: for both external & internal Vref, 010 & 011 & 110 & 111: for only internal Vref,
External Vref will not have (50, 100, 150, 200) mV hysteresis.)
ACMP3 Wake & Sleep
function Enable
[1445]
[1491]
0: Disable
1: Enable
LDO2 VOUT output
connection enable to
ACMP3
0: Default ACMP function
1: Enable LDO2 VOUT function
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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Table 82: ACMP3 Register Settings(Continued)
Register Bit
Address
Signal Function
Register Definition
LDO0 VOUT output
connection enable to
ACMP3
[1492]
0: Default ACMP function
1: Enable LDO0 VOUT function
ACMP3 In Voltage
Select
[1652:1648]
00000: 50 mV
00010: 150 mV
00100: 250 mV
00110: 350 mV
01000: 450 mV
01010: 550 mV
01100: 650 mV
01110: 750 mV
10000: 850 mV
10010: 950 mV
10100: 1.05 V
10110: 1.15 V
00001: 100 mV
00011: 200 mV
00101: 300 mV
00111: 400 mV
01001: 500 mV
01011: 600 mV
01101: 700 mV
01111: 800 mV
10001: 900 mV
10011: 1 V
10101: 1.1 V
10111: 1.2 V
11000: VDD: ACMP3-/3
11001: VDD: ACMP3-/4
11010: IO4: EXT_Vref
11011: IO4: EXT_Vref/2
ACMP3 Positive Input
Divider
[1654:1653]
[1655]
00: 1.00x
01: 0.50x
10: 0.33x
11: 0.25x
ACMP3 Low
Bandwidth (Max: 1
0: Off
1: On
MHz) Enable
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9.5 ACMPS TYPICAL PERFORMANCE
Figure 43: ACMPs Power-On Delay vs. VDD
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10 Pipe Delay
The SLG46585 has a pipe delay logic cell that is shared with the 3-bit LUT11 in one of the Combination Function macrocells. The
user can select one of these functions to use in a design, but not both. Please see Section 7.3.1 for the description of this
Combination Function macrocell.
11 Programmable Delay/Edge Detector
The SLG46585 has a programmable time delay logic cell available that can generate a delay that is selectable from one of four
timings (time1) configured in the GreenPAK Designer. The programmable time delay cell can generate one of four different delay
patterns, rising edge detection, falling edge detection, both edge detection, and both edge delay. These four patterns can be
further modified with the addition of delayed edge detection, which adds an extra unit of delay as well as glitch rejection during
the delay period. See Figure 44 for further information.
Note: The input signal must be longer than the delay, otherwise it will be filtered out.
registers [1311:1310]
Delay Value Selection
registers [1309:1308]
Edge Mode Selection
To Connection
Matrix Input [61]
Programmable
From Connection Matrix Output [58]
IN
OUT
Delay
Figure 44: Programmable Delay
11.1 PROGRAMMABLE DELAY TIMING DIAGRAM - EDGE DETECTOR OUTPUT
width
width
IN
time1
Rising Edge Detector
time1
Falling Edge Detector
Edge Detector
Output
Both Edge Detector
Both Edge Delay
time2
time2
time1 is a fixed value
time2 delay value is selected via register
Figure 45: Edge Detector Output
Please refer to Table 12.
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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Table 83: Programmable Delay Register Settings
Register Bit
Signal Function
Address
Register Definition
Select the edge
mode of
programmable
delay & edge
detector
[1309:1308]
00: Rising Edge Detector
01: Falling Edge Detector
10: Both Edge Detector
11: Both Edge Delay
Delay value select
for programmable
delay & edge
detector
[1311:1310]
00: 165 ns
01: 300 ns
10: 440 ns
11: 575 ns
(VDD = 3.3 V, typical
condition)
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12 Additional Logic Functions
The SLG46585 has two additional logic functions that are connected directly to the Connection Matrix inputs and outputs. There
are two deglitch filters, each with edge detector functions.
12.1 DEGLITCH FILTER/EDGE DETECTOR
Filter_0
R
From Connection Matrix Output [56]
C
To Connection Matrix
Input [30]
Edge
Detect
register [1422]
register [1423]
Edge Select
registers [1421:1420]
Filter_1
R
From Connection Matrix Output [57]
C
Edge
Detect
To Connection Matrix
Input [31]
register [1418]
Edge Select
registers [1417:1416]
register [1419]
Figure 46: Deglitch Filter/Edge Detector
Table 84: Deglitch Filter Register Settings
Register Bit
Signal Function
Address
Register Definition
Filter_1/Edge
Detector_1 Edge
Select
[1417:1416]
00: Rising Edge Detector
01: Fall Edge Detector
10: Both Edge Detector
11: Both Edge Delay
Filter_1/Edge
Detector_1 output
Polarity Select
[1418]
[1419]
0: Filter_1 output
1: Filter_1 output inverted
Filter_1 or Edge
Detector_1 Select
(Typ. 50 nS
0: Filter_1
1: Edge Detector_1
@VDD=3.3 V)
Filter_0/Edge
Detector_0 Edge
Select
[1421:1420]
[1422]
00: Rising Edge Detector
01: Fall Edge Detector
10: Both Edge Detector
11: Both Edge Delay
Filter_0/Edge
0: Filter_0 output
Detector_0 output
1: Filter_0 output inverted
Polarity Select
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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Table 84: Deglitch Filter Register Settings(Continued)
Register Bit
Address
Signal Function
Register Definition
Filter_0 or Edge
Detector_0 Select
(Typ. 70 nS
[1423]
0: Filter_0
1: Edge Detector_0
@VDD=3.3 V)
13 RTC Binary Counter
The SLG46585 includes a 47-bit binary Real Time Counter (RTC) designed to continuously count time. This counter consists of
three components and can be programmed serially through an I2C serial interface.
The first component is a 15-bit Counter Divider used to divide the external clock, which generates a high level pulse (with width
equal to the RTC clock period) to Connection Matrix Input [23] when the counter reaches the end of the count. Since the RTC
counter is used for time keeping, the most common expected use case is to connect this 15-bit counter divider to a 32.768 kHz
clock source, in which case the output will be a pulse at 1 second intervals, with high time of ~30.5 µs.
The second component is the 32-bit Time Counter, which takes its clock input from either the output of the 15-bit counter divider,
or directly from Connection Matrix Output [101]. If the input clock comes from the 15-bit counter divider, and this counter divider
is used to count time in seconds (most common use case), then the count value in this 32-bit time counter will be the number of
seconds elapsed since it was loaded. The contents are read/write accessible via the address range 0x75 to 0x7A. When the
counter is read, the current time is latched into a shadow buffer register, which is output on the serial data line while the counter
continues to increment.
The third component is a 32-bit Alarm Digital Comparator (DCMP). This generates an alarm signal to Connection Matrix Input
[24] when the time counter value matches the DCMP alarm value, which is set via I2C serial interface. An I2C bus Master is used
to write to the 32-bit Alarm DCMP register bits in order to define the next wake up time. The 32-bit Alarm DCMP loads its initial
value from registers [1023:992] at POR, and can be changed at any time by I2C. The Alarm DCMP output is high for one clock
period of the 32-bit Time Counter.
I2C Address
Detector
RTC Counter
48-bit Shadow Buffer
S1
registers [983:936]
From Connection
Matrix Output [102]
S0
register [990]
Direction register [989]
S0
32-bit
TimeCounter
15-bit
Counter
Divider
From Connection
Matrix Output [101]
RTC Clock
S1
To Connection Matrix
Input [23]
RTC CNT
DIV Out
register [991]
To Connection Matrix
Input [24]
RTC
DCMP Out
32-bit
Alarm DCMP
registers [1023:992]
Figure 47: RTC Counter Macrocell
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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13.1 RTC BINARY COUNTER SHADOW BUFFER
All reading or writing of data to this macrocell goes through the 48-bit Shadow Buffer. In order to read the current RTC counter
value through the I2C, the RTC counter value must first be copied to the shadow buffer. The RTC Counter’s value can be copied
to the 48-bit shadow buffer by either rising edge trigger signal through the Connection Matrix Output [102] or by a trigger signal
generated by reading the I2C address at 0x75 to 0x7A. The same trigger signals are used to transfer data in the opposite
direction (from the shadow buffer to RTC counter).
48-bit Shadow Buffer data
47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 28 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32-bit Time Counter data
15-bit Counter Divider data
Unused data
Figure 48: RTC Counter Shadow Buffer Bits
Register [990] defines the source of the trigger signal for the copy to shadow buffer, either from the Connection Matrix or from
the designated I2C address read. The trigger source can be changed though an I2C write command to change this bit setting.
Register [989] defines the direction of whether RTC Counter data will be copied to 48-bit shadow buffer or the 48-bit shadow
buffer data will be copied to the RTC Counter. The direction can be changed though an I2C write command to change this bit
setting.
13.1.1 RTC Binary Counter Shadow Buffer Operating Modes
The combined values in register [990] and register [989] provide four modes of operation for the shadow buffer, allowing the user
to latch the shadow buffer data into the RTC counter, or to latch data the RTC counter data into the shadow buffer, and to choose
the signal that will latch the data.
Table 85: Shadow Buffer Register Settings
Register
[989]
Register
[990]
Shadow Buffer Operating Modes
0
0
0
1
RTC data will be latched in the shadow buffer by rising edge on Connection Matrix Output [102].
RTC data will be latched in the shadow buffer by reading any I2C address in the range 0x75 –
0x7A. The LATCH signal is activated when the I2C address comparison circuit indicates a match-
ing address in an incoming command. All bytes of one RTC data sample can be read using
Sequential Read Command.
1
1
0
1
Shadow buffer data will be latched in the RTC by rising edge on Connection Matrix Output [102].
Shadow buffer data willbelatchedintheRTC at the completionof awrite commandtoI2Caddress
in the range 0x75 to 0x7A. All bytes of one shadow buffer data sample can be written using
Sequential Write Command.
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14 Voltage Reference
14.1 VOLTAGE REFERENCE OVERVIEW
The SLG46585 has a Voltage Reference Macrocell to provide references to the four analog comparators. This macrocell can
supply a user selection of fixed voltage references, /3 and /4 reference off of the VDD power supply to the device, and externally
supplied voltage references from IO4. See Table 86 for the available selections for each analog comparator.
14.2 VREF SELECTION TABLE
Table 86: Vref Selection Table
SEL[4:0]
11011
11010
11001
11000
10111
10110
10101
10100
10011
10010
10001
10000
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
ACMP0_VREF
IO4: EXT_VREF/2
IO4: EXT_VREF
ACMP1_VREF
ACMP2_VREF
ACMP3_VREF
IO4: EXT_VREF/2
IO4: EXT_VREF/2
IO4: EXT_VREF/2
IO4: EXT_VREF
VDD: ACMP1-/4
VDD: ACMP1-/3
1.20
IO4: EXT_VREF
VDD: ACMP2-/4
VDD: ACMP2-/3
1.20
IO4: EXT_VREF
VDD: ACMP3-/4
VDD: ACMP3-/3
1.20
V
DD: ACMP0-/4
VDD: ACMP0-/3
1.20
1.15
1.15
1.15
1.15
1.10
1.10
1.10
1.10
1.05
1.05
1.05
1.05
1.00
1.00
1.00
1.00
0.95
0.95
0.95
0.95
0.90
0.90
0.90
0.90
0.85
0.85
0.85
0.85
0.80
0.80
0.80
0.80
0.75
0.75
0.75
0.75
0.70
0.70
0.70
0.70
0.65
0.65
0.65
0.65
0.60
0.60
0.60
0.60
0.55
0.55
0.55
0.55
0.50
0.50
0.50
0.50
0.45
0.45
0.45
0.45
0.40
0.40
0.40
0.40
0.35
0.35
0.35
0.35
0.30
0.30
0.30
0.30
0.25
0.25
0.25
0.25
0.20
0.20
0.20
0.20
0.15
0.15
0.15
0.15
0.10
0.10
0.10
0.10
0.05
0.05
0.05
0.05
Note: the ACMP external reference voltage (IN-) is limited by 1.2 V for full power supply range.
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15 Analog Temperature Sensor
The SLG46585 has an analog temperature sensor (TS) with an output voltage linearly-proportional to Centigrade temperature.
This feature was designed with a range from 50 °C to 150 °C as a tool to protect the chip from overheating. The TS's operates
based on the temperature coefficient of a Silicon diode (~-2.1 mV/°C). As the chip temperature increases, the TS's analog output
voltage decreases.
If the junction temperature exceeds the thresholds of ACMP2 or ACMP3, the ACMP outputs toggle and can shut down both
internal and external circuitry. Since most of the GreenPAK's self-heating originates within the LDO regulation circuitry, ACMP2's
output can lower the chip's junction temperature by disabling the LDOs.
The equation below calculates the typical analog voltage passed from the TS to the ACMPs' IN+ source input. It is important to
note that there will be a chip to chip variation of about ±2 °C.
VTS = -4.935 x T + 1467.03
where:
TS (mV) - TS Output Voltage
V
T (°C) - Temperature
Temperature hysteresis can be setup by enabling the GreenPAK's internal ACMP hysteresis. Many of the applicable ACMP
reference voltages are listed in Table 87, but for those that are not, use the previous equation to approximate the temperature level.
Table 87: Temperature Sensor Voltage for VDD = 2.5 V to 5.5 V
Vref, mV
700
TIL - Typ, °C
154.84
144.82
134.87
124.87
114.89
104.85
94.75
TIH - Typ, °C
155.06
145.47
135.61
125.65
115.63
105.56
95.42
750
800
850
900
950
1000
1050
1100
1150
1200
84.64
85.22
74.45
74.98
64.26
64.73
54.01
54.22
To enable the TS, set the TS enable register high in the "Temp Sensor" macrocell or the "ACMP2" macrocell's IN+ source settings.
In addition, the PWR UP matrix connection of ACMP2 or ACMP3 must be set high. See Figure 49 for the TS block diagram when
used with ACMP2 and ACMP3.
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ACMP2 PWR UP: Matrix Output [54]
ACMP3 PWR UP: Matrix Output [55]
TS
VDD
En
ACMP2 Positive Input Source Select - ACMP0 IN+ Source: register [1124]
TS Output Connection Enable to ACMP2: register [1493]
ACMP2 PWR UP:
Matrix Output [54]
Temp. Sensor_EN
register [1656]
LDO Temp.
Sensor Input
PWR UP
+
-
En
+
-
ACMP IN- Vref:
registers [1644:1640]
To Connection
Matrix Input[59]
ACMP2 Positive Input Divider
registers [1646:1645]
ACMP3 Positive Input Source Select - ACMP2 IN+ Source: register [1120]
LDO2 VOUT Output Connection Enable to ACMP3: register [1491]
LDO0 VOUT Output Connection Enable to ACMP3: register [1492]
ACMP3 PWR UP: Matrix Output [55]
To Connection
Matrix Input [60]
PWR UP
+
-
ACMP IN- Vref:
registers [1652:1648]
ACMP3 Positive Input Divider
registers [1654:1653]
Figure 49: Analog Temperature Sensor Structure Diagram
Note: If ACMP2 or/and ACMP3 is/are used for TS function, IO5 or/and IO6 should not be used as “Analog IO”.
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16 Clocking
16.1 OSC GENERAL DESCRIPTION
The SLG46585 has two internal oscillators to support a variety of applications:
Low Power Oscillator (1.73 kHz)
Configurable Oscillator (25 kHz or 2 MHz)
There are two divider stages that give the user flexibility for introducing clock signals to connection matrix, as well as various other
Macrocells. The pre-divider (first stage) for Configurable Oscillator allows the selection of /1, /2, /4 or /8 to divide down frequency
from the fundamental. The second stage divider has an input of frequency from the pre-divider, and outputs one of eight different
frequencies divided by /1, /2, /3, /4, /8, /12, /24 or /64 on Connection Matrix Input lines [27] and [28]. The second stage divider is
available to the configurable OSC (25 kHz or 2 MHz) only while the Low Power OSC is connected to Connection Matrix Input [29]
directly after the pre-divider /1, /2, /4 or /16 for LP OSC.
The Matrix Power-Down/Force On function allows switching off or force on the oscillator using an external pin. The Matrix
Power-Down/Force On (Connection Matrix Output [59] and [60) signal has the highest priority.The OSC operates according to
the Table 88.
Table 88: Oscillator Operation Mode Configuration Settings
Power-Down/Force ON
matrix control selection
registers [1658], [1657]
OSC POWER MODE
selection
registers [1295], [1290]
From Connection Matrix
Output [59], [60]
OSC operation mode
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Auto Power-On (Note 1)
ON
OFF
OFF
Auto Power-On (Note 1)
ON
ON
ON
Note 1 The OSC will run only when any macrocell that uses OSC is powered on.
The SLG46585 has a 25 kHz/2 MHz OSC Fast Start-up option up function controlled by register [1293] (1: Enabled; 0: Disabled).
It allows the OSC to have faster start up time, less than one OSC cycle when this option is enabled).
Note: The quiescent current consumption will increase when the OSC Fast Start-up option is enabled.
16.2 LOW POWER OSC (1.73 KHZ)
From Connection Matrix
Output [60]
PWR DWN/Force ON
Matrix Output control register [1657]
OSC Power Mode
register [1290]
registers [1289:1288]
PWR DOWN/
To Connection Matrix
Input [29]
FORCE ON
Low
Auto Power-On
OUT
DIV /1 /2 /4 /16
Power
OSC
0
Force Power-On
(1.73 kHz)
Pre-divider
1
Figure 50: Low Power Oscillator Block Diagram
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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16.3 CONFIGURABLE OSC(25 KHZ/2MHZ)
From Connection Matrix
Output [59]
PWR DWN/Force ON
Matrix Output control register [1658]
OSC Power Mode
register [1295]
Pre-divided Clock
PWR DOWN/
FORCE ON
registers [1292:1291]
Auto Power-On
Force Power-On
Config.
OSC
OUT
0
1
0
1
DIV /1 /2 /4 /8
0
1
IO0: EXT_CLK
pre-divider
/ 2
/ 3
register [1294]
register [1303]
0: 25 kHz
1: 2 MHz
2
3
4
5
6
7
To Connection Matrix
Input [27]
Ext. Clk Sel register [1282]
/ 4
/ 8
To Connection Matrix
Input [28]
/ 12
/ 24
/ 64
register [1299]
registers [1298:1296]
registers [1302:1300]
Second Stage
Divider
Figure 51: Configurable OSC Block Diagram
16.4 OSCILLATOR POWER-ON DELAY
OSC enable
Power-On
Delay
CLK
Figure 52: Oscillator Startup Diagram
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Note 1 OSC power mode: "Auto Power-On".
Note 2 'OSC enable' signal appears when any macrocell that uses OSC is powered on.
ꢎQ`I:Cꢍꢓꢕ:`ꢕRꢖ]ꢍ#QꢗV
&:'ꢕꢍꢓꢕ:`ꢕRꢖ]ꢍ#QꢗV
ꢆꢁꢁ
ꢅꢁꢁ
ꢄꢁꢁ
ꢃꢁꢁ
ꢂꢁꢁ
ꢀꢁꢁ
ꢔꢏꢏꢍ^ꢔ_
Figure 53: Oscillator Maximum Power-On Delay vs. VDD, T = +25 °C, OSC0 = 2 MHz
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ꢃꢀ
ꢂꢁ
ꢂꢀ
ꢁ
ꢕ:ꢖꢗꢍꢓꢗ:`ꢗRꢘ]ꢍ!QꢙV
ꢎQ`I:Cꢍꢓꢗ:`ꢗRꢘ]ꢍ!QꢙV
ꢀ
ꢔꢏꢏꢍ^ꢔ_
Figure 54: Oscillator Maximum Power-On Delay vs. VDD at T = 25 °C, OSC0 = 25 kHz
ꢇꢈꢂ
ꢇꢇꢂ
ꢇꢀꢂ
ꢇꢂꢂ
ꢀꢆꢂ
ꢀꢅꢂ
ꢀꢄꢂ
ꢀꢃꢂ
ꢀꢁꢂ
ꢖꢑꢑꢏ^ꢖ_
Figure 55: Oscillator Maximum Power-On Delay vs. VDD at T = 25 °C, OSC1 = 1.73 kHz
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16.5 OSCILLATOR ACCURACY
Note 1 OSC power setting: Force Power-On; Clock to matrix input - enable; Bandgap: turn on by register - enable.
Note 2 For more information see Section 3.6.
2.13
2.08
Fmax @ VDD=2.5 V
2.03
Fmax @ VDD=3.3 V
Fmax @ VDD=5.0 V
Fmin @ VDD=2.5 V
Fmin @ VDD=3.3 V
Fmin @ VDD=5.0 V
1.98
1.93
1.88
1.83
T (°C)
Figure 56: Oscillator Frequency vs. Temperature, OSC0 = 2 MHz
27
Fmax @ VDD=2.5 V
Fmax @ VDD=3.3 V
Fmax @ VDD=5.0 V
Fmin @ VDD=2.5 V
Fmin @ VDD=3.3 V
Fmin @ VDD=5.0 V
26.5
26
25.5
25
24.5
24
23.5
T (°C)
Figure 57: Oscillator Frequency vs. Temperature, OSC0 = 25 kHz
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2.1
2
1.9
1.8
Fmax @ VDD=2.5 V
Fmax @ VDD=3.3 V
1.7
Fmax @ VDD=5.0 V
Fmin @ VDD=2.5 V
1.6
Fmin @ VDD=3.3 V
1.5
1.4
1.3
1.2
1.1
Fmin @ VDD=5.0 V
Figure 58: Oscillator Frequency vs. Temperature, OSC1 = 1.73 kHz
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17 Power-On Reset
The SLG46585 has a Power-On Reset (POR) macrocell to ensure correct device initialization and operation of all macrocells in
the device. The purpose of the POR circuit is to have consistent behavior and predictable results when the VDD power is first
ramping to the device, and also while the VDD is falling during Power-down. To accomplish this goal, the POR drives a defined
sequence of internal events that trigger changes to the states of different macrocells inside the device, and finally to the state of
the IO pins.
17.1 GENERAL OPERATION
The SLG46585 is guaranteed to be powered down and non-operational when the VDD voltage (voltage on VDD pin) is less than
Power-Off Threshold (see Section 3.4), but not less than -0.6 V. Another essential condition for the chip to be powered down is
that no voltage higher (see Note) than the VDD voltage is applied to any other PIN. For example, if VDD voltage is 0.3 V, applying
a voltage higher than 0.3 V to any other PIN is incorrect and can lead to incorrect or unexpected device behavior.
Note: There is a 0.6 V margin due to forward drop voltage of the ESD protection diodes.
To start the POR sequence in the SLG46585, the voltage applied on the VDD should be higher than the Power-On threshold
(Note). The full operational VDD range for the SLG46585 is 2.5 V – 5.5 V. This means that the VDD voltage must ramp up to the
operational voltage value, but the POR sequence will start earlier, as soon as the VDD voltage rises to the Power-On threshold.
After the POR sequence has started, the SLG46585 will have a typical period of time to go through all the steps in the sequence
(noted in the datasheet for that device), and will be ready and completely operational after the POR sequence is complete.
Note: The Power_ON threshold is defined in Table 6.
Note: LDOs begin to operate when VDD ≥ 2.5 V.
To power-down the chip the VDD voltage should be lower than the operational and to guarantee that chip is powered down, it
should be less than Power-Off Threshold.
All PINs are in high impedance state when the chip is powered down and while the POR sequence is taking place. The last step
in the POR sequence releases the IO structures from the high impedance state, at which time the device is operational. The pin
configuration at this point in time is defined by the design programmed into the chip. Also, as it was mentioned before, the voltage
on PINs can’t be bigger than the VDD, this rule also applies to the case when the chip is powered on.
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17.2 POR SEQUENCE
The POR system generates a sequence of signals that enable certain macrocells. The sequence is shown in Figure 59.
Tsu
VDD
t
t
t
t
t
t
t
t
t
POR_NVM
(reset for NVM)
NVM_ready_out
POR_GPI
(reset for input enable)
POR_LUT
(reset for LUT output)
POR_CORE
(reset for DLY/RCO/DFF
/LATCH/Pipe DLY
POR_OUT
(generate low to high to matrix)
POR_GPO
ASM enable
(reset for output enable)
POR_LDO
Figure 59: POR Sequence
As can be seen from Figure 59 after the VDD has started ramping up and crossed the Power-On threshold, first, the on-chip NVM
memory is reset. Next, the chip reads the data from NVM, and transfers this information to a CMOS LATCH that serves to configure
each macrocell, and the Connection Matrix which routes signals between macrocells. The third stage causes the reset of the input
pins, and then to enable them. After that, the LUTs are reset and become active. After LUTs, the Delay cells, RC OSC, DFFs,
Latches, and Pipe Delay are initialized. Only after all macrocells are initialized, internal POR signal (POR macrocell output) goes
from LOW to HIGH (POR_OUT in Figure 59). The last portion of the device to be initialized is the output pins, which transition
from high impedance to active at this point. LDOs begin to operate in 500 µs after PINs become active.
The typical time that takes to complete the POR sequence varies by device type in the GreenPAK family. It also depends on many
environmental factors, such as: slew rate, VDD value, temperature, and even will vary from chip to chip (process influence).
17.3 MACROCELLS OUTPUT STATES DURING POR SEQUENCE
To have a full picture of SLG46585 operation during powering and POR sequence, review the overview of macrocell output states
during the POR sequence (Figure 60 describes the output signals states).
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First, before the NVM has been reset, all macrocells have their output set to logic LOW (except the output PINs which are in high
impedance state). Before the NVM is ready, all macrocell outputs are unpredictable (except the output PINs). On the next step,
some of the macrocells start initialization: input pins output state becomes LOW; LUTs also output LOW. After that input PINs are
enabled. Next, only LUTs are configured. Next, all other macrocells are initialized. After macrocells are initialized, internal POR
matrix signal switches from LOW to HIGH. The last are output PINs that become active and determined by the input signals.
VDD
Guaranteed HIGH before POR_GPI
t
VDD_out
to matrix
Unpredictable
t
Input PIN_out
Unpredictable
Unpredictable
Determined by External Signal
Determined by Input signals
to matrix
t
t
LUT_out
to matrix
Determined by input signals
OUT = IN without Delay
Prog. Edge_Detector_out
to matrix
Unpredictable
Unpredictable
Unpredictable
Unpredictable
Determined by Input signals
t
t
t
t
t
Determined by initial state
DFF/LATCH_out
to matrix
Determined by Input signals
Determined by input signals
OUT = IN without Delay
Delay_out
to matrix
Determined by Input signals
Starts to detect input edges
POR_out
to matrix
Ext. GPO
Tri-state
Determined by input signals
Output State Unpredictable
Figure 60: Internal Macrocell States during POR Sequence
17.3.1 Initialization
All internal macrocells by default have initial low level. Starting from indicated power-up time of 1.15 V - 1.6 V, macrocells are
powered on while forced to the reset state, All outputs are in Hi-Z and chip starts loading data from NVM. Then the reset signal
is released for internal macrocells and they start to initialize according to the following sequence:
1. Input PINs, ACMP, Pull-up/down.
2. LUTs.
3. DFFs, Delays/Counters, Pipe Delay.
4. POR output to matrix.
5. Output PIN corresponds to the internal logic.
6. LDOs.
Note: LDOs begin to operate above 2.5 V.
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Note: The maximum voltage applied to any PIN should not be higher than the VDD level. There are ESD Diodes between PIN →
V
DD and PIN → GND on each PIN. So, if the input signal applied to PIN is higher than VDD, then current will sink through the
diode to VDD. Exceeding VDD results in leakage current on the input PIN, and VDD will be pulled up, following the voltage on the
input PIN.There is no effect from input pin when input voltage is applied at the same time as VDD
.
17.3.2 Power-Down
VDD (V)
2 V
1.6 V
1.15 V
1 V
Time
Not guaranteed output state
Figure 61: Power-Down
During power down, macrocells in SLG46585 are powered off after VDD falling down below Power-Off Threshold. Please note
that during a slow rampdown, outputs can possibly switch state.
17.4 EXTERNAL RESET
The SLG46585 has an optional External Reset function on IO3. It allows to reset the chip while powered on.
IO3 must be configured as Digital Input registers [1071:1070] and function Reset must be enabled also, register [1307]:
0 - disabled, 1 - enabled. Unlike POR, External Reset affects only GPI, LUTs, DLY, RC OSC, DFFs, Latches, Pipe Delay, Matrix,
and GPO. While NVM remains its previous state, see Figure 62 to Figure 64.
Note that during External Reset the output pin's status will depend on the OE control circuits and current consumption is
determined by the design.
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External Reset
Level polarity: Non-Inverted
t
Level polarity: Inverted
VDD
t
t
POR_NVM
(reset for NVM)
t
t
t
t
t
t
t
NVM_ready_out
POR_GPI
(reset for input enable)
POR_LUT
(reset for LUT output)
POR_CORE
(reset for DLY/RCO/DFF
/LATCH/Pipe DLY
POR_OUT
(generate low to high to matrix)
POR_GPO
(reset for output enable)
Figure 62: External Reset Sequence (Level Sensitive)
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External Reset
(
rising edge detect)
t
t
VDD
POR_NVM
(reset for NVM)
t
NVM_ready_out
t
POR_GPI
(reset for input enable)
t
POR_LUT
(reset for LUT output)
t
POR_CORE
(reset for DLY/RCO/DFF
/LATCH/Pipe DLY
t
POR_OUT
(generate low to high
t
POR_GPO
(reset for output en-
t
Figure 63: External Reset Sequence (Rising Edge Detect)
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External Reset
(
falling edge detect)
t
t
VDD
POR_NVM
(reset for NVM)
t
NVM_ready_out
t
POR_GPI
(reset for input enable)
t
POR_LUT
(reset for LUT output)
t
POR_CORE
reset for DLY/RCO/DFF
/LATCH/Pipe DLY
t
POR_OUT
(generate low to high
t
POR_GPO
(reset for output en-
t
Figure 64: External Reset Sequence (Falling Edge Detect)
Table 89: External Reset Register Settings
Register Bit
Signal Function
Address
Register Definition
IO3 Reset level
polarity selection
[1304]
0: Non-inverted
1: Inverted
IO3 edge reset
enable
[1305]
[1306]
[1307]
0: Edge reset enable (controlled by register [1306])
1: High level reset
IO3 rising/falling
edge reset
0: Rising
1: Falling
IO3 reset function
0: Disable
1: Enable
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18 Asynchronous State Machine Macrocell
18.1 ASM MACROCELL OVERVIEW
The Asynchronous State Machine (ASM) macrocell is designed to allow the user to create state machines with between 2 to 8
states. The user has flexibility to define the available states, the available state transitions, and the input signals (a, b, c …) that
will cause transitions from one state to another state, as shown in Figure 65.
This macrocell has a total of 25 inputs, as shown in Figure 66, which come from the Connection Matrix outputs. Of these 25 inputs,
24 are user selectable for driving general state transitions, and 1 is for driving a state transition to an Initial/Reset state. Each of
the 24 inputs is level sensitive and active high, meaning that a high level input will drive the user selected transition from one state
to another. Additionally, 8 out of the 24 inputs (one per state) has an option to select whether the input is rising edge sensitive,
meaning that a rising level input signal will drive the user selected transition from one state to another. The fact that there are 24
inputs puts the upper bound of 24 possible state transitions total in the user defined state machine design. There is a nReset input
which will drive an immediate state transition to the user-defined Initial/Reset state when active, shown in red, in Figure 65.
There are a total of 8 outputs, which go to the Connections Matrix inputs, and from there can be routed to other internal macrocells
or pins. The 8 outputs are user defined for each of the possible 8 states. This information is held in the Connection Matrix Output
RAM.
In using this macrocell, the user must take into consideration the critical timing required on all input and output signals. The timing
waveforms and timing specifications for this macrocell are all measured relative to the input signals (which come into the macrocell
on the Connection Matrix outputs) and on the outputs from the macrocell (which are direct connections to Connection Matrix
inputs). The user must consider any delays from other logic and internal chip connections, including IO delays, to ensure that
signals are properly processed, and state transitions are deterministic.
The GPAK Designer development tools support user designs for the ASM macrocell at both the physical level and logic level.
Figure 65 is a representation of the user design at the logical level, and Figure 66 shows the physical resources inside the
macrocell. To best utilize this macrocell, the user must develop a logical representation of their desired state machine, as well as
a physical mapping of the input and outputs required for the desired functionality.
Off
a
d
c
Normal
Speed
Standby
Fault
b
e
f
g
h
High
Speed
Figure 65: Asynchronous State Machine State Transitions
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Connection Matrix
Output RAM
(8x8)
State Holding
LATCHES
State 0
State 0 In
State 1 In
State 2 In
State 3 In
State 4 In
State 5 In
State 6 In
State 0
State 1
State 2
State 3
State 4
State 5
State 6
State 7
Output Bits (8)
State 1
Output Bits (8)
State 2
Output Bits (8)
State 3
Output Bits (8)
from
Connection
Matrix
State
Transition
Signal
State 4
Output Bits (8)
Routing
State 5
Output Bits (8)
State 6
Output Bits (8)
State 7
Output Bits (8)
State 7 In
nReset
to Connection Matrix
Figure 66: Asynchronous State Machine
18.2 ASM INPUTS
The ASM macrocell has a total of 25 inputs which come from the Connection Matrix outputs. Of these 25 inputs, 24 are user
selectable for driving general state transitions, and 1 is for driving a state transition to an Initial/Reset state.
There are a total of 24 inputs to the ASM macrocell for general state transitions, highlighted in red in Figure 67. Each of these
inputs is level sensitive, and active high. A high level input will trigger a state transition. Additionally, 8 out of the 24 inputs (one
per state) has an option to select whether the input is rising edge sensitive, meaning that a rising level input signal will drive the
user selected transition from one state to another, shown in Figure 68.
These inputs are grouped so that each set of 3 inputs can drive a state transition going into a particular state. As an example,
there are three inputs that can drive a state transition to State 1. This sets an upper bound on the number of transitions that the
user can select going into a particular state to be 3, shown in Figure 69.
There is no limitation on the number of transitions that can be supported coming out of a particular state, the user can select to
have transitions going from a state to all other states, shown in Figure 70.
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The ASM macrocell also has a nReset input highlighted in blue in Figure 67. This input is level sensitive and active low. An
active signal on this input will drive an immediate state transition to the user-defined Initial/Reset state. The user can choose
which state within the ASM Editor inside GPAK Designer is the initial state.
Connection Matrix
Output RAM
(8x8)
State Holding
Latches
State 0
State 0 In
State 1 In
State 2 In
State 3 In
State 4 In
State 5 In
State 6 In
State 0
State 1
State 2
State 3
State 4
State 5
State 6
State 7
Output Bits (8)
State 1
Output Bits (8)
State 2
Output Bits (8)
State 3
Output Bits (8)
from
Connection
Matrix
State
Transition
Signal
State 4
Output Bits (8)
Routing
State 5
Output Bits (8)
State 6
Output Bits (8)
State 7
Output Bits (8)
State 7 In
nReset
to Connection Matrix
Figure 67: Asynchronous State Machine Inputs
State X In
Rising Edge
Detection
Figure 68: Rising Edge State Transition Selection (for Each State X)
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State 1
State 0
State 3
State 2
Figure 69: Maximum 3 State Transitions into Given State
State 1
State 7
State 2
State 0
State 6
State 3
State5
State 4
Figure 70: Maximum 7 State Transitions out of a Given State
18.3 ASM OUTPUTS
There are a total of 8 outputs from the ASM macrocell, which go to the Connections Matrix inputs, and from there can be routed
to other internal macrocells or pins. The 8 outputs are user defined for each of the possible 8 states, this information is held in
the Connection Matrix Output RAM, shown in Figure 71. The Connection Matrix Output RAM has a total of 64 bits, arranged as
8 bits per state. The values loaded in each of the 8 bits define the signal level on each of the 8 ASM macrocell outputs.
The ASM Editor inside the GPAK Designer software allows the user to make their selections for the value of each bit in the
Connection Matrix Output RAM, which selects the level of the macrocell outputs based on the current state of the ASM macrocell,
as shown in Figure 66.
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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Connection Matrix
Output RAM
(8x8)
State Holding
Latches
State 0
State 0 In
State 1 In
State 2 In
State 3 In
State 4 In
State 5 In
State 6 In
State 0
State 1
State 2
State 3
State 4
State 5
State 6
State 7
Output Bits (8)
State 1
Output Bits (8)
State 2
Output Bits (8)
State 3
Output Bits (8)
from
Connection
Matrix
State
Transition
Signal
State 4
Output Bits (8)
Routing
State 5
Output Bits (8)
State 6
Output Bits (8)
State 7
Output Bits (8)
State 7 In
nReset
to Connection Matrix
Figure 71: Connection Matrix Output RAM
Table 90: ASM Editor - Connection Matrix Output RAM
RAM
Connection Matrix Output RAM
State name
State 0
State 1
State 2
State 3
State 4
State 5
State 6
State 7
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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18.4 BASIC ASM TIMING
The basic state transition timing from input on Matrix Connection output to output on Matrix Connection input is shown in
Figure 72 and Figure 73. The time from a valid input signal to the time that there is a valid change of state and valid signals
being available on the state outputs is State Machine Output Delay Time (Tst_out_delay). The minimum and maximum values of
Tst_out_delay define the differential timing between the shortest state transition (input on matrix output and output on matrix input)
and the longest state transition (input on matrix output and output on matrix input).
a
State 0
State 1
Figure 72: State Transition
Input
Signal (a)
Tst_out_delay
State
Outputs
State 0
State 1
Figure 73: State Transition Timing
18.5 ASYNCHRONOUS STATE MACHINES VS. SYNCHRONOUS STATE MACHINES
It is important to note that this macrocell is designed for asynchronous operation, which means the following:
1. No clock source is needed, it reacts only to input signals.
2. The input signals do not have to be synchronized to each other, the macrocell will react to the earliest valid signal for state
transition.
3. This macrocell does not have traditional set-up and hold time specifications which are related to incoming clock, as this
macrocell has no clock source.
4. The macrocell only consumes power while in state transition.
18.6 ASM POWER CONSIDERATION
A benefit of the asynchronous nature of this macrocell is that it will consume power only during state transitions. Shown in
Figure 72 and Figure 74, the current consumption of the macrocell will be a fraction of a µA between state transitions, and will
rise only during state transitions. See Section 3.4 to find average current during state transitions.
a
State 0
State 1
Figure 74: State Transition
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Input
Signal (a)
Tst_out_delay
State
Outputs
State 0
State 1
Average Active ASM Power
ASM
Power
Consumption
Sub µA Inactive ASM Power Consumption
Figure 75: State Transition Timing and Power Consumption
18.7 ASM LOGICAL VS. PHYSICAL DESIGN
A successful design with the ASM macrocell must include both the logic level design as well as the physical level design. The
GPAK Designer development software support user designs for the ASM macrocell at both the logic level and physical level. The
logic level design of the user defined state machine takes place inside the ASM Editor. In the ASM Editor, the user can select and
name states, define and name allowed state transitions, define the Initial/Reset state, and define the output values for the 8 outputs
in the Output RAM Matrix. The physical level design takes place in the general GPAK Designer window, and here the user makes
connections for the sources for ASM input signals, as well as making connections for destinations for ASM output signals.
18.8 ASM SPECIAL CASE TIMING CONSIDERATIONS
18.8.1 State Transition Pulse Input Timing
All inputs to the ASM macrocell are level sensitive. If the input to the state machine macrocell for a state transition is a pulse,
there is a minimum pulse width on the input to the state machine macrocell (as measured at the matrix input to the macrocell)
which is guaranteed to result in a state transition shown in Figure 76 and Figure 77. This pulse width is defined by the State
Machine Input Pulse Acceptance Time (Tst_pulse). If a pulse width that is shorter than Tst_pulse is input to the state machine
macrocell, it is indeterminate whether the state transition will happen or not. If a pulse that is rejected (invalid due to the pulse
width being narrower than the guaranteed minimum of Tst_pulse), this will not stop a valid pulse on another state transition input
that does meet minimum pulse width.
a
State 0
State 1
Figure 76: State Transition
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Input
Signal (a)
Tst_pulse
Tst_pulse
State
Outputs
State 0
State 1
Tst_out_delay
Figure 77: State Transition Pulse Input Timing
18.8.2 ASM State Transition Competing Input Timing
There will be situations where two input signals can be valid inputs that will drive two different state transitions from a given state.
In that sense, the two signals are “competing” (signals a and b in Figure 78), and the signal that arrives sooner should drive the
state transition that will “win”, or drive the state transition. If one signal arrives Tst_comp before the other one, it is guaranteed to
win, and the state transition that it codes for will be taken, as shown in Figure 79. If the two signals arrive within Tst_comp of each
other, it will be indeterminate which state transition will win, but one of the transitions will take place as long as the winning signal
satisfies the pulse width criteria described in the paragraph above, as shown in Figure 80.
a
b
State 0
State 1
State 2
Figure 78: State Transition - Competing Inputs
Input
Signal (a)
Tst_comp
Input
Signal (b)
Tst_out_delay
State
Outputs
State 0
State 1 or State 2
Figure 79: State Transition Timing - Competing Inputs Indeterminate
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Input
Signal (a)
Tst_comp
Input
Signal (b)
Tst_out_delay
State
State 0
State 1
Outputs
Figure 80: State Transition Timing - Competing Inputs Determinable
18.8.3 ASM State Transition Sequential Timing
It is possible to have a valid input signal for a transition out from a particular state be active before the state is active. If this is the
case, the macrocell will only stay in that particular state for Tst_sequential_delay time before making the transition to the next state.
An example of this sequential behavior is shown in Figure 81 and the associated timing is shown in Figure 82.
a
b
State 0
State 1
State 2
Figure 81: State Transition - Sequential
Input
Signal (a)
Input
Signal (b)
Tst_out_delay
Tst_out_delay
State
Outputs
State 0
State 1
State 2
Figure 82: State Transition - Sequential Timing
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18.8.4 State Transition Closed Cycling
It is possible to have a closed cycle of state transitions that will run continuously if there if there are valid inputs that are active at
the same time. The rate at which the state transitions will take place is determined by Tst_out_delay. The example shown in Figure 83
involves cycling between two states, but any number of two to eight states can be included in state transition closed cycling of
this nature. Figure 84 shows the associated timing for closed cycling.
a
State 0
State 1
b
Figure 83: State Transition - Closed Cycling
Input
Signal (a)
Input
Signal (b)
Tst_out_delay
Tst_out_delay
Tst_out_delay
State
Outputs
State 0
State 1
State 0
State 1
Figure 84: State Transition - Closed Cycling Timing
18.8.5 ASM State Transition Using Edge Detector Option
It is possible to use a rising edge detector option for state transitions. In this case, state transition happens on low to high signal
transition as shown in Figure 85 and Figure 86.
a
a
State 0
State 1
State 2
rising edge
rising edge
Figure 85: State Transition - Rising Edge Transition
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Input
Signal (a)
Tst_out_delay
Tst_out_delay
State
Outputs
State 0
State 1
State 2
Figure 86: State Transition - Rising Edge Transition Timing
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2
19 I C Serial Communications Macrocell
19.1 I2C SERIAL COMMUNICATIONS MACROCELL OVERVIEW
In the standard use case for the GreenPAK devices, the configuration choices made by the user are stored as bit settings in the
Non-Volatile Memory (NVM). This information is transferred at startup time to volatile RAM registers that enable the configuration
of the macrocells. Other RAM registers in the device are responsible for setting the connections in the Connection Matrix to route
signals in the manner most appropriate for the user’s application.
The I2C Serial Communications Macrocell in this device allows an I2C bus Master to read and write this information via a serial
channel directly to the RAM registers, allowing the remote re-configuration of macrocells, and remote changes to signal chains
within the device.
An I2C bus Master is also able read and write other register bits that are not associated with NVM memory. As an example, the
input lines to the Connection Matrix can be read as digital register bits. These are the signal outputs of each of the macrocells in
the device, giving an I2C bus Master the capability to remotely read the current value of any macrocell.
The SLG46585 supports both 400 kHz (Fast-mode I2C bus) and 1 MHz (Fast-mode Plus I2C bus) I2C bus interfaces, which is
selected by register [1868].
The user has the flexibility to control read access and write access via registers bits register [1832] and register [1871]. See
Section for more details on I2C read/write memory protection.
Note: GreenPAK I2C is fully compatible with standard I2C protocol.
19.2 I2C SERIAL COMMUNICATIONS DEVICE ADDRESSING
Each command to the I2C Serial Communications macrocell begins with a Control Byte. The bits inside this Control Byte are
shown in Figure 87. After the Start bit, the first four bits are a control code, which can be set by the user in registers [1867:1864].
This gives the user flexibility on the chip level addressing of this device and other devices on the same I2C bus. The Block Address
is the next three bits (A10,A9, A8), which will define the most significant bits in the addressing of the data to be read or written by
the command. The last bit in the Control Byte is the R/W bit, which selects whether a read command or write command is
requested, with a “1” selecting for a Read command, and a “0” selecting for a Write command. This Control Byte will be followed
by an Acknowledge bit (ACK), which is sent by this device to indicate successful communication of the Control Byte data.
In the I2C-bus specification and user manual, there are two groups of eight addresses (0000 xxx and 1111 xxx) that are reserved
for the special functions, such as a system General Call address. If the user of this device choses to set the Control Code to either
“1111” or “0000” in a system with other slave device, please consult the I2C-bus specification and user manual to understand the
addressing and implementation of these special functions, to ensure reliable operation.
In the read and write command address structure, there are a total of 11 bits of addressing, each pointing to a unique byte of
information, resulting in a total address space of 2K bytes. Of this 2K byte address space, the valid addresses accessible to the
I2C Macrocell on the SLG46585 are in the range from 0 (0x00) to 255 (0xFF). The MSB address bits (A10, A9, and A8) will be
“0” for all commands to the SLG46585.
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With the exception of the Current Address Read command, all commands will have the Control Byte followed by the Word
Address. Figure 87 shows this basic command structure.
Start
bit
Acknowledge
bit
Control Byte
Word Address
A
10
A
9
A
8
A
7
A
0
S
X
X
X
X
R/W ACK
Control
Code
Block
Address
Not used, se
t to 0
Read/Write bit
(1 = Read, 0 = Write)
Figure 87: Basic Command Structure
19.3 I2C SERIAL GENERAL TIMING
General timing characteristics for the I2C Serial Communications macrocell are shown in Figure 88. Timing specifications can be
found in Section 3.4.
tHIGH
tF
tR
tLOW
SCL
tSU STA
tHD DAT
tHD STA
tSU DAT
tSU STO
SDA IN
tBUF
tAA
tDH
SDA OUT
Figure 88: I2C General Timing Characteristics
19.4 I2C SERIAL COMMUNICATIONS COMMANDS
19.4.1 Byte Write Command
Following the Start condition from the Master, the Control Code [4 bits], the Block Address [3 bits], and the R/W bit (set to “0”),
are placed onto the I2C bus by the Master. After the SLG46585 sends an Acknowledge bit (ACK), the next byte transmitted by
the Master is the Word Address. The Block Address (A10, A9, A8), combined with the Word Address (A7 through A0), together
set the internal address pointer in the SLG46585, where the data byte is to be written. After the SLG46585 sends another
Acknowledge bit, the Master will transmit the data byte to be written into the addressed memory location. The SLG46585 again
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provides an Acknowledge bit and then the Master generates a Stop condition. The internal write cycle for the data will take place
at the time that the SLG46585 generates the Acknowledge bit.
Acknowledge
bit
Acknowledge
bit
Start
bit
Acknowledge
bit
Bus Activity
Control Byte
Word Address
Data
A
10
A
9
A
8
A
7
A
0
D
7
D
0
S
X
X
X
X
W
ACK
ACK
ACK
SDA LINE
P
Control
Code
Block
Address
Stop
bit
Not used, set to
0
R/W bit = 0
Figure 89: Byte Write Command, R/W = 0
19.4.2 Sequential Write Command
The write Control Byte, Word Address and the first data byte are transmitted to the SLG46585 in the same way as in a Byte Write
command. However, instead of generating a Stop condition, the Master continues to transmit data bytes to the SLG46585. Each
subsequent data byte will increment the internal address counter, and will be written into the next higher byte in the command
addressing. As in the case of the Byte Write command, the internal write cycle will take place at the time that the SLG46585
generates the Acknowledge bit.
Acknowledge
Acknowledge
bit
Start
bit
bit
Bus Activity
Data (n + 1)
Data (n + x)
Control Byte
Word Address (n)
Data (n)
A
10
A
8
A
9
ACK
ACK
P
SDA LINE
S
X
X
X
X
W
ACK
ACK
ACK
Control
Code
Block
Address
Stop
bit
Not used, set to
0
R/W bit = 0
Figure 90: Sequential Write Command, R/W = 0
19.4.3 Current Address Read Command
The Current Address Read Command reads from the current pointer address location. The address pointer is incremented at the
first STOP bit following any write control byte. For example, if a Write or Random Read (which contains a write control byte) writes
or reads data up to address n, the address pointer would get incremented to n + 1 upon the STOP of that command. Subsequently,
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a Current Address Read that follows would start reading data at n + 1. The Current Address Read Command contains the Control
Byte sent by the Master, with the R/W bit = “1”. The SLG46585 will issue an Acknowledge bit, and then transmit eight data bits
for the requested byte. The Master will not issue an Acknowledge bit, and follow immediately with a Stop condition.
Start
bit
Acknowledge
bit
Stop
bit
Bus Activity
Control Byte
Data (n+1)
A
10
A
9
A
8
S
X
X
X
X
R
ACK
SDA LINE
P
Control
Code
Block
Address
No Ack
bit
Not used, set to
0
R/W bit = 1
Figure 91: Current Address Read Command, R/W = 1
19.4.4 Random Read Command
The Random Read command starts with a Control Byte (with R/W bit set to “0”, indicating a write command) and Word Address
to set the internal byte address, followed by a Start bit, and then the Control Byte for the read (exactly the same as the Byte
Write command). The Start bit in the middle of the command will halt the decoding of a Write command, but will set the internal
address counter in preparation for the second half of the command. After the Start bit, the Master issues a second control byte
with the R/W bit set to “1”, after which the SLG46585 issues an Acknowledge bit, followed by the requested eight data bits.
.
Acknowledge
Stop
bit
Start
bit
bit
Bus Activity
Data (n)
Control Byte
Word Address (n)
Control Byte
A
10
A
9
A
8
A
10
A
9
A
8
R
ACK
P
S
ACK
X
X
X
X
SDA LINE
S
X
X
X
X
W
ACK
Control
Code
Block
Address
Control
Code
R/W bit = 1
No Ack
bit
Not used, se
t to 0
R/W bit = 0
Figure 92: Random Read Command
19.4.5 Sequential Read Command
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The Sequential Read command is initiated in the same way as a Current Address Read or Random Read command, except that
once the SLG46585 transmits the first data byte, the Bus Master issues an Acknowledge bit as opposed to a Stop condition in a
random read. The Master can continue reading sequential bytes of data, and will terminate the command with a Stop condition.
Acknowledge
Start
bit
bit
Bus Activity
Data (n + 2)
Data (n + x)
Control Byte
Data (n)
Data (n+1)
A
8
A
10
A
9
ACK
P
SDA LINE
S
X
X
X
X
R
ACK
ACK
ACK
Control
Code
Block
Address
Stop
bit
Not used, set
to 0
No Ack
bit
R/W bit = 1
Figure 93: Sequential Read Command
19.4.6 I2C Serial Command Address Space
In the read and write command address structure, there are a total of 11 bits of addressing, each pointing to a unique byte of
information, resulting in a total address space of 2K bytes. Of this 2K byte address space, the valid addresses accessible to the
I2C Macrocell on the SLG46585 are in the range from 0 (0x00) to 255 (0xFF). The MSB address bits (A10, A9, and A8) will be
“0” for all commands to the SLG46585.
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19.5 I2C SERIAL COMMAND REGISTER MAP
There are seven read/write protect modes for the design sequence from being corrupted or copied. See Table 91 for details.
Table 91: Read/Write Protection Options
Protection Modes Configuration
Locked Locked for
Locked
Unlocked for read
bits
Locked
for write
bits
Locked
for write
all bits
for read
and write andwriteall
read bits
Data
Output
From
Register
Address
(HEX)
bits
bits
Configurations
Register
[1832]=0
Register
[1871]=0
Register
[1870]=0
Register
[1832]=1
Register
[1871]=0
Register
[1870]=0
Register
[1832]=0
Register
[1871]=1
Register
[1870]=0
Register
[1832]=0
Register
[1871]=x
Register
[1870]=1
Register
[1832]=1
Register
[1871]=1
Register
[1870]=0
Register
[1832]=1
Register
[1871]=x
Register
[1870]=1
I2C Serial Reset
Command
R/W
R
R/W
R
R/W
R
R
R
R
R/W
R
R
R
R
Memory
Memory
Macrocell
CF,b’6
CF,b’7
F4
Outputs Latching During
I2C Write
Connection Matrix
Virtual Inputs
R/W
R/W
R/W
R/W
Configuration Bits for All
Macrocells
(IO Pins, Combination
Function Macrocells,
ASM, etc.)
R/W
R/W
W
W
R
R
R
R
-
-
-
-
Memory
Memory
80-BF
Macrocells Inputs
Configuration
(Connection Matrix
00-67
Outputs)
6E, D0-E3;
CF,b’0-b’2;
C6-CE;
C0-C4;
75-7F
LDO settings, RAM,
ACMP settings, DLY/
CNT control data, RTC
settings
R/W
R
R/W
R
R/W
R
R
R
R/W
R
R
R
Macrocells Output
Values (Connection
Matrix Inputs)
F0-F3;
F5-F7
Macrocell
Counter Current Value
ASM Current State
R
R
R
R
R
R
R
R
R
R
R
R
Macrocell
Macrocell
70-71
EF
Silicon Identification
Service Bits
R
R
R
R
R
R
Memory
Memory
E8
Pattern ID0/1
I2C Control Code
R/W
R
R/W
R
R/W
R
R
R
R/W
R
R
R
E6, E4
Memory E9,b’0-b3;
Protection Read
Configuration (Register
[1832])
R
R
R
R
R
R
R
R
R
R
R
R
Memory E5,b’0
Protection Write
Configuration (Register
[1870],
Memory E9,b’6-b’7
Register [1871)
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R/W
W
R
Allow Read and Write Data
Allow Write Data Only
Allow Read Data Only
-
The Data is protected for Read and Write
It is possible to read some data from macrocells, such as counter current value, ASM current state, connection matrix, and
connection matrix virtual inputs. The I2C write does not have any impact on data in case data comes from macrocell output, except
Connection Matrix Virtual Inputs. The silicon identification service bits allow identifying silicon family, its revision, and others.
Note: If register [1663] = 1, all outputs are latched while inputs and internal macrocells retain their status during I2C write.
Note: Any write commands that come to the device via I2C that are not blocked, based on the protection bits, will change the
contents of the RAM register bits that mirror the NVM bits. These write commands will not change the NVM bits themselves, and
a POR event will restore the register bits to original programmed contents of the NVM.
See Section 22 for detailed information on all registers.
19.5.1 I2C Serial Reset Command
If I2C serial communication is established with the device, it is possible to reset the device to initial power up conditions, including
configuration of all macrocells, and all connections provided by the Connection Matrix. This is implemented by setting
register [1662] I2C reset bit to “1”, which causes the device to re-enable the Power-On Reset (POR) sequence, including the
reload of all register data from NVM. During the POR sequence, the outputs of the device will be in tri-state. After the reset has
taken place, the contents of register [1662] will be set to “0” automatically. The timing diagram shown in Figure 94 illustrates the
sequence of events for this reset function.
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Acknowledge
bit
Acknowledge
bit
Start
bit
Acknowledge
bit
Bus Activity
Control Byte
Word Address
Data
A
10
A
9
A
8
A
7
A
0
D
7
D
0
S
X
X
X
X
W
ACK
ACK
ACK
SDA LINE
P
Internal Reset bit
Control
Code
Block
Address
Stop
bit
Not used, set to
0
Write bit
by I2C Stop Signal
Reset-bit register output
Internal POR
reloading NVM into Data register
Reset-bit register (register [1662]) is cleared by reloading NVM into Data register
1) I2C write with register [1622] = 1 (I2C reset bit with reloading NVM into Data register)
2) POR go to LOW and reloading NVM into Data register start after “STOP” of I2C
3) POR go to HIGH after reloading NVM into Data register
Figure 94: Reset Command Timing
19.5.2 Reading Counter Data via I2C
The current count value in the RTC counter and two counters in the device can be read via I2C. The counters that have this
additional functionality are 8-bit counters CNT2 and CNT4.
19.5.3 User RAM and OTP Memory Array
There are eight bytes of RAM memory that can be read and written remotely by I2C commands. The initial contents of this
memory space can be selected by the user, and this information will be transferred from OTP memory to the RAM memory
space during the power-up sequence. The lowest order byte in this array (User Configurable RAM/OTP Byte 0) is located at I2C
address 0xD8, and the highest order byte in this array is located at I2C address 0xDF.
Table 92: RAM Array Table
I2C Address
(hex)
Highest Bit
Address
Lowest Bit
Address
Memory Byte
D8
D9
DA
DB
DC
DD
DE
DF
1735
1743
1751
1759
1767
1775
1783
1791
1728
1736
1744
1752
1760
1768
1776
1784
User Configurable RAM/OTP Byte 0
User Configurable RAM/OTP Byte 1
User Configurable RAM/OTP Byte 2
User Configurable RAM/OTP Byte 3
User Configurable RAM/OTP Byte 4
User Configurable RAM/OTP Byte 5
User Configurable RAM/OTP Byte 6
User Configurable RAM/OTP Byte 7
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
20 Low Dropout Regulators
20.1 LDO REGULATOR DESCRIPTION
The SLG46585 comes with four low dropout regulators each rated at 150 mA. Each LDO regulator has 3 modes which are: HP
MODE is the standard active mode supporting full 150 mA output; LP MODE is a low power mode with maximum 100 µA; and
finally Power Switch Mode in which the LDO regulator ceases to regulate and the Regulator MOSFET is turned on as a power
switch, passing the voltage applied to VIN directly to VOUT.
The LDO regulators are paired together with LDO0 and LDO1 sharing the same VIN called LDO0/1 VIN, likewise LDO2 and
LDO3 share the same VIN called LDO2/3 VIN.
P-Ch MOSFET
LDO0 VOUT
LDO0/1 VIN
Vref Selection
V1 Value
300 Ω
Dis_en
register [1455]
registers
Vref
[1599:1595]
-
Vref Selection
V2 Value
registers
[1799:1795]
+
pd
Connection Matrix
Input [49]
LDO0 nFault
PWR Switch Mode
Enable register
[1452]
LDO On/Off
pd
From Connection Matrix Out [97]
0: V1 value
1: V2 value or PWR Switch
Selection Enable register [1793]
Start-Up Ramping Slope Selection
1.25 V/ms, 2.5 V/ms, 10 V/ms or 20 V/ms
register [1592], register [1453]
LDO0 Overcurrent & Short-circuit
Detection Enable register [1454]
From Connection Matrix Output [92]
LDO LP Mode Enable register [1794]
From Connection Matrix Out [93]
LDO ON/OFF
0: LDO Off
1: LDO On
LDO0 _en register [1792]
UVLO_0 Out (ACMP0 Out)
UVLO_0_HW_EN register [1585]
Temp Sensor Out (ACMP2 Out)
Temp_Sensor_HW_EN register [1656]
Figure 95: LDO0 Regulator Block Diagram
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
P-Ch MOSFET
LDO1 VOUT
LDO0/1 VIN
Dis_en
register
[1451]
Vref Selection
V1 Value
300 Ω
registers
Vref
[1607:1603]
-
Vref Selection
V2 Value
registers
[1807:1803]
+
pd
Connection Matrix
Input [50]
LDO1 nFault
PWR Switch Mode
Enable register
[1448]
LDO On/Off
From Connection Matrix Out [98]
0: V1 value
1: V2 value or PWR Switch
pd
Selection Enable register [1801]
Start-Up Ramping Slope Selection
1.25 V/ms, 2.5 V/ms, 10 V/ms or 20 V/ms
register[1600], register[1449]
LDO1 Overcurrent & Short-circuit
Detection Enable register [1450]
From Connection Matrix Output [92]
LDO LP Mode Enable register [1794]
From Connection Matrix Out [94]
LDO ON/OFF
0: LDO Off
1: LDO On
LDO1 _en register [1800]
UVLO_0 Out (ACMP0 Out)
UVLO_0_HW_EN register [1585]
Temp Sensor Out (ACMP2 Out)
Temp_Sensor_HW_EN register [1656]
Figure 96: LDO1 Regulator Block Diagram
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
P-Ch MOSFET
LDO2 VOUT
LDO2/3 VIN
Vref Selection
V1 Value
Dis_en
register
[1463]
300 Ω
registers
[1615:1611]
Vref
-
Vref Selection
V2 Value
registers
[1815:1811]
+
pd
Connection Matrix
Input [51]
LDO2 nFault
PWR Switch Mode
Enable register
[1460]
LDO On/Off
From Connection Matrix Out [99]
0: V1 value
1: V2 value or PWR Switch
pd
Selection Enable register [1809]
Start-Up Ramping Slope Selection
1.25 V/ms, 2.5 V/ms, 10 V/ms or 20 V/ms
register [1608], register [1461]
LDO2 Overcurrent & Short-circuit
Detection Enable register [1462]
From Connection Matrix Output [92]
LDO LP Mode Enable register [1794]
From Connection Matrix Out [95]
LDO ON/OFF
0: LDO Off
1: LDO On
LDO2 _en register [1808]
UVLO_1 Out (ACMP1 Out)
UVLO_1_HW_EN register [1584]
Temp Sensor Out (ACMP2 Out)
Temp_Sensor_HW_EN register [1656]
Figure 97: LDO2 Regulator Block Diagram
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
P-Ch MOSFET
LDO3 VOUT
LDO2/3 VIN
Vref Selection
V1 Value
Dis_en
register
[1459]
300 Ω
registers
Vref
[1623:1619]
-
Vref Selection
V2 Value
+
pd
Connection Matrix
Input [52]
registers
[1823:1819]
LDO3 nFault
PWR Switch Mode
Enable register
[1456]
LDO On/Off
pd
From Connection Matrix Out [100]
0: V1 value
1: V2 value or PWR Switch
Selection Enable register [1817]
Start-Up Ramping Slope Selection
1.25 V/ms, 2.5 V/ms, 10 V/ms or 20 V/ms
register [1616], register [1457]
LDO3 Overcurrent & Short-circuit
Detection Enable register [1458]
From Connection Matrix Output [92]
LDO LP Mode Enable register [1794]
From Connection Matrix Out [96]
LDO ON/OFF
0: LDO Off
1: LDO On
LDO3 _en register [1816]
UVLO_1 Out (ACMP1 Out)
UVLO_1_HW_EN register [1584]
Temp Sensor Out (ACMP2 Out)
Temp_Sensor_HW_EN register [1656]
Figure 98: LDO3 Regulator Block Diagram
20.1.1 Voltage Selection
Each LDO has access to 32 voltage levels derived from a bandgap voltage reference.
It is possible to select two different output voltage levels (V1 and V2) per LDO. The voltage levels can be changed through the
Connection Matrix, after V1/V2 selection is enabled through the register bit. It is also possible to change the LDO output voltage
level through the I2C by writing the corresponding LDO output voltage selection number according to Table 93.
Table 93: LDO Output Voltage Selection
Selection #
LDO VOUT (V)
0.90
LDO Min VIN (V)
Min VDD (V)
2.50
PW SEL
000
0
1
2
3
4
5
2.50
2.50
2.50
2.50
2.50
2.50
1.00
2.50
000
1.05
2.50
000
1.10
2.50
000
1.20
2.50
000
1.25
2.50
000
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 93: LDO Output Voltage Selection (Continued)
Selection #
LDO VOUT (V)
1.35
1.50
1.67
1.80
1.90
2.00
2.10
2.20
2.30
2.40
2.50
2.60
2.70
2.80
2.85
2.90
3.00
3.10
3.20
3.30
3.40
3.50
3.60
4.00
4.10
4.20
LDO Min VIN (V)
2.50
Min VDD (V)
2.50
2.50
2.50
2.50
2.50
2.50
2.80
2.80
2.80
2.80
2.80
3.00
3.00
3.30
3.30
3.30
3.30
3.60
3.60
3.60
3.90
3.90
3.90
4.40
4.50
4.50
PW SEL
000
000
000
000
000
000
001
001
001
001
001
010
010
011
011
011
011
100
100
100
101
101
101
110
111
6
7
2.50
8
2.50
9
2.50
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
2.50
2.50
2.50
2.50
2.60
2.70
2.80
2.90
3.00
3.10
3.15
3.20
3.30
3.40
3.50
3.60
3.70
3.80
3.90
4.30
4.40
4.50
111
Note 1 The combination of VIN, VDD, and VOUT must satisfy the rule: VDD ≥ VIN ≥ VOUT + 0.3 V.
Note 2 VIN and VDD should not exceed 5.5 V.
20.1.2 LDO HP Mode Operation
HP Mode is the standard active LDO mode with a 150 mA per LDO output loading capability. VDD ≥ 2.5 V.
A high level signal should be applied to Connection Matrix Outputs [93], [94], [95], and [96] together with the register enable bits
[1792], [1800], [1808], and [1816] to enable LDO0, LDO1, LDO2, and LDO3, respectively. The LDO requires a wait time to enable
analog circuitry before the LDO output starts to rise with the desired ramping slope selected through the register bits.
20.1.3 LDO LP Mode Operation
It is possible to enable ultra-low power LP Mode in which max output loading is 100 µA and quiescent current consumption is
~2 µA per LDO (without load). LP Mode can be enabled through Connection Matrix Output [92] together with the register enable
bit <1794> and have an impact for all LDOs enabled in the SLG46585 chip.
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
20.1.4 Power Switch Mode Operation
Each LDO has an additional option to operate in power switch mode. In this case, all LDO related circuitry will be disabled. The
quiescent current consumption is ~1 µA in power switch mode.
The power switch option is available in each LDO and can be used instead of the VOUT2 output voltage level selected by the
following register bits: register [1452] for LDO0, register [1448] for LDO1, register [1460] for LDO2, and register [1456] for LDO3.
The Power Switch Mode can be selected by applying a high-level signal to the Connection Matrix Output [97], [98], [99], and [100]
for LDO0, LDO1, LDO2, and LDO3 respectively.
20.2 OVER-CURRENT LIMIT AND SHORT-CIRCUIT DETECTION
Each LDO has the option to enable OCL (Over-Current Limit, if the output current rises above 210 mA) and SCD (Short-Circuit
Detection, if output voltage drops below 0.5 V with the current limited by 20 mA).
These options are available for the LDO in HP Mode only. The nFAULT signal per LDO will generate a low-level signal to the
connection matrix input when the over-current limit is detected.
20.3 LDO EFFICIENCY
The efficiency of LDO regulators is limited by the quiescent current and input/output voltages as follows:
IOUT × VOUT
--------------------------------------------
(IOUT + IQ) × VIN
ηEF
=
× 100
where:
ηEF = LDO efficiency, in percents (%)
IOUT = Output current, in Amps (A)
VOUT = Output voltage, in Volts (V)
IQ = Quiescent current, in Amps (A)
VIN = Input voltage, in Volts (V)
To have a high efficiency, drop out voltage and quiescent current must be minimized. In addition, the voltage difference between
input and output must be minimized, since the power dissipation of LDO regulators accounts for efficiency:
PD = VDO × IOUT
where:
PD = Power Dissipation, in Watts (W)
V
DO = Drop out voltage, in Volts (V)
IOUT = Output current, in Amps (A)
The Input/Output voltage difference is an intrinsic factor in determining the efficiency, regardless of the load conditions.
20.4 LDO THERMAL CONSIDERATIONS
The thermal limitations must be taken into consideration during regulator design. The SLG46585 is rated at 0.6 W of power
dissipation at 85 °C ambient and 0.8 W of power dissipation at 70 °C ambient. If a regulator is connected to 5.0 V and then is
programmed to output 1.8 V, the power dissipation at 150 mA is 0.48 W or almost the entire thermal budget of the SLG46585. In
this case we recommend putting an external resistor between the application’s power source (battery or wall power) and the
SLG46585’s LDO VIN to help distribute the thermal load. A 10 Ω, ¼ watt resistor would cut the IC thermal dissipation about in
half without impacting overall performance. However, because the LDO VIN voltage is shared between two LDOs the resistor
should be properly selected for the higher of the desired LDO output voltages.
If it is possible to use the temperature sensor together with ACMP2 to automatically shut down all LDOs if the die temperature
rises to a predetermined threshold level. The LDOs will automatically restart when the chip has cooled down within the hysteresis
range forACMP2. Other temperature shut off levels may be achieved by incorporating the temperature sensor intoACMP3’s input.
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
20.5 SOFT START FUNCTION (SS)
Table 94 to Table 97 show the bit settings and slew rate selection options for each LDO.
Table 94: LDO0 Ramp Rate Selection Table
Parameter
SS0
Description
SS Slew Rate 0
SS Slew Rate 1
SS Slew Rate 2
SS Slew Rate 3
Typical Value
10 V/ms
register [1453]
register [1592]
0
0
1
1
0
1
0
1
SS1
20 V/ms
SS2
1.25 V/ms
2.50 V/ms
SS3
Table 95: LDO1 Ramp Rate Selection Table
Parameter
SS0
Description
SS Slew Rate 0
SS Slew Rate 1
SS Slew Rate 2
SS Slew Rate 3
Typical Value
10 V/ms
register [1449]
register [1600]
0
0
1
1
0
1
0
1
SS1
20 V/ms
SS2
1.25 V/ms
2.50 V/ms
SS3
Table 96: LDO2 Ramp Rate Selection Table
Parameter
SS0
Description
SS Slew Rate 0
SS Slew Rate 1
SS Slew Rate 2
SS Slew Rate 3
Typical Value
10 V/ms
register [1461]
register [1608]
0
0
1
1
0
1
0
1
SS1
20 V/ms
SS2
1.25 V/ms
2.50 V/ms
SS3
Table 97: LDO3 Ramp Rate Selection Table
Parameter
SS0
Description
SS Slew Rate 0
SS Slew Rate 1
SS Slew Rate 2
SS Slew Rate 3
Typical Value
10 V/ms
register [1457]
register [1616]
0
0
1
1
0
1
0
1
SS1
20 V/ms
SS2
1.25 V/ms
2.50 V/ms
SS3
20.6 ACMPS: UNDER VOLTAGE LOCKOUT CAPABILITY, POWER GOOD
LDO0/1 VIN and LDO2/3 VIN are sensed by ACMP0 and ACMP1 respectively as one of their input options. The sense line can
be divided by 2, 3, or 4 for the common mode voltage input limitation of ACMP0 and ACMP1. ACMP0 and ACMP1 can be set to
the customers desired under voltage lockout (UVLO) level. The undervoltage lockout can be set by either hardware connection
to control the LDO or through the Connection Matrix. The UVLO_0 hardware connection to the LDO can be enabled by
register [1585] for LDO0 and LDO1, and UVLO_1 by register [1584] for LDO2 and LDO3.
Note: ACMP0 needs to be properly configured to use UVLO_0 for LDO0 and LDO1. ACMP1 needs to be properly configured to
use UVLO_1 for LDO2 and LDO3.
A lockout level below 2.5 V is not useful as the lowest acceptable power supply voltage is 2.5 V.
ACMP3 has a selectable input from the output of LDO0 or 2 for the purpose of a power good.
The ACMPs connection to VDD may be reused for the purpose stated above.
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
20.7 REGULATOR STABILITY CONSIDERATIONS
The regulators are only stable in HP MODE when a 2 µF (min) capacitor or greater is attached to each LDOs VOUT. The
recommended capacitor is a 2 µF (min) X5R capacitor rated for 6 V or greater. The X5R capacitor varies with temperature, DC
bias voltage, and process; however the SLG46585 LDOs have taken this variance into consideration when recommending the
2 µF (min) X5R from -40 °C to +85 °C.
20.8 LDO REGULATOR COLD START UP
When the SLG46585 VDD goes high, then the fastest that an LDO regulator can begin to power up under the control of the
SLG46585 is ~2 ms typical, and 3 ms max.
During this cold start period the P Channel MOSFET gate is 0 V so the MOSFET is automatically turning on if LDO VIN is also
coming up.
20.9 LDO REGULATOR HOT START UP
When the SLG46585 VDD is already high, then the fastest than an LDO regulator can begin to power up is around 500 µs + soft
start ramping.
20.10 DISCHARGE RESISTORS
Each LDO comes with a program selectable 300 Ω discharge resistor. For applications that desire a power rail to be brought to
near zero during shutdown, then the 300 Ω discharge resistor is useful. For applications that desire to keep remaining charge on
a VOUT capacitor the discharge resistor should not be selected.
The discharge resistor is set by register [1455] for LDO0, register [1451] for LDO1, register [1463] for LDO2, and register [1459]
for LDO3.
20.11 TYPICAL APPLICATION CIRCUIT
VDD
LDO0 VOUT
LDO0
C1
0.1 µF
Cout0
4.7 µF
*
*
*
**
LDO0/1 VIN
LDO2/3 VIN
LDO1 VOUT
LDO2 VOUT
LDO1
LDO2
Cin0
10 µF
Cout1
4.7 µF
**
**
Cout2
4.7 µF
Cin1
10 µF
LDO3 VOUT
AGND
GND
LDO3
Cout3
4.7 µF
**
Note: All internal connections shown inside the SLG46585 are hardwired connections that cannot be changed.
Note*: Keep decoupling capacitors close to the SLG46585.
Note**: Keep output capacitors close to the SLG46585. Long distances negatively impact LDO stability.
Figure 99: LDO Typical Application Circuit
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
20.12 TYPICAL APPLICATION PERFORMANCE
4.342
4.34
4.338
4.336
4.334
4.332
4.33
4.328
0.0
20.0
40.0
60.0
80.0 100.0 120.0 140.0 160.0 180.0 200.0
OUT (mA)
I
Figure 100: LDO Load Regulation, HIGH POWER Mode, T = 25 °C, VDD = 5 V, VOUT = 4.35 V
4.50
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
0.0
1.0
2.0
3.0
4.0
5.0
IOUT (mA)
Figure 101: LDO Load Regulation, LOW POWER Mode, T = 25 °C, VDD = 5 V, VOUT = 4.35 V
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
ꢀ8ꢄ
ꢀ8ꢃꢁ
ꢀ8ꢃ
ꢉQ%ꢋYꢂꢁꢀIꢌ
ꢉQ%ꢋYꢂꢀꢀIꢌ
ꢉQ%ꢋYꢁꢀIꢌ
ꢉQ%ꢋYꢂꢀIꢌ
ꢀ8ꢂꢁ
ꢀ8ꢂ
ꢀ8ꢀꢁ
ꢀ
ꢃ8ꢁ
ꢄ8ꢀ
ꢄ8ꢁ
ꢅ8ꢀ
ꢅ8ꢁ
ꢁ8ꢀ
ꢆꢉꢊ ^ꢆ_
Figure 102: LDO Dropout Voltage vs. VIN
ꢄ8ꢂꢁ
ꢄ8ꢁꢁ
ꢃ8ꢂꢁ
ꢃ8ꢁꢁ
ꢀ8ꢂꢁ
ꢀ8ꢁꢁ
ꢌQ%ꢎYꢇꢂꢁIꢏ
ꢌQ%ꢎYꢇꢁꢁIꢏ
ꢌQ%ꢎYꢂꢁIꢏ
ꢌQ%ꢎYꢇꢁIꢏ
ꢀ8ꢂ
ꢀ8ꢅ
ꢃ8ꢃ
ꢃ8ꢆ
ꢄ8ꢇ
ꢈꢌꢍ ^ꢈ_
ꢄ8ꢂ
ꢄ8ꢅ
ꢂ8ꢃ
Figure 103: LDO High Power Mode VOUT vs. VIN, T = 25 °C, VDD = 5 V
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
ꢇ8ꢇꢀ
ꢇ8ꢀꢀ
ꢀ8ꢆꢀ
ꢀ8ꢅꢀ
ꢀ8ꢄꢀ
ꢀ8ꢃꢀ
ꢀ8ꢂꢀ
ꢀ8ꢁꢀ
ꢐQ%ꢑYꢈꢀꢀIꢒ
ꢐQ%ꢑYꢇꢂꢀIꢒ
ꢐQ%ꢑYꢇꢀꢀIꢒ
ꢐQ%ꢑYꢂꢀIꢒ
ꢐQ%ꢑYꢇꢀIꢒ
ꢈ8ꢂ
ꢈ8ꢆ
ꢉ8ꢉ
ꢉ8ꢄ
ꢁ8ꢇ
ꢏꢐꢎ ^ꢏ_
ꢁ8ꢂ
ꢁ8ꢆ
ꢂ8ꢉ
Figure 104: LDO P-Channel ON Resistance RDSon vs. VIN, Power Switch Mode, T = 25 °C
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
21 1 A Synchronous DC/DC Step Down Converter
21.1 DC/DC BUCK CONVERTER DESCRIPTION
The SLG46585 has a Synchronous DC/DC Step Down Converter macrocell. The DC/DC is rated for 1 A of current for an input
voltage range 2.5 V to 5.5 V and has one output voltage that can be regulated at six user selectable steps from 1.2 V to 3.3 V.
The DC/DC Step Down Converter is classified as a synchronous driver circuit that uses constant-on-time and constant frequency
pulse modulation technique. The device features DCM and CCM mode with automatic mode switching, and uses an integrated
internal resistive feedback divider.
Protection features include Over Current Protection, Thermal Shutdown, Under Voltage Lockout.
21.2 SYNCHRONOUS DC/DC STEP DOWN CONVERTER BLOCK DIAGRAM
DC_CCM
DC_INT
CCM Det
CMP
OCP
Note: DC_VIN and VDD pins must be connected together externally.
DC_VIN
Sw Freq. Sel
registers
[1876:1875]
OCP Prot. Level Sel
registers [1874:1873]
DC_Enable
From Connection Matrix [103]
VOSNS
SW
ON Time
Gen
Soft-Start
Power Good
DC_SW
CMP
PWM
ASM
DRV
DC_Enable
0.6 V
+
-
CMP
XZ
PGND
VOSNS
VOUT
Setting
Output Voltage Sel
registers [1879:1877]
Figure 105: DC/DC Block Diagram
21.3 TYPICAL APPLICATION CIRCUIT
Figure 106 shows the typical application circuit for the Synchronous DC/DC Step Down Converter macrocell, including a
selection of typical external components.
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SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
L1*
3.6 V
1.0 µH
VIN
2.5 V
VOUT @ 1 A
DC_VIN
DC_SW
CIN1
10 µF
CIN2
0.1 µF
CLOAD1
4.7 µF
CLOAD2
10 µF
DC_VOSNS
SLG46585
* Wurth 744777001
Taiyo Yuden NR6045T1R0N
VIN
R1
10 kΩ
1%
DC_CCM
R2
10 kΩ
1%
Continuous Conduction
Mode Indicator
DC_INT
Current Fault Interrupt
Indicator
AGND
PGND
Figure 106: DC/DC Typical Application Circuit
21.4 DC/DC BUCK CONVERTER PINOUT DESCRIPTION
ON/OFF command for the Synchronous DC/DC Step Down Converter is a matrix connection [831:824]. Its enable signal is
edge sensitive. During pin transition from Low to High, the Buck Converter will be enabled. And during transition from High to
Low, the Buck Converter will be disabled. This pin should never be floating.
DC_VIN - DC/DC Buck Converter input voltage pin.
DC_SW - DC/DC Buck Converter Switching Node. The SW is a pulse modulated signal that is connected to the inductor of
the LC Filter Circuit.
DC_VOSNS - DC/DC Buck Converter VOUT feedback (sense) input. This pin is connected to the Output Voltage at the load.
An internal feedback circuit regulates the output voltage by comparing it with an internal reference generated by the
DC_AGND. No external resistors are required.
DC_AGND - DC/DC Buck Converter Analog Ground feedback. This pin is connected to the Output Ground at the load. This
pin is the source for both internal feedback circuit and internal generated reference.
DC_PGND - DC/DC Buck Converter Power Ground.
DC_CCM - DC/DC Buck Converter digital output indicates whether the current mode is CCM or DCM.
DC_INT - DC/DC Buck Converter digital output indicates whether the over-current protection circuit has been activated due to
an over-current event or a thermal shutdown has occurred. The DC/DC Step Down Converter Fault Signal is routed to Matrix
Input 3.
21.5 CONFIGURABLE PARAMETERS
The DC/DC Converter's output voltage, switching frequency and current limit threshold are configurable. To change the
configuration in system, use I2C to write the registers and then toggle the ON/OFF Signal.
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 98: DC/DC Output Voltage Bit Settings
Table 100: DC/DC Current Limit Bit Settings
Output Voltage
1.2 V
registers [1879:1877]
Current Limit
2.5 A
registers [1874:1873]
000
001
010
011
100
101
00
10
1.5 V
2.0 A
1.8 V
2.5 V
3.0 V
3.3 V
Table 99: DC/DC Switching Frequency Bit Settings
Switching Frequency
1.5 MHz
registers [1876:1875]
00
01
2.0 MHz
21.6 OUTPUT VOLTAGE SELECTION
The Synchronous DC/DC Step Down Converter macrocell supports six user selectable output voltage levels. Register bits
registers [1879:1877] control this selection.
The DC/DC VIN operating range is from 2.5 to 5.5. However, the input voltage must be an extra 20 to 25% greater than the
output voltage due to the maximum duty-cycle limit. The maximum allowable duty cycle at 1.5 MHz is 80% and the maximum
allowable duty cycle at 2 MHz is 75%. Refer to the Table 101 for the typical input voltage ranges for each selectable output
voltage.
Table 101: DC/DC Output Voltage Selection
Input Voltage, 1.5 MHz
2.5 V to 5.5 V
Input Voltage, 2.0 MHz
2.5 V to 5.5 V
Output Voltage
1.2 V
2.5 V to 5.5 V
2.5 V to 5.5 V
1.5 V
2.5 V to 5.5 V
2.5 V to 5.5 V
1.8 V
3.125 V to 5.5 V
3.75 V to 5.5 V
4.125 V to 5.5 V
3.33 V to 5.5 V
4.0 V to 5.5 V
2.5 V
3.0 V
4.4 V to 5.5 V
3.3 V
21.7 SWITCHING FREQUENCY SELECTION
The Synchronous DC/DC Step Down Converter macrocell supports two user selectable output switching frequencies 1.5 MHz
and 2 MHz. Register bits registers [1876:1875] control frequency selection.
The Switching Frequency Selection affects the allowable input voltage range for each selectable output voltage. Refer to the
Table 101.
21.8 OVER-CURRENT PROTECTION LEVEL SELECTION
The Synchronous DC/DC Step Down Converter macrocell supports two user selectable current levels for the internal Over-Current
Protection circuitry. Register bits registers [1874:1873] control current level selection, see Table 100. The Over Current Protection
selections are dividers of the first register selection 00. So each subsequent selection is a ratio of the first current selection.
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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The Synchronous DC/DC Step Down Converter macrocell senses the current when the high-side MOSFET is on. If
an over-current condition occurs, i.e. the inductor current is higher than the user selected level between 2.0 A or 2.5 A (current
limit), the high-side MOSFET turns off for 2 µs, and the INT/pin will become active. Then the high-side MOSFET turns on again
if VOUT is lower than the user set voltage. If the inductor current is still higher than the current limit, the high-side MOSFET turns
off again. This process will repeat.
The converter has an INT pin which becomes active if an over-current condition occurs. User can feed this INT signal into an
input pin of the PAK, and then the PAK processes the signal and turn on/off the buck converter. For example, the PAK counts 8
INT pulses continuously, and then sends an “off” signal to the buck and turns it off. After a 1ms pause (off-time), the PAK sends
an “on” signal to the buck and turns it on. This is one of many possible solutions how the OCP hiccup handling can be implement-
ed. Please refer to an application note for more details.
21.9 DC/DC THERMAL SHUTDOWN
The Thermal Limit is set at 125 °C with a 25 °C hysteresis. The device must cool down to 100 °C before attempting to restart.
During thermal shutdown, the converter operation is disabled. The Buck can self-recover without toggling the Enable.
21.10 DC/DC UNDER VOLTAGE LOCKOUT
The Under Voltage Lockout is used to protect the converter from operating at an insufficient voltage. When the VIN is High enough
to reach the UVLO High threshold voltage, the converter will soft start to the selected output voltage if the ON/OFF command is
already High or transitions from Low to High. When the VIN decreases to its Low threshold voltage, the converter shuts down.
21.11 FAULT SIGNALS
The Fault Matrix Connection is an active High signal and signifies when there is a UVLO or a Thermal Shutdown. The output will
shut off. The DC/DC Buck Converter has a self-recovery capability. In UVLO, the device will recover if the DC_VIN satisfies the
UVLO condition. In Thermal Shutdown, the device will recover if the temperature drops below the hysteresis value.
The DC_INT is an active High signal and signifies when there is an Over Current Protection event. The DC/DC Buck Converter
will need to be powered off and then powered back on through the ON/OFF signal in order to recover from the Over-Current
event.
Table 102: DC/DC Output Voltage Selection
Fault
UVLO
OCP
TS
Fault Matrix Connection
DC_INT
Yes
--
--
Yes
--
Yes
21.12 DC/DC SOFT START
The DC/DC Soft Start begins after Under Voltage Lockout is satisfied and the Enable is toggled from Low to High. The time
between Enable and Soft Start will vary based on how fast the bandgap is able to rise. Once the bandgap is settled, the Converter
will enter the soft start sequence. In the soft-start sequence, the ramp time is 0.5 ms.
Any DC/DC Step Down Converter comparator outputs are ignored during the soft-start sequence. After soft-start ends, the output
is compared internally to the reference.
If the device enters Over Current Protection, there is a minimum Over Current Protection discharge period before which the device
will begin soft-start again. If the load is not released, the current in the inductor will build and the process repeats.
21.13 CONSTANT-ON-TIME
The constant-on-time control topology (COT) provides fast transient response and makes loop stabilization easier. Fault condition
protection includes current limiting and thermal shutdown. An Open-Drain INT output signals the host when an over-current
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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condition is detected and an Open-Drain CCM output signals the host when the converter operates in full continuous conduction
mode. The typical application circuit requires a minimum number of readily-available standard external components.
21.14 DC/DC CONTINUOUS CONDUCTION MODE (CCM)
The DC/DC Step Down Converter automatically switches into CCM when the regulating current exceeds the maximum deliverable
current in DCM Mode. In Continuous Conduction Mode, the current through the inductor may reach zero for a while before
charging again.
In this mode, the DC_CCM pin will be asserted.
21.15 DC/DC DISCONTINUOUS CONDUCTION MODE (DCM)
The DC/DC Step Down Converter automatically switches into DCM when the regulating current is below the minimum deliverable
current in CCM Mode. In Discontinuous Conduction Mode, the current through the inductor may reach zero for a while before
charging again.
21.16 DC/DC POWER DISSIPATION
Power Dissipation is estimated by the use of the efficiency chart for the buck.
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Figure 107: DC/DC Recommended PCB Layout
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21.17 LAYOUT CONSIDERATION
Layout is important to avoid instability and noise coupling which can lead to system failures. DC/DC Converters are highly
susceptible to instability and noise generated by high-current paths. At higher currents, both the DC/DC Converter and LDO are
susceptible to thermal self-heating. Proper layout will mitigate, suppress and avoid these undesirable artifacts.
21.17.1 Current Loops
Determine the path of current through the DC/DC Converter and the LDO. Blue is the path of current through the power stage
when the PMOS is enabled. Red is the path of current through the power stage when the NMOS is enabled. Green is the path of
current through the LDO is enabled. The path of current for the Push-Pull digital signals are supplied by VDD. Keep the digital
logic bypass capacitor close by (labeled CVDD).
Figure 108: DC/DC Converter Current Loops
21.17.2 AC vs DC
The blue and red lines are both AC because of the switching DC DC converter. While the upper FET is On, current flows along
the blue line. When the lower FET is On the current flows along the red line. The inductor prevents instantaneous changes in
current and therefore the red/blue path through the inductor and output capacitors are DC. The green LDO path is always DC
since there is no switching element.
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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Figure 109: DC/DC Converter AC and DC Loops
21.17.3 DC/DC Converter
AC Loop
Place the bypass capacitor CIN1 close to Vin and PGND to reduce EMI and voltage spikes caused by V = Ldi/dt. Place vias
near the capacitors to direct the current flow and ease thermal radiation.
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DC_SW and Inductor
Rotate the inductor so that the SW node is turned away from the chip in order not to disrupt any other signals and the output
capacitors are farthest from the AC Loop. Keep the DC_SW trace small in size, do not make the trace larger than it needs
to be. Keep inductor terminals and other traces separated to avoid coupling noise through stray capacitance.
Figure 110: AC Loop
Figure 111: DC Switch and Inductor
DC_VOSNS and DC_AGND
DC_VOSNS taps the VOUT close to the output. Place this tap point at the output. DC_AGND should be similarly tapped at
the output ground side. The purpose of these signals is for feedback loop and to generate a voltage reference. They are not
intended for large current flow.
DC_VIN, DC_SW and PGND
Due to the MSTQFN-29 package pitch size, the thermal bottlenecks occur at the pin leads. The Buck current limit is based
on the over-current selection. The width of the DC_SW and DC_VIN trace should be wide enough to avoid too much heating.
General rule of thumb is to allow 2 mm per 1 A. PGND should be fairly large, flat and as continuous as possible. Preferably
it should have a dedicated ground plane for the PGND and place bias to connect to the common GND.
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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Figure 112: DC Switch and Inductor
21.17.4 DC/DC Converter
LDO_VIN and LDO_VOUT
For best performance, place input and output capacitors as close as possible. The smaller the capacitor size, the lower the
voltage rating, but also the lower ESR.
LDO Stability
SLG46585 LDO requires very small inductance loops to guarantee stability. The total maximum inductance allowed is 5 nH
(including packaging). Outside the packaging, the total maximum inductance is 2 nH. This equates to 3 mm. The entire LDO
loop from LDO_VOUT to LDO_AGND should be no greater than 3 mm. Taking this into consideration, the LDO1_VOUT
should be pulled out to the side closest to the LDO_AGND to minimize inductance.
LDO_AGND
Use another layer and multiple vias to connect all the LDO_AGNDs together. LDO_AGND needs to be wide to help
dissipate the heat from the LDOs.
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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Figure 113: LDO_VIN and LDO_VOUT Current Flow
Figure 114: LDO Decoupling
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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Figure 115: LDO_AGND Layout
21.17.5 Digital
CVDD
VDD and GND power the digital side of the SLG46585. CVDD is the bypass capacitor (value 0.1 µF). The GND and VDD are
on opposite ends of the chip. Use a layer underneath to connect the GND pin to the ground on CVDD, which is placed as
close as possible to VDD pin
Ground Source
The Black Circle is the recommended location for connecting ground. It is in the middle, between the LDO and Buck. This is
called star grounding. When the ground source is placed in a central location, the current comes out like a star keeping the
ground currents going to the LDO and the Buck separated.
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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Figure 116: Ground Source for LDO and Buck
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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Figure 117: SLG46585 Ground Layout
Digital Signals
Shown in Teal, the digital signals should be wired on a separate routing layer. Since this device is in an MSP Package, a
multi-layer layout is unavoidable if all pins are sued. The Pull-up resistors are not shown on DC_INT and DC_CCM to
signal faults and CCM mode.
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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Figure 118: Digital Signals PCB Recommendation
21.18 TYPICAL PERFORMANCE CHARACTERISTICS
Figure 119: Efficiency vs. Output Current
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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Figure 120: Output Voltage vs. Load Current
VOUT
(20mV/Div)
VIN=5V, VOUT=1.2V
IOUT= 0.42A to 1A,
L=1uH
IOUT
(415mA/Div)
Figure 121: Load Transient Response
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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VIN
(5V/Div)
VOUT
(1V/Div)
VSW
(5V/Div)
IOUT
(1.25A/Div)
VIN=5V, VOUT=1.2V
IOUT= 0A, L=1uH
Figure 122: VIN Power Up without Load
VIN
(5V/Div)
VOUT
(1V/Div)
VSW
(5V/Div)
IOUT
(1.25A/Div)
VIN=5V, VOUT=1.2V
IOUT= 400mA, L=1uH
Figure 123: VIN Power Up with 400 mA Load
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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VIN
(5V/Div)
VOUT
(1V/Div)
VSW
(5V/Div)
IOUT
(1.25A/Div)
VIN=5V, VOUT=1.2V
IOUT= 1A, L=1uH
Figure 124: VIN Power Up with 1A Load
Figure 125: Low IQ Current vs. Input Voltage
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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VOUT
(100mV/Div)
VSW
(2V/Div)
VIN=5V, VOUT=1.2V
IOUT= 100mA, L=1uH
Figure 126: Output Ripple vs. IOUT = 100 mA
VOUT
(20mV/Div)
VSW
(5V/Div)
VIN=5V, VOUT=1.2V
IOUT= 1A, L=1uH
Figure 127: Output Ripple vs. IOUT = 1 A
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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22 Register Definitions
22.1 REGISTER MAP
Table 103: Register Map
I2C Interface
Register Bit
Address
Signal Function
Register Bit Definition
I2C Read I2C Write
Note: For register [0] to register [1495], I2C Read is valid (assuming register [1832] = 0), I2C Write is valid (assuming
register [1871] = 0)
Matrix Output
5:0
Matrix OUT: ASM-state0-EN0
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
7:6
13:8
Matrix OUT: ASM-state0-EN1
Reserved
15:14
21:16
Matrix OUT: ASM-state0-EN2
Reserved
23:22
29:24
Matrix OUT: ASM-state1-EN0
Reserved
31:30
37:32
Matrix OUT: ASM-state1-EN1
Reserved
39:38
45:40
Matrix OUT: ASM-state1-EN2
Reserved
47:46
53:48
Matrix OUT: ASM-state2-EN0
Reserved
55:54
61:56
Matrix OUT: ASM-state2-EN1
Reserved
63:62
69:64
Matrix OUT: ASM-state2-EN2
Reserved
71:70
77:72
Matrix OUT: ASM-state3-EN0
Reserved
79:78
85:80
Matrix OUT: ASM-state3-EN1
Reserved
87:86
93:88
Matrix OUT: ASM-state3-EN2
Reserved
95:94
101:96
103:102
109:104
111:110
117:112
119:118
125:120
127:126
133:128
135:134
141:136
143:142
Matrix OUT: ASM-state4-EN0
Reserved
Matrix OUT: ASM-state4-EN1
Reserved
Matrix OUT: ASM-state4-EN2
Reserved
Matrix OUT: ASM-state5-EN0
Reserved
Matrix OUT: ASM-state5-EN1
Reserved
Matrix OUT: ASM-state5-EN2
Reserved
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 103: Register Map (Continued)
I2C Interface
Register Bit
Address
Signal Function
Register Bit Definition
I2C Read I2C Write
149:144
151:150
157:152
159:158
165:160
167:166
173:168
175:174
181:176
183:182
189:184
191:190
197:192
199:198
Matrix OUT: ASM-state6-EN0
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Matrix OUT: ASM-state6-EN1
Reserved
Matrix OUT: ASM-state6-EN2
Reserved
Matrix OUT: ASM-state7-EN0
Reserved
Matrix OUT: ASM-state7-EN1
Reserved
Matrix OUT: ASM-state7-EN2
Reserved
Matrix OUT: ASM-state-nRST
Reserved
Matrix OUT: IN0 of LUT3_6 or Delay0 Input
(or Counter0 RST Input)
205:200
207:206
213:208
Valid
Valid
Valid
Valid
Valid
Valid
Reserved
MatrixOUT:IN1ofLUT3_6orExternalClock
Input of Delay0 (or Counter0)
215:214
221:216
223:222
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
Matrix OUT: IN2 of LUT3_6
Reserved
Matrix OUT: IN0 of LUT3_7 or Delay1 Input
(or Counter1 RST Input)
229:224
231:230
237:232
Valid
Valid
Valid
Valid
Valid
Valid
Reserved
MatrixOUT:IN1ofLUT3_7orExternalClock
Input of Delay1 (or Counter1)
239:238
245:240
247:246
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
Matrix OUT: IN2 of LUT3_7
Reserved
Matrix OUT: IN0 of LUT3_8 or Delay2 Input
(or Counter2 RST Input)
253:248
255:254
261:256
Valid
Valid
Valid
Valid
Valid
Valid
Reserved
MatrixOUT:IN1ofLUT3_8orExternalClock
Input of Delay2 (or Counter2)
263:262
269:264
271:270
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
Matrix OUT: IN2 of LUT3_8
Reserved
Matrix OUT: IN0 of LUT3_9 or Delay3 Input
(or Counter3 RST Input)
277:272
279:278
285:280
287:286
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Reserved
MatrixOUT:IN1ofLUT3_9orExternalClock
Input of Delay3 (or Counter3)
Reserved
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 103: Register Map (Continued)
I2C Interface
Register Bit
Address
Signal Function
Register Bit Definition
I2C Read I2C Write
293:288
295:294
Matrix OUT: IN2 of LUT3_9
Reserved
Valid
Valid
Valid
Valid
Matrix OUT: IN0 of LUT3_10 or Delay4 Input
(or Counter4 RST Input)
301:296
303:302
309:304
Valid
Valid
Valid
Valid
Valid
Valid
Reserved
Matrix OUT: IN1 of LUT3_10 or External
Clock Input of Delay4 (or Counter4)
311:310
317:312
319:318
325:320
327:326
333:328
335:334
341:336
343:342
349:344
351:350
357:352
359:358
365:360
367:366
373:368
375:374
381:376
383:382
389:384
391:390
397:392
399:398
405:400
407:406
413:408
415:414
421:416
423:422
429:424
431:430
437:432
439:438
445:440
447:446
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Matrix OUT: IN2 of LUT3_10
Reserved
Matrix OUT: IO0 Digital Output Source
Reserved
Matrix OUT: IO0 Output Enable
Reserved
Matrix OUT: IO1 Digital Output Source
Reserved
Reserved
Reserved
Reserved
Reserved
Matrix OUT: IO2 Digital Output Source
Reserved
Matrix OUT: IO2 Output Enable
Reserved
Matrix OUT: IO4 Digital Output Source
Reserved
Matrix OUT: IO4 Output Enable
Reserved
Matrix OUT: IO5 Digital Output Source
Reserved
Matrix OUT: IO6 Digital Output Source
Reserved
Matrix OUT: IO6 Output Enable
Reserved
Matrix OUT: ACMP0 PWR UP
Reserved
Matrix OUT: ACMP1 PWR UP
Reserved
Matrix OUT: ACMP2 PWR UP
Reserved
Matrix OUT: ACMP3 PWR UP
Reserved
Datasheet
18-Sep-2019
Revision 3.3
173 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 103: Register Map (Continued)
I2C Interface
Register Bit
Address
Signal Function
Register Bit Definition
I2C Read I2C Write
Matrix OUT: Input of Filter_0 with fixed time
edge detector
453:448
455:454
461:456
463:462
469:464
471:470
477:472
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Reserved
Matrix OUT: Input of Filter_1 with fixed time
edge detector
Reserved
Matrix OUT: Input of Programmable Delay &
Edge Detector
Reserved
Matrix OUT: OSC 25kHz/2MHz PD
(Power-Down)
479:478
485:480
487:486
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
Matrix OUT: LPOSC PD (Power-Down)
Reserved
Matrix OUT: IN0 of LUT2_0 or Clock Input of
DFF0
493:488
495:494
501:496
503:502
509:504
511:510
517:512
519:518
525:520
527:526
533:528
535:534
541:536
543:542
549:544
551:550
557:552
559:558
565:560
567:566
573:568
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Reserved
Matrix OUT: IN1 of LUT2_0 or Data Input of
DFF0
Reserved
Matrix OUT: IN0 of LUT2_1 or Clock Input of
DFF1
Reserved
Matrix OUT: IN1 of LUT2_1 or Data Input of
DFF1
Reserved
Matrix OUT: IN0 of LUT2_2 or Clock Input of
DFF2
Reserved
Matrix OUT: IN1 of LUT2_2 or Data Input of
DFF2
Reserved
Matrix OUT: IN0 of LUT3_0 or Clock Input of
DFF3
Reserved
Matrix OUT: IN1 of LUT3_0 or Data Input of
DFF3
Reserved
Matrix OUT: IN2 of LUT3_0 or nRST (nSET)
of DFF3
Reserved
Matrix OUT: IN0 of LUT3_1 or Clock Input of
DFF4
Reserved
Matrix OUT: IN1 of LUT3_1 or Data Input of
DFF4
Datasheet
18-Sep-2019
Revision 3.3
174 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 103: Register Map (Continued)
I2C Interface
Register Bit
Address
Signal Function
Register Bit Definition
I2C Read I2C Write
575:574
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Matrix OUT: IN2 of LUT3_1 or nRST (nSET)
of DFF4
581:576
583:582
589:584
591:590
597:592
599:598
605:600
607:606
613:608
615:614
621:616
623:622
629:624
631:630
637:632
639:638
645:640
647:646
653:648
655:654
Reserved
Matrix OUT: IN0 of LUT3_2 or Clock Input of
DFF5
Reserved
Matrix OUT: IN1 of LUT3_2 or Data Input of
DFF5
Reserved
Matrix OUT: IN2 of LUT3_2 or nRST (nSET)
of DFF5
Reserved
Matrix OUT: IN0 of LUT3_3 or Clock Input of
DFF6
Reserved
Matrix OUT: IN1 of LUT3_3 or Data Input of
DFF6
Reserved
Matrix OUT: IN2 of LUT3_3 or nRST (nSET)
of DFF6
Reserved
Matrix OUT: IN0 of LUT3_4 or Clock Input of
DFF7
Reserved
Matrix OUT: IN1 of LUT3_4 or Data Input of
DFF7
Reserved
Matrix OUT: IN2 of LUT3_4 or nRST (nSET)
of DFF7
Reserved
Matrix OUT: IN0 of LUT3_11 or Input of Pipe
661:656
Delay or Up/Down selection of Ripple Count-
er
Valid
Valid
663:662
669:664
671:670
677:672
679:678
685:680
687:686
693:688
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Matrix OUT: IN1 of LUT3_11 or nRSTof Pipe
Delay or nRST of Ripple Counter
Reserved
Matrix OUT: IN2 of LUT3_11 or Clock of Pipe
Delay or Clock of Ripple Counter
Reserved
Matrix OUT: IN0 of LUT3_5 or Clock Input of
DFF8
Reserved
Matrix OUT: IN1 of LUT3_5 or Data Input of
DFF8
Datasheet
18-Sep-2019
Revision 3.3
175 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 103: Register Map (Continued)
I2C Interface
Register Bit
Address
Signal Function
Register Bit Definition
I2C Read I2C Write
695:694
Reserved
Valid
Valid
Matrix OUT: IN2 of LUT3_5 or nRST (nSET)
of DFF8
701:696
Valid
Valid
703:702
709:704
711:710
717:712
719:718
725:720
727:726
733:728
735:734
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Matrix OUT: IN0 of LUT4x2_0
Reserved
Matrix OUT: IN1 of LUT4x2_0
Reserved
Matrix OUT: IN2 of LUT4x2_0
Reserved
Matrix OUT: IN3 of LUT4x2_0
Reserved
Matrix OUT: LDO MODE1 Enable for LDO0/
1/2/3
741:736
Valid
Valid
743:742
749:744
751:750
757:752
759:758
765:760
767:766
773:768
775:774
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Matrix OUT: LDO0_EN
Reserved
Matrix OUT: LDO1_EN
Reserved
Matrix OUT: LDO2_EN
Reserved
Matrix OUT: LDO3_EN
Reserved
Matrix OUT: LDO0 2nd VOUT Selection En-
able
781:776
783:782
789:784
791:790
797:792
799:798
805:800
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Reserved
Matrix OUT: LDO1 2nd VOUT Selection En-
able
Reserved
Matrix OUT: LDO2 2nd VOUT Selection En-
able
Reserved
Matrix OUT: LDO3 2nd VOUT Selection En-
able
807:806
813:808
815:814
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
Matrix OUT: RTC Clock
Reserved
Matrix OUT: RTC Trigger signal to read/write
RTC CNT values
821:816
823:822
829:824
Valid
Valid
Valid
Valid
Valid
Valid
Reserved
Matrix OUT: ON/OFF command for Synchro-
nous DC/DC Step Down Converter
831:830
837:832
Reserved
Valid
Valid
Valid
Valid
Matrix OUT: Reserved
Datasheet
18-Sep-2019
Revision 3.3
176 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 103: Register Map (Continued)
I2C Interface
Register Bit
Address
Signal Function
Register Bit Definition
I2C Read I2C Write
839:838
845:840
847:846
853:848
855:854
861:856
863:862
869:864
871:870
877:872
879:878
881:880
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Matrix OUT: Reserved
Reserved
Matrix OUT: Reserved
Reserved
Matrix OUT: Reserved
Reserved
Matrix OUT: Reserved
Reserved
Reserved
Reserved
Reserved
LDO2/3 VDD minimum Power Selection for 000: 2.5V, 001: 2.8V, 010: 3.0V, 011: 3.3V,
LDO3 100: 3.6V, 101: 3.9V, 110: 4.4V, 111: 4.5V
884:882
887:885
Valid
Valid
Valid
Valid
LDO2/3 VDD minimum Power Selection for 000: 2.5V, 001: 2.8V, 010: 3.0V, 011: 3.3V,
LDO2
100: 3.6V, 101: 3.9V, 110: 4.4V, 111: 4.5V
895:888
903:896
911:904
919:912
927:920
935:928
943:936
950:944
951
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Valid
CNT2 Counted Value for I2C read
CNT4 Counted Value for I2C read
Reserved
Reserved
Reserved
Shadow buffer for RTC counter [7:0]
Shadow buffer for RTC counter [14:8]
Reserved
Valid
Valid
959:952
967:960
975:968
983:976
988:984
Shadow buffer for RTC counter [23:16]
Shadow buffer for RTC counter [31:24]
Shadow buffer for RTC counter [39:32]
Shadow buffer for RTC counter [47:40]
Reserved
Valid
Valid
Valid
Valid
Valid
Shadow buffer data transfer direction selec-
tion
989
990
991
Valid
Valid
Valid
Valid
Valid
Valid
Shadow buffer trigger signal selection
0: From 15-bit counter divider
1: From RTC clock
RTC 32-bit time counter clock source
999:992
1007:1000
1015:1008
1023:1016
Alarm DCMP [23:16]
Alarm DCMP [31:24]
Alarm DCMP [39:32]
Alarm DCMP [47:40]
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
IO0
1024
1025
Reserved
Valid
Valid
Valid
Valid
0: Pull-down Resistor
1: Pull-up Resistor
IO0 Pull-up/down Resistor Selection
Datasheet
18-Sep-2019
Revision 3.3
177 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 103: Register Map (Continued)
I2C Interface
Register Bit
Address
Signal Function
Register Bit Definition
I2C Read I2C Write
00: Floating
01: 10K
10: 100K
1027:1026
IO0 Pull-up/down Resistor Value Selection
Valid
Valid
Valid
Valid
Valid
Valid
11: 1M
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
11: Reserved
1029:1028
1031:1030
IO0 Mode Control (sig_io0_oe = 0)
IO0 Mode Control (sig_io0_oe = 1)
00: Push-Pull 1x
01: Push-Pull 2x
10: Open-Drain NMOS 1x
11: Open-Drain NMOS 2x
IO1
1032
1033
Reserved
Valid
Valid
Valid
Valid
0: 1x
1: 2x
IO1 Driver Strength Selection
0: Pull-down Resistor
1: Pull-up Resistor
1034
IO1 Pull-up/down Resistor Selection
Valid
Valid
Valid
Valid
00: Floating
01: 10K
10: 100K
1036:1035
IO1 Pull-up/down Resistor Value Selection
11: 1M
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Analog Input/Output
1039:1037
IO1 Mode Control
Valid
Valid
100: Push-Pull
101: Open-Drain NMOS
110: Open-Drain PMOS
111: Analog Input & Open-Drain NMOS
Reserved
1040
1041
Reserved
Reserved
Reserved
Reserved
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
1042
1044:1043
1047:1045
Reserved
1048
1049
Reserved
Reserved
Reserved
Reserved
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
1050
1052:1051
1055:1053
IO2
1056
1057
Reserved
Valid
Valid
Valid
Valid
0: Pull-down Resistor
1: Pull-up Resistor
IO2 Pull-up/down Resistor Selection
Datasheet
18-Sep-2019
Revision 3.3
178 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 103: Register Map (Continued)
I2C Interface
Register Bit
Address
Signal Function
Register Bit Definition
I2C Read I2C Write
00: Floating
01: 10K
10: 100K
1059:1058
IO2 Pull-down Resistor Value Selection
Valid
Valid
Valid
Valid
Valid
Valid
11: 1M
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
1061:1060
1063:1062
IO2 Mode Control (sig_io2_oe = 0)
IO2 Mode Control (sig_io2_oe = 1)
11: Analog Input/Output
00: Push-Pull 1x
01: Push-Pull 2x
10: Open-Drain NMOS 1x
11: Open-Drain NMOS 2x
IO3
1064
1065
Reserved
Reserved
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
1067:1066
00: Floating
01: 10K
10: 100K
11: 1M
1069:1068
1071:1070
IO3 Pull-down Resistor Value Selection
IO3 Mode Control
Valid
Valid
Valid
Valid
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
11: Reserved
SCL
1072
1073
Reserved
Reserved
Reserved
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
1074
1076:1075
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
11: Reserved
1078:1077
1079
SCL Mode Control
Reserved
Valid
Valid
Valid
Valid
SDA
1080
1081
Reserved
Valid
Valid
Valid
Valid
0: 1x
1: 2x
SDA Driver Strength Selection
1082
Reserved
Reserved
Valid
Valid
Valid
Valid
1084:1083
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
11: Reserved
1086:1085
SDA Mode Control
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
1087
IO4
1088
Reserved
Datasheet
18-Sep-2019
Revision 3.3
179 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 103: Register Map (Continued)
I2C Interface
Register Bit
Address
Signal Function
Register Bit Definition
I2C Read I2C Write
0: Pull-down Resistor
1: Pull-up Resistor
1089
IO4 Pull-up/down Resistor Selection
Valid
Valid
00: Floating
01: 10K
10: 100K
1091:1090
1093:1092
1095:1094
IO4 Pull-up/down Resistor Value Selection
IO4 Mode Control (sig_io4_oe = 0)
IO4 Mode Control (sig_io4_oe = 1)
Valid
Valid
11: 1M
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
Valid
Valid
Valid
Valid
11: Analog Input/Output
00: Push-Pull 1x
01: Push-Pull 2x
10: Open-Drain NMOS 1x
11: Open-Drain NMOS 2x
IO5
1096
1097
Reserved
Valid
Valid
Valid
Valid
0: 1x
1: 2x
IO5 Driver Strength Selection
0: Pull-down Resistor
1: Pull-up Resistor
1098
IO5 Pull-up/down Resistor Selection
Valid
Valid
Valid
Valid
00: Floating
01: 10K
10: 100K
1100:1099
IO5 Pull-up/down Resistor Value Selection
11: 1M
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Analog Input/Output
1103:1101
IO5 Mode Control
Valid
Valid
100: Push-Pull
101: Open-Drain NMOS
110: Open-Drain PMOS
111: Analog Input & Open-Drain NMOS
IO6
1104
1105
Reserved
Valid
Valid
Valid
Valid
0: Pull-down Resistor
1: Pull-up Resistor
IO6 Pull-up/down Resistor Selection
00: Floating
01: 10K
10: 100K
11: 1M
1107:1106
1109:1108
1111:1110
IO6 Pull-up/down Resistor Value Selection
IO6 Mode Control (sig_io6_oe = 0)
IO6 Mode Control (sig_io6_oe = 1)
Valid
Valid
Valid
Valid
Valid
Valid
00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
11: Analog Input/Output
00: Push-Pull 1x
01: Push-Pull 2x
10: Open-Drain NMOS 1x
11: Open-Drain NMOS 2x
ACMP
1112
ACMP1 Positive Input Source Select -
ACMP0 IN+ Source
0: Disable
1: Enable
Valid
Valid
Datasheet
18-Sep-2019
Revision 3.3
180 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 103: Register Map (Continued)
I2C Interface
Register Bit
Address
Signal Function
Register Bit Definition
I2C Read I2C Write
ACMP1 Analog Buffer Enable (Max. BW
1MHz)
0: Disable analog buffer
1: Enable analog buffer
1113
Valid
Valid
00: 0 mV
01: 25 mV
10: 50 mV
11: 200 mV
1115:1114
ACMP1 Hysteresis Enable
Valid
Valid
(01: for both external & internal Vref, 10 &
11: for only internal Vref, External Vref will
not have 50 mV & 200 mV hysteresis.)
0: Disable
1: Enable
1116
1117
ACMP0 Positive Input Source Select VDD
Valid
Valid
Valid
Valid
ACMP0 Analog Buffer Enable (Max. BW
1MHz)
0: Disable analog buffer
1: Enable analog buffer
00: 0 mV
01: 25 mV
10: 50 mV
1119:1118
1120
ACMP0 Hysteresis Enable
11: 200 mV
Valid
Valid
Valid
Valid
(01: for both external & internal Vref, 10 &
11: for only internal Vref, External Vref will
not have 50 mV & 200 mV hysteresis.)
ACMP3 Positive Input Source Select -
ACMP2 IN+ Source
0: Disable
1: Enable
000: 0 mV
001: 25 mV
010: 50 mV
011: 200 mV
100: Reserved
101: Reserved
110: 100 mV
111: 150 mV
(001: for both external & internal Vref, 010
& 011 & 110 & 111: for only internal Vref,
External Vref will not have (50, 100, 150,
200) mV hysteresis.)
1123:1121
ACMP3 Hysteresis Enable
Valid
Valid
Valid
Valid
Valid
Valid
ACMP2 Positive Input Source Select -
ACMP0 IN+ Source
0: Disable
1: Enable
1124
000: 0 mV
001: 25 mV
010: 50 mV
011: 200 mV
100: Reserved
101: Reserved
110: 100 mV
1127:1125
ACMP2 Hysteresis Enable
111: 150 mV
(001: for both external & internal Vref, 010
& 011 & 110 & 111: for only internal Vref,
External Vref will not have (50, 100, 150,
200) mV hysteresis.)
LUT
0: LUT3_4
1: DFF7 with nRST/nSET
1128
1129
LUT3_4 or DFF7 with nRST/nSET Select
LUT3_3 or DFF6 with nRST/nSET Select
Valid
Valid
Valid
Valid
0: LUT3_3
1: DFF6 with nRST/nSET
Datasheet
18-Sep-2019
Revision 3.3
181 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 103: Register Map (Continued)
I2C Interface
Register Bit
Address
Signal Function
Register Bit Definition
I2C Read I2C Write
0: LUT3_2
1: DFF5 with nRST/nSET
1130
LUT3_2 or DFF5 with nRST/nSET Select
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
0: LUT3_1
1: DFF4 with nRST/nSET
1131
1132
1133
1134
1135
LUT3_1 or DFF4 with nRST/nSET Select
LUT3_0 or DFF3 with nRST/nSET Select
0: LUT3_0
(Two consecutive DFFs if [1431]=1 for ASM) 1: DFF3 with nRST/nSET
0: LUT2_2
LUT2_2 or DFF2 Select
1: DFF2
0: LUT2_1
LUT2_1 or DFF1 Select
1: DFF1
0: LUT2_0
LUT2_0 or DFF0 Select
1: DFF0
LUT3
1136
1137
Reserved
Reserved
Valid
Valid
Valid
Valid
0: LUT3_5
LUT3_5 or DFF8 with nRST/nSET Select
1: DFF8 with nRST/nSET
1138
1139
1140
1141
1142
1143
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
0: LUT3_10
LUT3_10 or DLY/CNT4(8bits) Select
1: DLY/CNT4(8bits)
0: LUT3_9
LUT3_9 or DLY/CNT3(8bits) Select
1: DLY/CNT3(8bits)
0: LUT3_8
LUT3_8 or DLY/CNT2(8bits) Select
1: DLY/CNT2(8bits)
0: LUT3_7
LUT3_7 or DLY/CNT1(8bits) Select
1: DLY/CNT1(8bits)
0: LUT3_6
LUT3_6 or DLY/CNT0(8bits) Select
1: DLY/CNT0(8bits)
LUT2
1144
1145
LUT2_1 [0]
Valid
Valid
Valid
Valid
0: Low
LUT2_1 [1]/DFF1 Initial Polarity Select
1: High
0: Q output
LUT2_1 [2]/DFF1 Output Select
1: nQ output
1146
Valid
Valid
0: DFF function
LUT2_1 [3]/DFF1 or LATCH1 Select
1: LATCH function
1147
1148
1149
Valid
Valid
Valid
Valid
Valid
Valid
LUT2_0 [0]
0: Low
LUT2_0 [1]/DFF0 Initial Polarity Select
1: High
0: Q output
LUT2_0 [2]/DFF0 Output Select
1: nQ output
1150
1151
Valid
Valid
Valid
Valid
0: DFF function
LUT2_0 [3]/DFF0 or LATCH0 Select
1: LATCH function
1155:1152
1156
Reserved
Valid
Valid
Valid
Valid
LUT2_2 [0]
0: Low
LUT2_2 [1]/DFF2 Initial Polarity Select
1: High
1157
Valid
Valid
Datasheet
18-Sep-2019
Revision 3.3
182 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 103: Register Map (Continued)
I2C Interface
Register Bit
Address
Signal Function
Register Bit Definition
I2C Read I2C Write
0: Q output
1: nQ output
1158
LUT2_2 [2]/DFF2 Output Select
Valid
Valid
Valid
Valid
0: DFF function
1: LATCH function
1159
LUT2_2 [3]/DFF2 or LATCH2 Select
LUT3
1163:1160
LUT3_0 [3:0]
Valid
Valid
Valid
Valid
0: Low
1: High
1164
LUT3_0 [4]/DFF3 Initial Polarity Select
0: nRST from Matrix Output
1: nSET from Matrix Output
1165
1166
LUT3_0 [5]/DFF3 nRST or nSET Select
LUT3_0 [6]/DFF3 Output Select
Valid
Valid
Valid
Valid
0: Q output
1: nQ output
0: DFF function
1: LATCH function
1167
1171:1168
1172
LUT3_0 [7]/DFF3 or LATCH3 Select
LUT3_1 [3:0]
Valid
Valid
Valid
Valid
Valid
Valid
0: Low
1: High
LUT3_1 [4]/DFF4 Initial Polarity Select
0: nRST from Matrix Output
1: nSET from Matrix Output
1173
1174
LUT3_1 [5]/DFF4 nRST or nSET Select
LUT3_1 [6]/DFF4 Output Select
Valid
Valid
Valid
Valid
0: Q output
1: nQ output
0: DFF function
1: LATCH function
1175
1179:1176
1180
LUT3_1 [7]/DFF4 or LATCH4 Select
LUT3_2 [3:0]
Valid
Valid
Valid
Valid
Valid
Valid
0: Low
1: High
LUT3_2 [4]/DFF5 Initial Polarity Select
0: nRST from Matrix Output
1: nSET from Matrix Output
1181
1182
LUT3_2 [5]/DFF5 nRST or nSET Select
LUT3_2 [6]/DFF5 Output Select
Valid
Valid
Valid
Valid
0: Q output
1: nQ output
0: DFF function
1: LATCH function
1183
1187:1184
1188
LUT3_2 [7]/DFF5 or LATCH5 Select
LUT3_3 [3:0]
Valid
Valid
Valid
Valid
Valid
Valid
0: Low
1: High
LUT3_3 [4]/DFF6 Initial Polarity Select
0: nRST from Matrix Output
1: nSET from Matrix Output
1189
1190
LUT3_3 [5]/DFF6 nRST or nSET Select
LUT3_3 [6]/DFF6 Output Select
Valid
Valid
Valid
Valid
0: Q output
1: nQ output
0: DFF function
1: LATCH function
1191
1195:1192
1196
LUT3_3 [7]/DFF6 or LATCH6 Select
LUT3_4 [3:0]
Valid
Valid
Valid
Valid
Valid
Valid
0: Low
1: High
LUT3_4 [4]/DFF7 Initial Polarity Select
0: nRST from Matrix Output
1: nSET from Matrix Output
1197
1198
LUT3_4 [5]/DFF7 nRST or nSET Select
LUT3_4 [6]/DFF7 Output Select
Valid
Valid
Valid
Valid
0: Q output
1: nQ output
Datasheet
18-Sep-2019
Revision 3.3
183 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 103: Register Map (Continued)
I2C Interface
Register Bit
Address
Signal Function
Register Bit Definition
I2C Read I2C Write
0: DFF function
1: LATCH function
1199
1203:1200
1204
LUT3_4 [7]/DFF7 or LATCH7 Select
LUT3_5 [3:0]
Valid
Valid
Valid
Valid
Valid
Valid
0: Low
1: High
LUT3_5 [4]/DFF8 Initial Polarity Select
0: nRST from Matrix Output
1: nSET from Matrix Output
1205
1206
1207
LUT3_5 [5]/DFF8 nRST or nSET Select
LUT3_5 [6]/DFF8 Output Select
Valid
Valid
Valid
Valid
Valid
Valid
0: Q output
1: nQ output
0: DFF function
1: LATCH function
LUT3_5 [7]/DFF8 or LATCH8 Select
Reserved
1215:1208
1223:1216
Reserved
Reserved
Valid
Valid
Valid
Invalid
LUT3 & DLY/CNT
LUT3_11 [3:0]/Pipe Delay OUT0 Select/Rip-
ple Counter END[0],nSET[2:0]
1227:1224
Valid
Valid
LUT3_11 [7:4]/Pipe Delay OUT1 Select/Rip- [1230] for Ripple counter MODE function:
1231:1228
1232
Valid
Valid
Valid
Valid
Valid
Valid
ple Counter RSVD,MODE,END[2:1]
0: FULL, 1: RANGE
Reserved
0: Default function from [1277]
1: Delayed edge detect
1233
DLY/CNT4 Delayed Edge Output Selection
DLY/CNT3 Delayed Edge Output Selection
DLY/CNT2 Delayed Edge Output Selection
DLY/CNT1 Delayed Edge Output Selection
Pipe Delay Select or Ripple counter Select
LUT3_11 or Pipe Delay Select
0: Default function from [1269]
1: Delayed edge detect
1234
1235
1236
1237
1238
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
0: Default function from [1261]
1: Delayed edge detect
0: Default function from [1253]
1: Delayed edge detect
0: Pipe Delay
1: Ripple Counter
0: LUT3_11
1: Pipe Delay/Ripple counter by [1237]
0: Non-Inverted
1: Inverted
1239
Pipe Delay OUT1 Polarity Select
DLY/CNT0
00: On both Falling and Rising Edges
01: on Falling Edge only
10: on Rising Edge only
11: No Delay on either Falling or Rising
Edges/High Level Counter Reset
DLY0 Edge Select or Asynchronous CNT0
Reset
1241:1240
1244:1242
Valid
Valid
Valid
Valid
000: OSC
001: OSC/4
010: OSC/12
011: OSC/24
DLY/CNT0 Clock Source Select
100: OSC/64
101: LPOSC Clock
110: External Clock
111: Counter4 Overflow
Datasheet
18-Sep-2019
Revision 3.3
184 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 103: Register Map (Continued)
I2C Interface
Register Bit
Address
Signal Function
Register Bit Definition
I2C Read I2C Write
CNT0's Q are Set to data or Reset to 0s Se- 0: Reset to 0s
1245
Valid
Valid
lection (8bits)
1: Set to data ([1543:1536])
00: Delay mode
01: One Shot
10: Freq. Detect
1247:1246
DLY/CNT0 Mode Selection
Valid
Valid
11: Counter mode
DLY/CNT1
00: On both Falling and Rising Edges
01: On Falling Edge only
10: On Rising Edge only
11: No Delay on either Falling or Rising
Edges/High Level Counter Reset
DLY1 Edge Select or Asynchronous CNT1
Reset
1249:1248
1252:1250
Valid
Valid
Valid
Valid
000: OSC
001: OSC/4
010: OSC/12
011: OSC/24
DLY/CNT1 Clock Source Select
100: OSC/64
101: LPOSC Clock
110: External Clock
111: Counter0 Overflow
0: Default Output
1: Edge Detector Output
1253
DLY/CNT1 Output Selection
DLY/CNT1 Mode Selection
Valid
Valid
Valid
Valid
00: Delay mode
01: One Shot
10: Freq. Detect
1255:1254
11: Counter mode
DLY/CNT2
00: On both Falling and Rising Edges
01: on Falling Edge only
10: on Rising Edge only
11: No Delay on either Falling or Rising
Edges/High Level Counter Reset
DLY2 Edge Select or Asynchronous CNT2
Reset
1257:1256
1260:1258
Valid
Valid
Valid
Valid
000: OSC
001: OSC/4
010: OSC/12
011: OSC/24
DLY/CNT2 Clock Source Select
100: OSC/64
101: LPOSC Clock
110: External Clock
111: Counter1 Overflow
0: Default Output
1: Edge Detector Output
1261
DLY/CNT2 Output Selection
DLY/CNT2 Mode Selection
Valid
Valid
Valid
Valid
00: Delay mode
01: One Shot
10: Freq. Detect
1263:1262
11: Counter mode
DLY/CNT3
00: On both Falling and Rising Edges
01: On Falling Edge only
10: On Rising Edge only
11: No Delay on either Falling or Rising
Edges/High Level Counter Reset
DLY3 Edge Select or Asynchronous CNT3
Reset
1265:1264
Valid
Valid
Datasheet
18-Sep-2019
Revision 3.3
185 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 103: Register Map (Continued)
I2C Interface
Register Bit
Address
Signal Function
Register Bit Definition
I2C Read I2C Write
000: OSC
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
1268:1266
DLY/CNT3 Clock Source Select
Valid
Valid
101: LPOSC Clock
110: External Clock
111: Counter2 Overflow
0: Default Output
1: Edge Detector Output
1269
DLY/CNT3 Output Selection
DLY/CNT3 Mode Selection
Valid
Valid
Valid
Valid
00: Delay mode
01: One Shot
10: Freq. Detect
1271:1270
11: Counter mode
DLY/CNT4
00: On both Falling and Rising Edges
01: On Falling Edge only
10: On Rising Edge only
11: No Delay on either Falling or Rising
Edges/High Level Counter Reset
DLY4 Edge Select or Asynchronous CNT4
Reset
1273:1272
1276:1274
Valid
Valid
Valid
Valid
000: OSC
001: OSC/4
010: OSC/12
011: OSC/24
DLY/CNT4 Clock Source Select
100: OSC/64
101: LPOSC Clock
110: External Clock
111: Counter3 Overflow
0: Default Output
1: Edge Detector Output
1277
DLY/CNT4 Output Selection
DLY/CNT4 Mode Selection
Valid
Valid
Valid
Valid
00: Delay mode
01: One Shot
10: Freq. Detect
1279:1278
11: Counter mode
Reserved
1280
1281
Reserved
Reserved
Valid
Valid
Valid
Valid
External Clock Source Select instead of
25kHz/2MHz
0: Internal Oscillator,
1: External Clock (EXT_CLK)
1282
Valid
Valid
DLY/CNT Polarity Select
0: Default Output
1: Inverted Output
1283
1284
1285
1286
1287
Select the Polarity of DLY/CNT4's Output
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
0: Default Output
1: Inverted Output
Select the Polarity of DLY/CNT3's Output
Select the Polarity of DLY/CNT2's Output
Select the Polarity of DLY/CNT1's Output
Select the Polarity of DLY/CNT0's Output
0: Default Output
1: Inverted Output
0: Default Output
1: Inverted Output
0: Default Output
1: Inverted Output
Datasheet
18-Sep-2019
Revision 3.3
186 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 103: Register Map (Continued)
I2C Interface
Register Bit
Address
Signal Function
Register Bit Definition
I2C Read I2C Write
OSC
1289:1288
1290
LPOSC Clock Pre-divider
00: Div1, 01:Div2, 10: Div4, 11: Div16
Valid
Valid
Valid
Valid
0: Auto Power-On (if any CNT/DLY use
LPOSC source)
Force LPOSC Oscillator ON
1: Force Power-On
00: Div1
01: Div2
10: Div4
11: Div8
1292:1291
OSC Clock Pre-divider
Valid
Valid
0: Disable
1: Enable
1293
1294
OSC Fast Start-Up Enable
Valid
Valid
Valid
Valid
Oscillator (25kHz: RC-OSC, 2M: RC-OSC) 0: 25 kHz RC-OSC
Select
1: 2 MHz RC-OSC
0:Auto Power-On (if any CNT/DLYuse25K
source)
1295
Force Oscillator ON
Valid
Valid
1: Force Power-On
000: OSC/1
001: OSC/2
010: OSC/3
011: OSC/4
100: OSC/8
101: OSC/12
110: OSC/24
111: OSC/64
Internal OSC 25 kHz Frequency Divider
Control for matrix input [28]
1298:1296
1299
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
OSC Clock 25 kHz to matrix input [28] en- 0: Disable
able
1: Enable
000: OSC/1
001: OSC/2
010: OSC/3
011: OSC/4
100: OSC/8
101: OSC/12
110: OSC/24
111: OSC/64
Internal OSC 25 kHz Frequency Divider
Control for matrix input [27]
1302:1300
1303
OSC Clock 25 kHz to matrix input [27] en- 0: Disable
able
1: Enable
IO3
0: Non-inverted
1: Inverted
1304
1305
1306
1307
IO3 reset level polarity selection
IO3 reset bypass selection
IO3 reset edge selection
IO3 reset enable
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
0: Edge selection
1: Level selection
0: Rising edge
1: Falling edge
0: Disable
1: Enable
00: Rising Edge Detector
Select the Edge Mode of Programmable De- 01: Falling Edge Detector
1309:1308
Valid
Valid
lay & Edge Detector
10: Both Edge Detector
11: Both Edge Delay
Datasheet
18-Sep-2019
Revision 3.3
187 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 103: Register Map (Continued)
I2C Interface
Register Bit
Address
Signal Function
Register Bit Definition
I2C Read I2C Write
00: 165 ns
Delay Value Select for Programmable Delay 01: 300 ns
1311:1310
Valid
Valid
& Edge Detector (VDD = 3.3 V, typical)
10: 440 ns
11: 575 ns
ASM
ASM_reg_init[2:0] for ASM state default set-
up bits
1314:1312
Valid
Valid
1319:1315
1322:1320
1323
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
ASM_state0_dec8x1_EN1
Reserved
1326:1324
1327
ASM_state0_dec8x1_EN0
Reserved
1330:1328
1331
ASM_state1_dec8x1_EN0
Reserved
1334:1332
ASM_state0_dec8x1_EN2
ASM Rising Edge Detect Enable on EN2 of 0: Disable
1335
1338:1336
1339
Valid
Valid
Valid
Valid
Valid
Valid
state0
1: Enable
ASM_state1_dec8x1_EN2
ASM Rising Edge Detect Enable on EN2 of 0: Disable
state1
1: Enable
1342:1340
1343
ASM_state1_dec8x1_EN1
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
1346:1344
1347
ASM_state2_dec8x1_EN1
Reserved
1350:1348
1351
ASM_state2_dec8x1_EN0
Reserved
1354:1352
1355
ASM_state3_dec8x1_EN0
Reserved
1358:1356
ASM_state2_dec8x1_EN2
ASM Rising Edge Detect Enable on EN2 of 0: Disable
1359
1362:1360
1363
Valid
Valid
Valid
Valid
Valid
Valid
state2
1: Enable
ASM_state3_dec8x1_EN2
ASM Rising Edge Detect Enable on EN2 of 0: Disable
state3
1: Enable
1366:1364
1367
ASM_state3_dec8x1_EN1
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
1370:1368
1371
ASM_state4_dec8x1_EN1
Reserved
1374:1372
1375
ASM_state4_dec8x1_EN0
Reserved
1378:1376
1379
ASM_state5_dec8x1_EN0
Reserved
1382:1380
ASM_state4_dec8x1_EN2
Datasheet
18-Sep-2019
Revision 3.3
188 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 103: Register Map (Continued)
I2C Interface
Register Bit
Address
Signal Function
Register Bit Definition
I2C Read I2C Write
ASM Rising Edge Detect Enable on EN2 of 0: Disable
1383
1386:1384
1387
Valid
Valid
Valid
Valid
Valid
Valid
state4
1: Enable
ASM_state5_dec8x1_EN2
ASM Rising Edge Detect Enable on EN2 of 0: Disable
state5
1: Enable
1390:1388
1391
ASM_state5_dec8x1_EN1
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
1394:1392
1395
ASM_state6_dec8x1_EN1
Reserved
1398:1396
1399
ASM_state6_dec8x1_EN0
Reserved
1402:1400
1403
ASM_state7_dec8x1_EN0
Reserved
1406:1404
ASM_state6_dec8x1_EN2
ASM Rising Edge Detect Enable on EN2 of 0: Disable
1407
1410:1408
1411
Valid
Valid
Valid
Valid
Valid
Valid
state6
1: Enable
ASM_state7_dec8x1_EN2
ASM Rising Edge Detect Enable on EN2 of
state7
1414:1412
1415
ASM_state7_dec8x1_EN1
Reserved
Valid
Valid
Valid
Valid
Filter/Edge Detector
00: Rising Edge
01: Falling Edge
10: Both Edge
11: Delay
1417:1416
Select the edge mode of Edge Detector_1
Valid
Valid
Filter_1/Edge Detector_1 output Polarity Se- 0: Filter_1 output
1418
1419
Valid
Valid
Valid
Valid
lect
1: Filter_1 output inverted
Filter_1 (Typ. 50nS @VDD = 3.3 V) or Edge
Detector_1 (Typ. 125nS @VDD = 3.3 V) Se-
lect
0: Filter_1
1: Edge Detector_1
00: Rising Edge
01: Falling Edge
10: Both Edge
11: Delay
1421:1420
Select the edge mode of Edge Detector_0
Valid
Valid
Filter_0/Edge Detector_0 output Polarity Se- 0: Filter_0 output
1422
1423
Valid
Valid
Valid
Valid
lect
1: Filter_0 output inverted
Filter_0 (Typ. 70 ns @VDD = 3.3 V) or Edge
Detector_0 Select (Typ. 125 ns @
VDD=3.3 V)
0: Filter_0
1: Edge Detector_0
Vref/Bandgap
1424
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
1426:1425
1427
Reserved
Reserved
0: Disable
1: Enable
1428
Vref Op Amp Offset Chopper Enable
Datasheet
18-Sep-2019
Revision 3.3
189 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 103: Register Map (Continued)
I2C Interface
Register Bit
Address
Signal Function
Register Bit Definition
I2C Read I2C Write
Reserved
0: Disable
1: Enable
1429
Valid
Valid
Valid
Valid
Valid
Valid
0: 2 MHz
1: 1 MHz
1430
1431
Reserved
0: Disable
1: Enable
Two consecutive DFFs enable for ASM
100: CP Auto ON/OFF (Use for
1.71 V<VDD<5.5 V)
CP function selection & Power divider (VDD/ X10: CP always OFF (Use for 2.7 V<VDD),
1434:1432
Valid
Valid
Valid
3, VDD/4) ON/OFF
XX1: CP always ON (Use for VDD<2.7 V)
0XX: Power divider off (if there is no use of
VDD/3,VDD/4 @ACMP negative in)
1435
1436
Reserved
Valid
Valid
0: Auto-Mode
1: Enable (if chip is Power-Down, the Band- Valid
Force Bandgap ON
gap will Power-Down even if it is Set to 1).
0: None (Or Programming Enable)
Valid
1437
1438
1439
NVM Power-Down
Reserved
Valid
Valid
Valid
1: Power-Down (Or Programming Disable)
Valid
0: Disable
1: Enable
GPIO Quick Charge Enable
Valid
Wake/Sleep
1440
Reserved
Reserved
Valid
Valid
Valid
Valid
1441
0: Disable
1: Enable
1442
1443
1444
1445
ACMP0 Wake & Sleep function Enable
ACMP1 Wake & Sleep function Enable
ACMP2 Wake & Sleep function Enable
ACMP3 Wake & Sleep function Enable
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
0: Disable
1: Enable
0: Disable
1: Enable
0: Disable
1: Enable
Wake Sleep Output State When WS Oscilla-
tor is Power-Down if DLY/CNT0 Mode Selec-
tion is "11"
0: Low
1: High
1446
1447
Valid
Valid
Valid
Wake Sleep Ratio Control Mode Selection if 0: Default Mode
DLY/CNT0 Mode Selection is "11"
Valid
1: Wake Sleep Ratio Control Mode
LDO
LDO1 PS_Mode_Gate (LDO1 turn-on/off is 0: LDO Mode Enable
1448
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
controlled by LDO1_EN matrix output)
1: Power switch Mode Enable
LDO1 Start-up Ramping Slope Divide
Enable
0: Disable
1: Enable (Div 8 of 1600])
1449
1450
1451
1452
LDO1 Over-current & Short-current
Detection Enable
0: Disable
1: Enable
0: No discharge resistor
1: 300 ohm discharge resistor
LDO1 Discharge resistor Enable
LDO0 PS_Mode_Gate (LDO0 turn-on/off is 0: LDO Mode Enable
controlled by LDO0_EN matrix output) 1: Power switch Mode Gate Enable
Datasheet
18-Sep-2019
Revision 3.3
190 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 103: Register Map (Continued)
I2C Interface
Register Bit
Address
Signal Function
Register Bit Definition
I2C Read I2C Write
LDO0 Start-up Ramping Slope Divide
Enable
0: Disable
1: Enable (Div 8 of [1592])
1453
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
LDO0 Over-current & Short-current
Detection Enable
0: Disable
1: Enable
1454
1455
1456
1457
1458
1459
1460
1461
1462
0: No discharge resistor
1: 300 Ohm discharge resistor
LDO0 Discharge resistor Enable
LDO3 PS_Mode_Gate (LDO3 turn-on/off is 0: LDO Mode Enable
controlled by LDO3_EN matrix output)
1: Power switch Mode Gate Enable
LDO3 Start-up Ramping Slope Divide
Enable
0: Disable
1: Enable (Div 8 of [1616])
LDO3 Over-current & Short-current
Detection Enable
0: Disable
1: Enable
0: No discharge resistor
1: 300 Ω discharge resistor
LDO3 Discharge resistor Enable
LDO2 PS_Mode_Gate (LDO2 turn-on/off is 0: LDO Mode Enable
controlled by LDO2_EN matrix output)
1: Power switch Mode Gate Enable
LDO2 Start-up Ramping Slope Divide
Enable
0: Disable
1: Enable (Div 8 of [1608])
LDO2 Over-current & Short-current
Detection Enable
0: Disable
1: Enable
0: No discharge resistor
1: 300 Ω discharge resistor
1463
LDO2 Discharge resistor Enable
Reserved
Valid
Valid
Valid
Valid
Invalid
Invalid
1465:1464
1467:1466
Reserved
1469:1468
1471:1470
1479:1472
1487:1480
Reserved
Valid
Valid
Valid
Valid
Invalid
Invalid
Invalid
Invalid
Reserved
Reserved Reserved
Reserved
0: Disable
1: Enable
1488
ACMP1 100 µA Current Source Enable
Valid
Valid
1489
1490
Reserved
Reserved
Valid
Valid
Valid
Valid
LDO2 VOUT output connection enable to
ACMP3
0: Default ACMP function
1: Enable LDO2 VOUT function
1491
1492
1493
1494
1495
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
LDO0 VOUT output connection enable to
ACMP3
0: Default ACMP function
1: Enable LDO0 VOUT function
0: Default ACMP function
1: Enable TS function
TS output connection enable to ACMP2
LDO2/3 VIN connection enable to ACMP1
LDO0/1 VIN connection enable to ACMP0
0: Default ACMP function
1: Enable UVLO1 function
0: Default ACMP function
1: Enable UVLO0 function
1496
1497
1498
1499
Reserved
Reserved
Reserved
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Datasheet
18-Sep-2019
Revision 3.3
191 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 103: Register Map (Continued)
I2C Interface
Register Bit
Address
Signal Function
Register Bit Definition
I2C Read I2C Write
1503:1500
1519:1504
1535:1520
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
LUT4x2_0 Output0 [15:0]
LUT4x2_0 Output1 [15:0]
LUT/DLY/CNT Control Data
1 - 255 (Delay Time = [Counter Control
Data + 1]/Freq)
1543:1536
1551:1544
1559:1552
1567:1560
1575:1568
LUT3_6 [7:0] or DLY/CNT0 Control Data
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
1 - 255 (Delay Time = [Counter Control
Data + 1]/Freq)
LUT3_7 [7:0] or DLY/CNT1 Control Data
LUT3_8 [7:0] or DLY/CNT2 Control Data
LUT3_9 [7:0] or DLY/CNT3 Control Data
LUT3_10 [7:0] or DLY/CNT4 Control Data
1 - 255 (Delay Time = [Counter Control
Data + 1]/Freq)
1 - 255 (Delay Time = [Counter Control
Data + 1]/Freq)
1 - 255 (Delay Time = [Counter Control
Data + 1]/Freq)
1577:1576
1579:1578
1581:1580
1583:1582
Reserved
Reserved
Reserved
Reserved
Valid
Valid
Valid
Valid
Invalid
Invalid
Invalid
Invalid
UVLO1_HW_enable (Enable UVLO1 output 0: Disable UVLO1 HW connect
Hard-Wire connection to LDO2/3) 1: Enable UVLO1 HW connect
1584
1585
Valid
Valid
Valid
Valid
UVLO0_HW_enable (Enable UVLO0 output 0: Disable UVLO0 HW connect
Hard-Wire connection to LDO0/1)
1: Enable UVLO0 HW connect
000: 2.5 V
001: 2.8 V
010: 3.0 V
LDO0/1 VDD minimum Power Selection for 011: 3.3 V
1588:1586
1591:1589
Valid
Valid
Valid
Valid
LDO1
100: 3.6 V
101: 3.9 V
110: 4.4 V
111: 4.5 V
000: 2.5 V
001: 2.8 V
010: 3.0 V
LDO0/1 VDD minimum Power Selection for 011: 3.3 V
LDO0
100: 3.6 V
101: 3.9 V
110: 4.4 V
111: 4.5 V
0: 10 V/ms
1: 20 V/ms
1592
LDO0 Start-up Ramping Slope Selection
Reserved
Valid
Valid
Valid
Valid
1594:1593
Datasheet
18-Sep-2019
Revision 3.3
192 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 103: Register Map (Continued)
I2C Interface
Register Bit
Address
Signal Function
Register Bit Definition
I2C Read I2C Write
00000:0.90v, 00001:1.00v, 00010:1.05v,
00011:1.10v, 00100:1.20v, 00101:1.25v,
00110:1.35v, 00111:1.50v, 01000:1.67v,
01001:1.80v, 01010:1.90v, 01011:2.00v,
01100:2.10v, 01101:2.20v, 01110:2.50v,
01111:2.50v, 10000:2.50v, 10001:2.60v,
10010:2.70v, 10011:2.80v, 10100:2.85v,
10101:2.90v, 10110:3.00v, 10111:3.10v,
11000:3.20v, 11001:3.30v, 11010:3.40v,
11011:3.50v, 11100:3.60v, 11101:4.00v,
11110:4.10v, 11111:4.20v
1599:1595
LDO0 Vref Selection
Valid
Valid
0: 10 V/ms
1: 20 V/ms
1600
LDO1 Start-up Ramping Slope Selection
Reserved
Valid
Valid
Valid
Valid
1602:1601
00000:0.90v, 00001:1.00v, 00010:1.05v,
00011:1.10v, 00100:1.20v, 00101:1.25v,
00110:1.35v, 00111:1.50v, 01000:1.67v,
01001:1.80v, 01010:1.90v, 01011:2.00v,
01100:2.10v, 01101:2.20v, 01110:2.50v,
01111:2.50v, 10000:2.50v, 10001:2.60v,
10010:2.70v, 10011:2.80v, 10100:2.85v,
10101:2.90v, 10110:3.00v, 10111:3.10v,
11000:3.20v, 11001:3.30v, 11010:3.40v,
11011:3.50v, 11100:3.60v, 11101:4.00v,
11110:4.10v, 11111:4.20v
1607:1603
LDO1 Vref Selection
Valid
Valid
0: 10 V/ms
1: 20 V/ms
1608
LDO2 Start-up Ramping Slope Selection
Reserved
Valid
Valid
Valid
Valid
1610:1609
00000:0.90v, 00001:1.00v, 00010:1.05v,
00011:1.10v, 00100:1.20v, 00101:1.25v,
00110:1.35v, 00111:1.50v, 01000:1.67v,
01001:1.80v, 01010:1.90v, 01011:2.00v,
01100:2.10v, 01101:2.20v, 01110:2.50v,
01111:2.50v, 10000:2.50v, 10001:2.60v,
10010:2.70v, 10011:2.80v, 10100:2.85v,
10101:2.90v, 10110:3.00v, 10111:3.10v,
11000:3.20v, 11001:3.30v, 11010:3.40v,
11011:3.50v, 11100:3.60v, 11101:4.00v,
11110:4.10v, 11111:4.20v
1615:1611
LDO2 Vref Selection
Valid
Valid
0: 10 V/ms
1: 20 V/ms
1616
LDO3 Start-up Ramping Slope Selection
Reserved
Valid
Valid
Valid
Valid
1618:1617
00000:0.90v, 00001:1.00v, 00010:1.05v,
00011:1.10v, 00100:1.20v, 00101:1.25v,
00110:1.35v, 00111:1.50v, 01000:1.67v,
01001:1.80v, 01010:1.90v, 01011:2.00v,
01100:2.10v, 01101:2.20v, 01110:2.50v,
01111:2.50v, 10000:2.50v, 10001:2.60v,
10010:2.70v, 10011:2.80v, 10100:2.85v,
10101:2.90v, 10110:3.00v, 10111:3.10v,
11000:3.20v, 11001:3.30v, 11010:3.40v,
11011:3.50v, 11100:3.60v, 11101:4.00v,
11110:4.10v, 11111:4.20v
1623:1619
LDO3 Vref Selection
Valid
Valid
Datasheet
18-Sep-2019
Revision 3.3
193 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 103: Register Map (Continued)
I2C Interface
Register Bit
Address
Signal Function
Register Bit Definition
I2C Read I2C Write
ACMP0
00000: 50 mV
00010: 150 mV
00100: 250 mV
00110: 350 mV
01000: 450 mV
01010: 550 mV
01100: 650 mV
01110: 750 mV
10000: 850 mV
10010: 950 mV
10100: 1.05 V
10110: 1.15 V
00001: 100 mV
00011: 200 mV
00101: 300 mV
00111: 400 mV
01001: 500 mV
01011: 600 mV
01101: 700 mV
01111: 800 mV
10001: 900 mV
10011: 1 V
1628:1624
ACMP0- IN Voltage Select
Valid
Valid
10101: 1.1 V
10111: 1.2 V
11000: VDD: ACMP0- /3
11001: VDD: ACMP0- /4
11010: IO4: EXT_Vref
11011: IO4: EXT_Vref /2
00: 1.0x
01: 0.5x
10: 0.33x
11: 0.25x
1630:1629
1631
ACMP0 Positive Input Divider
Valid
Valid
Valid
Valid
ACMP0 Low Bandwidth (MAX: 1MHz) En- 0: OFF
able
1:ON
ACMP1
00000: 50 mV
00010: 150 mV
00100: 250 mV
00110: 350 mV
01000: 450 mV
01010: 550 mV
01100: 650 mV
01110: 750 mV
10000: 850 mV
10010: 950 mV
10100: 1.05 V
10110: 1.15 V
00001: 100 mV
00011: 200 mV
00101: 300 mV
00111: 400 mV
01001: 500 mV
01011: 600 mV
01101: 700 mV
01111: 800 mV
10001: 900 mV
10011: 1 V
1636:1632
ACMP1-IN Voltage Select
Valid
Valid
10101: 1.1 V
10111: 1.2 V
11000: VDD: ACMP1- /3
11001: VDD: ACMP1- /4
11010: IO4: EXT_Vref
11011: IO4: EXT_Vref /2
00: 1.0x
01: 0.5x
10: 0.33x
11: 0.25x
1638:1637
1639
ACMP1 Positive Input Divider
Valid
Valid
Valid
Valid
ACMP1 Low Bandwidth (MAX: 1MHz) En- 0: OFF
able
1: ON
Datasheet
18-Sep-2019
Revision 3.3
194 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 103: Register Map (Continued)
I2C Interface
Register Bit
Address
Signal Function
Register Bit Definition
I2C Read I2C Write
ACMP2
00000: 50 mV
00010: 150 mV
00100: 250 mV
00110: 350 mV
01000: 450 mV
01010: 550 mV
01100: 650 mV
01110: 750 mV
10000: 850 mV
10010: 950 mV
10100: 1.05 V
10110: 1.15 V
00001: 100 mV
00011: 200 mV
00101: 300 mV
00111: 400 mV
01001: 500 mV
01011: 600 mV
01101: 700 mV
01111: 800 mV
10001: 900 mV
10011: 1 V
1644:1640
ACMP2-IN Voltage Select
Valid
Valid
10101: 1.1 V
10111: 1.2 V
11000: VDD: ACMP2- /3
11001: VDD: ACMP2- /4
11010: IO4: EXT_Vref
11011: IO4: EXT_Vref /2
00: 1.0x
01: 0.5x
10: 0.33x
11: 0.25x
1646:1645
1647
ACMP2 Positive Input Divider
Valid
Valid
Valid
Valid
ACMP2 Low Bandwidth (MAX: 1MHz) En- 0: OFF
able
1: ON
ACMP3
00000: 50 mV
00010: 150 mV
00100: 250 mV
00110: 350 mV
01000: 450 mV
01010: 550 mV
01100: 650 mV
01110: 750 mV
10000: 850 mV
10010: 950 mV
10100: 1.05 V
10110: 1.15 V
00001: 100 mV
00011: 200 mV
00101: 300 mV
00111: 400 mV
01001: 500 mV
01011: 600 mV
01101: 700 mV
01111: 800 mV
10001: 900 mV
10011: 1 V
1652:1648
ACMP3-IN Voltage Select
Valid
Valid
10101: 1.1 V
10111: 1.2 V
11000: VDD: ACMP3- /3
11001: VDD: ACMP3- /4
11010: IO4: EXT_Vref
11011: IO4: EXT_Vref /2
00: 1.0x
01: 0.5x
10: 0.33x
11: 0.25x
1654:1653
1655
ACMP3 Positive Input Divider
Valid
Valid
Valid
Valid
ACMP3 Low Bandwidth (MAX: 1MHz) En- 0: OFF
able 1: ON
Misc.
TS_HW_enable (Enable Temp sensor out- 0: Disable TS HW connect
1656
1657
Valid
Valid
Valid
Valid
put Hard-Wire connection to LDO0/1/2/3)
1: Enable TS HW connect
Switch from “Matrix OUT: LPOSC PD” to
“Matrix OUT: LPOSC Force On”
0: OSC PD
1: OSC Force On (Matrix Output [60])
Datasheet
18-Sep-2019
Revision 3.3
195 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 103: Register Map (Continued)
I2C Interface
Register Bit
Address
Signal Function
Register Bit Definition
I2C Read I2C Write
Switchfrom“Matrix OUT:OSC25KHz/2MHz
PD” to “Matrix OUT: OSC 25KHz/2MHz
Force On”
0: OSC PD
1: OSC Force On (Matrix Output [59])
1658
Valid
Valid
1659
1660
1661
Reserved
Reserved
Reserved
Valid
Valid
Valid
Invalid
Invalid
Invalid
I2C reset bit with reloading NVM into Data 0: Keep existing condition
register 1: Reset execution
IO Latching Enable During I2C Write Inter- 0: Disable
1662
1663
Valid
Valid
Valid
Invalid
face
1: Enable
1671:1664
1679:1672
1687:1680
1695:1688
1703:1696
1711:1704
1719:1712
1727:1720
1735:1728
1743:1736
1751:1744
1759:1752
1767:1760
1775:1768
1783:1776
1791:1784
RAM 8 outputs for ASM-state0
RAM 8 outputs for ASM-state1
RAM 8 outputs for ASM-state2
RAM 8 outputs for ASM-state3
RAM 8 outputs for ASM-state4
RAM 8 outputs for ASM-state5
RAM 8 outputs for ASM-state6
RAM 8 outputs for ASM-state7
User configurable RAM/OTP Byte 0
User configurable RAM/OTP Byte 1
User configurable RAM/OTP Byte 2
User configurable RAM/OTP Byte 3
User configurable RAM/OTP Byte 4
User configurable RAM/OTP Byte 5
User configurable RAM/OTP Byte 6
User configurable RAM/OTP Byte 7
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
LDO0_EN_Gate (By this bit = 1, Matrix Out- 0: Disable
1792
1793
Valid
Valid
Valid
Valid
put: LDO0_EN will be enabled.)
1: Enable
0: Default VOUT selection
1: Enable 2nd VOUT selection
LDO0 VOUT_SEL_Gate
Mode1_EN_Gate (By this bit = 1, Matrix Out- 0: Disable LDO_LP_MODE_EN matrix out-
put: LDO MODE1_Enable for LDO0/1/2/3 put 1: Enable LDO_LP_MODE_ EN matrix
1794
Valid
Valid
will be enabled.)
output
00000:0.90v, 00001:1.00v, 00010:1.05v,
00011:1.10v, 00100:1.20v, 00101:1.25v,
00110:1.35v, 00111:1.50v, 01000:1.67v,
01001:1.80v, 01010:1.90v, 01011:2.00v,
01100:2.10v, 01101:2.20v, 01110:2.50v,
01111:2.50v, 10000:2.50v, 10001:2.60v,
10010:2.70v, 10011:2.80v, 10100:2.85v,
10101:2.90v, 10110:3.00v, 10111:3.10v,
11000:3.20v, 11001:3.30v, 11010:3.40v,
11011:3.50v, 11100:3.60v, 11101:4.00v,
11110:4.10v, 11111:4.20v
1799:1795
LDO0 2nd Vref Selection
Valid
Valid
Valid
Valid
LDO1_EN_Gate (By this bit = 1, Matrix Out- 0: Disable
put: LDO1_EN will be enabled.) 1: Enable
1800
Datasheet
18-Sep-2019
Revision 3.3
196 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 103: Register Map (Continued)
I2C Interface
Register Bit
Address
Signal Function
Register Bit Definition
I2C Read I2C Write
0: Default VOUT selection
1: Enable 2nd VOUT selection
1801
1802
LDO1 VOUT_SEL_Gate
Reserved
Valid
Valid
Valid
Valid
00000:0.90v, 00001:1.00v, 00010:1.05v,
00011:1.10v, 00100:1.20v, 00101:1.25v,
00110:1.35v, 00111:1.50v, 01000:1.67v,
01001:1.80v, 01010:1.90v, 01011:2.00v,
01100:2.10v, 01101:2.20v, 01110:2.50v,
01111:2.50v, 10000:2.50v, 10001:2.60v,
10010:2.70v, 10011:2.80v, 10100:2.85v,
10101:2.90v, 10110:3.00v, 10111:3.10v,
11000:3.20v, 11001:3.30v, 11010:3.40v,
11011:3.50v, 11100:3.60v, 11101:4.00v,
11110:4.10v, 11111:4.20v
1807:1803
LDO1 2nd Vref Selection
Valid
Valid
LDO2_EN_Gate (By this bit = 1, Matrix Out-
put: LDO2_EN will be enabled.)
1808
0: Disable 1: Enable
Valid
Valid
0: Default VOUT selection
1: Enable 2nd VOUT selection
1809
1810
LDO2 VOUT_SEL_Gate
Reserved
Valid
Valid
Valid
Valid
00000:0.90v, 00001:1.00v, 00010:1.05v,
00011:1.10v, 00100:1.20v, 00101:1.25v,
00110:1.35v, 00111:1.50v, 01000:1.67v,
01001:1.80v, 01010:1.90v, 01011:2.00v,
01100:2.10v, 01101:2.20v, 01110:2.50v,
01111:2.50v, 10000:2.50v, 10001:2.60v,
10010:2.70v, 10011:2.80v, 10100:2.85v,
10101:2.90v, 10110:3.00v, 10111:3.10v,
11000:3.20v, 11001:3.30v, 11010:3.40v,
11011:3.50v, 11100:3.60v, 11101:4.00v,
11110:4.10v, 11111:4.20v
1815:1811
LDO2 2nd Vref Selection
Valid
Valid
LDO3_EN_Gate (By this bit = 1, Matrix Out- 0: Disable
1816
Valid
Valid
put: LDO3_EN will be enabled.)
LDO3 VOUT_SEL_Gate
Reserved
1: Enable
0: Default VOUT selection
1: Enable 2nd VOUT selection
1817
1818
Valid
Valid
Valid
Valid
00000:0.90v, 00001:1.00v, 00010:1.05v,
00011:1.10v, 00100:1.20v, 00101:1.25v,
00110:1.35v, 00111:1.50v, 01000:1.67v,
01001:1.80v, 01010:1.90v, 01011:2.00v,
01100:2.10v, 01101:2.20v, 01110:2.50v,
01111:2.50v, 10000:2.50v, 10001:2.60v,
10010:2.70v, 10011:2.80v, 10100:2.85v,
10101:2.90v, 10110:3.00v, 10111:3.10v,
11000:3.20v, 11001:3.30v, 11010:3.40v,
11011:3.50v, 11100:3.60v, 11101:4.00v,
11110:4.10v, 11111:4.20v
1823:1819
LDO3 2nd Vref Selection
Valid
Valid
1831:1824
1832
Reserved
Valid
Valid
Valid
0: Disable (Programmeddata can be read.)
1: Enable (Programmed data can't be
read.)
NVMDataReadDisable(FromNVM):ID[24]
for BANK0/1/2 only
Invalid
Reserved
1833
1835:1834
Datasheet
Valid
Valid
Invalid
Invalid
Reserved Reserved
18-Sep-2019
Revision 3.3
197 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 103: Register Map (Continued)
I2C Interface
Register Bit
Address
Signal Function
Register Bit Definition
I2C Read I2C Write
1839:1836
Reserved
Valid
Invalid
8-bit Pattern ID Byte 0 (From NVM):
ID[23:16]
1847:1840
Valid
Valid
1855:1848
1863:1856
1867:1864
Reserved
Valid
Valid
Valid
Invalid
Invalid
Invalid
Reserved
I2C Control Code Bit [3:0]
Value for slave address
0: Up to 400 kHz
1: 1 MHz operation
1868
1869
1870
I2C 1 MHz operation enable
Reserved
Valid
Valid
Valid
Invalid
Invalid
Invalid
0: Writable
1: Non-writable
BANK0/1/2/3 I2C-write protection bit
0: Writable
1: Non-writable
1871
1872
BANK0/1/2 I2C-write protection bit
Reserved
Valid
Invalid
Invalid
Invalid
00: 2.5 A
10: 2.0 A
SEL_OCP[1:0] for Synchronous DC/DC
Step Down Converter control
1874:1873
Invalid
Invalid
00: 1.5 MHz
01: 2.0 MHz
10: Reserved
11: Reserved
SEL_FSW[1:0] for Synchronous DC/DC
Step Down Converter control
1876:1875
Invalid
Invalid
000: 1.2 V
001: 1.5 V
010: 1.8 V
SEL_VO[2:0] for Synchronous DC/DC Step 011: 2.5 V
1879:1877
Invalid
Invalid
Down Converter control
100: 3.0 V
101: 3.3 V
110: Reserved
111: Reserved
1880
Reserved
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
1881
Reserved
1882
Reserved
1887:1883
1891:1888
1895:1892
1899:1896
1903:1900
1904
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1905
Reserved
1907:1906
1911:1908
1919:1912
Reserved
Reserved
ASM State output [7:0]
Matrix Input
1920
Matrix Input 0
Matrix Input 1
Matrix Input 2
VSS
Valid
Valid
Valid
Invalid
Invalid
Invalid
1921
IO0 Digital Input
IO1 Digital Input
1922
Datasheet
18-Sep-2019
Revision 3.3
198 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 103: Register Map (Continued)
I2C Interface
Register Bit
Address
Signal Function
Register Bit Definition
I2C Read I2C Write
SynchronousDC/DCStepDownConverter
Fault B
1923
Matrix Input 3
Valid
Invalid
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
Matrix Input 4
Matrix Input 5
Matrix Input 6
Matrix Input 7
Matrix Input 8
Matrix Input 9
Matrix Input 10
Matrix Input 11
Matrix Input 12
Matrix Input 13
Matrix Input 14
Matrix Input 15
Matrix Input 16
Matrix Input 17
Matrix Input 18
VSS
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
IO2 Digital Input
LUT2_0/DFF0 Output
LUT2_1/DFF1 Output
LUT2_2/DFF2 Output
LUT3_0/DFF3 Output
LUT3_1/DFF4 Output
LUT3_2/DFF5 Output
LUT3_3/DFF6 Output
LUT3_4/DFF7 Output
LUT3_6/CNT_DLY0(8bit) Output
LUT3_7/CNT_DLY1(8bit) Output
LUT3_8/CNT_DLY2(8bit) Output
LUT3_9/CNT_DLY3(8bit) Output
LUT3_10/CNT_DLY4(8bit) Output
LUT3_11/Pipe Delay (1st stage) Output/
Ripple counter Q[0]
1939
Matrix Input 19
Valid
Invalid
1940
1941
1942
1943
1944
1945
1946
Matrix Input 20
Matrix Input 21
Matrix Input 22
Matrix Input 23
Matrix Input 24
Matrix Input 25
Matrix Input 26
LUT3_5/DFF8 Output
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
LUT4X2 Output0
LUT4X2 Output1
RTC CNT 1 second Output
RTC DCOMP Output
Pipe Delay Output0/Ripple counter Q[1]
Pipe Delay Output1/Ripple counter Q[2]
Internal OSC Post-Divided by 1/2/3/4/8/12/
24/64 Output (25KHz/2MHz)
1947
Matrix Input 27
Valid
Invalid
Internal OSC Post-Divided by 1/2/3/4/8/12/
24/64 Output (25KHz/2MHz)
1948
1949
Matrix Input 28
Matrix Input 29
Valid
Valid
Invalid
Invalid
LPOSC Output
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
Matrix Input 30
Matrix Input 31
Matrix Input 32
Matrix Input 33
Matrix Input 34
Matrix Input 35
Matrix Input 36
Matrix Input 37
Matrix Input 38
Matrix Input 39
Filter0/Edge Detect0 Output
Filter1/Edge Detect1 Output
I2C_virtual_0 Input
I2C_virtual_1 Input
I2C_virtual_2 Input
I2C_virtual_3 Input
I2C_virtual_4 Input
I2C_virtual_5 Input
I2C_virtual_6 Input
I2C_virtual_7 Input
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Invalid
Invalid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Datasheet
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Revision 3.3
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© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Table 103: Register Map (Continued)
I2C Interface
Register Bit
Address
Signal Function
Register Bit Definition
I2C Read I2C Write
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
Matrix Input 40
Matrix Input 41
Matrix Input 42
Matrix Input 43
Matrix Input 44
Matrix Input 45
Matrix Input 46
Matrix Input 47
Matrix Input 48
Matrix Input 49
Matrix Input 50
Matrix Input 51
Matrix Input 52
Matrix Input 53
Matrix Input 54
Matrix Input 55
Matrix Input 56
Matrix Input 57
Matrix Input 58
Matrix Input 59
Matrix Input 60
RAM_0 Output for ASM-state
RAM_1 Output for ASM-state
RAM_2 Output for ASM-state
RAM_3 Output for ASM-state
RAM_4 Output for ASM-state
RAM_5 Output for ASM-state
RAM_6 Output for ASM-state
RAM_7 Output for ASM-state
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
LDO0 FAULTB
LDO1 FAULTB
LDO2 FAULTB
LDO3 FAULTB
IO3 Digital Input (GPI)
IO4 Digital Input
IO5 Digital Input
IO6 Digital Input
ACMP_0 Output
ACMP_1 Output
ACMP_2 Output
ACMP_3 Output
Programmable Delay with Edge Detector
Output
1981
Matrix Input 61
Valid
Invalid
1982
1983
Matrix Input 62
Matrix Input 63
nRST_core as matrix input
VDD
Valid
Valid
Invalid
Invalid
Reserved
1991:1984
1999:1992
2007:2000
2015:2008
2023:2016
2031:2024
2032
Reserved
Reserved
Reserved
Reserved
Reserved
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Invalid
Invalid
Invalid
Valid
Invalid
Invalid
Valid
Reserved
2033
Valid
2034
Reserved
Reserved
Reserved
Reserved
Valid
2035
Invalid
Valid
2039:2036
2047:2040
Valid
Datasheet
18-Sep-2019
Revision 3.3
200 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
23 Package Top Marking System Definition
23.1 MSTQFN 29L 3 MM X 3 MM X 0.55 MM 0.4P PACKAGE
Part Code
PPPPP
WWWNN
Date Code + S/N Code
Assembly Code
+ Revision Code
ARR
Pin 1 Identifier
Datasheet
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Revision 3.3
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© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
24 Package Information
24.1 PACKAGE OUTLINES FOR MSTQFN 29L 3 MM X 3 MM 0.4P FC PACKAGE
JEDEC MO-220, Variation WECE
Marking View
BTM View
Side view
Datasheet
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Revision 3.3
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© 2019 Dialog Semiconductor
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
24.2 MSTQFN HANDLING
Be sure to handle MSTQFN package only in a clean, ESD-safe environment. Tweezers or vacuum pick-up tools are suitable for
handling. Do not handle MSTQFN package with fingers as this can contaminate the package pins and interface with solder reflow.
24.3 SOLDERING INFORMATION
Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 3.85 mm3 (nominal). More
information can be found at www.jedec.org.
25 Ordering Information
Part Number
Type
SLG46585M
29-Pin MSTQFN
29-Pin MSTQFN - Tape and Reel (3k units)
SLG46585MTR
25.1 TAPE AND REEL SPECIFICATIONS
Max Units
per Reel per Box
Leader (min)
Length
Trailer (min)
Nominal
Package Size
(mm)
Reel &
Hub Size
(mm)
Tape
Width Pitch
(mm) (mm)
Part
Package # of
Length
Type
Pins
Pockets
Pockets
(mm)
(mm)
MSTQFN
29L 3 mm x
3 mm 0.4P
Green
29
3 x 3 x 0.55
5,000
10,000
330/100
42
336
42
336
12
8
25.2 CARRIER TAPE DRAWING AND DIMENSIONS
Pocket
IndexHole IndexHole
to Tape to Pocket
Pocket
Pocket IndexHole Pocket IndexHole
Tape
Width Thickness
(mm)
Tape
BTM
Length
(mm)
BTM Width Depth
Pitch
(mm)
Pitch
(mm)
Diameter
(mm)
Package
Type
Edge
(mm)
Center
(mm)
(mm)
(mm)
(mm)
A0
B0
K0
P0
P1
D0
E
F
W
T
MSTQFN
29L 3 mm
x3 mm
3.3
3.3
0.8
4
8
1.55
1.75
5.5
12
0.3
0.4P Green
Datasheet
18-Sep-2019
Revision 3.3
203 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Refer to EIA-481 specification
Note: Orientation in carrier: Pin1 is at upper left corner (Quadrant 1).
Datasheet
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Revision 3.3
204 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
26 Layout Guidelines
26.1 MSTQFN 29L 3 MM X 3 MM X 0.55 MM 0.4P PACKAGE
Units: µm
Units: µm
Datasheet
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Revision 3.3
205 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Glossary
A
ACK
Acknowledge bit
ACMP
ACMPH
ACMPL
AGND
Analog Comparator
Analog Comparator High Speed
Analog Comparator Low Power
Analog Ground
B
BG
BW
Bandgap
Bandwidth
C
CCM
CLK
CMO
CNT
Continuous Conduction Mode
Clock
Connection matrix output
Counter
D
DCM
DCMP
DFF
DLY
Discontinuous Conduction Mode
Digital Comparator
D Flip-Flop
Delay
E
ESD
ESR
EV
Electrostatic Discharge
Equivalent Series Resistance
End Value
F
FSM
Finite State Machine
G
GPI
GPIO
GPO
General Purpose Input
General Purpose Input/Output
General Purpose Output
H
HP
High Power
I
IN
IQ
IO
Input
Quiescent Current
Input/Output
Datasheet
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Revision 3.3
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© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
L
LBW
LDO
LP
Low Bandwidth
Low Dropout Regulator
Low Power
LPF
LSB
LUT
LV
Low Pass Filter
Least Significant Bit
Look Up Table
Low Voltage
M
MSB
MUX
Most Significant Bit
Multiplexer
N
NPR
nRST
NVM
Non-Volatile Memory Read/Write/Erase Protection
Reset
Non-Volatile Memory
O
OCP
OD
Over-Current Protection
Open-Drain
OE
Output Enable
Oscillator
OSC
OTP
OUT
one time programmable
Output
P
PD
Power-Down
Pattern Generator
Power Ground
Power-On Reset
Push-Pull
PGen
PGND
POR
PP
PWR
P DLY
Power
Programmable Delay
R
R/W
RTC
Read/Write
Real Time Clock
S
SCL
SDA
SLA
SMT
SS
I2C Clock Input
I2C Data Input/Output
Slave Address
With Schmitt Trigger
Soft Start
Datasheet
18-Sep-2019
Revision 3.3
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© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
SV
nSET Value
Switch
SW
T
TC
TS
Case temperature
Temperature Sensor
U
UVLO
Under Voltage Lockout
V
VOSNS
Vref
DC/DC Converter VOUT feedback (sense) input
Voltage Reference
W
WOSMT
WS
Without Schmitt Trigger
Wake and Sleep Controller
Datasheet
18-Sep-2019
Revision 3.3
208 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Revision History
Revision
Date
Description
Added graphs in subsection Oscillator Accuracy
Updated 1.73 kHz OSC Frequency Limits and Errors
Corrected Low Power Oscillator frequency
Added section ACMP Typical Performance
Table Gain Divider Input Resistance added to section Analog Comparators
Updated according to new template
3.3
18-Sept-2018
Corrected LDO mode name
Updated according to Dialog’s Writing Guideline
Fixed typos
Corrected list of Pins connected to appropriate Power rails
Fixed typos
Added new subsection Electrostatic Discharge Ratings
Added Parameter Short Circuit Protection
Updated Registers Read/Write Protection Options
3.2
15-Mar-2018
Updated LDO Typical Application Performance
Updated Oscillator Power-On Delay graphs
Updated after review
3.1
3.0
17-Dec-2018
22-Nov-2018
Added new subsection LDO efficiency
Final version
Datasheet
18-Sep-2019
Revision 3.3
209 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
SLG46585
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine, LDOs, and DC/DC Converter
Status Definitions
Revision Datasheet Status
Product Status
Definition
1.<n>
Target
Development
This datasheet contains the design specifications for product development.
Specifications may change in any manner without notice.
2.<n>
Preliminary
Qualification
Production
This datasheet contains the specifications and preliminary characterization
data for products in pre-production. Specifications may be changed at any
time without notice in order to improve the design.
3.<n>
4.<n>
Final
This datasheet contains the final specifications for products in volume
production. The specifications may be changed at any time in order to
improve the design, manufacturing and supply. Major specification
changes are communicated via Customer Product Notifications. Datasheet
changes are communicated via www.dialog-semiconductor.com.
Obsolete
Archived
This datasheet contains the specifications for discontinued products. The
information is provided for reference only.
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Unless otherwise agreed in writing, the Dialog Semiconductor products (and any associated software) referred to in this document are not designed, authorized or warranted
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Datasheet
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Revision 3.3
210 of 210
© 2019 Dialog Semiconductor
CFR0011-120-00
相关型号：
SLG46585M
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous State Machine, LDOs, and DC/DC Converter
DIALOG
SLG46585MTR
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous State Machine, LDOs, and DC/DC Converter
DIALOG
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