SLG46811V_技术文档

SLG46811

GreenPAK Programmable Mixed-Signal Matrix

General Description

The SLG46811 provides a small, low power component for commonly used Mixed-Signal functions. The user creates their

circuit design by programming the one time programmable (OTP) Non-Volatile Memory (NVM) to configure the interconnect

logic, the IO Pins, and the macrocells of the SLG46811. This highly versatile device allows a wide variety of Mixed-Signal

functions to be designed within a very small, low power single integrated circuit.

Key Features



Multichannel Sampling Analog Comparator (MS ACMP)



Two Oscillators (OSC)



Sampling up to Four Analog Channels

Selectable Voltage Reference for Each Channel

Different Sampling Scenarios



Selectable 2.048 kHz or 10 kHz Oscillator

25 MHz Oscillator



Analog Temperature Sensor

Power-On Reset (POR) with CRC

Read Back Protection (Read Lock)

Power Supply

Synchronous or Asynchronous Result Appearance



Integrated Voltage References (Vref)

Twelve Combination Function Macrocells



Two 2-Bit LUT or DFF/LATCH Macrocells

One Selectable Programmable Pattern Generator or 2-

bit LUT

Four 3-Bit LUT or DFF/LATCH with Set/Reset

Four Selectable DFF/LATCH or 3-bit LUTs or Shift

Registers

 2.3 V ≤ V_DD≤ 5.5 V



Operating Temperature Range: -40 °C to 85 °C

RoHS Compliant/Halogen-Free

Available Package



12-pin STQFN: 1.6 mm x 1.6 mm x 0.55 mm, 0.4 mm

pitch



One 4-Bit LUT or DFF/LATCH with Set/Reset Macro-

cell



Six Multi-Function Macrocells



Five Selectable DFF/LATCH or 3-bit LUTs + 8-bit

Delay/Counters



One Selectable DFF/LATCH or 3-bit LUTs + 8-bit

Delay/Counter/FSM



Extended Pattern Generator



Up to 8 Parallel Outputs



92 bytes Pattern Stored in the NVM

Serial Communications



I²C Protocol Interface



Programmable Delay with Edge Detector Output

Deglitch Filter or Edge Detector

Applications



Notebook and Tablet PCs

Smartphones and Fitness Bands

Personal Computers and Servers

PC Peripherals

Consumer Electronics

Data Communications Equipment

Handheld and Portable Electronics

Datasheet

14-Apr-2021

Revision 3.0

1 of 171

CFR0011-120-00

SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Contents

General Description.................................................................................................................................................................1

Key Features.............................................................................................................................................................................1

Applications..............................................................................................................................................................................1

1 Block Diagram ......................................................................................................................................................................7

2 Pinout ....................................................................................................................................................................................8

2.1 Pin Configuration - STQFN- 12 ..............................................................................................................................8

3 Characteristics ...................................................................................................................................................................11

3.1 Absolute Maximum Ratings .................................................................................................................................11

3.2 Electrostatic Discharge Ratings ...........................................................................................................................11

3.3 Recommended Operating Conditions .................................................................................................................11

3.4 Electrical Characteristics ......................................................................................................................................12

3.5 I²C Pins Electrical Characteristics ........................................................................................................................14

3.6 Macrocells Current Consumption .........................................................................................................................17

3.7 Timing Characteristics ..........................................................................................................................................17

3.8 Counter/Delay Characteristics .............................................................................................................................19

3.9 Oscillator Characteristics .....................................................................................................................................20

3.10 MS ACMP Characteristics ..................................................................................................................................20

3.11 Analog Temperature Sensor Characteristics .....................................................................................................23

4 User Programmability ........................................................................................................................................................24

5 IO Pins .................................................................................................................................................................................25

5.1 GPIO Pins ............................................................................................................................................................25

5.2 GPI Pins ...............................................................................................................................................................25

5.3 Pull-Up/Down Resistors .......................................................................................................................................25

5.4 Fast Pull-up/down during Power-up .....................................................................................................................25

5.5 GPI Structure .......................................................................................................................................................25

5.6 GPIO with I²C Mode IO Structure ........................................................................................................................26

5.7 Matrix OE IO Structure .........................................................................................................................................27

5.8 Register OE IO Structure .....................................................................................................................................28

5.9 IO Typical Performance .......................................................................................................................................29

6 Connection Matrix ..............................................................................................................................................................32

6.1 Matrix Input Table ...............................................................................................................................................33

6.2 Matrix Output Table ..............................................................................................................................................35

6.3 Connection Matrix Virtual Inputs ..........................................................................................................................37

6.4 Connection Matrix Virtual Outputs .......................................................................................................................38

7 Combination Function Macrocells ....................................................................................................................................39

7.1 2-Bit LUT or D Flip-Flop Macrocells .....................................................................................................................39

7.2 2-bit LUT or Programmable Pattern Generator ....................................................................................................41

7.3 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells Or Shift Register Macrocells ...............................................42

7.4 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells .............................................................................................50

7.5 4-Bit LUT or D Flip-Flop with Set/Reset Macrocell ...............................................................................................52

8 Multi-Function Macrocells .................................................................................................................................................55

8.1 3-Bit LUT or DFF/Latch with 8-Bit Counter/Delay Macrocells ..............................................................................55

8.2 CNT/DLY Timing Diagrams ..................................................................................................................................64

8.3 FSM Timing Diagrams .........................................................................................................................................71

9 Multichannel Sampling Analog Comparator ....................................................................................................................72

9.1 Multichannel Sampling ACMP Block Diagram .....................................................................................................73

9.2 MS ACMP Timing Diagrams ................................................................................................................................74

9.3 ACMP Typical Performance .................................................................................................................................76

10 Programmable Delay/Edge Detector ..............................................................................................................................79

10.1 Programmable Delay Timing Diagram - Edge Detector OUTPUT .....................................................................79

11 Additional Logic Function. Deglitch Filter .....................................................................................................................80

12 Voltage Reference ............................................................................................................................................................81

12.1 Voltage Reference Overview .............................................................................................................................81

12.2 Vref Selection Table ...........................................................................................................................................81

13 Clocking ............................................................................................................................................................................82

Datasheet

14-Apr-2021

Revision 3.0

2 of 171

CFR0011-120-00

SLG46811

GreenPAK Programmable Mixed-Signal Matrix

13.1 OSC General description ...................................................................................................................................82

13.2 Oscillator0 (2.048 kHz/10 kHz) ..........................................................................................................................83

13.3 Oscillator1 (25 MHz) ..........................................................................................................................................83

13.4 CNT/DLY Clock Scheme ....................................................................................................................................84

13.5 External Clocking ...............................................................................................................................................84

13.6 Oscillators Power-On Delay ...............................................................................................................................84

13.7 Oscillators Accuracy ...........................................................................................................................................87

13.8 Oscillators Settling Time ....................................................................................................................................89

13.9 Oscillators Current Consumption .......................................................................................................................90

14 Power-On Reset ................................................................................................................................................................92

14.1 General Operation ..............................................................................................................................................92

14.2 POR Sequence ..................................................................................................................................................93

14.3 Macrocells Output States During POR Sequence .............................................................................................93

15 I²C Serial Communications Macrocell ............................................................................................................................96

15.1 I²C Serial Communications Macrocell Overview ................................................................................................96

15.2 I²C Serial Communications Device Addressing .................................................................................................96

15.3 I²C Serial General Timing ..................................................................................................................................97

15.4 I²C Serial Communications Commands .............................................................................................................97

15.5 I²C Serial Command Register Map ..................................................................................................................101

15.6 I²C Additional Options ......................................................................................................................................102

16 Extended Pattern Generator ..........................................................................................................................................104

17 Analog Temperature Sensor .........................................................................................................................................105

18 Register Definitions .......................................................................................................................................................107

18.1 Register Map ....................................................................................................................................................107

19 Package Top Marking Definitions .................................................................................................................................162

19.1 STQFN 12L 1.6 mm x 1.6 mm 0.4P FC, before February 1, 2021 ..................................................................162

19.2 STQFN 12L 1.6 mm x 1.6 mm 0.4P FC, after February 1, 2021 .....................................................................162

20 Package Information ......................................................................................................................................................163

20.1 Package outlines FOR STQFN 12L 1.6 mm x 1.6 mm x 0.55 mm 0.4P FC Package .....................................163

20.2 Moisture Sensitivity Level .................................................................................................................................164

20.3 Soldering Information .......................................................................................................................................164

21 Ordering Information .....................................................................................................................................................164

21.1 Tape and Reel Specifications ..........................................................................................................................164

21.2 Carrier Tape Drawing and Dimensions ............................................................................................................164

22 Layout Guidelines ..........................................................................................................................................................166

22.1 STQFN 12L 1.6 mm x 1.6 mm x 0.55 mm 0.4P FC Package ..........................................................................166

Glossary................................................................................................................................................................................167

Revision History...................................................................................................................................................................170

Datasheet

14-Apr-2021

Revision 3.0

3 of 171

CFR0011-120-00

SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Figures

Figure 1: Block Diagram.............................................................................................................................................................7

Figure 2: Steps to Create a Custom GreenPAK Device...........................................................................................................24

Figure 3: GPI Structure Diagram..............................................................................................................................................25

Figure 4: GPIO with I²C Mode IO Structure Diagram...............................................................................................................26

Figure 5: Matrix OE IO Structure Diagram...............................................................................................................................27

Figure 6: Register OE IO Structure Diagram............................................................................................................................28

Figure 7: Typical High Level Output Current vs. High Level Output Voltage at T = 25 °C.......................................................29

Figure 8: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 °C, Full Range......................29

Figure 9: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 °C .........................................30

Figure 10: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 °C, Full Range....................30

Figure 11: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 °C .......................................31

Figure 12: Connection Matrix...................................................................................................................................................32

Figure 13: Connection Matrix Usage Example.........................................................................................................................32

Figure 14: 2-bit LUT0 or DFF0.................................................................................................................................................39

Figure 15: 2-bit LUT1 or DFF1.................................................................................................................................................40

Figure 16: 2-bit LUT2 or PGen.................................................................................................................................................41

Figure 17: PGen Timing Diagram.............................................................................................................................................42

Figure 18: 3-bit LUT4 or DFF6 or Shift Register 0 ...................................................................................................................43

Figure 19: 3-bit LUT5 or DFF7 or Shift Register 1 ...................................................................................................................44

Figure 20: 3-bit LUT6 or DFF8 or Shift Register 2 ...................................................................................................................44

Figure 21: 3-bit LUT7 or DFF9 or Shift Register 3 ...................................................................................................................45

Figure 22: DFF6 to DFF9 or Shift Register 0 to Shift Register 3 Operation.............................................................................45

Figure 23: DFF6 to DFF9 or Shift Register 0 to Shift Register 3 Operation, nReset Option, DFF Initial Value: 1 ...................46

Figure 24: DFF6 to DFF9 or Shift Register 0 to Shift Register 3 Operation, nReset Option, DFF Initial Value: 1, Case 1......46

Figure 25: DFF6 to DFF9 or Shift Register 0 to Shift Register 3 Operation, nReset Option, DFF Initial Value: 1, Case 2......47

Figure 26: DFF6 to DFF9 or Shift Register 0 to Shift Register 3 Operation, nSet Option, DFF Initial Value: 0 .......................47

Figure 27: DFF6 to DFF9 or Shift Register 0 to Shift Register 3 Operation, nSet Option, DFF Initial Value: 0, Case 1..........48

Figure 28: DFF6 to DFF9 or Shift Register 0 to Shift Register 3 Operation, nSet Option, DFF Initial Value: 0, Case 2..........48

Figure 29: 3-bit LUT0 or DFF2.................................................................................................................................................50

Figure 30: 3-bit LUT1 or DFF3.................................................................................................................................................51

Figure 31: 3-bit LUT2 or DFF4.................................................................................................................................................51

Figure 32: 3-bit LUT3 or DFF5.................................................................................................................................................52

Figure 33: 4-bit LUT0 or DFF16...............................................................................................................................................53

Figure 34: Possible Connections Inside Multi-Function Macrocell...........................................................................................55

Figure 35: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT8/DFF10, CNT/DLY0/FSM)...........................................56

Figure 36: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT9/DFF11, CNT/DLY1) ...................................................57

Figure 37: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT10/DFF12, CNT/DLY2) .................................................58

Figure 38: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT11/DFF13, CNT/DLY3) .................................................59

Figure 39: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT12/DFF14, CNT/DLY4) .................................................60

Figure 40: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT13/DFF15, CNT/DLY5) .................................................61

Figure 41: Delay Mode Timing Diagram, Edge Select: Both, Counter Data: 3 ........................................................................64

Figure 42: Delay Mode Timing Diagram for Different Edge Select Modes...............................................................................65

Figure 43: Counter Mode Timing Diagram without Two DFFs Synced Up ..............................................................................65

Figure 44: Counter Mode Timing Diagram with Two DFFs Synced Up ...................................................................................66

Figure 45: One-Shot Function Timing Diagram........................................................................................................................67

Figure 46: Frequency Detection Mode Timing Diagram...........................................................................................................68

Figure 47: Edge Detection Mode Timing Diagram...................................................................................................................69

Figure 48: Delayed Edge Detection Mode Timing Diagram.....................................................................................................70

Figure 49: Counter Value, Counter Data = 3............................................................................................................................71

Figure 50: CNT/FSM Mode Timing Diagram (Set Rising Edge Mode, Oscillator Is Forced On, UP = 1) for CNT Data = 3 ....71

Figure 51: Multichannel Sampling ACMP Block Diagram ........................................................................................................73

Figure 52: Timing Diagrams for MS ACMP. Edge Sensitive Mode. OSC0 and BG are Forced On.........................................74

Figure 53: Timing Diagrams for MS ACMP. Level Sensitive Mode. OSC0 and BG are Forced On.........................................74

Figure 54: Timing Diagrams for MS ACMP. Level Sensitive Mode. OSC0 is in Auto Power On Mode. BG is Forced On ......75

Figure 55: Typical Propagation Delay vs. Vref for MS ACMP at T = 25 °C, Gain = 1, Hysteresis = 0, Regular Mode ............76

Datasheet

14-Apr-2021

Revision 3.0

4 of 171

CFR0011-120-00

SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Figure 56: MS ACMP Power-On Delay vs. V_DD, Regular Mode ..............................................................................................76

Figure 57: MS ACMP Power-On Delay vs. V_DD, Sampling Mode, T = -40 °C to 85 °C ...........................................................77

Figure 58: MS ACMP Input Offset Voltage vs. Vref at T = -40 °C to 85 °C..............................................................................77

Figure 59: Current Consumption vs. V_DDfor Regular Mode, External Vref, V_IN+= V_DD, V_IN-= GND .....................................78

Figure 60: Current Consumption vs. V_DDfor Sampling Mode, 4 Channels, V_IN+= 2048 mV, V_IN-= 32 mV, Clock = 10 kHz .78

Figure 61: Programmable Delay ..............................................................................................................................................79

Figure 62: Edge Detector Output .............................................................................................................................................79

Figure 63: Deglitch Filter/Edge Detector Simplified Structure..................................................................................................80

Figure 64: Oscillator0 Block Diagram.......................................................................................................................................83

Figure 65: Oscillator1 Block Diagram.......................................................................................................................................83

Figure 66: Clock Scheme.........................................................................................................................................................84

Figure 67: Oscillator Startup Diagram......................................................................................................................................85

Figure 68: Oscillator0 Maximum Power-On Delay vs. V_DDat T = 25 °C, OSC0 = 2.048 kHz/10 kHz .....................................85

Figure 69: Oscillator1 Maximum Power-On Delay vs. V_DDat T = 25 °C, OSC1 = 25 MHz .....................................................86

Figure 70: Oscillator0 Frequency vs. Temperature, OSC0 = 2.048 kHz..................................................................................87

Figure 71: Oscillator0 Frequency vs. Temperature, OSC0 = 10 kHz.......................................................................................87

Figure 72: Oscillator1 Frequency vs. Temperature, OSC1 = 25 MHz......................................................................................88

Figure 73: Oscillators Total Error vs. Temperature..................................................................................................................88

Figure 74: Oscillator0 Settling Time, V_DD= 3.3 V, T = 25 °C, OSC0 = 2.048 kHz...................................................................89

Figure 75: Oscillator0 Settling Time, V_DD= 3.3 V, T = 25 °C, OSC0 = 10 kHz........................................................................89

Figure 76: Oscillator1 Settling Time, V_DD= 3.3 V, T = 25 °C, OSC1 = 25 MHz (Normal Start)...............................................90

Figure 77: OSC0 Current Consumption vs. V_DD(All Pre-Dividers), OSC0 = 2.048 kHz..........................................................90

Figure 78: OSC0 Current Consumption vs. V_DD(All Pre-Dividers), OSC0 = 10 kHz...............................................................91

Figure 79: OSC1 Current Consumption vs. V_DD, T = -40 °C to 85 °C, OSC1 = 25 MHz .........................................................91

Figure 80: POR Sequence.......................................................................................................................................................93

Figure 81: Internal Macrocell States During POR Sequence...................................................................................................94

Figure 82: Power-Down............................................................................................................................................................95

Figure 83: Basic Command Structure......................................................................................................................................97

Figure 84: I²C General Timing Characteristics.........................................................................................................................97

Figure 85: Byte Write Command, R/W = 0...............................................................................................................................98

Figure 86: Sequential Write Command....................................................................................................................................98

Figure 87: Current Address Read Command, R/W = 1............................................................................................................99

Figure 88: Random Read Command .......................................................................................................................................99

Figure 89: Sequential Read Command..................................................................................................................................100

Figure 90: Reset Command Timing .......................................................................................................................................100

Figure 91: Example of I²C Byte Write Bit Masking.................................................................................................................103

Figure 92: I²C General Block Diagram...................................................................................................................................104

Figure 93: Analog Temperature Sensor Structure Diagram...................................................................................................105

Figure 94: TS Output vs. Temperature, V_DD= 2.3 V to 5.5 V................................................................................................106

Datasheet

14-Apr-2021

Revision 3.0

5 of 171

CFR0011-120-00

SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Tables

Table 1: Functional Pin Description............................................................................................................................................8

Table 2: Pin Type Definitions ...................................................................................................................................................10

Table 3: Absolute Maximum Ratings........................................................................................................................................11

Table 4: Electrostatic Discharge Ratings .................................................................................................................................11

Table 5: Recommended Operating Conditions........................................................................................................................11

Table 6: EC at T = -40 °C to +85 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted ..............................................................12

Table 7: EC of SDA and SCL Pins, DI Mode, at T = -40 °C to +85 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted ..........14

Table 8: EC of SDA and SCL Pins, DILV Mode, at T = -40 °C to +85 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted......15

Table 9: I²C Bus Timing Characteristics, DI Mode, at T = -40 °C to +85 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted..15

Table 10: I²C Bus Timing Characteristics, DILV Mode, at T = -40°C to +85°C, V_DD= 2.3V to 5.5V Unless Otherwise Noted16

Table 11: Typical Current Estimated for Each Macrocell at T = -40 °C to +85 °C ...................................................................17

Table 12: Typical Delay Estimated for Each Macrocell at T = 25 °C........................................................................................17

Table 13: Programmable Delay Expected Delays and Widths (Typical) at T = 25 °C .............................................................19

Table 14: Typical Filter Rejection Pulse Width at T = 25 °C ....................................................................................................19

Table 15: Typical Counter/Delay Offset at T = 25 °C...............................................................................................................19

Table 16: Oscillators Frequency Limits, V_DD= 2.3 V to 5.5 V..................................................................................................20

Table 17: Oscillators Power-On Delay at T = -40 °C to +85 °C, OSC Power Setting: "Auto Power-On".................................20

Table 18: MS ACMP Specifications at T = -40 °C to +85 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted .........................20

Table 19: Temperature Sensor Output vs Temperature at VDD = 2.3 V to 5.5 V.....................................................................23

Table 20: Matrix Input Table.....................................................................................................................................................33

Table 21: Matrix Output Table..................................................................................................................................................35

Table 22: Connection Matrix Virtual Inputs ..............................................................................................................................37

Table 23: 2-bit LUT2_0 to 2-bit LUT2_1 Truth Table ...............................................................................................................40

Table 24: 2-bit LUT Standard Digital Functions .......................................................................................................................40

Table 25: 2-bit LUT2_2 Truth Table.........................................................................................................................................42

Table 26: 2-bit LUT Standard Digital Functions .......................................................................................................................42

Table 27: 3-bit LUT3_0 to 3-bit LUT3_9 Truth Table ...............................................................................................................49

Table 28: 3-bit LUT Standard Digital Functions .......................................................................................................................49

Table 29: 4-bit LUT0 Truth Table.............................................................................................................................................53

Table 30: 4-bit LUT Standard Digital Functions .......................................................................................................................54

Table 31: 3-bit LUT8 Truth Table.............................................................................................................................................62

Table 32: 3-bit LUT9 Truth Table.............................................................................................................................................62

Table 33: 3-bit LUT10 Truth Table...........................................................................................................................................62

Table 34: 3-bit LUT11 Truth Table...........................................................................................................................................62

Table 35: 3-bit LUT12 Truth Table...........................................................................................................................................62

Table 36: 3-bit LUT13 Truth Table...........................................................................................................................................62

Table 37: Recommended MS ACMP Clock Frequencies ........................................................................................................72

Table 38: Vref Selection Table.................................................................................................................................................81

Table 39: Oscillator Control Input Modes.................................................................................................................................82

Table 40: Oscillator Operation Mode Configuration Settings...................................................................................................82

Table 41: Read/Write Protection Options...............................................................................................................................101

Table 42: Register Map..........................................................................................................................................................107

Table 43: MSL Classification..................................................................................................................................................164

Datasheet

14-Apr-2021

Revision 3.0

6 of 171

CFR0011-120-00

SLG46811

GreenPAK Programmable Mixed-Signal Matrix

1

Block Diagram

GPI

V_DD

GPIO8

Multichannel

Sampling ACMP

Combination Function Macrocells

GPIO4

GPIO5

GPIO6

6

in

1

3-bit

LUT3_0

or DFF2

2-bit

LUT2_2

or PGen

GPIO0

GPIO7

MS_ACMP IN3

GPIO7

I²C_SCL

LUT2_0

or DFF0

LUT2_1

or DFF1

V

DD

Temp

ACMP0H

3-bit

LUT3_2

or DFF4

3-bit

LUT3_3

or DFF5

4-bit

LUT4_0

or DFF16

3-bit

LUT3_1

or DFF3

Config.

Vref

3-bit

LUT3_4

LUT3_5

LUT3_6

LUT3_7

Sampling Engine

or DFF6 or

Shift_Reg0

or DFF7 or

Shift_Reg1

or DFF8 or

Shift_Reg2

or DFF9 or

Shift_Reg3

GPIO1

GPIO6

MS_ACMP IN2

I²C_SDA

Oscillators

Multi-Function Macrocells

2.048 kHz/

10 kHz

25 MHz

3-bit

LUT3_8 /

DFF10+8bit

CNT/DLY0/

FSM

3-bit

LUT3_10 /

DFF12+8bit

CNT/DLY2

LUT3_9 /

DFF11+8bit

CNT/DLY1

2

I C Serial

Filter with Edge

Detect

POR with CRC

Communication

3-bit

LUT3_11 /

DFF13+8bit

CNT/DLY3

LUT3_12 /

DFF14+8bit

CNT/DLY4

LUT3_13 /

DFF15+8bit

CNT/DLY5

Extended Pattern

Generator

Programmable

Delay

Temperature

Sensor

GPIO5

MS_ACMP IN1

GPIO2

GPIO3

Ext_Vref

GPIO4

MS_ACMP IN0

GND

Figure 1: Block Diagram

Datasheet

14-Apr-2021

Revision 3.0

7 of 171

CFR0011-120-00

SLG46811

GreenPAK Programmable Mixed-Signal Matrix

2

Pinout

2.1 PIN CONFIGURATION - STQFN- 12

Pin # Pin Name Pin Functions

1

2

V_DD

Power Supply

GPI

GPI, SLA_0, EXT_CLK_OSC0

GPIO, I²C SCL

GPIO, I²C SDA

3

GPIO0

GPIO1

GPIO2

GPIO3

GND

4

5

GPIO with OE

6

GPIO with OE, SLA_1, EXT_Vref

Ground

7

12 11

GPIO6

GPIO5

GPIO4

GND

V_DD

1

8

GPIO4

GPIO5

GPIO6

GPIO, SLA_2, MS ACMP input 0

GPIO, MS ACMP input 1

GPIO, MS ACMP input 2

10

9

GPI

GPIO0

GPIO1

2

3

4

9

8

7

10

GPIO with OE, MS ACMP input 3, SLA_3,

EXT_CLK_OSC1

11

12

GPIO7

GPIO8

GPIO with OE

5

6

Legend:

OE: Output Enable

MS ACMP input: Multichannel Sample ACMP Positive Input

I²C SCL: I²C Clock Input

I²C SDA: I²C Data Input/Output

EXT_CLKx: External Clock Input

SLA: Slave Address

STQFN-12

(Top View)

Table 1: Functional Pin Description

STQFN

12 Pin # Name

Signal

Name

Input

Options

Output

Options

Function

1

2

V_DD

Power Supply

--

Digital Input

without Schmitt Trigger

--

GPI

General Purpose Input

Digital Input

with Schmitt Trigger

--

GPI

Low Voltage Digital Input

Slave

Address 0

--

External Clock

of OSC0

External Clock Connection

--

Digital Input

without Schmitt Trigger

Open-Drain NMOS

(3.2x)

General Purpose IO

with OE (Note 1)

GPIO

Digital Input

with Schmitt Trigger

3

GPIO0

Low Voltage Digital Input

--

Digital Input

without Schmitt Trigger

I²C SCL

I²C Serial Clock

Low Voltage Digital Input

Datasheet

14-Apr-2021

Revision 3.0

8 of 171

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SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 1: Functional Pin Description (Continued)

STQFN

12 Pin # Name

Signal

Name

Input

Options

Output

Options

Function

Digital Input

without Schmitt Trigger

Open-Drain NMOS

(3.2x)

GPIO

I²C SDA

GPIO

General Purpose IO

Digital Input

with Schmitt Trigger

4

5

GPIO1

GPIO2

Low Voltage Digital Input

Digital Input

without Schmitt Trigger

--

I²C Serial Data

Low Voltage Digital Input

--

Digital Input

without Schmitt Trigger

Push-Pull (1x) (2x)

General Purpose IO

with OE (Note 1)

Digital Input

with Schmitt Trigger

Open-Drain NMOS

(1x) (2x)

Low Voltage Digital Input

--

Digital Input

without Schmitt Trigger

Push-Pull (1x) (2x)

General Purpose IO

with OE (Note 1)

GPIO

Digital Input

with Schmitt Trigger

Open-Drain NMOS

(1x) (2x)

6

7

GPIO3

GND

Low Voltage Digital Input

Analog

--

EXT_Vref

ACMP Inverting Input

Power Supply

Slave

Address 1

--

GND

--

Digital Input

without Schmitt Trigger

Push-Pull (1x) (2x)

GPIO

General Purpose IO

Digital Input

with Schmitt Trigger

Open-Drain NMOS

(1x) (2x)

8

GPIO4

Low Voltage Digital Input

--

Positive Input 0 of

MS ACMP

MS_ACMP In0

Analog

--

Slave

Address 2

--

Digital Input

without Schmitt Trigger

Push-Pull (1x) (2x)

GPIO

General Purpose IO

Digital Input

with Schmitt Trigger

Open-Drain NMOS

(1x) (2x)

9

GPIO5

GPIO6

Low Voltage Digital Input

--

Positive Input 1 of

MS ACMP

MS ACMP In1

GPIO

Analog

--

Digital Input

without Schmitt Trigger

Push-Pull (1x) (2x)

General Purpose IO

Digital Input

with Schmitt Trigger

Open-Drain NMOS

(1x) (2x)

10

Low Voltage Digital Input

--

Positive Input 2 of

MS ACMP

MS ACMP In2

Analog

--

Datasheet

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GreenPAK Programmable Mixed-Signal Matrix

Table 1: Functional Pin Description (Continued)

STQFN

12 Pin # Name

Signal

Name

Input

Options

Output

Options

Function

Digital Input

without Schmitt Trigger

Push-Pull (1x) (2x)

General Purpose IO

with OE (Note 1)

GPIO

Digital Input

with Schmitt Trigger

Open-Drain NMOS

(1x) (2x)

Low Voltage Digital Input

--

11

GPIO7

Positive Input 3 of

MS ACMP

MS ACMP In 3

Analog

--

Slave

Address 3

--

External Clock

of OSC1

External Clock Connection

--

Digital Input

without Schmitt Trigger

Push-Pull (1x) (2x)

General Purpose IO

with OE (Note 1)

12

GPIO8

GPIO

Digital Input

with Schmitt Trigger

Open-Drain NMOS

(1x) (2x)

Low Voltage Digital Input

--

Note 1 General Purpose IO's with OE can be used to implement bidirectional signals under user control via Connection Matrix

to OE signal in IO structure or as a 3-state output.

Table 2: Pin Type Definitions

Pin Type

V_DD

Description

Power Supply

GPI

General Purpose Input

General Purpose Input/Output

Ground

GPIO

GND

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GreenPAK Programmable Mixed-Signal Matrix

3

Characteristics

3.1 ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, so functional operation of the device at these or any other conditions beyond those indicated in the operational

sections of the specification are not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect

device reliability.

Table 3: Absolute Maximum Ratings

Parameter

Supply Voltage on V_DDrelative to GND

DC Input Voltage

Min

Max

Unit

V

-0.3

7

GND - 0.5 V V_DD+ 0.5 V

V

Maximum Average or DC Current

(Through V_DDor GND pin)

--

90

mA

Push-Pull 1x

--

11

16

Push-Pull 2x

OD 1x

Maximum Average or DC Current

(Through pin)

--

11

OD 2x

--

21

Current at Input Pin

-1.0

--

1.0

1000

150

mA

nA

°C

Input Leakage Current (Absolute Value)

Storage Temperature Range

Junction Temperature

-65

--

°C

Moisture Sensitive Level

1

3.2 ELECTROSTATIC DISCHARGE RATINGS

Table 4: Electrostatic Discharge Ratings

Parameter

Min

2000

1300

Max

--

Unit

V

ESD Protection (Human Body Model)

ESD Protection (Charged Device Model)

--

V

3.3 RECOMMENDED OPERATING CONDITIONS

Table 5: Recommended Operating Conditions

Parameter

Condition

Min

2.3

-40

Max

5.5

85

Unit

V

Supply Voltage (V_DD

)

Operating Temperature

°C

Maximal Voltage Applied to any PIN in High

Impedance State

V_DD+

0.3

--

V

Capacitor Value at V_DD

0.1

0

--

µF

Analog Input Common Mode Range

Allowable Input Voltage atAnalog Pins

V_DD

V

Datasheet

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GreenPAK Programmable Mixed-Signal Matrix

3.4 ELECTRICAL CHARACTERISTICS

Table 6: EC at T = -40 °C to +85 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted

Parameter Description

Condition

Min

Typ

Max

Unit

0.7x

V_DD

0.3

+

Logic Input (Note 1)

--

V

Logic InputwithSchmittTrigger (Positive

V_IH

HIGH-Level Input Voltage

0.8x

V_DD

0.3

+

Going Threshold Voltage min = 0.4xV_DD

,

--

V

max = 0.7xV_DD

)

Low-Level Logic Input (Note 1)

1.25

--

V

GND-

0.3

0.3x

V_DD

Logic Input (Note 1)

Logic Input with Schmitt Trigger

(Negative Going Threshold Voltage min

GND-

0.4

0.2x

V_DD

V_IL

LOW-Level Input Voltage

--

V

= 0.3xV_DD, max = 0.6xV_DD

)

GND-

0.5

Low-Level Logic Input (Note 1)

--

0.5

--

V

Push-Pull, 1x Drive,

V_DD= 2.5 V ± 8 %, I_OH= 1 mA

2.18

2.68

4.16

2.24

2.83

4.33

--

Push-Pull, 1x Drive,

--

V

_DD= 3.3 V ± 10 %, I_OH= 3 mA

Push-Pull, 1x Drive,

V_DD= 5.0 V ± 10 %, I_OH= 5 mA

--

V_OH

HIGH-Level Output Voltage

Push-Pull, 2x Drive,

V_DD= 2.5 V ± 8 %, I_OH= 1 mA

--

Push-Pull, 2x Drive,

--

V

_DD= 3.3 V ± 10 %, I_OH= 3 mA

Push-Pull, 2x Drive,

V_DD= 5.0 V ± 10 %, I_OH= 5 mA

--

Push-Pull, 1x Drive,

V_DD= 2.5 V ± 8 %, I_OL= 1 mA

0.092

0.227

0.283

0.045

0.111

0.140

0.036

0.089

Push-Pull, 1x Drive,

--

V

_DD= 3.3 V ± 10 %, I_OL= 3 mA

Push-Pull, 1x Drive,

V_DD= 5.0 V ± 10 %, I_OL= 5 mA

--

Push-Pull, 2x Drive,

V_DD= 2.5 V ± 8 %, I_OL= 1 mA

--

V_OL

LOW-Level Output Voltage

Push-Pull, 2x Drive,

V_DD= 3.3 V ± 10 %, I_OL= 3 mA

--

Push-Pull, 2x Drive,

V_DD= 5.0 V ± 10 %, I_OL= 5 mA

--

NMOS OD, 1x Drive,

V_DD= 2.5 V ± 8 %, I_OL= 1 mA

--

NMOS OD, 1x Drive,

V_DD= 3.3 V ± 10 %, I_OL= 3 mA

--

Datasheet

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GreenPAK Programmable Mixed-Signal Matrix

Table 6: EC at T = -40 °C to +85 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted (Continued)

Parameter Description

Condition

Min

Typ

Max

Unit

NMOS OD, 1x Drive,

V_DD= 5.0 V ± 10 %, I_OL= 5 mA

--

0.112

V

NMOS OD, 2x Drive,

V_DD= 2.5 V ± 8 %, I_OL= 1 mA

--

0.018

V

V_OL

LOW-Level Output Voltage

NMOS OD, 2x Drive,

V_DD= 3.3 V ± 10 %, I_OL= 3 mA

--

0.046

0.059

--

V

NMOS OD, 2x Drive,

V_DD= 5.0 V ± 10 %, I_OL= 5 mA

--

V

Push-Pull, 1x Drive,

V_DD= 2.5 V ± 8 %, V_OH= V_DD- 0.2

1.520

5.125

19.589

3.008

10.106

37.960

1.483

4.622

6.250

2.965

9.228

12.443

3.676

11.438

15.397

7.285

22.589

30.030

mA

Push-Pull, 1x Drive,

V_DD= 3.3 V ± 10 %, V_OH= 2.4 V

--

Push-Pull, 1x Drive,

V_DD= 5.0 V ± 10 %, V_OH= 2.4 V

--

HIGH-Level Output Pulse

Current (Note 2)

I_OH

Push-Pull, 2x Drive,

--

V

_DD= 2.5 V ± 8 %, V_OH= V_DD- 0.2

Push-Pull, 2x Drive,

V_DD= 3.3 V ± 10 %, V_OH= 2.4 V

--

Push-Pull, 2x Drive,

V_DD= 5.0 V ± 10 %, V_OH= 2.4 V

--

Push-Pull, 1x Drive,

--

V

_DD= 2.5 V ± 8 %, V_OL= 0.15 V

Push-Pull, 1x Drive,

V_DD= 3.3 V ± 10 %, V_OL= 0.4 V

--

Push-Pull, 1x Drive,

V_DD= 5.0 V ± 10 %, V_OL= 0.4 V

--

Push-Pull, 2x Drive,

--

V

_DD= 2.5 V ± 8 %, V_OL= 0.15 V

Push-Pull, 2x Drive,

V_DD= 3.3 V ± 10 %, V_OL= 0.4 V

--

Push-Pull, 2x Drive,

V_DD= 5.0 V ± 10 %, V_OL= 0.4 V

--

LOW-Level Output Pulse

Current (Note 2)

I_OL

NMOS OD, 1x Drive,

V_DD= 2.5 V ± 8 %, V_OL= 0.15 V

--

NMOS OD, 1x Drive,

V_DD= 3.3 V ± 10 %, V_OL= 0.4 V

--

NMOS OD, 1x Drive,

V_DD= 5.0 V ± 10 %, V_OL= 0.4 V

--

NMOS OD, 2x Drive,

V_DD= 2.5 V ± 8 %, V_OL= 0.15 V

--

NMOS OD, 2x Drive,

V_DD= 3.3 V ± 10 %, V_OL= 0.4 V

--

NMOS OD, 2x Drive,

V_DD= 5.0 V ± 10 %, V_OL= 0.4 V

--

T_RAMP=1 V/µs ,

From V_DDrising past PON_THR

T_SU

Startup Time

--

1.85

1.86

3.42

2.17

ms

V

PON_THR

Power-On Threshold

V_DDLevel Required to Start Up the Chip

1.55

Datasheet

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Revision 3.0

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GreenPAK Programmable Mixed-Signal Matrix

Table 6: EC at T = -40 °C to +85 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted (Continued)

Parameter Description

Condition

Min

Typ

Max

Unit

V_DDLevel Required to Switch Off the

Chip

POFF_THRPower-Off Threshold

1.06

1.34

1.62

V

1 M for Pull-up: V_IN= GND;

for Pull-down: V_IN= V_DD

0.86

83.30

7.01

1.03

1.33

MΩ

kΩ

Pull-up or Pull-down

Resistance

100 k for Pull-up: V_IN= GND

for Pull-down: V_IN= V_DD

R_PULL

105.20 133.81

10 k For Pull-up: V_IN= GND

for Pull-down: V_IN= V_DD

9.62

2.4

13.28

kΩ

C_IN

Input Capacitance

T = 25 °C

pF

Note 1 No hysteresis.

Note 2 DC or average current through any pin should not exceed value given in Absolute Maximum Conditions.

3.5 I²C PINS ELECTRICAL CHARACTERISTICS

Table 7: EC of SDA and SCL Pins, DI Mode, at T = -40 °C to +85 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted

Fast-Mode

Fast-Mode Plus

Parameter Description

Condition

Unit

Min

Max

Min

Max

LOW-level Input

Voltage

V_IL

-0.5

0.3xV_DD

-0.5

0.3xV_DD

V

HIGH-level Input

Voltage

V_IH

0.7xV_DD

5.5

--

0.7xV_DD

5.5

--

Hysteresis of

Schmitt Trigger

Inputs

V_HYS

V_OL1

V_OL2

0.05xV_DD

V

(Open-Drain or open

collector) at 3 mAsink current

LOW-Level Output

Voltage 1

0

0.4

0

0.4

V

_DD> 2 V

(Open-Drain or open

collector) at 2 mAsink current

LOW-Level Output

Voltage 2

0.2xV_DD

V

_DD≤ 2 V

V_OL= 0.4 V, V_DD= 2.3 V

V_OL= 0.4 V, V_DD= 3.3 V

V_OL= 0.4 V, V_DD= 4.5 V

V_OL= 0.6 V, V_DD= 5.5 V

3

6

--

20

--

mA

LOW-Level Output

Current

I_OL

Output Fall Time

from V_IHminto

V_ILmax

14x

(V_DD/5.5V)

10x

(V_DD/5.5V)

t_of

250

120

ns

(Note 1)

Digital Input (SDA)

Digital Input (SCL)

50

--

50

--

ns

Input Filter Spike

Suppression

t_SP

Input Current each

IO Pin

I_i

0.1xV_DD< V_I< 0.9xV_DDmax

-10

+10

-10

+10

µA

Capacitance for

each IO Pin

C_i

--

10

--

10

pF

Note 1 Does not meet standard I²C specifications: t_of= 20x(V_DD/5.5V) (min).

Note 2 For Fast-mode Plus SDA pin must be configured as NMOS 3.2x Open-Drain, see register [613] in section 18.

Datasheet

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Revision 3.0

14 of 171

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SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 8: EC of SDA and SCL Pins, DILV Mode, at T = -40 °C to +85 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted

Fast-Mode

Parameter Description

Condition

Unit

Min

Max

LOW-level Input Voltage

(Note 1)

V_IL

V_IH

--

0.7

V

HIGH-level Input Voltage

(Note 1)

1.25

--

Hysteresis of Schmitt Trigger

Inputs

V_HYS

V_OL1

V_OL2

0.05xV_DD

(Open-Drain or open collector) at 3 mA sink

current, V_DD> 2 V

LOW-Level Output Voltage 1

LOW-Level Output Voltage 2

0

0.4

(Open-Drain or open collector) at 2 mA sink

current, V_DD≤ 2 V

0.2xV_DD

V

_OL= 0.4 V, V_DD= 2.3 V

3

6

--

mA

V_OL= 0.4 V, V_DD= 3.3 V

V_OL= 0.4 V, V_DD= 4.5 V

V_OL= 0.6 V, V_DD= 5.5 V

I_OL

LOW-Level Output Current

Output Fall Time from V_IHminto

V_ILmax(Note 1)

14x

(V_DD/5.5V)

t_of

250

ns

Digital Input LOW Voltage (SDA)

Digital Input LOW Voltage (SCL)

0.1xV_DD< V_I< 0.9xV_DDmax

50

-10

--

ns

µA

pF

Input Filter Spike Suppression

(SCL, SDA)

t_SP

I_i

Input Current each IO Pin

+10

10

C_i

Capacitance for each IO Pin

Note 1 Does not meet standard I²C specifications: V_IL= 0.3xV_DD(max); V_IH= 0.7xV_DD(min); t_of= 20x(V_DD/5.5V) (min).

Table 9: I²C Bus Timing Characteristics, DI Mode, at T = -40 °C to +85 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted

Speed

Parameter Description

Condition

400 kHz

1 MHz

Unit

Min

Max

400

--

Min

Max

1000

--

F_SCL

t_LOW

t_HIGH

Clock Frequency, SCL

--

kHz

ns

Clock Pulse Width Low

Clock Pulse Width High

1300

600

500

260

--

ns

Bus Free Time between Stop and

Start

t_BUF

1300

--

500

--

ns

t_{HD_STA}

t_{SU_STA}

t_{HD_DAT}

t_{SU_DAT}

t_R

Start Hold Time

600

0

--

260

0

--

ns

Start Set-up Time

Data Hold Time

--

Data Set-up Time

Inputs Rise Time

Inputs Fall Time

100

--

50

--

300

--

120

--

t_F

--

t_{SU_STO}

t_{VD_ACK}

t_{VD_DAT}

Stop Set-up Time

Data Out Hold Time

Clock Low to Data Out Valid

600

50

--

260

50

--

900

450

Datasheet

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Revision 3.0

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GreenPAK Programmable Mixed-Signal Matrix

Table 9: I²C Bus Timing Characteristics, DI Mode, at T = -40 °C to +85 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted

Speed

Parameter Description

Condition

400 kHz

Min Max

1 MHz

Min Max

Unit

Note 1 Timing diagram can be found in the Figure 84.

Note 2 Please follow official I²C spec UM10204.

Table 10: I²C Bus Timing Characteristics, DILV Mode, at T = -40°C to +85°C, V_DD= 2.3V to 5.5V Unless Otherwise Noted

Speed

Parameter Description

Condition

400 kHz

Unit

Min

--

Max

400

--

F_SCL

t_LOW

Clock Frequency, SCL

kHz

ns

Clock Pulse Width Low

Clock Pulse Width High

Bus Free Time between Stop and Start

Start Hold Time

1300

600

1300

600

264

382

--

t_HIGH

--

t_BUF

--

t_{HD_STA}

t_{SU_STA}

t_{HD_DAT}

t_{SU_DAT}

t_R

--

Start Set-up Time

--

Data Hold Time (Note 1)

Data Set-up Time (Note 1)

Inputs Rise Time

--

300

--

t_F

Inputs Fall Time

--

t_{SU_STO}

t_{VD_ACK}

t_{VD_DAT}

Stop Set-up Time

600

50

Data Out Hold Time

--

Clock Low to Data Out Valid

--

900

Note 1 Does not meet standard I²C specifications: t_{HD_DAT}= 0 ns, t_{SU_DAT}= 100 ns.

Note 2 Please follow official I²C spec UM10204.

Note 3 When SCL Input is in Low-Level Logic mode max frequency is 400 kHz.

Note 4 Timing diagram can be found in the Figure 84.

Datasheet

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Revision 3.0

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GreenPAK Programmable Mixed-Signal Matrix

3.6 MACROCELLS CURRENT CONSUMPTION

Table 11: Typical Current Estimated for Each Macrocell at T = -40 °C to +85 °C

Parameter

Description Note

PDET+I²C

V_DD= 2.5 V V_DD= 3.3 V V_DD= 5.0 V

Unit

µA

0.06

0.38

0.08

0.41

0.13

0.49

PDET+BG+I²C

Temperature Sensor Output

OSC2 25 MHz, Pre-divider = 1

OSC2 25 MHz, Pre-divider = 4

OSC2 25 MHz, Pre-divider = 8

OSC0 2.048 kHz, Pre-divider = 1

OSC0 2.048 kHz, Pre-divider = 4

OSC0 2.048 kHz, Pre-divider = 8

OSC0 10 kHz, Pre-divider = 1

OSC0 10 kHz, Pre-divider = 4

OSC0 10 kHz, Pre-divider = 8

15.06

82.44

45.97

39.62

0.33

15.14

106.46

57.00

48.35

0.36

15.48

162.02

83.21

69.35

0.44

0.33

0.36

0.44

0.33

0.36

0.44

0.45

0.49

0.60

0.44

0.48

0.57

0.44

0.47

0.56

I_DD

Current

MS ACMP in regular mode

(Vref Source - External

VIN+ = 0 V,

14.44

21.56

35.40

14.83

21.97

36.11

15.95

23.21

38.18

µA

VIN- = 32 mV), level sensitive

MS ACMP in regular mode

(Vref Source − Internal

V

_IN+= 0 V; V_IN-= 32 mV), level sensitive

MS ACMP in regular mode

(Vref Source − Internal

V

_IN+= 1 M Pull-up

V_IN-= 32 mV), level sensitive

MSACMPin continuous sampling mode,

four channels,

V_IN+= 2.048 mV, V_IN-= 32 mV,

10 kHz oscillator clock (average con-

sumption), level sensitive

35.78

36.47

38.57

µA

3.7 TIMING CHARACTERISTICS

Table 12: Typical Delay Estimated for Each Macrocell at T = 25 °C

V_DD= 2.5 V

V_DD= 3.3 V

V_DD= 5 V

Note

Parameter Description

Unit

Rising Falling Rising Falling Rising Falling

tpd

Delay

Digital Input to PP 1x

Digital Input to PP 2x

31

30

32

270

31

30

--

22

21

22

24

--

24

23

24

178

22

--

17

16

17

19

--

18

17

18

104

17

16

--

ns

Digital Input with Schmitt Trigger to PP 1x 31

Low Voltage Digital Input to PP 1x

Digital input to NMOS 1x

Digital input to NMOS 2x

Output enable from Pin, OE Hi-Z to 1

Output enable from Pin, OE Hi-Z to 0

1x3 State Hi-Z to 1

33

--

28

--

20

--

15

--

27

--

20

--

15

--

28

--

20

--

15

--

1x3 State Hi-Z to 0

27

--

20

--

15

--

2x3 State Hi-Z to 1

27

19

15

Datasheet

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Revision 3.0

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SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 12: Typical Delay Estimated for Each Macrocell at T = 25 °C (Continued)

V_DD= 2.5 V

V_DD= 3.3 V

V_DD= 5 V

Note

Parameter Description

Unit

Rising Falling Rising Falling Rising Falling

tpd

tw

Delay

Width

Delay

2x3 State Hi-Z to 0

LATCH Q

--

15

16

23

21

22

21

13

19

18

70

26

18

212

230

15

16

--

26

16

24

25

24

23

22

13

21

20

71

25

18

212

232

17

23

--

12

11

16

17

16

15

14

16

10

15

13

49

19

13

157

169

11

12

--

19

11

12

18

17

18

16

17

16

15

10

14

50

18

13

157

170

13

17

--

8

14

8

ns

LATCH nQ

9

8

LATCH nRESET High Q

LATCH nRESET High nQ

LATCH nRESET Low Q

LATCH nRESET Low nQ

LATCH nSET High Q

LATCH nSET High nQ

LATCH nSET Low Q

LATCH nSET Low nQ

2-bit LUT

12

11

10

11

7

12

11

7

3-bit LUT

11

9

10

32

13

9

4-bit LUT

Shift Register Transition

Shift Register Reset

Edge detect

32

13

9

Edge detect

113

122

8

114

122

9

tpd

Edge detect Delayed

DFF Q

DFF nQ

8

9

DFF nRESET High Q

DFF nRESET High nQ

DFF nRESET Low Q

DFF nRESET Low nQ

DFF nSET High Q

DFF nSET High nQ

DFF nSET Low Q

DFF nSET Low nQ

СNT/DLY

--

12

--

22

--

16

--

11

--

23

--

16

--

12

--

22

--

15

16

--

11

--

23

--

17

--

12

--

22

--

15

--

11

--

23

79

16

19

--

17

70

12

14

--

12

70

9

81

18

--

59

14

--

43

9

PGen CLK

PGen nRESET Z to 0

PGen nRESET Z to 1

Extended PGen CLK

Extended PGen nRESET Z to 0

Extended PGen nRESET Z to 1

Filter Q, nQ

--

10

--

18

488

--

13

487

--

9

488

67

--

487

48

--

493

--

495

35

--

68

122

48

93

33

68

125

95

69

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GreenPAK Programmable Mixed-Signal Matrix

Table 13: Programmable Delay Expected Delays and Widths (Typical) at T = 25 °C

Parameter

tw

Description

Note

V_DD= 2.5 V V_DD= 3.3 V V_DD= 5.0 V Unit

Pulse Width, 1 cell mode: (any) edge detect, edge detect output

Pulse Width, 2 cell mode: (any) edge detect, edge detect output

Pulse Width, 3 cell mode: (any) edge detect, edge detect output

Pulse Width, 4 cell mode: (any) edge detect, edge detect output

216

427

638

850

18

160

316

471

627

13

115

228

341

453

9

ns

tw

time1

time2

Delay, 1 cell

Delay, 2 cell

Delay, 3 cell

Delay, 4 cell

Delay, 1 cell

Delay, 2 cell

Delay, 3 cell

Delay, 4 cell

mode: (any) edge detect, edge detect output

mode: both edge delay, edge detect output

18

13

9

18

13

9

18

13

9

234

446

656

866

172

328

483

639

124

237

350

461

Table 14: Typical Filter Rejection Pulse Width at T = 25 °C

Parameter

V_DD= 2.5 V V_DD= 3.3 V V_DD= 5.0 V

< 63 < 49 < 37

Unit

Filtered Pulse Width, t_block

ns

3.8 COUNTER/DELAY CHARACTERISTICS

Table 15: Typical Counter/Delay Offset at T = 25 °C

RC OSC

Parameter

RC OSC Power V_DD= 2.5 V V_DD= 3.3 V V_DD= 5.0 V

Unit

Freq

25 MHz

2.048 kHz

10 kHz

Power-On time

auto

0.055

695

0.04

575

0.025

480

µs

695

480

Stabilized

Clk

Frequency Settling Time

25 MHz

2.048 kHz

10 kHz

auto

10

1

10

1

10

1

Stabilized

Clk

Stabilized

Clk

5

Variable (CLK period)

25 MHz

2.048 kHz

10 kHz

forced

0-40

0-488

0-100

0-40

0-488

0-100

0-40

0-488

0-100

ns

µs

25 MHz/

2.048 kHz/

10 kHz

Typical Propagation Delay

(non-delayed edge)

either

35

25

18

ns

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3.9 OSCILLATOR CHARACTERISTICS

Table 16: Oscillators Frequency Limits, V_DD= 2.3 V to 5.5 V

Temperature Range

+25 °C

-40 °C to +85 °C

Parameter

Minimum

Value, kHz

Maximum

Value, kHz

Minimum

Value, kHz

Maximum

Value, kHz

Error, %

+1.6

-1.6

+1.6

-1.6

+1.6

-1.6

+2.5

-7.2

+1.6

-5.4

+1.6

-4.0

2.048 kHz OSC0

10 kHz OSC0

2.015

9.84

2.081

10.16

25400

1.900

2.099

10.16

25400

9.46

25 MHz OSC1

24600

24000

3.9.1 OSC Power-On Delay

Table 17: Oscillators Power-On Delay at T = -40 °C to +85 °C, OSC Power Setting: "Auto Power-On"

OSC1 25 MHz

Start with Delay

Power Sup-

ply Range

(V_DD), V

OSC0 2.048 kHz

OSC0 10 kHz

OSC1 25 MHz

Typical

Maximum

Value, µs

Typical

Maximum

Value, µs

Typical

Maximum

Value, ns

Typical

Maximum

Value, ns

Value, µs

Value, ns

2.30

3.30

4.00

5.00

5.50

725

1098

815

714

623

581

725

1101

816

716

624

582

60

37

31

26

24

77

51

44

38

41

150

163

159

160

161

577

142

528

141

483

140

459

140

3.10 MS ACMP CHARACTERISTICS

Table 18: MS ACMP Specifications at T = -40 °C to +85 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted

Parame-

ter

Description

Note

Condition

Min

0

Typ

--

Max

Unit

V

Positive Input

Negative Input

V_DD

MS ACMP Input

Voltage Range

V_ACMP

0

--

V

MS ACMP Vhys = 0 mV,

Gain = 1,

Vref = 32 mV to 2016 mV

(regular mode)

-6.7

-4.3

-0.6

1.1

5.2

7.2

mV

MS ACMP Input

Offset

V_offset

MS ACMP Vhys = 0 mV,

Gain = 1,

Vref = 32 mV to 2016 mV

(sampling mode)

V_DD= 2.3 V

V_DD= 3.3 V

V_DD= 5.5 V

--

1.5

6.0

nA

ACMP Input

Leakage

I_LKG

V_IN= V_DD

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GreenPAK Programmable Mixed-Signal Matrix

Table 18: MS ACMP Specifications at T = -40 °C to +85 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted (Continued)

Parame-

ter

Description

Note

Condition

Min

Typ

Max

Unit

MS ACMP Power-On

delay (regular mode)

--

70.8

µs

MS ACMP Power-On

delay (sampling mode),

OSC0 = 10 kHz

Bandgap: Forced On,

OSC0: Forced On

--

0.56

2.66

1.23

2.59

ms

MS ACMP Power-On

delay (sampling mode),

OSC0 = 10 kHz

Bandgap: Auto-On,

OSC0: Auto-On

t_start

ACMP Startup Time

MS ACMP Power-On

delay (sampling mode),

OSC0 = 10 kHz

Bandgap: Forced On,

OSC0: Auto-On

MS ACMP Power-On

delay (sampling mode),

OSC0 = 10 kHz

Bandgap: Auto-On,

OSC0: Forced On

V_HYS= 32 mV (sampling

T = 25 °C

23.36

55.62

55.01

30.22

61.57

62.16

34.83

65.58

66.64

mV

mode) (Note 2)

V_HYS= 64 mV (regular

mode)

V_HYS= 64 mV (sampling

mode)

V_HYS= 192 mV (regular

mode)

182.69 189.56 193.88

182.08 190.14 195.22

T = 25 °C

V_HYS= 192 mV (sampling

mode)

Built-in Hysteresis

V_HYS

(Note 1)

V_HYS= 32 mV (sampling

21.08

52.29

52.24

30.22

61.57

62.16

37.44

67.63

69.77

mode) (Note 2)

V_HYS= 64 mV (regular

mode)

V_HYS= 64 mV (sampling

mode)

V_HYS= 192 mV (regular

mode)

178.95 189.56 195.75

179.54 190.14 198.71

V_HYS= 192 mV (sampling

mode)

Gain = 1x

--

10

1.9

--

GΩ

MΩ

Gain = 0.5x

Gain = 0.33x

Gain = 0.25x

1.6

2.4

Series Input

Resistance

R_sin

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GreenPAK Programmable Mixed-Signal Matrix

Table 18: MS ACMP Specifications at T = -40 °C to +85 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted (Continued)

Parame-

ter

Description

Note

Condition

Min

Typ

Max

Unit

Gain = 1,

Low to High

0.35

1.05

4.01

µs

Vref = 32 mV to 2016 mV,

Overdrive = 10 mV,

regular mode

High to Low

Low to High

High to Low

Low to High

High to Low

Low to High

0.53

0.56

0.69

1.18

2.23

0.23

1.45

1.05

1.45

1.50

2.49

0.34

3.30

2.49

2.42

1.75

2.84

0.48

µs

Gain = 1, T = 25 °C,

Vref = 32 mV to 2016 mV,

Overdrive = 10 mV,

regular mode

Gain = 0.25, T = 25 °C,

Vref = 32 mV,

Overdrive = 10 mV,

regular mode

Propagation Delay,

Response Time

PROP

Gain = 1, T = 25 °C,

Vref = 32 mV to 2016 mV,

Overdrive = 100 mV,

High to Low

0.27

0.39

0.65

µs

regular mode

Gain = 0.25, T = 25 °C,

Vref = 32 mV,

Overdrive = 100 mV,

regular mode

Low to High

High to Low

0.46

1.33

0.56

1.48

0.65

1.70

µs

G = 1

1

G = 0.5

G = 0.33

G = 0.25

0.498

0.332

0.249

-0.43

-0.82

0.500

0.334

0.251

-0.10

0.503

0.337

0.253

0.21

G

Gain error

T = 25 °C

%

Vref Accuracy,

Vref = 2016 mV

Vref

0.24

Note 1 V_IL= Vin - V_HYS, V_IH= Vin.

Note 2 Available only in Sampling mode.

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3.11 ANALOG TEMPERATURE SENSOR CHARACTERISTICS

Temperature Sensor typical nonlinearity ±0.57 % at V_DD= 2.3 V to 5.5 V.

Table 19: Temperature Sensor Output vs Temperature at V_DD= 2.3 V to 5.5 V

TS OUT, V

T, °C

Error, %

Min

Typ

Max

1.997

1.951

1.906

1.861

1.814

1.769

1.722

1.699

1.675

1.628

1.579

1.531

1.482

1.433

1.409

1.384

1.335

1.285

1.235

1.210

1.185

2.008

1.963

1.918

1.872

1.826

1.779

1.733

1.710

1.686

1.639

1.591

1.543

1.494

1.446

1.421

1.397

1.347

1.298

1.249

1.224

1.200

2.023

1.979

1.933

1.886

1.840

1.792

1.745

1.722

1.698

1.651

1.603

1.555

1.507

1.458

1.433

1.409

1.359

1.310

1.260

1.236

1.211

-40 °C

-30 °C

-20 °C

-10 °C

0 °C

±0.75

±0.82

±0.78

±0.75

±0.77

±0.73

±0.69

±0.70

±0.71

±0.73

±0.75

±0.78

±0.87

±0.90

±0.84

±0.93

±0.89

±1.00

±1.12

±1.14

±1.25

10 °C

20 °C

25 °C

30 °C

40 °C

50 °C

60 °C

70 °C

80 °C

85 °C

90 °C

100 °C

110 °C

120 °C

125 °C

130 °C

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GreenPAK Programmable Mixed-Signal Matrix

4

User Programmability

The SLG46811 is a user programmable device with one time programmable (OTP) memory elements that are able to configure

the connection matrix and macrocells. A programming development kit allows the user the ability to create initial devices. Once

the design is finalized, the programming code (.gpx file) is forwarded to Dialog Semiconductor to integrate into a production

process.

Product

Definition

E-mail Product Idea, Definition, Drawing or

Customer creates their own design in

Schematic to

GreenPAK Designer

CMBUGreenPAK@diasemi.com

Dialog Semiconductor Applications

Engineer will review design specifications

with customer

Customer verifies GreenPAK in system

design

GreenPAK Design

approved

Samples, Design and Characterization

Report send to customer

GreenPAK Design

approved

Customers verifies GreenPAK design

GreenPAK Design

approved in system test

Custom GreenPAK part enters production

Figure 2: Steps to Create a Custom GreenPAK Device

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5

IO Pins

The SLG46811 has a total of 9 GPIO and 1 GPI Pins which can function as either a user defined Input or Output.

5.1 GPIO PINS

Pins from GPIO0 to GPIO8 serve as General Purpose IO Pins. Input function of GPIO shared with I²C virtual inputs. See Section

6.1.

5.2 GPI PINS

GPI serves as a General Purpose Input Pin.

5.3 PULL-UP/DOWN RESISTORS

All IO Pins have the option for user selectable resistors connected to the input structure. The selectable values on these resistors

are 10 kΩ, 100 kΩ, and 1 MΩ. The internal resistors can be configured as either Pull-up or Pull-downs.

5.4 FAST PULL-UP/DOWN DURING POWER-UP

During power-up, IO Pull-up/down resistance will switch to 2.6 kΩ initially and then it will switch to normal setting value. This

function is enabled by register [594].

5.5 GPI STRUCTURE

5.5.1 GPI Structure (for GPI)

Non-Schmitt

Trigger Input

Input Mode [1:0]

00: Digital In without Schmitt Trigger, wosmt_en = 1, OE=0

01: Digital In with Schmitt Trigger, smt_en = 1, OE = 0

10: Low Voltage Digital In mode, lv_en = 1, OE = 0

11: Reserved

WOSMT_EN

SMT_EN

OE

Schmitt

Trigger Input

Digital IN

Note 1: OE cannot be selected by user

Note 2: OE is Matrix output, Digital In is Matrix input

Low Voltage

Input

LV_EN

OE

Floating

PAD

s0

s1

s2

s3

V_DD

s1

s0

900 kΩ

90 kΩ

10 kΩ

Res_sel [1:0]

00: Floating

01: 10 kΩ

Pull-up_EN

10: 100 kΩ

11: 1 MΩ

Figure 3: GPI Structure Diagram

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5.6 GPIO WITH I²C MODE IO STRUCTURE

5.6.1 GPIO with I²C Mode Structure (for GPIO0 and GPIO1)

Input Mode [1:0]

00: Digital Input without Schmitt Trigger

01: Reserved

10: Low Voltage Digital Input

11: Reserved

Non-Schmitt

Trigger Input

register [606]=1: Open-Drain NMOS for GPIO0

register [613]=1: Open-Drain NMOS for GPIO1

WOSMT_EN

OE

Digital IN

Low Voltage

Input

Note 1: OE cannot be selected by user and is controlled by register.

Digital In is Matrix input.

Note 2: GPIO0 and GPIO1 do not support Push-Pull and PMOS

Open-Drain modes.

Note 3: It is possible to apply an input voltage higher than V_DDto

GPIO0 and GPIO1. However, this voltage should not exceed 5.5 V.

Note 4: Can be varied over PVT, for reference only.

LV_EN

OE

Analog IO

Floating

s0

s1

s2

s3

172 Ω

(Note 4)

s1

s0

900 kΩ

90 kΩ

10 kΩ

Res_sel [1:0]

00: Floating

01: 10 kΩ

Pull-up_EN

10: 100 kΩ

11: 1 MΩ

Digital OUT

OE

OD 3.2x_en

PAD

Figure 4: GPIO with I²C Mode IO Structure Diagram

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5.7 MATRIX OE IO STRUCTURE

5.7.1 Matrix OE IO Structure (for GPIO2, GPIO3, GPIO7, GPIO8)

Non-Schmitt

Trigger Input

Input Mode [1:0]

00: Digital In without Schmitt Trigger, wosmt_en = 1

01: Digital In with Schmitt Trigger, smt_en = 1

10: Low Voltage Digital In mode, lv_en = 1

11: analog IO mode

WOSMT_EN

SMT_EN

Schmitt

Trigger Input

Digital IN

Output Mode [1:0]

00: Push-Pull 1x mode, pp1x_en = 1

01: Push-Pull 2x mode, pp2x_en = 1, pp1x_en = 1

10: NMOS 1x Open-Drain mode, od1x_en = 1

11: NMOS 2x Open-Drain mode, od2x_en = 1, od1x_en = 1

Low Voltage

Input

Note 1: Digital Out and OE are Matrix Output, Digital In is Matrix Input

Note 2: Can be varied over PVT, for reference only.

LV_EN

Analog IO

Floating

s0

V_DD

s1

s2

s3

s1

s0

172 Ω

(Note 2)

900 kΩ

Res_sel

[1:0]

90 kΩ

10 kΩ

V_DD

00: Floating

01: 10 kΩ

10: 100 kΩ

11: 1 MΩ

Pull-up_EN

Digital OUT

OE

OD1x_EN

PP1x_EN

V_DD

PAD

V_DD

Digital OUT

OE

OD2x_EN

PP2x_EN

Figure 5: Matrix OE IO Structure Diagram

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5.8 REGISTER OE IO STRUCTURE

5.8.1 Register OE IO Structure (for GPIO4, GPIO5, GPIO6)

Non-Schmitt

Trigger Input

Input Mode [1:0]

00: Digital In without Schmitt Trigger, wosmt_en = 1

01: Digital In with Schmitt Trigger, smt_en = 1

10: Low Voltage Digital In mode, lv_en = 1

11: Analog IO mode

WOSMT_EN

SMT_EN

Schmitt

Trigger Input

Digital IN

Output Mode [1:0]

00: Push-Pull 1x mode, pp1x_en = 1

01: Push-Pull 2x mode, pp2x_en = 1, pp1x_en = 1

10: NMOS 1x Open-Drain mode, od1x_en = 1

11: NMOS 2x Open-Drain mode, od2x_en = 1, od1x_en = 1

Low Voltage

Input

Note 1: Digital Out is Matrix Output, Digital In is Matrix Input. OE is register

bit

Note 2: Can be varied over PVT, for reference only.

LV_EN

Analog IO

Floating

s0

V_DD

s1

s2

s3

s1

s0

172 Ω

(Note 2)

900 kΩ

Res_sel

[1:0]

90 kΩ

10 kΩ

V_DD

00: Floating

01: 10 kΩ

10: 100 kΩ

11: 1 MΩ

Pull-up_EN

Digital OUT

OE

OD1x_EN

PP1x_EN

V_DD

PAD

V_DD

Digital OUT

OE

OD2x_EN

PP2x_EN

Figure 6: Register OE IO Structure Diagram

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5.9 IO TYPICAL PERFORMANCE

60

Push-Pull 2x @ VDD = 5 V

Push-Pull 1x @ VDD = 5 V

50

Push-Pull 2x @ VDD = 3.3 V

Push-Pull 1x @ VDD = 3.3 V

Push-Pull 2x @ VDD = 2.5 V

40

30

20

10

0

Push-Pull 1x @ VDD = 2.5 V

5.00

4.75

4.50

4.25

4.00

3.75

3.50

3.25

3.00

2.75

2.50

2.25

2.00

1.75

1.50

1.25

V_OH(V)

Figure 7: Typical High Level Output Current vs. High Level Output Voltage at T = 25 °C

80

70

60

50

40

30

20

10

0

Open Drain 1x @ VDD = 5 V

Open Drain 1x @ VDD = 3.3 V

Open Drain 1x @ VDD = 2.5 V

Push-Pull 1x @ VDD = 5 V

Push-Pull 1x @ VDD = 3.3 V

Push-Pull 1x @ VDD = 2.5 V

0

0.25

0.5

0.75

1

1.25

1.5

1.75

2

2.25

2.5

V_OL(V)

Figure 8: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 °C, Full Range

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30

Open Drain 1x @ VDD = 5 V

25

Open Drain 1x @ VDD = 3.3 V

Open Drain 1x @ VDD = 2.5 V

Push-Pull 1x @ VDD = 5 V

20

15

10

5

Push-Pull 1x @ VDD = 3.3 V

Push-Pull 1x @ VDD = 2.5 V

0

0.1

0.2

0.3

0.4

0.5

V_OL(V)

Figure 9: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 °C

140

130

120

110

100

90

Open Drain 2x @ VDD = 5 V

Open Drain 2x @ VDD = 3.3 V

Open Drain 2x @ VDD = 2.5 V

Push-Pull 2x @ VDD = 5 V

Push-Pull 2x @ VDD = 3.3 V

Push-Pull 2x @ VDD = 2.5 V

80

70

60

50

40

30

20

10

0

0.25

0.5

0.75

1

1.25

1.5

1.75

2

2.25

2.5

V_OL(V)

Figure 10: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 °C, Full Range

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50

45

Open Drain 2x @ VDD = 5 V

Open Drain 2x @ VDD = 3.3 V

40

Open Drain 2x @ VDD = 2.5 V

Push-Pull 2x @ VDD = 5 V

35

Push-Pull 2x @ VDD = 3.3 V

Push-Pull 2x @ VDD = 2.5 V

30

25

20

15

10

5

0

0.1

0.2

0.3

0.4

0.5

V_OL(V)

Figure 11: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 °C

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GreenPAK Programmable Mixed-Signal Matrix

6

Connection Matrix

The Connection Matrix in the SLG46811 is used to create the internal routing for internal functional macrocells of the device once

it is programmed. The registers are programmed from the one time programmable (OTP) NVM cell during Test Mode Operation.

The output of each functional macrocell within the SLG46811 has a specific digital bit code assigned to it that is either set to active

“High” or inactive “Low”, based on the design that is created. Once the 1200 register bits within the SLG46811 are programmed

a fully custom circuit will be created.

The Connection Matrix has 53 inputs and 72 outputs. Each of the 53 inputs to the Connection Matrix is hard-wired to the digital

output of a particular source macrocell, including IO pins, LUTs, analog comparators, other digital resources, such as V_DDand

GND. The input to a digital macrocell uses a 6-bit register to select one of these 53 input lines.

For a complete list of the SLG46811’s register table, see Section 18.

Matrix Input Signal

N

Functions

GND

0

1

2

3

LUT2_0/DFF0 output

LUT2_1/DFF1 output

LUT2_3/PGen output

POR

V_DD

51

52

Matrix Inputs

0

1

2

71

N

Registers

registers [5:0]

IN0 of LUT2_0 or

registers [11:6]

IN1 of LUT2_0 or

registers [17:12]

registers [431:426]

Extended Pattern

Generator nReset

IN0 of LUT2_1 or

Clock Input of DFF1

Function

Clock Input of DFF0 Data Input of DFF0

Matrix Outputs

Figure 12: Connection Matrix

Function

Connection Matrix

GPIO7

GPIO6

LUT

GPIO6

GPIO7

GPIO8

LUT

GPIO8

Figure 13: Connection Matrix Usage Example

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GreenPAK Programmable Mixed-Signal Matrix

6.1 MATRIX INPUT TABLE

Table 20: Matrix Input Table

Matrix Decode

Matrix Input

Matrix Input Signal Function

Number

5

0

4

0

1

3

0

1

0

1

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

GND

LUT2_0/DFF0 output

2

LUT2_1/DFF1 output

3

LUT2_3/PGen output

4

LUT3_0/DFF2 output

5

LUT3_1/DFF3 output

6

LUT3_2/DFF4 output

7

LUT3_3/DFF5 output

8

LUT3_4/DFF6 output/Shift_Reg0 output

LUT3_5/DFF7 output/Shift_Reg1 output

LUT3_6/DFF8 output/Shift_Reg2 output

LUT3_7/DFF9 output/Shift_Reg3 output

CNT0 output

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

MLT0_LUT3_8/DFF10_OUT

CNT1 output

MLT1_LUT3_9/DFF11_OUT

CNT2 output

MLT2_LUT3_10/DFF12_OUT

CNT3 output

MLT3_LUT3_11/DFF13_OUT

CNT4 output

MLT4_LUT3_12/DFF14_OUT

CNT5 output

MLT5_LUT3_13/DFF15_OUT

I²C_virtual_0 Input, Extended Pattern Generator Output 0

I²C_virtual_1 Input, Extended Pattern Generator Output 1

I²C_virtual_2 Input, Extended Pattern Generator Output 2

I²C_virtual_3 Input, Extended Pattern Generator Output 3

I²C_virtual_4 Input, Extended Pattern Generator Output 4

I²C_virtual_5 Input, Extended Pattern Generator Output 5

25

26

27

28

29

30

0

1

0

1

0

1

0

1

0

1

0

1

0

I²C_virtual_6 Input, GPIO0 digital input, Extended Pattern

Generator Output 6 or SCL

I²C_virtual_7 Input, GPIO1 digital input, Extended Pattern

Generator Output 7 or SDA

31

32

0

1

0

1

0

1

0

1

0

1

0

GPIO2 Digital Input or I²C_virtual_8 Input

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GreenPAK Programmable Mixed-Signal Matrix

Table 20: Matrix Input Table (Continued)

Matrix Decode

Matrix Input

Matrix Input Signal Function

Number

5

1

4

0

3

0

2

0

1

0

1

0

1

0

1

0

1

0

1

0

GPIO3 Digital Input or I²C_virtual_9 Input

33

GPIO4 Digital Input or I²C_virtual_10 Input

34

GPIO5 Digital Input or I²C_virtual_11 Input

35

GPIO6 Digital Input or I²C_virtual_12 Input

36

GPIO7 Digital Input or I²C_virtual_13 Input

37

GPIO8 Digital Input or I²C_virtual_14 Input

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

LUT4_0/DFF16 output

GPI Digital Input

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Programmable Delay Edge Detect Output

Edge Detect Filter Output

Oscillator0 output 0

Oscillator1 output

MS ACMP Output 0

MS ACMP Output 1

MS ACMP Output 2

MS ACMP Output 3

Oscillator0 output 1

MS ASMP Data Ready Signal

POR

V_DD

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GreenPAK Programmable Mixed-Signal Matrix

6.2 MATRIX OUTPUT TABLE

Table 21: Matrix Output Table

Register Bit

Matrix Output

Number

Matrix Output Signal Function

Address

[5:0]

IN0 of LUT2_0 or Clock Input of DFF0

0

[11:6]

IN1 of LUT2_0 or Data Input of DFF0

1

[17:12]

IN0 of LUT2_1 or Clock Input of DFF1

2

[23:18]

IN1 of LUT2_1 or Data Input of DFF1

3

[29:24]

IN0 of LUT2_2 or Clock Input of PGen

4

[35:30]

IN1 of LUT2_2 or nRST of PGen

5

[41:36]

IN0 of LUT3_0 or CLK Input of DFF2

6

[47:42]

IN1 of LUT3_0 or Data of DFF2

7

[53:48]

IN2 of LUT3_0 or nRST (nSET) of DFF2

8

[59:54]

IN0 of LUT3_1 or CLK Input of DFF3

9

[65:60]

IN1 of LUT3_1 or Data of DFF3

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

[71:66]

IN2 of LUT3_1 or nRST (nSET) of DFF3

[77:72]

IN0 of LUT3_2 or CLK Input of DFF4

[83:78]

IN1 of LUT3_2 or Data of DFF4

[89:84]

IN2 of LUT3_2 or nRST (nSET) of DFF4

[95:90]

IN0 of LUT3_3 or CLK Input of DFF5

[101:96]

[107:102]

[113:108]

[119:114]

[125:120]

[131:126]

[137:132]

[143:138]

[149:144]

[155:150]

[161:156]

[167:162]

[173:168]

[179:174]

IN1 of LUT3_3 or Data of DFF5

IN2 of LUT3_3 or nRST (nSET) of DFF5

IN0 of LUT3_4 or CLK Input of DFF6 or Clock Input of Shift_Reg0

IN1 of LUT3_4 or Data of DFF6 or Data Input of Shift_Reg0

IN2 of LUT3_4 or nRST (nSET) of DFF6 or nRST (nSET) of Shift_Reg0

IN0 of LUT3_5 or CLK Input of DFF7 or Clock Input of Shift_Reg1

IN1 of LUT3_5 or Data of DFF7 or Data Input of Shift_Reg1

IN2 of LUT3_5 or nRST (nSET) of DFF7 or nRST (nSET) of Shift_Reg1

IN0 of LUT3_6 or CLK Input of DFF8 or Clock Input of Shift_Reg2

IN1 of LUT3_6 or Data of DFF8 or Data Input of Shift_Reg2

IN2 of LUT3_6 or nRST (nSET) of DFF8 or nRST (nSET) of Shift_Reg2

IN0 of LUT3_7 or CLK Input of DFF9 or Clock Input of Shift_Reg3

IN1 of LUT3_7 or Data of DFF9 or Data Input of Shift_Reg3

IN2 of LUT3_7 or nRST (nSET) of DFF9 or nRST (nSET) of Shift_Reg3

IN0 of LUT3_8 or CLK Input of DFF10 Delay0 Input (or Counter0 nRST Input) Up input

of FSM

[185:180]

[191:186]

[197:192]

IN1 of LUT3_8 or nRST (nSET) of DFF10 Delay0 Input (or Counter0 nRST Input) or

DLY/CNT/FSM External CLK input

31

32

IN2 of LUT3_8 or Data of DFF10 Delay0 Input (or Counter0 nRST Input) or FSM

Reset/Set input

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Table 21: Matrix Output Table (Continued)

Register Bit

Matrix Output

Number

Matrix Output Signal Function

Address

[203:198]

[209:204]

[215:210]

[221:216]

[227:222]

[233:228]

[239:234]

[245:240]

[251:246]

[257:252]

[263:258]

[269:264]

[275:270]

[281:276]

[287:282]

[293:288]

[299:294]

[305:300]

[311:306]

[317:312]

[323:318]

[329:324]

[335:330]

[341:336]

[347:342]

[353:348]

[359:354]

[365:360]

[371:366]

[377:372]

[383:378]

[389:384]

[395:390]

[401:396]

[407:402]

[413:408]

[419:414]

IN0 of LUT3_9 or CLK Input of DFF11 Delay1 Input (or Counter1 nRST Input)

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

IN1 of LUT3_9 or nRST (nSET) of DFF11 Delay1 Input (or Counter1 nRST Input)

IN2 of LUT3_9 or Data of DFF11 Delay1 Input (or Counter1 nRST Input)

IN0 of LUT3_10 or CLK Input of DFF12 Delay2 Input (or Counter1 nRST Input)

IN1 of LUT3_10 or nRST (nSET) of DFF12 Delay2 Input (or Counter1 nRST Input)

IN2 of LUT3_10 or Data of DFF12 Delay2 Input (or Counter2 nRST Input)

IN0 of LUT3_11 or CLK Input of DFF13 Delay3 Input (or Counter3 nRST Input)

IN1 of LUT3_11 or nRST (nSET) of DFF13 Delay3 Input (or Counter3 nRST Input)

IN2 of LUT3_11 or Data of DFF13 Delay3 Input (or Counter3 nRST Input)

IN0 of LUT3_12 or CLK Input of DFF14 Delay4 Input (or Counter4 nRST Input)

IN1 of LUT3_12 or nRST (nSET) of DFF14 Delay4 Input (or Counter4 nRST Input)

IN2 of LUT3_12 or Data of DFF14 Delay4 Input (or Counter4 nRST Input)

IN0 of LUT3_13 or CLK Input of DFF15 Delay5 Input (or Counter5 nRST Input)

IN1 of LUT3_13 or nRST (nSET) of DFF15 Delay5 Input (or Counter5 nRST Input)

IN2 of LUT3_13 or Data of DFF15 Delay5 Input (or Counter5 nRST Input)

IN0 of LUT4_0 or CLK Input of DFF16

IN1 of LUT4_0 or Data of DFF16

IN2 of LUT4_0 or nRST (nSET) of DFF16

IN3 of LUT4_0

Programmable Delay/Edge Detect Input

Filter/Edge Detect Input

GPIO0 Digital Output

GPIO1 Digital Output

GPIO2, Digital Output

GPIO2, Digital Output OE

GPIO3, Digital Output

GPIO3, Digital Output OE

GPIO4 Digital Output

GPIO5 Digital Output

GPIO6 Digital Output

GPIO7 Digital Output

GPIO7 Digital Output OE

GPIO8 Digital Output

GPIO8 Digital Output OE

MS ACMP Enable Input

Reset of MS ACMP DFFs

OSC Enable

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GreenPAK Programmable Mixed-Signal Matrix

Table 21: Matrix Output Table (Continued)

Register Bit

Matrix Output

Number

Matrix Output Signal Function

Address

[425:420]

[431:426]

Extended Pattern Generator Clock

Extended Pattern Generator nReset

70

71

Note 1 For each Address, the two most significant bits are unused.

6.3 CONNECTION MATRIX VIRTUAL INPUTS

As mentioned previously, the Connection Matrix inputs come from the outputs of various digital macrocells on the device. Fifteen

of the Connection Matrix inputs have the special characteristic that the state of these signal lines comes from a corresponding

data bit written as a register value via I²C. This gives the user the ability to write data via the serial channel, and have this

information translated to the inputs of other macrocells through Connection Matrix. The I²C address for reading and writing these

register values is byte 0x39, 0x3A<6:0>.

An I²C write command to these register bits will set the signal values going into the Connection Matrix to the desired state. A read

command to these register bits will read either the original data values coming from the NVM memory bits (that were loaded during

the initial device startup), or the values from a previous write command (if that has happened).

Connection Matrix Virtual Inputs are shared with input function of GPIO and Pattern Generator input.

If the virtual input mode is selected, an I²C write command to these register bits will set the signal values going into the Connection

Matrix to the desired state. A read command to these register bits will read either the original data values coming from the NVM

memory bits (that were loaded during the initial device startup), or the values from a previous write command (if that has hap-

pened). The I²C disable/enable registers [1078:1072] and [1184] select whether the Connection Matrix input comes from the Pin

input or from the I²C virtual input. All I²C virtual inputs with shared functions are listed below:



Select Pattern Generator 0 or Virtual Input 0

Select Pattern Generator 1 or Virtual Input 1

Select Pattern Generator 2 or Virtual Input 2

Select Pattern Generator 3 or Virtual Input 3

Select Pattern Generator 4 or Virtual Input 4

Select Pattern Generator 5 or Virtual Input 5

Select Pattern Generator 6 or Virtual Input 6 or GPI (GPIO0)

Select Pattern Generator 7 or Virtual Input 7 or GPI (GPIO1)

Select Virtual Input 8 or GPI (GPIO2)

Select Virtual Input 9 or GPI (GPIO3)

Select Virtual Input 10 or GPI (GPIO4)

Select Virtual Input 11 or GPI (GPIO5)

Select Virtual Input 12 or GPI (GPIO6)

Select Virtual Input 13 or GPI (GPIO7)

Select Virtual Input 14 or GPI (GPIO8)

See Table for Connection Matrix Virtual Inputs.

Table 22: Connection Matrix Virtual Inputs

Matrix Input

Number

Register Bit

Addresses (d)

Matrix Input Signal Function

Extended Pattern Generator 0

or I²C_virtual_0 Input

24

25

26

[456]

[457]

[458]

Extended Pattern Generator 1

or I²C_virtual_1 Input

Extended Pattern Generator 2

or I²C_virtual_2 Input

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Table 22: Connection Matrix Virtual Inputs (Continued)

Matrix Input

Number

Register Bit

Addresses (d)

Matrix Input Signal Function

Extended Pattern Generator 3

or I²C_virtual_3 Input

27

[459]

[460]

[461]

[462]

[463]

Extended Pattern Generator 4

or I²C_virtual_4 Input

28

29

30

31

Extended Pattern Generator 5

or I²C_virtual_5 Input

Extended Pattern Generator 6

or I²C_virtual_6 Input or GPI (GPIO0)

Extended Pattern Generator 7

or I²C_virtual_7 Input or GPI (GPIO1)

32

33

34

35

36

37

38

GPI (GPIO2) or I²C_virtual_8 Input

GPI (GPIO3) or I²C_virtual_9 Input

GPI (GPIO4) or I²C_virtual_10 Input

GPI (GPIO5) or I²C_virtual_11 Input

GPI (GPIO6) or I²C_virtual_12 Input

GPI (GPIO7) or I²C_virtual_13 Input

GPI (GPIO8) or I²C_virtual_14 Input

[464]

[465]

[466]

[467]

[468]

[469]

[470]

6.4 CONNECTION MATRIX VIRTUAL OUTPUTS

The digital outputs of the various macrocells are routed to the Connection Matrix to enable interconnections to the inputs of other

macrocells in the device. At the same time, it is possible to read the state of each of the macrocell outputs as a register value via

I²C. This option, called Connection Matrix Virtual Outputs, allows the user to remotely read the values of each macrocell output.

The I²C addresses for reading these register values are bytes 0x36 (053) to 0x3C (060) (except for registers [470:456]). Write

commands to these same register values will be ignored (with the exception of the Virtual Input register bits at registers [470:456]).

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7

Combination Function Macrocells

The SLG46811 has 12 combination function macrocells that can serve more than one logic or timing function. In each case, they

can serve as a Look Up Table (LUT), or as another logic or timing function. See the list below for the functions that can be

implemented in these macrocells.



Two macrocells that can serve as either 2-bit LUT or as D Flip-Flop

One macrocell that can serve as either 2-bit LUT or as Programmable Pattern Generator (PGen)

Four macrocells that can serve as either 3-bit LUTs or as D Flip-Flops with Set/Reset Input

Four macrocells that can serve as either 3-bit LUTs or as D Flip-Flops with Set/Reset Input or as Shift Register

One macrocell that can serve as either 4-bit LUT or as D Flip-Flop with Set/Reset Input

Inputs/Outputs for the 12 combination function macrocells are configured from the connection matrix with specific logic functions

being defined by the state of configuration bits.

When used as a LUT to implement combinatorial logic functions, the outputs of the LUTs can be configured to any user defined

function, including the following standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR).

7.1 2-BIT LUT OR D FLIP-FLOP MACROCELLS

There is one macrocell that can serve as either 2-bit LUT or as D Flip-Flop. When used to implement LUT functions, the 2-bit LUT

takes in two input signals from the connection matrix and produce a single output, which goes back into the connection matrix.

When used to implement D Flip-Flop function, the two input signals from the connection matrix go to the data (D) and clock (CLK)

inputs for the Flip-Flop, with the output going back to the connection matrix.

The operation of the D Flip-Flop and LATCH will follow the functional descriptions below:

DFF: CLK is rising edge triggered, then Q = D; otherwise Q will not change

LATCH: when CLK is Low, then Q = D; otherwise Q remains its previous value (input D has no effect on the output, when CLK is

High).

register [1019] DFF or Latch Select

IN1

register [1018] Output Select (Q or nQ)

S0

From Connection Matrix Output [1]

register [1017] DFF Initial Polarity Select

OUT

2-bit LUT0

0: 2-bit LUT0 IN1

1: DFF0 Data

S1

IN0

LUT Truth

Table

To Connection Matrix

Input [0]

S0

S1

4-bits NVM

registers [1019:1016]

0: 2-bit LUT0 Out

1: DFF0 Out

DFF/Latch

Registers

D

From Connection Matrix

Output [0]

S0

S1

Q/nQ

DFF0

0: 2-bit LUT0 IN0

1: DFF0 CLK

CLK

1-bit NVM

register [1024]

Figure 14: 2-bit LUT0 or DFF0

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register [1023] DFF or Latch Select

register [1022] Output Select (Q or nQ)

register [1021] DFF Initial Polarity Select

IN1

S0

From Connection Matrix Output [3]

OUT

2-bit LUT1

0: 2-bit LUT1 IN1

1: DFF1 Data

S1

IN0

LUT Truth

Table

To Connection Matrix

S0

Input [1]

4-bits NVM

registers [1023:1020]

S1

0: 2-bit LUT1 Out

1: DFF1 Out

DFF/Latch

Registers

D

From Connection Matrix

Output [2]

S0

S1

Q/nQ

DFF1

0: 2-bit LUT1 IN0

1: DFF1 CLK

CLK

1-bit NVM

register [1025]

Figure 15: 2-bit LUT1 or DFF1

7.1.1 2-Bit LUT or D Flip-Flop Macrocell Used as 2-Bit LUT

This macrocell, when programmed for a LUT function, uses a 4-bit register to define their output function:

2-Bit LUT0 is defined by register [1019:1016]

2-Bit LUT1 is defined by register [1023:1020]

Table 23: 2-bit LUT2_0 to 2-bit LUT2_1 Truth Table

IN1

0

IN0

0

OUT LUT0

OUT LUT1

Register [1016]

Register [1017]

Register [1018]

Register [1019]

Register [1020]

Register [1021]

Register [1022]

Register [1023]

LSB

0

1

0

1

MSB

Table 24 shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be created

within each of the 2-bit LUT logic cells.

Table 24: 2-bit LUT Standard Digital Functions

Function

AND-2

MSB

LSB

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

NAND-2

OR-2

NOR-2

XOR-2

XNOR-2

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7.2 2-BIT LUT OR PROGRAMMABLE PATTERN GENERATOR

The SLG46811 has one combination function macrocell that can serve as a logic or timing function. This macrocell can serve as

a Look Up Table (LUT), or Programmable Pattern Generator (PGen).

When used to implement LUT functions, the 2-bit LUT takes in two input signals from the connection matrix and produces a single

output, which goes back into the connection matrix. When used as a LUT to implement combinatorial logic functions, the outputs

of the LUT can be configured to any user defined function, including the following standard digital logic devices (AND, NAND,

OR, NOR, XOR, XNOR). The user can also define the combinatorial relationship between inputs and outputs to be any selectable

function.

It is possible to define the RST level for the PGen macrocell. There are both high level reset (RST) and a low level reset (nRST)

options available which are selected by register [1027]. When operating as a Programmable Pattern Generator, the output of the

macrocell will clock out a sequence of two to sixteen bits that are user selectable in their bit values, and user selectable in the

number of bits (up to sixteen) that are output before the pattern repeats.

From Connection Matrix Output [4]

From Connection Matrix Output [5]

In0

In1

OUT

2-bit LUT2

LUT Truth

Table

To Connection Matrix Input [3]

S0

S1

registers [1031:1028]

0: 2-bit LUT2 OUT

1: PGen OUT

Pattern

Size

nRST/RST

CLK

PGen

OUT

PGen

Data

register [1026]

registers [1047:1032]

Figure 16: 2-bit LUT2 or PGen

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V

DD

t

nRST

CLK

1

2

6

8

16 17

0

3

4

5

7

9

11

10

14 15

12 13

t

OUT

D6

D7

D5

D10

D8

D4

D3

D2

D1

D15

D11

D9

D0

D15

D14

D13

D12

D0

Figure 17: PGen Timing Diagram

Table 25: 2-bit LUT2_2 Truth Table

IN1

0

IN0

0

OUT

register [1028]

register [1029]

register [1030]

register [1031]

LSB

0

1

0

1

MSB

This macrocell, when programmed for a LUT function, uses a 4-bit register to define their output function:

2-Bit LUT2_2 is defined by registers [1031:1028]

Table 26 shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be created

within each of the 2-bit LUT logic cells.

Table 26: 2-bit LUT Standard Digital Functions

Function

AND-2

MSB

LSB

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

NAND-2

OR-2

NOR-2

XOR-2

XNOR-2

7.3 3-BIT LUT OR D FLIP-FLOP WITH SET/RESET MACROCELLS OR SHIFT REGISTER MACROCELLS

There are four macrocells that can serve as 3-bit LUT or as DFF/LATCH or as Shift Register. It is also possible to define the active

level (Q or nQ) for the macrocell’s output by registers [958], [974], [990], [1006]. DFF/Shift Register or LUT are selected by

registers [951:948]. When used to implement LUT functions, the 3-bit LUT takes in three input signals from the connection matrix

and produce a single output, which goes back into the connection matrix.

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When used to implement Shift Register, the three input signals from the connection matrix go to the data (D_IN), clock (CLK),

and Set/Reset (nSET/nRST) inputs for the Shift Register, with the output going back to the connection matrix. It is possible to

define the active level for the reset/set input of Shift Register macrocell which is selected by registers [955], [971], [987], [1003].

The input data (D_IN) writes into LSB. The Shift Register length (up to 8 bits/memory cells) is selected by registers [954:952],

registers [970:968], registers [986:984], and registers [1002:1000]. Shift register length = 1 (corresponding registers = 0) means

that DFF/LATCH function is selected. Please note that D and CLK inputs of the Shift Register should remain unchanged while

the I²C master is reading data from the Shift Register. Otherwise, the I²C master can read the wrong data. Signals at D and CLK

inputs of the Shift Register will be ignored while I²C master is writing a new data to the Shift Register macrocell. Also, note that

the reset input of the Shift Register has higher priority to the Shift Register than the I²C write routine.

When used to implement D Flip-Flop/LATCH function, the three input signals from the connection matrix go to the data (D_IN),

clock (CLK), and Set/Reset (nSET/nRST) inputs for the Flip-Flop/LATCH, with the output going back to the connection matrix. It

is possible to define the active level for the reset/set input (nSET/nRST_sel which is selected by registers [956], [972], [988],

[1004]) of DFF/LATCH macrocell. LATCH or DFF configuration is selected by registers [959], [975], [991], [1007].

The operation of the D Flip-Flop and LATCH will follow the functional descriptions below:

DFF: CLK is rising edge triggered, then Q = D; otherwise Q will not change.

LATCH: when CLK is Low, then Q = D; otherwise Q remains its previous value (input D has no effect on the output, when CLK

is High).

Special care must be taken when writing new data to bytes 78h, 7Ah, 7Ch, 7Eh via I²C. If LUT/DFF/LATCH/Shift_Register

macrocells configured as DFF or LATCH, writing new data to LSB of bytes 78h, 7Ah, 7Ch, 7Eh can change the current state of

DFF (LATCH).

It's allowed to read data from the Shift Register. Note that CLK signal of the Shift Register should be low when getting access to

the Shift Register macrocell via I²C.

LUT IN1

DFF data in

ShRg data in

From Connectinon

Matrix Output [19]

8 memory cells

S1

S0

D_in

CLK

LUT IN0

DFF CLK

ShRg CLK

From Connectinon

Matrix Output [18]

S1

S0

From Connectinon

Matrix Output [20]

LUT IN2

DFF nSet/nRST

ShRg nSet/nRST

S0

S1

nSET/nRST

SET/RST

LATCH/DFF_sel

nSET/nRST_sel Out[7:0]

SET/RST_act_level

8

3-bit LUT

[7]

[0]

111

To Connection Matrix

Input [8]

.

S0

3

S1

LUT config

000

S0

S1

ShRg/LUT_sel

1-bit NVM

ShRg_

length

[2:0]

3

7

4

nQ/Q_sel

7-bit NVM

Figure 18: 3-bit LUT4 or DFF6 or Shift Register 0

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LUT IN1

DFF data in

ShRg data in

From Connectinon

Matrix Output [22]

8 memory cells

S1

S0

D_in

CLK

LUT IN0

DFF CLK

ShRg CLK

From Connectinon

Matrix Output [21]

S1

S0

From Connectinon

Matrix Output [23]

LUT IN2

DFF nSet/nRST

ShRg nSet/nRST

S0

S1

nSET/nRST

SET/RST

LATCH/DFF_sel

nSET/nRST_sel Out[7:0]

SET/RST_act_level

8

3-bit LUT

[7]

[0]

111

To Connection Matrix

Input [9]

S0

.

3

S1

LUT config

000

S0

S1

ShRg/LUT_sel

1-bit NVM

ShRg_

length

[2:0]

3

7

4

nQ/Q_sel

7-bit NVM

Figure 19: 3-bit LUT5 or DFF7 or Shift Register 1

LUT IN1

DFF data in

ShRg data in

From Connectinon

Matrix Output [25]

8 memory cells

S1

S0

D_in

CLK

LUT IN0

DFF CLK

ShRg CLK

From Connectinon

Matrix Output [24]

S1

S0

From Connectinon

Matrix Output [26]

LUT IN2

DFF nSet/nRST

ShRg nSet/nRST

S0

S1

nSET/nRST

SET/RST

LATCH/DFF_sel

nSET/nRST_sel Out[7:0]

SET/RST_act_level

8

3-bit LUT

[7]

[0]

111

To Connection Matrix

Input [10]

S0

.

3

S1

LUT config

000

S0

S1

ShRg/LUT_sel

1-bit NVM

ShRg_

length

[2:0]

3

7

4

nQ/Q_sel

7-bit NVM

Figure 20: 3-bit LUT6 or DFF8 or Shift Register 2

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LUT IN1

DFF data in

ShRg data in

From Connectinon

Matrix Output [28]

8 memory cells

S1

S0

D_in

CLK

LUT IN0

DFF CLK

ShRg CLK

From Connectinon

Matrix Output [27]

S1

S0

From Connectinon

Matrix Output [29]

LUT IN2

DFF nSet/nRST

ShRg nSet/nRST

S0

S1

nSET/nRST

SET/RST

nSET/nRST_sel Out[7:0]

SET/RST_act_level LATCH/DFF_sel

8

3-bit LUT

[7]

[0]

To Connection Matrix

Input [11]

S0

111

.

3

S1

LUT config

000

S0

S1

ShRg/LUT_sel

1-bit NVM

ShRg_

length

[2:0]

3

7

4

nQ/Q_sel

7-bit NVM

Figure 21: 3-bit LUT7 or DFF9 or Shift Register 3

Inital Value is loaded from NVM to Shift Register

V_DD

Data

CLK

POR

ShReg_Out[7:0]

Initial Value 10011011 (x9B)

00110111 01101111 11011110 10111100 01111000 11110000 11100000 11000001 10000011 00000111 00001111

(Internal Signal)

Q=ShReg_Out[0]

(see note 1)

Q=ShReg_Out[7]

(see note 2)

MSB

LSB

x9

xB

Initial Value is transmitted (x9B)

Input Data are transmitted

Note1 :Macrocell is configured as DFF

Note2 : Macrocell is configured as 8-bit Shift Register

Figure 22: DFF6 to DFF9 or Shift Register 0 to Shift Register 3 Operation

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Inital Value is loaded from NVM to Shift Register

V_DD

Data

CLK

POR

ShReg_Out[7:0]

(Internal Signal)

Initial Value 10011011 (x9B)

00000010 00000101 00001010 00010100 00101000 01010000 10100000

00000000

00000000 00000001

nReset

(see note 1)

Q=ShReg_Out[0]

(see note 2)

Q=ShReg_Out[7]

(see note 3)

8 Clk pulses

Note1 : DFF Setting “Initial Value: 1”

Note2 : Macrocell is configured as DFF

Note3 : Macrocell is configured as 8-bits

Figure 23: DFF6 to DFF9 or Shift Register 0 to Shift Register 3 Operation, nReset Option, DFF Initial Value: 1

Inital Value is loaded from NVM to Shift Register

V_DD

Data

CLK

POR

ShReg_Out[7:0]

(Internal Signal)

Initial Value 10011011

00000010 00000101

00000001

00000000

00000001 00000011 00000111

00000000

nReset

(see note 1)

Q=ShReg_Out[0]

(see note 2)

Q=ShReg_Out[7]

(see note 3)

Note1 : DFF Setting “Initial Value: 1”

Note2 : Macrocell is configured as DFF

Note3 : Macrocell is configured as 8-bits

Figure 24: DFF6 to DFF9 or Shift Register 0 to Shift Register 3 Operation, nReset Option, DFF Initial Value: 1, Case 1

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Inital Value is loaded from NVM to Shift Register

V_DD

Data

CLK

POR

ShReg_Out[7:0]

(Internal Signal)

nReset

Initial Value 00011011

11011110 10111101

00000000

00000001 00000011 00000111

00110111 01101111

(see note 1)

Q=ShReg_Out[0]

(see note 2)

Q=ShReg_Out[7]

(see note 3)

Note1 : DFF Setting “Initial Value: 1”

Note2 : Macrocell is configured as DFF

Note3 : Macrocell is configured as 8-bits

Figure 25: DFF6 to DFF9 or Shift Register 0 to Shift Register 3 Operation, nReset Option, DFF Initial Value: 1, Case 2

Inital Value is loaded from NVM to Shift Register

V_DD

Data

CLK

POR

ShReg_Out[7:0]

Initial Value 00011010 (x1A)

11111100 11111001 11110010 11100100 11001000 10010000 00100000 11111111 11111111

11111111 11111110

(Internal Signal)

nSet

(see note 1)

Q=ShReg_Out[0]

(see note 2)

Q=ShReg_Out[7]

(see note 3)

8 Clk pulses

Note1 : DFF Setting “Initial Value: 0”

Note2 : Macrocell is configured as DFF

Note3 : Macrocell is configured as 8-bits

Figure 26: DFF6 to DFF9 or Shift Register 0 to Shift Register 3 Operation, nSet Option, DFF Initial Value: 0

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Inital Value is loaded from NVM to Shift Register

V_DD

Data

CLK

POR

ShReg_Out[7:0]

(Internal Signal)

Initial Value 00011010

11111111

11111100 11111001

11111111

11111110 11111100 11111000

11111110

nSet

(see note 1)

Q=ShReg_Out[0]

(see note 2)

Q=ShReg_Out[7]

(see note 3)

Note1 : DFF Setting “Initial Value: 0”

Note2 : Macrocell is configured as DFF

Note3 : Macrocell is configured as 8-bits

Figure 27: DFF6 to DFF9 or Shift Register 0 to Shift Register 3 Operation, nSet Option, DFF Initial Value: 0, Case 1

Inital Value is loaded from NVM to Shift Register

V_DD

Data

CLK

POR

ShReg_Out[7:0]

(Internal Signal)

Initial Value 10011010

00110101

11010100 10101001

11111111

11111110 11111100 11111000

01101010

nSet

(see note 1)

Q=ShReg_Out[0]

(see note 2)

Q=ShReg_Out[7]

(see note 3)

Note1 : DFF Setting “Initial Value: 0”

Note2 : Macrocell is configured as DFF

Note3 : Macrocell is configured as 8-bits

Figure 28: DFF6 to DFF9 or Shift Register 0 to Shift Register 3 Operation, nSet Option, DFF Initial Value: 0, Case 2

7.3.1 3-Bit LUT or D Flip-Flop Macrocells Used as 3-Bit LUTs

Each macrocell, when programmed for a LUT function, uses an 8-bit register to define their output function:

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3-Bit LUT3_0 is defined by registers [895:888]

3-Bit LUT3_1 is defined by registers [903:896]

3-Bit LUT3_2 is defined by registers [911:904]

3-Bit LUT3_3 is defined by registers [919:912]

3-Bit LUT3_4 is defined by registers [967:960]

3-Bit LUT3_5 is defined by registers [983:976]

3-Bit LUT3_6 is defined by registers [999:992]

3-Bit LUT3_7 is defined by registers [1015:1008]

Table 27: 3-bit LUT3_0 to 3-bit LUT3_9 Truth Table

0

1

0

1

0

1

0

1

0

1

0

1

0

1

register

[888]

register

[896]

register

[904]

register

[912]

register

[960]

register

[976]

register

[992]

register

[1008]

LSB

register

[889]

register

[897]

register

[905]

register

[913]

register

[961]

register

[977]

register

[993]

register

[1009]

register

[890]

register

[898]

register

[906]

register

[914]

register

[962]

register

[978]

register

[994]

register

[1010]

register

[891]

register

[899]

register

[907]

register

[915]

register

[963]

register

[979]

register

[995]

register

[1011]

register

[892]

register

[900]

register

[908]

register

[916]

register

[964]

register

[980]

register

[996]

register

[1012]

register

[893]

register

[901]

register

[909]

register

[917]

register

[965]

register

[981]

register

[997]

register

[1013]

register

[894]

register

[902]

register

[910]

register

[918]

register

[966]

register

[982]

register

[998]

register

[1014]

register

[895]

register

[903]

register

[911]

register

[919]

register

[967]

register

[983]

register

[999]

register

[1015]

MSB

Table 28 shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be created

within each of the four 3-bit LUT logic cells.

Table 28: 3-bit LUT Standard Digital Functions

Function

AND-3

MSB

LSB

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

NAND-3

OR-3

NOR-3

XOR-3

XNOR-3

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7.4 3-BIT LUT OR D FLIP-FLOP WITH SET/RESET MACROCELLS

There are 4 macrocells that can serve as either 3-bit LUTs or as D Flip-Flops with Set/Reset inputs. When used to implement

LUT functions, the 3-bit LUTs each take in three input signals from the connection matrix and produce a single output, which

goes back into the connection matrix. When used to implement D Flip-Flop function, the three input signals from the connection

matrix go to the data (D) and clock (CLK), and Reset/Set (nRST/nSET) inputs for the Flip-Flop, with the output going back to the

connection matrix. It is possible to define the active level for the reset/set input of DFF/LATCH macrocell. There are both active

high level Reset/Set (RST/SET) and active low level Reset/Set (nRST/nSET) options available which are selected by register

[890].

DFF2 operation will flow the functional description below:



If register [892] = 0, and the CLK is rising edge triggered, then Q = D, otherwise Q will not change.

If register [892] = 1, then data from D is written into the DFF by the rising edge on CLK and output to Q by the falling edge on

CLK.

register [895] DFF or Latch Select

register [894] Output Select (Q or nQ)

register [893] DFF Initial Polarity Select

register [892] Q1 or Q2 Select

register [891] DFF nRST or nSET Select

register [890] Active level selection for RST/

SET

IN2

IN1

From Connection

Matrix Output [8]

S0

S1

OUT

3-bit LUT0

IN0

LUT Truth

Table

From Connection

Matrix Output [7]

To Connection Matrix

S0

S1

Input [4]

S0

S1

8-bits NVM

registers [895:888]

From Connection

Matrix Output [6]

S0

S1

DFF/Latch

Registers

0

1

Q/nQ

DFF

D

Q

D

Q

nRST/

nSET

nRST/

CL

nSET

CL

nRST/nSET

CLK

register [892]

1-bit NVM

register [920]

Figure 29: 3-bit LUT0 or DFF2

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register [903] DFF or Latch Select

register [902] Output Select (Q or nQ)

register [901] DFF Initial Polarity Select

register [900] DFF nRST or nSET Select

register [899] Active level selection for RST/

SET

IN2

IN1

From Connection

Matrix Output [11]

S0

S1

OUT

3-bit LUT1

IN0

LUT Truth

Table

From Connection

Matrix Output [10]

To Connection Matrix

S0

S1

Input [5]

S0

8-bits NVM

registers [903:896]

S1

DFF/Latch

Registers

D

From Connection

Matrix Output [9]

S0

S1

^nRST/nSETDFF3

Q/nQ

RST/SET

CLK

1-bit NVM

register [921]

Figure 30: 3-bit LUT1 or DFF3

register [911] DFF or Latch Select

register [910] Output Select (Q or nQ)

register [909] DFF Initial Polarity Select

register [908] DFF nRST or nSET Select

register [907] Active level selection for RST/

SET

IN2

From Connection

Matrix Output [14]

S0

S1

IN1

IN0

OUT

3-bit LUT2

LUT Truth

Table

From Connection

Matrix Output [13]

To Connection Matrix

S0

S1

S0

S1

Input [6]

8-bits NVM

registers [911:904]

DFF/Latch

Registers

D

From Connection

Matrix Output [12]

S0

S1

^nRST/nSETDFF4

RST/SET

Q/nQ

CLK

1-bit NVM

register [922]

Figure 31: 3-bit LUT2 or DFF4

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register [919] DFF or Latch Select

register [918] Output Select (Q or nQ)

register [917] DFF Initial Polarity Select

register [916] DFF nRST or nSET Select

register [915] Active level selection for RST/

SET

IN2

IN1

From Connection

Matrix Output [17]

S0

S1

OUT

3-bit LUT3

IN0

LUT Truth

Table

From Connection

Matrix Output [16]

To Connection Matrix

S0

S1

S0

S1

Input [9]

8-bits NVM

registers [919:912]

DFF

Registers

D

From Connection

Matrix Output [15]

S0

S1

nRST/nSET

RST/SET

DFF5

Q/nQ

CLK

1-bit NVM

register [923]

Figure 32: 3-bit LUT3 or DFF5

7.5 4-BIT LUT OR D FLIP-FLOP WITH SET/RESET MACROCELL

There is one macrocell that can serve as either a 4-bit LUT or as a D Flip-Flop with Set/Reset inputs. When used to implement

LUT functions, the 4-bit LUT takes in four input signals from the connection matrix and produce a single output, which goes back

into the connection matrix. When used to implement D Flip-Flop function, the input signals from the connection matrix go to the

data (D) and clock (CLK), and Reset/Set (nRST/nSET) inputs for the Flip-Flop, with the output going back to the connection matrix



If register [943] = 0, and the CLK is rising edge triggered, then Q = D, otherwise Q will not change.

If register [943] = 1, then data from D is written into the DFF by the rising edge on CLK and output to Q by the falling edge on

CLK.

It is possible to define the active level for the reset/set input of DFF/LATCH macrocell. There are both active high level reset/set

(RST/SET) and active low level reset/set (nRST/nSET) options available which are selected by register [938].

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From Connection

register [943] DFF or Latch Select

S0

S1

Matrix Output [51]

register [942] Output Select (Q or nQ)

register [941] DFF Initial Polarity Select

register [940] Q1 or Q2 Select

register [939] DFF nRST or nSET Select

register [938] Active level selection for RST/SET

IN3

IN2

IN1

From Connection

Matrix Output [50]

S0

S1

OUT

4-bit LUT0

IN0

LUT Truth

Table

From Connection

Matrix Output [49]

To Connection Matrix

S0

S1

Input [39]

S0

16-bits NVM

registers [943:928]

S1

DFF/Latch

Registers

D

From Connection

Matrix Output [48]

S0

S1

^nRST/nSETDFF16

RST/SET

Q/nQ

Q1/Q2

CLK

Select

register [940]

1-bit NVM

register [927]

Figure 33: 4-bit LUT0 or DFF16

7.5.1 4-Bit LUT Macrocell Used as 4-Bit LUT

Table 29: 4-bit LUT0 Truth Table

IN3

0

IN2

0

IN1

0

IN0

0

OUT

register [928]

register [929]

register [930]

register [931]

register [932]

register [933]

register [934]

register [935]

register [936]

register [937]

register [938]

register [939]

register [940]

register [941]

register [942]

register [943]

LSB

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

MSB

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This macrocell, when programmed for a LUT function, uses a 16-bit register to define their output function:

4-Bit LUT0 is defined by registers [943:928]

Table 30: 4-bit LUT Standard Digital Functions

Function

AND-4

MSB

LSB

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

NAND-4

OR-4

NOR-4

XOR-4

XNOR-4

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8

Multi-Function Macrocells

The SLG46811 has 6 Multi-Function macrocells that can serve more than one logic or timing function. In each case, they can

serve as a LUT, DFF with flexible settings, or as CNT/DLY with multiple modes such as One Shot, Frequency Detect, Edge Detect,

and others. Also, the macrocell is capable to combine those functions: LUT/DFF connected to CNT/DLY or CNT/DLY connected

to LUT/DFF, see Figure 34.

See the list below for the functions that can be implemented in these macrocells:



Five macrocells that can serve as 3-bit LUTs/D Flip-Flops and as 8-Bit Counter/Delays

One macrocell that can serve as a 3-bit LUT/D Flip-Flop and as 8-Bit Counter/Delay/FSM

To Connection Matrix

From Connection

Matrix

To Connection

Matrix

From Connection

Matrix

To Connection

Matrix

LUT

or

DFF

LUT

or

DFF

CNT/DLY

Figure 34: Possible Connections Inside Multi-Function Macrocell

Inputs/Outputs for the 6 Multi-Function function macrocells are configured from the connection matrix with specific logic functions

being defined by the state of NVM bits.

When used as a LUT to implement combinatorial logic functions, the outputs of the LUTs can be configured to any user defined

function, including the following standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR).

8.1 3-BIT LUT OR DFF/LATCH WITH 8-BIT COUNTER/DELAY MACROCELLS

There are five macrocells that can serve as 3-bit LUTs/D Flip-Flops and as 8-Bit Counter/Delays.

When used to implement LUT functions, the 3-bit LUTs each take in three input signals from the connection matrix and produce

a single output, which goes back into the connection matrix or can be connected to CNT/DLY's input.

When used to implement D Flip-Flop function, the three input signals from the connection matrix go to the data (D), clock (CLK),

and Set/Reset (nRST/nSET) inputs of the Flip-Flop, with the output going back to the connection matrix or to the CNT/DLY's input.

When used to implement Counter/Delays, each macrocell has a dedicated matrix input connection. For flexibility, each of these

macrocells has a large selection of internal and external clock sources, as well as the option to chain from the output of the

previous (N-1) CNT/DLY macrocell, to implement longer count/delay circuits. These macrocells can also operate in a One-Shot

mode, which will generate an output pulse of user-defined width. They can also operate in a Frequency Detection or Edge

Detection mode.

Counter/Delay macrocell has an initial value, which define its initial value after GPAK is powered up. It is possible to select initial

Low or initial High, as well as initial value defined by a Delay In signal.

For example, in case initial LOW option is used, the rising edge delay will start operation.

For timing diagrams refer to sections 7.1 and 8.2.

Note: After two DFF – counters initialize with counter data = 0 after POR.

Initial state = 1 – counters initialize with counter data = 0 after POR.

Initial state = 0 And After two DFF is bypass – counters initialize with counter data after POR.

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GreenPAK Programmable Mixed-Signal Matrix

CNT/DLY0/FSM macrocell has an optional Finite State Machine (FSM) function. There is one additional Up/Down matrix input in

FSM mode.

8.1.1 3-Bit LUT or 8-Bit CNT/DLY Block Diagrams

register [799] DFF or Latch Select

register [798] Output Select (Q or

From Connection

Matrix Output [32]

nQ)

register [797] (nRST or nSET) from

matrix Output

register [796] DFF Initial Polarity

Select

IN2

IN1

IN0

S0

S1

3-bit LUT8

S0

S1

OUT

LUT Truth

Table

From Connection

Matrix Output [31]

To Connection

S0

S1

S0

S1

Matrix Input [13]

8-bits NVM

registers [799:792]

S1

DFF

Registers

D

From Connection

Matrix Output [30]

S0

S1

S0

S1

nRST/nSET

CLK

DFF/

Latch10

Q/nQ

register [676]

LUT/DFF Sel

registers [807:800]

registers [675:672]

Mode Sel

CNT

Data

ext_CLK

To Connection

Matrix Input [12]

0

S0

OUT

CNT/DLY0

DLY_IN/CNT Reset

S0

S1

S2

S1

S2

S3

UP

0

S3

Config

Data

registers [691:677]

0

S0

S1

Figure 35: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT8/DFF10, CNT/DLY0/FSM)

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register [815] DFF or Latch Select

register [814] Output Select (Q or

nQ)

From Connection

Matrix Output [35]

register [813] (nRST or nSET) from

matrix Output

IN2

IN1

IN0

S0

3-bit LUT9

S0

register [812] DFF Initial Polarity

Select

OUT

S1

LUT Truth

Table

From Connection

Matrix Output [34]

To Connection

S0

S1

S0

S1

Matrix Input [15]

8-bits NVM

registers [815:808]

S1

DFF

Registers

D

From Connection

Matrix Output [33]

S0

S1

S0

S1

DFF/

Latch11

nRST/nSET

CLK

Q/nQ

register [700]

LUT/DFF Sel

registers [823:816]

registers [699:696]

Mode Sel

CNT

Data

ext_CLK

To Connection

Matrix Input [14]

0

S0

OUT

CNT/DLY1

DLY_IN/CNT Reset

S0

S1

S2

S1

S2

S3

Config

Data

0

S3

registers [710:701]

Figure 36: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT9/DFF11, CNT/DLY1)

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register [831] DFF or Latch Select

register [830] Output Select (Q or

nQ)

From Connection

Matrix Output [38]

register [829] (nRST or nSET) from

matrix Output

IN2

IN1

IN0

S0

3-bit LUT10

S0

register [828] DFF Initial Polarity

Select

OUT

S1

LUT Truth

Table

From Connection

Matrix Output [37]

To Connection

S0

S1

S0

S1

Matrix Input [17]

8-bits NVM

registers [831:824]

S1

DFF

Registers

D

From Connection

Matrix Output [36]

S0

S1

S0

S1

DFF/

Latch12

nRST/nSET

Q/nQ

CLK

register [716]

LUT/DFF Sel

registers [839:832]

registers [715:712]

Mode Sel

CNT

Data

ext_CLK

To Connection

Matrix Input [16]

0

S0

OUT

CNT/DLY2

DLY_IN/CNT Reset

S0

S1

S2

S1

S2

S3

Config

Data

0

S3

registers [729:717]

Figure 37: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT10/DFF12, CNT/DLY2)

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register [847] DFF or Latch Select

register [846] Output Select (Q or

nQ)

register [845] (nRST or nSET) from

matrix Output

register [844] DFF Initial Polarity

Select

From Connection

Matrix Output [41]

IN2

IN1

IN0

S0

3-bit LUT11

S0

OUT

S1

LUT Truth

Table

From Connection

Matrix Output [40]

To Connection

S0

S1

S0

S1

Matrix Input [19]

8-bits NVM

registers [847:840]

S1

DFF

Registers

D

From Connection

Matrix Output [39]

S0

S1

S0

S1

_nRST/nSETDFF/

Q/nQ

Latch13

CLK

register [740]

LUT/DFF Sel

registers [855:848]

registers [739:736]

Mode Sel

CNT

Data

ext_CLK

To Connection

Matrix Input [18]

0

S0

OUT

CNT/DLY3

DLY_IN/CNT Reset

S0

S1

S2

S1

S2

S3

Config

Data

0

S3

registers [735:731], [748:741]

Figure 38: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT11/DFF13, CNT/DLY3)

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register [863] DFF or Latch Select

register [862] Output Select (Q or

nQ)

register [861] (nRST or nSET) from

matrix Output

register [860] DFF Initial Polarity

Select

From Connection

Matrix Output [44]

IN2

IN1

IN0

S0

3-bit LUT12

S0

OUT

S1

LUT Truth

Table

From Connection

Matrix Output [43]

To Connection

S0

S1

S0

S1

Matrix Input [21]

8-bits NVM

registers [863:856]

S1

DFF

Registers

D

From Connection

Matrix Output [43]

S0

S1

S0

S1

DFF/

Latch14

nRST/nSET

Q/nQ

CLK

register [756]

LUT/DFF Sel

registers [755:752]

Mode Sel

registers [871:864]

CNT

Data

ext_CLK

To Connection

Matrix Input [20]

0

S0

OUT

CNT/DLY4

DLY_IN/CNT Reset

S0

S1

S2

S1

S2

S3

Config

Data

0

S3

registers [751:749], [766:757]

Figure 39: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT12/DFF14, CNT/DLY4)

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GreenPAK Programmable Mixed-Signal Matrix

register [879] DFF or Latch Select

register [878] Output Select (Q or

nQ)

From Connection

Matrix Output [47]

register [877] (nRST or nSET) from

matrix Output

IN2

IN1

IN0

S0

3-bit LUT13

S0

register [876] DFF Initial Polarity

Select

OUT

S1

LUT Truth

Table

From Connection

Matrix Output [46]

To Connection

S0

S1

S0

S1

Matrix Input [23]

8-bits NVM

registers [879:872]

S1

DFF

Registers

D

From Connection

Matrix Output [45]

S0

S1

S0

S1

DFF/

Latch15

nRST/nSET

Q/nQ

CLK

register [772]

LUT/DFF Sel

registers [887:880]

registers [771:768]

Mode Sel

CNT

Data

ext_CLK

To Connection

Matrix Input [22]

0

S0

OUT

CNT/DLY5

DLY_IN/CNT Reset

S0

S1

S2

S1

S2

S3

Config

Data

0

S3

registers [785:773]

Figure 40: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT13/DFF15, CNT/DLY5)

As shown in Figure 35 - Figure 40 there is a possibility to use LUT/DFF and CNT/DLY simultaneously.

Note: It is not possible to use LUT and DFF at once, one of these macrocells must be selected.



Case 1. LUT/DFF in front of CNT/DLY. Three input signals from the connection matrix go to previously selected LUT or DFF's

inputs and produce a single output which goes to a CND/DLY input. In its turn Counter/Delay's output goes back to the matrix.

Case 2. CNT/DLY in front of LUT/DFF. Two input signals from the connection matrix go to CND/DLY's inputs (IN and CLK). Its

output signal can be connected to any input of previously selected LUT or DFF, after which the signal goes back to the matrix.

Case 3. Single LUT/DFF or CNT/DLY. Also, it is possible to use a standalone LUT/DFF or CNT/DLY. In this case, all inputs

and output of the macrocell are connected to the matrix.

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GreenPAK Programmable Mixed-Signal Matrix

8.1.2 3-Bit LUT or CNT/DLYs Used as 3-Bit LUTs

Table 31: 3-bit LUT8 Truth Table

Table 34: 3-bit LUT11 Truth Table

IN2

0

IN1

0

IN0

0

OUT

IN2

0

IN1

0

IN0

0

OUT

register [792]

register [793]

register [794]

register [795]

register [796]

register [797]

register [798]

register [799]

LSB

register [840]

register [841]

register [842]

register [843]

register [844]

register [845]

register [846]

register [847]

LSB

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

MSB

LSB

1

MSB

LSB

Table 32: 3-bit LUT9 Truth Table

Table 35: 3-bit LUT12 Truth Table

IN2

0

IN1

0

IN0

0

OUT

IN2

0

IN1

0

IN0

0

OUT

register [808]

register [809]

register [810]

register [811]

register [812]

register [813]

register [814]

register [815]

register [856]

register [857]

register [858]

register [859]

register [860]

register [861]

register [862]

register [863]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

MSB

LSB

1

MSB

LSB

Table 33: 3-bit LUT10 Truth Table

Table 36: 3-bit LUT13 Truth Table

IN2

0

IN1

0

IN0

0

OUT

IN2

0

IN1

0

IN0

0

OUT

register [824]

register [825]

register [826]

register [827]

register [828]

register [829]

register [830]

register [831]

register [872]

register [873]

register [874]

register [875]

register [876]

register [877]

register [878]

register [879]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

MSB

1

MSB

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GreenPAK Programmable Mixed-Signal Matrix

Each macrocell, when programmed for a LUT function, uses a 8-bit register to define their output function:

3-Bit LUT8 is defined by registers [799:792]

3-Bit LUT9 is defined by registers [815:808]

3-Bit LUT10 is defined by registers [831:824]

3-Bit LUT11 is defined by registers [847:840]

3-Bit LUT12 is defined by registers [863:856]

3-Bit LUT13 is defined by registers [879:872]

Optional Finite State Machine (FSM) function. There are two additional matrix inputs for Up and Keep to support FSM functionality.

This macrocell can also operate in a one-shot mode, which will generate an output pulse of user-defined width.

This macrocell can also operate in a frequency detection or edge detection mode.

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GreenPAK Programmable Mixed-Signal Matrix

8.2 CNT/DLY TIMING DIAGRAMS

8.2.1 Delay Mode CNT/DLY0 to CNT/DLY5

Delay In

Asynchronous delay variable

OSC: force power-on

(always running)

Delay Output

delay = period x (counter data + 1) + variable

variable is from 0 to 1 clock period

delay = period x (counter data + 1) + variable

variable is from 0 to 1 clock period

Delay In

offset

OSC: auto power-on

(powers up from delay in)

Delay Output

delay = offset + period x (counter data + 1)

See offset in table 11

delay = offset + period x (counter data + 1)

See offset in table 11

Figure 41: Delay Mode Timing Diagram, Edge Select: Both, Counter Data: 3

The macrocell shifts the respective edge to a set time and restarts by appropriate edge. It works as a filter, if the input signal is

shorter than the delay time.

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GreenPAK Programmable Mixed-Signal Matrix

Delay time

One-Shot/Freq. DET/Delay IN

t

Delay time

Delay Function

Rising Edge Detection

Delay Function

Falling Edge Detection

t

Delay Function

Both Edge Detection

Figure 42: Delay Mode Timing Diagram for Different Edge Select Modes

8.2.2 Count Mode (Count Data: 3), Counter Reset (Rising Edge Detect) CNT/DLY0 to CNT/DLY5

RESET_IN

CLK

Counter OUT

4 CLK period pulse

Count start in first rising edge CLK

Figure 43: Counter Mode Timing Diagram without Two DFFs Synced Up

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GreenPAK Programmable Mixed-Signal Matrix

.

RESET_IN

CLK

Counter OUT

4 CLK period pulse

Count start in 0 CLK after reset

Figure 44: Counter Mode Timing Diagram with Two DFFs Synced Up

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GreenPAK Programmable Mixed-Signal Matrix

8.2.3 One-Shot Mode CNT/DLY0 to CNT/DLY5

This macrocell will generate a pulse whenever a selected edge is detected on its input. Register bits set the edge selection. The

pulse width determines by counter data and clock selection properties. The output pulse polarity (non-inverted or inverted) is

selected by register bit. Any incoming edges will be ignored during the pulse width generation. The following diagram shows one-

shot function for non-inverted output.

Delay time

One-Shot/Freq. DET/Delay IN

t

Delay time

One-Shot Function

Rising Edge Detection

t

One-Shot Function

Falling Edge Detection

t

One-Shot Function

Both Edge Detection

t

Figure 45: One-Shot Function Timing Diagram

This macrocell generates a high level pulse with a set width (defined by counter data) when detecting the respective edge. It does

not restart while pulse is high.

8.2.4 Frequency Detection Mode CNT/DLY0 to CNT/DLY5

Rising Edge: The output goes high if the time between two successive edges is less than the delay. The output goes low if the

second rising edge has not come after the last rising edge in specified time.

Falling Edge: The output goes high if the time between two falling edges is less than the set time. The output goes low if the

second falling edge has not come after the last falling edge in specified time.

Both Edge: The output goes high if the time between the rising and falling edges is less than the set time, which is equivalent to

the length of the pulse. The output goes low if after the last rising/falling edge and specified time, the second edge has not come.

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GreenPAK Programmable Mixed-Signal Matrix

Delay time

One-Shot/Freq. DET/Delay IN

t

Delay time

Frequency Detector Function

Rising Edge Detection

Frequency Detector Function

Falling Edge Detection

t

Frequency Detector Function

Both Edge Detection

Figure 46: Frequency Detection Mode Timing Diagram

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GreenPAK Programmable Mixed-Signal Matrix

8.2.5 Edge Detection Mode CNT/DLY1 to CNT/DLY5

The macrocell generates high level short pulse when detecting the respective edge. See Figure 47.

Delay time

One-Shot/Freq. DET/Delay IN

t

Edge Detector Function

Rising Edge Detection

Edge Detector Function

Falling Edge Detection

t

Edge Detector Function

Both Edge Detection

Figure 47: Edge Detection Mode Timing Diagram

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GreenPAK Programmable Mixed-Signal Matrix

8.2.6 Delayed Edge Detection Mode CNT/DLY0 to CNT/DLY5

In Delayed Edge Detection Mode, High level short pulses are generated on the macrocell output after the configured delay time,

if the corresponding edge was detected on the input.

If the input signal is changed during the set delay time, the pulse will not be generated. See Figure 48.

Delay time

One-Shot/Freq. DET/Delay IN

t

Delay time

Delayed Edge Detector Function

Rising Edge Detection

Delayed Edge Detector Function

Falling Edge Detection

t

Delayed Edge Detector Function

Both Edge Detection

Figure 48: Delayed Edge Detection Mode Timing Diagram

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GreenPAK Programmable Mixed-Signal Matrix

8.2.7 Difference in Counter Value for Counter, Delay, One-Shot, and Frequency Detect Modes

There is a difference in counter value for Counter and Delay/One-Shot/Frequency Detect modes. The counter value is shifted for

two rising edges of the clock signal in Delay/One-Shot/Frequency Detect modes compared to Counter mode. See Figure 49:

One-Shot/Freq. SET/Delay IN

CLK

CNT Out

3

2

1

0

3

CNT Data

2

DLY Out

3

2

Delay Data

1

3

One-Shot Out

One-Shot Data

3

2

3

1

3

Figure 49: Counter Value, Counter Data = 3

8.3 FSM TIMING DIAGRAMS

The behavior of FSM macrocell with low level at Up input is the same as the behavior of other multifunction macrocells in

corresponding modes (Counter, Delay, One Shot, Freq. Detector, Delayed Edge Detector).

Reset In

Clk

3

4

5

3

4

5

6

7

Internal Counter

Q

253

254

255

3

4

Figure 50: CNT/FSM Mode Timing Diagram (Set Rising Edge Mode, Oscillator Is Forced On, UP = 1) for CNT Data = 3

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9

Multichannel Sampling Analog Comparator

The SLG46811 has one multichannel sampling ACMP that can make periodical samples of up to four input channels and latch

the results at four outputs. The input sources for MS ACMP can be GPIO4, GPIO5, GPIO6, GPIO7, V_DD, Temperature sensor.

User can select any number of channels to be sampled from one up to four, for example, Channel0, Channel2 and Channel3.

Note that the channels are sampled in fixed order from 0 to 3rd. Each channel has separate configurable voltage reference and

hysteresis. Vref range is from 32 mV to 2016 mV with 32 mV step in sampling mode and from 64 mV to 2016 mV with 32 mV step

in regular mode. Hysteresis options are: no hysteresis, 32 mV (available only in sampling mode), 64 mV, 192 mV.

Non-inverting input of MS ACMP has the input divider that can be configured for each channel separately. The options for the

divider are: Vin, Vin / 2, Vin / 3, Vin / 4.

MS ACMP uses internal oscillator0 to switch between channels, change Vref and latch the results. Clock from the oscillator0 can

be divided by 2, 4, or 8 inside the MS ACMP. If "Auto power on" setting of oscillator is selected, High voltage level (or rising edge,

depending on setting) on Enable input starts the internal oscillator. Please use MS ACMP clock frequencies from Table 37 when

interfacing the sensor with high output impedance with SLG46811.

Table 37: Recommended MS ACMP Clock Frequencies

Parameter

Range 1

< 1

Range 2

1 to 2

≤ 5

Range 3

2 to 4

Range 4

4 to 6

Range 5

> 6

Unit

MΩ

Sensor Output Resistance

MS ACMP Clock Frequency

≤ 10

≤ 2.5

≤ 1.25

≤ 0.5

kHz

User can select the way the results appear at the outputs of MS ACMP. In asynchronous mode (register [499] = 0) results appear

continuously after each channel is sampled. In synchronous mode (register [499] = 1) results at the output appear simultaneously

after the last selected channel was sampled. The signal Sync data ready (matrix input [50]) generates a pulse of 100 ns appro-

ximate width when the sequence of selected channels was sampled.

Basic modes for MS ACMP are the next:



Regular mode, register [497] = 0. In this mode MS ACMP operates as conventional ACMP. One selected channel is mea-

sured continuously when logic level at Enable input is High

Sampling mode, register [497] = 1. Enable input is level sensitive, register [498] = 0. In this mode MS ACMP changes sam-

pled channels and latches the result every pulse at Clk input while Enable input is High. When Enable becomes Low level MS

ACMP finishes sampling the sequence and goes power down.



Sampling mode, register [497] = 1. Enable input is edge sensitive, register [498] = 1. In this mode, when rising edge comes at

Enable input, MS ACMP samples selected channels (up to four) every rising edge at Clk input and goes power down until the

next pulse at Enable input.

User can select the way the results appear at the outputs of MS ACMP. In asynchronous mode (register [499] = 0) results appear

continuously after each channel is sampled. In synchronous mode (register [499] = 1) results at the output appear simultaneously

after the last selected channel was sampled.

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9.1 MULTICHANNEL SAMPLING ACMP BLOCK DIAGRAM

Input MUX

Divider

GPIO4

GPIO5

ACMP LAT RST accessible selection

Register [515]

Register [514]

/1

/2

/3

/4

Register [513]

Register [512]

GPIO6

V_DD

V_DDEn Register[500]

Div. sel. MUX

2

ACMP

Div1

Registers[529:528]

Matrix IN

(OUT0)

GPIO7

Div2

Temp. sensor

2

Registers[537:536]

Div3

Registers[545:544]

2

PwrUp

Temp. sensor En

RegIster [501]

Matrix IN

(OUT1)

RST

Matrix Output [68]

Div4

Registers[553:552]

DFFs

2

Matrix IN

(OUT2)

2

Matrix IN

(OUT03)

OSC0

Vref sel. MUX

Vref/Hys

Channel

00

01

OSC0/2

6

OSC0/4

OSC0/8

Vref1 Registers [535:530]

10

11

Sampling

Engine

Vref2 Registers [543:538]

Vref3 Registers [551:546]

6

CLK

En

PwrUp

Registers [517:516]

6

Sync Data Ready

Matrix Input [50]

Enable

Matrix Output [67]

Data ready

Vref and

hysteresis

control

Vref4 Registers [559:554]

Async/Sync

Register[499]

Level/Edge

sensitive enable

Register [498]

2

Hys1 Registers[521:520]

Hys2 Registers[523:522]

Hys3 Registers[525:524]

2

Regular/Sampling mode

Register [497]

2

Hys4 Registers[527:526]

6

Hys sel. MUX

Define the number of sampling channels,

NUM<1:0>

Registers [503:502]

Vref MUX

Ext. Vref

111111

111110

2016 mV

1984 mV

Define positive input channel on

1^stsampling Registers [505:504]

2^ndsampling Registers [507:506]

3^rdsampling Registers [509:508]

4^thsampling Registers [511:510]

64 mV

32 mV

000001

000000

Figure 51: Multichannel Sampling ACMP Block Diagram

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GreenPAK Programmable Mixed-Signal Matrix

9.2 MS ACMP TIMING DIAGRAMS

.

Assumption: All DFF OUTs are configuresed as resetable by ACMPDFF_RST

This will be effective at both edge & level sensitive mode

ACMPDFF_RSTB(Matrix OUT)

ACMP_EN [Matrix OUT]

VREFGEN/ACMP ON

OSC0 clk

T1 = VREFGEN & ACMP settling time

T1

Sampling OK

Sampling CLK

T2=0.5~1.5 cycle of sampling CLK

T2

T3

01

00

01

10

11

00

Pos./Neg. Channel Selection

ACMP_OUT

T4

ACMP0/1/2/3 ready

ACMP0 OUT [Async, Matrix IN]

ACMP1 OUT [Async, Matrix IN]

ACMP2 OUT [Async, Matrix IN]

ACMP3 OUT [Async, Matrix IN]

Sync Ready [ Matrix IN]

T5

Sync Ready will be generated always regardless of

sync or async mode

T5 ≈ 100 ns

ACMP1/2/3/4 OUT [Sync, Matrix IN]

Figure 52: Timing Diagrams for MS ACMP. Edge Sensitive Mode. OSC0 and BG are Forced On

.

ACMP_EN [Matrix OUT]

Assumption: LPBG is forced ON

VREFGEN/ACMP ON

OSC0 clk

T1 = VREFGEN & ACMP settling time

T1

Sampling OK

T2=0.5~1.5 cycle of sampling CLK

T2

Sampling CLK

T3

0 0

00

01

10

11

00

01

10

11

Pos./Neg. Channel Selection

ACMP_OUT

T4

ACMP0/1/2/3 ready

ACMP0 OUT [Async, Matrix IN]

ACMP1 OUT [Async, Matrix IN]

ACMP2 OUT [Async, Matrix IN]

ACMP3 OUT [Async, Matrix IN]

Sync Ready [ Matrix IN]

T5

T5 ≈ 100 ns

Sync Ready will be generated always regardless of sync or async mode

ACMP1/2/3/4 OUT [Sync, Matrix IN]

Figure 53: Timing Diagrams for MS ACMP. Level Sensitive Mode. OSC0 and BG are Forced On

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GreenPAK Programmable Mixed-Signal Matrix

.

ACMP_EN [Matrix OUT]

VREFGEN/ACMP ON

T2=OSC0 enabling time

T2

OSC0 clk

T1 = VREFGEN & ACMP

settling time

T1

Sampling OK

Sampling CLK

T3

0 0

00

01

10

11

00

01

10

11

Pos./Neg. Channel Selection

ACMP_OUT

T4

ACMP0/1/2/3 ready

ACMP0 OUT [Async, Matrix IN]

ACMP1 OUT [Async, Matrix IN]

ACMP2 OUT [Async, Matrix IN]

ACMP3 OUT [Async, Matrix IN]

Sync Ready [ Matrix IN]

T5

T5 ≈ 100 ns

Sync Ready will be generated always regardless of sync or async mode

ACMP1/2/3/4 OUT [Sync, Matrix IN]

Figure 54: Timing Diagrams for MS ACMP. Level Sensitive Mode. OSC0 is in Auto Power On Mode. BG is Forced On

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9.3 ACMP TYPICAL PERFORMANCE

1.8

1.6

1.4

1.2

1

High To Low, Overdrive = 10 mV

0.8

0.6

0.4

0.2

0

Low to High, Overdrive = 10 mV

High To Low, Overdrive = 100 mV

Low to High, Overdrive = 100 mV

32

480

1024

1504

2016

Vref (mV)

Figure 55: Typical Propagation Delay vs. Vref for MS ACMP at T = 25 °C, Gain = 1, Hysteresis = 0, Regular Mode

55

T = -40 °C

T = 25 °C

50

T = 85 °C

45

40

35

30

25

20

2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5

V_DD(V)

Figure 56: MS ACMP Power-On Delay vs. V_DD, Regular Mode

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2.4

2.2

2

Bandgap: Auto-On, OSC0: Auto-On

Bandgap: Auto-On, OSC0: Forced

Bandgap: Forced, OSC0: Auto-On

Bandgap: Forced, OSC0: Forced

1.8

1.6

1.4

1.2

1

0.8

0.6

0.4

0.2

0

2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5

V_DD(V)

Figure 57: MS ACMP Power-On Delay vs. V_DD, Sampling Mode, T = -40 °C to 85 °C

6

4

2

0

Upper Limit

Lower Limit

-2

-4

-6

-8

32

480

1024

1504

2016

Vref (mV)

Figure 58: MS ACMP Input Offset Voltage vs. Vref at T = -40 °C to 85 °C

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45

T = 85 °C

T = 25 °C

40

35

30

25

20

T = -40 °C

2.3

2.8

3.3

3.8

4.3

4.8

5.3

V_DD(V)

Figure 59: Current Consumption vs. V_DDfor Regular Mode, External Vref, V_IN+= V_DD, V_IN-= GND

50

T = 85 °C

T = 25 °C

45

40

35

30

25

T = -40 °C

2.3

2.8

3.3

3.8

4.3

4.8

5.3

V_DD(V)

Figure 60: Current Consumption vs. V_DDfor Sampling Mode, 4 Channels, V_IN+= 2048 mV, V_IN-= 32 mV, Clock = 10 kHz

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10 Programmable Delay/Edge Detector

The SLG46811 has a programmable time delay logic cell that can generate a delay that is selectable from one of four timings

(time2) configured in the GreenPAK Designer. The programmable time delay cell can generate one of four different delay patterns,

rising edge detection, falling edge detection, both edge detection, and both edge delay. These four patterns can be further

modified with the addition of delayed edge detection, which adds an extra unit of delay, as well as glitch rejection during the delay

period. See Figure 62 for further information.

Note: The input signal must be longer than the delay, otherwise it will be filtered out.

registers [1053:1052]

Delay Value Selection

registers [1051:1050]

Edge Mode Selection

To Connection

Matrix Input [41]

Programmable

From Connection Matrix Output [52]

IN

OUT

Delay

Figure 61: Programmable Delay

10.1 PROGRAMMABLE DELAY TIMING DIAGRAM - EDGE DETECTOR OUTPUT

width

IN

time1

Rising Edge Detector

time1

Falling Edge Detector

Edge Detector

Output

Both Edge Detector

Both Edge Delay

time2

time1 is a fixed value

time2 delay value is selected via register

Figure 62: Edge Detector Output

Please refer to Table 12.

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11 Additional Logic Function. Deglitch Filter

The SLG46811 has one Deglitch Filter macrocell with inverter function that is connected directly to the Connection Matrix inputs

and outputs. The filter pass the input signal for pulse width > tpass (at typical temperature 25 °C. See Table 14).

In addition, this macrocell can be configured as an Edge Detector, with the following settings:



Rising Edge Detector

Falling Edge Detector

Both Edge Detector

Both Edge Delay

Filter

R

From Connection Matrix

Output [53]

0

1

C

0

1

To Connection Matrix

Input [42]

Edge

Detector

Logic

register [1048]

registers [1051:1050]

register [1049]

Figure 63: Deglitch Filter/Edge Detector Simplified Structure

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12 Voltage Reference

12.1 VOLTAGE REFERENCE OVERVIEW

The SLG46811 has a Voltage Reference (Vref) macrocell to provide references to the Multichannel Sampling Analog Comparator.

See Table 38 for the available selections for Multichannel Sampling Analog Comparator.

12.2 VREF SELECTION TABLE

Table 38: Vref Selection Table

SEL[5:0]

0

Vref

0.032

0.064

0.096

0.128

0.16

SEL[5:0]

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

Vref

1.056

1.088

1.12

1

2

3

1.152

1.184

1.216

1.248

1.28

4

5

0.192

0.224

0.256

0.288

0.32

6

7

8

1.312

1.344

1.376

1.408

1.44

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

0.352

0.384

0.416

0.448

0.48

1.472

1.504

1.536

1.568

1.6

0.512

0.544

0.576

0.608

0.64

1.632

1.664

1.696

1.728

1.76

0.672

0.704

0.736

0.768

0.8

1.792

1.824

1.856

1.888

1.92

0.832

0.864

0.896

0.928

0.96

1.952

1.984

2.016

External

0.992

1.024

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GreenPAK Programmable Mixed-Signal Matrix

13 Clocking

13.1 OSC GENERAL DESCRIPTION

The SLG46811 has two internal oscillators to support a variety of applications:



Oscillator0 (2.048 kHz or 10 kHz optional selection)

Oscillator1 (25 MHz).

The Oscillator0 can operate in one of two modes (2.048 kHz or 10 kHz) selected by register [581]. There are two divider stages

for each oscillator that gives the user flexibility for introducing clock signals to connection matrix, as well as various other macro-

cells. The pre-divider (first stage) for Oscillator0 is clock /1, /2, /4 or /8. The pre-divider (first stage) for Oscillator1 is clock /1, /2,

/4, /8, /12, /24, /48. The second stage divider has an input of frequency from the pre-divider, and outputs one of eight different

frequencies divided by /1, /2, /3, /4, /8, /12, /24 or /64 on Connection Matrix Input lines [43], [49]. Please see Figure 64, Figure 65

and Figure 66 for more details on the SLG46811 clock scheme.

Oscillator1 (25 MHz) has an additional function of 100 ns delayed startup, which can be enabled/disabled by register [592]. This

function is recommended to use when analog blocks are used along with the Oscillator.

The Matrix Power-down/Force On function allows switching off or force on the oscillators using an external pin (see Table 39).

The Matrix Power-down/Force On (Connection Matrix Output [579]) signal has the highest priority.

Table 39: Oscillator Control Input Modes

Registers [567:566]

Description

OSC0 (2kHz/10kHz): Controlled by register [578]

OSC1 (25MHz): Controlled by register [568]

b00

OSC0 (2kHz/10kHz): Controlled by Matrix Output

OSC1 (25MHz): Controlled by register [568]

b01

b10

b11

OSC0 (2kHz/10kHz): Controlled by register [578]

OSC1 (25MHz): Controlled by Matrix Output

OSC0 (2kHz/10kHz): Controlled by Matrix Output

OSC1 (25MHz): Controlled by Matrix Output

The OSC operates according to the Table 40:

Table 40: Oscillator Operation Mode Configuration Settings

OSC Enable

Signal from

CNT/DLY

Register:

OSC

Operation

Mode

Signal From

Connection

Matrix

Register: Auto

Power-On or

Force On

External Clock

Selection

Power-Down

or Force On by

Matrix Input

POR

Macrocells

0

1

X

1

X

OFF

Internal OSC is

OFF, logic is ON

1

0

1

0

1

X

1

X

OFF

ON

X

CNT/DLY

requires OSC

1

0

X

0

CNT/DLY

doesnotrequire

OSC

OFF

Note 1 The OSC will run only when any macrocell that uses OSC is powered on.

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13.2 OSCILLATOR0 (2.048 KHZ/10 KHZ)

From Connection Matrix

Output [69]

PWR DOWN/Force On

to CNT/DLYs Clock Scheme

2.048 kHz Pre-divider Clock

Matrix Output control Register [579]

OSC Power Mode

Register [578]

PWR DOWN/

FORCE ON

Registers [583:582]

OSC0

(2.048 kHz /

10 kHz)

Auto Power On

Force Power On

OUT

0

1

0

1

DIV /1 /2 /4 /8

Predivider

0

1

2

3

Ext. Clock

/2

/3

2.048/10 kHz Selection

Register [581]

OSC0 Matrix Out0 Enable Register [587]

To Connection Matrix

Ext. CLK Sel Register [580]

/4

OUT0

Input [43]

/8

4

5

6

7

To Connection Matrix

Input [49]

OUT1

/12

/24

/64

OSC0 Matrix Out1 Enable Register [591]

Registers [586:584]

Registers [590:588]

Second Stage

Divider

Figure 64: Oscillator0 Block Diagram

13.3 OSCILLATOR1 (25 MHZ)

From Connection Matrix

Output [69]

PWR DOWN/Force On

To CNT/DLYs Clock Scheme

25 MHz Pre-divider Clock

Matrix Output Control Register [569]

OSC Power Mode

Register [568]

PWR DOWN/

FORCE ON

Registers [574:572]

OSC1

(25 MHz)

Auto Power On

Force Power On

OUT

0

1

0

1

DIV /1 /2 /4 /8 /

12 /24 /48

Startup delay

0

1

2

3

4

5

6

7

Register [592]

/2

/3

Predivider

Ext. Clock

OSC1 Matrix Out Enable Register [571]

Ext. CLK Sel Register [570]

/4

To Connection Matrix

Input [44]

/8

/12

/24

/64

Registers [577:575]

Second Stage

Divider

Figure 65: Oscillator1 Block Diagram

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13.4 CNT/DLY CLOCK SCHEME

Each CNT/DLY within Multi-Function macrocell has its own additional clock divider connected to oscillators pre-divider. Available

dividers are:



OSC0/1, OSC0/8, OSC0/12, OSC0/24, OSC0/64, OSC0/512, OSC0/4096

OSC1/1, OSC1/4, OSC1/8, OSC1/64, OSC1/512

registers [686:683] for CNT0,

registers [710:707] for CNT1,

registers [726:723] for CNT2,

registers [748:745] for CNT3,

registers [766:763] for CNT4,

registers [782:779] for CNT5

0

1

from 25 MHz

Pre-divided clock

/4

/8

2

3

4

5

6

7

8

/64

/512

CNT/DLY/

ONESHOT/

FREQ_DET/

from 2.048/10 kHz

Pre-divided clock

/8

/12

DLY_EDGE_DET

/24

/64

9

CNT overflow

/512

/4096

10

11

12

13

14

15

CNT (x-1) overflow

from Connection Matrix out

(separate for each CNT/DLY macrocell)

reserved

CNT0/CNT1/CNT2/CNT3/

CNT4/CNT5

Figure 66: Clock Scheme

13.5 EXTERNAL CLOCKING

The SLG46811 supports several ways to use an external, higher accuracy clock as a reference source for internal operations.

13.5.1 GPI Source for Oscillator0 (2.048kHz/10 kHz)

When register [580] is set to 1, an external clocking signal on GPI will be routed in place of the internal oscillator derived 2.048

kHz clock source. See Figure 64. The low and high limits for external frequency that can be selected are 0 MHz and 10 MHz.

13.5.2 GPIO Source for Oscillator1 (25 MHz)

When register [570] is set to 1, an external clocking signal on GPIO7 will be routed in place of the internal oscillator derived 25

MHz clock source. See Figure 65. The external frequency range is 0 MHz to 20 MHz at V_DD= 2.3 V, 30 MHz at V_DD= 3.3 V, 50

MHz at V_DD= 5.0 V.

13.6 OSCILLATORS POWER-ON DELAY

When OSC power mode is "Auto Power-On" "OSC enable" signal appears when any macrocell that uses OSC is powered on

(see Figure 67). The values of Power-On Delay are in Table 17.

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OSC enable

Power-On

Delay

CLK

Figure 67: Oscillator Startup Diagram

Note 1 OSC power mode: “Auto Power-On”.

Note 2 “OSC enable” signal appears when any macrocell that uses OSC is powered on.

1 100

1 000

900

800

700

600

500

2.3

3.3

4.0

5.0

5.5

V_DD(V)

Figure 68: Oscillator0 Maximum Power-On Delay vs. V_DDat T = 25 °C, OSC0 = 2.048 kHz/10 kHz

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180

160

140

120

100

80

Start with Delay

Normal Start

60

40

20

0

2.3

3.3

4.0

5.0

5.5

V_DD(V)

Figure 69: Oscillator1 Maximum Power-On Delay vs. V_DDat T = 25 °C, OSC1 = 25 MHz

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13.7 OSCILLATORS ACCURACY

Note: OSC power setting: Force Power-On; Clock to matrix input - enable; Bandgap: turn on by register - enable.

2.15

2.1

2.05

2

Fmax @ VDD = 2.3 V to 5.0 V

Ftyp @ VDD = 3.3 V

1.95

1.9

Fmin @ VDD = 2.3 V to 5.0 V

T (°C)

Figure 70: Oscillator0 Frequency vs. Temperature, OSC0 = 2.048 kHz

10.4

10.2

10

9.8

9.6

9.4

Fmax @ VDD = 2.3 V to 5.0 V

Ftyp @ VDD = 3.3 V

Fmin @ VDD = 2.3 V to 5.0 V

T (°C)

Figure 71: Oscillator0 Frequency vs. Temperature, OSC0 = 10 kHz

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26

25.5

25

24.5

Fmax @ VDD = 5.0 V

24

23.5

23

Fmax @ VDD = 3.3 V

Fmax @ VDD = 2.3 V

Ftyp @ VDD = 3.3V

Fmin @ VDD = 5.0 V

Fmin @ VDD = 3.3 V

Fmin @ VDD = 2.3 V

T (°C)

Figure 72: Oscillator1 Frequency vs. Temperature, OSC1 = 25 MHz

8

10 kHz Total Error @ VDD = 2.3 V to 5.5 V

25 MHz Total Error @ VDD = 2.3 V to 5.5 V

2.048 kHz Total Error @ VDD = 2.3 V to 5.5 V

7

6

5

4

3

2

1

0

T (°C)

Figure 73: Oscillators Total Error vs. Temperature

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Note: For more information see Section 3.9.

13.8 OSCILLATORS SETTLING TIME

580

570

560

550

540

530

520

510

500

490

480

0

1

2

3

4

5

Period

Figure 74: Oscillator0 Settling Time, V_DD= 3.3 V, T = 25 °C, OSC0 = 2.048 kHz

600

550

500

450

400

350

300

250

200

150

100

50

0

1

2

3

4

5

Period

Figure 75: Oscillator0 Settling Time, V_DD= 3.3 V, T = 25 °C, OSC0 = 10 kHz

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55

50

45

40

35

30

25

20

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Period

Figure 76: Oscillator1 Settling Time, V_DD= 3.3 V, T = 25 °C, OSC1 = 25 MHz (Normal Start)

13.9 OSCILLATORS CURRENT CONSUMPTION

750

700

650

600

550

500

450

400

T = 85 °C

T = -40 °C

T = 25 °C

2.5

3

3.5

4

4.5

5

5.5

V_DD(V)

Figure 77: OSC0 Current Consumption vs. V_DD(All Pre-Dividers), OSC0 = 2.048 kHz

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600

T = 85 °C

550

T = 25 °C

T = -40 °C

500

450

400

350

2.5

3

3.5

4

4.5

5

5.5

V_DD(V)

Figure 78: OSC0 Current Consumption vs. V_DD(All Pre-Dividers), OSC0 = 10 kHz

170

150

130

110

90

Pre-Divider = 1

Pre-Divider = 4

Pre-Divider = 8

70

50

30

2.5

3

3.5

4

4.5

5

5.5

V_DD(V)

Figure 79: OSC1 Current Consumption vs. V_DD, T = -40 °C to 85 °C, OSC1 = 25 MHz

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14 Power-On Reset

The SLG46811 has a Power-On Reset (POR) macrocell to ensure correct device initialization and operation of all macrocells in

the device. The purpose of the POR circuit is to have consistent behavior and predictable results when the V_DDpower is first

ramping to the device, and also while the V_DDis falling during power-down. To accomplish this goal, the POR drives a defined

sequence of internal events that trigger changes to the states of different macrocells inside the device, and finally to the state of

the IOs.

14.1 GENERAL OPERATION

The SLG46811 is guaranteed to be powered down and non-operational when the V_DDvoltage (voltage on PIN1) is less than

Power-Off Threshold (see in Table 6), but not less than -0.6 V. Another essential condition for the chip to be powered down is that

no voltage higher (Note) than the V_DDvoltage is applied to any other PIN. For example, if V_DDvoltage is 0.3 V, applying a voltage

higher than 0.3 V to any other PIN is incorrect, and can lead to incorrect or unexpected device behavior.

Note: There is a 0.6 V margin due to forward drop voltage of the ESD protection diodes.

To start the POR sequence in the SLG46811, the voltage applied on the V_DDshould be higher than the Power-On threshold

(Note). The full operational V_DDrange for the SLG46811 is 2.3 V to 5.5 V. This means that the V_DDvoltage must ramp up to the

operational voltage value, but the POR sequence will start earlier, as soon as the V_DDvoltage rises to the Power-On threshold.

After the POR sequence has started, the SLG46811 will have a typical period of time to go through all the steps in the sequence

(noted in the datasheet for that device), and will be ready and completely operational after the POR sequence is complete.

Note: The Power-On threshold is defined in Table 6.

To power down the chip the V_DDvoltage should be lower than the operational and to guarantee that chip is powered down it

should be less than Power-Off Threshold.

All PINs are in high impedance state when the chip is powered down and while the POR sequence is taking place. The last step

in the POR sequence releases the IO structures from the high impedance state, at which time the device is operational. The pin

configuration at this point in time is defined by the design programmed into the chip. Also, as it was mentioned before, the voltage

on PINs can’t be bigger than the V_DD, this rule also applies to the case when the chip is powered on.

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14.2 POR SEQUENCE

The POR system generates a sequence of signals that enable certain macrocells. The sequence is shown in Figure 80.

V_DD

t

POR_NVM

(reset for NVM)

NVM_ready_out

POR_GPI

(reset for input enable)

POR_LUT

(reset for LUT/FILTER/EPG)

POR_CORE

(reset for DLY/OSC/DFF/LATCH/

Pipe DLY/MS ACMP/Shift Register/

Edge Detector in Filter)

POR_OUT

(generate low to high to matrix)

POR_GPO

(reset for output enable)

Figure 80: POR Sequence

As can be seen from Figure 80 after the V_DDhas start ramping up and crosses the Power-On threshold, first, the on-chip NVM

memory is reset. Next, the chip reads the data from NVM, and transfers this information to a CMOS LATCH that serves to

configure each macrocell, and the Connection Matrix which routes signals between macrocells. The third stage causes the reset

of the input pins, and then to enable them. After that, the LUTs are reset and become active. After LUTs the Delay cells, OSCs,

DFFs, LATCHES, and Pipe Delay are initialized. Only after all macrocells are initialized internal POR signal (POR macrocell

output) goes from LOW to HIGH. The last portion of the device to be initialized are the output pins, which transition from high

impedance to active at this point.

The typical time that takes to complete the POR sequence varies by device type in the GreenPAK family. It also depends on many

environmental factors, such as: slew rate, V_DDvalue, temperature, and even will vary from chip to chip (process influence).

14.3 MACROCELLS OUTPUT STATES DURING POR SEQUENCE

To have a full picture of SLG46811 operation during powering and POR sequence, review the overview the macrocell output

states during the POR sequence (Figure 81 describes the output signals states).

First, before the NVM has been reset, all macrocells have their output set to logic LOW (except the output pins which are in high

impedance state). On the next step, some of the macrocells start initialization: input pins output state becomes LOW; LUTs also

output LOW. Only P_DLY macrocell configured as edge detector becomes active at this time. After that input pins are enabled.

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Next, only LUTs are configured. Next, all other macrocells are initialized. After macrocells are initialized, internal POR matrix signal

switches from LOW to HIGH. The last are output pins that become active and determined by the input signals.

V_DD

Guaranteed HIGH before POR_GPI

Unpredictable

t

V_DD_out

to matrix

t

Input PIN _out

to matrix

Unpredictable

Determined by External Signal

Determined by Input signals

LUT/FILTER/EPG_out

to matrix

Determined by input signals

OUT = IN without Delay

t

Programmable Delay_out

to matrix

Determined by Input signals

Starts to detect input edges

Determined by initial state

DFF/LATCH/MS ACMP/

Shift Register/Edge Detec-

tor in Filter_out to matrix

Determined by Input signals

Determined by input signals

OUT = IN without Delay

Delay_out

to matrix

Determined by Input signals

Starts to detect input edges

POR_out

to matrix

Unpredictable

Ext. GPO

Tri-state

Determined by input signals

Output State Unpredictable

Figure 81: Internal Macrocell States During POR Sequence

14.3.1 Initialization

All internal macrocells by default have initial low level. Starting from indicated power-up time of 1.84 V (typical), macrocells in

SLG46811 are powered on while forced to the reset state. All outputs are in Hi-Z and chip starts loading data from NVM. Then

the reset signal is released for internal macrocells and they start to initialize according to the following sequence:

1. Input pins, ACMP, Pull-up/down.

2. LUTs.

3. DFFs, Delays/Counters.

4. POR output to matrix.

5. Output pin corresponds to the internal logic.

The POR signal going high indicates the mentioned power-up sequence is complete.

Note: The maximum voltage applied to any pin should not be higher than the V_DDlevel. There are ESD Diodes between pin

→V_DDand pin → GND on each pin. So, if the input signal applied to pin is higher than V_DD, then current will sink through the

diode to V_DD. Exceeding V_DDresults in leakage current on the input pin, and V_DDwill be pulled up, following the voltage on the

input pin.There is no effect from input pin when input voltage is applied at the same time as V_DD

.

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14.3.2 Power-Down

V_DD(V)

POR OUT

PON_THR

Time

POFF_THR

Not guaranteed output state

Figure 82: Power-Down

During Power-down, macrocells in SLG46811 are powered off after V_DDfalling down below Power-Off Threshold. Please note

that during a slow rampdown, outputs can possibly switch state during this time.

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2

15 I C Serial Communications Macrocell

15.1 I²C SERIAL COMMUNICATIONS MACROCELL OVERVIEW

In the standard use case for the GreenPAK devices, the configuration choices made by the user are stored as bit settings in the

Non-Volatile Memory (NVM), and this information is transferred at startup time to volatile RAM registers that enable the configu-

ration of the macrocells. Other RAM registers in the device are responsible for setting the connections in the Connection Matrix

to route signals in the manner most appropriate for the user’s application.

The I²C Serial Communications Macrocell in this device allows an I²C bus Master to read and write this information via a serial

channel directly to the RAM registers, allowing the remote re-configuration of macrocells, and remote changes to signal chains

within the device.

An I²C bus Master is also able read and write other register bits that are not associated with NVM memory. As an example, the

input lines to the Connection Matrix can be read as digital register bits. These are the signal outputs of each of the macrocells in

the device, giving an I²C bus Master the capability to remotely read the current value of any macrocell.

The user has the flexibility to control read access and write access via registers bits registers [1119:1117]. See Section 15.5 for

more details on I²C read/write memory protection.

15.2 I²C SERIAL COMMUNICATIONS DEVICE ADDRESSING

Each command to the I²C Serial Communications macrocell begins with a Control Byte. The bits inside this Control Byte are

shown in Figure 83. After the Start bit, the first four bits are a control code. Each bit in a control code can be sourced independently

from the register or by value defined externally GPI0, GPIO2, GPIO4, and GPIO5. The LSB of the control code is defined by the

value of GPI0, while the MSB is defined by the value of GPIO5. The address source (either register bit or PIN) for each bit in the

control code is defined by registers [1179:1176]. This gives the user flexibility on the chip level addressing of this device and other

devices on the same I²C bus. The Block Address is the next three bits (A10, A9, A8), which will define the most significant bits

in the addressing of the data to be read or written by the command. The last bit in the Control Byte is the R/W bit, which selects

whether a read command or write command is requested, with a “1” selecting for a Read command, and a “0” selecting for a Write

command. This Control Byte will be followed by an Acknowledge bit (ACK), which is sent by this device to indicate successful

communication of the Control Byte data.

In the I²C-bus specification and user manual, there are two groups of eight addresses (0000 xxx and 1111 xxx) that are reserved

for the special functions, such as a system General Call address. If the user of this device choses to set the Control Code to either

“1111” or “0000” in a system with other slave device, please consult the I²C-bus specification and user manual to understand the

addressing and implementation of these special functions, to insure reliable operation.

In the read and write command address structure, there are a total of 11 bits of addressing, each pointing to a unique byte of

information, resulting in a total address space of 2K bytes. Of this 2K byte address space, the valid addresses accessible to the

I²C Macrocell on the SLG46811 are in the range from 0 (0x00) to 255 (0xFF). The MSB address bits (A10, A9, and A8) will be

“0” for all commands to the SLG46811.

With the exception of the Current Address Read command, all commands will have the Control Byte followed by the Word

Address. Figure 83 shows this basic command structure.

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Start

bit

Acknowledge

bit

Control Byte

Word Address

A

10

A

9

A

8

A

7

A

0

S

X

R/W ACK

Control

Code

Block

Address

Not used, set to

0

Read/Write bit

(1 = Read, 0 = Write)

Figure 83: Basic Command Structure

15.3 I²C SERIAL GENERAL TIMING

General timing characteristics for the I²C Serial Communications macrocell are shown in Figure 84. Timing specifications can be

found in the AC Characteristics section.

t_HIGH

t_F

t_R

t_LOW

SCL

t_{SU STA}

t_{HD DAT}

t_{HD STA}

t_{SU DAT}

t_{SU STO}

SDA IN

t_DH

t_BUF

t_{VD ACK}

ACK 1-bit

SDA OUT

DATA 8-bit

Figure 84: I²C General Timing Characteristics

15.4 I²C SERIAL COMMUNICATIONS COMMANDS

15.4.1 Byte Write Command

Following the Start condition from the Master, the Control Code [4 bits], the Block Address [3 bits], and the R/W bit (set to “0”),

are placed onto the I²C bus by the Master. After the SLG46811 sends an Acknowledge bit (ACK), the next byte transmitted by

the Master is the Word Address. The Block Address (A10, A9, A8), combined with the Word Address (A7 through A0), together

set the internal address pointer in the SLG46811, where the data byte is to be written. After the SLG46811 sends another

Acknowledge bit, the Master will transmit the data byte to be written into the addressed memory location. The SLG46811 again

provides an Acknowledge bit and then the Master generates a Stop condition. The internal write cycle for the data will take place

at the time that the SLG46811 generates the Acknowledge bit.

It is possible to latch all IOs during I²C write command, register [1113] = 1 - Enable. It means that IOs will remain their state until

the write command is done.

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Acknowledge

bit

Acknowledge

bit

Start

bit

Acknowledge

bit

Bus Activity

Control Byte

Word Address

Data

A

10

A

9

A

8

A

7

A

0

D

7

D

0

S

X

W

ACK

SDA LINE

P

Control

Code

Block

Address

Stop

bit

Not used, set to

0

R/W bit = 0

Figure 85: Byte Write Command, R/W = 0

15.4.2 Sequential Write Command

The write Control Byte, Word Address and the first data byte are transmitted to the SLG46811 in the same way as in a Byte Write

command. However, instead of generating a Stop condition, the Bus Master continues to transmit data bytes to the SLG46811.

Each subsequent data byte will increment the internal address counter, and will be written into the next higher byte in the command

addressing. As in the case of the Byte Write command, the internal write cycle will take place at the time that the SLG46811

generates the Acknowledge bit.

Acknowledge

bit

Start

bit

Bus Activity

Data (n + 1)

Data (n + x)

Control Byte

Word Address (n)

Data (n)

A

10

A

9

A

8

ACK

P

SDA LINE

S

X

W

ACK

Control

Code

Block

Address

Stop

bit

Not used, set

to 0

Write bit

Figure 86: Sequential Write Command

15.4.3 Current Address Read Command

The Current Address Read Command reads from the current pointer address location. The address pointer is incremented at the

first STOP bit following any write control byte. For example, if a Sequential Read command (which contains a write control byte)

reads data up to address n, the address pointer would get incremented to n + 1 upon the STOP of that command. Subsequently,

a Current Address Read that follows would start reading data at n + 1. The Current Address Read Command contains the Control

Byte sent by the Master, with the R/W bit = “1”. The SLG46811 will issue an Acknowledge bit, and then transmit eight data bits

for the requested byte. The Master will not issue an Acknowledge bit, and follow immediately with a Stop condition.

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Start

bit

Acknowledge

bit

Stop

bit

Bus Activity

Control Byte

Data (n)

A

10

A

9

A

8

S

X

R

ACK

SDA LINE

P

Control

Code

Block

Address

No ACK

bit

Not used, set to 0

R/W bit = 1

Figure 87: Current Address Read Command, R/W = 1

15.4.4 Random Read Command

The Random Read command starts with a Control Byte (with R/W bit set to “0”, indicating a write command) and Word Address

to set the internal byte address, followed by a Start bit, and then the Control Byte for the read (exactly the same as the Byte Write

command). The Start bit in the middle of the command will halt the decoding of a Write command, but will set the internal address

counter in preparation for the second half of the command. After the Start bit, the Bus Master issues a second control byte with

the R/W bit set to “1”, after which the SLG46811 issues an Acknowledge bit, followed by the requested eight data bits.

Acknowledge

Stop

bit

Start

bit

Bus Activity

Data (n)

Control Byte

Word Address (n)

Control Byte

A

10

A

9

A

8

A

10

A

9

A

8

S

ACK

X

R ACK

P

SDA LINE

S

X

W

ACK

Control

Code

Block

Address

Control

Code

Block

Address

No ACK

bit

Not used, set to 0

Write bit

Read bit

Figure 88: Random Read Command

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15.4.5 Sequential Read Command

The Sequential Read command is initiated in the same way as a Random Read command, except that once the SLG46811

transmits the first data byte, the Bus Master issues an Acknowledge bit as opposed to a Stop condition in a random read. The

Bus Master can continue reading sequential bytes of data, and will terminate the command with a Stop condition.

Acknowledge

Start

bit

Bus Activity

Data (n + 2)

Data (n + x)

Control Byte

Data (n)

Data (n + 1)

A

10

A

9

A

8

ACK

P

SDA LINE

S

X

R

ACK

Control

Code

Block

Address

Stop

bit

No ACK

bit

Read bit

Figure 89: Sequential Read Command

15.4.6 I²C Serial Reset Command

If I²C serial communication is established with the device, it is possible to reset the device to initial power up conditions, including

configuration of all macrocells, and all connections provided by the Connection Matrix. This is implemented by setting

register [1112] I²C reset bit to “1”, which causes the device to re-enable the Power-On Reset (POR) sequence, including the reload

of all register data from NVM. During the POR sequence, the outputs of the device will be in tri-state. After the reset has taken

place, the contents of register [1112] will be set to “0” automatically. The Figure 90 illustrates the sequence of events for this reset

function.

Acknowledge

bit

Acknowledge

bit

Start

bit

Acknowledge

bit

Bus Activity

Control Byte

Word Address

Data

A

10

A

9

A

8

A

7

A

0

D

7

D

0

S

X

W

ACK

SDA LINE

P

Internal Reset bit

Control

Code

Block

Address

Stop

bit

Not used, set

to 0

Write bit

by I2C Stop Signal

Reset-bit register output

DFF output gated by stop signal

Internal POR for core only

Figure 90: Reset Command Timing

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15.5 I²C SERIAL COMMAND REGISTER MAP

There are seven read/write protect modes for the design sequence from being corrupted or copied. See Table 40 for details.

Table 41: Read/Write Protection Options

Protection Modes Configuration

Partly

Lock

Partly

Lock

Read/

Write

Lock

Read2/

Write

Lock

Read

Lock

Write

Register Ad-

Configurations

Unlocked

dress

(Mode 0) (Mode1) (Mode2) (Mode3) (Mode4) (Mode5) (Mode 6)

I²C Byte Write Bit Masking

(section 15.6.1)

I²C Serial Reset Command

(section 15.4.6)

Outputs Latching During I²C

Write

R/W

W

R

-

8C

R/W

R

8B, b'0

8B, b'1

Connection Matrix Virtual

Inputs

R/W

W

R/W

W

R/W

W

R

-

39; 3A, b'6~0

3D~83, 85, 86

0~35

(section 6.3)

Configuration Bits for All

Macrocells

(IO Pins, ACMPs,

Combination Function

Macrocells, etc.)

-

Macrocells Inputs

Configuration (Connection

Matrix Outputs, section 6.2)

W

Protection Mode Enable

Protection Mode Selection

R

8B, b'3

R/W

8B, b'7~5

Macrocells Output Values

(Connection Matrix Inputs,

section 6.1)

36~38; 3A,b'7;

3B; 3C,'b4~0

R

-

R

-

I²C Control Code

(section 15.2)

R

93, b'3~0

Pin Slave Address Select

I²C Disable/Enable

R

93, b'7~4

94, b'0

Programming

disable

R

94, b'1

94, b'2

Code Compare Enable

R/W

W

R

Allow Read and Write Data

Allow Write Data Only

Allow Read Data Only

-

The Data is protected for Read and Write

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It is possible to read some data from macrocells, such as connection matrix, Shift Registers State, and connection matrix virtual

inputs. The I²C write will not have any impact on data in case data comes from macrocell output, except Connection Matrix Virtual

Inputs. The silicon identification service bits allows identifying silicon family, its revision, and others.

See Section 18 for detailed information on all registers.

15.6 I²C ADDITIONAL OPTIONS

When Output latching during I²C write, register [1113] = 1 allows all PINs output value to be latched until I²C write is done. It will

protect the output change due to configuration process during I²C write in case multiple register bytes are changed. Inputs and

internal macrocells retain their status during I²C write.

If the user sets GPIO0 and GPIO1 function to a selection other than SDA and SCL, all access via I²C will be disabled.

Note: Any write commands that come to the device via I²C that are not blocked, based on the protection bits, will change the

contents of the RAM register bits that mirror the NVM bits. These write commands will not change the NVM bits themselves, and

a POR event will restore the register bits to original programmed contents of the NVM.

See Section 18 for detailed information on all registers.

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15.6.1 I²C Byte Write Bit Masking

The I²C macrocell inside SLG46811 supports masking of individual bits within a byte that is written to the RAM memory space.

This function is supported across the entire RAM memory space. To implement this function, the user performs a Byte Write

Command (see Section 15.4.1 for details) on the I²C Byte Write Mask Register (address 0F6H) with the desired bit mask pattern.

This sets a bit mask pattern for the target memory location that will take effect on the next Byte Write Command to this register

byte. Any bit in the mask that is set to “1” in the I²C Byte Write Mask Register will mask the effect of changing that particular bit

in the target register, during the next Byte Write Command. The contents of the I²C Byte Write Mask Register are reset (set to

00h) after valid Byte Write Command. If the next command received by the device is not a Byte Write Command, the effect of the

bit masking function will be aborted, and the I²C Byte Write Mask Register will be reset with no effect. Figure 91 shows an example

of this function.

User Actions



Byte Write Command, Address = 8Ch, Data = 11110000b [sets mask bits]

Byte Write Command, Address = 74h, Data = 10101010b [writes data with mask]

Memory Address 74h (original contents)

Mask to choose bit from new

write command

1

0

1

0

Mask to choose bit from

original register contents

Memory Address 74h (new data in write command)

0 1

1

0

1

0

Bit from new write command

Memory Address 8Ch (mask register)

1

0

Bit from original register

contents

Memory Address 74h (new contents after write command)

1

0

1

0

1

0

Figure 91: Example of I²C Byte Write Bit Masking

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16 Extended Pattern Generator

SLG46811 has an ability to read the data from the part of NVM and to set this data to the matrix inputs. This is done with help of

Extended Pattern Generator that shares its output with I²C virtual inputs. Figure 92 shows I²C General block diagram with

shared outputs. Registers [1078:1064] define I²C block configuration as Virtual Inputs or Pattern Generator, or GPI.

I2C

Pat Gen 0 or Virt.input 0

Pat Gen 1 or Virt.input 1

nReset

Pat Gen 2 or Virt.input 2

Pattern

Pat Gen 3 or Virt.input 3

Pat Gen 4 or Virt.input 4

Pat Gen 5 or Virt.input 5

Pat Gen 6 or Virt.input 6 or GPI (GPIO0)

Pat Gen 7 or Virt.input 7 or GPI (GPIO1)

Clk

Generator

or

Virtual input

SDA

SCL

GPI (GPIO2) or Virt.input 8

GPI (GPIO3) or Virt.input 9

GPI (GPIO4) or Virt.input 10

GPI (GPIO5) or Virt.input 11

GPI (GPIO6) or Virt.input 12

GPI (GPIO7) or Virt.input 13

GPI (GPIO8) or Virt.input 14

GPI

or

Virtual input

Figure 92: I²C General Block Diagram

Initial value of Extended Pattern Generator is defined by registers [495:488]. This value appears at the output of the macrocell

after power up event and after applying low level at nReset input.

Every rising edge at Clk input generator loads byte from the NVM and this data appears at Pattern Generator outputs. The

internal NVM pointer increases by 1. At the next rising edge new data from the next NVM byte will be loaded. The range of the

data for the Extended Pattern Generator is 92 bytes from the NVM bit [1280] to the NVM bit [2015]. User can select the behavior

of the Generator when the internal pointer reaches the last address of the NVM:



If register [564] = 0, the internal counter will overflow.

If register [564] = 1, the internal counter will stop when reaching the last byte of the NVM.

The maximum allowable speed of the EPG is 1 MHz.

The minimum duration of the clock pulse low and high level is 100 ns.

Low level at nReset input sets NVM pointer to the beginning and loads the initial value to the outputs.

User can select any of Pattern Generator outputs to operate as Virtual Inputs.

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17 Analog Temperature Sensor

The SLG46811 has an Analog Temperature sensor (TS) with an output voltage linearly-proportional to the Centigrade tempera-

ture. TS output can be selected as a source of MS ACMP channel. The TS is rated to operate over a -40°C to 85°C temperature

range. The error in the whole temperature range does not exceed 5.96 %. For more detail refer to section 3.11.

The equation below calculates the typical analog voltage passed from the TS to the ACMPs' IN+ source input for V_DD= 2.3 V to

5.5 V . It is important to note that there will be a chip to chip variation of about ±2 °C.

V_T= -4.8xT + 1825.2

where:

_TS(mV) - TS Output Voltage.

V

T (°C) - Temperature

Temperature hysteresis can be setup by enabling the GreenPAK's internal ACMP hysteresis.

TS

From MS ACMP

V_DD

TS Power Up

To MS ACMP

input

Analog

Signal

OUT

Processing

Figure 93: Analog Temperature Sensor Structure Diagram

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2.1

2

1.9

1.8

1.7

1.6

1.5

1.4

T (°C)

Figure 94: TS Output vs. Temperature, V_DD= 2.3 V to 5.5 V

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18 Register Definitions

18.1 REGISTER MAP

Table 42: Register Map

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

Matrix Output

0

1

2

OUT0:

IN0 of LUT2_0 or Clock Input of DFF0

3

4

0

5

6

LUT2_0 & DFF0

7

8

OUT1:

IN1 of LUT2_0 or Data Input of DFF0

9

10

11

12

1

13

14

15

16

17

18

OUT2:

IN0 of LUT2_1 or Clock Input of DFF1

LUT2_1 & DFF1

19

20

2

OUT3:

IN1 of LUT2_1 or Data Input of DFF1

21

22

23

24

25

26

OUT4:

IN0 of LUT2_2 or Clock Input of PGen

27

3

28

29

30

31

32

LUT2_2 & PGen

OUT5:

IN1 of LUT2_2 or RSTB of PGen

33

34

4

35

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Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

Byte

4

OUT6:

IN0 of LUT3_0 or CLK Input of DFF2

5

6

7

8

OUT7:

LUT3_0 & DFF2

IN1 of LUT3_0 or Data of DFF2

OUT8:

IN2 of LUT3_0 or RSTB (SETB) of DFF2

OUT9:

IN0 of LUT3_1 or CLK Input of DFF3

OUT10:

IN1 of LUT3_1 or Data of DFF3

LUT3_1 & DFF3

OUT11:

IN2 of LUT3_1 or RSTB (SETB) of DFF3

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Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

72

Byte

73

74

OUT12:

IN0 of LUT3_2 or CLK Input of DFF4

75

76

9

77

78

79

80

81

OUT13:

IN1 of LUT3_2 or Data of DFF4

LUT3_2 & DFF4

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

A

B

C

D

E

OUT14:

IN2 of LUT3_2 or RSTB (SETB) of DFF4

OUT15:

IN0 of LUT3_3 or CLK Input of DFF5

OUT16:

IN1 of LUT3_3 or Data of DFF5

LUT3_3 & DFF5

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

OUT17:

IN2 of LUT3_3 or RSTB (SETB) of DFF5

OUT18:

IN0 of LUT3_4 or CLK Input of DFF6 or CLK input of SR0

LUT3_4 & DFF6 & SR0

OUT19:

IN1 of LUT3_4 or Data Input of DFF6 or Data Input of SR0

Datasheet

14-Apr-2021

Revision 3.0

109 of 171

CFR0011-120-00

SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

OUT20:

LUT3_4 & DFF6 & SR0

IN2 of LUT3_4 or RSTB (SETB) of DFF6 or RSTB(SETB)

input of SR0

F

OUT21:

IN0 of LUT3_5 or CLK Input of DFF7 or CLK input of SR1

10

11

12

13

14

OUT22:

LUT3_5 & DFF7 & SR1

IN1 of LUT3_5 or Data of DFF7 or Data Input of SR1

OUT23:

IN2 of LUT3_5 or RSTB (SETB) of DFF7 or RSTB(SETB)

input of SR1

OUT24:

IN0 of LUT3_6 or CLK Input of DFF8 or CLK input of SR2

OUT25:

LUT3_6 & DFF8 & SR2

IN1 of LUT3_6 or Data of DFF8 or Data Input of SR2

OUT26:

IN2 of LUT3_6 or RSTB (SETB) of DFF8 or RSTB(SETB)

input of SR2

OUT27:

LUT3_7 & DFF9 & SR3

IN0 of LUT3_7 or CLK Input of DFF9 or CLK input of SR3

Datasheet

14-Apr-2021

Revision 3.0

110 of 171

CFR0011-120-00

SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

OUT28:

IN1 of LUT3_7 or Data of DFF9 or Data Input of SR3

15

LUT3_7 & DFF9 & SR3

OUT29:

IN2 of LUT3_7 or RSTB (SETB) of DFF9 or RSTB(SETB)

input of SR3

16

17

18

19

1A

OUT30:

IN0 of LUT3_8 or CLK Input of DFF10

Delay0 Input (or Counter5 RSTB Input)

OUT31:

Multi_function0

IN1 of LUT3_8 or RSTB (SETB) of DFF10

Delay0 Input (or Counter5 RSTB Input)

OUT32:

IN2 of LUT3_8 or Data of DFF10

Delay0 Input (or Counter5 RSTB Input)

OUT33:

IN0 of LUT3_9 or CLK Input of DFF111

Delay1 Input (or Counter1 RSTB Input)

OUT34:

Multi_function1

IN1 of LUT3_9 or RSTB (SETB) of DFF11

Delay1 Input (or Counter1 RSTB Input)

OUT35:

IN2 of LUT3_9 or Data of DFF11

Delay1 Input (or Counter1 RSTB Input)

Datasheet

14-Apr-2021

Revision 3.0

111 of 171

CFR0011-120-00

SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

251

252

253

254

255

256

257

258

259

260

261

262

263

OUT36:

IN0 of LUT3_10 or CLK Input of DFF12

Delay2 Input (or Counter2 RSTB Input)

1B

OUT37:

Multi_function2

IN1 of LUT3_10 or RSTB (SETB) of DFF12

Delay2 Input (or Counter2 RSTB Input)

1C

1D

1E

1F

20

OUT38:

IN2 of LUT3_10 or Data of DFF12

Delay2 Input (or Counter2 RSTB Input)

OUT39:

IN0 of LUT3_11 or CLK Input of DFF13

Delay3 Input (or Counter3 RSTB Input)

OUT40:

Multi_function3

IN1 of LUT3_11 or RSTB (SETB) of DFF13

Delay3 Input (or Counter3 RSTB Input)

OUT41:

IN2 of LUT3_11 or Data of DFF13

Delay3 Input (or Counter3 RSTB Input)

OUT42:

IN0 of LUT3_12 or CLK Input of DFF14

Delay4 Input (or Counter5 RSTB Input)

Multi_function4

OUT43:

IN1 of LUT3_12 or RSTB (SETB) of DFF14

Delay4 Input (or Counter5 RSTB Input)

Datasheet

14-Apr-2021

Revision 3.0

112 of 171

CFR0011-120-00

SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

264

265

266

267

268

269

270

271

272

273

274

275

276

277

278

279

280

281

282

283

284

285

286

287

288

289

290

291

292

293

294

295

296

297

298

299

300

301

302

303

304

305

306

307

308

309

310

311

OUT44:

Multi_function4

IN2 of LUT3_12 or Data of DFF14

Delay4 Input (or Counter5 RSTB Input)

21

OUT45:

IN0 of LUT3_13 or CLK Input of DFF15

Delay5 Input (or Counter5 RSTB Input)

22

23

24

25

26

OUT46:

Multi_function5

IN1 of LUT3_13 or RSTB (SETB) of DFF15

Delay5 Input (or Counter5 RSTB Input)

OUT47:

IN2 of LUT3_13 or Data of DFF15

Delay5 Input (or Counter5 RSTB Input)

OUT48:

IN0 of LUT4_0 or CLK Input of DFF16

OUT49:

IN1 of LUT4_0 or Data of DFF16

LUT4_0_DFF16

OUT50:

IN2 of LUT4_0 or RSTB (SETB) of DFF16

OUT51:

IN3 of LUT4_0

Datasheet

14-Apr-2021

Revision 3.0

113 of 171

CFR0011-120-00

SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

312

313

314

315

316

317

318

319

320

321

322

323

324

325

326

327

328

329

330

331

332

333

334

335

336

337

338

339

340

341

342

343

344

345

346

347

348

349

350

351

352

353

354

355

356

357

358

359

OUT52:

Programmable Delay

Programmable Delay/Edge Detect Input

27

OUT53:

Filter/Edge Detect Input

Filter/Edge Detect

28

29

2A

2B

2C

OUT54:

GPIO0 DOUT

GPIO0

OUT55:

GPIO1 DOUT

GPIO1

OUT56:

GPIO2 DOUT

GPIO2

OUT57:

GPIO2 DOUT OE

OUT58:

GPIO3 DOUT

GPIO3

OUT59:

GPIO3 DOUT OE

Datasheet

14-Apr-2021

Revision 3.0

114 of 171

CFR0011-120-00

SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

360

361

362

363

364

365

366

367

368

369

370

371

372

373

374

375

376

377

378

379

380

381

382

383

384

385

386

387

388

389

390

391

392

393

394

395

396

397

398

399

400

401

402

403

404

405

406

407

OUT60:

GPIO4

GPIO4 DOUT

2D

OUT61:

GPIO5 DOUT

GPIO5

GPIO6

2E

2F

30

31

32

OUT62:

GPIO6 DOUT

OUT63:

GPIO7 DOUT

GPIO7

OUT64:

GPIO7 DOUT OE

OUT65:

GPIO8 DOUT

GPIO8

OUT66:

GPIO8 DOUT OE

OUT67:

EN of MS ACMP

MS ACMP

Datasheet

14-Apr-2021

Revision 3.0

115 of 171

CFR0011-120-00

SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

408

409

410

411

412

413

414

415

416

417

418

419

420

421

422

423

424

425

426

427

428

429

430

431

432

433

434

435

436

437

438

439

440

441

442

443

444

445

446

447

448

449

450

451

452

453

454

455

OUT68:

MS ACMP

RSTB of ACMP LATs

33

OUT69:

Oscillator Enable/Disable Input

OSC0/1

34

35

36

37

38

OUT70:

Clock of Pattern Generator

EPG

(Embedded Input Pattern Generator)

OUT71:

RESETB of Pattern Generator

Matrix Input 0

Matrix Input 1

Matrix Input 2

Matrix Input 3

Matrix Input 4

Matrix Input 5

Matrix Input 6

Matrix Input 7

Matrix Input 8

Matrix Input 9

Matrix Input 10

Matrix Input 11

Matrix Input 12

Matrix Input 13

Matrix Input 14

Matrix Input 15

Matrix Input 16

Matrix Input 17

Matrix Input 18

Matrix Input 19

Matrix Input 20

Matrix Input 21

Matrix Input 22

Matrix Input 23

GND

LUT2_0/DFF0 output

LUT2_1/DFF1 output

LUT2_2/PGen output

LUT3_0/DFF2 output

LUT3_1/DFF3 output

LUT3_2/DFF4 output

LUT3_3/DFF5 output

LUT3_4/DFF6/SR0 output

LUT3_5/DFF7/SR1 output

LUT3_6/DFF8/SR2 output

LUT3_7/DFF9/SR3 output

CNT0 output

MLT0_LUT3_8/DFF10_OUT

CNT1 output

MLT1_LUT3_9/DFF11_OUT

CNT2 output

MLT2_LUT3_10/DFF12_OUT

CNT3 output

MLT3_LUT3_11/DFF13_OUT

CNT4 output

MLT4_LUT3_12/DFF14_OUT

CNT5 output

MLT5_LUT3_13/DFF15_OUT

Datasheet

14-Apr-2021

Revision 3.0

116 of 171

CFR0011-120-00

SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

456

457

458

459

460

461

462

463

464

465

466

467

468

469

470

471

472

473

474

475

476

477

478

479

480

481

482

483

484

485

486

487

488

489

490

491

492

493

494

495

Virtual_0 Input

Virtual_1 Input

Virtual_2 Input

Virtual_3 Input

Virtual_4 Input

Virtual_5 Input

Virtual_6 Input

Virtual_7 Input

Virtual_8 Input

Virtual_9 Input

Virtual_10 Input

Virtual_11 Input

Virtual_12 Input

Virtual_13 Input

Virtual_14 Input

Matrix Input 39

Matrix Input 40

Matrix Input 41

Matrix Input 42

Matrix Input 43

Matrix Input 44

Matrix Input 45

Matrix Input 46

Matrix Input 47

Matrix Input 48

Matrix Input 49

Matrix Input 50

Matrix Input 51

Matrix Input 52

Reserved

I2C_virtual_0 Input data value

I2C_virtual_1 Input data value

I2C_virtual_2_Input data value

I2C_virtual_3_input data value

I2C_virtual_4 Input data value

I2C_virtual_5 Input data value

I2C_virtual_6 Input data value

I2C_virtual_7 Input data value

I2C_virtual_8 Input data value

I2C_virtual_9 Input data value

I2C_virtual_10 Input data value

I2C_virtual_11 Input data value

I2C_virtual_12 Input data value

I2C_virtual_13 Input data value

I2C_virtual_14 Input data value

LUT4_0/DFF16 output

GPI Digital Input

progdly_edgedet output

edgedet_filter output

OSC0 output 0

OSC1 output

ACMP0 Output

ACMP1 Output

ACMP2 Output

ACMP3 Output

OSC0 output 1

39

3A

3B

3C

3D

ACMP sync mode ready

Reset_core_matrix

V_DD

Reserved

EPG

Initial Value at POR & EPG RESETB

(Extended Pattern Generator)

MS ACMP

Datasheet

14-Apr-2021

Revision 3.0

117 of 171

CFR0011-120-00

SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

0: always on,

496

497

498

499

500

Bandgap power down control

Sampling enable

Edge enable

1: power down if no function enable it (ACMP, Vref, TS)

0: regular mode,

1: multi-channel sampling mode

0: level sensitive mode,

1: edge sensitive mode

0: ACMPs out async,

1: ACMPs out sync

Sync enable

3E

V_DDinputenable(ACMPpositiveinputselected 0: disable,

as V_DD1: enable

Temp sensor enable (ACMP positive input se- 0: disable,

)

501

502

lected as TS)

1: enable

00: 1 channel,

01: 2 channels,

10: 3 channels,

11: 4 channels

Define the number of sampling

channels, NUM[1:0]

503

504

505

506

00: APIO0,

Define positive input channel on 1st sampling, 01: APIO1,

CHS0[1:0]

10: APIO2 (or V_DDdecided by register [500]),

11: APIO3 (or TS decided by register [501])

00: APIO0,

Define positive input channel on 2nd sampling, 01: APIO1,

CHS1[1:0] 10: APIO2 (or V_DDdecided by register [500]),

11: APIO3 (or TS decided by register [501])

00: APIO0,

Define positive input channel on 3rd sampling, 01: APIO1,

CHS2[1:0] 10: APIO2 (or V_DDdecided by register [500]),

507

508

509

3F

11: APIO3 (or TS decided by register [501])

510

511

00: APIO0,

Define positive input channel on 4th sampling, 01: APIO1,

CHS3[1:0]

10: APIO2 (or V_DDdecided by register [500]),

11: APIO3 (or TS decided by register [501])

0: not accessible,

1: accessible

0: not accessible,

1: accessible

0: not accessible,

1: accessible

0: not accessible,

1: accessible

00: div1,

01: div2,

10: div4,

11:div8

512

513

514

ACMP LAT0 RST accessible selection

ACMP LAT1 RST accessible selection

ACMP LAT2 RST accessible selection

ACMP LAT3 RST accessible selection

40

515

516

Sampling CK selection

517

518

519

Reserved

Datasheet

14-Apr-2021

Revision 3.0

118 of 171

CFR0011-120-00

SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 42: Register Map (Continued)

Address

Signal Function

ACMP0 hysteresis

ACMP1 hysteresis

ACMP2 hysteresis

Register Bit Definition

Register

Bit

Byte

520

00: 0 mV,

01: 32 mV,

10: 64mV;

11: 192 mV

521

522

523

524

00: 0 mV,

01: 32 mV,

10: 64 mV,

11: 192 mV

41

00: 0 mV,

01: 32 mV,

10: 64 mV,

11: 192 mV

525

526

527

528

00: 0mV,

01: 32 mV,

10: 64 mV,

11: 192 mV

ACMP3 hysteresis

ACMP Gain Divider Select:

00: 1x;

ACMP0 Gain Divider

01: 0.5x;

529

10: 0.33x;

11: 0.25x

530

531

532

533

534

535

536

42

ACMP Vref Select:

ACMP0 Vref

000000: 32 mV ~ 111110: 2.016 V/step = 32 mV;

111111: External Vref

ACMP Gain Divider Select:

00: 1x;

ACMP1 Gain Divider

ACMP1 Vref

01: 0.5x;

10: 0.33x;

11: 0.25x

537

538

539

540

541

542

543

544

43

ACMP Vref Select:

000000: 32 mV ~ 111110: 2.016 V/ step = 32 mV;

111112: External Vref

ACMP Gain Divider Select:

00: 1x;

ACMP2 Gain Divider

ACMP2 Vref

01: 0.5x;

10: 0.33x;

11: 0.25x

545

546

547

548

549

550

551

44

ACMP Vref Select:

000000: 32 mV ~ 111110: 2.016 V/ step = 32 mV;

111111: External Vref

Datasheet

14-Apr-2021

Revision 3.0

119 of 171

CFR0011-120-00

SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

552

ACMP Gain Divider Select:

00: 1x;

ACMP3 Gain Divider

01: 0.5x;

553

10: 0.33x;

11: 0.25x

554

555

556

557

558

559

560

561

562

563

45

ACMP Vref Select:

ACMP3 Vref

000000: 32 mV ~ 111110: 2.016 V/ step = 32 mV;

111111: External Vref

Reserved

EPG CNT overflow/keep selection

0: overflow to A0,

1: keep at FB

46

EPG

564

565

Reserved

OSC0/1

566

567

00: OSC0 (2kHz/10kHz): Controlled by register

OSC1 (25MHz): Controlled by register

01: OSC0 (2kHz/10kHz): Controlled by Matrix Output

OSC1 (25MHz): Controlled by register

10: OSC0 (2kHz/10kHz): Controlled by register

OSC1 (25MHz): Controlled by Matrix Output

11: OSC0 (2kHz/10kHz): Controlled by Matrix Output

OSC1 (25MHz): Controlled by Matrix Output

Oscillator Enable/Disable Input Selection from

Matrix Output

46

Datasheet

14-Apr-2021

Revision 3.0

120 of 171

CFR0011-120-00

SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

0: auto on by delay cells,

1: always on

0: matrix down,

1: matrix on

0: internal OSC1,

1: external clock from GPIO7

568

569

570

571

OSC1 turn on by register

Matrix power down or on select

External clock source enable

Output enable to matrix in 44

47

0: disable,

1: enable

572

573

574

575

576

577

000: /1, 001: /2, 010: /4, 011: /8, 100: /12, 101: /24, 110: /48,

111: N/A

Pre-divider ratio control

000: /1, 001:/2, 010:/3, 011: /4, 100: /8, 101: /12, 110: /24, 111:

/64

Output mux control to matrix in 44

0: auto on by delay cells

1: always on

0: matrix down,

1: matrix on

0: internal OSC0,

1: external clock from GPI

0: 2.048 kHz,

1: 10 kHz

00: div 1;

01: div 2;

10: div 4;

11: div 8

578

579

580

OSC0 turn on by register

Matrix power down or on select

External clock source enable

OSC0 frequency selection

48

581

582

Pre-divider ratio control

583

584

585

586

000: /1, 001:/2, 010:/3, 011: /4, 100: /8, 101: /12, 110: /24, 111:

/64

Output mux control to matrix in 43

Output enable to matrix in 43

0: disable,

1: enable

587

49

588

589

590

000: /1, 001:/2, 010:/3, 011: /4, 100: /8, 101: /12, 110: /24, 111:

/64

OSC0 2nd output mux control to matrix in 49

2nd output enable to matrix in 49

0: disable,

1: enable

591

0: enable,

1: disable

Reserved

0: disable,

1: enable

592

593

594

OSC1 startup delay with 100 ns

Reserved

4A

IO fast Pull-up/down enable

GPI

595

596

597

598

00: digital without Schmitt Trigger,

01: digital with Schmitt Trigger,

10: low voltage digital in,

11: Reserved

00: floating,

01: 10K,

10: 100K,

11: 1M

Input mode configuration

4A

Pull-up/down resistance selection

Pull-up/down selection

0: Pull-down,

1: Pull-up

599

GPIO0

Datasheet

14-Apr-2021

Revision 3.0

121 of 171

CFR0011-120-00

SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

600

00: digital without Schmitt Trigger,

01: digital with Schmitt Trigger,

10: low voltage digital in,

11: reserved

Input mode configuration

601

602

603

Pull-up/down resistance selection

00: floating, 01: 10K, 10: 100K, 11: 1M

4B

0: Pull-down,

1: Pull-up

0: I2C fast mode +,

1: I2C standard/fast mode

604

605

Pull-up/down selection

I²C mode selection

0: disable,

1: enable (3.2x)

606

607

Open-drain output enable (3.2x drivability)

Reserved

GPIO1

608

609

00: digital without Schmitt Trigger,

01: digital with Schmitt Trigger,

10: low voltage digital in,

11: reserved

Input mode configuration

610

611

Pull-up/down resistance selection

00: floating, 01: 10K, 10: 100K, 11: 1M

4C

0: Pull-down,

1: Pull-up

0: disable,

1: enable (3.2x)

612

613

Pull-up/down selection

Open-drain output enable (3.2x drivability)

614

615

Reserved

GPIO2

616

617

618

619

00: digital without Schmitt Trigger,

01: digital with Schmitt Trigger,

10: low voltage digital in,

11: reserved

00: Push-Pull 1x,

01: Push-Pull 2x,

10: 1x Open-Drain,

11: 2x Open-Drain

Input mode configuration

Output mode configuration

4D

620

621

Pull-up/down resistance selection

00: floating, 01: 10K, 10: 100K, 11: 1M

0: Pull-down,

1: Pull-up

622

623

Pull-up/down selection

Reserved

GPIO3

624

625

626

627

00: digital without Schmitt Trigger,

01: digital with Schmitt Trigger,

10: low voltage digital in,

11: analog IO

00: Push-Pull 1x,

01: Push-Pull 2x,

10: 1x Open-Drain,

11: 2x Open-Drain

Input mode configuration

Output mode configuration

4E

628

629

Pull-up/down resistance selection

00: floating, 01: 10K, 10: 100K, 11: 1M

0: Pull-down,

1: Pull-up

630

631

Pull-up/down selection

Reserved

Datasheet

14-Apr-2021

Revision 3.0

122 of 171

CFR0011-120-00

SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

GPIO4

632

633

634

635

00: digital without Schmitt Trigger,

01: digital with Schmitt Trigger,

10: low voltage digital in,

11: analog IO

00: Push-Pull 1x,

01: Push-Pull 2x,

10: 1x Open-Drain,

11: 2x Open-Drain

Input mode configuration

Output mode configuration

4F

636

637

Pull-up/down resistance selection

00: floating, 01: 10K, 10: 100K, 11: 1M

0: Pull-down,

1: Pull-up

0: input,

1: output

638

639

Pull-up/down selection

Input mode/output mode selection

GPIO5

640

641

642

643

00: digital without Schmitt Trigger,

01: digital with Schmitt Trigger,

10: low voltage digital in,

11: analog IO

00: Push-Pull 1x,

01: Push-Pull 2x,

10: 1x Open-Drain,

11: 2x Open-Drain

Input mode configuration

Output mode configuration

50

644

645

Pull-up/down resistance selection

00: floating, 01: 10K, 10: 100K, 11: 1M

0: Pull-down,

1: Pull-up

0: input,

1: output

646

647

Pull-up/down selection

Input mode/output mode selection

GPIO6

648

649

650

651

00: digital without Schmitt Trigger,

01: digital with Schmitt Trigger,

10: low voltage digital in,

11: analog IO

00: Push-Pull 1x,

01: Push-Pull 2x,

10: 1x Open-Drain,

11: 2x Open-Drain

Input mode configuration

Output mode configuration

51

652

653

Pull-up/down resistance selection

00: floating, 01: 10K, 10: 100K, 11: 1M

0: Pull-down,

1: Pull-up

0: input,

1: output

654

655

Pull-up/down selection

Input mode/output mode Selection

GPIO7

656

657

658

659

00: digital without Schmitt Trigger,

01: digital with Schmitt Trigger,

10: low voltage digital in,

11: analog IO

00: Push-Pull 1x,

01: Push-Pull 2x,

10: 1x Open-Drain,

11: 2x Open-Drain

Input mode configuration

Output mode configuration

52

Datasheet

14-Apr-2021

Revision 3.0

123 of 171

CFR0011-120-00

SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

660

661

Pull-up/down resistance selection

00: floating, 01: 10K, 10: 100K, 11: 1M

0: Pull-down,

1: Pull-up

0: disable,

1: enable

52

662

663

Pull-up/down selection

Analog input enable for ACMP3 IP

GPIO8

664

665

666

00: digital without Schmitt Trigger,

01: digital with Schmitt Trigger,

10: low voltage digital in,

11: Reserved

00: Push-Pull 1x,

01: Push-Pull 2x,

10: 1x Open-Drain,

11: 2x Open-Drain

Input mode configuration

Output mode configuration

667

53

668

669

Pull-up/down resistance selection

00: floating, 01: 10K, 10: 100K, 11: 1M

0: Pull-down,

1: Pull-up

670

671

Pull-up/down selection

Reserved

00000: Matrix A - In2; Matrix B - In1;

Matrix C - In0

(DLY_IN - LOW)

Single 3-bit LUT

10000: Matrix A - D; Matrix B - nSET/nRST; Matrix C - CLK

(DLY_IN - LOW)

00001: Matrix A- DLY_IN (CNT); Matrix B - EXT_CLK (CNT);

Matrix C - NC

(DLY_OUT connected to LUT/DFF)

Single DFF w RST and SET

Single CNT/DLY

00010: Matrix A - DLY_IN; Matrix B - In1; Matrix C - In0

(DLY_OUT connected to In2)

CNT/DLY → LUT

10010: Matrix A - DLY_IN; Matrix B - nSET/nRST;

Matrix C - CLK

(DLY_OUT connected to D)

CNT/DLY → DFF

54

676:672

00110: Matrix A - In2; Matrix B - DLY_IN; Matrix C - In0

(DLY_OUT connected to In1)

10110: Matrix A - D; Matrix B - DLY_IN; Matrix C - CLK

(DLY_OUT connected to nSET/nRST)

CNT/DLY → LUT

CNT/DLY → DFF

01010: Matrix A - In2; Matrix B - In1;

Matrix C - DLY_IN

(DLY_OUT connected to In0)

CNT/DLY → LUT

11010: MatrixA- D; Matrix B - nSET/nRST; Matrix C - DLY_IN

(DLY_OUT connected to CLK)

00011: Matrix A - In2; Matrix B - In1; Matrix C - In0

(LUT_OUT connected to DLY_IN)

10011: Matrix A - D; Matrix B - nSET/nRST; Matrix C - CLK

(DFF_OUT connected to DLY_IN)

CNT/DLY → DFF

LUT → CNT/DLY

DFF → CNT/DLY

Datasheet

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Revision 3.0

124 of 171

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SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

677

678

679

0000: both edge Delay;

0001: falling edge delay;

0010: rising edge delay:

0011: both edge One Shot;

0100: falling edge One Shot;

0101: rising edge One Shot;

0110: both edge freq detect;

0111: falling edge freq detect;

1000: rising edge freq detect;

1001: both edge detect;

54

CNT0 function and edge mode selection

680

1010: falling edge detect;

1011: rising edge detect;

1100: both edge reset cnt;

1101: falling edge reset cnt;

1110: rising edge reset cnt;

1111: high level reset cnt

681

682

00: bypass the initial;

01: initial 0;

CNT0 initial value selection

10: initial 1;

11: initial 1

55

683

684

685

Clock source sel [3:0]

0000: OSC1(25MHz);

0001: OSC1/4;

0010: OSC1/8;

0011: OSC1/64;

0100: OSC1/512;

0101: OSC0(2K/10KHz);

0110: OSC0/8;

DLY/CNT0 Clock Source Select

0111: OSC0/12;

686

1000: OSC0/24;

1001: OSC0/64;

1010: OSC0/512;

1011: OSC0/4096

1100: CNT4_END;

1101: External;

0: Default Output,

1: Inverted Output

0: bypass;

1: after two DFF

687

688

CNT0 output pol selection

CNT0 CNT mode SYNC selection

0: normal;

689

690

CNT0 DLY EDET FUNCTION Selection

CNT0 SET/RST Selection

1: DLY function edge detection (registers [679:677] = 0000/

0001/0010)

0: Reset to 0 (High CNT output at CNT reset),

1: Set to data (Low CNT output at CNT reset)

0: bypass;

691

692

693

FSM0 UP signal SYCN selection

Reserved

1: after two DFF

56

0: Default Output,

1: Inverted Output

CNT1 output pol selection

0: bypass;

694

695

CNT1 CNT mode SYNC selection

1: after two DFF

0: normal;

CNT1 DLY EDET FUNCTION Selection

1: DLY function edge detection (register [703:701] = 0000/

0001/0010)

Datasheet

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Revision 3.0

125 of 171

CFR0011-120-00

SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

00000: Matrix A - In2; Matrix B - In1;

Matrix C - In0

(DLY_IN - LOW)

Single 3-bit LUT

10000: Matrix A - D; Matrix B - nSET/nRST; Matrix C - CLK

(DLY_IN - LOW)

00001: Matrix A- DLY_IN (CNT); Matrix B - EXT_CLK (CNT);

Matrix C - NC

(DLY_OUT connected to LUT/DFF)

Single DFF w RST and SET

Single CNT/DLY

00010: Matrix A - DLY_IN; Matrix B - In1; Matrix C - In0

(DLY_OUT connected to In2)

CNT/DLY → LUT

10010: Matrix A - DLY_IN; Matrix B - nSET/nRST;

Matrix C - CLK

(DLY_OUT connected to D)

CNT/DLY → DFF

700:696

00110: Matrix A - In2; Matrix B - DLY_IN; Matrix C - In0

(DLY_OUT connected to In1)

10110: Matrix A - D; Matrix B - DLY_IN; Matrix C - CLK

(DLY_OUT connected to nSET/nRST)

CNT/DLY → LUT

CNT/DLY → DFF

57

01010: Matrix A - In2; Matrix B - In1;

Matrix C - DLY_IN

(DLY_OUT connected to In0)

CNT/DLY → LUT

11010: MatrixA- D; Matrix B - nSET/nRST; Matrix C - DLY_IN

(DLY_OUT connected to CLK)

00011: Matrix A - In2; Matrix B - In1; Matrix C - In0

(LUT_OUT connected to DLY_IN)

10011: Matrix A - D; Matrix B - nSET/nRST; Matrix C - CLK

(DFF_OUT connected to DLY_IN)

CNT/DLY → DFF

LUT → CNT/DLY

DFF → CNT/DLY

701

702

703

0000: both edge Delay;

0001: falling edge delay;

0010: rising edge delay:

0011: both edge One Shot;

0100: falling edge One Shot;

0101: rising edge One Shot;

0110: both edge freq detect;

0111: falling edge freq detect;

1000: rising edge freq detect;

1001: both edge detect;

1010: falling edge detect;

1011: rising edge detect;

1100: both edge reset cnt;

1101: falling edge reset cnt;

1110: rising edge reset cnt;

1111: high level reset cnt

CNT1 function and edge mode selection

704

58

705

706

00: bypass the initial;

01: initial 0;

10: initial 1;

CNT1 initial value selection

11: initial 1

Datasheet

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Revision 3.0

126 of 171

CFR0011-120-00

SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

707

708

709

Clock source sel [3:0]

0000: OSC1(25MHz);

0001: OSC1/4;

0010: OSC1/8;

0011: OSC1/64;

0100: OSC1/512;

0101: OSC0(2K/10KHz);

0110: OSC0/8;

DLY/CNT1 Clock Source Select

58

0111: OSC0/12;

710

711

1000: OSC0/24;

1001: OSC0/64;

1010: OSC0/512;

1011: OSC0/4096

1100: CNT4_END;

1101: External;

Reserved

00000: Matrix A - In2; Matrix B - In1;

Matrix C - In0

(DLY_IN - LOW)

Single 3-bit LUT

10000: Matrix A - D; Matrix B - nSET/nRST; Matrix C - CLK

(DLY_IN - LOW)

00001: Matrix A- DLY_IN (CNT); Matrix B - EXT_CLK (CNT);

Matrix C - NC

(DLY_OUT connected to LUT/DFF)

Single DFF w RST and SET

Single CNT/DLY

00010: Matrix A - DLY_IN; Matrix B - In1; Matrix C - In0

(DLY_OUT connected to In2)

CNT/DLY → LUT

10010: Matrix A - DLY_IN; Matrix B - nSET/nRST;

Matrix C - CLK

(DLY_OUT connected to D)

CNT/DLY → DFF

59

716:712

00110: Matrix A - In2; Matrix B - DLY_IN; Matrix C - In0

(DLY_OUT connected to In1)

10110: Matrix A - D; Matrix B - DLY_IN; Matrix C - CLK

(DLY_OUT connected to nSET/nRST)

CNT/DLY → LUT

CNT/DLY → DFF

01010: Matrix A - In2; Matrix B - In1;

Matrix C - DLY_IN

(DLY_OUT connected to In0)

CNT/DLY → LUT

11010: MatrixA- D; Matrix B - nSET/nRST; Matrix C - DLY_IN

(DLY_OUT connected to CLK)

00011: Matrix A - In2; Matrix B - In1; Matrix C - In0

(LUT_OUT connected to DLY_IN)

10011: Matrix A - D; Matrix B - nSET/nRST; Matrix C - CLK

(DFF_OUT connected to DLY_IN)

CNT/DLY → DFF

LUT → CNT/DLY

DFF → CNT/DLY

Datasheet

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Revision 3.0

127 of 171

CFR0011-120-00

SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

717

718

719

0000: both edge Delay;

0001: falling edge delay;

0010: rising edge delay:

0011: both edge One Shot;

0100: falling edge One Shot;

0101: rising edge One Shot;

0110: both edge freq detect;

0111: falling edge freq detect;

1000: rising edge freq detect;

1001: both edge detect;

1010: falling edge detect;

1011: rising edge detect;

1100: both edge reset cnt;

1101: falling edge reset cnt;

1110: rising edge reset cnt;

1111: high level reset cnt

59

CNT2 function and edge mode selection

720

721

722

00: bypass the initial;

01: initial 0;

10: initial 1;

CNT2 initial value selection

11: initial 1

5A

723

724

725

Clock source sel [3:0]

0000: OSC1(25MHz);

0001: OSC1/4;

0010: OSC1/8;

0011: OSC1/64;

0100: OSC1/512;

0101: OSC0(2K/10KHz);

0110: OSC0/8;

DLY/CNT2 Clock Source Select

0111: OSC0/12;

726

1000: OSC0/24;

1001: OSC0/64;

1010: OSC0/512;

1011: OSC0/4096;

1100: CNT4_END;

1101:External;

0: Default Output,

1: Inverted Output

0: bypass;

1: after two DFF

727

728

CNT2 output pol selection

CNT2 CNT mode SYNC selection

0: normal;

729

CNT2 DLY EDET FUNCTION Selection

1: DLY function edge detection (register [719:717] = 0000/

0001/0010)

730

731

Reserved

0: Default Output,

1: Inverted Output

CNT3 output pol selection

5B

0: bypass;

1: after two DFF

732

CNT3 CNT mode SYNC selection

0: normal;

733

734

735

CNT3 DLY EDET FUNCTION Selection

1: DLY function edge detection (registers [743:742] = 0000/

0001/0010)

00: bypass the initial;

01: initial 0;

10: initial 1;

CNT3 initial value selection

11: initial 1

Datasheet

14-Apr-2021

Revision 3.0

128 of 171

CFR0011-120-00

SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

00000: Matrix A - In2; Matrix B - In1;

Matrix C - In0

(DLY_IN - LOW)

Single 3-bit LUT

10000: Matrix A - D; Matrix B - nSET/nRST; Matrix C - CLK

(DLY_IN - LOW)

00001: Matrix A- DLY_IN (CNT); Matrix B - EXT_CLK (CNT);

Matrix C - NC

(DLY_OUT connected to LUT/DFF)

Single DFF w RST and SET

Single CNT/DLY

00010: Matrix A - DLY_IN; Matrix B - In1; Matrix C - In0

(DLY_OUT connected to In2)

CNT/DLY → LUT

10010: Matrix A - DLY_IN; Matrix B - nSET/nRST;

Matrix C - CLK

(DLY_OUT connected to D)

CNT/DLY → DFF

740:736

00110: Matrix A - In2; Matrix B - DLY_IN; Matrix C - In0

(DLY_OUT connected to In1)

10110: Matrix A - D; Matrix B - DLY_IN; Matrix C - CLK

(DLY_OUT connected to nSET/nRST)

CNT/DLY → LUT

CNT/DLY → DFF

5C

01010: Matrix A - In2; Matrix B - In1;

Matrix C - DLY_IN

(DLY_OUT connected to In0)

CNT/DLY → LUT

11010: MatrixA- D; Matrix B - nSET/nRST; Matrix C - DLY_IN

(DLY_OUT connected to CLK)

00011: Matrix A - In2; Matrix B - In1; Matrix C - In0

(LUT_OUT connected to DLY_IN)

10011: Matrix A - D; Matrix B - nSET/nRST; Matrix C - CLK

(DFF_OUT connected to DLY_IN)

CNT/DLY → DFF

LUT → CNT/DLY

DFF → CNT/DLY

741

742

743

0000: both edge Delay;

0001: falling edge delay;

0010: rising edge delay:

0011: both edge One Shot;

0100: falling edge One Shot;

0101: rising edge One Shot;

0110: both edge freq detect;

0111: falling edge freq detect;

1000: rising edge freq detect;

1001: both edge detect;

CNT3 function and edge mode selection

5D

744

1010: falling edge detect;

1011: rising edge detect;

1100: both edge reset cnt;

1101: falling edge reset cnt;

1110: rising edge reset cnt;

1111: high level reset cnt

Datasheet

14-Apr-2021

Revision 3.0

129 of 171

CFR0011-120-00

SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

745

746

747

Clock source sel [3:0]

0000: OSC1(25MHz);

0001: OSC1/4;

0010: OSC1/8;

0011: OSC1/64;

0100: OSC1/512;

0101: OSC0 (2K/10KHz);

0110: OSC0/8;

DLY/CNT3 Clock Source Select

0111: OSC0/12;

748

1000: OSC0/24;

1001: OSC0/64;

1010: OSC0/512;

1011: OSC0/4096

1100: CNT4_END;

1101:External;

5D

0: Default Output,

1: Inverted Output

0: bypass;

1: after two DFF

749

750

CNT4 output pol selection

CNT4 CNT mode SYNC selection

0: normal;

751

CNT4 DLY EDET FUNCTION Selection

1: DLY function edge detection (registers [759:757] = 0000/

0001/0010)

00000: Matrix A - In2; Matrix B - In1;

Matrix C - In0

(DLY_IN - LOW)

Single 3-bit LUT

10000: Matrix A - D; Matrix B - nSET/nRST; Matrix C - CLK

(DLY_IN - LOW)

00001: Matrix A- DLY_IN (CNT); Matrix B - EXT_CLK (CNT);

Matrix C - NC

(DLY_OUT connected to LUT/DFF)

Single DFF w RST and SET

Single CNT/DLY

00010: Matrix A - DLY_IN; Matrix B - In1; Matrix C - In0

(DLY_OUT connected to In2)

CNT/DLY → LUT

10010: Matrix A - DLY_IN; Matrix B - nSET/nRST;

Matrix C - CLK

(DLY_OUT connected to D)

CNT/DLY → DFF

5E

756:752

00110: Matrix A - In2; Matrix B - DLY_IN; Matrix C - In0

(DLY_OUT connected to In1)

10110: Matrix A - D; Matrix B - DLY_IN; Matrix C - CLK

(DLY_OUT connected to nSET/nRST)

CNT/DLY → LUT

CNT/DLY → DFF

01010: Matrix A - In2; Matrix B - In1;

Matrix C - DLY_IN

(DLY_OUT connected to In0)

CNT/DLY → LUT

11010: MatrixA- D; Matrix B - nSET/nRST; Matrix C - DLY_IN

(DLY_OUT connected to CLK)

00011: Matrix A - In2; Matrix B - In1; Matrix C - In0

(LUT_OUT connected to DLY_IN)

10011: Matrix A - D; Matrix B - nSET/nRST; Matrix C - CLK

(DFF_OUT connected to DLY_IN)

CNT/DLY → DFF

LUT → CNT/DLY

DFF → CNT/DLY

Datasheet

14-Apr-2021

Revision 3.0

130 of 171

CFR0011-120-00

SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

757

758

759

0000: both edge Delay;

0001: falling edge delay;

0010: rising edge delay:

0011: both edge One Shot;

0100: falling edge One Shot;

0101: rising edge One Shot;

0110: both edge freq detect;

0111: falling edge freq detect;

1000: rising edge freq detect;

1001: both edge detect;

1010: falling edge detect;

1011: rising edge detect;

1100: both edge reset cnt;

1101: falling edge reset cnt;

1110: rising edge reset cnt;

1111: high level reset cnt

5E

CNT4 function and edge mode selection

760

761

762

00: bypass the initial;

01: initial 0;

10: initial 1;

CNT4 initial value selection

5F

11: initial 1

763

764

765

Clock source sel [3:0]

0000: OSC1(25MHz);

0001: OSC1/4;

0010: OSC1/8;

0011: OSC1/64;

0100: OSC1/512;

0101: OSC0(2K/10KHz);

0110: OSC0/8;

DLY/CNT4 Clock Source Select

0111: OSC0/12;

766

767

1000: OSC0/24;

1001: OSC0/64;

1010: OSC0/512;

1011: OSC0/4096

1100: CNT4_END;

1101: External;

Reserved

00000: Matrix A - In2; Matrix B - In1;

Matrix C - In0

(DLY_IN - LOW)

Single 3-bit LUT

10000: Matrix A - D; Matrix B - nSET/nRST; Matrix C - CLK

(DLY_IN - LOW)

00001: Matrix A- DLY_IN (CNT); Matrix B - EXT_CLK (CNT);

Matrix C - NC

(DLY_OUT connected to LUT/DFF)

Single DFF w RST and SET

Single CNT/DLY

60

772:768

00010: Matrix A - DLY_IN; Matrix B - In1; Matrix C - In0

(DLY_OUT connected to In2)

CNT/DLY → LUT

10010: Matrix A - DLY_IN; Matrix B - nSET/nRST;

Matrix C - CLK

(DLY_OUT connected to D)

CNT/DLY → DFF

00110: Matrix A - In2; Matrix B - DLY_IN; Matrix C - In0

(DLY_OUT connected to In1)

10110: Matrix A - D; Matrix B - DLY_IN; Matrix C - CLK

(DLY_OUT connected to nSET/nRST)

CNT/DLY → LUT

CNT/DLY → DFF

Datasheet

14-Apr-2021

Revision 3.0

131 of 171

CFR0011-120-00

SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

01010: Matrix A - In2; Matrix B - In1;

Matrix C - DLY_IN

(DLY_OUT connected to In0)

CNT/DLY → LUT

11010: MatrixA- D; Matrix B - nSET/nRST; Matrix C - DLY_IN

(DLY_OUT connected to CLK)

00011: Matrix A - In2; Matrix B - In1; Matrix C - In0

(LUT_OUT connected to DLY_IN)

10011: Matrix A - D; Matrix B - nSET/nRST; Matrix C - CLK

(DFF_OUT connected to DLY_IN)

CNT/DLY → DFF

LUT → CNT/DLY

DFF → CNT/DLY

772:768

60

773

774

775

0000: both edge Delay;

0001: falling edge delay;

0010: rising edge delay:

0011: both edge One Shot;

0100: falling edge One Shot;

0101: rising edge One Shot;

0110: both edge freq detect;

0111: falling edge freq detect;

1000: rising edge freq detect;

1001: both edge detect;

CNT5 function and edge mode selection

776

1010: falling edge detect;

1011: rising edge detect;

1100: both edge reset cnt;

1101: falling edge reset cnt;

1110: rising edge reset cnt;

1111: high level reset cnt

777

778

00: bypass the initial;

01: initial 0;

CNT5 initial value selection

10: initial 1;

11: initial 1

61

779

780

781

Clock source sel [3:0]

0000: OSC1(25MHz);

0001: OSC1/4;

0010: OSC1/8;

0011: OSC1/64;

0100: OSC1/512;

0101: OSC0 (2K/10KHz);

0110: OSC0/8;

DLY/CNT5 Clock Source Select

0111: OSC0/12;

782

1000: OSC0/24;

1001: OSC0/64;

1010: OSC0/512;

1011: OSC0/4096

1100: CNT4_END;

1101:External;

0: Default Output,

1: Inverted Output

0: bypass;

1: after two DFF

783

784

CNT5 output pol selection

CNT5 CNT mode SYNC selection

0: normal;

785

CNT5 DLY EDET FUNCTION Selection

1: DLY function edge detection (registers [775:773] = 0000/

0001/0010)

786

787

788

789

790

791

Reserved

62

Datasheet

14-Apr-2021

Revision 3.0

132 of 171

CFR0011-120-00

SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

792

793

794

795

796

797

798

799

800

801

802

803

804

805

806

807

808

809

810

811

812

813

814

815

816

817

818

819

820

821

822

823

824

825

826

827

828

829

830

831

832

833

834

835

836

837

838

839

[7]:LUT3_8 [7]/DFF10 or LATCH Select

0: DFF function, 1: LATCH function

[6]:LUT3_8 [6]/DFF10 Output Select

0: Q output, 1: QB output

63

Multi0_LUT3_8_DFF10 setting

[5]:LUT3_8 [5]/DFF10

0: RSTB from Matrix Output, 1: SETB from Matrix Output

[4]:LUT3_8 [4]/DFF10 Initial Polarity Select

0: Low, 1: High

[3:0]:LUT3_8 [3:0]

64

65

66

67

68

REG_CNT0_D[7:0]

Data[7:0]

[7]:LUT3_9 [7]/DFF11 or LATCH Select

0: DFF function, 1: LATCH function

[6]:LUT3_9 [6]/DFF11 Output Select

0: Q output, 1: QB output

Multi1_LUT3_9_DFF11 setting

[5]:LUT3_9 [5]/DFF11

0: RSTB from Matrix Output, 1: SETB from Matrix Output

[4]:LUT3_9 [4]/DFF11 Initial Polarity Select

0: Low, 1: High

[3:0]:LUT3_9 [3:0]

REG_CNT1_D[7:0]

Data[7:0]

[7]:LUT3_10 [7]/DFF12 or LATCH Select

0: DFF function, 1: LATCH function

[6]:LUT3_10 [6]/DFF12 Output Select

0: Q output, 1: QB output

Multi2_LUT3_10_DFF12 setting

[5]:LUT3_10 [5]/DFF12

0: RSTB from Matrix Output, 1: SETB from Matrix Output

[4]:LUT3_10 [4]/DFF12 Initial Polarity Select

0: Low, 1: High

[3:0]:LUT3_10 [3:0]

REG_CNT2_D[7:0]

Data[7:0]

Datasheet

14-Apr-2021

Revision 3.0

133 of 171

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SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

840

841

842

843

844

845

846

847

848

849

850

851

852

853

854

855

856

857

858

859

860

861

862

863

864

865

866

867

868

869

870

871

872

873

874

875

876

877

878

879

880

881

882

883

884

885

886

887

[7]:LUT3_11 [7]/DFF13 or LATCH Select

0: DFF function, 1: LATCH function

[6]:LUT3_11 [6]/DFF13 Output Select

0: Q output, 1: QB output

69

Multi3_LUT3_11_DFF13 setting

[5]:LUT3_11 [5]/DFF13

0: RSTB from Matrix Output, 1: SETB from Matrix Output

[4]:LUT3_11 [4]/DFF13 Initial Polarity Select

0: Low, 1: High

[3:0]:LUT3_11 [3:0]

6A

6B

6C

6D

6E

REG_CNT3_D[7:0]

Data [7:0]

[7]:LUT3_12 [7]/DFF14 or LATCH Select

0: DFF function, 1: LATCH function

[6]:LUT3_12 [6]/DFF14 Output Select

0: Q output, 1: QB output

Multi4_LUT3_12_DFF14 setting

[5]:LUT3_12 [5]/DFF14

0: RSTB from Matrix Output, 1: SETB from Matrix Output

[4]:LUT3_12 [4]/DFF14 Initial Polarity Select

0: Low, 1: High

[3:0]:LUT3_12 [3:0]

REG_CNT4_D[7:0]

Data [7:0]

[7]:LUT3_13 [7]/DFF15 or LATCH Select

0: DFF function, 1: LATCH function

[6]:LUT3_13 [6]/DFF15 Output Select

0: Q output, 1: QB output

Multi5_LUT3_13_DFF15 setting

[5]:LUT3_13 [5]/DFF15

0: RSTB from Matrix Output, 1: SETB from Matrix Output

[4]:LUT3_13 [4]/DFF15 Initial Polarity Select

0: Low, 1: High

[3:0]:LUT3_13 [3:0]

REG_CNT5_D[7:0]

Data[7:0]

Datasheet

14-Apr-2021

Revision 3.0

134 of 171

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SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

888

889

890

891

892

893

894

[7]:LUT3_0 [7]/DFF2 or LATCH Select

0: DFF function, 1: LATCH function

[6]:LUT3_0 [6]/DFF2 Output Select

0: Q output, 1: QB output

[5]:LUT3_0 [5]/DFF2 Initial Polarity Select

0: Low, 1: High

6F

LUT3_0_DFF2 setting

[4]:LUT3_0 [4]/DFF2 stage selection

0: Q of first DFF; 1: Q of second DFF

[3]:LUT3_0 [3]/DFF2

0: RSTB from Matrix Output, 1: SETB from Matrix Output

[2]:LUT3_0 [2]/DFF2 Active level selection for RST/SET

0: Active low level reset/set, 1: Active high level reset/set

[1:0]: LUT3_0 [1:0]

895

896

897

898

899

900

901

902

[7]:LUT3_1 [7]/DFF3 or LATCH Select

0: DFF function, 1: LATCH function

[6]:LUT3_1 [6]/DFF3 Output Select

0: Q output, 1: QB output

[5]:LUT3_1 [5]/DFF3 Initial Polarity Select

0: Low, 1: High

70

71

72

LUT3_1_DFF3 setting

LUT3_2_DFF4 setting

LUT3_3_DFF5 setting

[4]:LUT3_1 [4]/DFF3

0: RSTB from Matrix Output, 1: SETB from Matrix Output

[3]:LUT3_1 [3]/DFF3 Active level selection for RST/SET

0: Active low level reset/set, 1: Active high level reset/set

[2:0]: LUT3_1 [2:0]

903

904

905

906

907

908

909

910

[7]:LUT3_2 [7]/DFF4 or LATCH Select

0: DFF function, 1: LATCH function

[6]:LUT3_2 [6]/DFF4 Output Select

0: Q output, 1: QB output

[5]:LUT3_2 [5]/DFF4 Initial Polarity Select

0: Low, 1: High

[4]:LUT3_2 [4]/DFF4

0: RSTB from Matrix Output, 1: SETB from Matrix Output

[3]:LUT3_2 [3]/DFF4 Active level selection for RST/SET

0: Active low level reset/set, 1: Active high level reset/set

[2:0]: LUT3_2 [2:0]

[7]:LUT3_3 [7]/DFF5 or LATCH Select

0: DFF function, 1: LATCH function

[6]:LUT3_3 [6]/DFF5 Output Select

0: Q output, 1: QB output

[5]:LUT3_3 [5]/DFF5 Initial Polarity Select

0: Low, 1: High

[4]:LUT3_3 [4]/DFF5

0: RSTB from Matrix Output, 1: SETB from Matrix Output

[3]:LUT3_3 [3]/DFF5 Active level selection for RST/SET

0: Active low level reset/set, 1: Active high level reset/set

[2:0]: LUT3_3 [2:0]

0: LUT3_0,

1: DFF2

0: LUT3_1,

1: DFF3

0: LUT3_2,

1: DFF4

0: LUT3_3,

1: DFF5

911

912

913

914

915

916

917

918

919

920

LUT3_0 or DFF2 Select

LUT3_1 or DFF3 Select

LUT3_2 or DFF4 Select

LUT3_3 or DFF5 Select

921

922

923

73

924

925

926

Reserved

0: LUT4_0,

1: DFF16

927

LUT4_0 or DFF16 Select

Datasheet

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Revision 3.0

135 of 171

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SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

928

929

930

931

932

933

934

935

936

937

938

939

940

941

942

943

944

945

946

947

[15]:LUT4_0 [15]/DFF16 or LATCH Select

0: DFF function, 1: LATCH function

[14]:LUT4_0 [14]/DFF16 Output Select

0: Q output, 1: QB output

74

[13]:LUT4_0 [13]/DFF16 Initial Polarity Select

0: Low, 1: High

LUT4_0_DFF16 setting

[12]:LUT4_0 [12]/DFF16 stage selection

0: Q of first DFF; 1 Q of second DFF

[11]:LUT4_0 [11]/DFF16

0: RSTB from Matrix Output, 1: SETB from Matrix Output

[10]:LUT4_0 [10]/DFF16 Active level selection for RST/SET

0: Active low level reset/set, 1: Active high level reset/set

[9:0]: LUT4_0 [9:0]

75

Reserved

0: LUT3_4

948

949

950

951

LUT3_4 or DFF6/LATCH6/SR0 selection

LUT3_5 or DFF7/LATCH7/SR1 selection

LUT3_6 or DFF8/LATCH8/SR2 selection

LUT3_7 or DFF9/LATCH9/SR3 selection

1: DFF6/LATCH6/SR0

76

0: LUT3_5

1: DFF7/LATCH7/SR1

0: LUT3_6

1: DFF8/LATCH8/SR2

0: LUT3_7

1: DFF9/LATCH9/SR3

952

953

954

955

956

957

958

[7]:DFF or LATCH Select

0: DFF function,

1: LATCH function

[6]:DFF/LATCH/SR/Output polarity select

0: non-inverted output,

1: inverted output

[5] Reserved

[4]:DFF/LATCH/SR RSTB or SETB selection

0: RSTB from Matrix Output,

1: SETB from Matrix Output

[3]:DFF/LATCH/SR Active level selection for RST/SET

0: Active low level reset/set,

1: Active high level reset/set

[2:0] SR Output Select

77

DFF6/SR0 setting

000: DFF/1st SR output,

001: 2nd SR output

959

010: 3rd SR output,

011: 4th SR output

100: 5th SR output,

101: 6th SR output

110: 7th SR output,

111: 8th SR output

Datasheet

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Revision 3.0

136 of 171

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SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

960

961

962

963

964

965

966

967

968

969

970

971

972

973

974

[7:1]:LUT [7:1] or SR initial value[7:1]

[0]:LUT [0] or SR initial value [0]

(= DFF/LATCH Initial polarity select)

0: Low, 1: High

78

LUT3_4/DFF6/SR0 setting

[7]:DFF or LATCH Select

0: DFF function,

1: LATCH function

[6]:DFF/LATCH/SR/Output polarity select

0: non-inverted output,

1: inverted output

[5] Reserved

[4]:DFF/LATCH/SR RSTB or SETB selection

0: RSTB from Matrix Output,

1: SETB from Matrix Output

[3]:DFF/LATCH/SR Active level selection for RST/SET

0: Active low level reset/set,

1: Active high level reset/set

[2:0] SR Output Select

79

DFF7/SR1 setting

000: DFF/1st SR output,

001: 2nd SR output

975

010: 3rd SR output,

011: 4th SR output

100: 5th SR output,

101: 6th SR output

110: 7th SR output,

111: 8th SR output

976

977

978

979

980

981

982

983

[7:1]:LUT [7:1] or SR initial value[7:1]

[0]:LUT [0] or SR initial value [0]

(= DFF/LATCH Initial polarity select)

0: Low, 1: High

7A

LUT3_5/DFF7/SR1 setting

Datasheet

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Revision 3.0

137 of 171

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SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

984

985

986

987

988

989

990

[7]: DFF or LATCH Select

0: DFF function,

1: LATCH function

[6]:DFF/LATCH/SR/Output polarity select

0: non-inverted output,

1: inverted output

[5] Reserved

[4]:DFF/LATCH/SR RSTB or SETB selection

0: RSTB from Matrix Output,

1: SETB from Matrix Output

[3]:DFF/LATCH/SR Active level selection for RST/SET

0: Active low level reset/set,

1: Active high level reset/set

[2:0] SR Output Select

7B

DFF8/SR2 setting

000: DFF/1st SR output,

001: 2nd SR output

991

010: 3rd SR output,

011: 4th SR output

100: 5th SR output,

101: 6th SR output

110: 7th SR output,

111: 8th SR output

992

993

994

995

996

997

[7:1]:LUT [7:1] or SR initial value[7:1]

[0]:LUT [0] or SR initial value [0]

(= DFF/LATCH Initial polarity select)

0: Low, 1: High

7C

LUT3_6/DFF8/SR2 setting

998

999

1000

1001

1002

1003

1004

1005

1006

[7]:DFF or LATCH Select

0: DFF function,

1: LATCH function

[6]:DFF/LATCH/SR/Output polarity select

0: non-inverted output,

1: inverted output

[5] Reserved

[4]:DFF/LATCH/SR RSTB or SETB selection

0: RSTB from Matrix Output,

1: SETB from Matrix Output

[3]:DFF/LATCH/SR Active level selection for RST/SET

0: Active low level reset/set,

1: Active high level reset/set

[2:0] SR Output Select

7D

DFF9/SR3 setting

000: DFF/1st SR output,

001: 2nd SR output

1007

010: 3rd SR output,

011: 4th SR output

100: 5th SR output,

101: 6th SR output

110: 7th SR output,

111: 8th SR output

Datasheet

14-Apr-2021

Revision 3.0

138 of 171

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SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1008

1009

1010

1011

1012

1013

1014

1015

1016

1017

1018

[7:1]:LUT [7:1] or SR initial value[7:1]

[0]:LUT [0] or SR initial value [0]

(= DFF/LATCH Initial polarity select)

0: Low, 1: High

7E

LUT3_7/DFF9/SR3 setting

[3]:LUT2_0 [3]/DFF0 or LATCH Select

0: DFF function, 1: LATCH function

[2]:LUT2_0 [2]/DFF0 Output Select

0: Q output, 1: QB output

[1]:LUT2_0 [1]/DFF0 Initial Polarity Select

0: Low, 1: High

[0]:LUT2_0 [0]

[3]:LUT2_1 [3]/DFF1 or LATCH Select

0: DFF function, 1: LATCH function

[2]:LUT2_1 [2]/DFF1 Output Select

0: Q output, 1: QB output

[1]:LUT2_1 [1]/DFF1 Initial Polarity Select

0: Low, 1: High

[0]:LUT2_1 [0]

LUT2_0/DFF0 setting

LUT2_1/DFF1 setting

1019

7F

1020

1021

1022

1023

0: LUT2_0,

1: DFF0

0: LUT2_1,

1: DFF1

0: LUT2_3,

1: PGen

1024

1025

1026

1027

LUT2_0 or DFF0 Select

LUT2_1 or DFF1 Select

LUT2_2 or PGen Select

80

Active level selection for RST/SET for LUT2_2 0: Active low level reset/set,

or PGen

1: Active high level reset/set

1028

1029

LUT2_2[3:0] or PGen BIT

NUMBER[3:0]

LUT2_2_VAL or PGEN_BIT_NUMBER

1030

1031

1032

1033

1034

1035

1036

1037

1038

1039

1040

1041

1042

1043

1044

1045

1046

1047

81

PGen data

PGen Data [15:0]

82

Datasheet

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Revision 3.0

139 of 171

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SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

0, filter,

1048

Filter or Edge Detector Selection

Output Polarity Select

1, edge det

0: output non-invert,

1: output invert

00: Rising Edges Det

01: Falling Edge Det

10: Both Edge Det

11: Both Edge DLY

1049

1050

Select the edge mode

1051

1052

1053

1054

1055

83

00: 125 ns,

Delay Value Select for Programmable Delay & 01: 250 ns,

Edge Detector

10: 375 ns,

11: 500 ns

00: Rising Edge Detector,

Select the Edge Mode of Programmable Delay 01: Falling Edge Detector,

& Edge Detector

10: Both Edge Detector,

11: Both Edge Delay

1056

1057

1058

1059

1060

1061

1062

1063

Reserved

84

Reserved

Matrix Virtual Data

0: matrix in 24 select Pat Gen 0

1064

1065

1066

1067

1068

1069

Pat Gen 0/I²C_virtual input [0] select

1: matrix in 24 select I²C_virtual Input [0]

Pat Gen 1/I2C_virtual input [1] digital

input select

Pat Gen 2/I2C_virtual input [2] digital

input select

Pat Gen 3/I2C_virtual input [3] digital

input select

Pat Gen 4/I2C_virtual input [4] digital

input select

0: matrix in 25 select Pat Gen 1

1: matrix in 25 select I²C_virtual Input [1]

0: matrix in 26 select Pat Gen 2

1: matrix in 26 select I²C_virtual Input [2]

0: matrix in 27 select Pat Gen 3

1: matrix in 27 select I²C_virtual Input [3]

0: matrix in 28 select Pat Gen 4

85

1: matrix in 28 select I²C_virtual Input [4]

Pat Gen 5/I2C_virtual input [5] digital

input select

0: matrix in 28 select Pat Gen 5

1: matrix in 29 select I²C_virtual Input [5]

0: matrix in 30 select Pat Gen 6

1: matrix in 30 select I²C_virtual Input [6] or GPIO0

(at non-i2c mode)

0: matrix in 31 select Pat Gen 7

1: matrix in 31 select I²C_virtual Input [7] or GPIO1

(at non-i2c mode)

Pat Gen 6/I²C_virtual input [6] digital

input select

1070

1071

Pat Gen 7/I²C_virtual input [7] digital input se-

lect

Datasheet

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Revision 3.0

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SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

0: matrix in 32 select GPIO2 digital input (GPIO2)

1: matrix in 32 select I²C_virtual Input [8]

0: matrix in 33 select GPIO3 digital input (GPIO3)

1: matrix in 33 select I²C_virtual Input [9]

1072

1073

1074

1075

1076

1077

1078

GPIO2/I²C_virtual input [8] select

GPIO3 /I²C_virtual input [9] digital input select

GPIO4/I²C_virtual input [10] digital input select

GPIO5/I²C_virtual input [11] digital input select

GPIO6/I²C_virtual input [12] digital input select

GPIO7/I²C_virtual input [13] digital input select

GPIO8/I²C_virtual input [14] digital input select

0: matrix in 34 select GPIO4 digital input (GPIO4)

1: matrix in 34 select I²C_virtual Input [10]

0: matrix in 35 select GPIO5 digital input (GPIO5)

1: matrix in 35 select I²C_virtual Input [11]

0: matrix in 36 select GPIO6 digital input (GPIO6)

1: matrix in 36 select I²C_virtual Input [12]

0: matrix in 37 select GPIO7 digital input (GPIO7)

1: matrix in 37 select I²C_virtual Input [13]

86

0: matrix in 38 select GPIO8 digital input (GPIO8)

1: matrix in 38 select I²C_virtual Input [14]

1079

1080

1081

1082

1083

1084

1085

1086

1087

1088

1089

1090

1091

1092

1093

1094

1095

1096

1097

1098

1099

1100

1101

1102

1103

1104

1105

1106

1107

1108

1109

1110

1111

Reserved

87

88

89

8A

Datasheet

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Revision 3.0

141 of 171

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SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

I2C reset bit with reloading NVM into Data reg- 0: Keep existing condition,

1112

1113

ister (soft reset)

1: Reset execution

0: Disable,

1: Enable

IO Latching Enable During I2C Write Interface

1114

1115

1116

1117

1118

1119

1120

1121

1122

1123

1124

1125

1126

1127

1128

1129

1130

1131

Reserved

8B

1: mask,

0: overwrite

8C

I²C write mask bits

Reserved

8D

0: partial OTP read (A0 to FB)

1: all OTP read (00 to FF)

1132

Testmode EPG

1133

1134

1135

1136

1137

1138

1139

1140

1141

1142

1143

1144

1145

1146

1147

1148

1149

1150

1151

Reserved

8E

8F

Datasheet

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Revision 3.0

142 of 171

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SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1152

1153

1154

1155

1156

1157

1158

1159

1160

1161

1162

1163

1164

1165

1166

1167

1168

1169

1170

1171

1172

1173

1174

1175

1176

1177

1178

1179

Reserved

90

91

92

I²C slave address

0: from register [1176],

1: from GPI

0: from register [1177],

1: from GPIO3

0: from register [1178],

1: from GPIO4

0: from register [1179],

1: from GPIO7

1180

1181

1182

1183

Slave address selection bit0

Slave address selection bit1

Slave address selection bit2

Slave address selection bit3

93

0: I2C operation enable; matrix in 26(27) select

I²C_virtual_0(1) Input

1184

I²C operation disable bit

1: I²C operation disable; matrix in 26(27) select

GPIO3(4) digital input

1185

1186

1187

1188

1189

1190

1191

Reserved

94

Datasheet

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Revision 3.0

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SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1192

1193

1194

1195

1196

1197

1198

1199

1200

1201

1202

1203

1204

1205

1206

1207

1208

1209

1210

1211

1212

1213

1214

1215

1216

1217

1218

1219

1220

1221

1222

1223

1224

1225

1226

1227

1228

1229

1230

1231

1232

1233

1234

1235

1236

1237

1238

1239

Reserved

95

96

97

98

99

9A

Reserved

Datasheet

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Revision 3.0

144 of 171

CFR0011-120-00

SLG46811

GreenPAK Programmable Mixed-Signal Matrix

Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1240

1241

1242

1243

1244

1245

1246

1247

1248

1249

1250

1251

1252

1253

1254

1255

1256

1257

1258

1259

1260

1261

1262

1263

1264

1265

1266

1267

1268

1269

1270

1271

1272

1273

1274

1275

1276

1277

1278

1279

1280

1281

1282

1283

1284

1285

1286

1287

Reserved

9B

9C

9D

9E

9F

A0

EPG Data Byte 0

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Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1288

1289

1290

1291

1292

1293

1294

1295

1296

1297

1298

1299

1300

1301

1302

1303

1304

1305

1306

1307

1308

1309

1310

1311

1312

1313

1314

1315

1316

1317

1318

1319

1320

1321

1322

1323

1324

1325

1326

1327

1328

1329

1330

1331

1332

1333

1334

1335

A1

EPG Data Byte 1

A2

A3

A4

A5

A6

EPG Data Byte 2

EPG Data Byte 3

EPG Data Byte 4

EPG Data Byte 5

EPG Data Byte 6

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Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1336

1337

1338

1339

1340

1341

1342

1343

1344

1345

1346

1347

1348

1349

1350

1351

1352

1353

1354

1355

1356

1357

1358

1359

1360

1361

1362

1363

1364

1365

1366

1367

1368

1369

1370

1371

1372

1373

1374

1375

1376

1377

1378

1379

1380

1381

1382

1383

A7

EPG Data Byte 7

A8

A9

AA

AB

AC

EPG Data Byte 8

EPG Data Byte 9

EPG Data Byte 10

EPG Data Byte 11

EPG Data Byte 12

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Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1384

1385

1386

1387

1388

1389

1390

1391

1392

1393

1394

1395

1396

1397

1398

1399

1400

1401

1402

1403

1404

1405

1406

1407

1408

1409

1410

1411

1412

1413

1414

1415

1416

1417

1418

1419

1420

1421

1422

1423

1424

1425

1426

1427

1428

1429

1430

1431

AD

EPG Data Byte 13

AE

AF

B0

B1

B2

EPG Data Byte 14

EPG Data Byte 15

EPG Data Byte 16

EPG Data Byte 17

EPG Data Byte 18

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Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1432

1433

1434

1435

1436

1437

1438

1439

1440

1441

1442

1443

1444

1445

1446

1447

1448

1449

1450

1451

1452

1453

1454

1455

1456

1457

1458

1459

1460

1461

1462

1463

1464

1465

1466

1467

1468

1469

1470

1471

1472

1473

1474

1475

1476

1477

1478

1479

B3

EPG Data Byte 19

B4

B5

B6

B7

B8

EPG Data Byte 20

EPG Data Byte 21

EPG Data Byte 22

EPG Data Byte 23

EPG Data Byte 24

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Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1480

1481

1482

1483

1484

1485

1486

1487

1488

1489

1490

1491

1492

1493

1494

1495

1496

1497

1498

1499

1500

1501

1502

1503

1504

1505

1506

1507

1508

1509

1510

1511

1512

1513

1514

1515

1516

1517

1518

1519

1520

1521

1522

1523

1524

1525

1526

1527

B9

EPG Data Byte 25

BA

BB

BC

BD

BE

EPG Data Byte 26

EPG Data Byte 27

EPG Data Byte 28

EPG Data Byte 29

EPG Data Byte 30

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Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1528

1529

1530

1531

1532

1533

1534

1535

1536

1537

1538

1539

1540

1541

1542

1543

1544

1545

1546

1547

1548

1549

1550

1551

1552

1553

1554

1555

1556

1557

1558

1559

1560

1561

1562

1563

1564

1565

1566

1567

1568

1569

1570

1571

1572

1573

1574

1575

BF

EPG Data Byte 31

C0

C1

C2

C3

C4

EPG Data Byte 32

EPG Data Byte 33

EPG Data Byte 34

EPG Data Byte 35

EPG Data Byte 36

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Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1576

1577

1578

1579

1580

1581

1582

1583

1584

1585

1586

1587

1588

1589

1590

1591

1592

1593

1594

1595

1596

1597

1598

1599

1600

1601

1602

1603

1604

1605

1606

1607

1608

1609

1610

1611

1612

1613

1614

1615

1616

1617

1618

1619

1620

1621

1622

1623

C5

EPG Data Byte 37

C6

C7

C8

C9

CA

EPG Data Byte 38

EPG Data Byte 39

EPG Data Byte 40

EPG Data Byte 41

EPG Data Byte 42

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Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1624

1625

1626

1627

1628

1629

1630

1631

1632

1633

1634

1635

1636

1637

1638

1639

1640

1641

1642

1643

1644

1645

1646

1647

1648

1649

1650

1651

1652

1653

1654

1655

1656

1657

1658

1659

1660

1661

1662

1663

1664

1665

1666

1667

1668

1669

1670

1671

CB

EPG Data Byte 43

CC

CD

CE

CF

D0

EPG Data Byte 44

EPG Data Byte 45

EPG Data Byte 46

EPG Data Byte 47

EPG Data Byte 48

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Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1672

1673

1674

1675

1676

1677

1678

1679

1680

1681

1682

1683

1684

1685

1686

1687

1688

1689

1690

1691

1692

1693

1694

1695

1696

1697

1698

1699

1700

1701

1702

1703

1704

1705

1706

1707

1708

1709

1710

1711

1712

1713

1714

1715

1716

1717

1718

1719

D1

EPG Data Byte 49

D2

D3

D4

D5

D6

EPG Data Byte 50

EPG Data Byte 51

EPG Data Byte 52

EPG Data Byte 53

EPG Data Byte 54

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Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1720

1721

1722

1723

1724

1725

1726

1727

1728

1729

1730

1731

1732

1733

1734

1735

1736

1737

1738

1739

1740

1741

1742

1743

1744

1745

1746

1747

1748

1749

1750

1751

1752

1753

1754

1755

1756

1757

1758

1759

1760

1761

1762

1763

1764

1765

1766

1767

D7

EPG Data Byte 55

D8

D9

DA

DB

DC

EPG Data Byte 56

EPG Data Byte 57

EPG Data Byte 58

EPG Data Byte 59

EPG Data Byte 60

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Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1768

1769

1770

1771

1772

1773

1774

1775

1776

1777

1778

1779

1780

1781

1782

1783

1784

1785

1786

1787

1788

1789

1790

1791

1792

1793

1794

1795

1796

1797

1798

1799

1800

1801

1802

1803

1804

1805

1806

1807

1808

1809

1810

1811

1812

1813

1814

1815

DD

EPG Data Byte 61

DE

DF

E0

E1

E2

EPG Data Byte 62

EPG Data Byte 63

EPG Data Byte 64

EPG Data Byte 65

EPG Data Byte 66

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Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1816

1817

1818

1819

1820

1821

1822

1823

1824

1825

1826

1827

1828

1829

1830

1831

1832

1833

1834

1835

1836

1837

1838

1839

1840

1841

1842

1843

1844

1845

1846

1847

1848

1849

1850

1851

1852

1853

1854

1855

1856

1857

1858

1859

1860

1861

1862

1863

E3

EPG Data Byte 67

E4

E5

E6

E7

E8

EPG Data Byte 68

EPG Data Byte 69

EPG Data Byte 70

EPG Data Byte 71

EPG Data Byte 72

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Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1864

1865

1866

1867

1868

1869

1870

1871

1872

1873

1874

1875

1876

1877

1878

1879

1880

1881

1882

1883

1884

1885

1886

1887

1888

1889

1890

1891

1892

1893

1894

1895

1896

1897

1898

1899

1900

1901

1902

1903

1904

1905

1906

1907

1908

1909

1910

1911

E9

EPG Data Byte 73

EA

EB

EC

ED

EE

EPG Data Byte 74

EPG Data Byte 75

EPG Data Byte 76

EPG Data Byte 77

EPG Data Byte 78

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Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1912

1913

1914

1915

1916

1917

1918

1919

1920

1921

1922

1923

1924

1925

1926

1927

1928

1929

1930

1931

1932

1933

1934

1935

1936

1937

1938

1939

1940

1941

1942

1943

1944

1945

1946

1947

1948

1949

1950

1951

1952

1953

EF

EPG Data Byte 79

F0

F1

F2

F3

EPG Data Byte 80

EPG Data Byte 81

EPG Data Byte 82

EPG Data Byte 83

1954

1955

1956

1957

1958

1959

F4

EPG Data Byte 84

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Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1960

1961

1962

1963

1964

1965

1966

1967

1968

1969

1970

1971

1972

1973

1974

1975

1976

1977

1978

1979

1980

1981

1982

1983

1984

1985

1986

1987

1988

1989

1990

1991

1992

1993

1994

1995

1996

1997

1998

1999

2000

2001

2002

2003

2004

2005

2006

2007

F5

EPG Data Byte 85

F6

F7

F8

F9

FA

EPG Data Byte 86

EPG Data Byte 87

EPG Data Byte 88

EPG Data Byte 89

EPG Data Byte 90

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Table 42: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

2008

2009

2010

2011

2012

2013

2014

2015

2016

2017

2018

2019

2020

2021

2022

2023

2024

2025

2026

2027

2028

2029

2030

2031

2032

2033

2034

2035

2036

2037

2038

2039

2040

2041

2042

2043

2044

2045

2046

2047

FB

EPG Data Byte 91

Reserved

FC

FD

FE

FF

NVM CRC Remainder

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19 Package Top Marking Definitions

19.1 STQFN 12L 1.6 MM X 1.6 MM 0.4P FC, BEFORE FEBRUARY 1, 2021

Part Code + Assembly

PPA

WWR

Date Code + Revision C

Serial Number Code

Pin 1 Identifier

NN

19.2 STQFN 12L 1.6 MM X 1.6 MM 0.4P FC, AFTER FEBRUARY 1, 2021

Part Code

PPP

WWR

Date Code + Revision C

Serial Number Code

Pin 1 Identifier

NN

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20 Package Information

20.1 PACKAGE OUTLINES FOR STQFN 12L 1.6 MM X 1.6 MM X 0.55 MM 0.4P FC PACKAGE

JEDEC MO-220

Bottom View

Top View

Side View

Controlling dimensions: mm

Notes:

1. All dimensions are in millimeters.

2. Dimension “b” applies to metalized terminal and is

measured between 0.15 mm and 0.30 mm from the

terminal tip. If the terminal has the optional radius on the

other end of the terminal, the dimension “b” should not

be measured in that radius area.

3. Bilateral coplanarity zone applies to the exposed heat

sink slug as well as the terminals.

“A1” max lead coplanarity 0.05 mm

Standard tolerance: ±0.05

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20.2 MOISTURE SENSITIVITY LEVEL

The Moisture Sensitivity Level (MSL) is an indicator for the maximum allowable time period (floor lifetime) in which a moisture

sensitive plastic device, once removed from the dry bag, can be exposed to an environment with a specified maximum

temperature and a maximum relative humidity before the solder reflow process. The MSL classification is defined in Table 43.

For detailed information on MSL levels refer to the IPC/JEDEC standard J-STD-020, which can be downloaded from:

http://www.jedec.org.

The <PACKAGE_NAME> package is qualified for MSL <n>.

Table 43: MSL Classification

MSL Level

Floor Lifetime

72 hours

168 hours

4 weeks

Conditions

MSL 4

MSL 3

MSL 2A

MSL 2

MSL 1

30 °C / 60 % RH

30 °C / 85 % RH

1 year

Unlimited

20.3 SOLDERING INFORMATION

Refer to the IPC/JEDEC standard J-STD-020 for relevant soldering information. This document can be downloaded from http://

www.jedec.org.

21 Ordering Information

Part Number

SLG46811V

Type

12-pin STQFN

SLG46811VTR

12-pin STQFN - Tape and Reel (3k units)

21.1 TAPE AND REEL SPECIFICATIONS

Max Units

Leader (min)

Length

Trailer (min)

Nominal

# of

Pins

Reel &

Hub Size

(mm)

Tape Part

Width Pitch

(mm) (mm)

Package Type

Package Size

(mm)

Length

(mm)

per Reel per Box

Pockets

(mm)

STQFN 12L

1.6 mm x 1.6mm x

0.55 mm

12

1.6x1.6x0.55

3000

178/60

100

400

100

400

8

4

0.4P FC Green

21.2 CARRIER TAPE DRAWING AND DIMENSIONS

Index Hole Index Hole

PocketBTMPocketBTM Pocket Index Hole Pocket Index Hole

to Tape

Edge

to Pocket Tape Width

Center

(mm)

Length

(mm)

Width

(mm)

Depth

(mm)

Pitch

(mm)

Pitch Diameter

(mm)

Package Type

(mm)

A0

B0

K0

P0

P1

D0

E

F

W

STQFN 12L

1.6 mm x 1.6mm x

0.55 mm

1.9

2.3

0.76

4

1.5

1.75

3.5

8

0.4P FC Green

Datasheet

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Index hole to

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GreenPAK Programmable Mixed-Signal Matrix

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22 Layout Guidelines

22.1 STQFN 12L 1.6 MM X 1.6 MM X 0.55 MM 0.4P FC PACKAGE

Datasheet

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Glossary

A

ACK

Acknowledge bit

ACMP

Analog Comparator

B

BG

Bandgap

C

CLK

CMO

Clock

Connection matrix output

D

DFF

DLY

D Flip-Flop

Delay

E

EPG

ESD

EV

Extended Pattern Generator

Electrostatic discharge

End Value

F

FSM

Finite State Machine

G

GPI

GPIO

GPO

General Purpose Input

General Purpose Input/Output

General Purpose Output

I

IN

IO

Input

Input/Output

L

LPF

LSB

LUT

LV

Low Pass Filter

Least Significant Bit

Look Up Table

Low Voltage

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M

MS ACMP

MSB

Multichannel Sampling Analog Comparator

Most Significant Bit

MUX

Multiplexer

N

NPR

nRST

NVM

Non-Volatile Memory Read/Write/Erase Protection

Reset

Non-Volatile Memory

O

OD

Open-Drain

OE

Output Enable

Oscillator

OSC

OTP

OUT

One Time Programmable

Output

P

PD

Power-down

PGen

POR

PP

Pattern Generator

Power-On Reset

Push-Pull

PWR

P DLY

Power

Programmable Delay

R

R/W

Read/Write

S

SCL

SDA

SLA

SMT

SV

I²C Clock Input

I²C Data Input/Output

Slave Address

With Schmitt Trigger

nSET Value

T

TS

Temperature Sensor

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V

Vref

Voltage Reference

W

WOSMT

Without Schmitt Trigger

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Revision History

Revision

Date

Description

3.0

14-Apr-2021

Final version

Datasheet

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Status Definitions

Revision Datasheet Status

Product Status

Definition

1.<n>

Target

Development

This datasheet contains the design specifications for product development.

Specifications may change in any manner without notice.

2.<n>

Preliminary

Qualification

Production

This datasheet contains the specifications and preliminary characterization

data for products in pre-production. Specifications may be changed at any

time without notice in order to improve the design.

3.<n>

4.<n>

Final

This datasheet contains the final specifications for products in volume

production. The specifications may be changed at any time in order to

improve the design, manufacturing and supply. Major specification

changes are communicated via Customer Product Notifications. Datasheet

changes are communicated via www.dialog-semiconductor.com.

Obsolete

Archived

This datasheet contains the specifications for discontinued products. The

information is provided for reference only.

Disclaimer

Unless otherwise agreed in writing, the Dialog Semiconductor products (and any associated software) referred to in this document are not designed, authorized or warranted

to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of a Dialog Semiconductor product (or

associated software) can reasonably be expected to result in personal injury, death or severe property or environmental damage. Dialog Semiconductor and its suppliers

accept no liability for inclusion and/or use of Dialog Semiconductor products (and any associated software) in such equipment or applications and therefore such inclusion

and/or use is at the customer's own risk.

Information in this document is believed to be accurate and reliable. However, Dialog Semiconductor does not give any representations or warranties, express or implied, as

to the accuracy or completeness of such information. Dialog Semiconductor furthermore takes no responsibility whatsoever for the content in this document if provided by any

information source outside of Dialog Semiconductor.

Dialog Semiconductor reserves the right to change without notice the information published in this document, including, without limitation, the specification and the design of

the related semiconductor products, software and applications. Notwithstanding the foregoing, for any automotive grade version of the device, Dialog Semiconductor

reserves the right to change the information published in this document, including, without limitation, the specification and the design of the related semiconductor products,

software and applications, in accordance with its standard automotive change notification process.

Applications, software, and semiconductor products described in this document are for illustrative purposes only. Dialog Semiconductor makes no representation or warranty

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such testing or modification is the sole responsibility of the customer and Dialog Semiconductor excludes all liability in this respect.

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Datasheet

14-Apr-2021

Revision 3.0

171 of 171

CFR0011-120-00


型号：	SLG46811V
厂家：	Dialog Semiconductor
描述：	GreenPAK Programmable Mixed-Signal Matrix
文件：	总171页 (文件大小：2916K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SLG46811V [DIALOG]

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