SLG46827-AG_技术文档

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

General Description

The SLG46827-A provides a small, low power component for commonly used Mixed-Signal functions. The user creates the

circuit design by programming the multiple time Non-Volatile Memory (NVM) to configure the interconnect logic, the IOs, and

the macrocells of the SLG46827-A. Dual power supply allows to flexibly interface two independent voltage domains.This

highly versatile device allows a wide variety of Mixed-Signal functions to be designed within a very small, low power single

integrated circuit.



In-System Debug

Multiple Time Programmable Memory in Development

Wide Range Power Supply

Key Features



Two High Speed General Purpose Rail-to-Rail Analog

Comparators (ACMPxH)

Two Low Power General Purpose Rail-to-Rail Analog

Comparators (ACMPxL)



2.5 V (±8 %) to 5 V (±10 %) V_DD



1.8 V (±5 %) to 5 V (±10 %) V_DD2(V_DD2≤ V_DD)



Operating Temperature Range: -40 °C to +105 °C

RoHS Compliant/Halogen-Free

Packages Available

Two Voltage References



Two Vref Outputs

Eleven Combination Function Macrocells



20-pin TSSOP: 6.5 mm x 6.4 mm x 1.2 mm, 0.65 mm

pitch



Three Selectable DFF/LATCH or 2-bit LUTs

One Selectable Programmable Pattern Generator or

2-bit LUT



AEC-Q100 Grade 2 Qualified



Six Selectable DFF/LATCH or 3-bit LUTs

One Selectable Pipe Delay or Ripple Counter, or

3-bit LUT



Eight Multi-Function Macrocells



Seven Selectable DFF/LATCH or 3-bit LUTs + 8-bit

Delay/Counters



One Selectable DFF/LATCH or 4-bit LUT + 16-bit

Delay/Counter

Serial Communications



I²C Protocol Interface



Programmable Delay with Edge Detector Output

Deglitch Filter or Edge Detector

Three Oscillators



2.048 kHz Oscillator

2.048 MHz Oscillator

25 MHz Oscillator



Analog Temperature Sensor

Power-On Reset

Applications



Car Navigation and Telematics

In-Car Infotainment/Dashboard

Automotive Display Clusters

Advanced Driver Assistance Systems (ADAS)

Datasheet

24-Feb-2021

Revision 3.2

1 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Contents

General Description.................................................................................................................................................................1

Key Features.............................................................................................................................................................................1

Applications .............................................................................................................................................................................1

1 Block Diagram ......................................................................................................................................................................7

2 Pinout ....................................................................................................................................................................................8

2.1 Pin Configuration - TSSOP-20L .............................................................................................................................8

3 Characteristics ...................................................................................................................................................................12

3.1 Absolute Maximum Ratings .................................................................................................................................12

3.2 Electrostatic Discharge Ratings ...........................................................................................................................12

3.3 Recommended Operating Conditions ..................................................................................................................12

3.4 Electrical Characteristics ......................................................................................................................................13

3.5 Timing Characteristics .........................................................................................................................................21

3.6 OSC Characteristics .............................................................................................................................................26

3.7 ACMP Specifications ............................................................................................................................................26

3.8 Analog Temperature Sensor Characteristics .......................................................................................................30

4 In-System Debug ................................................................................................................................................................32

5 IO Pins .................................................................................................................................................................................33

5.1 IO Pins .................................................................................................................................................................33

5.2 GPIO Pins ............................................................................................................................................................33

5.3 GPO Pins .............................................................................................................................................................33

5.4 GPI Pins ...............................................................................................................................................................33

5.5 Pull-Up/Down Resistors .......................................................................................................................................33

5.6 Fast Pull-up/down during Power-up .....................................................................................................................33

5.7 I2C Mode IO Structure (VDD or VDD2) ...............................................................................................................34

5.8 Matrix OE IO Structure (VDD or VDD2) ...............................................................................................................35

5.9 Register OE IO Structure (VDD or VDD2) ...........................................................................................................36

5.10 Register OE IO Structure (VDD or VDD2) .........................................................................................................37

5.11 IO Typical Performance ....................................................................................................................................38

6 Connection Matrix ..............................................................................................................................................................40

6.1 Matrix Input Table ................................................................................................................................................41

6.2 Matrix Output Table .............................................................................................................................................42

6.3 Connection Matrix Virtual Inputs ..........................................................................................................................45

6.4 Connection Matrix Virtual Outputs .......................................................................................................................46

7 Combination Function Macrocells ....................................................................................................................................47

7.1 2-Bit LUT or D Flip-Flop Macrocells .....................................................................................................................47

7.2 2-bit LUT or Programmable Pattern Generator ....................................................................................................50

7.3 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells .............................................................................................52

7.4 3-Bit LUT or Pipe Delay/Ripple Counter Macrocell ..............................................................................................59

8 Multi-Function Macrocells .................................................................................................................................................64

8.1 3-Bit LUT or DFF/LATCH with 8-Bit Counter/Delay Macrocells ...........................................................................64

8.2 CNT/DLY/FSM Timing Diagrams .........................................................................................................................73

8.3 4-Bit LUT or DFF/LATCH with 16-Bit Counter/Delay Macrocell ...........................................................................82

8.4 Wake and Sleep Controller ..................................................................................................................................85

9 Analog Comparators ..........................................................................................................................................................89

9.1 ACMP0H Block Diagram .....................................................................................................................................90

9.2 ACMP1H Block Diagram .....................................................................................................................................91

9.3 ACMP2L Block Diagram .....................................................................................................................................92

9.4 ACMP3L Block Diagram .....................................................................................................................................93

9.5 ACMP Typical Performance .................................................................................................................................94

10 Programmable Delay/Edge Detector ..............................................................................................................................98

10.1 Programmable Delay Timing Diagram - Edge Detector Output .........................................................................98

11 Additional Logic Function. Deglitch Filter .....................................................................................................................99

12 Voltage Reference ..........................................................................................................................................................100

12.1 Voltage Reference Overview ...........................................................................................................................100

12.2 Vref Selection Table ........................................................................................................................................100

12.3 Vref Block Diagram .........................................................................................................................................101

Datasheet

24-Feb-2021

Revision 3.2

2 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

12.4 Vref Load Regulation .......................................................................................................................................102

13 Clocking ..........................................................................................................................................................................104

13.1 Oscillator general description ...........................................................................................................................104

13.2 Oscillator0 (2.048 kHz) .....................................................................................................................................105

13.3 Oscillator1 (2.048 MHz) ...................................................................................................................................106

13.4 Oscillator2 (25 MHz) ........................................................................................................................................107

13.5 CNT/DLY Clock Scheme ..................................................................................................................................108

13.6 External Clocking .............................................................................................................................................108

13.7 Oscillators Power-On Delay .............................................................................................................................109

13.8 Oscillators Accuracy .........................................................................................................................................111

14 Power-On Reset ..............................................................................................................................................................114

14.1 General Operation ............................................................................................................................................114

14.2 POR Sequence ................................................................................................................................................115

14.3 Macrocells Output States During POR Sequence ...........................................................................................115

15 I²C Serial Communications Macrocell ..........................................................................................................................118

15.1 I²C Serial Communications Macrocell Overview ..............................................................................................118

15.2 I²C Serial Communications Device Addressing ...............................................................................................118

15.3 I²C Serial General Timing ................................................................................................................................119

15.4 I²C Serial Communications Commands ...........................................................................................................119

15.5 Chip Configuration Data Protection ..................................................................................................................122

15.6 I2C Serial Command Register Map .................................................................................................................123

15.7 I²C Additional Options ......................................................................................................................................124

16 Non-Volatile Memory ......................................................................................................................................................127

16.1 Serial NVM Write Operations ...........................................................................................................................127

16.2 Serial NVM Read Operations ...........................................................................................................................129

16.3 Serial NVM Erase Operations ..........................................................................................................................129

17 Analog Temperature Sensor .........................................................................................................................................130

18 Register Definitions .......................................................................................................................................................133

18.1 Register Map ....................................................................................................................................................133

19 Package Top Marking System Definition .....................................................................................................................172

19.1 TSSOP-20 .......................................................................................................................................................172

20 Package Information ......................................................................................................................................................173

20.1 Package outlines for TSSOP 20L 173 MIL Green Package ............................................................................173

20.2 TSSOP Handling ..............................................................................................................................................173

20.3 Soldering Information .......................................................................................................................................174

21 Ordering Information .....................................................................................................................................................174

21.1 Tape and Reel Specifications ..........................................................................................................................174

21.2 Carrier Tape Drawing and Dimensions ............................................................................................................174

21.3 TSSOP-20L ......................................................................................................................................................174

22 Layout Guidelines ..........................................................................................................................................................175

22.1 TSSOP-20 ........................................................................................................................................................175

Glossary................................................................................................................................................................................176

Revision History...................................................................................................................................................................179

Datasheet

24-Feb-2021

Revision 3.2

3 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Figures

Figure 1: Block Diagram............................................................................................................................................................ 7

Figure 2: Steps to Create a Custom GreenPAK Device.......................................................................................................... 32

Figure 3: IO with I²C Mode IO Structure Diagram................................................................................................................... 34

Figure 4: Matrix OE IO Structure Diagram.............................................................................................................................. 35

Figure 5: GPIO Register OE IO Structure Diagram................................................................................................................. 36

Figure 6: GPIO Register OE IO Structure Diagram................................................................................................................. 37

Figure 7: Typical High Level Output Current vs. High Level Output Voltage .......................................................................... 38

Figure 8: Typical Low Level Output Current vs. Low Level Output Voltage (for 1x Drive)...................................................... 38

Figure 9: Typical Low Level Output Current vs. Low Level Output Voltage (for 2x Drive)...................................................... 39

Figure 10: Connection Matrix.................................................................................................................................................. 40

Figure 11: Connection Matrix Example................................................................................................................................... 40

Figure 12: 2-bit LUT0 or DFF0................................................................................................................................................ 47

Figure 13: 2-bit LUT1 or DFF1................................................................................................................................................ 48

Figure 14: 2-bit LUT2 or DFF2................................................................................................................................................ 48

Figure 15: DFF Polarity Operations......................................................................................................................................... 50

Figure 16: 2-bit LUT3 or PGen................................................................................................................................................ 51

Figure 17: PGen Timing Diagram............................................................................................................................................ 51

Figure 18: 3-bit LUT0 or DFF3................................................................................................................................................ 53

Figure 19: 3-bit LUT1 or DFF4................................................................................................................................................ 53

Figure 20: 3-bit LUT2 or DFF5................................................................................................................................................ 54

Figure 21: 3-bit LUT3 or DFF6................................................................................................................................................ 54

Figure 22: 3-bit LUT4 or DFF7................................................................................................................................................ 55

Figure 23: 3-bit LUT5 or DFF8................................................................................................................................................ 55

Figure 24: DFF Polarity Operations with nReset..................................................................................................................... 58

Figure 25: DFF Polarity Operations with nSet......................................................................................................................... 59

Figure 26: 3-bit LUT6/Pipe Delay/Ripple Counter................................................................................................................... 61

Figure 27: Example: Ripple Counter Functionality.................................................................................................................. 62

Figure 28: Possible Connections Inside Multi-Function Macrocell.......................................................................................... 64

Figure 29: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT7/DFF10, CNT/DLY1) .................................................. 65

Figure 30: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT8/DFF11, CNT/DLY2) .................................................. 66

Figure 31: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT9/DFF12, CNT/DLY3) .................................................. 67

Figure 32: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT10/DFF13, CNT/DLY4) ................................................ 68

Figure 33: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT11/DFF14, CNT/DLY5) ................................................ 69

Figure 34: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT12/DFF15, CNT/DLY6) ................................................ 70

Figure 35: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT13/DFF16, CNT/DLY7) ................................................ 71

Figure 36: Delay Mode Timing Diagram, Edge Select: Both, Counter Data: 3 ....................................................................... 73

Figure 37: Delay Mode Timing Diagram for Different Edge Select Modes.............................................................................. 74

Figure 38: Counter Mode Timing Diagram without Two DFFs Synced Up ............................................................................. 74

Figure 39: Counter Mode Timing Diagram with Two DFFs Synced Up .................................................................................. 75

Figure 40: One-Shot Function Timing Diagram....................................................................................................................... 76

Figure 41: Frequency Detection Mode Timing Diagram.......................................................................................................... 77

Figure 42: Edge Detection Mode Timing Diagram.................................................................................................................. 78

Figure 43: Delayed Edge Detection Mode Timing Diagram.................................................................................................... 79

Figure 44: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP = 0) for Counter Data = 3.... 80

Figure 45: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced On, UP = 0) for Counter Data = 3 ........ 80

Figure 46: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP = 1) for Counter Data = 3.... 81

Figure 47: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced On, UP = 1) for Counter Data = 3 ........ 81

Figure 48: Counter Value, Counter Data = 3........................................................................................................................... 82

Figure 49: 4-bit LUT0 or CNT/DLY0........................................................................................................................................ 83

Figure 50: Wake and Sleep Controller.................................................................................................................................... 85

Figure 51: Wake and Sleep Timing Diagram, Normal Wake Mode, Counter Reset is Used .................................................. 86

Figure 52: Wake and Sleep Timing Diagram, Short Wake Mode, Counter Reset is Used ..................................................... 86

Figure 53: Wake and Sleep Timing Diagram, Normal Wake Mode, Counter Set is Used ...................................................... 87

Figure 54: Wake and Sleep Timing Diagram, Short Wake Mode, Counter Set is Used ......................................................... 87

Figure 55: ACMP0H Block Diagram........................................................................................................................................ 90

Figure 56: ACMP1H Block Diagram........................................................................................................................................ 91

Datasheet

24-Feb-2021

Revision 3.2

4 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Figure 57: ACMP2L Block Diagram ........................................................................................................................................ 92

Figure 58: ACMP3L Block Diagram ........................................................................................................................................ 93

Figure 59: Typical Propagation Delay vs. Vref for ACMPxH at T = 25 °C, Gain = 1, Buffer - Disabled, Hysteresis = 0 ......... 94

Figure 60: Typical Propagation Delay vs. Vref for ACMPxL at T = 25 °C, Gain = 1, Buffer - Disabled, Hysteresis = 0.......... 94

Figure 61: ACMPxH Power-On Delay vs. V_{DD ....................................................................................................................................................... 95}

Figure 62: ACMPxL Power-On Delay vs. V_{DD........................................................................................................................................................ 95}

Figure 63: ACMPxH Input Offset Voltage vs. Vref at T = -40 °C to 105 °C, Input Buffer Disabled......................................... 96

Figure 64: ACMPxH Input Offset Voltage vs. Vref at T = -40 °C to 105 °C, Input Buffer Enabled.......................................... 96

Figure 65: ACMPxL Input Offset Voltage vs. Vref at T = -40 °C to 105°C .............................................................................. 97

Figure 66: ACMP Input Current Source vs. Input Voltage at T = -40 °C to 105 °C, V_DD= 3.3 V ............................................ 97

Figure 67: Programmable Delay ............................................................................................................................................. 98

Figure 68: Edge Detector Output ............................................................................................................................................ 98

Figure 69: Deglitch Filter or Edge Detector............................................................................................................................. 99

Figure 70: Voltage Reference Block Diagram....................................................................................................................... 101

Figure 71: Typical Load Regulation, Vref = 320 mV, T = -40 °C to +105 °C, Buffer - Enable............................................... 102

Figure 72: Typical Load Regulation, Vref = 640 mV, T = -40 °C to +105 °C, Buffer - Enable............................................... 102

Figure 73: Typical Load Regulation, Vref = 1280 mV, T = -40 °C to +105 °C, Buffer - Enable............................................. 103

Figure 74: Typical Load Regulation, Vref = 2016 mV, T = -40 °C to +105 °C, Buffer - Enable............................................. 103

Figure 75: Oscillator0 Block Diagram.................................................................................................................................... 105

Figure 76: Oscillator1 Block Diagram.................................................................................................................................... 106

Figure 77: Oscillator2 Block Diagram.................................................................................................................................... 107

Figure 78: Clock Scheme...................................................................................................................................................... 108

Figure 79: Oscillator Startup Diagram................................................................................................................................... 109

Figure 80: Oscillator0 Maximum Power-On Delay vs. V_DDat T = 25 °C, OSC0 = 2.048 kHz............................................... 109

Figure 81: Oscillator1 Maximum Power-On Delay vs. V_DDat T = 25 °C, OSC1 = 2.048 MHz ............................................. 110

Figure 82: Oscillator2 Maximum Power-On Delay vs. V_DDat T = 25 °C, OSC2 = 25 MHz .................................................. 110

Figure 83: Oscillator0 Frequency vs. Temperature, OSC0 = 2.048 kHz............................................................................... 111

Figure 84: Oscillator1 Frequency vs. Temperature, OSC1 = 2.048 MHz.............................................................................. 112

Figure 85: Oscillator2 Frequency vs. Temperature, OSC2 = 25 MHz................................................................................... 112

Figure 86: Oscillators Total Error vs. Temperature............................................................................................................... 113

Figure 87: POR Sequence.................................................................................................................................................... 115

Figure 88: Internal Macrocell States during POR Sequence................................................................................................. 116

Figure 89: Power-Down......................................................................................................................................................... 117

Figure 90: Basic Command Structure................................................................................................................................... 118

Figure 91: I²C General Timing Characteristics...................................................................................................................... 119

Figure 92: Byte Write Command, R/W = 0............................................................................................................................ 119

Figure 93: Sequential Write Command................................................................................................................................. 120

Figure 94: Current Address Read Command, R/W = 1......................................................................................................... 120

Figure 95: Random Read Command .................................................................................................................................... 121

Figure 96: Sequential Read Command................................................................................................................................. 121

Figure 97: Reset Command Timing ...................................................................................................................................... 122

Figure 98: Example of I²C Byte Write Bit Masking................................................................................................................ 126

Figure 99: Page Write Command.......................................................................................................................................... 127

Figure 100: I²C Block Addressing ......................................................................................................................................... 128

Figure 101: Analog Temperature Sensor Structure Diagram................................................................................................ 131

Figure 102: Typical TS Output vs Temperature, V_DD= 2.3 V to 5.5 V.................................................................................. 132

Datasheet

24-Feb-2021

Revision 3.2

5 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Tables

Table 1: Functional Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 2: Pin Type Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 3: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 4: Electrostatic Discharge Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 5: Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 6: EС at T = -40 °C to +105 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted . . . . . . . . . . . . . . . . . . . . 13

Table 7: Input Leakage Current at T = -40 °C to +105 °C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 8: EC of the SDA and SCL IO Stages at T = -40 °C to +105 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted . . . 18

Table 9: I²C Bus Timing Characteristics at T = -40 °C to +105 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted . . . . . 19

Table 10: Typical Current Consumption Estimated for Each Macrocell at T = -40 °C to +105 °C . . . . . . . . . . . . . . 19

Table 11: Typical Delay Estimated for Each Macrocell at T = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 12: Programmable Delay Expected Delays and Widths (Typical) at T = 25 °C . . . . . . . . . . . . . . . . . . . . 24

Table 13: Typical Filter Rejection Pulse Width at T = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 14: Typical Counter/Delay Offset Measurements at T = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 15: Oscillators Frequency Limits, V_DD= 2.3 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 16: Oscillators Power-On Delay at T = 25 °C, OSC Power Mode: "Auto Power-On". . . . . . . . . . . . . . . . . . 26

Table 17: ACMP Specifications at T = -40 °C to +105 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted . . . . . . . . . . 26

Table 18: TS Output vs Temperature (Output Range 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 19: TS Output vs Temperature (Output Range 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 20: TS Output Error (Output Range 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 21: TS Output Error (Output Range 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 22: Matrix Input Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 23: Matrix Output Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 24: Connection Matrix Virtual Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 25: 2-bit LUT0 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 26: 2-bit LUT1 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 27: 2-bit LUT2 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 28: 2-bit LUT Standard Digital Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 29: 2-bit LUT1 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 30: 2-bit LUT Standard Digital Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 31: 3-bit LUT0 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 32: 3-bit LUT1 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 33: 3-bit LUT2 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 34: 3-bit LUT3 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 35: 3-bit LUT4 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 36: 3-bit LUT5 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 37: 3-bit LUT Standard Digital Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 38: 3-bit LUT6 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 39: 3-bit LUT7 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 40: 3-bit LUT8 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 41: 3-bit LUT9 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 42: 3-bit LUT10 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 43: 3-bit LUT11 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 44: 3-bit LUT12 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 45: 3-bit LUT13 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 46: 4-bit LUT0 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 47: 4-bit LUT Standard Digital Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 48: Vref Selection Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 49: Oscillator Operation Mode Configuration Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 50: Oscillator Output Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 51: RPR Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 52: RPR Bit Function Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 53: NPR Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Table 54: NPR Bit Function Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Table 55: Read/Write Register Protection Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Table 56: Erase Register Bit format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 57: Erase Register Bit Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 58: Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Datasheet

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SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

1

Block Diagram

IO11

ACMP3L

IO14

ACMP0H

IO13

ACMP1H

IO12

ACMP2L

IO10

Vref Out0

V_DD

Multiple Time

Programmable

Memory

I²C Serial

Communication

High Speed

Analog

In-System

Debug

Vref

Combination Function Macrocells

IO0

FILTER

with Edge

Detect

IO9

Vref Out1

ACMP0H

ACMP1H

2-bit

LUT2_0

or DFF0

LUT2_1

or DFF1

LUT2_2

or DFF2

LUT2_3

or PGEN

IO1

Temperature

Sensor

3bit

LUT3_0

or DFF3

3-bit

LUT3_1

or DFF4

3-bit

LUT3_2

or DFF5

3-bit

LUT3_3

or DFF6

V_DD2

Low Power

Analog

Low

Power

Vref

3-bit LUT3_6

or Pipe Delay

or Ripple

CNT

3-bit

LUT3_4

or DFF7

3-bit

LUT3_5

or DFF8

Programmable

Delay or Edge

Detect

IO2

IO8

ACMP2L

ACMP3L

Multi-Function Macrocells

3-bitLUT3_10

/DFF13+8bit

CNT/DLY4

3-bitLUT3_7

/DFF10+8bit

CNT/DLY1

3-bitLUT3_8

/DFF11+8bit

CNT/DLY2

3-bitLUT3_9

/DFF12+8bit

CNT/DLY3

IO3

IO7

Oscillators

POR

2.048

kHz

2.048

MHz

25

MHz

3-bit

4-bitLUT4_0

/DFF9+

3-bit

LUT3_11

LUT3_12

LUT3_13

/DFF14+8bit

CNT/DLY5

16bit

/DFF15+8bit

CNT/DLY6

/DFF16+8bit

CNT/DLY7

CNT/DLY0

IO4

GND

SDA

IO6

IO5

SCL

Figure 1: Block Diagram

Datasheet

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SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

2

Pinout

2.1 PIN CONFIGURATION - TSSOP-20L

Pin # Pin Name Pin Functions

1

2

IO14

IO13

IO12

IO11

IO10

IO9

GPIO or ACMP0H_IN

GPIO or ACMP1H_IN

GPIO or ACMP2L_IN

GPIO or ACMP3L_IN

GPIO or Vref_OUT0

GPIO or Vref_OUT1

Power Supply

GPIO

V_DD

IO0

IO1

IO2

IO3

IO4

IO5

SCL

SDA

IO6

IO14

IO13

IO12

IO11

IO10

IO9

1

2

20

19

18

17

16

15

14

13

12

11

3

4

3

5

4

6

5

7

V_DD2

IO8

6

8

V_DD2

7

9

IO7

GPO

IO8

IO7

GND

8

10

11

12

13

14

15

16

17

18

19

20

GND

IO6

Ground

9

GPO

I²C_SDA

I²C_SCL

10

SDA

SCL

IO5

GPIO, SLA_3

GPIO, SLA_2

GPIO, SLA_1

GPIO, SLA_0

GPIO or Vref IN

GPIO

TSSOP-20

(Top View)

IO4

IO3

IO2

IO1

IO0

V_DD

Power Supply

Legend:

ACMPx+: ACMPx Positive Input

ACMPx-: ACMPx Negative Input

SCL: I²C Clock Input

SDA: I²C Data Input/Output

Vrefx: Voltage Reference Output

SLA: Slave Address

Table 1: Functional Pin Description

Name

Signal

Name

Input

Options

Output

Options

Pin #

Function

Digital Input without

Schmitt Trigger

Push-Pull (1x) (2x)

General Purpose IO

with OE (Note 1)

IO14

Digital Input

with Schmitt Trigger

Open-Drain NMOS

(1x) (2x)

1

IO14

Low Voltage Digital Input

--

Analog Comparator 0

Positive Input

ACMP0H+

Analog

--

EXT_RESET

--

Datasheet

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

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Table 1: Functional Pin Description(Continued)

Name

Signal

Name

Input

Options

Output

Options

Pin #

Function

Digital Input without

Schmitt Trigger

Push-Pull (1x) (2x)

General Purpose IO

with OE (Note 1)

IO13

ACMP1H+

IO12

Digital Input

with Schmitt Trigger

Open-Drain NMOS

(1x) (2x)

2

IO13

Low Voltage Digital Input

--

Analog Comparator 1

Positive Input

Analog

--

Digital Input without Schmitt Trigger Push-Pull (1x) (2x)

Digital Input

with Schmitt Trigger

Open-Drain NMOS

(1x) (2x)

General Purpose IO

with OE (Note 1)

3

4

IO12

IO11

Low Voltage

Digital Input

--

Analog Comparator 2

Positive Input

ACMP2L+

IO11

Analog

Digital Input without Schmitt Trigger Push-Pull (1x) (2x)

General Purpose IO

with OE (Note 1)

Digital Input

with Schmitt Trigger

Open-Drain NMOS

(1x) (2x)

Low Voltage Digital Input

--

Analog Comparator 3

Positive Input

ACMP3L+

Analog

--

Digital Input without

Schmitt Trigger

Push-Pull (1x) (2x)

General Purpose IO

with OE (Note 1)

IO10

Digital Input

with Schmitt Trigger

Open-Drain NMOS

(1x) (2x)

5

IO10

Low Voltage Digital Input

--

Analog

--

Voltage Reference 0

Output

Vref0_OUT

--

EXT_OSC1_IN

--

Digital Input without Schmitt Trigger Push-Pull (1x) (2x)

General Purpose IO

with OE (Note 1)

Digital Input

with Schmitt Trigger

Open-Drain NMOS

(1x) (2x)

IO9

6

IO9

Low Voltage Digital Input

--

Voltage Reference 1

Output

Vref1_OUT

--

Analog

I²C_EXPAND_3

V_DD2

--

7

8

V_DD2

IO8

Power Supply

Digital Input without Schmitt Trigger Push-Pull (1x) (2x)

General Purpose IO

with OE (Note 1)

Digital Input

with Schmitt Trigger

Open-Drain NMOS

(1x) (2x)

IO8

EXT_OSC2_IN

IO7

Low Voltage Digital Input

--

Push-Pull (1x) (2x)

General Purpose Out-

Open-Drain NMOS

(1x) (2x)

9

IO7

--

put

--

10

GND

Ground

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

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Table 1: Functional Pin Description(Continued)

Name

Signal

Name

Input

Options

Output

Options

Pin #

Function

General Purpose Out-

11

IO6

--

Push-Pull (1x) (2x)

put

Digital Input without

Schmitt Trigger

--

12

13

SDA

I²C Serial Data

I²C Serial Clock

Low Voltage Digital Input

--

Digital Input without

Schmitt Trigger

--

SCL

IO5

SCL

IO5

Low Voltage Digital Input

--

Digital Input without

Schmitt Trigger

Push-Pull (1x) (2x)

General Purpose IO

with OE (Note 1)

Digital Input

with Schmitt Trigger

Open-Drain NMOS

(1x) (2x)

14

EXT_SLA_3

Low Voltage Digital Input

--

I²C_EXPAND_1

IO4

--

Digital Input without

Schmitt Trigger

Push-Pull (1x) (2x)

General Purpose IO

with OE (Note 1)

15

16

17

IO4

IO3

IO2

Digital Input

with Schmitt Trigger

Open-Drain NMOS

(1x) (2x)

EXT_SLA_2

IO3

Low Voltage Digital Input

--

Digital Input without Schmitt Trigger Push-Pull (1x) (2x)

Digital Input

with Schmitt Trigger

Open-Drain NMOS

(1x) (2x)

General Purpose IO

EXT_SLA_1

IO2

Low Voltage

Digital Input

--

Digital Input without Schmitt Trigger Push-Pull (1x) (2x)

Digital Input

with Schmitt Trigger

Open-Drain NMOS

(1x) (2x)

EXT_SLA_0

Low Voltage

Digital Input

--

Digital Input without

Schmitt Trigger

Push-Pull (1x) (2x)

General Purpose IO

with OE (Note 1)

IO1

EXT_Vref

IO0

Digital Input

with Schmitt Trigger

Open-Drain NMOS

(1x) (2x)

18

IO1

Low Voltage Digital Input

--

Analog Comparator

Negative Input

Analog

--

Digital Input without Schmitt Trigger Push-Pull (1x) (2x)

Digital Input

with Schmitt Trigger

Open-Drain NMOS

(1x) (2x)

General Purpose IO

--

Low Voltage

Digital Input

19

IO0

--

I²C_EXPAND_0

EXT_OSC0_IN

--

External Clock

Connection

--

Datasheet

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Revision 3.2

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SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 1: Functional Pin Description(Continued)

Name

Signal

Name

Input

Options

Output

Options

Pin #

Function

VDD

Power Supply

--

Analog Comparator 0

Positive Input

ACMP0H+

Analog

--

Analog Comparator 1

Positive Input

ACMP1H+

ACMP2L+

ACMP3L+

Analog

--

20

V_DD

Analog Comparator 2

Positive Input

Analog Comparator 3

Positive Input

Note 1 General Purpose IO's with OE can be used to implement bidirectional signals under user control via Connection Matrix

to OE signal in IO structure.

Table 2: Pin Type Definitions

Pin Type

V_DD

Description

Power Supply

Input/Output

I²C Serial Clock

I²C Serial Data

Ground

IO

SCL

SDA

GND

V_DD2

Power Supply 2

Datasheet

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Revision 3.2

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SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

3

Characteristics

3.1 ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, so functional operation of the device at these or any other conditions beyond those indicated in the operational

sections of the specification are not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect

device reliability.

Table 3: Absolute Maximum Ratings

Parameter

Supply Voltage on V_DDrelative to GND

DC Input Voltage

Min

Max

Unit

V

-0.3

7

GND - 0.5 V V_DD+ 0.5 V

V

Maximum Average or DC Current Through V_DDPin

Maximum Average or DC Current Through V_DD2Pin

Maximum Average or DC Current Through GND Pin (Per chip side, (Note 1))

Push-Pull 1x

--

90

mA

--

100

15.3

22.1

15.5

23

--

Push-Pull 2x

OD 1x

--

Maximum Average or DC Current

(Through pin)

mA

--

OD 2x

--

Current at Input Pin

-1.0

--

1.0

mA

nA

°C

Input leakage (Absolute Value)

Storage Temperature Range

Junction Temperature

1000

150

-65

--

°C

Moisture Sensitivity Level

1

Note 1 The GreenPAK’s GND rail is divided in two sides. IOs 0 to 6, SCL, SDA are connected to one side and IOs 7 to 14 are

connected to another side.

3.2 ELECTROSTATIC DISCHARGE RATINGS

Table 4: Electrostatic Discharge Ratings

Parameter

Min

2000

1300

Max

--

Unit

V

ESD Protection (Human Body Model)

ESD Protection (Charged Device Model)

--

V

3.3 RECOMMENDED OPERATING CONDITIONS

Table 5: Recommended Operating Conditions

Parameter

Condition

Min

Max

Unit

2.3

5.5

V

Supply Voltage (V_DD

)

During NVM Write and Erase

commands

2.5

5.5

V

Supply Voltage 2 (V_DD2

Operating Temperature

)

V_DD2≤ V_DD

1.71

-40

5.5

V

105

°C

Maximal VoltageApplied to any PIN in High

Impedance State

V_DD+0.3

(Note 1)

--

0.1

0

V

µF

V

Capacitor Value at V_DD

--

Allowable Input Voltage at Analog

Pins

V_DDor V_DD2

(Note 2)

Analog Input Common Mode Range

Note 1 IOs 0 to 6, SCL, SDA are powered from V_DDand IOs 7 to 14 are powered from V_DD2.

Note 2 V_DDfor IO1 and V_DD2for IO11 to IO14

Datasheet

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Revision 3.2

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SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

3.4 ELECTRICAL CHARACTERISTICS

Table 6: EС at T = -40 °C to +105 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted

Parameter Description

Condition

Min

Typ

Max

Unit

0.7x

V_DD

(Note 1)

V_DD+

0.3

(Note 1)

Logic Input

--

V

0.8x

V_DD

(Note 1)

V_DD+

0.3

(Note 1)

HIGH-Level Input Voltage

(Note 2)

V_IH

Logic Input with Schmitt Trigger

Low-Level Logic Input

Logic Input

--

V

V_DD+

1.25

0.3

(Note 1)

0.3x

V_DD

(Note 1)

GND-

0.3

LOW-Level Input Voltage

(Note 2)

0.2x

V_DD

(Note 1)

GND-

0.3

V_IL

Logic Input with Schmitt Trigger

Low-Level Logic Input

--

V

GND-

0.3

0.5

V_DD2= 1.8 V ± 5 %

V_DD= 2.3 V

0.195

0.199

0.232

0.283

0.370

0.38

0.559

0.634

0.604

0.641

0.785

V

0.391

0.422

0.440

0.577

Schmitt Trigger Hysteresis

Voltage (Note 1)

V_HYS

V_DD= 3.3 V

V_DD= 4.0 V

V_DD= 5.5 V

V

Maximal Voltage Applied to

any PIN in High Impedance

State

V_DD+

V_O

--

0.3

(Note 1)

Push-Pull, 1x Drive, I_OH= 1 mA,

V_DD= V_DD2= 2.3 V

2.167

3.022

3.769

3.600

5.192

2.234

3.161

3.883

3.800

5.340

--

2.207

3.100

3.831

3.709

5.268

2.254

3.200

3.915

3.854

5.382

0.069

0.154

--

V

Push-Pull, 1x Drive, I_OH= 3 mA,

V_DD= V_DD2= 3.3 V

--

Push-Pull, 1x Drive, I_OH= 3 mA,

V_DD= V_DD2= 4.0 V

--

Push-Pull, 1x Drive, I_OH= 5 mA,

V_DD= V_DD2= 4.0 V

--

Push-Pull, 1x Drive, I_OH= 5 mA,

V_DD= V_DD2= 5.5 V

HIGH-Level Output Voltage

(Note 1)

V_OH

Push-Pull, 2x Drive, I_OH= 1 mA,

V_DD= V_DD2= 2.3 V

--

Push-Pull, 2x Drive, I_OH= 3 mA,

V_DD= V_DD2= 3.3 V

--

Push-Pull, 2x Drive, I_OH= 3 mA,

V_DD= V_DD2= 4.0 V

--

Push-Pull, 2x Drive, I_OH= 5 mA,

V_DD= V_DD2= 4.0 V

--

Push-Pull, 2x Drive, I_OH= 5 mA,

V_DD= V_DD2= 5.5 V

--

Push-Pull, 1x Drive, I_OL= 1 mA,

V_DD= V_DD2= 2.3 V

0.100

0.222

LOW-Level Output Voltage

(Note 1)

V_OL

Push-Pull, 1x Drive, I_OL= 3 mA,

V_DD= V_DD2= 3.3 V

--

Datasheet

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Revision 3.2

13 of 180

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SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 6: EС at T = -40 °C to +105 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted(Continued)

Parameter Description

Condition

Min

Typ

Max

Unit

Push-Pull, 1x Drive, I_OL= 3mA,

V_DD= V_DD2= 4.0 V v

--

0.133

0.192

V

Push-Pull, 1x Drive, I_OL= 5 mA,

V_DD= V_DD2= 4.0 V

--

0.226

0.188

0.036

0.079

0.069

0.116

0.099

0.029

0.064

0.056

0.094

0.080

0.015

0.035

0.031

0.052

0.045

0.327

0.268

0.051

0.113

0.099

0.167

0.140

0.041

0.091

0.080

0.135

0.113

0.021

0.050

0.044

0.074

0.064

V

Push-Pull, 1x Drive, I_OL= 5 mA,

V_DD= V_DD2= 5.5 V

Push-Pull, 2x Drive, I_OL= 1 mA,

V_DD= V_DD2= 2.3 V

Push-Pull, 2x Drive, I_OL= 3 mA,

V_DD= V_DD2= 3.3 V

Push-Pull, 2x Drive, I_OL= 3mA,

V_DD= V_DD2= 4.0 V

Push-Pull, 2x Drive, I_OL= 5 mA,

V_DD= V_DD2= 4.0 V

Push-Pull, 2x Drive, I_OL= 5 mA,

V_DD= V_DD2= 5.5 V

NMOS OD, 1x Drive, I_OL= 1 mA,

V_DD= V_DD2= 2.3 V

LOW-Level Output Voltage

(Note 1)

V_OL

NMOS OD, 1x Drive, I_OL= 3 mA,

V_DD= V_DD2= 3.3 V

NMOS OD, 1x Drive, I_OL= 3 mA,

V_DD= V_DD2= 4.0 V

NMOS OD, 1x Drive, I_OL= 5 mA,

V_DD= V_DD2= 4.0 V

NMOS OD, 1x Drive, I_OL= 5 mA,

V_DD= V_DD2= 5.5 V

NMOS OD, 2x Drive, I_OL= 1 mA,

V_DD2= V_DD2= 2.3 V

NMOS OD, 2x Drive, I_OL= 3 mA,

V_DD= V_DD2= 3.3 V

NMOS OD, 2x Drive, I_OL= 3 mA,

V_DD= V_DD2= 4.0 V

NMOS OD, 2x Drive, I_OL= 5 mA,

V_DD= V_DD2= 4.0 V

NMOS OD, 2x Drive, I_OL= 5 mA,

V_DD= V_DD2= 5.5 V

Push-Pull, 1x Drive,

V_OH= V_DD- 0.2 = V_DD2- 0.2

V_DD= V_DD2= 2.3 V

Over lifetime at 105 °C (Note 3)

1.461

7.920

2.040

--

mA

Push-Pull, 1x Drive,

V_OH= 2.4 V, V_DD= V_DD2= 3.3 V

10.682

--

mA

HIGH-Level Output Current

(Note 1) (Note 4)

Push-Pull, 1x Drive,

V_OH= 2.4 V, V_DD= V_DD2= 4.0 V

I_OH

14.321 18.775

27.466 34.554

Push-Pull, 1x Drive,

V_OH= 2.4 V, V_DD= V_DD2= 5.5 V

Push-Pull, 2x Drive,

V_OH= V_DD- 0.2 = V_DD2- 0.2

V_DD= V_DD2= 2.3 V

2.678

3.987

--

mA

Over lifetime at 105 °C (Note 3)

Datasheet

24-Feb-2021

Revision 3.2

14 of 180

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SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 6: EС at T = -40 °C to +105 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted(Continued)

Parameter Description

Condition

Min

Typ

Max

Unit

Push-Pull, 2x Drive,

V_OH= 2.4 V, V_DD= V_DD2= 3.3 V

15.288 20.800

27.581 36.524

52.371 66.673

--

mA

HIGH-Level Output Current

(Note 1) (Note 4)

Push-Pull, 2x Drive,

V_OH= 2.4 V, V_DD= V_DD2= 4.0 V

I_OH

--

mA

Push-Pull, 2x Drive,

V_OH= 2.4 V, V_DD= V_DD2= 5.5 V

Push-Pull, 1x Drive, V_OL= 0.15 V,

V_DD= V_DD2= 2.3 V

1.413

2.099

--

mA

Over lifetime at 105 °C (Note 3)

Push-Pull, 1x Drive, V_OL= 0.4 V,

V_DD= V_DD2= 3.3 V

5.159

5.989

7.287

7.301

8.514

--

mA

Push-Pull, 1x Drive, V_OL= 0.4 V,

V

_DD= V_DD2= 4.0 V

Push-Pull, 1x Drive, V_OL= 0.4 V,

_DD= V_DD2= 5.5 V

Push-Pull, 2x Drive, V_OL= 0.15 V,

_DD= V_DD2= 2.3 V

10.289

V

2.713

4.065

--

mA

Over lifetime at 105 °C (Note 3)

Push-Pull, 2x Drive, V_OL= 0.4 V,

V_DD= V_DD2= 3.3

9.964

14.054

16.293

--

mA

Push-Pull, 2x Drive, V_OL= 0.4 V,

V_DD= V_DD2= 4.0

11.488

Push-Pull, 2x Drive, V_OL= 0.4 V,

V_DD= V_DD2= 5.5

13.871 19.524

LOW-Level Output Current

(Note 1) (Note 4)

I_OL

NMOS OD, 1x Drive, V_OL= 0.15 V,

V_DD= V_DD2= 2.3 V

3.329

16.164

--

mA

Over lifetime at 105 °C (Note 3)

NMOS OD, 1x Drive, V_OL= 0.4 V,

V_DD= V_DD2= 3.3 V

12.336 17.366

14.199 20.093

17.070 23.978

--

mA

NMOS OD, 1x Drive, V_OL= 0.4 V,

V_DD= V_DD2= 4.0 V

NMOS OD, 1x Drive, V_OL= 0.4 V,

V_DD= V_DD2= 5.5 V

NMOS OD, 2x Drive, V_OL= 0.15 V,

V_DD= V_DD2= 2.3 V

6.483

9.464

--

mA

Over lifetime at 105 °C (Note 3)

NMOS OD, 2x Drive, V_OL= 0.4 V,

V_DD= V_DD2= 3.3 V

22.766 32.108

25.870 36.604

--

mA

ms

NMOS OD, 2x Drive, V_OL= 0.4 V,

V_DD= V_DD2= 4.0 V

NMOS OD, 2x Drive, V_OL= 0.4 V,

V_DD= V_DD2= 5.5 V

30.115

--

42.783

2.082

--

From V_DDrising past PON_THR

T_ramp= 10ms

T_SU

Startup Time

2.745

T_WR

T_ER

NVM Page Write Time

NVM Page Erase Time

Power-On Threshold

V_DD= 2.5 V to 5.5 V

--

20

ms

V

PON_THR

V_DDLevel Required to Start Up the Chip 1.521

1.843

2.117

V_DDLevel Required to Switch Off the

Chip

POFF_THRPower-Off Threshold

0.839

1.242

1.593

V

Datasheet

24-Feb-2021

Revision 3.2

15 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 6: EС at T = -40 °C to +105 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted(Continued)

Parameter Description

Condition

Min

Typ

Max

Unit

1 M for Pull-up: V_IN= GND;

for Pull-down: V_IN= V_DD

0.860

1.091

1.432

MΩ

Over lifetime at 105 °C (Note 3)

100 k for Pull-up: V_IN= GND;

for Pull-down: V_IN= V_DD

Over lifetime at 105 °C (Note 3)

R_PULL

Pull-up Resistance (Note 1)

90.517 107.62

133.83

13.113

1.384

kΩ

MΩ

kΩ

10 k For Pull-up: V_IN= GND;

for Pull-down: V_IN= V_DD

Over lifetime at 105 °C (Note 3)

7.196

0.904

9.921

1.091

1 M for Pull-up: V_IN= GND;

for Pull-down: V_IN= V_DD

Over lifetime at 105 °C (Note 3)

100 k for Pull-up: V_IN= GND;

Pull-down Resistance (Note 1) for Pull-down: V_IN= V_DD

Over lifetime at 105 °C (Note 3)

R_PULL

85.674 107.648 137.865

10 k For Pull-up: V_IN= GND;

for Pull-down: V_IN= V_DD

Over lifetime at 105 °C (Note 3)

7.130

1.986

9.884

2.330

13.005

2.620

kΩ

CIN

Input Capacitance

pF

Note 1 The GreenPAK’s power rails are divided in two sides. IOs 0 to 6, SCL, SDA are powered from V_DD(one side) and IOs

7 to 14 are powered from V_DD2(another side).

Note 2 No hysteresis.

Note 3 Calculations based on HTOL drift data obtained through AEC-Q100 stress tests.

Note 4 DC or average current through any pin should not exceed value given in Absolute Maximum Conditions.

Datasheet

24-Feb-2021

Revision 3.2

16 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 7: Input Leakage Current at T = -40 °C to +105 °C

Parameter Description

Condition

Min

Typ

Max

Unit

V_IN= V_DD, V_DD= V_DD2,

V_DD= 2.3 V to 5.5 V

--

0.008

7.022

nA

Logic Input without Schmitt

Trigger (Floating) Leakage

(IO0-IO2, IO5, IO8, IO9-IO14)

V_IN= 0 V, V_DD= V_DD2,

V_DD= 2.3 V to 5.5 V

--

0.112

0.009

0.016

0.013

0.099

0.004

0.039

0.008

0.111

0.013

0.099

0.004

0.039

0.008

0.111

0.009

0.016

0.013

0.098

0.004

0.039

0.105

0.164

2.452

9.577

0.765

10.868

2.117

5.109

0.918

6.867

2.272

10.724

2.063

5.098

0.917

6.803

2.185

9.250

0.619

10.547

1.953

5.072

0.910

2.243

4.385

nA

V_IN= V_DD, V_DD= V_DD2,

V_DD= 2.3 V to 5.5 V

Logic Input without Schmitt

Trigger (Floating) Leakage

(SDA ans SCL Pins)

V_IN= 0 V, V_DD= V_DD2,

V_DD= 2.3 V to 5.5 V

V

_IN= V_DD, V_DD= V_DD2,

Logic Input without Schmitt

Trigger (Floating) Leakage

(IO3, IO4)

V_DD= 2.3 V to 5.5 V

V_IN= 0 V, V_DD= V_DD2,

V_DD= 2.3 V to 5.5 V

V_IN= V_DD2, V_DD2= 1.8 ± 5%,

Logic Input without Schmitt

Trigger (Floating) Leakage

(IO8, IO9-IO14)

V

_DD= 2.3 V to 5.5 V

V_IN= 0 V, V_DD2= 1.8 ± 5%_,

V_DD= 2.3 V to 5.5 V

V_IN= V_DD, V_DD= V_DD2,

V_DD= 2.3 V to 5.5 V

Logic Input with Schmitt

Trigger (Floating) Leakage

(IO0-IO2, IO5, IO8, IO9-IO14)

V_IN= 0 V, V_DD= V_DD2,

V_DD= 2.3 V to 5.5 V

V_IN= V_DD, V_DD= V_DD2,

V_DD= 2.3 V to 5.5 V

Logic Input with Schmitt

Trigger (Floating) Leakage

(IO3, IO4)

V_IN= 0 V, V_DD= V_DD2,

V_DD= 2.3 V to 5.5 V

I_LKG

(Absolute

Value)

V_IN= V_DD2, V_DD2= 1.8 ± 5%,

Logic Input with Schmitt

Trigger (Floating) Leakage

(IO8, IO9-IO14)

V

_DD= 2.3 V to 5.5 V

V_IN= 0 V, V_DD2= 1.8 ± 5%_,

V_DD= 2.3 V to 5.5 V

V_IN= V_DD, V_DD= V_DD2,

V_DD= 2.3 V to 5.5 V

Low-Level Logic Input

(Floating) Leakage

(IO0-IO2, IO5, IO8, IO9-IO14)

V_IN= 0 V, V_DD= V_DD2,

V_DD= 2.3 V to 5.5 V

V_IN= V_DD, V_DD= V_DD2,

V_DD= 2.3 V to 5.5 V

Low-Level Logic Input Trigger

(Floating) Leakage

(SDA ans SCL Pins)

V_IN= 0 V, V_DD= V_DD2,

V_DD= 2.3 V to 5.5 V

V_IN= V_DD, V_DD= V_DD2,

V_DD= 2.3 V to 5.5 V

Low-Level Logic Input Trigger

(Floating) Leakage

(IO3, IO4)

V_IN= 0 V, V_DD= V_DD2,

V_DD= 2.3 V to 5.5 V

V_IN= V_DD2, V_DD2= 1.8 ± 5%,

V_DD= 2.3 V to 5.5 V

Low-Level Logic Input Trigger

(Floating) Leakage

(IO8, IO9-IO14)

V_IN= 0 V, V_DD2= 1.8 ± 5%_,

V_DD= 2.3 V to 5.5 V

V_IN-= 0 V, V_DD= 2.3 V to 5.5 V

Ext.Vref, Gain = 1

ACMP Input Leakage

V_IN+= 0 V, V_DD= 2.3 V to 5.5 V

Ext.Vref, Gain = 1

Datasheet

24-Feb-2021

Revision 3.2

17 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 7: Input Leakage Current at T = -40 °C to +105 °C(Continued)

Parameter Description

Condition

Min

Typ

Max

Unit

V_IN-= V_DD, V_DD= 2.3 V

Ext.Vref, Gain = 1

--

0.006

5.752

nA

V_IN+= V_DD, V_DD= 2.3 V

Ext.Vref, Gain = 1

--

0.007

0.009

0.008

0.010

0.011

0.014

7.724

7.911

nA

V_IN-= V_DD, V_DD= 3.3 V

Ext.Vref, Gain = 1

V_IN+= V_DD, V_DD= 3.3 V

Ext.Vref, Gain = 1

8.392

9.441

8.875

12.928

10.705

I_LKG

(Absolute ACMP Input Leakage

Value)

V_IN-= V_DD, V_DD= 4 V

Ext.Vref, Gain = 1

V_IN+= V_DD, V_DD= 4 V

Ext.Vref, Gain = 1

V_IN-= V_DD, V_DD= 5.5 V

Ext.Vref, Gain = 1

V

_IN+= V_DD, V_DD= 5.5 V

Ext.Vref, Gain = 1

Table 8: EC of the SDA and SCL IO Stages at T = -40 °C to +105 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted

Fast-Mode

Fast-Mode Plus

Parameter Description

Condition

Unit

Min

Max

Min

Max

LOW-level Input

Voltage

V_IL

-0.5

0.3xV_DD

-0.5

0.3xV_DD

V

HIGH-level Input

Voltage

V_IH

0.7xV_DD

0.05xV_DD

5.5

--

0.7xV_DD

5.5

--

Hysteresis of Schmitt

V_HYS

0.05xV_DD

Trigger Inputs

(Open-Drain) at 3mA sink

current

LOW-Level Output

Voltage 1

V_OL1

0

0.4

0

0.4

V

_DD> 2 V

(Open-Drain) at 2 mA sink

current

V_DD≤ 2 V

LOW-Level Output

Voltage 2

V_OL2

0.2xV_DD

V_OL= 0.4 V

V_OL= 0.6 V

3

6

--

20

--

mA

LOW-Level Output

I_OL

Current (Note 2)

Output Fall Time from

V_IHminto V_ILmax

(Note 1)

14x

(V_DD/5.5 V)

10x

(V_DD/5.5 V)

t_of

250

120

ns

PIN configured as Digital

Input

0

50

2.5

+10

10

0

50

2.5

+10

10

ns

µA

pF

Input Filter Spike

Suppression (SCL,

SDA)

t_SP

PIN configured as Digital

Input LOW Voltage (Note 1)

Input Current each IO

I_i

0.1xV_DD< V_I< 0.9xV_DDmax

-10

Capacitance for each

IO Pin

C_i

--

Note 1 Does not meet standard I²C specifications: t_of(min)= 20x(V_DD/5.5 V); t_SP= 50 ns

Note 2 For Fast-mode Plus SDA pin must be configured as NMOS 2x Open-Drain, see register [769] in Section 18.

Datasheet

24-Feb-2021

Revision 3.2

18 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 9: I²C Bus Timing Characteristics at T = -40 °C to +105 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted

Fast-Mode

Plus

Parameter Description

Condition

Unit

Min

--

Max

400

--

Min

--

Max

1000

--

F_SCL

t_LOW

t_HIGH

Clock Frequency, SCL

kHz

ns

Clock Pulse Width Low

Clock Pulse Width High

1300

600

500

260

--

ns

Bus Free Time between Stop and

Start

t_BUF

1300

--

500

--

ns

t_{HD_STA}

t_{SU_STA}

t_{HD_DAT}

t_{SU_DAT}

t_R

Start Hold Time

600

0

--

260

0

--

ns

Start Set-up Time

Data Hold Time

--

Data Set-up Time

Inputs Rise Time

Inputs Fall Time

100

--

50

--

300

--

120

--

t_F

--

t_{SU_STO}

t_{VD ACK}

t_{VD DAT}

Stop Set-up Time

Data valid acknowledge time

Data valid time

600

--

260

--

900

450

--

Note 1 Timing diagram can be found in the Figure 91

Table 10: Typical Current Consumption Estimated for Each Macrocell at T = -40 °C to +105 °C

Parameter

Description Note

Chip Quiescent Current

V_DD= 2.3 V V_DD= 3.3 V V_DD= 5.0 V

Unit

0.33

0.24

0.39

0.25

0.48

0.28

µA

OSC 2.048 kHz Force PWR On

OSC 2.048 MHz Force PWR On;

Matrix PWR Down; Pre-Divider = 1;

Second Divider = 1

µA

22.16

18.37

17.72

44.88

25.29

19.51

18.52

59.09

31.10

21.57

19.93

85.34

OSC 2.048 MHz Force PWR On;

Matrix PWR Down; Pre-Divider = 4;

Second Divider = 1

I

Current

OSC 2.048 MHz Force PWR On;

Matrix PWR Down; Pre-Divider = 8;

Second Divider = 1

OSC 25 MHz Force PWR On;

Matrix PWR Down; Pre-Divider = 1;

Second Divider = 1

Datasheet

24-Feb-2021

Revision 3.2

19 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 10: Typical Current Consumption Estimated for Each Macrocell at T = -40 °C to +105 °C (Continued)

Parameter

Description Note

OSC 25 MHz Force PWR On;

V_DD= 2.3 V V_DD= 3.3 V V_DD= 5.0 V

Unit

µA

Matrix PWR Down; Pre-Divider = 4;

Second Divider = 1

30.68

28.06

38.36

34.54

53.25

47.32

OSC 25 MHz Force PWR On;

Matrix PWR Down; Pre-Divider = 8;

Second Divider = 1

µA

Temp Sensor; Output Range 2;

Source: Matrix

µA

14.01

14.14

14.06

14.19

14.37

14.50

Temp Sensor; Output Range 1;

Source: Matrix

µA

Vref0

Vref1

7.04

0.99

7.06

0.99

7.18

0.99

Vref0; Source: ACMP0H; Vref = 32 mV;

Buffer On

µA

10.60

12.03

6.35

10.71

12.25

6.42

11.60

12.94

6.76

Vref0; Source: None; Buffer On

Vref1; Source: ACMP2L; Vref = 32 mV;

Buffer On

Vref1; Source: None; Buffer On

ACMP0H; 100 uA Dis; Gain: Any;

IN PIN1; Vref = 32mV

5.97

6.03

6.36

µA

20.80

21.29

22.39

ACMP2L; Gain: Any;

IN PIN3; Vref = 32 mV

µA

1.23

34.43

1.48

1.23

35.34

1.48

1.25

37.44

1.51

I

Current

ACMP0H,1H; 100 uA Dis; Hyst Dis;

Gain x1; IN PIN1, 2; Vref = 32 mV

ACMP2L,3L; Hyst Dis; Gain x1;

IN PIN3, 4; Vref = 32 mV

ACMP0H; 100 uA Dis; Hyst Dis;

Gain x1; IN V_DD; Vref = 32 mV

34.41

24.23

46.87

35.75

1.03

35.24

24.72

48.39

36.67

1.10

37.11

25.97

51.82

38.83

1.91

ACMP0H; 100 uA Dis; Hyst Dis;

Gain x1; IN BUFF PIN1; Vref = 32 mV

ACMP0H; 100 uA EN; Hyst Dis;

Gain x1; IN PIN1; Vref = 32 mV

ACMP0H,1H,2L,3L; Hyst Dis; Gain x1;

IN PIN1, 2, 3, 4; Vref = 32 mV

ACMP0H; WS En; Force Sleep Low;

WT Short; CNT Data = 1

ACMP0H; WS En; Force Sleep Low;

WT Short; CNT Data = 10

0.39

0.42

0.59

ACMP0H; WS En; Force Sleep Low;

WT Short; CNT Data = 100

0.27

0.28

0.33

ACMP0H,1H; WS En; Force Sleep Low;

WT Short; CNT Data = 1

1.58

1.68

2.85

ACMP0H,1H; WS En; Force Sleep Low;

WT Short; CNT Data = 10

0.49

0.52

0.76

Datasheet

24-Feb-2021

Revision 3.2

20 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 10: Typical Current Consumption Estimated for Each Macrocell at T = -40 °C to +105 °C (Continued)

Parameter

Description Note

ACMP0H,1H; WS En; Force Sleep Low;

V_DD= 2.3 V V_DD= 3.3 V V_DD= 5.0 V

Unit

µA

0.28

1.83

0.29

1.97

0.35

3.42

WT Short; CNT Data = 100

ACMP0H,1H; IN BUF PIN1,2; WS En;

Force Sleep Low; WT Short;

CNT Data = 1

µA

ACMP0H,1H; IN BUF PIN1,2; WS En;

Force Sleep Low; WT Short;

CNT Data = 10

0.54

0.28

0.57

0.3

0.87

0.36

ACMP0H,1H; IN BUF PIN1,2; WS En;

Force Sleep Low; WT Short;

CNT Data = 100

ACMP0H; WS En; Force Sleep Low;

WT Normal; CNT Data = 1

µA

10.76

2.17

0.46

17.66

3.43

0.60

11.23

2.27

0.49

18.50

3.59

0.63

12.58

2.53

0.54

20.63

4

ACMP0H; WS En; Force Sleep Low;

WT Normal; CNT Data = 10

ACMP0H; WS En; Force Sleep Low;

WT Normal; CNT Data = 100

I

Current

ACMP0H,1H; WS En; Force Sleep Low;

WT Normal; CNT Data = 1

ACMP0H,1H; WS En; Force Sleep Low;

WT Normal; CNT Data = 10

ACMP0H,1H; WS En; Force Sleep Low;

WT Normal; CNT Data = 100

0.70

ACMP0H,1H; IN BUF PIN1,2; WS En;

Force Sleep Low; WT Normal;

CNT Data = 1

µA

21.13

4.06

0.67

22.07

4.24

0.70

24.58

4.72

0.78

ACMP0H,1H; IN BUF PIN1,2; WS En;

Force Sleep Low; WT Normal;

CNT Data = 10

ACMP0H,1H; IN BUF PIN1,2; WS En;

Force Sleep Low; WT Normal;

CNT Data = 100

3.5 TIMING CHARACTERISTICS

Table 11: Typical Delay Estimated for Each Macrocell at T = 25 °C

V_DD= 2.5 V

V_DD= 3.3 V

V_DD= 5 V

Parameter Description Note

Unit

Rising Falling Rising Falling Rising Falling

tpd

Delay

23

24

26

16

17

19

11

12

14

ns

Multi-Function DFF Q

Multi-Function DFF nQ

Multi-Function DFF nRESET

Q

Multi-Function DFF nRESET

nQ

tpd

Delay

--

30

--

21

--

15

--

ns

27

18

13

tpd

Delay

27

--

19

--

13

--

ns

Multi-Function DFF nSET Q

Multi-Function DFF nSET nQ

DFF Q

30

22

16

15

11

18

13

9

Datasheet

24-Feb-2021

Revision 3.2

21 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 11: Typical Delay Estimated for Each Macrocell at T = 25 °C(Continued)

V_DD= 2.5 V

V_DD= 3.3 V

V_DD= 5 V

Parameter Description Note

Unit

Rising Falling Rising Falling Rising Falling

tpd

Delay

19

--

22

23

--

13

--

16

--

9

--

9

11

--

ns

DFF nQ

DFF nRESET Q

19

--

13

--

DFF nRESET nQ

DFF nSET Q

--

9

--

23

24

--

16

17

--

9

11

12

--

DFF nSET nQ

19

20

--

13

14

--

DFF3 First Q

10

--

9

DFF3 First nQ

DFF3 First nRESET Q

DFF3 First nRESET nQ

DFF3 First nSET Q

DFF3 First nSET nQ

DFF3 Second Q

21

20

--

14

--

9

--

24

22

21

24

--

17

16

15

17

--

8

12

11

12

--

18

19

--

12

13

--

8

DFF3 Second nQ

DFF3 Second nRESET Q

DFF3 Second nRESET nQ

DFF3 Second nSET Q

DFF3 Second nSET nQ

Multi-Function LATCH Q

--

9

20

--

14

13

--

9

--

24

25

17

18

19

--

11

12

13

22

23

15

Multi-Function LATCH nQ

Multi-Function LATCH

nRESET Q

Multi-Function LATCH

nRESET nQ

Multi-Function LATCH

nSET Q

Multi-Function LATCH

nSET nQ

tpd

Delay

--

28

26

--

31

--

19

17

--

22

--

13

12

--

16

--

ns

--

29

21

15

tpd

Delay

17

--

20

21

24

--

12

11

--

14

15

17

--

8

7

10

11

12

--

ns

LATCH Q

LATCH nQ

--

LATCH nRESET Q

LATCH nRESET nQ

LATCH nSET Q

21

18

--

14

12

--

10

8

--

22

21

22

25

--

15

16

18

--

11

10

11

12

--

LATCH nSET nQ

18

--

13

12

--

9

LATCH3 First Q

8

LATCH3 First nQ

--

LATCH3 First nRESET Q

LATCH3 First nRESET nQ

LATCH3 First nSET Q

LATCH3 First nSET nQ

LATCH3 Second Q

LATCH3 Second nQ

LATCH3 Second nRESET Q

22

19

--

15

13

--

10

9

--

23

24

23

25

16

18

17

18

--

11

12

20

21

--

14

15

--

10

--

Datasheet

24-Feb-2021

Revision 3.2

22 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 11: Typical Delay Estimated for Each Macrocell at T = 25 °C(Continued)

V_DD= 2.5 V

V_DD= 3.3 V

V_DD= 5 V

Parameter Description Note

Unit

Rising Falling Rising Falling Rising Falling

tpd

Delay

22

19

--

15

13

--

10

9

--

ns

LATCH3 Second nRESET nQ

LATCH3 Second nSET Q

LATCH3 Second nSET nQ

22

24

16

17

--

11

12

22

15

11

Multi-Function 3-bit LUT

Multi-Function 3-bit LUT, CNT

Delay

tpd

Delay

52

22

54

25

53

37

15

38

39

18

38

25

11

26

27

13

27

ns

Multi-Function 4-bit LUT

Multi-Function 4-bit LUT, CNT

Delay

tpd

Delay

17

16

17

11

12

8

9

ns

2-bit LUT

3-bit LUT

Digital input to Low Voltage to

PP 1x

Digital input to with Schmitt

Trigger to PP 1x

tpd

Delay

32

30

226

35

23

22

153

26

18

17

90

19

ns

tpd

Delay

29

28

--

34

33

31

30

21

20

--

25

24

23

22

15

--

19

18

17

ns

Digital input to 1xPP

Digital input to 2xPP

Digital input to 1xNMOS

--

Digital input to 2xNMOS

Digital input to 1x3-State

(Z to 0)

Digital input to 2x3-State

(Z to 0)

Digital input to 1x3-State

(Z to 1)

Digital input to 2x3-State

(Z to 1)

tpd

Delay

--

28

27

--

20

--

15

14

--

ns

30

29

22

21

16

--

tpd

tw

Delay

Width

Delay

--

30

27

32

38

26

27

26

24

23

21

24

23

21

23

214

237

28

--

22

19

23

27

19

16

15

16

14

16

158

174

20

--

16

13

16

19

13

11

10

11

10

11

116

126

15

--

ns

Digital input to 1xOE (Z to 0)

Digital input to 1xOE (Z to 1)

Ripple CNT CLK UP Q0

Ripple CNT CLK UP Q1

Ripple CNT CLK UP Q2

Ripple CNT CLK DOWN Q0

Ripple CNT CLK DOWN Q1

Ripple CNT CLK DOWN Q2

Ripple CNT nSET UP Q0

Ripple CNT nSET UP Q1

Ripple CNT nSET UP Q2

Ripple CNT nSET DOWN Q0

Ripple CNT nSET DOWN Q1

Ripple CNT nSET DOWN Q2

Edge detect

17

16

15

28

34

42

49

54

60

47

46

45

22

215

238

20

19

21

25

30

36

39

44

35

33

15

159

175

14

15

18

22

25

28

31

25

24

23

10

116

127

Edge detect

tpd

Edge detect Delayed

Datasheet

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Table 11: Typical Delay Estimated for Each Macrocell at T = 25 °C(Continued)

V_DD= 2.5 V

V_DD= 3.3 V

V_DD= 5 V

Parameter Description Note

Unit

Rising Falling Rising Falling Rising Falling

tpd

Delay

167

147

17

147

168

21

114

102

12

103

115

16

71

67

8

68

72

11

--

ns

Filter Q

Filter nQ

PGen CLK

--

21

--

15

--

PGen nRESET (Z to 0)

19

--

13

--

9

PGen nRESET (Z to 1)

Pipe Delay OUT0 Q

PD number = 1

tpd

Delay

30

31

--

32

35

28

29

21

22

--

23

24

26

21

15

--

17

18

15

ns

Pipe Delay OUT1 Q

PD number = 1

Pipe Delay OUT1 nQ

PD number = 1

Pipe Delay OUT0 nRESET Q

PD number = 1

Pipe Delay OUT1 nRESET Q

PD number = 1

--

Pipe Delay OUT1

nRESET nQ

PD number = 1

tpd

Delay

27

--

19

--

14

--

ns

Table 12: Programmable Delay Expected Delays and Widths (Typical) at T = 25 °C

Parameter

tw

Description

Note

V_DD= 2.5 V V_DD= 3.3V V_DD= 5.0V Unit

Pulse Width, 1 cell mode: (any) edge detect, edge detect output

Pulse Width, 2 cell mode: (any) edge detect, edge detect output

Pulse Width, 3 cell mode: (any) edge detect, edge detect output

Pulse Width, 4 cell mode: (any) edge detect, edge detect output

214

424

634

844

21

158

313

467

622

14

116

229

342

455

10

ns

tw

time1

time2

Delay, 1 cell

Delay, 2 cell

Delay, 3 cell

Delay, 4 cell

Delay, 1 cell

Delay, 2 cell

Delay, 3 cell

Delay, 4 cell

mode: (any) edge detect, edge detect output

mode: both edge delay, edge detect output

21

14

10

21

14

10

21

15

10

236

446

656

866

173

327

482

637

126

239

351

464

Table 13: Typical Filter Rejection Pulse Width at T = 25 °C

Parameter

V_DD= 2.5 V V_DD= 3.3V V_DD= 5.0V

< 123 < 84 < 52

Unit

Filtered Pulse Width

ns

Table 14: Typical Counter/Delay Offset Measurements at T = 25 °C

Parameter

OSC Freq

25 MHz

OSC Power

auto

V_DD= 2.5 V V_DD= 3.3V V_DD= 5.0V

Unit

µs

Power-ON time

0.14

0.51

0.14

0.46

0.14

0.41

2.048 MHz

auto

µs

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Table 14: Typical Counter/Delay Offset Measurements at T = 25 °C(Continued)

Parameter

OSC Freq

2.048 kHz

25 MHz

OSC Power

auto

V_DD= 2.5 V V_DD= 3.3V V_DD= 5.0V

Unit

µs

ns

Power-ON time

705

4

604

4

486

8

frequency settling time

variable (CLK period)

auto

2.048 MHz

2.048 kHz

25 MHz

auto

0.3

0.4

auto

660

0-40

0-0.5

0-488

570

0-40

0-0.5

0-488

480

0-40

0-0.5

0-488

forced

2.048 MHz

2.048 kHz

µs

25 MHz/

2.048 kHz

tpd (non-delayed edge)

either

35

14

10

ns

Datasheet

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3.6 OSC CHARACTERISTICS

3.6.1 OSC Specifications

Table 15: Oscillators Frequency Limits, V_DD= 2.3 V to 5.5 V

Temperature Range

+25 °C

-40 °C to +105 °C

OSC

Minimum

Value, kHz

Maximum

Value, kHz

Minimum

Value, kHz

Maximum

Value, kHz

Error, %

-1.51

+1.95

-1.72

+1.80

-1.83

2.17

-10.64

2.39

2.048 kHz OSC0

2.048 MHz OSC1

25 MHz OSC2

2.017

2.088

1.830

2.097

-4.81

+2.05

-5.28

+2.30

2012.696

24542.143

2084.811

25541.706

1949.486

23680.428

2089.938

25573.976

3.6.2 OSC Power-On Delay

Table 16: Oscillators Power-On Delay at T = 25 °C, OSC Power Mode: "Auto Power-On"

Oscillator2

25 MHz

Oscillator2 25 MHz

Start with delay

Oscillator1

2.048 MHz

Oscillator0

2.048 kHz

Power

Supply

Range

Typical

Maximum

Value, ns

Typical

Value, ns

Maximum

Value, ns

Typical

Maximum

Value, ns

Typical

Maximum

Value, µs

(V_DD), V

Value, ns

43.844

38.807

30.497

27.357

24.944

22.527

18.789

17.591

Value, ns

527.828

505.070

469.337

455.916

445.562

434.368

411.165

406.866

Value, µs

755.871

712.941

639.114

608.531

584.415

558.844

511.201

485.845

2.3

2.5

3.0

3.3

3.6

4.0

5.0

5.5

59.862

51.244

40.400

36.686

33.393

30.599

25.868

24.709

145.991

144.046

141.900

141.517

141.397

141.366

141.627

141.713

163.927

162.859

163.675

164.780

165.476

166.690

168.998

169.854

558.805

541.510

511.057

497.886

487.231

475.042

453.440

445.683

1141.833

1066.115

930.827

873.573

827.475

777.883

686.248

642.574

3.7 ACMP SPECIFICATIONS

Table 17: ACMP Specifications at T = -40 °C to +105 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted

Parameter Description

Note

Condition

Min

Typ

Max

Unit

ACMP0H,

Positive Input

0

--

V_DD

V

ACMP1H,ACMP2L,

ACMP3L

V_ACMP

Negative Input

0

--

V_DD

V

Input Voltage Range

Datasheet

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

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Table 17: ACMP Specifications at T = -40 °C to +105 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted(Continued)

Parameter Description

Note

Condition

Min

-8.765

-7.511

-7.937

-5.656

-5.942

-4.968

-5.387

-3.610

-4.741

-4.174

-4.436

--

Typ

Max

5.135

5.212

4.086

4.143

6.200

6.400

6.220

6.295

9.525

9.964

8.894

9.266

43.386

61.280

Unit

mV

µs

T = 25 °C

--

ACMP0H, ACMP1H

Input Offset Voltage

--

Vhys = 0 mV, Gain = 1,

Vref = 32 mV

T = 25 °C

--

ACMP2L, ACMP3L

Input Offset Voltage

--

ACMP0H, ACMP1H

Input Offset Voltage

--

Vhys = 0 mV, Gain = 1,

Vref = 1024 mV

V_offset

--

ACMP2L, ACMP3L

Input Offset Voltage

--

ACMP0H, ACMP1H

Input Offset Voltage

Vhys = 0 mV, Gain = 1,

Vref = 2016 mV

--

ACMP2L, ACMP3L

Input Offset Voltage

--

25.340

25.065

ACMP0H, ACMP1H

Start Time

ACMP Power-On delay,

Minimal required wake

time for the “Wake and

Sleep function”

--

µs

t_start

--

133.910 267.936

138.254 358.760

µs

ACMP2L, ACMP3L

Start Time

--

µs

V

_HYS= 32 mV

T = 25 °C

21.287

53.756

182.832

20.837

52.266

181.522

23.977

57.066

184.021

23.410

55.246

183.259

--

39.111

71.486

mV

V_HYS= 64 mV

V_HYS= 192 mV

V_HYS= 32 mV

V_HYS= 64 mV

V_HYS= 192 mV

--

199.421 mV

ACMP0H, ACMP1H

Built-in Hysteresis

--

39.552

71.486

mV

--

199.621 mV

V_HYS

V

_HYS= 32 mV

T = 25 °C

--

39.375

72.087

mV

V_HYS= 64 mV

V_HYS= 192 mV

V_HYS= 32 mV

V_HYS= 64 mV

V_HYS= 192 mV

Gain = 1x

--

200.268 mV

ACMP2L, ACMP3L

Built-in Hysteresis

--

39.910

72.207

mV

--

200.645 mV

100.0

2.0

1.622

--

MΩ

µs

Gain = 0.5x

--

R_sin

Input Resistance

Gain = 0.33x

Gain = 0.25x

--

Gain = 1,

Vref=32mVto2016mV,

Overdrive = 10 mV

Low to High

High to Low

Low to High

High to Low

Low to High

High to Low

--

2.708

--

2.319

0.527

0.530

1.521

1.744

4.505

1.179

0.968

--

µs

Propagation Delay,

Response Time

for ACMP0H,

ACMP1H

Gain = 1,

Vref = 32 mV to 2016 mV,

Overdrive = 100 mV

PROP

Gain = 1, T = 25 °C,

Vref = 32 mV,

Overdrive = 10 mV

--

Datasheet

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

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Table 17: ACMP Specifications at T = -40 °C to +105 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted(Continued)

Parameter Description

Note

Condition

Min

Typ

Max

Unit

Gain = 0.5, T = 25 °C,

Vref = 32 mV,

Overdrive = 10 mV

Low to High

--

2.268

--

µs

High to Low

Low to High

High to Low

Low to High

High to Low

Low to High

High to Low

Low to High

High to Low

Low to High

High to Low

Low to High

High to Low

Low to High

High to Low

Low to High

High to Low

Low to High

High to Low

Low to High

High to Low

Low to High

High to Low

Low to High

High to Low

Low to High

High to Low

Low to High

High to Low

Low to High

High to Low

Low to High

High to Low

--

2.089

2.156

1.979

2.037

1.856

0.567

0.783

0.752

0.700

0.738

0.690

0.715

0.670

47.879

--

µs

Gain = 0.33, T = 25 °C,

Vref = 32 mV,

Overdrive = 10 mV

--

Gain = 0.25, T = 25 °C,

Vref = 32 mV,

Overdrive = 10 mV

--

Propagation Delay,

Response Time

for ACMP0H,

ACMP1H

Gain = 1, T = 25 °C,

Vref = 32 mV,

Overdrive = 100 mV

--

PROP

--

Gain = 0.5, T = 25 °C,

Vref = 32 mV,

Overdrive = 100 mV

--

Gain = 0.33, T = 25 °C,

Vref = 32 mV,

Overdrive = 100 mV

--

Gain = 0.25, T = 25 °C,

Vref = 32 mV,

Overdrive = 100 mV

--

Gain = 1,

Vref = 32 mV to 2016 mV,

Overdrive = 10 mV

88.052

54.803 109.606

Gain = 1,

Vref = 32 mV to 2016 mV,

Overdrive = 100 mV

18.008

17.701

70.241

66.944

61.681

52.956

60.891

52.603

61.228

52.796

28.322

41.648

25.301

24.212

25.022

24.124

24.937

24.097

38.364

38.578

Gain = 1, T = 25 °C,

Vref = 32 mV,

Overdrive = 10 mV

--

Gain = 0.5, T = 25 °C,

Vref = 32 mV,

Overdrive = 10 mV

Gain = 0.33, T = 25 °C,

Vref = 32 mV,

Overdrive = 10 mV

Propagation Delay,

Response Time

for ACMP2L,

PROP

Gain = 0.25, T = 25 °C,

Vref = 32 mV,

Overdrive = 10 mV

ACMP3L

Gain = 1, T = 25 °C,

Vref = 32 mV,

Overdrive = 100 mV

Gain = 0.5, T = 25 °C,

Vref = 32 mV,

Overdrive = 100 mV

Gain = 0.33, T = 25 °C,

Vref = 32 mV,

Overdrive = 100 mV

Gain = 0.25, T = 25 °C,

Vref = 32 mV,

Overdrive = 100 mV

Datasheet

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Revision 3.2

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SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 17: ACMP Specifications at T = -40 °C to +105 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted(Continued)

Parameter Description

Note

Condition

Min

--

Typ

1

Max

--

Unit

G = 1

Gainerror (including

threshold and

internal Vref error)

G = 0.5

G = 0.33

G = 0.25

0.446

0.302

0.227

0.501

0.335

0.251

0.544

0.363

0.272

G

Internal Vref0 error,

Vref0 =

V_DD= 4.0 V

T = 25 °C

-2.465

--

0.633

%

32 mV to 2016 mV

Vref0 Output error,

Vref0 =

224 mV to 2016 mV,

T = 25 °C,

-10.319

-10.923

--

3.514

3.755

5

%

Loading = 1 mA

Buffer Enabled

Load Resistance =

pF

1 MΩ

Load Resistance =

--

10

40

pF

560 kΩ

Load Resistance =

100 kΩ

Vref0 Output

Capacitance

Loading

Load Resistance =

80

10 kΩ

Load Resistance =

120

2 kΩ

Load Resistance =

1 kΩ,

Vref = 32 mV to

1024 mV

--

150

pF

%

Vref

Internal Vref1 error,

Vref1 =

V

_DD= 4.0 V

T = 25 °C

-2.855

1.480

32 mV to 2016 mV

Vref1 Output error,

Vref1 =

224 mV to 2016 mV,

Buffer Enabled

T = 25 °C,

-11.220

-12.731

--

2.915

2.720

15

%

Loading = 1 mA

Load Resistance =

pF

1 MΩ

Load Resistance =

--

27

64

pF

560 kΩ

Load Resistance =

100 kΩ

Vref1 Output

Capacitance

Loading

Load Resistance =

120

180

10 kΩ

Load Resistance =

2 kΩ

Load Resistance =

1 kΩ,

Vref = 32 mV to

1024 mV

--

210

pF

Datasheet

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SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

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Table 17: ACMP Specifications at T = -40 °C to +105 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted(Continued)

Parameter Description

Note

Condition

Min

Typ

Max

Unit

V_DD= 2.3 V,

V_IN= V_DD- 0.7 V

22.567 104.679 139.873 µA

66.853 104.512 126.130 µA

69.223 109.215 142.554 µA

Input Current

Source

V_DD= 3.3 V,

V_IN= V_DD- 0.7 V

Is

V_DD= 5.5 V,

V_IN= V_DD- 0.7 V

3.8 ANALOG TEMPERATURE SENSOR CHARACTERISTICS

Temperature Sensor typical nonlinearity ±2.74% for output range 1 and ±2.69% for output range 2 at V_DD= 3.3 V.

Table 18: TS Output vs Temperature (Output Range 1)

V_DD= 2.3 V

Typical, mV

V_DD= 3.3 V

Typical, mV

V_DD= 5.5 V

Typical, mV

T, °C

Accuracy, %

±1.59

±1.64

±1.63

±1.55

±1.58

±1.57

±1.63

±1.56

±1.71

±1.73

±1.89

±1.84

±1.85

±2.23

±2.03

±2.00

±2.07

Accuracy, %

±1.52

±1.58

±1.61

±1.54

±1.59

±1.54

±1.58

±1.6

Accuracy, %

±1.49

±1.57

±1.55

±1.56

±1.73

±1.74

±1.70

±1.71

±1.85

±1.79

±2.00

±2.43

±2.08

±1.96

±1.98

-40

-30

-20

-10

0

997

975

952

930

907

884

861

851

837

814

790

767

743

719

694

671

659

995

973

950

928

905

882

860

849

836

812

789

765

741

717

693

669

657

995

973

951

929

905

882

860

849

836

813

789

766

741

717

693

670

658

10

20

25

30

40

±1.75

±1.78

±1.85

±1.89

±2.30

±1.89

±1.98

±1.06

50

60

70

80

90

100

105

Table 19: TS Output vs Temperature (Output Range 2)

V_DD= 2.3 V

T, °C

V_DD= 3.3 V

V_DD= 5.5 V

Typical, mV

1205

Accuracy, %

±1.67

Typical, mV

1202

Accuracy, %

±1.42

Typical, mV

1202

Accuracy, %

±1.38

-40

-30

-20

-10

0

1178

±2.09

1175

±1.44

1175

±1.43

1151

±2.59

1148

±1.51

1148

±1.54

1124

±2.21

1121

±1.49

1122

±1.53

1096

±1.80

1094

±1.50

1094

±1.65

10

20

25

30

1068

±1.72

1066

±1.59

1067

±1.63

1041

±1.61

1039

±1.52

1039

±1.68

1027

±1.70

1025

±1.62

1026

±1.63

1012

±1.71

1010

±1.66

1010

±1.73

Datasheet

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

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Table 19: TS Output vs Temperature (Output Range 2)(Continued)

V_DD= 2.3 V

V_DD= 3.3 V

V_DD= 5.5 V

T, °C

Typical, mV

Accuracy, %

±1.71

Typical, mV

Accuracy, %

±1.65

Typical, mV

Accuracy, %

±1.74

40

50

984

955

927

897

868

839

810

796

982

953

925

895

866

837

808

793

982

954

926

895

866

837

809

794

±1.84

±1.81

±1.77

60

±1.85

±1.80

±1.75

70

±1.82

±1.80

±1.92

80

±2.14

±2.28

90

±1.94

±1.88

±1.99

100

105

±2.06

±1.99

±1.94

±2.05

±2.11

±2.04

Table 20: TS Output Error (Output Range 1)

V_DD, V

Error at T

-40 °C, % -20 °C, %

0 °C, %

20 °C, %

40 °C, %

1.73

60 °C, %

1.84

80 °C, % 100 °C, % 105 °C, %

2.30

3.30

4.00

5.50

1.59

1.52

1.48

1.49

1.63

1.61

1.57

1.55

1.58

1.59

1.55

1.73

1.63

1.54

1.50

1.70

2.23

2.30

2.42

2.43

2.00

1.98

1.93

1.96

2.07

2.06

2.00

1.98

1.75

1.85

1.71

1.79

1.71

1.79

Table 21: TS Output Error (Output Range 2)

V_DD, V

Error at T

40 °C, %

1.71

-40 °C, % -20 °C, %

0 °C, %

20 °C, %

1.61

60 °C, %

1.85

80 °C, % 100 °C, % 105 °C, %

2.30

3.30

4.00

5.50

1.67

1.42

1.46

1.38

2.59

1.51

1.54

1.80

1.50

1.58

1.65

2.14

2.22

2.28

2.06

1.99

2.07

1.94

2.05

2.11

2.06

2.04

1.52

1.65

1.80

1.60

1.71

1.76

1.68

1.74

1.75

Datasheet

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Revision 3.2

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CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

4

In-System Debug

In the development phase, the SLG46827-A is a user programmable device with Multiple-Time-Programmable (MTP) memory

elements that are able to configure the connection matrix and macrocells. A programming development kit allows the user the

ability to create initial devices. Once the design is finalized, the programming code (.gpx file) is forwarded to Dialog

Semiconductor to integrate into a production process. At this point, software write protection will be permanently set and the In-

System debug feature will no longer be available to the user.

Product

Definition

E-mail Product Idea, Definition, Drawing or

Customer creates their own design in

Schematic to

GreenPAK Designer

CMBUGreenPAK@diasemi.com

Dialog Semiconductor Applications

Engineer will review design specifications

with customer

Customer verifies GreenPAK in system

design

GreenPAK Design

approved

Samples, Design and Characterization

Report send to customer

GreenPAK Design

approved

Customers verifies GreenPAK design

GreenPAK Design

Approved in system test

Custom GreenPAK part enters production

Figure 2: Steps to Create a Custom GreenPAK Device

Datasheet

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SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

5

IO Pins

5.1 IO PINS

The SLG46827-A has a total of 13 GPIO, 2 GPO, and 2 GPI Pins which can function as either a user defined Input or Output, as

well as serving as a special function (such as outputting the voltage reference).

5.2 GPIO PINS

IO0, IO1, IO2, IO3, IO4, IO5, IO8, IO9, IO10, IO11, IO12, IO13, IO14 serve as General Purpose IO Pins.

5.3 GPO PINS

IO6 and IO7 serve as General Purpose Output Pins.

5.4 GPI PINS

SCL and SDA serve as General Purpose Input Pins.

5.5 PULL-UP/DOWN RESISTORS

All IO Pins have the option of user-selectable resistors that can be connected to the pin structure. The selectable values on these

resistors are 10 kΩ, 100 kΩ, and 1 MΩ. The internal resistors can be configured as either Pull-up or Pull-downs.

5.6 FAST PULL-UP/DOWN DURING POWER-UP

During power-up, IO pull-up/down resistance will switch to 2.6 kΩ initially and then it will switch to normal setting value. This

function is enabled by register [768].

Datasheet

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SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

5.7 I²C MODE IO STRUCTURE (V_DDOR V_DD2

5.7.1 I²C Mode Structure (for SCL and SDA)

)

Input Mode [1:0]

00: Digital In without Schmitt Trigger, wosmt_en = 1

01: Reserved

10: Low Voltage Digital In mode 1, lv_en = 1

11: Reserved

V_DD

PAD

Non-Schmitt

Trigger Input

WOSMT_EN

Digital IN

V_DD

Low Voltage

Input 1

LV_EN

I²C SDA Signal

Only used when

I²C is selected

not available for direct user control

Figure 3: IO with I²C Mode IO Structure Diagram

Datasheet

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SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

5.8 MATRIX OE IO STRUCTURE (V_DDOR V_DD2

)

5.8.1 Matrix OE IO Structure (for IOs 1, 4, 5 with V_DD, and IOs 8, 9, 10, 11, 12, 13, 14 with V_DD2

)

Non-Schmitt

Trigger Input

Input Mode [1:0]

00: Digital In without Schmitt Trigger, wosmt_en = 1

01: Digital In with Schmitt Trigger, smt_en = 1

WOSMT_EN

Schmitt

Trigger Input

10: Low Voltage Digital In mode, lv_en = 1

11: analog IO mode

Digital IN

Output Mode [1:0]

00: Push-Pull 1x mode, pp1x_en = 1

01: Push-Pull 2x mode, pp2x_en = 1, pp1x_en = 1

10: NMOS 1x Open-Drain mode, od1x_en = 1

11: NMOS 2x Open-Drain mode, od2x_en = 1, od1x_en = 1

SMT_EN

LV_EN

Low Voltage

Input

Note 1: Digital Out and OE are Matrix Output, Digital In is Matrix Input

Note 2: Can be varied over PVT, for reference only.

Analog IO

Floating

s0

s1

s2

s3

V_DDor V_DD2

s1

s0

172 Ω

(Note 2)

900 kΩ

Res_sel

90 kΩ

10 kΩ

V

_DDor V_DD2

[1:0]

00: Floating

01: 10 kΩ

10: 100 kΩ

11: 1 MΩ

Pull-up_EN

Digital OUT

OE

OD1x_EN

PP1x_EN

V_DDor V_DD2

PAD

V_DDor V_DD2

Digital OUT

OE

OD2x_EN

PP2x_EN

Figure 4: Matrix OE IO Structure Diagram

Datasheet

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SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

5.9 REGISTER OE IO STRUCTURE (V_DDOR V_DD2

)

5.9.1 Register OE IO Structure (for IOs 0, 2, 3 with V_DD

)

Non-Schmitt

Trigger Input

Input Mode [1:0]

00: Digital In without Schmitt Trigger, wosmt_en = 1, OE = 0

01: Digital In with Schmitt Trigger, smt_en = 1, OE = 0

10: Low Voltage Digital In mode, lv_en = 1, OE = 0

11: Reserved

WOSMT_EN

SMT_EN

OE

Schmitt

Trigger Input

Digital IN

Output Mode [1:0]

00: Push-Pull 1x mode, pp1x_en = 1, OE = 1

01: Push-Pull 2x mode, pp2x_en = 1, OE = 1

10: 1x Open-Drain mode, od1x_en = 1, OE = 1

11: 2x Open-Drain mode, od2x_en = 1, OE = 1

Low Voltage

Input

Note 1: OE cannot be selected by user and is controlled by register

Note 2: Can be varied over PVT, for reference only

LV_EN

OE

Analog IO

Floating

s0

s1

s2

s3

V_DD

s1

s0

172 Ω

(Note 2)

900 kΩ

Res_sel

90 kΩ

10 kΩ

V_DD

[1:0]

00: Floating

01: 10 kΩ

10: 100 kΩ

11: 1 MΩ

Pull-up_EN

Digital OUT

OE

Digital OUT

OE

1x_en

odn_en

1x_en

pp_en

V_DD

PAD

V_DD

Digital OUT

OE

2x_en

pp_en

2x_en

odn_en

Figure 5: GPIO Register OE IO Structure Diagram

Datasheet

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SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

5.10 REGISTER OE IO STRUCTURE (V_DDOR V_DD2

)

5.10.1 Register OE IO Structure (for IO 6 with V_DD, and IO 7 with V_DD2

)

Mode [2:0]

000: Reserved

001: Reserved

010: Reserved

011: Reserved

100: Push-Pull mode, pp_en = 1, OE = 1

101: NMOS Open-Drain mode, odn_en = 1, OE = 1

110: PMOS Open-Drain mode, odp_en = 1, OE = 1

111: analog IO and NMOS Open-Drain mode, odn_en = 1 and aio_en=1

Floating

s0

s1

s2

s3

V_DDor V_DD2

Note: OE cannot be selected by user and is controlled by register

s1

s0

V_DDor V_DD2

900 kΩ

Res_sel

90 kΩ

10 kΩ

[1:0]

00: Floating

01: 10 kΩ

10: 100 kΩ

11: 1 MΩ

Pull-up_EN

odp_EN

Digital OUT

OE

Digital OUT

OE

pp_en

1x_en

odn_EN

V_DDor V_DD2

PAD

V_DDor V_DD2

odp_EN

Digital OUT

OE

Digital OUT

OE

2x_en

pp_en

2x_en

odn_en

Figure 6: GPIO Register OE IO Structure Diagram

Datasheet

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Revision 3.2

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SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

5.11 IO TYPICAL PERFORMANCE

75

70

65

60

55

50

45

40

35

30

25

20

15

10

5

Push-Pull 2x @ VDD = 5.5 V

Push-Pull 1x @ VDD = 5.5 V

Push-Pull 2x @ VDD = 4 V

Push-Pull 1x @ VDD = 4 V

Push-Pull 2x @ VDD = 3.3 V

Push-Pull 1x @ VDD = 3.3 V

Push-Pull 2x @ VDD = 2.3 V

Push-Pull 1x @ VDD = 2.3 V

0

5.5 5.3 5.1 4.9 4.7 4.5 4.3 4.1 3.9 3.7 3.5 3.3 3.1 2.9 2.7 2.5 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 0.7

V_OH(V)

Figure 7: Typical High Level Output Current vs. High Level Output Voltage

80

NMOS 1x @ VDD = 5.5 V

NMOS 1x @ VDD = 4 V

75

70

65

60

55

50

45

40

35

30

25

20

15

10

5

NMOS 1x @ VDD = 3.3 V

NMOS 1x @ VDD = 2.3 V

Push-Pull 1x @ VDD = 5.5 V

Push-Pull 1x @ VDD = 4 V

Push-Pull 1x @ VDD = 3.3 V

Push-Pull 1x @ VDD = 2.3 V

0

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

V_OL(V)

Figure 8: Typical Low Level Output Current vs. Low Level Output Voltage (for 1x Drive)

Datasheet

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SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

160

NMOS 2x @ VDD = 5.5 V

150

NMOS 2x @ VDD = 4 V

140

NMOS 2x @ VDD = 3.3 V

130

NMOS 2x @ VDD = 2.3 V

120

Push-Pull 2x @ VDD = 5.5 V

110

Push-Pull 2x @ VDD = 4 V

100

90

80

70

60

50

40

30

20

10

0

Push-Pull 2x @ VDD = 3.3 V

Push-Pull 2x @ VDD = 2.3 V

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

V_OL(V)

Figure 9: Typical Low Level Output Current vs. Low Level Output Voltage (for 2x Drive)

Datasheet

CFR0011-120-00

24-Feb-2021

Revision 3.2

39 of 180

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

6

Connection Matrix

The Connection Matrix in the SLG46827-A is used to create the internal routing for internal functional macrocells of

the device once it is programmed. The registers are programmed from the multiple-time NVM cell during Test Mode

Operation. The output of each functional macrocell within the SLG46827-A has a specific digital bit code assigned

to it that is either set to active “High” or inactive “Low”, based on the design that is created. Once the 2048 register

bits within the SLG46827-A are programmed a fully custom circuit will be created.

The Connection Matrix has 64 inputs and 96 outputs. Each of the 64 inputs to the Connection Matrix is hard-wired to

the digital output of a particular source macrocell, including IOs, LUTs, analog comparators, other digital resources,

such as V_DDand GND. The input to a digital macrocell uses a 6-bit register to select one of these 64 input lines.

For a complete list of the SLG46827-A’s register table, see Section 18.

Matrix Input Signal

N

Functions

GND

0

1

2

3

IO0 Digital In

IO1 Digital In

IO2 Digital In

62

63

POR OUT

V

DD

Matrix Inputs

N

0

1

2

95

Registers

registers [5:0]

registers [11:6]

registers [17:12]

registers [575:570]

Matrix OUT: IN0 of

LUT2_0 or Clock

Input of DFF0

Matrix OUT: IN1 of

LUT2_0 or Data

Input of DFF0

Matrix Out: IN0 of

LUT2_1 or Clock

Input of PGen

Function

Matrix Output 95

Matrix Outputs

Figure 10: Connection Matrix

Function

Connection Matrix

IO13

IO12

LUT

IO12

IO13

IO14

LUT

IO14

Figure 11: Connection Matrix Example

Datasheet

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Revision 3.2

40 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

6.1 MATRIX INPUT TABLE

Table 22: Matrix Input Table

Matrix Decode

Matrix Input

Matrix Input Signal Function

Number

5

0

1

4

0

1

0

3

0

1

0

1

0

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

GND

1

IO0 Digital Input

2

IO1 Digital Input

3

IO2 Digital Input

4

IO3 Digital Input

5

IO4 Digital Input

6

IO5 Digital Input

7

IO8 Digital Input

8

IO9 Digital Input

9

IO10 Digital Input

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

IO11 Digital Input

IO12 Digital Input

IO13 Digital Input

IO14 Digital Input

LUT2_0_DFF0_OUT

LUT2_1_DFF1_OUT

LUT2_2_DFF2_OUT

LUT2_3_PGEN_OUT

LUT3_0_DFF3_OUT

LUT3_1_DFF4_OUT

LUT3_2_DFF5_OUT

LUT3_3_DFF6_OUT

LUT3_4_DFF7_OUT

LUT3_5_DFF8_OUT

LUT3_6_PIPEDLY_RIPP_CNT_OUT0

PIPEDLY_RIPP_CNT_OUT1

RIPP_CNT_OUT2

EDET_FILTER_OUT

PROG_DLY_EDET_OUT

MULTFUNC_8BIT_1: DLY_CNT_OUT

CKOSC1_MATRIX: OSC1 matrix input

CKOSC0_MATRIX: OSC0 matrix input

CKOSC2_MATRIX: OSC2 matrix input

MULTFUNC_8BIT_2: DLY_CNT_OUT

MULTFUNC_8BIT_3: DLY_CNT_OUT

MULTFUNC_8BIT_4: DLY_CNT_OUT

MULTFUNC_8BIT_5: DLY_CNT_OUT

MULTFUNC_8BIT_6: DLY_CNT_OUT

Datasheet

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Revision 3.2

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SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 22: Matrix Input Table(Continued)

Matrix Decode

Matrix Input

Matrix Input Signal Function

Number

5

1

4

0

1

3

0

1

0

1

2

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

MULTFUNC_8BIT_7: DLY_CNT_OUT

MULTFUNC_16BIT_0: LUT_DFF_OUT

MULTFUNC_8BIT_1: LUT_DFF_OUT

MULTFUNC_8BIT_2: LUT_DFF_OUT

MULTFUNC_8BIT_3: LUT_DFF_OUT

MULTFUNC_8BIT_4: LUT_DFF_OUT

MULTFUNC_8BIT_5: LUT_DFF_OUT

MULTFUNC_8BIT_6: LUT_DFF_OUT

MULTFUNC_8BIT_7: LUT_DFF_OUT

MULTFUNC_16BIT_0: DLY_CNT_OUT

2

I C_virtual_7 Input: register [976]

2

I C_virtual_6 Input: register [977]

2

I C_virtual_5 Input: register [978]

2

I C_virtual_4 Input: register [979]

2

I C_virtual_3 Input: register [980]

2

I C_virtual_2 Input: register [981]

2

I C_virtual_1 Input: register [982]

2

I C_virtual_0 Input: register [983]

ACMP0H_OUT

ACMP1H_OUT

ACMP2L_OUT

ACMP3L_OUT

2nd CKOSC1_MATRIX

2nd CKOSC0_MATRIX

POR OUT

V

DD

6.2 MATRIX OUTPUT TABLE

Table 23: Matrix Output Table

Register Bit

Address

Matrix Output

Number

Matrix Output Signal Function

[5:0]

IN0 of LUT2_0 or Clock Input of DFF0

IN1 of LUT2_0 or Data Input of DFF0

IN0 of LUT2_3 or Clock Input of PGen

IN1 of LUT2_3 or nRST of PGen

0

1

2

3

4

5

6

7

8

[11:6]

[17:12]

[23:18]

[29:24]

[35:30]

[41:36]

[47:42]

[53:48]

IN0 of LUT2_1 or Clock Input of DFF1

IN1 of LUT2_1 or Data Input of DFF1

IN0 of LUT2_2 or Clock Input of DFF2

IN1 of LUT2_2 or Data Input of DFF2

IN0 of LUT3_0 or Clock Input of DFF3

Datasheet

CFR0011-120-00

24-Feb-2021

Revision 3.2

42 of 180

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 23: Matrix Output Table(Continued)

Register Bit

Matrix Output

Number

Matrix Output Signal Function

Address

[59:54]

[65:60]

IN1 of LUT3_0 or Data Input of DFF3

IN2 of LUT3_0 or nRST(nSET) of DFF3

IN0 of LUT3_1 or Clock Input of DFF4

IN1 of LUT3_1 or Data Input of DFF4

IN2 of LUT3_1 or nRST(nSET) of DFF4

IN0 of LUT3_2 or Clock Input of DFF5

IN1 of LUT3_2 or Data Input of DFF5

IN2 of LUT3_2 or nRST(nSET) of DFF5

IN0 of LUT3_3 or Clock Input of DFF6

IN1 of LUT3_3 or Data Input of DFF6

IN2 of LUT3_3 or nRST(nSET) of DFF6

IN0 of LUT3_4 or Clock Input of DFF7

IN1 of LUT3_4 or Data Input of DFF7

IN2 of LUT3_4 or nRST(nSET) of DFF7

IN0 of LUT3_5 or Clock Input of DFF8

IN1 of LUT3_5 or Data Input of DFF8

IN2 of LUT3_5 or nRST(nSET) of DFF8

IN0 of LUT3_6 or Input of Pipe Delay or UP Signal of RIPP CNT

IN1 of LUT3_6 or nRST of Pipe Delay or STB of RIPP CNT

IN2 of LUT3_6 or Clock of Pipe Delay_RIPP_CNT

Reserved

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

[71:66]

[77:72]

[83:78]

[89:84]

[95:90]

[101:96]

[107:102]

[113:108]

[119:114]

[125:120]

[131:126]

[137:132]

[143:138]

[149:144]

[155:150]

[161:156]

[167:162]

[173:168]

[179:174]

MULTFUNC_16BIT_0: IN0 of LUT4_0 or Clock Input of DFF9;

Delay0 Input (or Counter0 RST/SET Input)

[185:180]

[191:186]

[197:192]

[203:198]

[209:204]

[215:210]

[221:216]

[227:222]

[233:228]

[239:234]

[245:240]

MULTFUNC_16BIT_0: IN1 of LUT4_0 or nRST of DFF9;

Delay0 Input (or Counter0 nRST Input) or Delay/Counter0 External Clock Source

31

32

33

34

35

36

37

38

39

40

MULTFUNC_16BIT_0: IN2 of LUT4_0 or nSET of DFF9 or KEEP Input of FSM0 or

External Clock Input of Delay0 (or Counter0)

MULTFUNC_16BIT_0: IN3 of LUT4_0 or Data Input of DFF9;

Delay0 Input (or Counter0 nRST Input) or UP Input of FSM0

MULTFUNC_8BIT_1: IN0 of LUT3_7 or Clock Input of DFF10;

Delay1 Input (or Counter1 nRST Input)

MULTFUNC_8BIT_1: IN1 of LUT3_7 or nRST (nSET) of DFF10;

Delay1 Input (or Counter1 nRST Input) or Delay/Counter1 External Clock Source

MULTFUNC_8BIT_1: IN2 of LUT3_7 or Data Input of DFF10;

Delay1 Input (or Counter1 nRST Input)

MULTFUNC_8BIT_2: IN0 of LUT3_8 or Clock Input of DFF11;

Delay2 Input (or Counter2 nRST Input)

MULTFUNC_8BIT_2: IN1 of LUT3_8 or nRST (nSET) of DFF11;

Delay2 Input (or Counter2 nRST Input) or Delay/Counter2 External Clock Source

MULTFUNC_8BIT_2: IN2 of LUT3_8 or Data Input of DFF11;

Delay2 Input (or Counter2 nRST Input)

MULTFUNC_8BIT_3: IN0 of LUT3_9 or Clock Input of DFF12;

Delay3 Input (or Counter3 nRST Input)

Datasheet

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24-Feb-2021

Revision 3.2

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SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 23: Matrix Output Table(Continued)

Register Bit

Matrix Output

Number

Matrix Output Signal Function

Address

MULTFUNC_8BIT_3: IN1 of LUT3_9 or nRST (nSET) of DFF12;

[251:246]

41

42

43

44

45

46

47

48

49

50

51

52

53

54

Delay3 Input (or Counter3 nRST Input) or Delay/Counter3 External Clock Source

MULTFUNC_8BIT_3: IN2 of LUT3_9 or Data Input of DFF12;

Delay3 Input (or Counter3 nRST Input)

[257:252]

MULTFUNC_8BIT_4: IN0 of LUT3_10 or Clock Input of DFF13;

Delay4 Input (or Counter4 nRST Input)

[263:258]

MULTFUNC_8BIT_4: IN1 of LUT3_10 or nRST (nSET) of DFF13;

[269:264]

Delay4 Input (or Counter4 nRST Input) or Delay/Counter4 External Clock Source

MULTFUNC_8BIT_4: IN2 of LUT3_10 or Data Input of DFF13;

Delay4 Input (or Counter4 nRST Input)

[275:270]

MULTFUNC_8BIT_5: IN0 of LUT3_11 or Clock Input of DFF14;

Delay5 Input (or Counter5 nRST Input)

[281:276]

MULTFUNC_8BIT_5: IN1 of LUT3_11 or nRST (nSET) of DFF14;

[287:282]

Delay5 Input (or Counter5 nRST Input) or Delay/Counter5 External Clock Source

MULTFUNC_8BIT_5: IN2 of LUT3_11 or Data Input of DFF14;

Delay5 Input (or Counter5 nRST Input)

[293:288]

MULTFUNC_8BIT_6: IN0 of LUT3_12 or Clock Input of DFF15;

Delay6 Input (or Counter6 nRST Input)

[299:294]

MULTFUNC_8BIT_6: IN1 of LUT3_12 or nRST (nSET) of DFF15;

[305:300]

Delay6 Input (or Counter6 nRST Input) or Delay/Counter6 External Clock Source

MULTFUNC_8BIT_6: IN2 of LUT3_12 or Data Input of DFF15;

Delay6 Input (or Counter6 nRST Input)

[311:306]

MULTFUNC_8BIT_7: IN0 of LUT3_13 or Clock Input of DFF16;

Delay7 Input (or Counter7 nRST Input)

[317:312]

MULTFUNC_8BIT_7: IN1 of LUT3_13 or nRST (nSET) of DFF16;

[323:318]

Delay7 Input (or Counter7 nRST Input) or Delay/Counter7 External Clock Source

MULTFUNC_8BIT_7: IN2 of LUT3_13 or Data Input of DFF16;

Delay7 Input (or Counter7 nRST Input)

[329:324]

[335:330]

[341:336]

[347:342]

[353:348]

[359:354]

[365:360]

[371:366]

[377:372]

[383:378]

[389:384]

[395:390]

[401:396]

[407:402]

[413:408]

[419:414]

[425:420]

Filter/Edge detect input

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

Programmable delay/edge detect input

OSC2 ENABLE from matrix

OSC0 ENABLE from matrix

OSC1 ENABLE matrix

Temp sensor and Vref PD from matrix

BG power-down from matrix

PWR UP of ACMP0H from matrix

PWR UP of ACMP1H from matrix

PWR UP of ACMP2L from matrix

PWR UP of ACMP3L from matrix

Reserved

IO0 Digital Output

IO1 Digital Output

IO1 Digital Output OE

IO2 Digital Output

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Table 23: Matrix Output Table(Continued)

Register Bit

Matrix Output

Number

Matrix Output Signal Function

Address

[431:426]

[437:432]

[443:438]

[449:444]

[455:450]

[461:456]

[467:462]

[473:468]

[479:474]

[485:480]

[491:486]

[497:492]

[503:498]

[509:504]

[515:510]

[521:516]

[527:522]

[533:528]

[539:534]

[545:540]

[551:546]

[557:552]

[563:558]

[569:564]

[575:570]

IO3 Digital Output

IO4 Digital Output

IO4 Digital Output OE

IO5 Digital Output

IO5 Digital Output OE

IO6 Digital Output

IO7 Digital Output

IO8 Digital Output

IO8 Digital Output OE

IO9 Digital Output

IO9 Digital Output OE

IO10 Digital Output

IO10 Digital Output OE

IO11 Digital Output

IO11 Digital Output OE

IO12 Digital Output

IO12 Digital Output OE

IO13 Digital Output

IO13 Digital Output OE

IO14 Digital Output

IO14 Digital Output OE

Reserved

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

Reserved

Matrix OUT 94

Matrix OUT 95

Note 1 For each Address, the two most significant bits are unused.

6.3 CONNECTION MATRIX VIRTUAL INPUTS

As mentioned previously, the Connection Matrix inputs come from the outputs of various digital macrocells on the

device. Eight of the Connection Matrix inputs have the special characteristic that the state of these signal lines comes

from a corresponding data bit written as a register value via I²C. This gives the user the ability to write data via the

serial channel, and have this information translated into signals that can be driven into the Connection Matrix and

from the Connection Matrix to the digital inputs of other macrocells on the device. The I²C address for reading and

writing these register values is at 0x7A (0122).

An I²C write command to these register bits will set the signal values going into the Connection Matrix to the desired

state. A read command to these register bits will read either the original data values coming from the NVM memory

bits (that were loaded during the initial device startup), or the values from a previous write command (if that has

happened).

See Table 24.

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Table 24: Connection Matrix Virtual Inputs

Matrix Input

Register Bit

Addresses (d)

Matrix Input Signal Function

Number

2

55

54

53

52

51

50

49

48

I C_virtual_0 Input

[983]

[982]

[981]

[980]

[979]

[978]

[977]

[976]

2

I C_virtual_1 Input

2

I C_virtual_2 Input

2

I C_virtual_3 Input

2

I C_virtual_4 Input

2

I C_virtual_5 Input

2

I C_virtual_6 Input

2

I C_virtual_7 Input

6.4 CONNECTION MATRIX VIRTUAL OUTPUTS

The digital outputs of the various macrocells are routed to the Connection Matrix to enable interconnections to the inputs of other

macrocells in the device. At the same time, it is possible to read the state of each of the macrocell outputs as a register value via

2

I C. This option, called Connection Matrix Virtual Outputs, allows the user to remotely read the values of each macrocell output.

2

The I C addresses for reading these register values are 0x74 (0116) to 0x7B (0123). Write commands to these same register

values will be ignored (with the exception of the Virtual Input register bits at 0x7A (0122)).

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7

Combination Function Macrocells

The SLG46827-A has 11 combination function macrocells that can serve more than one logic or timing function. In each case,

they can serve as a Look Up Table (LUT), or as another logic or timing function. See the list below for the functions that can be

implemented in these macrocells.

.

Three macrocells that can serve as either 2-bit LUT or as D Flip-Flop

Six macrocells that can serve as either 3-bit LUTs or as D Flip-Flops with Set/Reset Input

One macrocell that can serve as either 3-bit LUT or as Pipe Delay/Ripple Counter

One macrocell that can serve as either 2-bit LUT or as Programmable Pattern Generator (PGen)

Inputs/Outputs for the 11 combination function macrocells are configured from the connection matrix with specific logic functions

being defined by the state of NVM bits.

When used as a LUT to implement combinatorial logic functions, the outputs of the LUTs can be configured to any user defined

function, including the following standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR).

7.1 2-BIT LUT OR D FLIP-FLOP MACROCELLS

There are three macrocells that can serve as either 2-bit LUT or as D Flip-Flop. When used to implement LUT functions, the

2-bit LUT takes in two input signals from the connection matrix and produce a single output, which goes back into the connection

matrix. When used to implement D Flip-Flop function, the two input signals from the connection matrix go to the data (D) and

clock (CLK) inputs for the Flip-Flop, with the output going back to the connection matrix.

The operation of the D Flip-Flop and LATCH will follow the functional descriptions below:

DFF: CLK is rising edge triggered, then Q = D; otherwise Q will not change

LATCH: when CLK is Low, then Q = D; otherwise Q remains its previous value (input D has no effect on the output, when CLK is

High).

register [1155] DFF or Latch Select

IN1

register [1154] Output Select (Q or nQ)

S0

From Connection Matrix Output [1]

register [1153] DFF Initial Polarity Select

OUT

2-bit LUT0

0: 2-bit LUT0 IN1

1: DFF0 Data

S1

IN0

LUT Truth

Table

To Connection Matrix

Input [14]

S0

S1

4-bits NVM

registers [1155:1152]

0: 2-bit LUT0 Out

1: DFF0 Out

DFF/Latch

Registers

D

S0

S1

From Connection Matrix Output [0]

Q/nQ

DFF0

0: 2-bit LUT0 IN0

1: DFF0 CLK

CLK

1-bit NVM

register [1232]

Figure 12: 2-bit LUT0 or DFF0

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register [1159] DFF or Latch Select

register [1158] Output Select (Q or nQ)

register [1157] DFF Initial Polarity Select

IN1

S0

From Connection Matrix Output [5]

OUT

2-bit LUT1

0: 2-bit LUT1 IN1

1: DFF1 Data

S1

IN0

LUT Truth

Table

To Connection Matrix

S0

Input [15]

4-bits NVM

registers [1159:1156]

S1

0: 2-bit LUT1 Out

1: DFF1 Out

DFF/Latch

Registers

D

S0

S1

From Connection Matrix Output [4]

Q/nQ

DFF1

0: 2-bit LUT1 IN0

1: DFF1 CLK

CLK

1-bit NVM

register [1233]

Figure 13: 2-bit LUT1 or DFF1

register [1163] DFF or Latch Select

register [1162] Output Select (Q or nQ)

register [1161] DFF Initial Polarity Select

IN1

S0

S1

From Connection Matrix Output [7]

OUT

2-bit LUT2

0: 2-bit LUT2 IN1

1: DFF2 Data

IN0

LUT Truth

Table

To Connection Matrix

S0

Input [16]

4-bits NVM

registers [1163:1160]

S1

0: 2-bit LUT2 Out

1: DFF2 Out

DFF/Latch

Registers

D

S0

S1

From Connection Matrix Output [6]

Q/nQ

DFF2

0: 2-bit LUT2 IN0

1: DFF2 CLK

CLK

1-bit NVM

register [1234]

Figure 14: 2-bit LUT2 or DFF2

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7.1.1 2-Bit LUT or D Flip-Flop Macrocell Used as 2-Bit LUT

Table 25: 2-bit LUT0 Truth Table

IN1

0

IN0

0

OUT

register [1152]

register [1153]

register [1154]

register [1155]

LSB

0

1

0

1

MSB

Table 26: 2-bit LUT1 Truth Table

IN1

0

IN0

0

OUT

register [1156]

register [1157]

register [1158]

register [1159]

LSB

0

1

0

1

MSB

Table 27: 2-bit LUT2 Truth Table

IN1

0

IN0

0

OUT

register [1160]

register [1161]

register [1162]

register [1163]

LSB

0

1

0

1

MSB

This macrocell, when programmed for a LUT function, uses a 4-bit register to define their output function:

2-Bit LUT0 is defined by registers [1155:1152]

2-Bit LUT1 is defined by registers [1159:1156]

2-Bit LUT2 is defined by registers [1163:1160]

Table 28 shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be created

within each of the 2-bit LUT logic cells.

Table 28: 2-bit LUT Standard Digital Functions

Function

AND-2

MSB

LSB

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

NAND-2

OR-2

NOR-2

XOR-2

XNOR-2

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7.1.2 Initial Polarity Operations

V_DD

Data

Clock

POR

Initial Polarity: High

Q with nReset (Case 1)

Initial Polarity: Low

Q with nReset (Case 1)

Figure 15: DFF Polarity Operations

7.2 2-BIT LUT OR PROGRAMMABLE PATTERN GENERATOR

The SLG46827-A has one combination function macrocell that can serve as a logic or timing function. This macrocell can serve

as a Look Up Table (LUT), or Programmable Pattern Generator (PGen).

When used to implement LUT functions, the 2-bit LUT takes in two input signals from the connection matrix and produces a single

output, which goes back into the connection matrix. When used as a LUT to implement combinatorial logic functions, the outputs

of the LUT can be configured to any user defined function, including the following standard digital logic devices (AND, NAND,

OR, NOR, XOR, XNOR). The user can also define the combinatorial relationship between inputs and outputs to be any selectable

function.

When operating as a Programmable Pattern Generator, the output of the macrocell with clock out a sequence of two to sixteen

bits that are user selectable in their bit values, and user selectable in the number of bits (up to sixteen) that are output before the

pattern repeats.

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From Connection Matrix Output [2]

From Connection Matrix Output [3]

In0

In1

OUT

2-bit LUT3

LUT Truth

Table

To Connection Matrix Input [17]

S0

S1

registers [1183:1168]

0: 2-bit LUT3 OUT

1: PGen OUT

PGen

Data

nRST

CLK

PGen

OUT

Pattern

size

register [1235]

registers [1167:1164]

Figure 16: 2-bit LUT3 or PGen

V_DD

t

nRST

CLK

OUT

1

2

6

8

16 17

3

5

7

0

4

9

10 11

14 15

12 13

t

D7

D6

D5

D10

D8

D4

D3

D2

D1

D15

D0

D9

D0

D15

D14

D13

D12

D11

D0

t

Figure 17: PGen Timing Diagram

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7.2.1 2-Bit LUT or PGen Macrocell Used as 2-Bit LUT

Table 29: 2-bit LUT1 Truth Table

IN1

0

IN0

0

OUT

register [1164]

register [1165]

register [1166]

register [1167]

LSB

0

1

0

1

MSB

This macrocell, when programmed for a LUT function, uses a 4-bit register to define their output function:

2-Bit LUT3 is defined by [1167 1164

:

]

Table 30 shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be created

within each of the 2-bit LUT logic cells.

Table 30: 2-bit LUT Standard Digital Functions

Function

AND-2

MSB

LSB

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

NAND-2

OR-2

NOR-2

XOR-2

XNOR-2

7.3 3-BIT LUT OR D FLIP-FLOP WITH SET/RESET MACROCELLS

There are six macrocells that can serve as either 3-bit LUTs or as D Flip-Flops with Set/Reset inputs. When used to implement

LUT functions, the 3-bit LUTs each take in three input signals from the connection matrix and produce a single output, which goes

back into the connection matrix. When used to implement D Flip-Flop function, the three input signals from the connection matrix

go to the data (D) and clock (CLK), and Reset/Set (nRST/nSET) inputs for the Flip-Flop, with the output going back to the

connection matrix.

DFF3 operation is described below:



If register [1237] = 0, and the CLK is rising edge triggered, then Q = D, otherwise Q will not change

If register [1237] = 1, then data from D is written into the DFF by the rising edge on CLK and output to Q by the falling edge on

CLK.

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register [1191] DFF or Latch Select

register [1190] Output Select (Q or nQ)

register [1189] DFF nRST or nSET Select

register [1188] DFF Initial Polarity Select

IN2

IN1

From Connection

Matrix Output [10]

S0

S1

OUT

3-bit LUT0

IN0

LUT Truth

Table

From Connection

Matrix Output [9]

To Connection Matrix

S0

S1

Input [18]

S0

S1

8-bits NVM

registers [1191:1184]

From Connection

Matrix Output [8]

S0

S1

DFF/Latch

Registers

0

1

Q/nQ

DFF

D

Q

D

Q

nRST/

nSET

nRST/

CL

nSET

CL

nRST/nSET

CLK

register [1237]

1-bit NVM

register [1236]

Figure 18: 3-bit LUT0 or DFF3

register [1199] DFF or Latch Select

IN2

From Connection

Matrix Output [13]

S0

S1

register [1198] Output Select (Q or nQ)

register [1197] DFF nRST or nSET Select

register [1196] DFF Initial Polarity Select

IN1

OUT

3-bit LUT1

IN0

LUT Truth

Table

From Connection

Matrix Output [12]

To Connection Matrix

S0

S1

Input [19]

S0

8-bits NVM

registers [1199:1192]

S1

DFF/Latch

Registers

D

From Connection

Matrix Output [11]

S0

S1

nRST/nSET

CLK

DFF4

Q/nQ

1-bit NVM

register [1238]

Figure 19: 3-bit LUT1 or DFF4

Revision 3.2

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register [1207] DFF or Latch Select

IN2

From Connection

S0

register [1206] Output Select (Q or nQ)

register [1205] DFF nRST or nSET Select

register [1204] DFF Initial Polarity Select

Matrix Output [16]

IN1

IN0

OUT

3-bit LUT2

S1

LUT Truth

Table

From Connection

Matrix Output [15]

To Connection Matrix

S0

S1

S0

S1

Input [20]

8-bits NVM

registers [1207:1200]

DFF/Latch

Registers

D

From Connection

Matrix Output [14]

S0

S1

nRST/nSET

CLK

DFF5

Q/nQ

1-bit NVM

register [1239]

Figure 20: 3-bit LUT2 or DFF5

register [1215] DFF or Latch Select

IN2

From Connection

Matrix Output [19]

S0

S1

register [1214] Output Select (Q or nQ)

register [1213] DFF nRST or nSET Select

register [1212] DFF Initial Polarity Select

IN1

OUT

3-bit LUT3

IN0

LUT Truth

Table

From Connection

Matrix Output [18]

To Connection Matrix

S0

S1

S0

S1

Input [21]

8-bits NVM

registers [1215:1208]

DFF

Registers

D

From Connection

Matrix Output [17]

S0

S1

nRST/nSET

CLK

DFF6

Q/nQ

1-bit NVM

register [1240]

Figure 21: 3-bit LUT3 or DFF6

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register [1223] DFF or Latch Select

IN2

IN1

From Connection

Matrix Output [22]

S0

S1

register [1222] Output Select (Q or nQ)

register [1221] DFF nRST or nSET Select

register [1220] DFF Initial Polarity Select

OUT

3-bit LUT4

IN0

LUT Truth

Table

From Connection

Matrix Output [21]

To Connection Matrix

S0

S1

S0

S1

Input [22]

8-bits NVM

registers [1223:1216]

DFF/Latch

Registers

D

From Connection

Matrix Output [20]

S0

S1

nRST/nSET

CLK

DFF7

Q/nQ

1-bit NVM

registers [1241]

Figure 22: 3-bit LUT4 or DFF7

register [1231] DFF or Latch Select

IN2

From Connection

Matrix Output [25]

S0

S1

register [1230] Output Select (Q or nQ)

register [1229] DFF nRST or nSET Select

register [1228] DFF Initial Polarity Select

IN1

OUT

3-bit LUT5

IN0

LUT Truth

Table

From Connection

Matrix Output [24]

To Connection Matrix

S0

S1

S0

S1

Input [23]

8-bits NVM

registers [1231:1224]

DFF

Registers

D

From Connection

Matrix Output [23]

S0

S1

nRST/nSET

CLK

DFF8

Q/nQ

1-bit NVM

register [1242]

Figure 23: 3-bit LUT5 or DFF8

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7.3.1 3-Bit LUT or D Flip-Flop Macrocells Used as 3-Bit LUTs

Table 31: 3-bit LUT0 Truth Table

Table 34: 3-bit LUT3 Truth Table

IN2

0

IN1

0

IN0

0

OUT

IN2

0

IN1

0

IN0

0

OUT

register [1184]

register [1185]

register [1186]

register [1187]

register [1188]

register [1189]

register [1190]

register [1191]

LSB

register [1208]

register [1209]

register [1210]

register [1211]

register [1212]

register [1213]

register [1214]

register [1215]

LSB

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

MSB

LSB

1

MSB

LSB

Table 32: 3-bit LUT1 Truth Table

Table 35: 3-bit LUT4 Truth Table

IN2

0

IN1

0

IN0

0

OUT

IN2

0

IN1

0

IN0

0

OUT

register [1192]

register [1193]

register [1194]

register [1195]

register [1196]

register [1197]

register [1198]

register [1199]

register [1216]

register [1217]

register [1218]

register [1219]

register [1220]

register [1221]

register [1222]

register [1223]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

MSB

LSB

1

MSB

LSB

Table 33: 3-bit LUT2 Truth Table

Table 36: 3-bit LUT5 Truth Table

IN2

0

IN1

0

IN0

0

OUT

IN2

0

IN1

0

IN0

0

OUT

register [1200]

register [1201]

register [1202]

register [1203]

register [1204]

register [1205]

register [1206]

register [1207]

register [1224]

register [1225]

register [1226]

register [1227]

register [1228]

register [1229]

register [1230]

register [1231]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

MSB

1

MSB

Each macrocell, when programmed for a LUT function, uses a 8-bit register to define their output function:

3-Bit LUT0 is defined by registers [1191:1184]

3-Bit LUT1 is defined by registers [1199:1192]

3-Bit LUT2 is defined by registers [1207:1200]

3-Bit LUT3 is defined by registers [1215:1208]

3-Bit LUT4 is defined by registers [1223:1216]

3-Bit LUT5 is defined by registers [1231:1224]

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Table 37 shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be created

within each of the four 3-bit LUT logic cells.

Table 37: 3-bit LUT Standard Digital Functions

Function

AND-3

MSB

LSB

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

NAND-3

OR-3

NOR-3

XOR-3

XNOR-3

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7.3.2 Initial Polarity Operations

V_DD

Data

Clock

POR

Initial Polarity: High

nReset (Case 1)

Q with nReset (Case 1)

nReset (Case 2)

Q with nReset (Case 2)

Initial Polarity: Low

nReset (Case 1)

Q with nReset (Case 1)

nReset (Case 2)

Q with nReset (Case 2)

Figure 24: DFF Polarity Operations with nReset

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V_DD

Data

Clock

POR

Initial Polarity: High

nSet (Case 1)

Q with nSet (Case 1)

nSet (Case 2)

Q with nSet (Case 2)

Initial Polarity: Low

nSet (Case 1)

Q with nSet (Case 1)

nSet (Case 2)

Q with nSet (Case 2)

Figure 25: DFF Polarity Operations with nSet

7.4 3-BIT LUT OR PIPE DELAY/RIPPLE COUNTER MACROCELL

There is one macrocell that can serve as either a 3-bit LUT or as a Pipe Delay/Ripple Counter.

When used to implement LUT functions, the 3-bit LUT takes in three input signals from the connection matrix and produces a

single output, which goes back into the connection matrix.

When used as a Pipe Delay, there are three inputs signals from the matrix, Input (IN), Clock (CLK), and Reset (nRST). The Pipe

Delay cell is built from 16 D Flip-Flop logic cells that provide the three delay options, two of which are user selectable. The DFF

cells are tied in series where the output (Q) of each delay cell goes to the next DFF cell input (IN). Both of the two outputs (OUT0

and OUT1) provide user selectable options for 1 to 16 stages of delay. There are delay output points for each set of the OUT0

and OUT1 outputs to a 4-input mux that is controlled by registers [1251:1248] for OUT0 and registers [1255:1252] for OUT1.

The 4-input mux is used to control the selection of the amount of delay.

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The overall time of the delay is based on the clock used in the SLG46827-A design. Each DFF cell has a time delay of the inverse

of the clock time (either external clock or the internal Oscillator within the SLG46827-A). The sum of the number of DFF cells used

will be the total time delay of the Pipe Delay logic cell. OUT1 Output can be inverted (as selected by register [1256]).

In the Ripple Counter mode, there are 3 options for setting, which use 7 bits. There are 3 bits to set nSET value (SV) in range

from 0 to 7. It is a value, which will be set into the Ripple Counter outputs when nSET input goes LOW. End value (EV) will use

3 bits for setting outputs code, which will be last code in the cycle. After reaching the EV, the Ripple Counter goes to the first code

by the rising edge on CLK input. The Functionality mode option uses 1 bit. This setting defines how exactly Ripple Counter will

operate.

The user can select one of the functionality modes by register: RANGE or FULL. If the RANGE option is selected, the count starts

from SV. If UP input is LOW the count goes down: SV→EV→EV-1 to SV+1→SV, and others (if SV is smaller than EV), or SV→SV-

1 to EV+1→EV→SV (if SV is bigger than EV). If UP input is HIGH, count starts from SV up to EV, and others.

In the FULL range configuration the Ripple Counter functions as follows. If UP input is LOW, the count starts from SV and goes

down to 0. Then current counter value jumps to EV and goes down to 0, and others.

If UP input is HIGH, count goes up starting from SV. Then current counter value jumps to 0 and counts up to EV, and others. See

Ripple Counter functionality example in Figure 27.

Every step is executed by the rising edge on CLK input.

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registers [1255:1248]

From Connection

Matrix Output [26]

IN0

From Connection

Matrix Output [27]

IN1

IN2

OUT

3-bit LUT6

From Connection

Matrix Output [28]

registers [1255:1252]

Pipe Delay

register [1256]

0

1

0

1

OUT2

OUT1

To Connection

Matrix Input[26]

register [1258]

From Connection

Matrix Output [26]

IN

From Connection

Matrix Output [27]

nRST

16 Flip-Flops

0

OUT1

From Connection

Matrix Output [28]

CLK

To Connection

Matrix Input [25]

1

register [1258]

OUT0

0

OUT0

To Connection

Matrix Input [24]

0

1

registers [1251:1248]

1 Pipe OUT

register [1257]

Ripple Counter

3 Flip-Flops

UP

From Connection

Matrix Output [26]

UP/DOWN

Control

OUT0

D

Q

DFF1

CLK

From Connection

Matrix Output [28]

CL

nQ

nSET

From Connection

Matrix Output [27]

SET

OUT1

OUT2

Control

D

Q

DFF2

CL

nQ

Mode & SET/END

Value Control

D

Q

DFF3

nQ

CL

registers [1254:1248]

Figure 26: 3-bit LUT6/Pipe Delay/Ripple Counter

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Figure 27: Example: Ripple Counter Functionality

7.4.1 3-Bit LUT or Pipe Delay Macrocells Used as 3-Bit LUT

Table 38: 3-bit LUT6 Truth Table

IN2

0

IN1

0

IN0

0

OUT

register [1248]

register [1249]

register [1250]

register [1251]

register [1252]

register [1253]

register [1254]

register [1255]

0

1

0

1

0

1

0

1

0

1

0

1

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Each macrocell, when programmed for a LUT function, uses a 8-bit register to define their output function:

3-Bit LUT6 is defined by registers [1255:1248]

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8

Multi-Function Macrocells

The SLG46827-A has 8 Multi-Function macrocells that can serve more than one logic or timing function. In each case, they can

serve as a LUT, DFF with flexible settings, or as CNT/DLY with multiple modes such as One Shot, Frequency Detect, Edge Detect,

and others. Also, the macrocell is capable to combine those functions: LUT/DFF connected to CNT/DLY or CNT/DLY connected

to LUT/DFF, see Figure 28.

See the list below for the functions that can be implemented in these macrocells:



Seven macrocells that can serve as 3-bit LUTs/D Flip-Flops and as 8-Bit Counter/Delays

One macrocell that can serve as a 4-bit LUT/D Flip-Flop and as 16-Bit Counter/Delay/FSM

To Connection Matrix

To Connection

Matrix

LUT

or

DFF

LUT

Matrix

CNT/DLY

or

CNT/DLY

DFF

Figure 28: Possible Connections Inside Multi-Function Macrocell

Inputs/Outputs for the 8 Multi-Function macrocells are configured from the connection matrix with specific logic functions being

defined by the state of NVM bits.

When used as a LUT to implement combinatorial logic functions, the outputs of the LUTs can be configured to any user defined

function, including the following standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR).

8.1 3-BIT LUT OR DFF/LATCH WITH 8-BIT COUNTER/DELAY MACROCELLS

There are seven macrocells that can serve as 3-bit LUTs/D Flip-Flops and as 8-Bit Counter/Delays.

When used to implement LUT functions, the 3-bit LUTs each take in three input signals from the connection matrix and produce

a single output, which goes back into the connection matrix or can be connected to CNT/DLY's input.

When used to implement D Flip-Flop function, the three input signals from the connection matrix go to the data (D), clock (CLK),

and Reset/Set (nRST/nSET) inputs of the Flip-Flop, with the output going back to the connection matrix or to the CNT/DLY's input.

When used to implement Counter/Delays, each macrocell has a dedicated matrix input connection. For flexibility, each of these

macrocells has a large selection of internal and external clock sources, as well as the option to chain from the output of the

previous (N-1) CNT/DLY macrocell, to implement longer count/delay circuits. These macrocells can also operate in a One-Shot

mode, which will generate an output pulse of user-defined width. They can also operate in a Frequency Detection or Edge

Detection mode.

Counter/Delay macrocell has an initial value, which define its initial value after GPAK is powered up. It is possible to select initial

Low or initial High, as well as initial value defined by a Delay In signal.

For example, in case initial LOW option is used, the rising edge delay will start operation.

For timing diagrams refer to Section 8.2

.

Note: After two DFF – counters initialize with counter data = 0 after POR.

Initial state = 1 – counters initialize with counter data = 0 after POR.

Initial state = 0 And After two DFF is bypass – counters initialize with counter data after POR.

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2

Three of eight macrocells can have their current count value read via I C (CNT0, CNT2, and CNT4). However, it is possible to

2

change the counter data (value counter starts operating from) for any macrocell using I C write commands. In this mode, it is

possible to load count data immediately (after two DFF) or after counter ends counting. See Section 15.7.1 for further details.

8.1.1 3-Bit LUT or 8-Bit CNT/DLY Block Diagrams

register [1351] DFF or Latch Select

register [1350] Output Select (Q or nQ)

From Connection

Matrix Output [36]

register [1349] (nRST or nSET) from

matrix Output

IN2

IN1

IN0

register [1348] DFF Initial Polarity Select

S0

S1

3-bit LUT7

S0

S1

OUT

LUT Truth

Table

From Connection

Matrix Output [35]

To Connection

S0

S1

S0

S1

Matrix Input [40]

8-bits NVM

registers [1351:1344]

S1

DFF

Registers

D

From Connection

Matrix Output [34]

S0

S1

S0

S1

^nRST/nSETDFF10

Q/nQ

CLK

register [1339]

LUT/DFF Sel

registers [1341:1340],

registers [1338:1337]

registers [1367:1360]

Mode Sel

CNT

Data

ext_CLK

To Connection

Matrix Input [29]

0

S0

OUT

CNT/DLY1

S0

S1

S2

S1

S2

S3

DLY_IN/CNT Reset

Config

Data

0

registers [1359:1352],

registers [1343:1342], [1368]

S3

Figure 29: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT7/DFF10, CNT/DLY1)

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register [1383] DFF or Latch Select

register [1382] Output Select (Q or nQ)

register [1381] (nRST or nSET) from

matrix Output

From Connection

Matrix Output [39]

IN2

register [1380] DFF Initial Polarity Select

S0

S1

3-bit LUT8

S0

S1

OUT

IN1

IN0

LUT Truth

Table

From Connection

Matrix Output [38]

To Connection

S0

S1

S0

S1

Matrix Input [41]

8-bits NVM

registers [1383:1376]

S1

DFF

Registers

D

From Connection

Matrix Output [37]

S0

S1

S0

S1

nRST/nSET

CLK

DFF11 Q/nQ

register [1394]

LUT/DFF Sel

registers [1407:1400]

registers [1375:1372]

Mode Sel

CNT

Data

ext_CLK

To Connection

Matrix Input [33]

0

S0

OUT

CNT/DLY2

S0

S1

S2

S1

S2

S3

DLY_IN/CNT Reset

Config

Data

0

S3

registers [1395], [1393:1384]

Figure 30: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT8/DFF11, CNT/DLY2)

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register [1423] DFF or Latch Select

register [1422] Output Select (Q or nQ)

register [1421] (nRST or nSET) from

matrix Output

From Connection

Matrix Output [42]

IN2

register [1420] DFF Initial Polarity Select

S0

S1

3-bit LUT9

S0

S1

OUT

IN1

IN0

LUT Truth

Table

From Connection

Matrix Output [41]

To Connection

S0

S1

S0

S1

Matrix Input [42]

8-bits NVM

registers [1423:1416]

S1

DFF

Registers

D

From Connection

Matrix Output [40]

S0

S1

S0

S1

nRST/nSET

CLK

DFF12

Q/nQ

register [1411]

LUT/DFF Sel

registers [1413:1412],

registers [1410:1409]

registers [1439:1432]

Mode Sel

CNT

Data

ext_CLK

To Connection

Matrix Input [34]

0

S0

OUT

CNT/DLY3

S0

S1

S2

S1

S2

S3

DLY_IN/CNT Reset

Config

Data

0

S3

registers [1440], [1431:1424],

registers [1415:1414]

Figure 31: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT9/DFF12, CNT/DLY3)

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register [1455] DFF or Latch Select

register [1454] Output Select (Q or nQ)

register [1453] (nRST or nSET) from

matrix Output

From Connection

Matrix Output [45]

IN2

register [1452] DFF Initial Polarity Select

S0

3-bit LUT10

S0

S1

OUT

IN1

IN0

S1

LUT Truth

Table

From Connection

Matrix Output [44]

To Connection

S0

S1

S0

S1

Matrix Input [43]

8-bits NVM

registers [1455:1448]

S1

DFF

Registers

D

From Connection

Matrix Output [43]

S0

S1

S0

S1

nRST/nSET

CLK

DFF13

Q/nQ

register [1466]

LUT/DFF Sel

registers [1479:1472]

registers [1447:1444]

Mode Sel

CNT

Data

ext_CLK

To Connection

Matrix Input [35]

0

S0

OUT

CNT/DLY4

DLY_IN/CNT Reset

S0

S1

S2

S1

S2

S3

Config

Data

0

S3

registers [1467], [1465:1456]

Figure 32: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT10/DFF13, CNT/DLY4)

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register [1495] DFF or Latch Select

register [1494] Output Select (Q or nQ)

register [1493] (nRST or nSET) from

matrix Output

From Connection

Matrix Output [48]

register [1492] DFF Initial Polarity Select

IN2

S0

3-bit LUT11

S0

S1

OUT

IN1

IN0

S1

LUT Truth

Table

From Connection

Matrix Output [47]

To Connection

S0

S1

S0

S1

Matrix Input [44]

8-bits NVM

registers [1495:1488]

S1

DFF

Registers

D

From Connection

Matrix Output [46]

S0

S1

S0

S1

nRST/nSET

CLK

DFF14

Q/nQ

register [1483]

LUT/DFF Sel

registers [1485:1484],

registers [1482:1481]

registers [1511:1504]

Mode Sel

CNT

Data

ext_CLK

To Connection

Matrix Input [36]

0

S0

OUT

CNT/DLY5

DLY_IN/CNT Reset

S0

S1

S2

S1

S2

S3

Config

Data

0

S3

registers [1512], [1503:1496],

registers [1487:1486]

Figure 33: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT11/DFF14, CNT/DLY5)

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register [1527] DFF or Latch Select

register [1526] Output Select (Q or nQ)

register [1525] (nRST or nSET) from

matrix Output

From Connection

Matrix Output [51]

register [1524] DFF Initial Polarity Select

IN2

S0

3-bit LUT12

S0

S1

OUT

IN1

IN0

S1

LUT Truth

Table

From Connection

Matrix Output [50]

To Connection

S0

S1

S0

S1

Matrix Input [45]

8-bits NVM

registers [1527:1520]

S1

DFF

Registers

D

From Connection

Matrix Output [49]

S0

S1

S0

S1

nRST/nSET

CLK

DFF15

Q/nQ

register [1538]

LUT/DFF Sel

registers [1551:1544]

registers [1519:1516]

Mode Sel

CNT

Data

ext_CLK

To Connection

Matrix Input [37]

0

S0

OUT

CNT/DLY6

DLY_IN/CNT Reset

S0

S1

S2

S1

S2

S3

Config

Data

0

S3

registers [1539], [1537:1528]

Figure 34: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT12/DFF15, CNT/DLY6)

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register [1567] DFF or Latch Select

register [1566] Output Select (Q or nQ)

register [1565] (nRST or nSET) from

matrix Output

From Connection

Matrix Output [54]

IN2

register [1564] DFF Initial Polarity Select

S0

3-bit LUT13

S0

S1

OUT

IN1

IN0

S1

LUT Truth

Table

From Connection

Matrix Output [53]

To Connection

S0

S1

S0

S1

Matrix Input [46]

8-bits NVM

registers [1567:1560]

S1

DFF

Registers

D

From Connection

Matrix Output [52]

S0

S1

S0

S1

nRST/nSET

CLK

DFF16

Q/nQ

register [1556]

LUT/DFF Sel

registers [1591:1584]

registers [1555:1552]

Mode Sel

CNT

Data

ext_CLK

To Connection

Matrix Input [38]

0

S0

OUT

CNT/DLY7

S0

S1

S2

S1

S2

S3

DLY_IN/CNT Reset

Config

Data

0

S3

registers [1577:1568], [1557]

Figure 35: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT13/DFF16, CNT/DLY7)

As shown in Figures 24 to 30 there is a possibility to use LUT/DFF and CNT/DLY simultaneously.

Note: It is not possible to use LUT and DFF at once, one of these macrocells must be selected.



Case 1. LUT/DFF in front of CNT/DLY. Three input signals from the connection matrix go to previously selected LUT or DFF's

inputs and produce a single output which goes to a CND/DLY input. In its turn Counter/Delay's output goes back to the matrix.

Case 2. CNT/DLY in front of LUT/DFF. Two input signals from the connection matrix go to CND/DLY's inputs (IN and CLK). Its

output signal can be connected to any input of previously selected LUT or DFF, after which the signal goes back to the matrix.

Case 3. Single LUT/DFF or CNT/DLY. Also, it is possible to use a standalone LUT/DFF or CNT/DLY. In this case, all inputs

and output of the macrocell are connected to the matrix.

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8.1.2 3-Bit LUT or CNT/DLYs Used as 3-Bit LUTs

Table 39: 3-bit LUT7 Truth Table

Table 43: 3-bit LUT11 Truth Table

IN2

0

IN1

0

IN0

0

OUT

IN2

0

IN1

0

IN0

0

OUT

register [1344]

register [1345]

register [1346]

register [1347]

register [1348]

register [1349]

register [1350]

register [1351]

LSB

register [1488]

register [1489]

register [1490]

register [1491]

register [1492]

register [1493]

register [1494]

register [1495]

LSB

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

MSB

LSB

1

MSB

LSB

Table 40: 3-bit LUT8 Truth Table

Table 44: 3-bit LUT12 Truth Table

IN2

0

IN1

0

IN0

0

OUT

IN2

0

IN1

0

IN0

0

OUT

register [1376]

register [1377]

register [1378]

register [1379]

register [1380]

register [1381]

register [1382]

register [1383]

register [1520]

register [1521]

register [1522]

register [1523]

register [1524]

register [1525]

register [1526]

register [1527]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

MSB

LSB

1

MSB

LSB

Table 41: 3-bit LUT9 Truth Table

Table 45: 3-bit LUT13 Truth Table

IN2

0

IN1

0

IN0

0

OUT

IN2

0

IN1

0

IN0

0

OUT

register [1416]

register [1417]

register [1418]

register [1419]

register [1420]

register [1421]

register [1422]

register [1423]

register [1560]

register [1561]

register [1562]

register [1563]

register [1564]

register [1565]

register [1566]

register [1567]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

MSB

LSB

1

MSB

Table 42: 3-bit LUT10 Truth Table

IN2

0

IN1

0

IN0

0

OUT

register [1448]

register [1449]

register [1450]

register [1451]

register [1452]

register [1453]

register [1454]

register [1455]

0

1

0

1

0

1

0

1

0

1

0

1

MSB

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Each macrocell, when programmed for a LUT function, uses a 8-bit register to define their output function:

3-Bit LUT7 is defined by registers [1351:1344]

3-Bit LUT8 is defined by registers [1383:1376]

3-Bit LUT9 is defined by registers [1423:1416]

3-Bit LUT10 is defined by registers [1455:1448]

3-Bit LUT11 is defined by registers [1495:1488]

3-Bit LUT12 is defined by registers [1527:1520]

3-Bit LUT13 is defined by registers [1567:1560]

8.2 CNT/DLY/FSM TIMING DIAGRAMS

8.2.1 Delay Mode CNT/DLY0 to CNT/DLY7

Delay In

Asynchronous delay variable

OSC: force power-on

(always running)

Delay Output

delay = period x (counter data + 1) + variable

variable is from 0 to 1 clock period

delay = period x (counter data + 1) + variable

variable is from 0 to 1 clock period

Delay In

offset

OSC: auto power-on

(powers up from delay in)

Delay Output

delay = offset + period x (counter data + 1)

See offset in table 11

delay = offset + period x (counter data + 1)

See offset in table 11

Figure 36: Delay Mode Timing Diagram, Edge Select: Both, Counter Data: 3

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The macrocell shifts the respective edge to a set time and restarts by appropriate edge. It works as a filter if the input signal is

shorter than the delay time.

Delay time

One-Shot/Freq. DET/Delay IN

t

Delay time

Delay Function

Rising Edge Detection

t

Delay Function

Falling Edge Detection

t

Delay Function

Both Edge Detection

t

Figure 37: Delay Mode Timing Diagram for Different Edge Select Modes

8.2.2 Count Mode (Count Data: 3), Counter Reset (Rising Edge Detect) CNT/DLY0 to CNT/DLY7

RESET_IN

CLK

Counter OUT

4 CLK period pulse

Count start in first rising edge CLK

Figure 38: Counter Mode Timing Diagram without Two DFFs Synced Up

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

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RESET_IN

CLK

Counter OUT

4 CLK period pulse

Count start in 0 CLK after reset

Figure 39: Counter Mode Timing Diagram with Two DFFs Synced Up

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

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8.2.3 One-Shot Mode CNT/DLY0 to CNT/DLY7

This macrocell will generate a pulse whenever a selected edge is detected on its input. Register bits set the edge selection. The

pulse width determines by counter data and clock selection properties.

The output pulse polarity (non-inverted or inverted) is selected by register bit. Any incoming edges will be ignored during the pulse

width generation. The following diagram shows one-shot function for non-inverted output.

Delay time

One-Shot/Freq. DET/Delay IN

t

Delay time

One-Shot Function

Rising Edge Detection

t

One-Shot Function

Falling Edge Detection

t

One-Shot Function

Both Edge Detection

t

Figure 40: One-Shot Function Timing Diagram

This macrocell generates a high level pulse with a set width (defined by counter data) when detecting the respective edge. It does

not restart while pulse is high.

8.2.4 Frequency Detection Mode CNT/DLY0 to CNT/DLY7

Rising Edge: The output goes high if the time between two successive edges is less than the delay. The output goes low if the

second rising edge has not come after the last rising edge in specified time.

Falling Edge: The output goes high if the time between two falling edges is less than the set time. The output goes low if the

second falling edge has not come after the last falling edge in specified time.

Both Edge: The output goes high if the time between the rising and falling edges is less than the set time, which is equivalent to

the length of the pulse. The output goes low if after the last rising/falling edge and specified time, the second edge has not come.

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

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Delay time

One-Shot/Freq. DET/Delay IN

t

Delay time

Frequency Detector Function

Rising Edge Detection

Frequency Detector Function

Falling Edge Detection

t

Frequency Detector Function

Both Edge Detection

Figure 41: Frequency Detection Mode Timing Diagram

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8.2.5 Edge Detection Mode CNT/DLY1 to CNT/DLY7

The macrocell generates high level short pulse when detecting the respective edge. See Table 12.

Delay time

One-Shot/Freq. DET/Delay IN

t

Edge Detector Function

Rising Edge Detection

Edge Detector Function

Falling Edge Detection

t

Edge Detector Function

Both Edge Detection

Figure 42: Edge Detection Mode Timing Diagram

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8.2.6 Delayed Edge Detection Mode CNT/DLY0 to CNT/DLY7

In Delayed Edge Detection Mode, High level short pulses are generated on the macrocell output after the configured delay time,

if the corresponding edge was detected on the input.

If the input signal is changed during the set delay time, the pulse will not be generated. See Figure 43.

Delay time

One-Shot/Freq. DET/Delay IN

t

Delay time

Delayed Edge Detector Function

Rising Edge Detection

Delayed Edge Detector Function

Falling Edge Detection

t

Delayed Edge Detector Function

Both Edge Detection

Figure 43: Delayed Edge Detection Mode Timing Diagram

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8.2.7 CNT/FSM Mode CNT/DLY0

RESET IN

KEEP

COUNT END

CLK

3

2

1

0

3

2

1

0

3

2

1

3

2

1

0

Q

Note: Q = current counter value

Figure 44: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP = 0) for Counter Data = 3

SET IN

KEEP

COUNT END

CLK

2

1

0

3

2

1

0

3

2

1

2

1

0

3

Q

Note: Q = current counter value

Figure 45: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced On, UP = 0) for Counter Data = 3

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RESETI N

KEEP

COUNT END

CLK

65535

65533 65534

4

5

6

7

8

9

3

4

5

1

2

3

4

0

Q

Note: Q = current counter value

Figure 46: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP = 1) for Counter Data = 3

SET IN

KEEP

COUNT END

CLK

65533 65534 65535

8

9

10 11 12

3

4

5

3

4

5

4

5

6

7

3

Q

Note: Q = current counter value

Figure 47: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced On, UP = 1) for Counter Data = 3

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8.2.8 Difference in Counter Value for Counter, Delay, One-Shot, and Frequency Detect Modes

There is a difference in counter value for Counter and Delay/One-Shot/Frequency Detect modes. The counter value is shifted for

two rising edges of the clock signal in Delay/One-Shot/Frequency Detect modes compared to Counter mode. See Figure 48.

One-Shot/Freq. SET/Delay IN

CLK

CNT Out

3

2

1

0

3

CNT Data

2

DLY Out

3

2

Delay Data

1

3

One-Shot Out

One-Shot Data

3

2

3

1

3

Figure 48: Counter Value, Counter Data = 3

8.3 4-BIT LUT OR DFF/LATCH WITH 16-BIT COUNTER/DELAY MACROCELL

There is one macrocell that can serve as either 4-bit LUT/D Flip-Flop or as 16-bit Counter/Delay.

When used to implement LUT function, the 4-bit LUT takes in four input signals from the Connection Matrix and produces a single

output, which goes back into the Connection Matrix or can be connected to CNT/DLY’s input or LUT/DFF’s input.

When used to implement D Flip-Flop function, the two input signals from the connection matrix go to the data (D) and clock (CLK)

inputs for the Flip-Flop, with the output going back to the connection matrix.

When used to implement 16-Bit Counter/Delay function, two of the four input signals from the connection matrix go to the external

clock (EXT_CLK) and reset (DLY_IN/CNT Reset) for the Counter/Delay, with the output going back to the connection matrix.

This macrocell has an optional Finite State Machine (FSM) function. There are two additional matrix inputs for Up and Keep to

support FSM functionality.

This macrocell can also operate in a one-shot mode, which will generate an output pulse of user-defined width.

This macrocell can also operate in a frequency detection.

2

This macrocell can have its active count value read via I C. See Section 15.7.1 for further details.

Note: After two DFF – counters initialize with counter data = 0 after POR.

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Initial state = 1 – counters initialize with counter data = 0 after POR.

Initial state = 0 And After two DFF is bypass – counters initialize with counter data after POR.

8.3.1 4-Bit LUT or 16-Bit CNT/DLY Block Diagram

register [1303] DFF or Latch Select

register [1302] Output Select (Q or nQ)

register [1301] DFF Initial Polarity Select

CMO* [33]

CMO* [32]

CMO*[31]

CMO* [30]

IN3

S0

S1

S0

S1

IN2

IN1

0

LUT4_0

S0

S1

S0

S1

S0

0

OUT

IN0

LUT Truth

Table

S0

S1

To Connection

S0

S1

S0

Matrix Input [39]

registers [1286:1285],

registers [1281:1280]

16-bits NVM

1

registers [1303:1288]

S1

DFF

Registers

D

S0

S1

S0

S1

S0

nSET

Q/nQ

DFF9

1

nRST

CLK

registers [1286:1285]

LUT/DFF Sel

register [1282]

registers [1284:1283],

registers [1281:1280]

registers [1335:1320]

S0

0

S1

S2

S3

CMO* [32]

CMO* [31]

S0

S1

CNT

Data

ext_CLK

0

S0

S1

S2

S3

CMO* [33]

S0

S1

S2

S3

To Connection

Matrix Input [47]

CMO* [32]

CMO* [31]

CMO* [30]

CMO* [31]

OUT

CMO*[32]

CMO* [33]

CNT/DLY0

DLY_IN/CNT Reset

S1

S0

registers

[1284:1283]

registers

[1281:1280]

0

KEEP

UP

S1

S0

FSM

Config

Data

Note: CMO - Connection Matrix Output

0

registers [1314:1304],

register [1287]

registers [1281:1280]

Figure 49: 4-bit LUT0 or CNT/DLY0

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

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8.3.2 4-Bit LUT or 16-Bit Counter/Delay Macrocells Used as 4-Bit LUTs

Table 46: 4-bit LUT0 Truth Table

IN3

0

IN2

0

IN1

0

IN0

0

OUT

register [1288]

register [1289]

register [1290]

register [1291]

register [1292]

register [1293]

register [1294]

register [1295]

register [1296]

register [1297]

register [1298]

register [1299]

register [1300]

register [1301]

register [1302]

LSB

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

register [1303] MSB

This macrocell, when programmed for a LUT function, uses a 16-bit register to define their output function:

4-Bit LUT0 is defined by registers [1303:1288]

Table 47: 4-bit LUT Standard Digital Functions

Function

AND-4

MSB

LSB

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

NAND-4

OR-4

NOR-4

XOR-4

XNOR-4

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8.4 WAKE AND SLEEP CONTROLLER

The SLG46827-A has a Wake and Sleep (WS) function forACMP0H andACMP1H. The macrocell CNT/DLY0 can be reconfigured

for this purpose registers [1305:1304] = 11 and register [1316] = 1. The WS serves for power saving, it allows to switch on and

off selected ACMPs on selected bit of 16-bit counter

.

Power Control

From Connection Matrix Output [58] for 2 kHz OSC0.

WS Controller

OSC0

CNT0_out

cnt_end

CNT

To Connection Matrix Input [47]

ck

CK_OSC

Divider

Analog Control Block

ACMPxH WS EN [1:0]

register [1078], register [1070]

2

bg/regulator

pd

From Connection

Matrix Output [63:62]

WS_out

WS_PD

(from OSC PD)

ACMPxH_PD

2

WS_out

WS_PD to WS out

state selection register [1315]

registers [1311:1308]

WS clock freq. selection

registers [1335:1320]

WS ratio control data

ACMPxH

register [1079]

WS mode: normal or short wake

ACMPxH OUT

+

-

2

0

1

Note: WS_PD is High at OSC0 power down

2

To Connection

Matrix Input

[57:56]

ACMPxH_PD

WS_out

nRST

BG/Analog_Good

Figure 50: Wake and Sleep Controller

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

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time between Reset goes low

and 1st WS clock rsing edge

Force Wake

CNT_RST

(From Connection Matrix)

ACMP_PD is High

(From Connection Matrix)

CNT0_out

(To Connection Matrix)

WS_out

(internal signal)

Data is latched

BG/Analog_Good

(internal signal)

Sleep Mode

ACMP Latches Last Data

Normal ACMP

Operation

ACMP follows input

Sleep Mode

ACMP Latches New Data

Normal ACMP

Sleep Mode

ACMP Latches

New Data

Operation

ACMP follows input

BG/Analog

Startup time*

BG/Analog

Startup time*

Note: CNT0_out is a delayed WS_out signal for 1us to make sure the data is correct during LATCH.

Figure 51: Wake and Sleep Timing Diagram, Normal Wake Mode, Counter Reset is Used

time between Reset goes low

and 1st WS clock rising edge

Force Wake

CNT_RST

(From Connection Matrix)

ACMP_PD is High

(From Connection Matrix)

CNT0_out

(To Connection Matrix)

WS_out

(internal signal)

Data is latched

BG/Analog_Good

(internal signal)

Sleep Mode

ACMP Latches Last Data

Sleep Mode

ACMP Latches New Data

Normal ACMP

Operation for short time

ACMP follows input

Sleep Mode

ACMP Latches

New Data

Normal ACMP

Operation for short time

ACMP follows input

BG/Analog

Startup time*

BG/Analog

Startup time*

Note: CNT0_out is a delayed WS_out signal for 1us to make sure the data is correct during LATCH.

Figure 52: Wake and Sleep Timing Diagram, Short Wake Mode, Counter Reset is Used

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

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time between Reset goes low

and 1st WS clock rising edge

Force Sleep

CNT_SET

(From Connection Matrix)

ACMP_PD is High

(From Connection Matrix)

CNT0_out

(To Connection Matrix)

WS_out

(internal signal)

Data is latched

BG/Analog_Good

(internal signal)

Sleep Mode

ACMP Latches Last Data

Normal ACMP

Operation

ACMP follows input

Sleep Mode

ACMP Latches New Data

BG/Analog

Startup time*

Note: CNT0_out is a delayed WS_out signal for 1 us to make sure the data is correct during LATCH.

Figure 53: Wake and Sleep Timing Diagram, Normal Wake Mode, Counter Set is Used

time between Reset goes low

and 1st WS clock rising edge

Force Sleep

CNT_RST

(From Connection Matrix)

ACMP_PD is High

(From Connection Matrix)

CNT0_out

(To Connection Matrix)

WS_out

(internal signal)

Data is latched

BG/Analog_Good

(internal signal)

Sleep Mode

ACMP Latches New Data

ACMP Latches Last Data

Normal ACMP

Operation for short time

ACMP follows input

BG/Analog

Startup time*

Note: CNT0_out is a delayed WS_out signal for 1us to make sure the data is correct during LATCH.

Figure 54: Wake and Sleep Timing Diagram, Short Wake Mode, Counter Set is Used

Note: If low power BG is powered on/off by WS, the wake time should be longer than 2.1 ms. The BG/analog start up time will

take maximal 2 ms. If low power BG is always on, OSC0 period is longer than required wake time. The short wake mode can be

used to reduce the current consumption.

To use any ACMPxH under WS controller, the following settings must be done:



ACMPxH Power Up Input from matrix = 1 (for each ACMPxH separately);

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

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

CNT/DLY0 must be set to Wake and Sleep Controller function (for all ACMPxH);

Register WS → enable (for each ACMPxH separately);

CNT/DLY0 set/reset input = 0 (for all ACMPxH).

OSC0 is used to clock WS. The user can select a period of time while the ACMPxH is sleeping in a range of 1 - 65535 clock

cycles. Before they are sent to sleep, their outputs are latched, so the ACMPs remain their state (High or Low) while sleeping.

WS controller has the following settings:



Wake and Sleep Output State (High/Low)

If OSC is powered off (Power-down option is selected; Power-down input = 1) and Wake and Sleep Output State = High, the

ACMPxH is continuously on.

If OSC is powered off (Power-down option is selected; Power-down input = 1) and Wake and Sleep Output State = Low, the

ACMPxH is continuously off.

Both cases WS function is turned off.



Counter Data (Range: 1 to 65535)

User can select wake and sleep ratio of the ACMP; counter data = sleep time, one clock = wake time.

Q mode - defines the state of WS counter data when Set/Reset signal appears Reset - when active signal appears, the WS

counter will reset to zero and High level signal on its output will turn on the ACMPs. When Reset signal goes out, the WS

counter will go Low and turn off the ACMPxH until the counter counts up to the end. Set - when active signal appears, the WS

counter will stop and Low level signal on its output will turn off the ACMPxH. When Set signal goes out, the WS counter will go

on counting and High level signal will turn on the ACMPxH while counter is counting up to the end.

Note: The OSC0 matrix power-down to control ACMP WS is not supported for short wait time option.



Edge Select defines the edge for Q mode

High level Set/Reset - switches mode Set/Reset when level is High

Note: Q mode operates only in case of "High Level Set/Reset”.



Wake time selection - time required for wake signal to turn the ACMPxH on

Normal Wake Time - when WS signal is High, it takes BG/analog start up time to turn the ACMPs on. They will stay on until

WS signal is Low again. Wake time is one clock period. It should be longer than BG turn on time and minimal required com

paring time of the ACMP.

-

Short Wake Time - when WS signal is High, it takes BG/analog start up time to turn the ACMPs on. They will stay on for 1 µs

and turn off regardless of WS signal. The WS signal width does not matter.

Keep - pauses counting while Keep = 1



Up - reverses counting

If Up = 1, CNT is counting up from user selected value to 65535.

If Up = 0, CNT is counting down from user selected value to 0.

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9

Analog Comparators

There are four General Purpose Rail-to-Rail Analog Comparator (ACMP) macrocells in the SLG46827-A. In order for the ACMP

cells to be used in a GreenPAK design, the power up signals (ACMP0H PWR UP, ACMP1H PWR UP, ACMP2L PWR UP, and

ACMP3L PWR UP) need to be active. By connecting to signals coming from the Connection Matrix, it is possible to have each

ACMP be on continuously, off continuously, or switched on periodically based on a digital signal coming from the Connection

Matrix. When ACMP is powered down, output is low.

Two of the four General Purpose Rail-to-Rail Analog Comparators are optimized for high speed operation (ACMP0H and

ACMP1H), and two of the four are optimized for low power operation (ACMP2L and ACMP3L).

Each of the ACMP cells has a positive input signal that can be provided by a variety of external sources, and can also have a

selectable gain stage before connection to the analog comparator. Each of the ACMP cells has a negative input signal that is

either created from an internal Vref or provided by way of the external sources.

PWR UP = 1 → ACMP is powered up.

PWR UP = 0 → ACMP is powered down.

During power-up, the ACMP output will remain LOW, and then become valid 51.4 μs (max), after power up signal goes high for

ACMP0H and ACMP1H, and become valid 326.6 μs (max), after power up signal goes high for ACMP2L and ACMP3L. Input bias

current < 1 nA (typ). The Gain divider is unbuffered and consists of 1 MΩ resistors. IN- voltage range: 0 to 2.016 V.

Each High Speed ACMP (ACMP0H and ACMP1H) has an optional Rail-to-Rail Input Buffer, which can be used along with the

Gain divider to increase ACMP input resistance. However, Input buffer will increase an input offset voltage.

Each cell also has a hysteresis selection, to offer hysteresis of (0, 32, 64, 192) mV. The hysteresis option is available when using

an internal Vref only.

The ACMP0H has an additional option of connecting an internal 100 μA current source to its positive input, register [1071]. It is

also possible to connect the 100 μA current source to each next ACMP via an internal analog MUX.

ACMP0H IN+ options are IO14, V internal 100 μA current source

D,

ACMP1H IN+ options are IO13, ACMP0H IN+ MUX output

ACMP2L IN+ options are IO12, ACMP0H IN+ MUX output, ACMP1H IN+ MUX output

ACMP3L IN+ options are IO11, ACMP2L IN+ MUX output, Temp Sensor OUT

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

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9.1 ACMP0H BLOCK DIAGRAM

to ACMP1H, ACMP2L, ACMP3L’s

MUX input

registers [1065:1064]

Hysteresis

Selection

registers [1097:1096]

ACMP

Ready

00

IO14: ACMP0H(+)

Selectable

Gain

+

-

01

10

To Connection

Matrix Input [56]

0

1

Internal VDD (2.3V to 5.5 V)

pdb

Vref

Latch

HighSpeed

ACMP

register [1169]; register [1067]

W/S Control

register [1070]

Off after

1 µs

Ext. VREF (IO1)

111111

From Connection

Matrix Output [35]

111110-

000000

Internal

Vref

registers [1103:1098]

Figure 55: ACMP0H Block Diagram

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9.2 ACMP1H BLOCK DIAGRAM

to ACMP2L’s MUX input

registers [1075:1074]

Hysteresis

Selection

registers [1105:1104]

ACMP

Ready

00

IO13: ACMP1H(+)

Selectable

Gain

+

-

01

10

To Connection

Matrix Input [57]

0

1

ACMP0H IN+ MUX Output

pdb

Vref

Latch

HighSpeed

ACMP

register [1072]; register [1076]

W/S Control

register [1078]

Off after

1 µs

Ext. VREF (IO1)

111111

From Connection

Matrix Output [35]

111110-

000000

Internal

Vref

registers [1111:1106]

Figure 56: ACMP1H Block Diagram

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9.3 ACMP2L BLOCK DIAGRAM

registers [1083:1082]

Hysteresis

Selection

registers [1113:1112]

IO12: ACMP2L(+)

ACMP

Ready

00

To Connection

Matrix Input [58]

from ACMP0H’s MUX output

Selectable

Gain

+

01

from ACMP1H’s MUX output

pdb

10

Vref

-

Low Power

ACMP

registers [1081:1080]

Off after

1 µs

Ext. VREF (IO1)

111111

From Connection

Matrix Output [37]

Low

Power

Internal

Vref

111110-

000000

registers [1119:1114]

Figure 57: ACMP2L Block Diagram

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

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9.4 ACMP3L BLOCK DIAGRAM

registers [1089:1088]

Hysteresis

Selection

registers [1121:1120]

IO11: ACMP3L(+)

ACMP

Ready

00

To Connection

Matrix Input [59]

ACMP2L IN+ MUX Output

Selectable

Gain

+

01

Temp Sensor

pdb

10

Vref

-

Low Power

ACMP

register [1087]; register [1092]

Off after

1 µs

Ext. VREF (IO1)

111111

From Connection

Matrix Output [38]

Low

Power

Internal

Vref

111110-

000000

Low Power

ACMP

registers [1127:1122]

Figure 58: ACMP3L Block Diagram

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9.5 ACMP TYPICAL PERFORMANCE

3

2.5

2

1.5

High To Low, Overdrive = 10 mV

Low to High, Overdrive = 10 mV

High to Low, Overdrive = 100 mV

Low to High, Overdrive = 100 mV

1

0.5

0

512

1024

1536

Vref (mV)

Figure 59: Typical Propagation Delay vs. Vref for ACMPxH at T = 25 °C, Gain = 1, Buffer - Disabled, Hysteresis = 0

90

High To Low, Overdrive = 10 mV

80

Low to High, Overdrive = 10 mV

High to Low, Overdrive = 100 mV

70

Low to High, Overdrive = 100 mV

60

50

40

30

20

10

0

512

1024

1536

Vref (mV)

Figure 60: Typical Propagation Delay vs. Vref for ACMPxL at T = 25 °C, Gain = 1, Buffer - Disabled, Hysteresis = 0

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40

ACMP0 (T = -40 °C)

ACMP1 (T = -40 °C)

ACMP0 (T = 25 °C)

ACMP1 (T = 25 °C)

ACMP0 (T = 105 °C)

ACMP1 (T = 105 °C)

35

30

25

20

15

10

2.3

2.5

3

3.3

3.6

4

4.5

5

5.5

VDD (V)

Figure 61: ACMPxH Power-On Delay vs. V_DD

ACMP2 (T = -40 °C)

ACMP3 (T = -40 °C)

ACMP2 (T = 25 °C)

ACMP3 (T = 25 °C)

ACMP2 (T = 105 °C)

ACMP3 (T = 105 °C)

210

190

170

150

130

110

90

70

2.3

2.5

3

3.3

3.6

4

4.5

5

5.5

VDD (V)

Figure 62: ACMPxL Power-On Delay vs. V_DD

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10

8

6

4

2

0

32

480

1024

1504

2016

-2

-4

-6

-8

Upper Limit

Lower Limit

Vref (mV)

Figure 63: ACMPxH Input Offset Voltage vs. Vref at T = -40 °C to 105 °C, Input Buffer Disabled

15

10

5

0

32

480

1024

1504

2016

0

-5

-10

-15

-20

Upper Limit

Lower Limit

Upper Limit

-20

-25

Lower Limit

Vref (mV)

Figure 64: ACMPxH Input Offset Voltage vs. Vref at T = -40 °C to 105 °C, Input Buffer Enabled

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10

8

6

4

2

0

32

480

1024

1504

2016

-2

-4

-6

-8

Upper Limit

Lower Limit

Vref (mV)

Figure 65: ACMPxL Input Offset Voltage vs. Vref at T = -40 °C to 105°C

140

120

100

80

60

Max

40

Typical

Min

20

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

Input Voltage (V)

Figure 66: ACMP Input Current Source vs. Input Voltage at T = -40 °C to 105 °C, V_DD= 3.3 V

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10 Programmable Delay/Edge Detector

The SLG46827-A has a programmable time delay logic cell available that can generate a delay that is selectable from one of four

timings (time 2) configured in the GreenPAK Designer. The programmable time delay cell can generate one of four different delay

patterns, rising edge detection, falling edge detection, both edge detection, and both edge delay. These four patterns can be

further modified with the addition of delayed edge detection, which adds an extra unit of delay, as well as glitch rejection during

the delay period. See Figure 68 for further information.

Note: The input signal must be longer than the delay, otherwise it will be filtered out.

registers [1262:1261]

Delay Value Selection

registers [1260:1259]

Edge Mode Selection

To Connection

Matrix Input [28]

Programmable

From Connection Matrix Output [56]

IN

OUT

Delay

Figure 67: Programmable Delay

10.1 PROGRAMMABLE DELAY TIMING DIAGRAM - EDGE DETECTOR OUTPUT

width

IN

time1

Rising Edge Detector

time1

Falling Edge Detector

Edge Detector

Output

Both Edge Detector

Both Edge Delay

time2

time1 is a fixed value

time2 delay value is selected via register

Figure 68: Edge Detector Output

Please refer to Table 12

.

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11 Additional Logic Function. Deglitch Filter

The SLG46827-A has one Deglitch Filter macrocell with inverter function that is connected directly to the Connection Matrix inputs

and outputs. In addition, this macrocell can be configured as an Edge Detector, with the following settings:



Rising Edge Detector

Falling Edge Detector

Both Edge Detector

Both Edge Delay

Filter

R

From Connection Matrix

Output [55]

0

1

C

0

1

To Connection Matrix

Input [27]

Edge

Detector

Logic

registers [1246:1245] register [1243]

register [1244]

Figure 69: Deglitch Filter or Edge Detector

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12 Voltage Reference

12.1 VOLTAGE REFERENCE OVERVIEW

The SLG46827-A has a Voltage Reference (Vref) Macrocell to provide references to the four analog comparators. This macrocell

can supply a user selection of fixed voltage references, or temperature sensor output. The macrocell also has the option to output

reference voltages on IO9 and IO10. See Table 48 for the available selections for each analog comparator. Also, see Figure 70,

which shows the reference output structure.

12.2 VREF SELECTION TABLE

Table 48: Vref Selection Table

SEL[5:0]

0

Vref

0.032

0.064

0.096

0.128

0.16

SEL[5:0]

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

Vref

1.056

1.088

1.12

1

2

3

1.152

1.184

1.216

1.248

1.28

4

5

0.192

0.224

0.256

0.288

0.32

6

7

8

1.312

1.344

1.376

1.408

1.44

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

0.352

0.384

0.416

0.448

0.48

1.472

1.504

1.536

1.568

1.6

0.512

0.544

0.576

0.608

0.64

1.632

1.664

1.696

1.728

1.76

0.672

0.704

0.736

0.768

0.8

1.792

1.824

1.856

1.888

1.92

0.832

0.864

0.896

0.928

0.96

1.952

1.984

2.016

External

0.992

1.024

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12.3 VREF BLOCK DIAGRAM

registers [1103:1098]

External Vref

(IO1)

None

00

01

10

11

ACMP0H_Vref

IO10_aio_en

1

0

OP

pd

registers [1111:1106]

Vref Out_0 (IO10)

ACMP1H_Vref

registers [1130:1129]

register [1137]

Temp Sensor

0

1

From Matrix

Output [60]

register [1138]

None

00

01

10

11

registers [1119:1114]

IO9_aio_en

1

0

OP

pd

Vref Out_1 (IO9)

ACMP2L_Vref

registers [1127:1122]

registers [1133:1132]

ACMP3L_Vref

register [1139]

0

From Matrix

Output [60]

1

register [1140]

Figure 70: Voltage Reference Block Diagram

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12.4 VREF LOAD REGULATION

Note 1 It is not recommended to use Vref connected to external pin without buffer.

Note 2 Vref buffer performance is not guaranteed at V < 2.7 V.

DD

320

310

300

290

280

270

260

250

240

VDD=5.5V

VDD=3.3V

VDD=2.3V

I,ꢀUA

Figure 71: Typical Load Regulation, Vref = 320 mV, T = -40

°

C to +105

°C, Buffer - Enable

650

640

630

620

610

600

590

580

570

560

VDD=5.5V

VDD=3.3V

VDD=2.3V

I,ꢀUA

Figure 72: Typical Load Regulation, Vref = 640 mV, T = -40 °C to +105 °C, Buffer - Enable

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1290

1280

1270

1260

1250

1240

1230

1220

1210

1200

VDD=5.5V

VDD=3.3V

VDD=2.3V

I,ꢀUA

Figure 73: Typical Load Regulation, Vref = 1280 mV, T = -40

°

C to +105

°

C, Buffer - Enable

2020

2010

2000

1990

1980

1970

1960

1950

1940

1930

1920

1910

VDD=5.5V

VDD=3.3V

VDD=2.3V

I,ꢀUA

Figure 74: Typical Load Regulation, Vref = 2016 mV, T = -40 °C to +105 °C, Buffer - Enable

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13 Clocking

13.1 OSCILLATOR GENERAL DESCRIPTION

The SLG46827-A has three internal oscillators to support a variety of applications:



Oscillator0 (2.048 kHz)

Oscillator1 (2.048 MHz)

Oscillator2 (25 MHz)

There are two divider stages for each oscillator that gives the user flexibility for introducing clock signals to connection matrix, as

well as various other Macrocells. The pre-divider (first stage) for Oscillator allows the selection of /1, /2, /4 or /8 to divide down

frequency from the fundamental. The second stage divider has an input of frequency from the pre-divider, and outputs one of

eight different frequencies divided by /1, /2, /3, /4, /8, /12, /24 or /64 on Connection Matrix Input lines [27], [28], and [29]. Please

see Figure 78 for more details on the SLG46827-A clock scheme.

Oscillator2 (25 MHz) has an additional function of 100 ns delayed startup, which can be enabled/disabled by register [1052]. This

function is recommended to use when analog blocks are used along with the Oscillator.

The Matrix Power-down/Force On function allows switching off or force on the oscillator using an external pin. The Matrix Power-

down/Force On (Connection Matrix Output [72], [73], [74]) signal has the highest priority. The OSC operates according to the

Table 49.

Table 49: Oscillator Operation Mode Configuration Settings

OSC Enable

Signal from

CNT/DLY

Register:

Power-Down

or Force On by

Matrix Input

OSC

Operation

Mode

Signal From

Connection

Matrix

Register: Auto

Power-On or

Force On

External Clock

Selection

POR

Macrocells

0

1

X

1

X

OFF

Internal OSC is

OFF, logic is ON

1

0

1

0

1

X

1

X

OFF

ON

CNT/DLY re

quires OSC

-

1

0

X

0

CNT/DLY does

not require OSC

OFF

Note 1 The OSC will run only when any macrocell that uses OSC is powered on.

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13.2 OSCILLATOR0 (2.048 KHZ)

From Connection Matrix

Output [58]

Power-down/Force On

Matrix Output control [1041]

OSC Power Mode

register [1040]

2.048 kHz Pre-divided Clock

PD/ FORCE ON

registers [1044:1043]

OSC0

Auto Power-On

Force Power-On

(2.048 kHz) ^OUT

0

1

DIV /1 /2 /4 /8

0

1

Ext. Clock

Pre-divider

1

/ 2

/ 3

2

3

4

5

6

7

Ext. CLK Sel register [1042]

To Connection Matrix

Input [31]

/ 4

OUT0

/ 8

OUT1

To Connection Matrix

Input [61]

/ 12

/ 24

/ 64

registers [1047:1045]

registers [1061:1059]

Second Stage

Divider

Figure 75: Oscillator0 Block Diagram

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13.3 OSCILLATOR1 (2.048 MHZ)

From Connection Matrix

Output [59]

Power-down/Force On

Matrix Output control [register 1025]

OSC Power Mode

register [1024]

2.048 MHz Pre-divided Clock

PD/ FORCE ON

registers [1028:1027]

OSC1

Auto Power-On

Force Power-On

(2.048 MHz)^OUT

0

1

DIV /1 /2 /4 /8

0

1

Ext. Clock

Pre-divider

1

/ 2

/ 3

2

3

4

5

6

7

Ext. CLK Sel register [1026]

To Connection Matrix

Input [30]

/ 4

OUT0

/ 8

OUT1

To Connection Matrix

Input [60]

/ 12

/ 24

/ 64

registers [1031:1029]

registers [1058:1056]

Second Stage

Divider

Figure 76: Oscillator1 Block Diagram

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13.4 OSCILLATOR2 (25 MHZ)

From Connection Matrix

Output [57]

Power-down/Force On

Matrix Output control register[1033]

OSC Power Mode

register [1032]

25 MHz Pre-divided Clock

PD/ FORCE ON

registers [1036:1035]

OSC2

(25 MHz)

Auto Power-On

Force Power-On

OUT

0

1

Startup delay

DIV /1 /2 /4 /8

0

1

Pre-divider

register [1052]

1

/ 2

/ 3

Ext. Clock

2

3

4

5

6

Ext. CLK Sel [1034]

To Connection Matrix

Input [32]

/ 4

/ 8

/ 12

/ 24

/ 64

7

registers [1039:1037]

Second Stage

Divider

Figure 77: Oscillator2 Block Diagram

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13.5 CNT/DLY CLOCK SCHEME

Each CNT/DLY within Multi-Function macrocell has its own additional clock divider connected to oscillators pre-divider. Available

dividers are:

OSC0/1, OSC0/8, OSC0/64, OSC0/512, OSC0/4096, OSC0/32768, OSC0/262144

OSC1/1, OSC1/8, OSC1/64, OSC1/512

OSC2/1, OSC2/4

[3:0]

0

1

25 MHz Pre-divided clock

Div4

2

Div8

3

4

5

6

7

8

CNT/DLY/

ONESHOT/

FREQ_DET/

2.048 MHz Pre-divided clock

2.048 kHz Pre-divided clock

Div64

Div512

DLY_EDGE_DET

Div8

Div64

CNT overflow

Div512

9

Div4096

Div32768

Div262144

10

11

12

13

14

15

CNT (x-1) overflow

from Connection Matrix Out

(separate for each CNT/DLY macrocell)

CNT0/CNT1/CNT2/CNT3/

CNT4/CNT5/CNT6/CNT7

Figure 78: Clock Scheme

13.6 EXTERNAL CLOCKING

The SLG46827-A supports several ways to use an external, higher accuracy clock as a reference source for internal operations.

13.6.1 IO0 Source for Oscillator0 (2.048 kHz)

When register [1042] is set to 1, an external clocking signal on IO0 will be routed in place of the internal oscillator derived

2.048 kHz clock source. See Figure 75. The high and low limits for frequency that can be selected are 0 MHz and 10 MHz.

13.6.2 IO10 Source for Oscillator1 (2.048 MHz)

When register [1026] is set to 1, an external clocking signal on IO10 will be routed in place of the internal oscillator derived

2.048 MHz clock source. See Figure 76. The high and low limits for frequency that can be selected are 0 MHz and 10 MHz.

13.6.3 IO8 Source for Oscillator2 (25 MHz)

When register [1034] is set to 1, an external clocking signal on IO8 will be routed in place of the internal oscillator derived 25 MHz

clock source. See Figure 77. The external frequency range is 0 MHz to 20 MHz at V = 2.3 V, 0 MHz to 30 MHz at V = 3.3 V,

DD

0 MHz to 50 MHz at V = 5.0 V.

DD

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13.7 OSCILLATORS POWER-ON DELAY

OSC enable

Power-On

Delay

CLK

Figure 79: Oscillator Startup Diagram

Note 1 OSC power mode: “Auto Power-On”.

Note 2 “OSC enable” signal appears when any macrocell that uses OSC is powered on.

1 300

1 200

1 100

1 000

900

800

700

600

500

V_DD(V)

Figure 80: Oscillator0 Maximum Power-On Delay vs. V_DDat T = 25 °C, OSC0 = 2.048 kHz

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580

560

540

520

500

480

460

440

420

400

V_DD(V)

Figure 81: Oscillator1 Maximum Power-On Delay vs. V_DDat T = 25 °C, OSC1 = 2.048 MHz

180

160

140

Start with Delay

Normal Start

120

100

80

60

40

20

0

V_DD(V)

Figure 82: Oscillator2 Maximum Power-On Delay vs. V_DDat T = 25 °C, OSC2 = 25 MHz

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13.8 OSCILLATORS ACCURACY

Note: OSC power setting: Force Power-On; Clock to matrix input - enable; Bandgap: turn on by register - enable.

2.1

2.05

2

1.95

1.9

Fmax @ VDD = 2.5 V to 5 V

Ftyp @ VDD = 3.3 V

Fmin @ VDD = 2.5 V to 5 V

1.85

1.8

T (°C)

Figure 83: Oscillator0 Frequency vs. Temperature, OSC0 = 2.048 kHz

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2.1

2.05

2

Fmax @ VDD = 5 V

Fmax @ VDD = 3.3 V

Fmax @ VDD = 2.5 V

1.95

Ftyp @ VDD = 3.3 V

Fmin @ VDD = 5 V

Fmin @ VDD = 3.3 V

Fmin @ VDD = 2.5 V

1.9

T (°C)

Figure 84: Oscillator1 Frequency vs. Temperature, OSC1 = 2.048 MHz

25.8

25.4

25

24.6

Fmax @ VDD = 5 V

24.2

Fmax @ VDD = 3.3 V

Fmax @ VDD = 2.5 V

Ftyp @ VDD = 3.3 V

23.8

23.4

Fmin @ VDD = 5 V

Fmin @ VDD = 3.3 V

Fmin @ VDD = 2.5 V

T (°C)

Figure 85: Oscillator2 Frequency vs. Temperature, OSC2 = 25 MHz

Note: For more information see Section 3.6.

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Table 50: Oscillator Output Duty Cycle

Second Stage Divider

OSC0

OSC1

OSC2

OSC0

OSC1

OSC2

OSC0

OSC1

OSC2

OSC0

OSC1

OSC2

OSC0

OSC1

OSC2

OSC0

OSC1

OSC2

OSC0

OSC1

OSC0

OSC1

OSC2

Pre-divider

1

2

3

4

8

12

50

24

50

64

50

1

2

4

8

50

60

50

33.3

66

50

11

10

9

2.048 kHz Total Error @ VDD = 2.3 V to 5.5 V

25 MHz Total Error @ VDD = 2.3 V to 5.5 V

2.048 MHz Total Error @ VDD = 2.3 V to 5.5 V

8

7

6

5

4

3

2

1

T (°C)

Figure 86: Oscillators Total Error vs. Temperature

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14 Power-On Reset

The SLG46827-A has a Power-On Reset (POR) macrocell to ensure correct device initialization and operation of all macrocells

in the device. The purpose of the POR circuit is to have consistent behavior and predictable results when the V power is first

DD

ramping to the device, and also while the V is falling during power-down. To accomplish this goal, the POR drives a defined

DD

sequence of internal events that trigger changes to the states of different macrocells inside the device, and finally to the state of

the IOs.

14.1 GENERAL OPERATION

The SLG46827-A is guaranteed to be powered down and non-operational when the V voltage (voltage on PIN20 for TSSOP

DD

package) is less than Power-Off Threshold (see in Table 3.4), but not less than -0.6 V. Another essential condition for the chip to

be powered down is that no voltage higher (Note) than the V voltage is applied to any other PIN. For example, if V voltage

DD

is 0.3 V, applying a voltage higher than 0.3 V to any other PIN is incorrect, and can lead to incorrect or unexpected device behavior.

Note: There is a 0.6 V margin due to forward drop voltage of the ESD protection diodes.

To start the POR sequence in the SLG46827-A, the voltage applied on the V should be higher than the Power-On threshold

DD

(Note). The full operational V range for the SLG46827-A is 2.3 V to 5.5 V. This means that the V voltage must ramp up to

DD

the operational voltage value, but the POR sequence will start earlier, as soon as the V voltage rises to the Power-On threshold.

DD

After the POR sequence has started, the SLG46827-A will have a typical Startup Time (see in Table 3.4) to go through all the

steps in the sequence, and will be ready and completely operational after the POR sequence is complete.

Note: The Power-On threshold is defined in Table 3.4.

To power down the chip, the V voltage should be lower than the operational and to guarantee that chip is powered down, it

DD

should be less than Power-Off Threshold.

All PINs are in high impedance state when the chip is powered down and while the POR sequence is taking place. The last step

in the POR sequence releases the IO structures from the high impedance state, at which time the device is operational. The pin

configuration at this point in time is defined by the design programmed into the chip. Also, as it was mentioned before, the voltage

on PINs can’t be bigger than the V , this rule also applies to the case when the chip is powered on.

DD

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

14.2 POR SEQUENCE

The POR system generates a sequence of signals that enable certain macrocells. The sequence is shown in Figure 87.

V_DD

t

POR_NVM

(reset for NVM)

NVM_ready_out

POR_GPI

(reset for input enable)

POR_LUT

(reset for LUT output)

POR_CORE

(reset for DLY/OSC/DFF

/LATCH/Pipe DLY

POR_OUT

(generate low to high to matrix)

POR_GPO

(reset for output enable)

Figure 87: POR Sequence

As can be seen from Figure 87 after the V has started ramping up and crossed the Power-On threshold, first, the on-chip NVM

DD

memory is reset. Next, the chip reads the data from NVM, and transfers this information to a CMOS LATCH that serves to configure

each macrocell, and the Connection Matrix which routes signals between macrocells. The third stage causes the reset of the input

pins, and then to enable them. After that, the LUTs are reset and become active. After LUTs, the Delay cells, OSCs DFFs,

LATCHES, and Pipe Delay are initialized. Only after all macrocells are initialized, internal POR signal (POR macrocell output)

goes from LOW to HIGH (POR_OUT in Figure 87). The last portion of the device to be initialized is the output pins, which transition

from high impedance to active at this point.

The typical time that takes to complete the POR sequence varies by device type in the GreenPAK family. It also depends on many

environmental factors, such as: slew rate, V value, temperature, and even will vary from chip to chip (process influence).

DD

14.3 MACROCELLS OUTPUT STATES DURING POR SEQUENCE

To have a full picture of SLG46827-A operation during powering and POR sequence, refer to Figure 88 which describes the

macrocell output states during the POR sequence.

First, before the NVM has been reset, all macrocells have their output set to logic LOW (except the output pins which are in high

impedance state). On the next step, some of the macrocells start initialization: input pins output state becomes LOW; LUTs also

output LOW. After that input pins are enabled. Next, only LUTs are configured. Then, all other macrocells are initialized. After

macrocells are initialized, internal POR matrix signal switches from LOW to HIGH. The last are output pins that become active

and determined by the input signals.

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

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V_DD

Guaranteed HIGH before POR_GPI

t

V_DD_out

to matrix

t

Input PIN _out

Determined by External Signal

to matrix

LUT_out

to matrix

Determined by Input signals

t

Programmable Delay_out

to matrix

Determined by Input signals

Starts to detect input edges

t

Determined by initial state

DFF/Latch_out

to matrix

Determined by Input signals

Determined by initial value

settings

t

Delay_out

to matrix

Determined by Input signals

Starts to detect input edges

POR_out

to matrix

Ext. GPO

Tri-state

Determined by input signals

Output State Unpredictable

Figure 88: Internal Macrocell States during POR Sequence

14.3.1 Initialization

All internal macrocells by default have initial low level. Starting from indicated power-up time of 1.52 V to 2.12 V, macrocells in

SLG46827-A are powered on while forced to the reset state. All outputs are in Hi-Z and chip starts loading data from NVM. Then

the reset signal is released for internal macrocells and they start to initialize according to the following sequence:

1. Input pins, Pull-up/down.

2. LUTs.

3. DFFs, Delays/Counters, Pipe Delay, OSCs, ACMPs.

4. POR output to matrix.

5. Output pin corresponds to the internal logic.

The Vref output pin driving signal can precede POR output signal going high by 3

the mentioned power-up sequence is complete.

µs to 5 µs. The POR signal going high indicates

Note: The maximum voltage applied to any pin should not be higher than the V level. There are ESD Diodes between pin →

DD

V

and pin → GND on each pin. Exceeding V results in leakage current on the input pin, and V will be pulled up, following

DD DD

DD

the voltage on the input pin.

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

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14.3.2 Power-Down

V_DD(V)

2 V

1.59 V

0.84 V

1 V Vref Out Signal

1 V

Time

Not guaranteed output state

Figure 89: Power-Down

During power-down, macrocells in SLG46827-A are powered off after V falling down below Power-Off Threshold. Please note

DD

that during a slow rampdown, outputs can possibly switch state.

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2

15 I C Serial Communications Macrocell

15.1 I²C SERIAL COMMUNICATIONS MACROCELL OVERVIEW

In the standard use case for the GreenPAK devices, the configuration choices made by the user are stored as bit settings in the

Non-Volatile Memory (NVM), and this information is transferred at startup time to volatile RAM registers that enable the configu

-

ration of the macrocells. Other RAM registers in the device are responsible for setting the connections in the Connection Matrix

to route signals in the manner most appropriate for the user’s application.

2

The I C Serial Communications Macrocell in this device allows an I C bus Master to read and write this information via a serial

channel directly to the RAM registers, allowing the remote re-configuration of macrocells, and remote changes to signal chains

within the device.

2

An I C bus Master is also able read and write other register bits that are not associated with NVM memory. As an example, the

input lines to the Connection Matrix can be read as digital register bits. These are the signal outputs of each of the macrocells in

2

the device, giving an I C bus Master the capability to remotely read the current value of any macrocell.

The user has the flexibility to control read access and write access via registers bits registers [1795:1792]. See Section 16 for

2

more details on I C read/write memory protection.

15.2 I²C SERIAL COMMUNICATIONS DEVICE ADDRESSING

2

Each command to the I C Serial Communications macrocell begins with a Control Byte. The bits inside this Control Byte are

shown in Figure 90. After the Start bit, the first four bits are a control code. Each bit in a control code can be sourced independently

from the register or by value defined externally by IO5, IO4, IO3, and IO2. The LSB of the control code is defined by the value of

IO2, while the MSB is defined by the value of IO5. The address source (either register bit or PIN) for each bit in the control code

is defined by registers [1623:1620]. This gives the user flexibility on the chip level addressing of this device and other devices on

2

the same I C bus.The default control code is 0001. The Block Address is the next three bits (A10, A9, A8), which will define the

most significant bits in the addressing of the data to be read or written by the command. The last bit in the Control Byte is the R/W

bit, which selects whether a read command or write command is requested, with a “1” selecting for a Read command, and a “0”

selecting for a Write command. This Control Byte will be followed by an Acknowledge bit (ACK), which is sent by this device to

indicate successful communication of the Control Byte data.

2

In the I C-bus specification and user manual, there are two groups of eight addresses (0000 xxx and 1111 xxx) that are reserved

for the special functions, such as a system General Call address. If the user of this device choses to set the Control Code to either

2

“1111” or “0000” in a system with other slave device, please consult the I C-bus specification and user manual to understand the

addressing and implementation of these special functions, to insure reliable operation.

In the read and write command address structure, there are a total of 11 bits of addressing, each pointing to a unique byte of

information, resulting in a total address space of 16K bytes. The valid addresses are shown in the memory map in Figure 100.

With the exception of the Current Address Read command, all commands will have the Control Byte followed by the Word

Address.

Start

bit

Acknowledge

bit

Control Byte

Word Address

A

10

A

9

A

8

A

7

A

0

S

X

R/W ACK

Control

Code

Block

Address

Read/Write bit

Figure 90: Basic Command Structure

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

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15.3 I²C SERIAL GENERAL TIMING

2

General timing characteristics for the I C Serial Communications macrocell are shown in Figure 91. Timing specifications can be

found in the Section 3.4.

t_HIGH

t_F

t_R

t_LOW

SCL

t_{SU STA}

t_{HD DAT}

t_{HD STA}

t_{SU DAT}

t_{SU STO}

SDA IN

t_DH

t_BUF

t_{VD ACK}

ACK 1-bit

SDA OUT

DATA 8-bit

Figure 91: I²C General Timing Characteristics

15.4 I²C SERIAL COMMUNICATIONS COMMANDS

15.4.1 Byte Write Command

Following the Start condition from the Master, the Control Code [4 bits], the Block Address [3 bits], and the R/W bit (set to “0”) are

2

placed onto the I C bus by the Master. After the SLG46827-A sends an Acknowledge bit (ACK), the next byte transmitted by the

Master is the Word Address. The Block Address (A10, A9, A8), combined with the Word Address (A7 through A0), together set

the internal address pointer in the SLG46827-A, where the data byte is to be written. After the SLG46827-A sends another

Acknowledge bit, the Master will transmit the data byte to be written into the addressed memory location. The SLG46827-A again

provides an Acknowledge bit and then the Master generates a Stop condition. The internal write cycle for the data will take place

at the time that the SLG46827-A generates the Acknowledge bit.

2

It is possible to latch all IOs during I C write command to the register configuration data (block address A10, A9, A8 = 000),

register [1602] = 1 - Enable. It means that IOs will remain their state until the write command is done.

Acknowledge

bit

Acknowledge

bit

Start

bit

Acknowledge

bit

Bus Activity

Control Byte

Word Address

Data

A

10

A

9

A

8

A

7

A

0

D

7

D

0

S

X

W

ACK

SDA LINE

P

Control

Code

Block

Address

Stop

bit

R/W bit = 0

Figure 92: Byte Write Command, R/W = 0

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

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15.4.2 Sequential Write Command

The write Control Byte, Word Address, and the first data byte are transmitted to the SLG46827-A in the same way as in a Byte

Write command. However, instead of generating a Stop condition, the Bus Master continues to transmit data bytes to the

SLG46827-A. Each subsequent data byte will increment the internal address counter, and will be written into the next higher byte

in the command addressing. As in the case of the Byte Write command, the internal write cycle will take place at the time that the

SLG46827-A generates the Acknowledge bit.

Acknowledge

bit

Start

bit

Bus Activity

Data (n + 1)

Data (n + x)

Control Byte

Word Address (n)

Data (n)

A

10

A

9

A

8

ACK

P

SDA LINE

S

X

W

ACK

Control

Code

Block

Address

Stop

bit

Write bit

Figure 93: Sequential Write Command

15.4.3 Current Address Read Command

The Current Address Read Command reads from the current pointer address location. The address pointer is incremented at the

first STOP bit following any write control byte. For example, if a Sequential Read command (which contains a write control byte)

reads data up to address n, the address pointer would get incremented to n + 1 upon the STOP of that command. Subsequently,

a Current Address Read that follows would start reading data at n + 1. The Current Address Read Command contains the Control

Byte sent by the Master, with the R/W bit = “1”. The SLG46827-A will issue an Acknowledge bit, and then transmit eight data bits

for the requested byte. The Master will not issue an Acknowledge bit, and follow immediately with a Stop condition.

Start

bit

Acknowledge

bit

Stop

bit

Bus Activity

Control Byte

Data (n)

A

10

A

9

A

8

S

X

R

ACK

SDA LINE

P

Control

Code

Block

Address

No ACK

bit

R/W bit = 1

Figure 94: Current Address Read Command, R/W = 1

15.4.4 Random Read Command

The Random Read command starts with a Control Byte (with R/W bit set to “0”, indicating a write command) and Word Address

to set the internal byte address, followed by a Start bit, and then the Control Byte for the read (exactly the same as the Byte Write

command). The Start bit in the middle of the command will halt the decoding of a Write command, but will set the internal address

counter in preparation for the second half of the command. After the Start bit, the Bus Master issues a second control byte with

the R/W bit set to “1”, after which the SLG46827-A issues an Acknowledge bit, followed by the requested eight data bits.

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

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Acknowledge

Stop

bit

Start

bit

Bus Activity

Data (n)

Control Byte

Word Address (n)

Control Byte

A

10

A

9

A

8

A

10

A

9

A

8

S

ACK

X

R ACK

P

SDA LINE

S

X

W

ACK

Control

Code

Block

Address

Control

Code

Block

Address

No ACK

bit

Write bit

Read bit

Figure 95: Random Read Command

15.4.5 Sequential Read Command

The Sequential Read command is initiated in the same way as a Random Read command, except that once the SLG46827-A

transmits the first data byte, the Bus Master issues an Acknowledge bit as opposed to a Stop condition in a random read. The

Bus Master can continue reading sequential bytes of data, and will terminate the command with a Stop condition.

Acknowledge

Start

bit

Bus Activity

Data (n + 2)

Data (n + x)

Control Byte

Data (n)

Data (n + 1)

A

8

A

10

A

9

ACK

P

SDA LINE

S

X

R

ACK

Control

Code

Block

Address

Stop

bit

No ACK

bit

Read bit

Figure 96: Sequential Read Command

15.4.6 I²C Serial Reset Command

2

If I C serial communication is established with the device, it is possible to reset the device to initial power up conditions, including

configuration of all macrocells, and all connections provided by the Connection Matrix. This is implemented by setting

2

register [1601] I C reset bit to “1”, which causes the device to re-enable the Power-On Reset (POR) sequence, including the

reload of all register data from NVM. During the POR sequence, the outputs of the device will be in tri-state. After the reset has

taken place, the contents of register [1601] will be set to “0” automatically. Figure 97 illustrates the sequence of events for this

reset function.

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

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Acknowledge

bit

Acknowledge

bit

Start

bit

Acknowledge

bit

Bus Activity

Control Byte

Word Address

Data

A

10

A

9

A

8

A

7

A

0

D

7

D

0

S

X

W

ACK

SDA LINE

P

Internal Reset bit

Control

Code

Block

Address

Stop

bit

Write bit

by I²C Stop Signal

Reset-bit register output

DFF output gated by stop signal

Internal POR for core only

Figure 97: Reset Command Timing

15.5 CHIP CONFIGURATION DATA PROTECTION

The SLG46827-A utilizes a scheme that allows a portion or the entire Register and NVM to be inhibited from being read or

written/erased. There are two bytes that define the register and NVM access or change. The first byte RPR defines the 2k register

read and write protection. The second byte NPR defines the 2k NVM data configuration read and write protection. If desired, the

protection lock bit (PRL) can be set so that protection may no longer be modified, thereby making the current protection scheme

permanent. The status of the RPR and NPR can be determined by following a Random Read sequence. Changing the state of

the RPR and NPR is accomplished with a Byte Write sequence with the requirements outlined in this section.

The RPR register is located on H’E0 address, while NPR is located on H’E1 address.

The RPR format is shown in Table 51, and the RPR bit functions are included in Table 52.

Table 51: RPR Format

b7

b6

b5

b4

b3

b2

b1

b0

RPR

RPRB3

RPRB2

RPRB1

RPRB0

Table 52: RPR Bit Function Description

Bit

Name

2k Register

Type

Description

00: 2k register data is unprotected for write;

01: 2k register data is partly protected for write; Please refer to the Table 55.

10: 2k register data is fully protected for write.

RPRB3

RPRB2

RPRB1

RPRB0

R/W*

Write

Selection

Bits

3:2

R/W*

2k Register

Read

Selection

00: 2k register data is unprotected for read;

01: 2k register data is partly protected for read; Please refer to the Table 55.

10: 2k register data is fully protected for read.

1:0

Bits

* Becomes read only after PRL is high. The content is permanently locked for write and erase after PRL is high.

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

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The NPR format is shown in Table 53, and the NPR bit functions are included in Table 54.

Table 53: NPR Format

b7

b6

b5

b4

b3

b2

b1

b0

NPR

Table 54: NPR Bit Function Description

NPRB1

NPRB0

Bit

Name

Type

Description

NPRB1

NPRB0

R/W*

00: 2k NVM Configuration data is unprotected for read and write/erase;

01: 2k NVM Configuration data is fully protected for read;

10: 2k NVM Configuration data is fully protected for write/erase.

11: 2k NVM Configuration data is fully protected for read and write/erase.

2k NVM

Configuration

Selection Bits

1:0

R/W*

* Becomes read only after PRL is high. The content is permanently locked for write and erase after PRL is high.

The protection selection bits allow different levels of protection of the register and NVM Memory Array.

The Protect Lock Bit (PRL) is used to permanently lock (for write and erase) the current state of the RPR and NPR. A Logic 0

indicates that the protection byte can be modified, whereas a Logic 1 indicates the byte has been locked and can no longer be

modified.

In this case it is impossible to erase the whole page E with protection bytes. The PRL is located at E4 address (register [1824]).

15.6 I²C SERIAL COMMAND REGISTER MAP

There are nine read/write protect modes for the design sequence from being corrupted or copied. See Table 55 for details.

Table 55: Read/Write Register Protection Options

Protection Modes Configuration

Partly

Lock

Read &

Lock

Read &

Partly

Lock

Partly

Lock

Read/

Write

Configurations

Partly

Lock

Read

Partly

Lock

Write

Lock

Read/

Write

Lock

Read

Lock

Write

Unlock

Register

Address

Test

Mode

Write

00

01

00

01

10

01

10

00

10

RPR[1:0]

RPR[3:2]

2

I C Byte Write Bit

Masking

R/W

R

W

R

-

C9

C8b'1

C8b'2

7A

(section 15.7.3)

2

I C Serial Reset

Command

(section 15.4.6)

Outputs Latching

2

During I C Write

Connection Matrix

Virtual Inputs

(section 6.3)

Configuration Bits

for All Macrocells

(IOs, ACMPs,

Combination

R/W

W

R

-

W

R

-

Function

Macrocells, etc.)

Macrocells Inputs

Configuration

(Connection Matrix

Outputs)

00~47

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Table 55: Read/Write Register Protection Options(Continued)

Protection Modes Configuration

Partly

Lock

Read &

Lock

Read &

Partly

Lock

Partly

Lock

Read/

Write

Partly

Lock

Read

Partly

Lock

Write

Lock

Read/

Write

Configurations

Lock

Read

Lock

Write

Unlock

Register

Address

Test

Mode

Write

00

01

00

01

10

01

10

00

10

RPR[1:0]

RPR[3:2]

Protection Mode

Selection

R/W

R

R/W

R

E4

Macrocells Output

Values (Connection

Matrix Inputs,

section

R

-

R

-

74~79;7B

7C~7F

Counter Current

Value

R

-

R

-

R

SiliconIdentification

Service Bits

F9b'3~F9

b'2

R

2

I C Control Code

CAb'3~CA

b'0

R/W

W**

R/W

W**

R

R/W

W**

R

Page Erase byte

W**

E3

R/W

W

Allow Read and Write Data

Allow Write Data Only

W**

R

Pages that can be erased are defined by NVM write protection

Allow Read Data Only

-

The Data is protected for Read and Write

Note 1 R/W becomes read only if protection mode selection (lock bit) is set to 1.

Note 2 R/W Readable/writable depend on the "Trim mode enable" bit. If “Trim mode enable” bit value = 1, then trim bits are

enable.

It is possible to read some data from macrocells, such as counter current value, connection matrix, and connection matrix virtual

2

inputs. The I C write will not have any impact on data in case data comes from macrocell output, except Connection Matrix Virtual

Inputs. The silicon identification service bits allows identifying silicon family, its revision, and others.

See Section 18 for detailed information on all registers.

15.7 I²C ADDITIONAL OPTIONS

2

When Output latching during I C write to the register configuration data (block address A10,A9,A8 = 000), register [1602] = 1

allows all PINs output value to be latched while register content is changing. It will protect the output change due to configuration

2

process during I C write in case multiple register bytes are changed. Inputs and internal macrocells retain their status during I C

write.

See Section 18 for detailed information on all registers.

15.7.1 Reading Counter Data via I²C

2

The current count value in three counters in the device can be read via I C. The counters that have this additional functionality

are 16-bit CNT0, and 8-bit counters CNT2 and CNT4.

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15.7.2 I²C Expander

2

In addition to the eight Connection Matrix Virtual Inputs, the SLG46827-A chip has four pins which can be used as an I C

Expander. These four pins are IO0, IO5, IO6, and IO9.

2

Each of these pins can be used as an I C Expander output or used as a normal pin. Also, each of these four expander outputs

have initial state settings which are specified in registers [1599:1592].

15.7.3 I²C Byte Write Bit Masking

2

The I C macrocell inside SLG46827-A supports masking of individual bits within a byte that is written to the RAM memory space.

This function is supported across the entire RAM memory space. To implement this function, the user performs a Byte Write

2

Command (see Section 15.4.1 for details) on the I C Byte Write Mask Register (address 0C9H) with the desired bit mask pattern.

This sets a bit mask pattern for the target memory location that will take effect on the next Byte Write Command to this register

2

byte. Any bit in the mask that is set to “1” in the I C Byte Write Mask Register will mask the effect of changing that particular bit

2

in the target register, during the next Byte Write Command. The contents of the I C Byte Write Mask Register are reset (set to

00h) after valid Byte Write Command. If the next command received by the device is not a Byte Write Command, the effect of the

2

bit masking function will be aborted, and the I C Byte Write Mask Register will be reset with no effect. Figure 98 shows an example

of this function.

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User Actions



Byte Write Command, Address = C9h, Data = 11110000b [sets mask bits]

Byte Write Command, Address = 74h, Data = 10101010b [writes data with mask]

Memory Address 74h (original contents)

Mask to choose bit from new

write command

1

0

1

0

Mask to choose bit from

original register contents

Memory Address 74h (new data in write command)

0 1

1

0

1

0

Bit from new write command

Memory Address C9h (mask register)

1

0

Bit from original register

contents

Memory Address 74h (new contents after write command)

1

0

1

0

1

0

Figure 98: Example of I²C Byte Write Bit Masking

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16 Non-Volatile Memory

The SLG46827-A provides 2,048 bits of Serial Electrically Erasable Configuration Register memory that is used for device

configuration. Write protection settings of the device will be permanently disabled once the GreenPAK design is finalized and

enters production.

Key features:



Low-voltage Operation



for Read: VCC = 2.3 V to 5.5 V

for Write: VCC = 2.5 V to 5.5 V



2

I C-Compatible (2-Wire) Serial Interface



100 kHz Standard Mode

400 kHz Fast Mode (FM)



Low Current Consumption



Read Current 0.5 mA max

Page Write Current 3.0 mA max

Chip Erase Current 3.0 mA max

Standby Current (1.0 μA max)



16-byte Page Write Mode

Self-timed Write/Erase Cycle (20 ms max)

Reliability



Endurance: 1,000 write cycles



Data retention: 10 years at 125 °C

16.1 SERIAL NVM WRITE OPERATIONS

Write access to the NVM is possible in development by setting A3, A2, A1, A0 to “0000”, which allows serial write data for a single

page only. Upon receipt of the proper Control Byte and Word Address bytes, the SLG46827-A will send an ACK. The device will

then be ready to receive page data, which is 16 sequential writes of 8-bit data words. The SLG46827-A will respond with an ACK

after each data word is received. The addressing device, such as a bus Master, must then terminate the write operation with a

Stop condition after all page data is written. At that time the device will enter an internally self-timed write cycle, which will be

2

completed within t . While the data is being written into the NVM Memory Array, all inputs, outputs, internal logic, and I C access

WR

to the Register data will be operational/valid. Please refer to Figure 100 for the SLG46827-A Memory Map.

2

Note: The 16 programmed bytes should be in the same page. Any I C command that does not meet specific requirements will

be ignored and NVM will remain unprogrammed.

Data “1” cannot be re-programmed as data “0” without erasure. Each byte can only be programmed one time without erasure.

Acknowledge

bit

Start

bit

Bus Activity

Data (n + 1)

Data (n + 15)

Control Byte

Word Address (n)

Data (n)

A

10

A

9

A

8

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

ACK

P

SDA LINE

S

X

W

ACK

Control

Code

Block

Address

Stop

bit

R/W bit

Figure 99: Page Write Command

A10 will be ignored during communication to SLG46827-A.

A9 = 1 will enable access to the NVM.

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

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A9 = 1 and A8 = 0 corresponds to the 2K bits chip configuration NVM data.

A3, A2, A1, and A0 should be 0000 for the page write operation.

In a single page, if the data written to any byte is 00H, the contents of the matching byte in NVM memory will not be altered.

2

I C Block Address

Memory Space

Lowest I²C

Address = 000h

2 Kbits Register Data Configuration

A10 = 0

A9 = 0

A9 = 1

A8 = X

2 Kbits NVM Data Configuration

Not Used

A10 = 0

A10 = 1

A8 = 0

A8 = 1

A8 = X

A9 = 1

A9 = X

Not Used

Highest I²C

Address = 7FFh

Figure 100: I²C Block Addressing

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

16.2 SERIAL NVM READ OPERATIONS

There are three read operations:



Current Address Read

Random Address Read

Sequential Read

Please refer to the Section 15 for more details.

16.3 SERIAL NVM ERASE OPERATIONS

The erase scheme allows a 16 byte page in the NVM chip configuration space to be erased by modifying the contents of the Erase

Register (ERSR). When the ERSE bit is set in the ERSR register, the device will start a self-timed erase cycle which will complete

in a maximum of t ms.

ER

The V pin requires a voltage ranging from 2.5 V to 5.5 V for Programming and Erase operations.

DD

Changing the state of the ERSR is accomplished with a Byte Write sequence with the requirements outlined in this section.

2

The ERSR register is located on I C Block Address = 000b, I C Word Address = E3H.

The ERSR format is shown in Table 56, and the ERSR bit functions are included in Table 57.

Table 56: Erase Register Bit format

b7

b6

b5

b4

b3

b2

b1

b0

Page Erase

Register

ERSE

--

ERSEB4

ERSEB3

ERSEB2

ERSEB1

ERSEB0

Table 57: Erase Register Bit Function Description

Bit

Name

Type

Description

Erase

Enable

Setting b7 bit to "1" will start an internal erase cycle on the page defined

by ERSEB4-0

7

ERSE

W

6

5

4

3

2

1

0

--

ERSEB4

ERSEB3

ERSEB2

ERSEB1

ERSEB0

W

Page

Selection

for Erase

Define the page address, which will be erased.

ERSB4 = 0 corresponds to the Upper 2K NVM used for chip configuration;

Upon receipt of the proper Device Address and Erase Register Address, the SLG46827-A will send an ACK. The device will then

be ready to receive Erase Register data. The SLG46827-A will respond with an ACK after Erase Register data word is received.

The addressing device, such as a bus Master, must then terminate the write operation with a Stop condition. At that time the

device will enter an internally self-timed erase cycle, which will be completed within t ms. While the data is being written into

ER

2

the Memory Array, all inputs, outputs, internal logic, and I C access to the Register data will be operational/valid.

After the erase has taken place, the contents of ERSE bits will be set to “0” automatically. The internal erase cycle will be triggered

2

at the time the Stop Bit in the I C command is received.

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

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17 Analog Temperature Sensor

The SLG46827-A has an Analog Temperature sensor (TS) with an output voltage linearly-proportional to the Centigrade tempera

-

ture. The TS cell shares buffer with Vref0, so it is impossible to use both cells simultaneously, its output can be connected directly

to the IO10 or to the ACPM3_L positive input. Using buffer causes low-output impedance, linear output, and makes interfacing

to readout or control circuitry especially easy. The TS is rated to operate over a -40 °C to 105 °C temperature range. The error in

the whole temperature range does not exceed ±0.85 %. TS output voltage variation over V at constant temperature is less than

DD

±0.08 %. For more detail refer to Section 3.

The equation below calculates the typical analog voltage passed from the TS to the ACMPs' IN+ source input. It is important to

note that there will be a chip to chip variation of about ±2 °C.

V

= -2.3 x T + 904.5

= -2.8 x T + 1092.8

TS1

V

TS2

where:

V

(mV) - TS Output Voltage, range 1 (0.62 V to 0.95 V)

(mV) - TS Output Voltage, range 2 (0.75 V to 1.2 V)

TS1

TS2

T (°C) - Temperature

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

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register [1094]

TS

register [1093]

0

1

TS_ON

TS_En

registers [1130:1129] force to “11” when TS is ON

From Connection Matrix Output [60]

V_DD

register [1130]

register [1129]

11

10

01

00

+

-

Vref0

IO10

registers [889:888]=11

register [1135]=1

ACMP3L in+

register [1095]

ACMP1H Vref

ACMP0H Vref

none

0

1

TS_En

Closed

Note: In order to use TS, BG must be enabled.

Figure 101: Analog Temperature Sensor Structure Diagram

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

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1.2

1.15

1.1

OutputꢀRangeꢀꢀ

OutputꢀRangeꢀꢁ

1.05

1

0.95

0.9

0.85

0.8

0.75

0.7

Tꢀ(°C)

Figure 102: Typical TS Output vs Temperature, V_DD= 2.3 V to 5.5 V

Datasheet

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

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18 Register Definitions

18.1 REGISTER MAP

Table 58: Register Map

Address

Signal Function

Register Bit Definition

Byte

Matrix Output

5:0

Register Bit

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

Matrix OUT0

Matrix OUT1

IN0 of LUT2_0 or Clock Input of DFF0

IN1 of LUT2_0 or Data Input of DFF0

11:6

17:12

Matrix OUT2

IN0 of LUT2_3 or Clock Input of PGen

23:18

29:24

Matrix OUT3

Matrix OUT4

IN1 of LUT2_3 or nRST of PGen

IN0 of LUT2_1 or Clock Input of DFF1

35:30

41:36

Matrix OUT5

Matrix OUT6

IN1 of LUT2_1 or Data Input of DFF1

IN0 of LUT2_2 or Clock Input of DFF2

47:42

53:48

Matrix OUT7

Matrix OUT8

IN1 of LUT2_2 or Data Input of DFF2

IN0 of LUT3_0 or Clock Input of DFF3

59:54

65:60

Matrix OUT9

Matrix OUT10

IN1 of LUT3_0 or Data Input of DFF3

IN2 of LUT3_0 or nRST(nSET) of DFF3

71:66

77:72

Matrix OUT11

Matrix OUT12

IN0 of LUT3_1 or Clock Input of DFF4

IN1 of LUT3_1 or Data Input of DFF4

83:78

89:84

Matrix OUT13

Matrix OUT14

IN2 of LUT3_1 or nRST(nSET) of DFF4

IN0 of LUT3_2 or Clock Input of DFF5

95:90

Matrix OUT15

Matrix OUT16

IN1 of LUT3_2 or Data Input of DFF5

IN2 of LUT3_2 or nRST(nSET) of DFF5

101:96

107:102

113:108

Matrix OUT17

Matrix OUT18

IN0 of LUT3_3 or Clock Input of DFF6

IN1 of LUT3_3 or Data Input of DFF6

119:114

125:120

Matrix OUT19

Matrix OUT20

IN2 of LUT3_3 or nRST(nSET) of DFF6

IN0 of LUT3_4 or Clock Input of DFF7

131:126

137:132

Matrix OUT21

Matrix OUT22

IN1 of LUT3_4 or Data Input of DFF7

IN2 of LUT3_4 or nRST(nSET) of DFF7

11

143:138

149:144

Matrix OUT23

Matrix OUT24

IN0 of LUT3_5 or Clock Input of DFF8

IN1 of LUT3_5 or Data Input of DFF8

12

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

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Table 58: Register Map (Continued)

Address

Signal Function

Matrix OUT25

Matrix OUT26

Register Bit Definition

Byte

12

13

14

15

16

Register Bit

155:150

IN2 of LUT3_5 or nRST(nSET) of DFF8

IN0 of LUT3_6 or Input of Pipe Delay or UPSignal of RIPP

CNT

161:156

167:162

173:168

Matrix OUT27

Matrix OUT28

IN1 of LUT3_6 or nRSTof Pipe Delay or STB of RIPPCNT

IN2 of LUT3_6 or Clock of Pipe Delay_RIPP_CNT

179:174

185:180

Matrix OUT29

Matrix OUT30

Reserved

MULTFUNC_16BIT_0: IN0 of LUT4_0 or Clock Input of

DFF9;

Delay0 Input (or Counter0 nRST/SET Input)

17

MULTFUNC_16BIT_0: IN1 of LUT4_0 or nRST of DFF9;

Delay0Input (or Counter0 nRSTInput) or Delay/Counter0

External Clock Source

17

191:186

197:192

Matrix OUT31

Matrix OUT32

MULTFUNC_16BIT_0: IN2 of LUT4_0 or nSET of DFF9;

Delay0Input (or Counter0 nRSTInput) or Delay/Counter0

External Clock Source or KEEP Input of FSM0

18

19

MULTFUNC_16BIT_0: IN3 of LUT4_0 or Data Input of

DFF9;

Delay0 Input (or Counter0 nRST Input) or UP Input of

FSM0

203:198

209:204

215:210

Matrix OUT33

Matrix OUT34

Matrix OUT35

19

1A

MULTFUNC_8BIT_1: IN0 of LUT3_7 or Clock Input of

DFF10;

Delay1 Input (or Counter1 nRST Input)

MULTFUNC_8BIT_1: IN1 of LUT3_7 or nRST (nSET) of

DFF10;

Delay1Input (or Counter1 nRSTInput) or Delay/Counter1

External Clock Source

1A

MULTFUNC_8BIT_1: IN2 of LUT3_7 or Data Input of

DFF10;

Delay1 Input (or Counter1 nRST Input)

1B

221:216

227:222

Matrix OUT36

Matrix OUT37

1B

1C

MULTFUNC_8BIT_2: IN0 of LUT3_8 or Clock Input of

DFF11;

Delay2 Input (or Counter2 nRST Input)

MULTFUNC_8BIT_2: IN1 of LUT3_8 or nRST (nSET) of

DFF11;

Delay2Input (or Counter2 nRSTInput) or Delay/Counter2

External Clock Source

233:228

Matrix OUT38

1D

MULTFUNC_8BIT_2: IN2 of LUT3_8 or Data Input of

DFF11;

Delay2 Input (or Counter2 nRST Input)

239:234

245:240

Matrix OUT39

Matrix OUT40

MULTFUNC_8BIT_3: IN0 of LUT3_9 or Clock Input of

DFF12;

1E

Delay3 Input (or Counter3 nRST Input)

1E

1F

MULTFUNC_8BIT_3: IN1 of LUT3_9 or nRST (nSET) of

DFF12;

Delay3Input (or Counter3 nRSTInput) or Delay/Counter3

251:246

Matrix OUT41

External Clock Source

Datasheet

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SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 58: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Byte

Register Bit

1F

MULTFUNC_8BIT_3: IN2 of LUT3_9 or Data Input of

DFF12;

Delay3 Input (or Counter3 nRST Input)

257:252

Matrix OUT42

20

MULTFUNC_8BIT_4: IN0 of LUT3_10 or Clock Input of

DFF13;

Delay4 Input (or Counter4 nRST Input)

20

263:258

269:264

Matrix OUT43

Matrix OUT44

MULTFUNC_8BIT_4: IN1 of LUT3_10 or nRST (nSET) of

DFF13;

Delay4Input (or Counter4 nRSTInput) or Delay/Counter4

External Clock Source

21

22

23

MULTFUNC_8BIT_4: IN2 of LUT3_10 or Data Input of

DFF13;

Delay4 Input (or Counter4 nRST Input)

275:270

281:276

Matrix OUT45

Matrix OUT46

MULTFUNC_8BIT_5: IN0 of LUT3_11 or Clock Input of

DFF14;

Delay5 Input (or Counter5 nRST Input)

MULTFUNC_8BIT_5: IN1 of LUT3_11 or nRST (nSET) of

DFF14;

Delay5Input (or Counter5 nRSTInput) or Delay/Counter5

23

287:282

Matrix OUT47

External Clock Source

MULTFUNC_8BIT_5: IN2 of LUT3_11 or Data Input of

DFF14;

Delay5 Input (or Counter5 nRST Input)

24

293:288

299:294

Matrix OUT48

Matrix OUT49

24

25

MULTFUNC_8BIT_6: IN0 of LUT3_12 or Clock Input of

DFF15;

Delay6 Input (or Counter6 nRST Input)

MULTFUNC_8BIT_6: IN1 of LUT3_12 or nRST (nSET) of

DFF15;

Delay6Input (or Counter6 nRSTInput) or Delay/Counter6

External Clock Source

305:300

Matrix OUT50

26

MULTFUNC_8BIT_6: IN2 of LUT3_12 or Data Input of

DFF15;

Delay6 Input (or Counter6 nRST Input)

311:306

317:312

Matrix OUT51

Matrix OUT52

MULTFUNC_8BIT_7: IN0 of LUT3_13 or Clock Input of

DFF16;

27

Delay7 Input (or Counter7 nRST Input)

27

28

MULTFUNC_8BIT_7: IN1 of LUT3_13 or nRST (nSET) of

DFF16;

Delay7Input (or Counter7 nRSTInput) or Delay/Counter7

External Clock Source

323:318

329:324

Matrix OUT53

Matrix OUT54

28

29

MULTFUNC_8BIT_7: IN2 of LUT3_13 or Data Input of

DFF16;

Delay7 Input (or Counter7 nRST Input)

29

2A

2B

2C

335:330

341:336

Matrix OUT55

Matrix OUT56

Filter/Edge detect input

Programmable delay/edge detect input

347:342

Matrix OUT57

OSC2 ENABLE from matrix

353:348

359:354

Matrix OUT58

Matrix OUT59

OSC0 ENABLE from matrix

OSC1 ENABLE from matrix

Datasheet

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SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 58: Register Map (Continued)

Address

Signal Function

Matrix OUT60

Matrix OUT61

Register Bit Definition

Byte

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

40

41

Register Bit

365:360

Vref PD from matrix

371:366

377:372

BG power-down from matrix

Matrix OUT62

Reserved

383:378

389:384

Matrix OUT63

Matrix OUT64

Reserved

PWR UP of ACMP0L from matrix

395:390

401:396

Matrix OUT65

Matrix OUT66

PWR UP of ACMP1L from matrix

Reserved

407:402

413:408

Matrix OUT67

Matrix OUT68

IO0 Digital Output

IO1 Digital Output

419:414

425:420

Matrix OUT69

Matrix OUT70

IO1 Digital Output OE

IO2 Digital Output

431:426

437:432

Matrix OUT71

Matrix OUT72

IO3 Digital Output

IO4 Digital Output

443:438

449:444

Matrix OUT73

Matrix OUT74

IO4 Digital Output OE

IO5 Digital Output

455:450

461:456

Matrix OUT75

Matrix OUT76

IO5 Digital Output OE

IO6 Digital Output

467:462

473:468

Matrix OUT77

Matrix OUT78

IO7 Digital Output

IO8 Digital Output

479:474

485:480

Matrix OUT79

Matrix OUT80

IO8 Digital Output OE

IO9 Digital Output

491:486

497:492

Matrix OUT81

Matrix OUT82

IO9 Digital Output OE

IO10 Digital Output

503:498

509:504

Matrix OUT83

Matrix OUT84

IO10 Digital Output OE

IO11 Digital Output

515:510

Matrix OUT85

IO11 Digital Output OE

521:516

527:522

Matrix OUT86

Matrix OUT87

IO12 Digital Output

IO12 Digital Output OE

Datasheet

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SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 58: Register Map (Continued)

Address

Signal Function

Matrix OUT88

Matrix OUT89

Register Bit Definition

Byte

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

Register Bit

533:528

IO13 Digital Output

539:534

545:540

IO13 Digital Output OE

Matrix OUT90

IO14 Digital Output

551:546

557:552

Matrix OUT91

Matrix OUT92

IO14 Digital Output OE

Reserved

563:558

569:564

Matrix OUT93

Matrix OUT94

Reserved

575:570

583:576

591:584

599:592

607:600

615:608

623:616

631:624

639:632

647:640

655:648

663:656

671:664

679:672

687:680

695:688

703:696

711:704

719:712

727:720

735:728

743:736

751:744

759:752

767:760

Matrix OUT95

Reserved

IO Common

0: disable

1: enable

768

769

IO fast Pull-up/down enable

2

60

0: I C standard/fast mode

2

I C mode selection

2

1: I C fast mode+

775:770

Reserved

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SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 58: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Byte

IO0

Register Bit

00: digital in without Schmitt Trigger

01: digital in with Schmitt Trigger

10: low voltage digital in mode

11: reserved

777:776

IO0 input mode configuration

00: Push-Pull 1x

01: Push-Pull 2x

10: 1x Open-Drain

11: 2x Open-Drain

779:778

IO0 output mode configuration

IO0 Pull-up/down resistance selection

61

00: floating

01: 10K

10: 100K

781:780

11: 1M

0: Pull-down

1: Pull-up

782

783

IO0 Pull-up/down selection

IO0 output enable

0: disable

1: enable

IO1

00: digital in without Schmitt Trigger

01: digital in with Schmitt Trigger

10: low voltage digital in mode

11: analog input

785:784

787:786

789:788

IO1 input mode configuration

00: Push-Pull 1x

01: Push-Pull 2x

10: 1x Open-Drain

11: 2x Open-Drain

IO1 output mode configuration

IO1 Pull-up/down resistance selection

62

00: floating

01: 10K

10: 100K

11: 1M

0: Pull-down

1: Pull-up

790

791

IO1 Pull-up/down selection

Reserved

63

793:792

795:794

797:796

798

Reserved

799

IO2

Datasheet

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SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

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Table 58: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Byte

Register Bit

00: digital in without Schmitt Trigger

01: digital in with Schmitt Trigger

10: low voltage digital in mode

11: reserved

801:800

IO2 input mode configuration

00: Push-Pull 1x

01: Push-Pull 2x

10: 1x Open-Drain

11: 2x Open-Drain

803:802

805:804

IO2 output mode configuration

64

00: floating

01: 10K

10: 100K

11: 1M

IO2 Pull-up/down resistance selection

0: Pull-down

1: Pull-up

806

807

IO2 Pull-up/down selection

IO2 output enable

0: disable

1: enable

IO3

00: digital in without Schmitt Trigger

01: digital in with Schmitt Trigger

10: low voltage digital in mode

11: reserved

809:808

811:810

813:812

IO3 input mode configuration

00: Push-Pull 1x

01: Push-Pull 2x

10: 1x Open-Drain

11: 2x Open-Drain

IO3 output mode configuration

IO3 Pull-up/down resistance selection

65

00: floating

01: 10K

10: 100K

11: 1M

0: Pull-down

1: Pull-up

814

815

IO3 Pull-up/down selection

IO3 output enable

0: disable

1: enable

IO4

00: digital in without Schmitt Trigger

01: digital in with Schmitt Trigger

10: low voltage digital in mode

11: reserved

817:816

819:818

821:820

IO4 input mode configuration

00: Push-Pull 1x

01: Push-Pull 2x

10: 1x Open-Drain

11: 2x Open-Drain

IO4 output mode configuration

IO4 Pull-up/down resistance selection

66

00: floating

01: 10K

10: 100K

11: 1M

0: Pull-down

1: Pull-up

822

823

IO4 Pull-up/down selection

Reserved

IO5

Datasheet

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 58: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Byte

Register Bit

00: digital in without Schmitt Trigger

01: digital in with Schmitt Trigger

10: low voltage digital in mode

11: reserved

825:824

IO5 input mode configuration

00: Push-Pull 1x

01: Push-Pull 2x

10: 1x Open-Drain

11: 2x Open-Drain

827:826

829:828

IO5 output mode configuration

67

00: floating

01: 10K

10: 100K

11: 1M

IO5 Pull-up/down resistance selection

0: Pull-down

1: Pull-up

830

831

IO5 Pull-up/down selection

Reserved

SCL

832

Reserved

00: digital in without Schmitt Trigger

01: Reserved

10: low voltage digital in mode

834:833

SCL input mode configuration

11: Reserved

68

00: floating

01: Reserved

10: Reserved

11: Reserved

836:835

SCL Pull-up/down resistance selection

837

Reserved

839:838

SDA

840

Reserved

00: digital in without Schmitt Trigger

01: Reserved

10: low voltage digital in mode

842:841

SDA input mode configuration

11: Reserved

69

00: floating

01: Reserved

10: Reserved

11: Reserved

844:843

SDA Pull-up/down resistance selection

845

Reserved

847:846

IO6

Datasheet

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

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Table 58: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Byte

Register Bit

849:848

Reserved

00: Push-Pull 1x

01: Push-Pull 2x

10: 1x Open-Drain

11: 2x Open-Drain

851:850

853:852

IO6 output mode configuration

00: floating

01: 10K

10: 100K

11: 1M

6A

IO6 Pull-up/down resistance selection

0: Pull-down

1: Pull-up

854

855

IO6 Pull-up/down selection

IO6 output enable

0: disable

1: enable

IO7

857:856

859:858

Reserved

00: Push-Pull 1x

01: Push-Pull 2x

10: 1x Open-Drain

11: 2x Open-Drain

IO7 output mode configuration

00: floating

01: 10K

10: 100K

6B

861:860

IO7 Pull-up/down resistance selection

11: 1M

0: Pull-down

1: Pull-up

862

863

IO7 Pull-up/down selection

IO7 output enable

0: disable

1: enable

IO8

00: digital in without Schmitt Trigger

01: digital in with Schmitt Trigger

10: low voltage digital in mode

11: reserved

865:864

867:866

869:868

IO8 input mode configuration

00: Push-Pull 1x

01: Push-Pull 2x

10: 1x Open-Drain

11: 2x Open-Drain

IO8 output mode configuration

IO8 Pull-up/down resistance selection

6C

00: floating

01: 10K

10: 100K

11: 1M

0: Pull-down

1: Pull-up

870

871

IO8 Pull-up/down selection

Reserved

873:872

875:874

877:876

878

Reserved

6D

879

Datasheet

24-Feb-2021

Revision 3.2

141 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 58: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Byte

IO9

Register Bit

00: digital in without Schmitt Trigger

01: digital in with Schmitt Trigger

10: low voltage digital in mode

11: analog output

881:880

IO9 input mode configuration

00: Push-Pull 1x

01: Push-Pull 2x

10: 1x Open-Drain

11: 2x Open-Drain

883:882

IO9 output mode configuration

IO9 Pull-up/down resistance selection

6E

IO10

6F

00: floating

01: 10K

10: 100K

885:884

11: 1M

0: Pull-down

1: Pull-up

886

887

IO9 Pull-up/down selection

Reserved

00: digital in without Schmitt Trigger

01: digital in with Schmitt Trigger

10: low voltage digital in mode

11: analog output

889:888

891:890

893:892

IO10 input mode configuration

00: Push-Pull 1x

01: Push-Pull 2x

10: 1x Open-Drain

11: 2x Open-Drain

IO10 output mode configuration

IO10 Pull-up/down resistance selection

00: floating

01: 10K

10: 100K

11: 1M

0: Pull-down

1: Pull-up

894

895

IO10 Pull-up/down selection

Reserved

IO11

00: digital in without Schmitt Trigger

01: digital in with Schmitt Trigger

10: low voltage digital in mode

11: analog input

897:896

899:898

901:900

IO11 input mode configuration

00: Push-Pull 1x

01: Push-Pull 2x

10: 1x Open-Drain

11: 2x Open-Drain

IO11 output mode configuration

IO11 Pull-up/down resistance selection

70

00: floating

01: 10K

10: 100K

11: 1M

0: Pull-down

1: Pull-up

902

903

IO11 Pull-up/down selection

Reserved

IO12

Datasheet

24-Feb-2021

Revision 3.2

142 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 58: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Byte

Register Bit

00: digital in without Schmitt Trigger

01: digital in with Schmitt Trigger

10: low voltage digital in mode

11: analog input

905:904

IO12 input mode configuration

00: Push-Pull 1x

01: Push-Pull 2x

10: 1x Open-Drain

11: 2x Open-Drain

907:906

909:908

IO12 output mode configuration

71

00: floating

01: 10K

10: 100K

11: 1M

IO12 Pull-up/down resistance selection

0: Pull-down

1: Pull-up

910

911

IO12 Pull-up/down selection

Reserved

IO13

00: digital in without Schmitt Trigger

01: digital in with Schmitt Trigger

10: low voltage digital in mode

11: analog IO

913:912

915:914

917:916

IO13 input mode configuration

00: Push-Pull 1x

01: Push-Pull 2x

10: 1x Open-Drain

11: 2x Open-Drain

IO13 output mode configuration

IO13 Pull-up/down resistance selection

72

00: floating

01: 10K

10: 100K

11: 1M

0: Pull-down

1: Pull-up

918

919

IO13 Pull-up/down selection

Reserved

IO14

00: digital in without Schmitt Trigger

01: digital in with Schmitt Trigger

10: low voltage digital in mode

11: analog input

921:920

923:922

925:924

IO14 input mode configuration

00: Push-Pull 1x

01: Push-Pull 2x

10: 1x Open-Drain

11: 2x Open-Drain

IO14 output mode configuration

IO14 Pull-up/down resistance selection

73

00: floating

01: 10K

10: 100K

11: 1M

0: Pull-down

1: Pull-up

926

927

IO14 Pull-up/down selection

Reserved

Matrix Input

Datasheet

24-Feb-2021

Revision 3.2

143 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 58: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Byte

Register Bit

928

929

930

931

932

933

934

935

936

937

938

939

940

941

942

943

944

945

946

947

948

949

950

951

952

953

954

955

956

957

958

959

960

961

962

963

964

965

966

967

Matrix Input 0

Matrix Input 1

Matrix Input 2

Matrix Input 3

Matrix Input 4

Matrix Input 5

Matrix Input 6

Matrix Input 7

Matrix Input 8

Matrix Input 9

Matrix Input 10

Matrix Input 11

Matrix Input 12

Matrix Input 13

Matrix Input 14

Matrix Input 15

Matrix Input 16

Matrix Input 17

Matrix Input 18

Matrix Input 19

Matrix Input 20

Matrix Input 21

Matrix Input 22

Matrix Input 23

Matrix Input 24

Matrix Input 25

Matrix Input 26

Matrix Input 27

Matrix Input 28

Matrix Input 29

Matrix Input 30

Matrix Input 31

Matrix Input 32

Matrix Input 33

Matrix Input 34

Matrix Input 35

Matrix Input 36

Matrix Input 37

Matrix Input 38

Matrix Input 39

Tie low

IO0 Digital Input

IO1 Digital Input

IO2 Digital Input

74

IO3 Digital Input

IO4 Digital Input

IO5 Digital Input

IO8 Digital Input

IO9 Digital Input

IO10 Digital Input

IO11 Digital Input

IO12 Digital Input

75

76

77

78

IO13 Digital Input

IO14 Digital Input

LUT2_0_DFF0_OUT

LUT2_1_DFF1_OUT

LUT2_2_DFF2_OUT

LUT2_3_PGEN_OUT

LUT3_0_DFF3_OUT

LUT3_1_DFF4_OUT

LUT3_2_DFF5_OUT

LUT3_3_DFF6_OUT

LUT3_4_DFF7_OUT

LUT3_5_DFF8_OUT

LUT3_6_PIPEDLY_RIPP_CNT_OUT0

PIPEDLY_RIPP_CNT_OUT1

RIPP_CNT_OUT2

EDET_FILTER_OUT

PROG_DLY_EDET_OUT

MULTFUNC_8BIT_1: DLY_CNT_OUT

CKOSC1_MATRIX: OSC1 matrix input

CKOSC0_MATRIX: OSC0 matrix input

CKOSC2_MATRIX: OSC2 matrix input

MULTFUNC_8BIT_2: DLY_CNT_OUT

MULTFUNC_8BIT_3: DLY_CNT_OUT

MULTFUNC_8BIT_4: DLY_CNT_OUT

MULTFUNC_8BIT_5: DLY_CNT_OUT

MULTFUNC_8BIT_6: DLY_CNT_OUT

MULTFUNC_8BIT_7: DLY_CNT_OUT

MULTFUNC_16BIT_0: LUT_DFF_OUT

Datasheet

24-Feb-2021

Revision 3.2

144 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 58: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Byte

Register Bit

968

Matrix Input 40

MULTFUNC_8BIT_1: LUT_DFF_OUT

MULTFUNC_8BIT_2: LUT_DFF_OUT

MULTFUNC_8BIT_3: LUT_DFF_OUT

MULTFUNC_8BIT_4: LUT_DFF_OUT

MULTFUNC_8BIT_5: LUT_DFF_OUT

MULTFUNC_8BIT_6: LUT_DFF_OUT

MULTFUNC_8BIT_7: LUT_DFF_OUT

MULTFUNC_16BIT_0: DLY_CNT_OUT

Virtual Input [7]: register [976]

Virtual Input [6]: register [977]

Virtual Input [5]: register [978]

Virtual Input [4]: register [979]

Virtual Input [3]: register [980]

Virtual Input [2]: register [981]

Virtual Input [1]: register [982]

Virtual Input [0]: register [983]

ACMP0H OUT

969

Matrix Input 41

970

Matrix Input 42

971

Matrix Input 43

79

972

Matrix Input 44

973

Matrix Input 45

974

Matrix Input 46

975

Matrix Input 47

976

Matrix Input 48

977

Matrix Input 49

978

Matrix Input 50

979

Matrix Input 51

7A

980

Matrix Input 52

981

Matrix Input 53

982

Matrix Input 54

983

Matrix Input 55

984

Matrix Input 56

985

Matrix Input 57

ACMP1H OUT

986

Matrix Input 58

ACMP0L OUT

987

Matrix Input 59

ACMP1L OUT

7B

988

Matrix Input 60

2nd CKOSC1_MATRIX

2nd CKOSC0_MATRIX

POR CORE

989

Matrix Input 61

990

Matrix Input 62

991

Matrix Input 63

Tie high

7C

7D

7E

7F

999:992

1007:1000

1015:1008

1023:1016

CNT0(16-bit) Counted Value

CNT2(8-bit) Counted Value

CNT4(8-bit) Counted Value

Q[7:0]

Q[15:8]

Q[7:0]

OSC/ACMP

Datasheet

24-Feb-2021

Revision 3.2

145 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 58: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Byte

Register Bit

when matrix output enable/pd control signal = 0:

0: auto on by delay cells

1024

OSC1 turn on by register

1: always on

0: matrix down

1: matrix on

1025

1026

matrix power-down or on select

external clock source enable

0: internal OSC1

1: external clock from IO10

00: div1

01: div2

10: div4

11: div8

1028:1027

post divider ration control

80

000: /1

001: /2

010: /4

011: /3

100: /8

101: /12

110: /24

111: /64

1031:1029

1032

matrix divider ratio control

OSC2 turn on by register

when matrix output enable/pd control signal = 0:

0: auto on by delay cells

1: always on

0: matrix down

1: matrix on

1033

1034

matrix power-down or on select

external clock source enable

0: internal OSC2

1: external clock from IO8

00: div1

01: div2

10: div4

11: div8

1036:1035

post divider ration control

81

000: /1

001: /2

010: /4

011: /3

100: /8

101: /12

110: /24

111: /64

1039:1037

matrix divider ratio control

Datasheet

24-Feb-2021

Revision 3.2

146 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 58: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Byte

Register Bit

when matrix output enable/pd control signal = 0:

0: auto on by delay cells

1040

OSC0 turn on by register

1: always on

0: matrix down

1: matrix on

1041

1042

matrix power-down or on select

external clock source enable

0: internal OSC0

1: external clock from IO0

00: div1

01: div2

10: div4

11: div8

1044:1043

post divider ration control

82

000: /1

001: /2

010: /4

011: /3

100: /8

101: /12

110: /24

111: /64

1047:1045

matrix divider ratio control

1048

1049

Reserved

0: disable

1: enable

OSC0 matrix out enable

0: disable

1: enable

1050

1051

1052

1053

OSC1 matrix out enable

OSC2 matrix out enable

OSC2 100 ns Startup Delay

OSC0 2nd matrix out enable

0: disable

1: enable

83

0: enable

1: disable

0: disable

1: enable

0: disable

1: enable

1054

1055

OSC1 2nd matrix out enable

Reserved

000: /1

001: /2

010: /4

011: /3

100: /8

101: /12

110: /24

111: /64

OSC1 2nd matrix input:

matrix divider ratio control

1058:1056

84

000: /1

001: /2

010: /4

011: /3

100: /8

101: /12

110: /24

111: /64

OSC0 2nd matrix input:

matrix divider ratio control

1061:1059

1063:1062

Reserved

Datasheet

24-Feb-2021

Revision 3.2

147 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 58: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Byte

Register Bit

00: 0 mV

01: 32 mV

10: 64 mV

11: 192 mV

[1065:1064]

ACMP0H hysteresis

0: disable

1: enable

[1066]

[1067]

[1068]

[1069]

[1070]

[1071]

[1072]

[1073]

Reserved

0: disable

1: enable

ACMP0H input buffer enable

Reserved

85

0: disable

1: enable

0: disable

1: enable

ACMP0H input tie to V enable

DD

0: disable

1: enable

ACMP0H wake/sleep enable

0: disable

1: enable

ACMP0H 100 uA current source enable

ACMP1H positive input come from

ACMP0H's input mux output enable

0: disable

1: enable

0: disable

1: enable

Reserved

00: 0 mV

01: 32 mV

10: 64 mV

11: 192 mV

[1075:1074]

ACMP1H hysteresis

86

0: disable

1: enable

[1076]

[1077]

[1078]

[1079]

[1080]

[1081]

ACMP1H input buffer enable

Reserved

0: disable

1: enable

0: disable

1: enable

ACMP1H wake/sleep enable

ACMP wake/sleep time selection

0: short time wake/sleep

1: normal time wake/sleep

ACMP2L positive input come from

ACMP0H's input mux output enable

0: disable

1: enable

ACMP2L positive input come from

ACMP1H's input mux output enable

0: disable

1: enable

00: 0 mV

01: 32 mV

10: 64 mV

11: 192 mV

[1083:1082]

[1084]

ACMP2L hysteresis

Reserved

87

0: disable

1: enable

0: disable

1: enable

[1085]

[1086]

[1087]

Reserved

0: disable

1: enable

ACMP0H, ACMP1H input buffer WS enable

Datasheet

24-Feb-2021

Revision 3.2

148 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 58: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Byte

Register Bit

00: 0 mV

01: 32 mV

10: 64 mV

11: 192 mV

[1089:1088]

ACMP3L hysteresis

0: disable

1: enable

[1090]

[1091]

[1092]

[1093]

[1094]

[1095]

Reserved

0: disable

1: enable

88

ACMP3L positive input come from

ACMP2L's input mux output enable

0: disable

1: enable

0: power-down

1: power-on

Temp sensor register pd control

Temp sensor register pd select

Temp sensor range select

0: come from register

1: come from matrix

0: range 1 (0.62 V to 0.99 V typical)

1: range 2 (0.75 V to 1.2 V typical)

00: 1x

01: 0.5x

10: 0.33x

11: 0.25x

[1097:1096]

[1103:1098]

[1105:1104]

[1111:1106]

[1113:1112]

[1119:1114]

[1121:1120]

ACMP0H Gain divider

ACMP0H Vref

89

8A

8B

ACMP Vref select: 000000: 32 mV ~ 111110: 2.016 V/step

= 32 mV;

111111: External Vref

00: 1x

01: 0.5x

10: 0.33x

11: 0.25x

ACMP1H Gain divider

ACMP1H Vref

ACMP Vref select: 000000: 32 mV ~ 111110: 2.016 V/step

= 32 mV;

111111: External Vref

00: 1x

01: 0.5x

10: 0.33x

11: 0.25x

ACMP2L Gain divider

ACMP2L Vref

ACMP Vref select: 000000: 32 mV ~ 111110: 2.016 V/step

= 32 mV;

111111: External Vref

00: 1x

01: 0.5x

10: 0.33x

11: 0.25x

ACMP3L Gain divider

8C

ACMP Vref select:

000000: 32 mV ~

111110: 2.016 V/step = 32 mV;

111111: External Vref

[1127:1122]

ACMP3L Vref

Datasheet

24-Feb-2021

Revision 3.2

149 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 58: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Byte

Register Bit

0: disable

1: enable

[1128]

Vref_OUT0 output OP

00: None

01: ACMP0H Vref

10: ACMP1H Vref

11: temp sensor

[1130:1129]

[1131]

Vref_OUT0 input selection

Vref_OUT1 output OP

Vref_OUT0 input selection

Reserved

0: disable

1: enable

00: None

8D

01: ACMP2L Vref

10: ACMP3L Vref

11: Reserved

[1133:1132]

[1134]

0: disable connection from temp sensed voltage (VrefO0)

to ACMP3L input

1: enable connection from temp sensed voltage (VrefO0)

to ACMP3L input

[1135]

Tempsensed voltage to ACMP

[1136]

[1137]

Reserved

0: Vref_OUT0 disable

1: Vref_OUT0 enable

Vref_OUT0 PD

0: enable/disable using Vref_OUT0 PD [1137]

1: enable/disable using matrix out[60] TS_OSC_PD

[1138]

[1139]

[1140]

Vref_OUT0 PD selection

Vref_OUT1 PD

8E

8F

0: Vref_OUT1 disable

1: Vref_OUT1 enable

0: enable/disable using Vref_OUT1 PD [1139]

1: enable/disable using matrix out[60] TS_OSC_pd

Vref_OUT1 PD selection

[1143:1141]

1145:1144

1151:1146

Reserved

Digital Macrocell

[3]: LUT2_0[3]/DFF0 or LATCH Select

0: DFF function

1: LATCH function

[2]: LUT2_0[2]/DFF0 Output Sel

0: Q output

1155:1152

LUT2_0/DFF0 setting

1: QB output

[1]: LUT2_0[1]/DFF0 Initial Polarity Select

0: Low

1: High

[0]: LUT2_0[0]

90

[3]: LUT2_1[3]/DFF1 or LATCH Select

0: DFF function

1: LATCH function

[2]: LUT2_1[2]/DFF1 Output Select

0: Q output

1159:1156

LUT2_1/DFF1 setting

1: QB output

[1]: LUT2_1[1]/DFF1 Initial Polarity Select

0: Low

1: High

[0]: LUT2_1[0]

Datasheet

24-Feb-2021

Revision 3.2

150 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 58: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Byte

Register Bit

[3]: LUT2_2[3]/DFF2 or LATCH Select

0: DFF function

1: LATCH function

[2]: LUT2_2[2]/DFF2 Output Select

0: Q output

1163:1160

LUT2_2/DFF2 setting

1: QB output

91

[1]: LUT2_2[1]/DFF2 Initial Polarity Select

0: Low

1: High

[0]: LUT2_2[0]

1167:1164

1175:1168

1183:1176

LUT2_3_VAL or PGEN_data

PGen data [7:0]

LUT2_3[3:0] or PGen 4bit counter data[3:0]

PGen data [7:0]

92

93

PGen data [15:8]

[7]: LUT3_0[7]/DFF3 or LATCH Select

0: DFF function

1: LATCH function

[6]: LUT3_0[6]/DFF3 Output Select

0: Q output

1: QB output

94

95

96

1191:1184

1199:1192

1207:1200

LUT3_0_DFF3 setting

LUT3_1_DFF4 setting

LUT3_2_DFF5 setting

[5]: LUT3_0[5]/DFF3

0: nRST from Matrix Output

1: nSET from Matrix Output

[4]: LUT3_0[4]/DFF3 Initial Polarity Select

0: Low

1: High

[3:0]: LUT3_0[3:0]

[7]: LUT3_1[7]/DFF4 or LATCH Select

0: DFF function

1: LATCH function

[6]: LUT3_1[6]/DFF4 Output Select

0: Q output

1: QB output

[5]: LUT3_1[5]/DFF4

0: nRST from Matrix Output

1: nSET from Matrix Output

[4]: LUT3_1[4]/DFF4 Initial Polarity Select

0: Low

1: High

[3:0]: LUT3_1[3:0]

[7]: LUT3_2[7]/DFF5 or LATCH Select

0: DFF function

1: LATCH function

[6]: LUT3_2[6]/DFF5 Output Select

0: Q output

1: QB output

[5]: LUT3_2[5]/DFF5

0: nRST from Matrix Output

1: nSET from Matrix Output

[4]: LUT3_2[4]/DFF5 Initial Polarity Select

0: Low

1: High

[3:0]: LUT3_2[3:0]

Datasheet

24-Feb-2021

Revision 3.2

151 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 58: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Byte

Register Bit

[7]: LUT3_3[7]/DFF6 or LATCH Select

0: DFF function

1: LATCH function

[6]: LUT3_3[6]/DFF6 Output Select

0: Q output

1: QB output

97

1215:1208

LUT3_3_DFF6 setting

[5]: LUT3_3[5]/DFF6

0: nRST from Matrix Output

1: nSET from Matrix Output

[4]: LUT3_3[4]/DFF6 Initial Polarity Select

0: Low

1: High

[3:0]: LUT3_3[3:0]

[7]: LUT3_4[7]/DFF7 or LATCH Select

0: DFF function

1: LATCH function

[6]: LUT3_4[6]/DFF7 Output Select

0: Q output

1: QB output

98

1223:1216

LUT3_4_DFF7 setting

[5]: LUT3_4[5]/DFF7

0: nRST from Matrix Output

1: nSET from Matrix Output

[4]: LUT3_4[4]/DFF7 Initial Polarity Select

0: Low

1: High

[3:0]: LUT3_4[3:0]

[7]: LUT3_5[7]/DFF8 or LATCH Select

0: DFF function

1: LATCH function

[6]: LUT3_5[6]/DFF8 Output Select

0: Q output

1: QB output

99

1231:1224

LUT3_5_DFF8 setting

[5]: LUT3_5[5]/DFF8

0: RSTB from Matrix Output

1: SETB from Matrix Output

[4]: LUT3_5[4]/DFF8 Initial Polarity Select

0: Low

1: High

[3:0]: LUT3_5[3:0]

Datasheet

24-Feb-2021

Revision 3.2

152 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 58: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Byte

Register Bit

0: LUT2_0

1: DFF0

1232

LUT2_0 or DFF0 Select

LUT2_1 or DFF1 Select

LUT2_2 or DFF2 Select

LUT2_3 or PGen Select

LUT3_0 or DFF3 Select

DFF3_SECONDQ_Sel

LUT3_1 or DFF4 Select

LUT3_2 or DFF5 Select

LUT3_3 or DFF6 Select

LUT3_4 or DFF7 Select

LUT3_5 or DFF8 Select

Filter or Edge Detector selection

output Polarity Select

0: LUT2_1

1: DFF1

1233

1234

1235

1236

1237

1238

1239

1240

1241

1242

1243

1244

0: LUT2_2

1: DFF2

0: LUT2_3

1: PGen

9A

0: LUT3_0

1: DFF3

0: Q of first DFF

1: Q of second DFF

0: LUT3_1

1: DFF4

0: LUT3_2

1: DFF5

0: LUT3_3

1: DFF6

0: LUT3_4

1: DFF7

0: LUT3_5

1: DFF8

0: filter

1: edge det

9B

0: Filter/edge detect output

1: Filter/edge detect output inverted

00: Rising Edge Det

01: Falling Edge Det

10: Both Edge Det

11: Both Edge DLY

1246:1245

1247

Select the edge mode

Reserved

[7:4]:LUT3_6[7:4]/REG_S1[3:0]Pipe Delay out1 SEL

[3:0]:LUT3_6[3:0]/REG_S0[3:0]Pipe Delay out0 SEL

at RIPP CNT mode:

bit[1250:1248] is the nSET value

bit[1253:1251] is the END value

bit[1254] functional mode:0: full cycle;

1: ranged cycle

LUT value or Pipe Delay out SEL or

nSET/END value

9C

1255:1248

bit[1255] not used

Datasheet

24-Feb-2021

Revision 3.2

153 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 58: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Byte

Register Bit

0: Non-inverted

1: Inverted

1256

Pipe Delay OUT1 Polarity Select

LUT3_6 or Pipe Delay Select

PIPE_RIPP_CNT_S

0: LUT3_6

1: Pipe Delay or RIPP CNT

1257

1258

0: Pipe delay mode selection

1: Ripple Counter mode selection

00: Rising Edge Detector

01: Falling Edge Detector

10: Both Edge Detector

11: Both Edge Delay

9D

Select the Edge Mode of Programmable

Delay & Edge Detector

1260:1259

1262:1261

00: 125ns

Delay Value Select for Programmable Delay 01: 250ns

& Edge Detector

10: 375ns

11: 500ns

1263

1264

Reserved

1265

9E

9F

1266

1271:1267

1276:1272

1277

1278

1279

Multifunction

0000000: Matrix A - In3; Matrix B - In2; Matrix C - In1;

Matrix D - In0

Single 4-bit LUT

(DLY_IN - LOW)

1286

0010000: Matrix A - D; Matrix B - nSET; Matrix C - nRST;

1285

1282

1284

1283

1281

1280

Single DFF w RST and SET

Single CNT/DLY

Matrix D - CLK

(DLY_IN - LOW)

A0

0000001: Matrix A - UP (CNT); Matrix B - KEEP (CNT);

Matrix C - EXT_CLK (CNT); Matrix D - DLY_IN (CNT)

(DLY_OUT connected to LUT/DFF)

0000010: Matrix A- DLY_IN; Matrix B - In2; Matrix C - In1;

Matrix D - In0

CNT/DLY → LUT

(DLY_OUT connected to In3)

Datasheet

24-Feb-2021

Revision 3.2

154 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 58: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Byte

Register Bit

0000110: Matrix A - DLY_IN; Matrix B - nSET;

Matrix C - nRST; Matrix D - CLK

(DLY_OUT connected to D)

CNT/DLY → DFF

0100010: Matrix A - DLY_IN; Matrix B - EXT_CLK (CNT);

Matrix C - In1; Matrix D - In0

(DLY_OUT connected to In3; In2 - LOW)

CNT/DLY → LUT

CNT/DLY → DFF

0100110: Matrix A - DLY_IN; Matrix B - EXT_CLK (CNT);

Matrix C - nRST; Matrix D - CLK

(DLY_OUT connected to D; nSET - HIGH)

1000010: Matrix A - DLY_IN; Matrix B - In2;

Matrix C - EXT_CLK (CNT);

Matrix D - In0

CNT/DLY → LUT

CNT/DLY → DFF

(DLY_OUT connected to In3; In1 - LOW)

1000110: Matrix A - DLY_IN; Matrix B - nSET;

Matrix C - EXT_CLK (CNT);

Matrix D - CLK

(DLY_OUT connected to D; nRST - HIGH)

0001010: Matrix A- In3; Matrix B - DLY_IN; Matrix C - In1;

Matrix D - In0

(DLY_OUT connected to In2)

CNT/DLY → LUT

CNT/DLY → DFF

0001110: MatrixA- D; Matrix B - DLY_IN; Matrix C - nRST;

Matrix D - CLK

1286

1285

1282

1284

1283

1281

1280

(DLY_OUT connected to nSET)

A0

1001010: Matrix A - In3; Matrix B - DLY_IN;

Matrix C - EXT_CLK (CNT);

Matrix D - In0

CNT/DLY → LUT

CNT/DLY → DFF

(DLY_OUT connected to In2; In1 - LOW)

1001110: Matrix A - D; Matrix B - DLY_IN;

Matrix C - EXT_CLK (CNT);

Matrix D - CLK

(DLY_OUT connected to nSET; nRST - HIGH)

0010010: Matrix A- In3; Matrix B - In2; Matrix C - DLY_IN;

Matrix D - In0

(DLY_OUT connected to In1)

CNT/DLY → LUT

CNT/DLY → DFF

0010110: MatrixA- D; Matrix B - nSET; Matrix C - DLY_IN;

Matrix D - CLK

(DLY_OUT connected to nRST)

0110010: Matrix A - In3; Matrix B - EXT_CLK (CNT);

Matrix C - DLY_IN;

Matrix D - In0

CNT/DLY → LUT

(DLY_OUT connected to In1; In2 - LOW)

0110110: Matrix A - D; Matrix B - EXT_CLK (CNT);

Matrix C - DLY_IN; Matrix D - CLK

(DLY_OUT connected to nRST; nSET - HIGH)

CNT/DLY → DFF

CNT/DLY → LUT

0011010: Matrix A - In3; Matrix B - In2; Matrix C - In1;

Matrix D - DLY_IN

(DLY_OUT connected to In0)

Datasheet

24-Feb-2021

Revision 3.2

155 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 58: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Byte

Register Bit

0011110: Matrix A - D; Matrix B - nSET; Matrix C - nRST;

Matrix D - DLY_IN

CNT/DLY → DFF

(DLY_OUT connected to CLK)

0111010: Matrix A - In3; Matrix B - EXT_CLK (CNT);

Matrix C - In1;

Matrix D - DLY_IN

CNT/DLY → LUT

CNT/DLY → DFF

CNT/DLY → LUT

(DLY_OUT connected to In0; In2 - LOW)

0111110: Matrix A - D; Matrix B - EXT_CLK (CNT);

Matrix C - nRST; Matrix D - DLY_IN

(DLY_OUT connected to CLK; nSET - HIGH)

1011010: Matrix A - In3; Matrix B - In2;

Matrix C - EXT_CLK (CNT);

Matrix D - DLY_IN

(DLY_OUT connected to In0; In1 - LOW)

1011110: Matrix A - D; Matrix B - nSET;

Matrix C - EXT_CLK (CNT); Matrix D - DLY_IN

(DLY_OUT connected to CLK; nRST - HIGH)

1286

1285

1282

1284

1283

1281

1280

CNT/DLY → DFF

LUT → CNT/DLY

DFF → CNT/DLY

LUT → CNT/DLY

DFF → CNT/DLY

LUT → CNT/DLY

DFF → CNT/DLY

0000011: Matrix A - In3; Matrix B - In2; Matrix C - In1;

Matrix D - In0

(LUT_OUT connected to DLY_IN)

A0

0000111: Matrix A - D; Matrix B - nSET; Matrix C - nRST;

Matrix D - CLK

(DFF_OUT connected to DLY_IN)

0100011: Matrix A - In3; Matrix B - EXT_CLK (CNT);

Matrix C - In1; Matrix D - In0

(LUT_OUT connected to DLY_IN; In2 - LOW)

0100111: Matrix A - D; Matrix B - EXT_CLK (CNT);

Matrix C - nRST; Matrix D - CLK

(DFF_OUT connected to DLY_IN; nSET - HIGH)

1000011: Matrix A - In3; Matrix B - In2;

Matrix C - EXT_CLK (CNT); Matrix D - In0

(LUT_OUT connected to DLY_IN; In1 - LOW)

1000111: Matrix A - D; Matrix B - nSET;

Matrix C - EXT_CLK (CNT); Matrix D - CLK

(DFF_OUT connected to DLY_IN; nRST - HIGH)

0: Reset to 0

1: Set to data

1287

FSM0 SET/RST Selection

LUT4_0_DFF9 setting [7:0]

A1

A2

1295:1288

[7:0]: LUT4_0[7:0]

[15]: LUT4_0[15]/DFF or LATCH Select

0: DFF function; 1: LATCH function

[14]: LUT4_0[14]/DFF Output Select

0: Q output; 1: QB output

[13]: LUT4_0[13]/DFF Initial Polarity Select

0: Low; 1: High

1303:1296

LUT4_0_DFF9 setting [15:8]

[12:8]: LUT4_0[12:8]

Datasheet

24-Feb-2021

Revision 3.2

156 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 58: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Byte

Register Bit

00: DLY

01: one shot

10: frequency det

11: CNT

1305:1304

DLY/CNT0 Mode Selection

00: both edge

01: falling edge

10: rising edge

11: High Level Reset (only in CNT mode)

1307:1306

1311:1308

DLY/CNT0 edge Mode Selection

DLY/CNT0 Clock Source Select

A3

Clock source SEL [3:0]

0000: 25M(OSC2); 0001: 25M/4; 0010: 2M(OSC1);

0011: 2M/8; 0100: 2M/64; 0101: 2M/512; 0110:

2K(OSC0);

0111: 2K/8; 1000: 2K/64; 1001: 2K/512; 1010: 2K/4096;

1011: 2K/32768; 1100: 2K/262144; 1101: CNT_END;

1110: External; 1111: Not used

0: Default Output

1: Inverted Output

1312

CNT0 output pol selection

CNT0 initial value selection

00: bypass the initial

01: initial 0

10: initial 1

1314:1313

11: initial 1

1315

1316

Reserved

A4

0: bypass

1: after two DFF

1317

1318

1319

Keep signal SYNC selection

0: bypass

1: after two DFF

UP signal SYNC selection

0: normal

1: DLY function edge detection

CNT0 DLY EDET FUNCTION Selection

A5

A6

1327:1320

1335:1328

REG_CNT0_Data[7:0]

REG_CNT0_Data[15:8]

Data[7:0]

Data[15:8]

0: bypass

1: after two DFF

1336

CNT0 CNT mode SYNC selection

00000: Matrix A - In2; Matrix B - In1;

Matrix C - In0

(DLY_IN - LOW)

1339

1341

1340

1338

1337

A7

Single 3-bit LUT

10000: MatrixA- D; Matrix B - nSET/nRST; Matrix C - CLK

(DLY_IN - LOW)

Single DFF w RST and SET

Datasheet

24-Feb-2021

Revision 3.2

157 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 58: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Byte

Register Bit

00001: Matrix A - DLY_IN (CNT); Matrix B - EXT_CLK

(CNT); Matrix C - NC

(DLY_OUT connected to LUT/DFF)

Single CNT/DLY

CNT/DLY → LUT

CNT/DLY → DFF

00010: Matrix A - DLY_IN; Matrix B - In1; Matrix C - In0

(DLY_OUT connected to In2)

00110: Matrix A - DLY_IN; Matrix B - nSET/nRST;

Matrix C - CLK

(DLY_OUT connected to D)

01010: Matrix A - In2; Matrix B - DLY_IN; Matrix C - In0

(DLY_OUT connected to In1)

CNT/DLY → LUT

CNT/DLY → DFF

1339

1341

1340

1338

1337

01110: Matrix A - D; Matrix B - DLY_IN; Matrix C - CLK

(DLY_OUT connected to nSET/nRST)

10010: Matrix A - In2; Matrix B - In1;

Matrix C - DLY_IN

(DLY_OUT connected to In0)

A7

CNT/DLY → LUT

CNT/DLY → DFF

11010: Matrix A - D; Matrix B - nSET/nRST;

Matrix C - DLY_IN

(DLY_OUT connected to CLK)

00011: Matrix A - In2; Matrix B - In1; Matrix C - In0

(LUT_OUT connected to DLY_IN)

LUT → CNT/DLY

DFF → CNT/DLY

00111: MatrixA- D; Matrix B - nSET/nRST; Matrix C - CLK

(DFF_OUT connected to DLY_IN)

00: bypass the initial

01: initial 0

10: initial 1

1343:1342

1351:1344

CNT1 initial value selection

11: initial 1

[7]: LUT3_7[7]/DFF or LATCH Select

0: DFF function; 1: LATCH function

[6]: LUT3_7[6]/DFF Output Select

0: Q output; 1: QB output

[5]: LUT3_7[5]/DFF

A8

LUT3_7_DFF10 setting

0: nRST from Matrix Output;

1: nSET from Matrix Output

[4]: LUT3_7[4]/DFF Initial Polarity Select

0:Low; 1: High

[3:0]: LUT3_7[3:0]

Clock source SEL [3:0]

0000: 25M(OSC2); 0001: 25M/4; 0010: 2M(OSC1);

0011: 2M/8; 0100: 2M/64; 0101: 2M/512; 0110:

2K(OSC0);

1355:1352

DLY/CNT1 Clock Source Select

0111: 2K/8; 1000: 2K/64; 1001: 2K/512; 1010: 2K/4096;

1011: 2K/32768; 1100: 2K/262144; 1101: CNT_END;

1110: External; 1111: Not used

A9

AA

0000: both edge Delay; 0001: falling edge delay;

0010: rising edge delay; 0011: both edge One Shot;

0100: falling edge One Shot; 0101: rising edge One Shot;

0110: both edge freq detect; 0111: falling edge freq detect;

1000: rising edge freq detect; 1001: both edge detect;

1010: falling edge detect; 1011: rising edge detect;

1100: both edge reset CNT; 1101: falling edge reset CNT;

1110: rising edge reset CNT; 1111: high level reset CNT

1359:1356

1367:1360

CNT1 function and edge mode selection

REG_CNT1_Data[7:0]

Data[7:0]

Datasheet

24-Feb-2021

Revision 3.2

158 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 58: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Byte

Register Bit

1368

0: Default Output

1: Inverted Output

CNT1 output pol selection

Reserved

1369

0: bypass

1: after two DFF

1370

CNT1 CNT mode SYNC selection

0: normal

1: DLY function edge detection

AB

1371

CNT1 DLY EDET FUNCTION Selection

Single 3-bit LUT

00000: Matrix A - In2; Matrix B - In1;

Matrix C - In0

(DLY_IN - LOW)

1394,

1375:1372

10000: MatrixA- D; Matrix B - nSET/nRST; Matrix C - CLK

(DLY_IN - LOW)

Single DFF w RST and SET

Single CNT/DLY

00001: Matrix A - DLY_IN (CNT); Matrix B - EXT_CLK

(CNT); Matrix C - NC

(DLY_OUT connected to LUT/DFF)

00010: Matrix A - DLY_IN; Matrix B - In1; Matrix C - In0

(DLY_OUT connected to In2)

CNT/DLY → LUT

10010: Matrix A - DLY_IN; Matrix B - nSET/nRST;

Matrix C - CLK

CNT/DLY → DFF

(DLY_OUT connected to D)

00110: Matrix A - In2; Matrix B - DLY_IN; Matrix C - In0

(DLY_OUT connected to In1)

CNT/DLY → LUT

CNT/DLY → DFF

1394,

1375:1372

10110: Matrix A - D; Matrix B - DLY_IN; Matrix C - CLK

(DLY_OUT connected to nSET/nRST)

AB

01010: Matrix A - In2; Matrix B - In1;

Matrix C - DLY_IN

(DLY_OUT connected to In0)

CNT/DLY → LUT

CNT/DLY → DFF

11010: Matrix A - D; Matrix B - nSET/nRST;

Matrix C - DLY_IN

(DLY_OUT connected to CLK)

00011: Matrix A - In2; Matrix B - In1; Matrix C - In0

(LUT_OUT connected to DLY_IN)

LUT → CNT/DLY

DFF → CNT/DLY

10011: MatrixA- D; Matrix B - nSET/nRST; Matrix C - CLK

(DFF_OUT connected to DLY_IN)

[7]: LUT3_8[7]/DFF or LATCH Select

0: DFF function; 1: LATCH function

[6]: LUT3_8[6]/DFF Output Select

0: Q output; 1: QB output

[5]: LUT3_8[5]/DFF

AC

1383:1376

LUT3_8_DFF_11 setting

0: nRST from Matrix Output; 1: nSET from Matrix

Output

[4]: LUT3_8[4]/DFF Initial Polarity Select

0:Low; 1: High

[3:0]: LUT3_8[3:0]

Datasheet

24-Feb-2021

Revision 3.2

159 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 58: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Byte

Register Bit

Clock source SEL [3:0]

0000: 25M(OSC2); 0001: 25M/4; 0010: 2M(OSC1);

0011: 2M/8; 0100: 2M/64; 0101: 2M/512; 0110:

2K(OSC0);

1387:1384

DLY/CNT2 Clock Source Select

0111: 2K/8; 1000: 2K/64; 1001: 2K/512; 1010: 2K/4096;

1011: 2K/32768; 1100: 2K/262144; 1101: CNT_END;

1110: External; 1111: Not used

AD

0000: both edge Delay; 0001: falling edge delay;

0010: rising edge delay; 0011: both edge One Shot;

0100: falling edge One Shot; 0101: rising edge One Shot;

0110: both edge freq detect; 0111: falling edge freq detect;

1000: rising edge freq detect; 1001: both edge detect;

1010: falling edge detect; 1011: rising edge detect;

1100: both edge reset CNT; 1101: falling edge reset CNT;

1110: rising edge reset CNT; 1111: high level reset CNT

1391:1388

1393:1392

CNT2 function and edge mode selection

CNT2 initial value selection

00: bypass the initial

01: initial 0

10: initial 1

11: initial 1

0: Default Output

1: Inverted Output

1395

1396

1397

CNT2 output pol selection

Reserved

AE

0: bypass

1: after two DFF

CNT2 CNT mode SYNC selection

0: normal

1: DLY function edge detection

1398

CNT2 DLY EDET FUNCTION Selection

1399

1407:1400

1408

Reserved

AF

B0

REG_CNT2_Data[7:0]

Reserved

Data[7:0]

00000: Matrix A - In2; Matrix B - In1;

Matrix C - In0

(DLY_IN - LOW)

1411

1413

1412

1410

1409

Single 3-bit LUT

00100: MatrixA- D; Matrix B - nSET/nRST; Matrix C - CLK

(DLY_IN - LOW)

Single DFF w RST and SET

Datasheet

24-Feb-2021

Revision 3.2

160 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 58: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Byte

Register Bit

00001: Matrix A - DLY_IN (CNT); Matrix B - EXT_CLK

(CNT); Matrix C - NC

(DLY_OUT connected to LUT/DFF)

Single CNT/DLY

CNT/DLY → LUT

CNT/DLY → DFF

00010: Matrix A - DLY_IN; Matrix B - In1; Matrix C - In0

(DLY_OUT connected to In2)

00110: Matrix A - DLY_IN; Matrix B - nSET/nRST;

Matrix C - CLK

(DLY_OUT connected to D)

01010: Matrix A - In2; Matrix B - DLY_IN; Matrix C - In0

(DLY_OUT connected to In1)

CNT/DLY → LUT

CNT/DLY → DFF

1411

1413

1412

1410

1409

01110: Matrix A - D; Matrix B - DLY_IN; Matrix C - CLK

(DLY_OUT connected to nSET/nRST)

10010: Matrix A - In2; Matrix B - In1;

Matrix C - DLY_IN

(DLY_OUT connected to In0)

B0

CNT/DLY → LUT

CNT/DLY → DFF

10110: Matrix A - D; Matrix B - nSET/nRST;

Matrix C - DLY_IN

(DLY_OUT connected to CLK)

00011: Matrix A - In2; Matrix B - In1; Matrix C - In0

(LUT_OUT connected to DLY_IN)

LUT → CNT/DLY

DFF → CNT/DLY

00111: MatrixA- D; Matrix B - nSET/nRST; Matrix C - CLK

(DFF_OUT connected to DLY_IN)

00: bypass the initial

01: initial 0

10: initial 1

1415:1414

1423:1416

CNT3 initial value selection

11: initial 1

[7]: LUT3_9[7]/DFF or LATCH Select

0: DFF function; 1: LATCH function

[6]: LUT3_9[6]/DFF Output Select

0: Q output; 1: QB output

[5]: LUT3_9[5]/DFF

B1

LUT3_9_DFF12 setting

0: nRST from Matrix Output; 1: nSET from Matrix

Output

[4]: LUT3_9[4]/DFF Initial Polarity Select

0:Low; 1: High

[3:0]: LUT3_9[3:0]

Clock source SEL [3:0]

0000: 25M(OSC2); 0001: 25M/4; 0010: 2M(OSC1);

0011: 2M/8; 0100: 2M/64; 0101: 2M/512; 0110:

2K(OSC0);

1427:1424

DLY/CNT3 Clock Source Select

0111: 2K/8; 1000: 2K/64; 1001: 2K/512; 1010: 2K/4096;

1011: 2K/32768; 1100: 2K/262144; 1101: CNT_END;

1110: External; 1111: Not used

B2

B3

0000: both edge Delay; 0001: falling edge delay;

0010: rising edge delay; 0011: both edge One Shot;

0100: falling edge One Shot; 0101: rising edge One Shot;

0110: both edge freq detect; 0111: falling edge freq detect;

1000: rising edge freq detect; 1001: both edge detect;

1010: falling edge detect; 1011: rising edge detect;

1100: both edge reset CNT; 1101: falling edge reset CNT;

1110: rising edge reset CNT; 1111: high level reset CNT

1431:1428

1439:1432

CNT3 function and edge mode selection

REG_CNT3_Data[7:0]

Data[7:0]

Datasheet

24-Feb-2021

Revision 3.2

161 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 58: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Byte

Register Bit

1440

0: Default Output

1: Inverted Output

CNT3 output pol selection

Reserved

1441

0: bypass

1: after two DFF

1442

CNT3 CNT mode SYNC selection

0: normal

1: DLY function edge detection

B4

1443

CNT3 DLY EDET FUNCTION Selection

Single 3-bit LUT

00000: Matrix A - In2; Matrix B - In1;

Matrix C - In0

(DLY_IN - LOW)

1466,

1447:1444

10000: MatrixA- D; Matrix B - nSET/nRST; Matrix C - CLK

(DLY_IN - LOW)

Single DFF w RST and SET

Single CNT/DLY

00001: Matrix A - DLY_IN (CNT); Matrix B - EXT_CLK

(CNT); Matrix C - NC

(DLY_OUT connected to LUT/DFF)

00010: Matrix A - DLY_IN; Matrix B - In1; Matrix C - In0

(DLY_OUT connected to In2)

CNT/DLY → LUT

10010: Matrix A - DLY_IN; Matrix B - nSET/nRST;

Matrix C - CLK

CNT/DLY → DFF

(DLY_OUT connected to D)

00110: Matrix A - In2; Matrix B - DLY_IN; Matrix C - In0

(DLY_OUT connected to In1)

CNT/DLY → LUT

CNT/DLY → DFF

1466,

1447:1444

10110: Matrix A - D; Matrix B - DLY_IN; Matrix C - CLK

(DLY_OUT connected to nSET/nRST)

B4

01010: Matrix A - In2; Matrix B - In1;

Matrix C - DLY_IN

(DLY_OUT connected to In0)

CNT/DLY → LUT

CNT/DLY → DFF

11010: Matrix A - D; Matrix B - nSET/nRST;

Matrix C - DLY_IN

(DLY_OUT connected to CLK)

00011: Matrix A - In2; Matrix B - In1; Matrix C - In0

(LUT_OUT connected to DLY_IN)

LUT → CNT/DLY

DFF → CNT/DLY

10011: MatrixA- D; Matrix B - nSET/nRST; Matrix C - CLK

(DFF_OUT connected to DLY_IN)

[7]: LUT3[7]/DFF or LATCH Select

0: DFF function; 1: LATCH function

[6]: LUT3[6]/DFF Output Select

0: Q output; 1: QB output

[5]: LUT3[5]/DFF

B5

1455:1448

LUT3_DFF setting

0: nRST from Matrix Output; 1: nSET from Matrix

Output

[4]: LUT3[4]/DFF Initial Polarity Select

0:Low; 1: High

[3:0]: LUT3[3:0]

Datasheet

24-Feb-2021

Revision 3.2

162 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 58: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Byte

Register Bit

Clock source SEL [3:0]

0000: 25M(OSC2); 0001: 25M/4; 0010: 2M(OSC1);

0011: 2M/8; 0100: 2M/64; 0101: 2M/512; 0110:

2K(OSC0);

1459:1456

DLY/CNT4 Clock Source Select

0111: 2K/8; 1000: 2K/64; 1001: 2K/512; 1010: 2K/4096;

1011: 2K/32768; 1100: 2K/262144; 1101: CNT_END;

1110: External; 1111: Not used

B6

0000: both edge Delay; 0001: falling edge delay;

0010: rising edge delay; 0011: both edge One Shot;

0100: falling edge One Shot; 0101: rising edge One Shot;

0110: both edge freq detect; 0111: falling edge freq detect;

1000: rising edge freq detect; 1001: both edge detect;

1010: falling edge detect; 1011: rising edge detect;

1100: both edge reset CNT; 1101: falling edge reset CNT;

1110: rising edge reset CNT; 1111: high level reset CNT

1463:1460

1465:1464

CNT4 function and edge mode selection

CNT4 initial value selection

00: bypass the initial

01: initial 0

10: initial 1

11: initial 1

0: Default Output

1: Inverted Output

1467

1468

1469

CNT4 output pol selection

Reserved

B7

0: bypass

1: after two DFF

CNT4 CNT mode SYNC selection

0: normal

1: DLY function edge detection

1470

CNT4 DLY EDET FUNCTION Selection

1471

1479:1472

1480

Reserved

B8

B9

REG_CNT4_Data[7:0]

Reserved

Data[7:0]

00000: Matrix A - In2; Matrix B - In1;

Matrix C - In0

(DLY_IN - LOW)

1483

1485

1484

1482

1481

Single 3-bit LUT

00100: MatrixA- D; Matrix B - nSET/nRST; Matrix C - CLK

(DLY_IN - LOW)

Single DFF w RST and SET

Datasheet

24-Feb-2021

Revision 3.2

163 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 58: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Byte

Register Bit

00001: Matrix A - DLY_IN (CNT); Matrix B - EXT_CLK

(CNT); Matrix C - NC

(DLY_OUT connected to LUT/DFF)

Single CNT/DLY

CNT/DLY → LUT

CNT/DLY → DFF

00010: Matrix A - DLY_IN; Matrix B - In1; Matrix C - In0

(DLY_OUT connected to In2)

00110: Matrix A - DLY_IN; Matrix B - nSET/nRST;

Matrix C - CLK

(DLY_OUT connected to D)

01010: Matrix A - In2; Matrix B - DLY_IN; Matrix C - In0

(DLY_OUT connected to In1)

CNT/DLY → LUT

CNT/DLY → DFF

1483

1485

1484

1482

1481

01110: Matrix A - D; Matrix B - DLY_IN; Matrix C - CLK

(DLY_OUT connected to nSET/nRST)

10010: Matrix A - In2; Matrix B - In1;

Matrix C - DLY_IN

(DLY_OUT connected to In0)

B9

CNT/DLY → LUT

CNT/DLY → DFF

10110: Matrix A - D; Matrix B - nSET/nRST;

Matrix C - DLY_IN

(DLY_OUT connected to CLK)

00011: Matrix A - In2; Matrix B - In1; Matrix C - In0

(LUT_OUT connected to DLY_IN)

LUT → CNT/DLY

DFF → CNT/DLY

00111: MatrixA- D; Matrix B - nSET/nRST; Matrix C - CLK

(DFF_OUT connected to DLY_IN)

00: bypass the initial

01: initial 0

10: initial 1

1487:1486

1495:1488

CNT5 initial value selection

11: initial 1

[7]: LUT3_11[7]/DFF or LATCH Select

0: DFF function; 1: LATCH function

[6]: LUT3_11[6]/DFF Output Select

0: Q output; 1: QB output

[5]: LUT3_11[5]/DFF

BA

LUT3_11_DFF14 setting

0: nRST from Matrix Output; 1: nSET from Matrix

Output

[4]: LUT3_11[4]/DFF Initial Polarity Select

0:Low; 1: High

[3:0]: LUT3_11[3:0]

Clock source SEL [3:0]

0000: 25M(OSC2); 0001: 25M/4; 0010: 2M(OSC1);

0011: 2M/8; 0100: 2M/64; 0101: 2M/512; 0110:

2K(OSC0);

1499:1496

DLY/CNT5 Clock Source Select

0111: 2K/8; 1000: 2K/64; 1001: 2K/512; 1010: 2K/4096;

1011: 2K/32768; 1100: 2K/262144; 1101: CNT_END;

1110: External; 1111: Not used

BB

BC

0000: both edge Delay; 0001: falling edge delay;

0010: rising edge delay; 0011: both edge One Shot;

0100: falling edge One Shot; 0101: rising edge One Shot;

0110: both edge freq detect; 0111: falling edge freq detect;

1000: rising edge freq detect; 1001: both edge detect;

1010: falling edge detect; 1011: rising edge detect;

1100: both edge reset CNT; 1101: falling edge reset CNT;

1110: rising edge reset CNT; 1111: high level reset CNT

1503:1500

1511:1504

CNT5 function and edge mode selection

REG_CNT5_Data[7:0]

Data[7:0]

Datasheet

24-Feb-2021

Revision 3.2

164 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 58: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Byte

Register Bit

1512

0: Default Output

1: Inverted Output

CNT5 output pol selection

Reserved

1513

0: bypass

1: after two DFF

1514

CNT5 CNT mode SYNC selection

0: normal

1: DLY function edge detection

BD

1515

CNT5 DLY EDET FUNCTION Selection

Single 3-bit LUT

00000: Matrix A - In2; Matrix B - In1;

Matrix C - In0

(DLY_IN - LOW)

1538,

1519:1516

10000: MatrixA- D; Matrix B - nSET/nRST; Matrix C - CLK

(DLY_IN - LOW)

Single DFF w RST and SET

Single CNT/DLY

00001: Matrix A - DLY_IN (CNT); Matrix B - EXT_CLK

(CNT); Matrix C - NC

(DLY_OUT connected to LUT/DFF)

00010: Matrix A - DLY_IN; Matrix B - In1; Matrix C - In0

(DLY_OUT connected to In2)

CNT/DLY → LUT

10010: Matrix A - DLY_IN; Matrix B - nSET/nRST;

Matrix C - CLK

CNT/DLY → DFF

(DLY_OUT connected to D)

00110: Matrix A - In2; Matrix B - DLY_IN; Matrix C - In0

(DLY_OUT connected to In1)

CNT/DLY → LUT

CNT/DLY → DFF

1538,

1519:1516

10110: Matrix A - D; Matrix B - DLY_IN; Matrix C - CLK

(DLY_OUT connected to nSET/nRST)

BD

01010: Matrix A - In2; Matrix B - In1;

Matrix C - DLY_IN

(DLY_OUT connected to In0)

CNT/DLY → LUT

CNT/DLY → DFF

11010: Matrix A - D; Matrix B - nSET/nRST;

Matrix C - DLY_IN

(DLY_OUT connected to CLK)

00011: Matrix A - In2; Matrix B - In1; Matrix C - In0

(LUT_OUT connected to DLY_IN)

LUT → CNT/DLY

DFF → CNT/DLY

10011: MatrixA- D; Matrix B - nSET/nRST; Matrix C - CLK

(DFF_OUT connected to DLY_IN)

[7]: LUT3_12[7]/DFF or LATCH Select

0: DFF function; 1: LATCH function

[6]: LUT3_12[6]/DFF Output Select

0: Q output; 1: QB output

[5]: LUT3_12[5]/DFF

BE

1527:1520

LUT3_12_DFF15 setting

0: nRST from Matrix Output; 1: nSET from Matrix

Output

[4]: LUT3_12[4]/DFF Initial Polarity Select

0:Low; 1: High

[3:0]: LUT3_12[3:0]

Datasheet

24-Feb-2021

Revision 3.2

165 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 58: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Byte

Register Bit

Clock source SEL [3:0]

0000: 25M(OSC2); 0001: 25M/4; 0010: 2M(OSC1);

0011: 2M/8; 0100: 2M/64; 0101: 2M/512; 0110:

2K(OSC0);

1531:1528

DLY/CNT6 Clock Source Select

0111: 2K/8; 1000: 2K/64; 1001: 2K/512; 1010: 2K/4096;

1011: 2K/32768; 1100: 2K/262144; 1101: CNT_END;

1110: External; 1111: Not used

BF

0000: both edge Delay; 0001: falling edge delay;

0010: rising edge delay; 0011: both edge One Shot;

0100: falling edge One Shot; 0101: rising edge One Shot;

0110: both edge freq detect; 0111: falling edge freq detect;

1000: rising edge freq detect; 1001: both edge detect;

1010: falling edge detect; 1011: rising edge detect;

1100: both edge reset CNT; 1101: falling edge reset CNT;

1110: rising edge reset CNT; 1111: high level reset CNT

1535:1532

1537:1536

CNT6 function and edge mode selection

CNT6 initial value selection

00: bypass the initial

01: initial 0

10: initial 1

11: initial 1

0: Default Output

1: Inverted Output

1539

1540

1541

CNT6 output pol selection

Reserved

C0

0: bypass

1: after two DFF

CNT6 CNT mode SYNC selection

0: normal

1: DLY function edge detection

1542

CNT6 DLY EDET FUNCTION Selection

1543

Reserved

C1

C2

1551:1544

REG_CNT6_Data[7:0]

Data[7:0]

00000: Matrix A - In2; Matrix B - In1;

Matrix C - In0

(DLY_IN - LOW)

Single 3-bit LUT

1556:1552

10000: MatrixA- D; Matrix B - nSET/nRST; Matrix C - CLK

(DLY_IN - LOW)

Single DFF w RST and SET

Datasheet

24-Feb-2021

Revision 3.2

166 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 58: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Byte

Register Bit

00001: Matrix A - DLY_IN (CNT); Matrix B - EXT_CLK

(CNT); Matrix C - NC

(DLY_OUT connected to LUT/DFF)

Single CNT/DLY

CNT/DLY → LUT

CNT/DLY → DFF

00010: Matrix A - DLY_IN; Matrix B - In1; Matrix C - In0

(DLY_OUT connected to In2)

10010: Matrix A - DLY_IN; Matrix B - nSET/nRST;

Matrix C - CLK

(DLY_OUT connected to D)

00110: Matrix A - In2; Matrix B - DLY_IN; Matrix C - In0

(DLY_OUT connected to In1)

CNT/DLY → LUT

CNT/DLY → DFF

10110: Matrix A - D; Matrix B - DLY_IN; Matrix C - CLK

(DLY_OUT connected to nSET/nRST)

1556:1552

01010: Matrix A - In2; Matrix B - In1;

Matrix C - DLY_IN

(DLY_OUT connected to In0)

CNT/DLY → LUT

CNT/DLY → DFF

C2

11010: Matrix A - D; Matrix B - nSET/nRST;

Matrix C - DLY_IN

(DLY_OUT connected to CLK)

00011: Matrix A - In2; Matrix B - In1; Matrix C - In0

(LUT_OUT connected to DLY_IN)

LUT → CNT/DLY

DFF → CNT/DLY

10011: MatrixA- D; Matrix B - nSET/nRST; Matrix C - CLK

(DFF_OUT connected to DLY_IN)

0: Default Output

1: Inverted Output

1557

1558

1559

CNT7 output pol selection

Reserved

0: bypass

1: after two DFF

CNT7 CNT mode SYNC selection

[7]: LUT3_13[7]/DFF or LATCH Select

0: DFF function; 1: LATCH function

[6]: LUT3_13[6]/DFF Output Select

0: Q output; 1: QB output

[5]: LUT3_13[5]/DFF

C3

1567:1560

LUT3_13_DFF16 setting

0: nRST from Matrix Output; 1: nSET from Matrix

Output

[4]: LUT3_13[4]/DFF Initial Polarity Select

0:Low; 1: High

[3:0]: LUT3_13[3:0]

Clock source SEL [3:0]

0000: 25M(OSC2); 0001: 25M/4; 0010: 2M(OSC1);

0011: 2M/8; 0100: 2M/64; 0101: 2M/512; 0110:

2K(OSC0);

0111: 2K/8; 1000: 2K/64; 1001: 2K/512; 1010: 2K/4096;

1011: 2K/32768; 1100: 2K/262144; 1101: CNT_END;

1110: External; 1111: Not used

1571:1568

1575:1572

DLY/CNT7 Clock Source Select

C4

0000: both edge Delay; 0001: falling edge delay;

0010: rising edge delay; 0011: both edge One Shot;

0100: falling edge One Shot; 0101: rising edge One Shot;

0110: both edge freq detect; 0111: falling edge freq detect;

1000: rising edge freq detect; 1001: both edge detect;

1010: falling edge detect; 1011: rising edge detect;

1100: both edge reset CNT; 1101: falling edge reset CNT;

1110: rising edge reset CNT; 1111: high level reset CNT

CNT7 function and edge mode selection

Datasheet

24-Feb-2021

Revision 3.2

167 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 58: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Byte

C5

Register Bit

00: bypass the initial

01: initial 0

10: initial 1

1577:1576

CNT7 initial value selection

11: initial 1

0: normal

1: DLY function edge detection

1578

CNT7 DLY EDET FUNCTION Selection

1583:1579

1591:1584

1592

Reserved

C6

REG_CNT7_Data[7:0]

Data[7:0]

2

IO0 I C output expander data

0: IO0 output come from matrix

1: IO0 output is register

2

1593

1594

1595

1596

1597

1598

1599

1600

1601

IO0 I C output expander select

2

IO5 I C output expander data

0: IO5 output come from matrix

1: IO5 output is register

2

IO5 I C output expander select

C7

2

IO6 I C output expander data

0: IO6 output come from matrix

1: IO6 output is register

2

IO6 I C output expander select

2

IO9 I C output expander data

0: IO9 output come from matrix

1: IO9 output is register

2

IO9 I C output expander select

Reserved

2

I C reset bit with reloading NVM into

Data register (soft reset)

0: Keep existing condition

1: Reset execution

C8

C9

2

IO latching enable during I C write

interface

1: disable

0: enable

1602

1607:1603

1615:1608

1619:1616

1620

Reserved

0: overwrite

1: mask

2

I C write mask bits

2

I C slave address

0: from register

1: from IO2

Slave address selection A4

Slave address selection A5

Slave address selection A6

Slave address selection A7

0: from register

1: from IO3

1621

1622

1623

CA

0: from register

1: from IO4

0: from register

1: from IO5

8-bit Pattern ID Byte 0 (From NVM):

ID[23:16]

CB

CC

1631:1624

1639:1632

Reserved

1643:1640

1647:1644

Reserved

CD

Datasheet

24-Feb-2021

Revision 3.2

168 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 58: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Byte

Register Bit

1648

Reserved

1652:1649

CE

1653

Reserved

1654

1655

1657:1656

1658

1659

CF

1660

1661

1662

1663

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

DA

DB

DC

DD

DE

DF

1671:1664

1679:1672

1687:1680

1695:1688

1703:1696

1711:1704

1719:1712

1727:1720

1735:1728

1743:1736

1751:1744

1759:1752

1767:1760

1775:1768

1783:1776

1791:1784

00: 2k register data is unprotected for read;

01: 2k register data is partly protected for read;

10: 2k register data is fully protected for read;

11: reserved

2k Register Read Selection Bits

RPRB[1:0]

1793:1792

1795:1794

00: 2k register data is unprotected for write;

01: 2k register data is partly protected for write;

10: 2k register data is fully protected for write;

11: reserved

2k Register Write Selection Bits

RPRB[3:2]

E0

RPR

1796

1797

1798

1799

Reserved

Datasheet

24-Feb-2021

Revision 3.2

169 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 58: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Byte

Register Bit

00: 2k NVM Configuration data is unprotected for read

and write/erase;

01: 2k NVM Configuration data is fully protected for read;

10: 2k NVM Configuration data is fully protected for

write/erase;

2k NVM Configuration Selection Bits

NPRB[1:0]

1801:1800

11: 2k NVM Configuration data is fully protected for read

and write/erase.

E1

NPR

1802

1803

Reserved

1804

1805

1806

1807

1809:1808

E2

WPR

0: No Software Write Protection enabled (default).

1: Write Protection is set by the state of the WPB[1:0] bits.

1810

Write Protect Register Enable

Reserved

1815:1811

Define the page address which will be erased.

ERSEB[4] = 0 corresponds to the upper 2k NVM used for

chip configuration;

Page Selection for Erase

ERSEB[4:0]

1820:1816

1821

1822

Reserved

E3

E4

0: erase disable

Erase Enable

ERSE

1: cause the NVM erase: full NVM (4k bits) erase for

ERSCHIP = 1 (reg[1973]) if DIS_ERSCHIP = 0

(reg[1972]) or page erase for ERSCHIP = 0 (reg[1973]).

1823

0: RPR/WPR/NPR setting can be changed

1: RPR/WPR/NPR setting cannot be changed

1824

Protection Lock Bit (PRL)

1831:1825

1839:1832

1847:1840

1855:1848

1863:1856

1871:1864

1879:1872

1887:1880

1895:1888

1903:1896

1911:1904

1919:1912

1926:1920

1927

Reserved

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

F0

1932:1928

1934:1933

1935

F1

Reserved

Datasheet

24-Feb-2021

Revision 3.2

170 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Table 58: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Byte

Register Bit

1940:1936

1943:1941

1949:1944

1951:1950

1957:1952

1959:1958

1965:1960

1967:1966

1968

Reserved

F2

Reserved

F3

F4

F5

Reserved

1971:1969

1972

Reserved

F6

1973

1974

Reserved

1975

F7

F8

1983:1976

1991:1984

1992

1993

F9

1995:1994

1999:1996

2000

2001

FA

FB

2002

2006:2003

2007

Reserved

2015:2008

FC

FD

FE

FF

2023:2016

2031:2024

2039:2032

2047:2040

Reserved

Datasheet

24-Feb-2021

Revision 3.2

171 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

19 Package Top Marking System Definition

19.1 TSSOP-20

XXXXXXXXX

$RR###NNNN

YYWW

Device Name

$: Subcon

RR: Revision

###: Programming Code

NNNN: Alphanumeric

Date Code

Pin 1

Identifier

Datasheet

24-Feb-2021

Revision 3.2

172 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

20 Package Information

20.1 PACKAGE OUTLINES FOR TSSOP 20L 173 MIL GREEN PACKAGE

JEDEC MO-220

Side View

Marking View

Side view

20.2 TSSOP HANDLING

Be sure to handle TSSOP package only in a clean, ESD-safe environment. Tweezers or vacuum pick-up tools are suitable for

handling. Do not handle TSSOP package with fingers as this can contaminate the package pins and interface with solder reflow.

Datasheet

24-Feb-2021

Revision 3.2

173 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

20.3 SOLDERING INFORMATION

3

Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 25.74 mm (nominal) for

TSSOP-20 Package. More information can be found at www.jedec.org.

21 Ordering Information

Part Number

Type

SLG46827-AG

20-pin TSSOP

20-pin TSSOP Tape and Reel (4k units)

SLG46827-AGTR

21.1 TAPE AND REEL SPECIFICATIONS

Max Units

per Reel per Box

Leader (min)

Length

Trailer (min)

Nominal

Package Size

(mm)

Reel &

Hub Size

(mm)

Tape

Width Pitch

(mm) (mm)

Part

Package # of

Length

Type

Pins

Pockets

(mm)

TSSOP 20L

173 MIL

Green

20

6.5 x 6.4

4,000

330/100

42

336

42

336

16

8

Package

21.2 CARRIER TAPE DRAWING AND DIMENSIONS

Index Hole Index Hole

PocketBTMPocketBTM Pocket Index Hole Pocket Index Hole

to Tape

Edge

to Pocket Tape Width

Center

(mm)

Length

(mm)

Width

(mm)

Depth

(mm)

Pitch

(mm)

Pitch

(mm)

Diameter

(mm)

Package

Type

(mm)

A0

B0

K0

P0

P1

D0

E

F

W

TSSOP 20L

173 MIL

Green

6.8

6.9

1.6

4

8

1.5

1.75

7.5

16

Package

21.3 TSSOP-20L

Refer to EIA-481 specification

Note: Orientation in carrier: Pin1 is at upper left corner (Quadrant1).

Datasheet

24-Feb-2021

Revision 3.2

174 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

22 Layout Guidelines

22.1 TSSOP-20

Unit: µm

Datasheet

24-Feb-2021

Revision 3.2

175 of 180

CFR0011-120-00

SLG46827-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

with In-System Debug

Glossary

A

ACK

Acknowledge bit

ACMP

ACMPH

ACMPL

Analog Comparator

Analog Comparator High Speed

Analog Comparator Low Power

B

BG

Bandgap

C

CLK

CMO

CNT

Clock

Connection matrix output

Counter

D

DFF

DLY

D Flip-Flop

Delay

E

EC

Electrical Characteristics

Erase Enable

ERSE

ERSR

ESD

EV

Erase Register

Electrostatic discharge

End Value

F

FSM

Finite State Machine

G

GPI

GPIO

GPO

General Purpose Input

General Purpose Input/Output

General Purpose Output

I

IN

IO

Input

Input/Output

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L

LPF

LSB

LUT

LV

Low Pass Filter

Least Significant Bit

Look Up Table

Low Voltage

M

MSB

MTP

MUX

Most Significant Bit

Multiple-Time-Programmable

Multiplexer

N

NPR

nRST

NVM

Non-Volatile Memory Read/Write/Erase Protection

Reset

Non-Volatile Memory

O

OD

OE

Open-Drain

Output Enable

Oscillator

OSC

OUT

Output

P

PD

Power-down

PGen

POR

PP

Pattern Generator

Power-On Reset

Push-Pull

PRL

PWR

P DLY

Protect Lock Bit

Power

Programmable Delay

R

RPR

RPRB

RPRL

R/W

Register Read/Write Protection

Register Read/Write Protection Bit

Register Protection Read/Write/Erase Lock

Read/Write

S

SCL

I²C Clock Input

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SDA

SLA

SMT

SV

I²C Data Input/Output

Slave Address

With Schmitt Trigger

nSET Value

T

TS

Temperature Sensor

Voltage Reference

V

Vref

W

WOSMT

WPB

WPR

WPRE

WS

Without Schmitt Trigger

Write Protect Bit

Write Protection Register

Write Protect Enable

Wake and Sleep Controller

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Revision History

Revision

3.2

Date

Description

Updated table ACMP Specifications at T = -40 °C to +105 °C, V = 2.3 V to 5.5 V Unless

Otherwise Noted

DD

24-Feb-2021

11-Dec-2020

3.1

Updated register definitions: [984], [985]

Final version

Updated table Oscillators Power-On Delay

Updated table Oscillators Frequency Limits

Updated graphs in OSC Accuracy section

Updated graphs ACMPs Typical Propagation Delay vs. Vref

Updated graphs in Oscillators Power-On Delay section

Fixed typos

3.0

12-Oct-2020

Datasheet

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Status Definitions

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Target

Development

This datasheet contains the design specifications for product development. Specifications may

change in any manner without notice.

2.<n>

Preliminary

Qualification

Production

This datasheet contains the specifications and preliminary characterization data for products in

pre-production. Specifications may be changed at any time without notice in order to improve the

design.

3.<n>

4.<n>

Final

This datasheet contains the final specifications for products in volume production. The

specifications may be changed at any time in order to improve the design, manufacturing and

supply. Major specification changes are communicated via Customer Product Notifications.

Datasheet changes are communicated via www.dialog-semiconductor.com.

Obsolete

Archived

This datasheet contains the specifications for discontinued products. The information is provided

for reference only.

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Unless otherwise agreed in writing, the Dialog Semiconductor products (and any associated software) referred to in this document are not designed, authorized or

warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of a

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Datasheet

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CFR0011-120-00


型号：	SLG46827-AG
厂家：	Dialog Semiconductor
描述：	Auto Grade GreenPAK Programmable Mixed-Signal Matrix with In-System Debug
文件：	总180页 (文件大小：2601K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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