SLG46855-AP_技术文档

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

General Description

The SLG46855-A provides a small, low power component for commonly used Mixed-Signal functions. The user creates their

circuit design by programming the one time programmable (OTP) Non-Volatile Memory (NVM) to configure the interconnect

logic, the IO Pins, and the macrocells of the SLG46855-A. This highly versatile device allows a wide variety of Mixed-Signal

functions to be designed within a very small, low power single integrated circuit.

Key Features



Two High Speed General Purpose Analog Comparators

(ACMPxH)

Two Low Power General Purpose Analog Comparators

(ACMPxL)



Analog Temperature Sensor

Power-On Reset (POR)

Read Back Protection (Read Lock)

Power Supply

Two Voltage References (Vref)

 2.5 V (±8 %) to 5 V (±10 %)



Two Vref Outputs



Operating Temperature Range: -40 °C to 105 °C

RoHS Compliant/Halogen-Free

Available Package

14-pin FCQFN: 3.0 mm x 3.0 mm x 0.55 mm, 0.65 mm

pitch

Fifteen Combination Function Macrocells



Three Selectable DFF/LATCH or 2-bit LUTs

One Selectable Programmable Pattern Generator or

2-bit LUT



Nine Selectable DFF/LATCH or 3-bit LUTs

One Selectable Pipe Delay or Ripple Counter, or

3-bit LUT



AEC-Q100 Grade 2 Qualified



One Selectable DFF/LATCH or 4-bit LUTs



Eight Multi-Function Macrocells



Seven Selectable DFF/LATCH or 3-bit LUTs + 8-bit

Delay/Counters



One Selectable DFF/LATCH or 4-bit LUT + 16-bit

Delay/Counter

Serial Communications



I²C Protocol Interface



Programmable Delay with Edge Detector Output

Deglitch Filter or Edge Detector

Three Oscillators (OSC)



2.048 kHz Oscillator

2.048 MHz Oscillator

25 MHz Oscillator

Applications



Infotainment

Advanced Driver Assistance Systems (ADAS)

Instrument clusters

Audio, video, navigation

Datasheet

17-Jun-2021

Revision 3.0

1 of 199

CFR0011-120-00

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Contents

General Description................................................................................................................................................................. 1

Key Features ............................................................................................................................................................................ 1

Applications ............................................................................................................................................................................. 1

1 Block Diagram ...................................................................................................................................................................... 7

2 Pinout .................................................................................................................................................................................... 8

2.1 Pin Configuration - FCQFN- 14L ........................................................................................................................... 8

3 Characteristics ................................................................................................................................................................... 11

3.1 Absolute Maximum Ratings ................................................................................................................................. 11

3.2 Electrostatic Discharge Ratings ........................................................................................................................... 11

3.3 Recommended Operating Conditions ................................................................................................................. 11

3.4 Electrical Characteristics ..................................................................................................................................... 12

3.5 I²C Pins Electrical Characteristics ....................................................................................................................... 15

3.6 Macrocells Current Consumption ........................................................................................................................ 19

3.7 Timing Characteristics ......................................................................................................................................... 19

3.8 Counter/Delay Characteristics ............................................................................................................................. 23

3.9 Oscillator Characteristics ..................................................................................................................................... 23

3.10 ACMP Characteristics ........................................................................................................................................ 24

3.11 Analog Temperature Sensor Characteristics ..................................................................................................... 27

4 User Programmability ....................................................................................................................................................... 29

5 IO Pins ................................................................................................................................................................................ 30

5.1 GPIO Pins ............................................................................................................................................................ 30

5.2 GPI Pins ............................................................................................................................................................... 30

5.3 GPO Pins ............................................................................................................................................................. 30

5.4 Pull-Up/Down Resistors ....................................................................................................................................... 30

5.5 Fast Pull-up/down during Power-up ..................................................................................................................... 30

5.6 GPI Structure ....................................................................................................................................................... 31

5.7 GPIO with I²C Mode IO Structure ........................................................................................................................ 32

5.8 Matrix OE IO Structure ........................................................................................................................................ 33

5.9 GPO Structure ..................................................................................................................................................... 35

5.10 IO Typical Performance ..................................................................................................................................... 36

6 Connection Matrix ............................................................................................................................................................. 41

6.1 Matrix Input Table ............................................................................................................................................... 42

6.2 Matrix Output Table ............................................................................................................................................. 44

6.3 Connection Matrix Virtual Inputs .......................................................................................................................... 47

6.4 Connection Matrix Virtual Outputs ....................................................................................................................... 47

7 Combination Function Macrocells ................................................................................................................................... 48

7.1 2-Bit LUT or D Flip-Flop Macrocells ..................................................................................................................... 48

7.2 2-bit LUT or Programmable Pattern Generator ................................................................................................... 51

7.3 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells ............................................................................................ 53

7.4 4-Bit LUT or D Flip-Flop with Set/Reset Macrocell .............................................................................................. 62

7.5 3-Bit LUT or Pipe Delay/Ripple Counter Macrocell .............................................................................................. 64

8 Multi-Function Macrocells ................................................................................................................................................ 68

8.1 3-Bit LUT or DFF/Latch with 8-Bit Counter/Delay Macrocells .............................................................................. 68

8.2 4-Bit LUT or DFF/Latch with 16-Bit Counter/Delay Macrocell ............................................................................. 78

8.3 CNT/DLY/FSM Timing Diagrams ......................................................................................................................... 81

8.4 Wake and Sleep Controller .................................................................................................................................. 90

9 Analog Comparators ......................................................................................................................................................... 95

9.1 ACMP0H Block Diagram ..................................................................................................................................... 96

9.2 ACMP1H Block Diagram ..................................................................................................................................... 97

9.3 ACMP2L Block Diagram ..................................................................................................................................... 98

9.4 ACMP3L Block Diagram ..................................................................................................................................... 99

9.5 ACMP Typical Performance .............................................................................................................................. 100

10 Programmable Delay/Edge Detector ............................................................................................................................ 103

10.1 Programmable Delay Timing Diagram - Edge Detector Output ....................................................................... 103

11 Additional Logic Function. Deglitch Filter .................................................................................................................. 104

Datasheet

17-Jun-2021

Revision 3.0

2 of 199

CFR0011-120-00

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

12 Voltage Reference ......................................................................................................................................................... 105

12.1 Voltage Reference Overview ........................................................................................................................... 105

12.2 Vref Selection Table ........................................................................................................................................ 105

12.3 Vref Block Diagram ......................................................................................................................................... 106

12.4 Vref Load Regulation ....................................................................................................................................... 107

13 Clocking .......................................................................................................................................................................... 109

13.1 OSC General description ................................................................................................................................. 109

13.2 Oscillator0 (2.048 kHz) .................................................................................................................................... 110

13.3 Oscillator1 (2.048 MHz) ................................................................................................................................... 111

13.4 Oscillator2 (25 MHz) ........................................................................................................................................ 112

13.5 CNT/DLY Clock Scheme ................................................................................................................................. 112

13.6 External Clocking ............................................................................................................................................. 113

13.7 Oscillators Power-On Delay ............................................................................................................................. 114

13.8 Oscillators Accuracy ........................................................................................................................................ 116

14 Power-On Reset ............................................................................................................................................................. 118

14.1 General Operation ........................................................................................................................................... 118

14.2 POR Sequence ................................................................................................................................................ 119

14.3 Macrocells Output States During POR Sequence ........................................................................................... 119

15 I²C Serial Communications Macrocell ......................................................................................................................... 122

15.1 I²C Serial Communications Macrocell Overview ............................................................................................. 122

15.2 I²C Serial Communications Device Addressing ............................................................................................... 122

15.3 I²C Serial General Timing ................................................................................................................................ 123

15.4 I²C Serial Communications Commands .......................................................................................................... 123

15.5 I²C Serial Command Register Map ................................................................................................................. 127

15.6 I²C Additional Options ..................................................................................................................................... 128

16 Analog Temperature Sensor ......................................................................................................................................... 130

17 Register Definitions ....................................................................................................................................................... 133

17.1 Register Map ................................................................................................................................................... 133

18 Package Top Marking Definitions ................................................................................................................................ 191

18.1 FCQFN 14L 3mm x 3 mm 0.65P FCD ............................................................................................................. 191

19 Package Information ..................................................................................................................................................... 192

19.1 Package Outlines for FCQFN 14L 3.0 mm x 3.0 mm x 0.55 mm 0.65P FC Package ..................................... 192

19.2 FCQFN Handling ............................................................................................................................................. 193

19.3 Soldering Information ....................................................................................................................................... 193

20 Ordering Information ..................................................................................................................................................... 193

20.1 Tape and Reel Specifications .......................................................................................................................... 193

20.2 Carrier Tape Drawing and Dimensions ............................................................................................................ 193

21 Layout Guidelines .......................................................................................................................................................... 194

21.1 FCQFN 14L 3 mm x 3 mm x 0.5 mm 0.65P FC Green .................................................................................... 194

Glossary ............................................................................................................................................................................... 195

Revision History .................................................................................................................................................................. 198

Datasheet

17-Jun-2021

Revision 3.0

3 of 199

CFR0011-120-00

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Figures

Figure 1: Block Diagram ............................................................................................................................................................ 7

Figure 2: Steps to Create a Custom GreenPAK Device .......................................................................................................... 29

Figure 3: IO0 GPI Structure Diagram ...................................................................................................................................... 31

Figure 4: GPIO with I²C Mode IO Structure Diagram.............................................................................................................. 32

Figure 5: Matrix OE IO Structure Diagram............................................................................................................................... 33

Figure 6: Matrix OE IO 4x Drive Structure Diagram ................................................................................................................ 34

Figure 7: GPO Register OE 4x Drive Structure Diagram......................................................................................................... 35

Figure 8: Typical High Level Output Current vs. High Level Output Voltage at T = 25 °C ...................................................... 36

Figure 9: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 °C, Full Range...................... 36

Figure 10: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 °C....................................... 37

Figure 11: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 °C, Full Range.................... 37

Figure 12: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 °C....................................... 38

Figure 13: Typical Low Level Output Current vs. Low Level Output Voltage, 3.2x Drive at T = 25 °C, Full Range................. 38

Figure 14: Typical Low Level Output Current vs. Low Level Output Voltage, 3.2x Drive at T = 25 °C.................................... 39

Figure 15: Typical Low Level Output Current vs. Low Level Output Voltage, 4x Drive at T = 25 °C, Full Range.................... 39

Figure 16: Typical Low Level Output Current vs. Low Level Output Voltage, 4x Drive at T = 25 °C....................................... 40

Figure 17: Connection Matrix................................................................................................................................................... 41

Figure 18: Connection Matrix Example.................................................................................................................................... 41

Figure 19: 2-bit LUT0 or DFF0................................................................................................................................................. 48

Figure 20: 2-bit LUT1 or DFF1................................................................................................................................................. 49

Figure 21: 2-bit LUT2 or DFF2................................................................................................................................................. 49

Figure 22: DFF Polarity Operations......................................................................................................................................... 51

Figure 23: 2-bit LUT3 or PGen ................................................................................................................................................ 52

Figure 24: PGen Timing Diagram............................................................................................................................................ 52

Figure 25: 3-bit LUT0 or DFF3................................................................................................................................................. 54

Figure 26: 3-bit LUT1 or DFF4................................................................................................................................................. 55

Figure 27: 3-bit LUT2 or DFF5................................................................................................................................................. 55

Figure 28: 3-bit LUT3 or DFF6................................................................................................................................................. 56

Figure 29: 3-bit LUT4 or DFF7................................................................................................................................................. 56

Figure 30: 3-bit LUT5 or DFF8................................................................................................................................................. 57

Figure 31: 3-bit LUT6 or DFF9................................................................................................................................................. 57

Figure 32: 3-bit LUT7 or DFF10............................................................................................................................................... 58

Figure 33: 3-bit LUT8 or DFF11............................................................................................................................................... 58

Figure 34: DFF Polarity Operations with nReset ..................................................................................................................... 61

Figure 35: DFF Polarity Operations with nSet ......................................................................................................................... 62

Figure 36: 4-bit LUT0 or DFF12............................................................................................................................................... 63

Figure 37: 3-bit LUT16/Pipe Delay/Ripple Counter ................................................................................................................. 65

Figure 38: Example: Ripple Counter Functionality .................................................................................................................. 66

Figure 39: Possible Connections Inside Multi-Function Macrocell .......................................................................................... 68

Figure 40: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT9/DFF13, CNT/DLY1)................................................... 69

Figure 41: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT10/DFF14, CNT/DLY2)................................................. 70

Figure 42: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT11/DFF15, CNT/DLY3)................................................. 71

Figure 43: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT12/DFF16, CNT/DLY4)................................................. 72

Figure 44: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT13/DFF17, CNT/DLY5)................................................. 73

Figure 45: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT14/DFF18, CNT/DLY6)................................................. 74

Figure 46: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT15/DFF19, CNT/DLY7)................................................. 75

Figure 47: 4-bit LUT1 or CNT/DLY0 ........................................................................................................................................ 79

Figure 48: Delay Mode Timing Diagram, Edge Select: Both, Counter Data: 3........................................................................ 81

Figure 49: Delay Mode Timing Diagram for Different Edge Select Mode................................................................................ 82

Figure 50: Counter Mode Timing Diagram without Two DFFs Synced Up.............................................................................. 82

Figure 51: Counter Mode Timing Diagram with Two DFFs Synced Up................................................................................... 83

Figure 52: One-Shot Function Timing Diagram....................................................................................................................... 84

Figure 53: Frequency Detection Mode Timing Diagram.......................................................................................................... 85

Figure 54: Edge Detection Mode Timing Diagram................................................................................................................... 86

Figure 55: Delayed Edge Detection Mode Timing Diagram .................................................................................................... 87

Datasheet

17-Jun-2021

Revision 3.0

4 of 199

CFR0011-120-00

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Figure 56: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP = 0) for Counter Data = 3..... 88

Figure 57: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced On, UP = 0) for Counter Data = 3......... 88

Figure 58: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP = 1) for Counter Data = 3..... 89

Figure 59: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator Is Forced On, UP = 1) for Counter Data = 3 ........ 89

Figure 60: Counter Value, Counter Data = 3........................................................................................................................... 90

Figure 61: Wake/Sleep Controller............................................................................................................................................ 91

Figure 62: Wake/Sleep Timing Diagram, Normal Wake Mode, Counter Reset is Used.......................................................... 92

Figure 63: Wake/Sleep Timing Diagram, Short Wake Mode, Counter Reset is Used............................................................. 92

Figure 64: Wake/Sleep Timing Diagram, Normal Wake Mode, Counter Set is Used.............................................................. 93

Figure 65: Wake/Sleep Timing Diagram, Short Wake Mode, Counter Set is Used................................................................. 93

Figure 66: ACMP0H Block Diagram ........................................................................................................................................ 96

Figure 67: ACMP1H Block Diagram ........................................................................................................................................ 97

Figure 68: ACMP2L Block Diagram......................................................................................................................................... 98

Figure 69: ACMP3L Block Diagram......................................................................................................................................... 99

Figure 70: Typical Propagation Delay vs. Vref for ACMPxH at T = 25 °C, Gain = 1, Hysteresis = 0..................................... 100

Figure 71: Typical Propagation Delay vs. Vref for ACMPxL at T = 25 °C, Gain = 1, Hysteresis = 0..................................... 100

Figure 72: ACMPxH Power-On Delay vs. V_DD. ..................................................................................................................... 101

Figure 73: ACMPxL Power-On Delay vs. V_DD....................................................................................................................... 101

Figure 74: ACMPxH Input Offset Voltage vs. Vref at T = -40 °C to 105 °C ........................................................................... 102

Figure 75: ACMPxL Input Offset Voltage vs. Vref at T = -40 °C to 105 °C............................................................................ 102

Figure 76: Programmable Delay............................................................................................................................................ 103

Figure 77: Edge Detector Output........................................................................................................................................... 103

Figure 78: Deglitch Filter/Edge Detector................................................................................................................................ 104

Figure 79: Voltage Reference Block Diagram ....................................................................................................................... 106

Figure 80: Typical Load Regulation, Vref = 320 mV, T = -40 °C to +105 °C, Buffer - Enabled ............................................. 107

Figure 81: Typical Load Regulation, Vref = 640 mV, T = -40 °C to +105 °C, Buffer - Enabled ............................................. 107

Figure 82: Typical Load Regulation, Vref = 1280 mV, T = -40 °C to +105 °C, Buffer - Enabled ........................................... 108

Figure 83: Typical Load Regulation, Vref = 2016 mV, T = -40 °C to +105 °C, Buffer - Enabled ........................................... 108

Figure 84: Oscillator0 Block Diagram .................................................................................................................................... 110

Figure 85: Oscillator1 Block Diagram .................................................................................................................................... 111

Figure 86: Oscillator2 Block Diagram .................................................................................................................................... 112

Figure 87: Clock Scheme ...................................................................................................................................................... 113

Figure 88: Oscillator Startup Diagram ................................................................................................................................... 114

Figure 89: Oscillator0 Maximum Power-On Delay vs. V_DDat T = 25 °C, OSC0 = 2.048 kHz............................................... 114

Figure 90: Oscillator1 Maximum Power-On Delay vs. V_DDat T = 25 °C, OSC1 = 2.048 MHz.............................................. 115

Figure 91: Oscillator2 Maximum Power-On Delay vs. V_DDat T = 25 °C, OSC2 = 25 MHz................................................... 115

Figure 92: Oscillator0 Frequency vs. Temperature, OSC0 = 2.048 kHz ............................................................................... 116

Figure 93: Oscillator1 Frequency vs. Temperature, OSC1 = 2.048 MHz .............................................................................. 116

Figure 94: Oscillator2 Frequency vs. Temperature, OSC2 = 25 MHz ................................................................................... 117

Figure 95: Oscillators Total Error vs. Temperature................................................................................................................ 117

Figure 96: POR Sequence..................................................................................................................................................... 119

Figure 97: Internal Macrocell States During POR Sequence ................................................................................................ 120

Figure 98: Power-Down......................................................................................................................................................... 121

Figure 99: Basic Command Structure.................................................................................................................................... 123

Figure 100: I²C General Timing Characteristics.................................................................................................................... 123

Figure 101: Byte Write Command, R/W = 0 .......................................................................................................................... 124

Figure 102: Sequential Write Command................................................................................................................................ 124

Figure 103: Current Address Read Command, R/W = 1 ....................................................................................................... 125

Figure 104: Random Read Command................................................................................................................................... 125

Figure 105: Sequential Read Command ............................................................................................................................... 126

Figure 106: Reset Command Timing..................................................................................................................................... 126

Figure 107: Example of I²C Byte Write Bit Masking .............................................................................................................. 129

Figure 108: Analog Temperature Sensor Structure Diagram ................................................................................................ 131

Figure 109: TS Output vs. Temperature, V_DD= 2.3 V to 5.5 V.............................................................................................. 132

Datasheet

17-Jun-2021

Revision 3.0

5 of 199

CFR0011-120-00

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Tables

Table 1: Functional Pin Description........................................................................................................................................... 8

Table 2: Pin Type Definitions................................................................................................................................................... 10

Table 3: Absolute Maximum Ratings....................................................................................................................................... 11

Table 4: Electrostatic Discharge Ratings................................................................................................................................. 11

Table 5: Recommended Operating Conditions........................................................................................................................ 11

Table 6: EC at T = -40 °C to +105 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted............................................................ 12

Table 7: EC of the I²C Pins for DI Mode at T = -40 °C to +105 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted................ 15

Table 8: EC of the I²C Pins for DILV Mode at T = -40 °C to +105 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted............ 16

Table 9: I²C Pins Timing Characteristics, DI Mode, T = -40 °C to +105 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted... 16

Table 10: I²C Pins Timing Characteristics, DILV Mode, T = -40°C to +105°C, V_DD= 2.3V to 5.5V Unless Otherwise Noted 17

Table 11: Typical Current Estimated for Each Macrocell at T = -40 °C to +105 °C................................................................. 19

Table 12: Typical Delay Estimated for Each Macrocell at T = 25 °C ....................................................................................... 19

Table 13: Typical Propagations Delays and Pulse Widths at T = 25 °C.................................................................................. 22

Table 14: Typical Filter Rejection Pulse Width at T = 25 °C.................................................................................................... 23

Table 15: Typical Counter/Delay Offset at T = 25 °C .............................................................................................................. 23

Table 16: Oscillators Frequency Limits, V_DD= 2.3 V to 5.5 V ................................................................................................. 23

Table 17: Oscillators Power-On Delay at T = -40 °C to +105 °C, OSC Power Setting: "Auto Power-On"............................... 24

Table 18: ACMP Specifications at T = -40 °C to +105 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted ............................. 24

Table 19: TS Output vs Temperature (Output Range 1), V_DD= 2.3 V to 5.5 V ....................................................................... 27

Table 20: TS Output vs Temperature (Output Range 2), V_DD= 2.3 V to 5.5 V ....................................................................... 27

Table 21: TS Output Error (Output Range 1), V_DD= 2.3 V to 5.5 V ........................................................................................ 28

Table 22: TS Output Error (Output Range 2), V_DD= 2.3 V to 5.5 V ........................................................................................ 28

Table 23: Matrix Input Table.................................................................................................................................................... 42

Table 24: Matrix Output Table ................................................................................................................................................. 44

Table 25: Connection Matrix Virtual Inputs.............................................................................................................................. 47

Table 26: 2-bit LUT0 Truth Table............................................................................................................................................. 50

Table 27: 2-bit LUT1 Truth Table............................................................................................................................................. 50

Table 28: 2-bit LUT2 Truth Table............................................................................................................................................. 50

Table 29: 2-bit LUT Standard Digital Functions....................................................................................................................... 50

Table 30: 2-bit LUT1 Truth Table............................................................................................................................................. 53

Table 31: 2-bit LUT Standard Digital Functions....................................................................................................................... 53

Table 32: 3-bit LUT0 Truth Table............................................................................................................................................. 59

Table 33: 3-bit LUT1 Truth Table............................................................................................................................................. 59

Table 34: 3-bit LUT2 Truth Table............................................................................................................................................. 59

Table 35: 3-bit LUT3 Truth Table............................................................................................................................................. 59

Table 36: 3-bit LUT4 Truth Table............................................................................................................................................. 59

Table 37: 3-bit LUT5 Truth Table............................................................................................................................................. 59

Table 38: 3-bit LUT6 Truth Table............................................................................................................................................. 59

Table 39: 3-bit LUT7 Truth Table............................................................................................................................................. 59

Table 40: 3-bit LUT8 Truth Table............................................................................................................................................. 60

Table 41: 3-bit LUT Standard Digital Functions....................................................................................................................... 60

Table 42: 4-bit LUT0 Truth Table............................................................................................................................................. 63

Table 43: 4-bit LUT Standard Digital Functions....................................................................................................................... 64

Table 44: 3-bit LUT16 Truth Table........................................................................................................................................... 67

Table 45: 3-bit LUT9 Truth Table............................................................................................................................................. 76

Table 46: 3-bit LUT10 Truth Table........................................................................................................................................... 76

Table 47: 3-bit LUT11 Truth Table........................................................................................................................................... 76

Table 48: 3-bit LUT12 Truth Table........................................................................................................................................... 76

Table 49: 3-bit LUT13 Truth Table........................................................................................................................................... 76

Table 50: 3-bit LUT14 Truth Table........................................................................................................................................... 76

Table 51: 3-bit LUT15 Truth Table........................................................................................................................................... 76

Table 52: 4-bit LUT1 Truth Table............................................................................................................................................. 80

Table 53: 4-bit LUT Standard Digital Functions....................................................................................................................... 80

Table 54: Vref Selection Table .............................................................................................................................................. 105

Table 55: Oscillator Operation Mode Configuration Settings................................................................................................. 109

Table 56: Read/Write Protection Options .............................................................................................................................. 127

Table 57: Register Map ......................................................................................................................................................... 133

Datasheet

17-Jun-2021

Revision 3.0

6 of 199

CFR0011-120-00

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

1

Block Diagram

GPIO8

Vref0

GPIO9

Vref1

Combination Function Macrocells

I²C Serial

Communication

High Speed

Analog

Vref0

V

GPIO7

ACMP3_L

DD

2-bit

LUT2_0

or DFF0

2-bit

LUT2_1

or DFF1

2-bit

LUT2_2

or DFF2

2-bit

LUT2_3

or PGen

FILTER

with Edge

Detect

ACMP0H

ACMP1H

3bit

LUT3_0

or DFF3

3-bit

LUT3_1

or DFF4

3-bit

LUT3_2

or DFF5

3-bit

LUT3_3

or DFF6

GPIO6

ACMP2_L

GPI0

3-bit

LUT3_4

or DFF7

3-bit

LUT3_5

or DFF8

3-bit

LUT3_6

or DFF9

3-bit

LUT3_7

or DFF10

Temperature

Sensor

Low Power

Analog

GPIO0

Low

Power

Vref1

GPIO5

ACMP1_H

3-bit LUT3_16

or Pipe Delay

or Ripple CNT

I²C_SCL

3-bit

LUT3_8

or DFF11

4-bit

LUT4_0

or DFF12

Programmable

Delay

ACMP2L

ACMP3L

GPIO4

ACMP0_H

GPIO1

Multi-Function Macrocells

I²C_SDA

3-bit

3-bitLUT3_12

/DFF16+8bit

CNT/DLY4

3-bitLUT3_9

/DFF13+8bit

CNT/DLY1

LUT3_11 /

DFF15+8bit

CNT/DLY3

LUT3_10/

DFF14+8bit

CNT/DLY2

Oscillators

GPIO2

EXT_

Vref0

3-bit

OSC0

2.048

kHz

OSC1

2.048

MHz

OSC2

25

MHz

4-bitLUT4_1

/DFF20+

16bit

3-bit

POR

GND

LUT3_13 /

DFF17+8bit

CNT/DLY5

LUT3_14

LUT3_15 /

DFF19+8bit

CNT/DLY7

/DFF18+8bit

CNT/DLY6

CNT/DLY0

GPO0

EXT_

Vref1

GPIO3

Figure 1: Block Diagram

Datasheet

17-Jun-2021

Revision 3.0

7 of 199

CFR0011-120-00

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

2

Pinout

2.1 PIN CONFIGURATION - FCQFN- 14L

Pin # Pin Name Pin Functions

1

2

V_DD

Power Supply

GPI0

GPI, SLA_0

3

GPIO0

GPIO1

GPIO2

GPIO3

GPO0

GND

GPIO, SCL

4

GPIO, SDA

5

GPIO with OE, EXT_Vref0, SLA_1

GPIO with OE

6

13

14

7

GPO, EXT_Vref1

1

2

12

11

V_DD

GPIO7

GPIO6

8

Ground

9

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO with OE, ACMP0_H+, SLA_2

GPIO with OE, ACMP1_H+, SLA_3

GPIO with OE, ACMP2_L+

GPIO with OE, ACMP3_L+

GPIO with OE, Vref0_OUT, TS_OUT

GPIO with OE, Vref1_OUT

GPI0

10

11

12

13

14

10

3

4

5

GPIO5

GPIO0

GPIO1

GPIO2

9

8

GPIO4

GND

6

7

Legend:

OE: Output Enable

ACMPx+: ACMPx Positive Input

ACMPx-: ACMPx Negative Input

SCL: I²C Clock Input

FCQFN-14L

(Top View)

SDA: I²C Data Input/Output

Vrefx: Voltage Reference Output

EXT_CLKx: External Clock Input

SLA: Slave Address

TS_OUT: Temperature Output

Table 1: Functional Pin Description

FCQFN

14L Pin # Name

Signal

Name

Input

Options

Output

Options

Function

V_DD

Power Supply

--

Analog Comparator 0

Positive Input

ACMP0_H+

Analog

--

Analog Comparator 1

Positive Input

ACMP1_H+

ACMP2_L+

ACMP3_L+

Analog

--

1

V_DD

Analog Comparator 2

Positive Input

Analog Comparator 3

Positive Input

Digital Input

without Schmitt Trigger

GPI0

General Purpose Input

Digital Input

with Schmitt Trigger

--

2

GPI0

Low Voltage Digital Input

Slave

Address 0

--

Datasheet

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 1: Functional Pin Description(Continued)

FCQFN

14L Pin # Name

Signal

Name

Input

Options

Output

Options

Function

Digital Input

without Schmitt Trigger

Open-Drain NMOS

(3.2x)

General Purpose IO

with OE (Note 1)

GPIO0

SCL

Digital Input

with Schmitt Trigger

3

GPIO0

Low Voltage Digital Input

--

Digital Input

without Schmitt Trigger

I²C Serial Clock

General Purpose IO

I²C Serial Data

Low Voltage Digital Input

Digital Input

without Schmitt Trigger

Open-Drain NMOS

(3.2x)

GPIO1

SDA

Digital Input

with Schmitt Trigger

4

GPIO1

Low Voltage Digital Input

Digital Input

without Schmitt Trigger

--

Low Voltage Digital Input

--

Digital Input

without Schmitt Trigger

Push-Pull (1x) (2x)

General Purpose IO

with OE (Note 1)

GPIO2

Digital Input

with Schmitt Trigger

Open-Drain NMOS

(1x) (2x)

5

6

GPIO2

GPIO3

Low Voltage Digital Input

--

Slave

Address 1

--

Analog Comparator

Negative Input

EXT_VREF0

Analog

--

Digital Input

without Schmitt Trigger

Push-Pull (1x) (2x)

General Purpose IO

with OE (Note 1)

GPIO3

Digital Input

with Schmitt Trigger

Open-Drain NMOS

(1x) (2x)

Low Voltage Digital Input

--

Push-Pull (1x) (2x)

GPO0

General Purpose Output

Open-Drain NMOS

(1x) (2x) (4x)

--

7

8

GPO0

GND

Analog Comparator

Negative Input

EXT_VREF1

GND

Analog

--

Power Supply

--

Digital Input

without Schmitt Trigger

Push-Pull (1x) (2x)

General Purpose IO

with OE (Note 1)

GPIO4

Digital Input

with Schmitt Trigger

Open-Drain NMOS

(1x) (2x) (4x)

9

GPIO4

Low Voltage Digital Input

--

Analog Comparator 0_H

Positive Input

ACMP0_H+

Analog

--

Slave

Address 2

--

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 1: Functional Pin Description(Continued)

FCQFN

14L Pin # Name

Signal

Name

Input

Options

Output

Options

Function

Digital Input

without Schmitt Trigger

Push-Pull (1x) (2x)

General Purpose IO

with OE (Note 1)

GPIO5

Digital Input

with Schmitt Trigger

Open-Drain NMOS

(1x) (2x)

10

GPIO5

Low Voltage Digital Input

--

Analog Comparator 1_H

Positive Input

ACMP1_H+

Analog

--

Slave

Address 3

--

Digital Input

without Schmitt Trigger

Push-Pull (1x) (2x)

General Purpose IO

with OE (Note 1)

GPIO6

ACMP2_L+

GPIO7

Digital Input

with Schmitt Trigger

Open-Drain NMOS

(1x) (2x)

11

12

GPIO6

GPIO7

Low Voltage Digital Input

--

Analog Comparator 2_L

Positive Input

Analog

--

Digital Input

without Schmitt Trigger

Push-Pull (1x) (2x)

General Purpose IO

with OE (Note 1)

Digital Input

with Schmitt Trigger

Open-Drain NMOS

(1x) (2x)

Low Voltage Digital Input

--

Analog Comparator 3_L

Positive Input

ACMP3_L+

Analog

--

Digital Input

without Schmitt Trigger

Push-Pull (1x) (2x)

General Purpose IO

with OE (Note 1)

GPIO8

Vref0

Digital Input

with Schmitt Trigger

Open-Drain NMOS

(1x) (2x)

13

14

GPIO8

GPIO9

Low Voltage Digital Input

Analog

--

Vref0 Output

Digital Input

without Schmitt Trigger

Push-Pull (1x) (2x)

General Purpose IO

with OE (Note 1)

GPIO9

Vref1

Digital Input

with Schmitt Trigger

Open-Drain NMOS

(1x) (2x)

Low Voltage Digital Input

Analog

--

Vref1 Output

Note 1 General Purpose IO's with OE can be used to implement bidirectional signals under user control via

Connection Matrix to OE signal in IO structure.

Table 2: Pin Type Definitions

Pin Type

V_DD

Description

Power Supply

GPI

General Purpose Input

General Purpose Input/Output

General Purpose Output

Ground

GPIO

GPO

GND

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

3

Characteristics

3.1 ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, so functional operation of the device at these or any other conditions beyond those indicated in the operational

sections of the specification are not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect

device reliability.

Table 3: Absolute Maximum Ratings

Parameter

Supply Voltage on V_DDrelative to GND

DC Input Voltage

Min

-0.3

Max

7

Unit

V

GND - 0.5 V

V

_DD+ 0.5 V

V

Maximum Average or DC Current

(Through V_DDor GND pin)

--

90

mA

Push-Pull 1x

--

11

16

Push-Pull 2x

Push-Pull 4x

OD 1x

--

32

Maximum Average or DC Current

(Through pin)

mA

--

11

OD 2x

--

21

OD 4x

--

43

Current at Input Pin

-1.0

--

1.0

1000

150

mA

nA

°C

Input Leakage Current (Absolute Value)

Storage Temperature Range

Junction Temperature

-65

--

°C

Moisture Sensitive Level

1

3.2 ELECTROSTATIC DISCHARGE RATINGS

Table 4: Electrostatic Discharge Ratings

Parameter

Min

2000

1300

Max

--

Unit

V

ESD Protection (Human Body Model)

ESD Protection (Charged Device Model)

--

V

3.3 RECOMMENDED OPERATING CONDITIONS

Table 5: Recommended Operating Conditions

Parameter

Condition

Min

2.3

-40

Max

5.5

Unit

V

Supply Voltage (V_DD

)

Operating Temperature

105

°C

Maximal Voltage Applied to any PIN in High

Impedance State

V_DD+

0.3

--

V

Capacitor Value at V_DD

0.1

0

--

µF

Analog Input Common Mode Range

Allowable Input Voltage atAnalog Pins

V_DD

V

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

3.4 ELECTRICAL CHARACTERISTICS

Table 6: EC at T = -40 °C to +105 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted

Parameter Description

Condition

Min

Typ

Max

Unit

0.7x

V_DD

0.3

+

Logic Input (Note 1)

--

V

0.8x

V_DD

0.3

+

V_IH

HIGH-Level Input Voltage

Logic Input with Schmitt Trigger

Low-Level Logic Input (Note 1)

Logic Input (Note 1)

--

V

V_DD+

1.25

0.3

GND-

0.3

0.3x

V_DD

GND-

0.3

0.2x

V_DD

V_IL

LOW-Level Input Voltage

Logic Input with Schmitt Trigger

GND-

0.3

Low-Level Logic Input (Note 1)

0.5

--

Push-Pull, 1x Drive,

2.17

3.02

5.19

2.23

3.16

5.34

V

_DD= 2.3 V, I_OH= 1 mA

Push-Pull, 1x Drive,

V_DD= 3.3 V, I_OH= 3 mA

--

Push-Pull, 1x Drive,

V_DD= 5.5 V, I_OH= 5 mA

--

Push-Pull, 2x Drive,

--

V

_DD= 2.3 V, I_OH= 1 mA

Push-Pull, 2x Drive,

V_DD= 3.3 V, I_OH= 3 mA

--

V_OH

HIGH-Level Output Voltage

Push-Pull, 2x Drive,

V_DD= 5.5 V, I_OH= 5 mA

--

Push-Pull, 4x Drive

(only for GPO0 and GPIO4),

2.27

3.23

5.41

--

V

_DD= 2.3 V, I_OH= 1 mA

Push-Pull, 4x Drive

(only for GPO0 and GPIO4),

V

_DD= 3.3 V, I_OH= 3mA

Push-Pull, 4x Drive

(only for GPO0 and GPIO4),

V_DD= 5.5 V, I_OH= 5 mA

Push-Pull, 1x Drive,

V_DD= 2.3 V, I_OL= 1 mA

--

0.100

0.227

0.272

0.049

0.112

V

Push-Pull, 1x Drive,

V_DD= 3.3 V, I_OL= 3 mA

Push-Pull, 1x Drive,

V_DD= 5.5 V, I_OL= 5 mA

V_OL

LOW-Level Output Voltage

Push-Pull, 2x Drive,

V_DD= 2.3 V, I_OL= 1 mA

Push-Pull, 2x Drive,

V_DD= 3.3 V, I_OL= 3 mA

Datasheet

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Revision 3.0

12 of 199

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SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 6: EC at T = -40 °C to +105 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted (Continued)

Parameter Description

Condition

Min

Typ

Max

Unit

Push-Pull, 2x Drive,

V_DD= 5.5 V, I_OL= 5 mA

--

0.137

V

Push-Pull, 4x Drive

(only for GPO0 and GPIO4),

V_DD= 2.3 V, I_OL= 1 mA

--

0.023

0.055

0.067

V

Push-Pull, 4x Drive

(only for GPO0 and GPIO4),

V_DD= 3.3 V, I_OL= 3 mA

Push-Pull, 4x Drive

(only for GPO0 and GPIO4),

V_DD= 5.5 V, I_OL= 5 mA

NMOS OD, 1x Drive,

--

0.042

0.093

0.117

0.020

0.047

0.058

V

_DD= 2.3 V, I_OL= 1 mA

NMOS OD, 1x Drive,

V_DD= 3.3 V, I_OL= 3 mA

NMOS OD, 1x Drive,

V_DD= 5.5 V, I_OL= 5 mA

V_OL

LOW-Level Output Voltage

NMOS OD, 2x Drive,

V_DD= 2.3 V, I_OL= 1 mA

NMOS OD, 2x Drive,

V

_DD= 3.3 V, I_OL= 3 mA

NMOS OD, 2x Drive,

V_DD= 5.5 V, I_OL= 5 mA

NMOS OD, 4x Drive

(only for GPO0 and GPIO4),

--

0.009

0.022

0.027

V

_DD= 2.3 V, I_OL= 1 mA

NMOS OD, 4x Drive

(only for GPO0 and GPIO4),

V_DD= 3.3 V, I_OL= 3 mA

NMOS OD, 4x Drive

(only for GPO0 and GPIO4),

V

_DD= 5.5 V, I_OL= 5 mA

Push-Pull, 1x Drive,

V_DD= 2.3 V, V_OH= V_DD- 0.2 V

1.44

7.75

--

mA

Push-Pull, 1x Drive,

V_DD= 3.3 V, V_OH= 2.4 V

Push-Pull, 1x Drive,

V_DD= 5.5 V, V_OH= 2.75 V

26.98

2.82

Push-Pull, 2x Drive,

V_DD= 2.3 V, V_OH= V_DD- 0.2 V

HIGH-Level Output Pulse

Current (Note 2)

Push-Pull, 2x Drive,

V_DD= 3.3 V, V_OH= 2.4 V

I_OH

15.12

51.97

Push-Pull, 2x Drive,

V_DD= 5.5 V, V_OH= 2.75 V

Push-Pull, 4x Drive

(only for GPO0 and GPIO4),

V_DD= 2.3 V, V_OH= V_DD- 0.2 V

5.47

--

mA

Push-Pull, 4x Drive

(only for GPO0 and GPIO4),

V_DD= 3.3 V, V_OH= 2.4 V

28.97

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 6: EC at T = -40 °C to +105 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted (Continued)

Parameter Description

Condition

Min

Typ

Max

Unit

Push-Pull, 4x Drive

(only for GPO0 and GPIO4),

V_DD= 5.5 V, V_OH= 2.75 V

HIGH-Level Output Pulse

Current (Note 2)

I_OH

97.85

--

mA

Push-Pull, 1x Drive,

V_DD= 2.3 V, V_OL= 0.2 V

1.92

5.01

7.10

3.84

9.96

13.96

--

mA

Push-Pull, 1x Drive,

V_DD= 3.3 V, V_OL= 0.4 V

Push-Pull, 1x Drive,

V_DD= 5.5 V, V_OL= 0.4 V

Push-Pull, 2x Drive,

V_DD= 2.3 V, V_OL= 0.2 V

Push-Pull, 2x Drive,

V_DD= 3.3 V, V_OL= 0.4 V

Push-Pull, 2x Drive,

V_DD= 5.5 V, V_OL= 0.4 V

Push-Pull, 4x Drive

(only for GPO0 and GPIO4),

7.72

20.12

28.34

--

mA

V

_DD= 2.3 V, V_OL= 0.2 V

Push-Pull, 4x Drive

(only for GPO0 and GPIO4),

V

_DD= 3.3 V, V_OL= 0.4 V

Push-Pull, 4x Drive

(only for GPO0 and GPIO4),

V_DD= 5.5 V, V_OL= 0.4 V

LOW-Level Output Pulse

Current (Note 2)

I_OL

NMOS OD, 1x Drive,

4.71

12.21

16.95

9.24

--

mA

V

_DD= 2.3 V, V_OL= 0.2 V

NMOS OD, 1x Drive,

V_DD= 3.3 V, V_OL= 0.4 V

NMOS OD, 1x Drive,

V_DD= 5.5 V, V_OL= 0.4 V

NMOS OD, 2x Drive,

V

_DD= 2.3 V, V_OL= 0.2 V

NMOS OD, 2x Drive,

V_DD= 3.3 V, V_OL= 0.4 V

23.68

32.64

NMOS OD, 2x Drive,

V_DD= 5.5 V, V_OL= 0.4 V

NMOS OD, 4x Drive

(only for GPO0 and GPIO4),

V_DD= 2.3 V, V_OL= 0.2 V

18.96

49.08

68.27

--

mA

NMOS OD, 4x Drive

(only for GPO0 and GPIO4),

V_DD= 3.3 V, V_OL= 0.4 V

NMOS OD, 4x Drive

(only for GPO0 and GPIO4),

V_DD= 5.5 V, V_OL= 0.4 V

From V_DDrising past PON_THR

T_RAMP= 10 ms

,

T_SU

Startup Time

--

1.4

2.1

ms

V

PON_THR

Power-On Threshold

V_DDLevel Required to Start Up the Chip

1.56

1.84

2.03

Datasheet

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 6: EC at T = -40 °C to +105 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted (Continued)

Parameter Description

Condition

Min

Typ

Max

Unit

V_DDLevel Required to Switch Off the

Chip

POFF_THRPower-Off Threshold

0.83

1.16

1.63

V

1 M for Pull-up: V_IN= GND

1 M for Pull-down: V_IN= V_DD

100 k for Pull-up: V_IN= GND

100 k for Pull-down: V_IN= V_DD

10 k For Pull-up: V_IN= GND

10 k for Pull-down: V_IN= V_DD

0.84

84

7

1.08

108

10

1.43

1.44

144

14

MΩ

kΩ

pF

nA

Pull-up or Pull-down

Resistance

R_PULL

7

10

14

C_IN

Input Capacitance

3

Vin = V_DD, V_DD= 2.3 V, All Pins

Vin = V_DD, V_DD= 3.3 V, All Pins

Vin = V_DD, V_DD= 5.5 V, All Pins

Vin = 0, V_DD= 2.3 V, All Pins

Vin = 0, V_DD= 3.3 V, All Pins

Vin = 0, V_DD= 5.5 V, All Pins

Vin = V_DD, V_DD= 2.3 V, All Pins

Vin = V_DD, V_DD= 3.3 V, All Pins

Vin = V_DD, V_DD= 5.5 V, All Pins

Vin = 0, V_DD= 2.3 V, All Pins

Vin = 0, V_DD= 3.3 V, All Pins

Vin = 0, V_DD= 5.5 V, All Pins

Vin = V_DD, V_DD= 2.3 V, All Pins

Vin = V_DD, V_DD= 3.3 V, All Pins

Vin = V_DD, V_DD= 5.5 V, All Pins

Vin = 0, V_DD= 2.3 V, All Pins

Vin = 0, V_DD= 3.3 V, All Pins

Vin = 0, V_DD= 5.5 V, All Pins

--

4.61

5.00

6.56

1.41

1.58

4.44

4.72

5.10

6.64

1.46

1.62

4.48

4.64

5.01

6.52

1.43

1.59

4.43

--

Logic Input without Schmitt

Trigger (Floating) Leakage

Logic Input with Schmitt

Trigger (Floating) Leakage

I_LKG

Low-Level Logic Input

(Floating) Leakage

Note 1 No hysteresis.

Note 2 DC or average current through any pin should not exceed value given in Absolute Maximum Conditions.

3.5 I²C PINS ELECTRICAL CHARACTERISTICS

Table 7: EC of the I²C Pins for DI Mode at T = -40 °C to +105 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted

Fast-Mode

Fast-Mode Plus

Parameter Description

Condition

Unit

Min

Max

Min

Max

LOW-level Input

Voltage

V_IL

-0.5

0.3xV_DD

-0.5

0.3xV_DD

V

HIGH-level Input

Voltage

V_IH

0.7xV_DD

5.5

--

0.7xV_DD

5.5

--

Hysteresis of

Schmitt Trigger

Inputs

V_HYS

0.05xV_DD

V

Datasheet

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Revision 3.0

15 of 199

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SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 7: EC of the I²C Pins for DI Mode at T = -40 °C to +105 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted(Continued)

Fast-Mode

Fast-Mode Plus

Parameter Description

Condition

Unit

Min

Max

Min

Max

(Open-Drain or open

collector) at 3 mAsink current

V_DD> 2 V

LOW-Level Output

Voltage 1

V_OL1

0

0.4

0

0.4

V

(Open-Drain or open

collector) at 2 mAsink current

V_DD≤ 2 V

LOW-Level Output

Voltage 2

V_OL2

0.2xV_DD

250

0

0.2xV_DD

120

V

Output Fall Time

from V_IHminto

V_ILmax

14x

(V_DD/5.5V)

10x

(V_DD/5.5V)

t_of

ns

(Note 1)

Input Current each

IO Pin

I_i

0.1xV_DD< V_I< 0.9xV_DDmax

-10

--

+10

10

-10

--

+10

10

µA

Capacitance for

each IO Pin

C_i

pF

Note 1 Does not meet standard I²C specifications: t_of= 20x(V_DD/5.5V) (min).

Note 2 For Fast-mode Plus SDA pin must be configured as NMOS 3.2x Open-Drain, see register [796] in section 17.

Table 8: EC of the I²C Pins for DILV Mode at T = -40 °C to +105 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted

Fast-Mode

Parameter Description

Condition

Unit

Min

GND-0.3

1.25

Max

0.5

V_IL

V_IH

LOW-level Input Voltage (Note 1)

V

HIGH-level Input Voltage (Note 1)

V_DD+0.3

Hysteresis of Schmitt Trigger

Inputs

V_HYS

0.05xV_DD

0

--

V

(Open-Drain or open collector) at 3mA

sink current

V_DD> 2 V

V_OL1

LOW-Level Output Voltage 1

LOW-Level Output Voltage 2

0.4

(Open-Drain or open collector) at 2 mA

sink current

V_DD≤ 2 V

V_OL2

0

0.2xV_DD

250

V

Output Fall Time from V_IHminto

V_ILmax

(Note 1)

14x

(V_DD/5.5V)

t_of

ns

I_i

Input Current each IO Pin

0.1xV_DD< V_I< 0.9xV_DDmax

-10

--

+10

10

µA

C_i

Capacitance for each IO Pin

pF

Note 1 Does not meet standard I²C specifications: V_IL= -0.5 V (min), V_IL= 0.3xV_DD(max), V_IH= 0.7xV_DD(min), V_IH= 5.5 V

(max), t_of= 20x(V_DD/5.5V) (min).

Table 9: I²C Pins Timing Characteristics, DI Mode, T = -40 °C to +105 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted

Speed

Parameter Description

Condition

400 kHz

1 MHz

Typ

--

Unit

Min

--

Typ

--

Max

400

--

Min

--

Max

1000

--

F_SCL

t_LOW

Clock Frequency, SCL

Clock Pulse Width Low

kHz

ns

1300

--

500

--

Datasheet

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Revision 3.0

16 of 199

CFR0011-120-00

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 9: I²C Pins Timing Characteristics, DI Mode, T = -40 °C to +105 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted

Speed

Parameter Description

Condition

400 kHz

1 MHz

Unit

Min

600

--

Typ

--

Max

--

Min

260

--

Typ

--

Max

--

t_HIGH

Clock Pulse Width High

ns

V_DD= 2.3 V

V_DD= 3.3 V

V_DD= 5.5 V

--

90

--

87

Input Filter Spike

Suppression (SCL, SDA)

(Note 1)

t_I

--

90

--

87

ns

--

90

--

87

t_AA

Clock Low to Data Out Valid

--

900

--

450

ns

Bus Free Time between

Stop and Start

t_BUF

1300

--

500

--

t_{HD_STA}

t_{SU_STA}

Start Hold Time

600

0

--

260

0

--

ns

Start Set-up Time

Rising Edge

Falling Edge

--

t_{HD_DAT}

t_{SU_DAT}

Data Hold Time

0

--

0

--

Data Set-up Time

100

--

50

--

C = 15 pF

C = 100 pF

C = 400 pF

C = 15 pF

C = 100 pF

C = 400 pF

300

--

120

--

t_R

Inputs Rise Time

Inputs Fall Time

--

t_F

--

t_{SU_STO}

t_DH

Stop Set-up Time

600

260

Data Out Hold Time

50

--

50

--

Note 1 Does not meet standard I²C specifications: t_I= 95 ns for V_DD= 2.3 V, t_I= 95 ns for V_DD= 3.3 V, t_I= 111 ns for V_DD

5.5V for 400 kHz; t_I= 168 ns for V_DD= 2.3 V, t_I= 157 ns for V_DD= 3.3 V, t_I= 156 ns for V_DD= 5.5 V for 1 MHz.

=

Note 2 Timing diagram can be found in the Figure 100.

Note 3 Please follow official I²C spec UM10204.

Table 10: I²C Pins Timing Characteristics, DILV Mode, T = -40°C to +105°C, V_DD= 2.3V to 5.5V Unless Otherwise Noted

Speed

Parameter Description

Condition

400 kHz

Unit

Min

--

Typ

--

Max

400

--

F_SCL

t_LOW

t_HIGH

Clock Frequency, SCL

kHz

ns

Clock Pulse Width Low

Clock Pulse Width High

1300

600

--

ns

V_DD= 2.3 V

V_DD= 3.3 V

V_DD= 5.5 V

--

300

235

185

900

--

Input Filter Spike Suppression (SCL,

SDA) (Note 1)

t_I

--

ns

--

t_AA

Clock Low to Data Out Valid

Bus Free Time between Stop and Start

Start Hold Time

--

ns

t_BUF

1300

600

--

t_{HD_STA}

t_{SU_STA}

--

Start Set-up Time

--

Datasheet

17-Jun-2021

Revision 3.0

17 of 199

CFR0011-120-00

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 10: I²C Pins Timing Characteristics, DILV Mode, T = -40°C to +105°C, V_DD= 2.3V to 5.5V Unless Otherwise Noted

Speed

Parameter Description

Condition

400 kHz

Unit

Min

255

0

Typ

--

Max

--

Rising Edge

Falling Edge

ns

t_{HD_DAT}

t_{SU_DAT}

Data Hold Time (Note 1)

--

Data Set-up Time

Inputs Rise Time

100

--

C = 15 pF

C = 100 pF

C = 400pF

C = 15 pF

C = 100 pF

C = 400 pF

--

300

--

t_R

--

t_F

Inputs Fall Time

--

t_{SU_STO}

t_DH

Stop Set-up Time

600

50

--

Data Out Hold Time

--

Note 1 Does not meet standard I²C specifications: t_I= 95 ns for V_DD= 2.3 V, t_I= 95 ns for V_DD= 3.3 V, t_I= 111 ns for V_DD

5.5 V; t_{HD_DAT}= 0 ns (min) for Rising Edge.

=

Note 2 Timing diagram can be found in the Figure 100.

Note 3 Please follow official I²C spec UM10204.

Note 4 When SCL Input is in Low-Level Logic mode max frequency is 400 kHz.

Datasheet

17-Jun-2021

Revision 3.0

18 of 199

CFR0011-120-00

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

3.6 MACROCELLS CURRENT CONSUMPTION

Table 11: Typical Current Estimated for Each Macrocell at T = -40 °C to +105 °C

Parameter

Description Note

Chip Quiescent

V_DD= 2.5 V V_DD= 3.3 V V_DD= 5.0 V

Unit

µA

0.34

7.61

1.39

0.39

7.67

1.42

0.46

7.88

1.51

Vref0, SourceNone

Vref1, SourceNone

µA

OSC2 25 MHz, pre-divider = 1, second

divider = 1

50.46

33.46

30.35

20.64

18.56

18.18

0.62

62.63

39.91

35.75

21.99

19.21

18.71

0.66

90.60

55.47

49.03

24.94

20.61

19.84

0.77

µA

OSC2 25 MHz, pre-divider = 4, second

divider = 1

OSC2 25 MHz, pre-divider = 8, second

divider = 1

OSC1 2.048 MHz, pre-divider = 1,

second divider = 1

OSC1 2.048 MHz, pre-divider = 4,

second divider = 1

OSC1 2.048 MHz, pre-divider = 8,

second divider = 1

OSC0 2.048 kHz, pre-divider= 1, second

divider = 1

I_DD

Current

OSC0 2.048 kHz, pre-divider= 4, second

divider = 1

0.62

0.66

0.76

OSC0 2.048 kHz, pre-divider= 8, second

divider = 1

0.61

0.66

0.76

Temperature Sensor, output range 1

(0.62 V to 0.99 V)

14.80

14.94

37.36

48.95

14.87

15.02

38.10

50.26

15.43

40.42

53.90

Temperature Sensor, output range 2

(0.75 V to 1.2 V)

All ACMPs (includes internal Vref,

Vin+ = 0, Vref = 32 mV)

All ACMPxH (includes internal Vref,

Vin+ = 0, Vref = 32 mV)

ACMP0H 100µA Enabled

(includes internal Vref, Vin+ = 0,

Vref = 32 mV)

35.95

1.89

36.65

1.93

38.92

2.04

µA

Any ACMPxL (includes internal Vref,

Vin+ = 0, Vref = 32 mV)

3.7 TIMING CHARACTERISTICS

Table 12: Typical Delay Estimated for Each Macrocell at T = 25 °C

V_DD= 2.5 V

V_DD= 3.3 V

V_DD= 5 V

Note

Parameter Description

Unit

Rising Falling Rising Falling Rising Falling

Digital Input to PP 1x

Digital Input to PP 2x

tpd

Delay

23

22

26

25

17

16

19

16

12

15

14

ns

Digital Input with Schmitt Trigger to

PP 1x

tpd

Delay

24

27

18

21

14

15

ns

Low Voltage Digital Input to PP 1x

Digital input to NMOS 1x

tpd

Delay

38

--

241

24

26

--

164

18

--

104

13

ns

Digital input to NMOS 2x

--

23

--

17

--

13

Datasheet

17-Jun-2021

Revision 3.0

19 of 199

CFR0011-120-00

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 12: Typical Delay Estimated for Each Macrocell at T = 25 °C(Continued)

V_DD= 2.5 V

V_DD= 3.3 V

V_DD= 5 V

Note

Parameter Description

Unit

Rising Falling Rising Falling Rising Falling

Digital input to NMOS 4x

Output enable from Pin, OE Hi-Z to 1

Output enable from Pin, OE Hi-Z to 0

PP 1x 3 State Hi-Z to 1

tpd

Delay

--

23

--

17

--

12

--

13

--

ns

23

--

16

--

22

--

16

--

12

--

22

--

16

--

12

--

PP 1x 3 State Hi-Z to 0

22

--

16

--

12

--

PP 2x 3 State Hi-Z to 1

21

--

16

--

12

--

PP 2x 3 State Hi-Z to 0

21

18

15

21

24

23

21

19

18

21

22

19

27

23

21

25

19

17

23

15

13

11

15

17

16

15

13

15

16

13

19

17

15

18

14

12

16

11

9

LATCH Q

16

19

25

22

24

19

22

19

22

23

27

25

21

17

20

26

11

14

17

16

15

17

14

16

14

16

20

18

15

12

14

18

8

LATCH nQ

9

7

LATCH nRESET High Q

LATCH nRESET High nQ

LATCH nRESET Low Q

LATCH nRESET Low nQ

LATCH nSET High Q

12

11

12

9

10

12

10

9

LATCH nSET High nQ

11

9

LATCH nSET Low Q

9

LATCH nSET Low nQ

10

11

9

Multi-Function LATCH Q

Multi-Function LATCH nQ

Multi-Function LATCH nRESET Q

Multi-Function LATCH nRESET nQ

Multi-Function LATCH nSET Q

Multi-Function LATCH nSET nQ

LATCH3, LATCH12 First Q

LATCH3, LATCH12 First nQ

LATCH3, LATCH12 First nRESET High Q

9

11

14

13

10

8

14

11

10

13

9

10

13

8

11

LATCH3, LATCH12 First nRESET High

nQ

tpd

Delay

24

23

26

25

23

17

16

18

16

12

11

13

12

11

ns

LATCH3, LATCH12 First nRESET Low Q

LATCH3, LATCH12 First nRESET Low

nQ

LATCH3, LATCH12 First nSET High Q

LATCH3, LATCH12 First nSET High nQ

LATCH3, LATCH12 First nSET Low Q

LATCH3, LATCH12 First nSET Low nQ

LATCH3, LATCH12 Second Q

tpd

Delay

21

23

21

19

20

22

20

23

19

18

15

17

16

15

13

14

16

14

16

13

10

12

11

10

9

11

10

11

9

ns

LATCH3, LATCH12 Second nQ

10

9

LATCH3, LATCH12 Second nRESET

High Q

LATCH3, LATCH12 Second nRESET

High nQ

tpd

Delay

--

22

--

16

--

11

--

ns

23

17

12

Datasheet

17-Jun-2021

Revision 3.0

20 of 199

CFR0011-120-00

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 12: Typical Delay Estimated for Each Macrocell at T = 25 °C(Continued)

V_DD= 2.5 V

V_DD= 3.3 V

V_DD= 5 V

Note

Parameter Description

Unit

Rising Falling Rising Falling Rising Falling

LATCH3, LATCH12 Second nRESET

Low Q

LATCH3, LATCH12 Second nRESET

Low nQ

LATCH3, LATCH12 Second nSET High

Q

tpd

Delay

--

25

--

18

--

12

--

ns

26

20

18

14

13

10

--

LATCH3, LATCH12 Second nSET High

nQ

tpd

Delay

--

23

--

20

--

16

--

14

--

11

--

10

--

ns

LATCH3, LATCH12 Second nSET Low Q

LATCH3, LATCH12 Second nSET Low

nQ

22

16

11

2-bit LUT

tpd

tw

Delay

Width

Delay

15

16

19

18

46

21

48

19

211

231

18

29

27

18

24

29

26

25

26

25

17

18

--

16

17

21

47

23

46

20

212

235

16

22

29

16

24

23

33

41

33

38

44

17

16

20

--

11

13

33

15

34

13

156

170

13

20

13

17

21

19

18

19

18

12

13

--

11

12

15

34

17

34

14

157

173

11

16

21

11

17

23

29

23

27

32

12

11

14

--

7

8

ns

3-bit LUT

4-bit LUT

9

Multi-Function 3-bit LUT

Multi-Function 3-bit LUT, CNT Delay

Multi-Function 4-bit LUT

Multi-Function 4-bit LUT, CNT Delay

Edge detect

9

11

24

12

24

9

23

10

23

9

Edge detect

115

124

9

115

126

8

Edge detect Delayed

Ripple CNT CLK DOWN Q0

Ripple CNT CLK DOWN Q1

Ripple CNT CLK DOWN Q2

Ripple CNT CLK UP Q0

Ripple CNT CLK UP Q1

Ripple CNT CLK UP Q2

Ripple CNT nSET DOWN Q0

Ripple CNT nSET DOWN Q1

Ripple CNT nSET DOWN Q2

Ripple CNT nSET UP Q0

Ripple CNT nSET UP Q1

Ripple CNT nSET UP Q2

DFF Q

tpd

14

9

11

14

8

12

15

14

13

14

13

8

12

16

21

20

16

19

22

8

DFF nQ

9

8

DFF nRESET High Q

DFF nRESET High nQ

DFF nRESET Low Q

DFF nRESET Low nQ

DFF nSET High Q

--

10

--

21

--

15

--

10

--

22

--

16

--

11

--

23

21

--

17

15

--

12

10

--

DFF nSET High nQ

20

--

14

--

10

--

DFF nSET Low Q

23

16

12

Datasheet

17-Jun-2021

Revision 3.0

21 of 199

CFR0011-120-00

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 12: Typical Delay Estimated for Each Macrocell at T = 25 °C(Continued)

V_DD= 2.5 V

V_DD= 3.3 V

V_DD= 5 V

Note

Parameter Description

Unit

Rising Falling Rising Falling Rising Falling

DFF nSET Low nQ

tpd

Delay

--

19

20

--

22

19

26

--

13

14

--

16

13

19

--

9

11

9

ns

Multi-Function DFF Q

Multi-Function DFF nQ

9

Multi-Function DFF nRESET Q

Multi-Function DFF nRESET nQ

Multi-Function DFF nSET Q

Multi-Function DFF nSET nQ

DFF3, DFF12 First Q

--

13

--

26

--

19

--

13

--

26

18

22

--

19

13

15

--

14

9

18

19

--

13

14

--

9

DFF3, DFF12 First nQ

9

DFF3, DFF12 First nRESET High Q

DFF3, DFF12 First nRESET High nQ

DFF3, DFF12 First nRESET Low Q

DFF3, DFF12 First nRESET Low nQ

DFF3, DFF12 First nSET High Q

DFF3, DFF12 First nSET High nQ

DFF3, DFF12 First nSET Low Q

DFF3, DFF12 First nSET Low nQ

DFF3, DFF12 Second Q

--

11

--

22

--

16

--

11

--

24

--

17

--

12

--

25

22

--

18

16

--

12

11

--

22

--

15

--

11

--

24

--

17

--

12

--

24

21

20

21

--

17

15

14

15

--

12

10

--

20

21

--

14

15

--

10

11

--

DFF3, DFF12 Second nQ

DFF3, DFF12 Second nRESET High Q

DFF3, DFF12 Second nRESET High nQ

DFF3, DFF12 Second nRESET Low Q

DFF3, DFF12 Second nRESET Low nQ

DFF3, DFF12 Second nSET High Q

DFF3, DFF12 Second nSET High nQ

DFF3, DFF12 Second nSET Low Q

DFF3, DFF12 Second nSET Low nQ

PGen CLK

22

--

16

--

11

--

23

--

17

--

12

--

24

22

--

17

15

--

12

11

--

21

--

15

--

10

--

24

--

17

--

12

--

23

16

21

--

17

11

15

--

12

8

16

--

12

--

8

PGen nRESET Hi-Z to 0

--

11

--

PGen nRESET Hi-Z to 1

20

23

30

160

141

14

16

22

109

99

10

11

16

68

66

Pipe Delay Out

20

28

140

159

15

21

98

108

10

15

65

68

Pipe Delay nRESET Out

Filter Q

Filter nQ

Table 13: Typical Propagations Delays and Pulse Widths at T = 25 °C

Parameter

Description

Note

V_DD= 2.5 V V_DD= 3.3V V_DD= 5.0V Unit

221 163 119 ns

tw

Pulse Width, 1 cell mode: (any)edge detect, edge detect output

Datasheet

17-Jun-2021

Revision 3.0

22 of 199

CFR0011-120-00

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 13: Typical Propagations Delays and Pulse Widths at T = 25 °C(Continued)

Parameter

tw

Description

Note

V_DD= 2.5 V V_DD= 3.3V V_DD= 5.0V Unit

Pulse Width, 2 cell mode: (any)edge detect, edge detect output

Pulse Width, 3 cell mode: (any)edge detect, edge detect output

Pulse Width, 4 cell mode: (any)edge detect, edge detect output

438

652

869

18

322

480

639

13

234

349

464

9

ns

tw

time1

time2

Delay, 1 cell

Delay, 2 cell

Delay, 3 cell

Delay, 4 cell

Delay, 1 cell

Delay, 2 cell

Delay, 3 cell

Delay, 4 cell

mode: (any)edge detect, edge detect output

mode: both edge delay, edge detect output

18

13

9

18

13

9

18

13

9

240

455

672

888

176

334

493

673

128

243

358

473

Table 14: Typical Filter Rejection Pulse Width at T = 25 °C

Parameter

V_DD= 2.5 V V_DD= 3.3V V_DD= 5.0V

< 127 < 86 < 54

Unit

Filtered Pulse Width

ns

3.8 COUNTER/DELAY CHARACTERISTICS

Table 15: Typical Counter/Delay Offset at T = 25 °C

Parameter

OSC Freq

25 MHz

OSC Power

auto

V_DD= 2.5 V V_DD= 3.3 V V_DD= 5.0 V

Unit

µs

ns

µs

Power-On time

0.14

0.5

0.14

0.5

0.14

0.4

Power-On time

2.048 MHz

2.048 kHz

25 MHz

auto

Power-On time

auto

628

4

544

4

466

8

frequency settling time

variable (CLK period)

auto

2.048 MHz

2.048 kHz

25 MHz

auto

0.3

0.4

auto

660

0-40

0-0.5

0-488

570

0-40

0-0.5

0-488

480

0-40

0-0.5

0-488

forced

2.048 MHz

2.048 kHz

25 MHz/

2.048 kHz

tpd (non-delayed edge)

either

35

14

10

ns

3.9 OSCILLATOR CHARACTERISTICS

Table 16: Oscillators Frequency Limits, V_DD= 2.3 V to 5.5 V

Temperature Range

+25 °C

-40 °C to +105 °C

OSC

Minimum

Value, kHz

Maximum

Value, kHz

Minimum

Error, %

Maximum

Value, kHz

Error, %

Value, kHz

+1.00

1.7799

-1.61

+2.95

-13.09

+1.60

-4.91

2.048 kHz OSC0

2.048 MHz OSC1

2.015

2.0685

2.1085

+1.00

2019.42

2068.48

1947.519

-1.40

2080.775

Datasheet

CFR0011-120-00

17-Jun-2021

Revision 3.0

23 of 199

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 16: Oscillators Frequency Limits, V_DD= 2.3 V to 5.5 V(Continued)

Temperature Range

+25 °C

-40 °C to +105 °C

OSC

Minimum

Value, kHz

Maximum

Value, kHz

Minimum

Value, kHz

Maximum

Value, kHz

Error, %

+1.00

-1.51

+1.48

-5.38

25 MHz OSC2

24623.20

25250

23655.43

25369.01

3.9.1 OSC Power-On Delay

Table 17: Oscillators Power-On Delay at T = -40 °C to +105 °C, OSC Power Setting: "Auto Power-On"

OSC2 25 MHz

Power

Supply

Range

(V_DD) V

OSC0 2.048 kHz

OSC1 2.048 MHz

OSC2 25 MHz

Start with Delay

Typical

Maximum

Value, µs

Typical

Maximum

Value, ns

Typical

Value, ns

Maximum

Value, ns

Typical

Maximum

Value, ns

Value, µs

698.2

663.6

601.9

576.1

555.7

533.8

492.0

468.7

Value, ns

527.6

505.5

471.0

457.7

447.3

436.0

415.6

408.3

Value, ns

144.5

142.5

140.3

139.8

139.6

139.9

2.30

2.50

3.00

3.30

3.60

4.00

5.00

5.50

1063.8

993.6

866.9

812.0

768.3

721.1

637.1

598.1

562.7

542.8

510.7

498.1

487.7

475.7

454.1

446.4

44.9

61.2

53.9

42.1

37.8

34.6

31.8

26.9

26.2

166.0

164.9

164.8

165.4

166.2

167.2

170.1

171.3

39.7

31.2

28.0

25.5

23.1

19.2

18.0

3.10 ACMP CHARACTERISTICS

Table 18: ACMP Specifications at T = -40 °C to +105 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted

Parameter Description

Note

Condition

Min

0

Typ

--

Max

Unit

V

Positive Input

Negative Input

V_DD

ACMPInputVoltage

V_ACMP

Range

0

--

V

ACMPxH V_HYS= 0 mV,

Gain = 1,

Vref = 32 mV to 2016 mV

-6.4

-4.6

--

6.4

5.3

mV

V_offset

ACMP Input Offset

ACMPxL V_HYS= 0 mV,

Gain = 1,

Vref = 32 mV to 2016 mV

ACMP Power-On delay,

Minimal required wake

time for the "Wake and

Sleep function", for

ACMPxH

--

37

µs

t_start

ACMP Startup Time

ACMP Power-On delay,

Minimal required wake

time for the "Wake and

Sleep function", for

ACMPxL

294

Datasheet

17-Jun-2021

Revision 3.0

24 of 199

CFR0011-120-00

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 18: ACMP Specifications at T = -40 °C to +105 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted(Continued)

Parameter Description

Note

Condition

T = 25 °C

Min

23.33

55.78

183.67

22.03

54.12

182.73

26.96

58.44

186.18

25.01

57.87

Typ

--

Max

Unit

V_HYS= 32 mV

V_HYS= 64 mV

V_HYS= 192 mV

V_HYS= 32 mV

V_HYS= 64 mV

V_HYS= 192 mV

V_HYS= 32 mV

V_HYS= 64 mV

V_HYS= 192 mV

V_HYS= 32 mV

V_HYS= 64 mV

36.59 mV

68.38 mV

197.36 mV

37.25 mV

68.99 mV

197.57 mV

36.84 mV

69.25 mV

198.18 mV

36.82 mV

69.19 mV

198.36 mV

--

ACMP0H, ACMP1H

Built-in Hysteresis

--

(Note 1)

--

V_HYS

T = 25 °C

--

ACMP2L, ACMP3L

Built-in Hysteresis

(Note 1)

--

V_HYS= 192 mV

Gain = 1x

184.78

--

10

2

--

GΩ

MΩ

Gain = 0.5x

Gain = 0.33x

Gain = 0.25x

Series Input

Resistance

R_sin

2

Gain = 1,

Vref = 32 mV to 2016 mV,

Overdrive =10 mV

Low to High

High to Low

Low to High

High to Low

Low to High

High to Low

Low to High

High to Low

Low to High

High to Low

Low to High

High to Low

Low to High

High to Low

Low to High

High to Low

--

1.85

2.48

0.54

0.53

1.46

1.75

0.55

0.53

13.55

10.04

2.03

0.97

--

µs

Gain = 1,

Vref = 32 mV to 2016 mV,

Overdrive = 100 mV

Propagation Delay,

Response Time

for ACMP0H,

ACMP1H

Gain = 1, T = 25 °C,

Vref = 32 mV,

Overdrive = 10 mV

--

Gain = 1, T = 25 °C,

Vref = 32 mV,

Overdrive = 100 mV

--

PROP

Gain = 1,

Vref = 32 mV to 2016 mV,

Overdrive = 10 mV

56.65 128.40 µs

63.01 141.48 µs

Gain = 1,

Vref = 32 mV to 2016 mV,

Overdrive = 100 mV

19.73

19.33

68.15

66.31

27.54

27.01

60.49

µs

Propagation Delay,

Response Time

for ACMP2L,

60.93

Gain = 1, T = 25 °C,

Vref = 32 mV,

Overdrive = 10 mV

--

ACMP3L

Gain = 1, T = 25 °C,

Vref = 32 mV,

Overdrive = 100 mV

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Table 18: ACMP Specifications at T = -40 °C to +105 °C, V_DD= 2.3 V to 5.5 V Unless Otherwise Noted(Continued)

Parameter Description

Note

Condition

Min

1

Typ

1

Max

1

Unit

G = 1, Vref = 32 mV

G = 0.5, Vref = 32 mV

G = 0.33, Vref = 32 mV

G = 0.25, Vref = 32 mV

G = 1, Vref = 480 mV

G = 0.5, Vref = 480 mV

G = 0.33, Vref = 480 mV

G = 0.25, Vref = 480 mV

0.484

0.324

0.238

1

0.502

0.338

0.250

1

0.526

0.358

0.263

1

G

Gain error

0.497

0.330

0.248

0.501

0.333

0.250

0.504

0.337

0.253

Internal Vref0 error

Vref0 = 32 mV to

2016 mV,

V_DD= 4.0 V

T = 25 °C

-0.85

--

4.95

%

Buffer disabled

Internal Vref0 error

Vref0 = 320 mV to

2016 mV,

T = 25 °C

_LOAD= 1 µA

-7.96

-8.66

--

2.39

%

I

I_LOAD= 1 µA

Buffer enabled

Vref

Internal Vref1 error

Vref1 = 32 mV to

2016 mV,

V

_DD= 4.0 V

T = 25 °C

-1.79

--

5.03

%

Buffer disabled

Internal Vref1 error

Vref1 = 320 mV to

2016 mV,

-6.04

-6.79

23.3

--

2.33

2.51

%

I

_LOAD= 1 µA

I_LOAD= 1 µA

Buffer enabled

Vin = V_DD- 0.7 V,

V_DD= 2.3 V

94.1

117.7

µA

Vin = V_DD- 0.7 V,

V_DD= 2.5 V

78.4

78.2

79.4

81.7

94.9

95.3

95.4

96.5

98.7

111.4

111.8

112.0

112.9

116.4

µA

Vin = V_DD- 0.7 V,

V

_DD= 3.3 V

Input Current

Source

Is

Vin = V_DD- 0.7 V,

V_DD= 4.0 V

Vin = V_DD- 0.7 V,

V_DD= 5.0 V

Vin = V_DD- 0.7 V,

V_DD=5.5 V

Note 1 V_IL= Vin - V_HYS, V_IH= Vin.

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3.11 ANALOG TEMPERATURE SENSOR CHARACTERISTICS

Temperature Sensor typical nonlinearity ± 0.72 % for output range 1 and ± 0.42 % for output range 2 at V_DD= 2.3 V to 5.5 V.

Table 19: TS Output vs Temperature (Output Range 1), V_DD= 2.3 V to 5.5 V

Buffer Enabled

Buffer Disabled

T, °C

Min, mV

992

Typ, mV

997

Max, mV

1004

960

Min, mV

992

Typ, mV

997

Max, mV

1005

960

-40

-20

0

947

952

947

952

902

907

914

902

907

914

20

856

861

868

856

861

868

40

809

814

821

808

814

821

60

761

767

775

761

766

775

80

713

719

727

713

719

727

100

105

664

670

679

664

670

679

652

658

667

652

658

667

Table 20: TS Output vs Temperature (Output Range 2), V_DD= 2.3 V to 5.5 V

Buffer Enabled

T, °C

Buffer Disabled

Typ, mV

1204

Min, mV

1192

1143

1088

1033

976

Typ, mV

1204

1150

1095

1040

983

Max, mV

1212

1158

1103

1048

992

Min, mV

1193

1143

1088

1033

976

Max, mV

1213

1158

1103

1048

991

-40

-20

0

1150

1095

20

1040

40

983

60

919

926

935

919

926

935

80

861

868

878

861

868

878

100

105

802

810

820

802

810

820

788

795

806

787

795

806

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Table 21: TS Output Error (Output Range 1), V_DD= 2.3 V to 5.5 V

Buffer Enabled

T, °C

Buffer Disabled

Min, %

-0.56

-0.58

-0.59

-0.64

-0.72

-0.79

-0.89

-0.91

Max, %

0.70

0.75

0.78

0.81

0.92

1.03

1.15

1.33

1.40

Min, %

-0.57

-0.56

-0.58

-0.59

-0.65

-0.73

-0.79

-0.90

-0.91

Max, %

0.73

0.76

0.78

0.80

0.92

1.06

1.17

1.33

1.35

-40

-20

0

20

40

60

80

100

105

Table 22: TS Output Error (Output Range 2), V_DD= 2.3 V to 5.5 V

Buffer Enabled

T, °C

Buffer Disabled

Min, %

-0.99

-0.58

-0.60

-0.63

-0.67

-0.73

-0.82

-0.93

-0.97

Max, %

0.70

0.72

0.76

0.78

0.89

1.00

1.12

1.28

1.31

Min, %

-0.96

-0.59

-0.60

-0.63

-0.67

-0.73

-0.82

-0.93

-0.97

Max, %

0.71

0.72

0.74

0.77

0.90

0.99

1.12

1.28

1.32

-40

-20

0

20

40

60

80

100

105

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4

User Programmability

The SLG46855-A is a user programmable device with one time programmable (OTP) memory elements that are able to

configure the connection matrix and macrocells. A programming development kit allows the user the ability to create initial

devices. Once the design is finalized, the programming code (.gpx file) is forwarded to Dialog Semiconductor to integrate into a

production process.

Product

Definition

E-mail Product Idea, Definition, Drawing or

Customer creates their own design in

Schematic to

GreenPAK Designer

CMBUGreenPAK@diasemi.com

Dialog Semiconductor Applications

Engineer will review design specifications

with customer

Customer verifies GreenPAK in system

design

GreenPAK Design

approved

Samples, Design and Characterization

Report send to customer

GreenPAK Design

approved

Customers verifies GreenPAK design

GreenPAK Design

approved in system test

Custom GreenPAK part enters production

Figure 2: Steps to Create a Custom GreenPAK Device

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5

IO Pins

The SLG46855-A has a total of 10 GPIO, 1 GPI, and 1 GPO Pins which can function as either a user defined Input or Output, as

well as serving as a special function (such as outputting the voltage reference).

5.1 GPIO PINS

GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8 and GPIO9 serve as General Purpose IO Pins.

5.2 GPI PINS

GPI0 serves as a General Purpose Input Pin.

5.3 GPO PINS

GPO0 serves as a General Purpose Output Pin.

5.4 PULL-UP/DOWN RESISTORS

All IO Pins have the option for user selectable resistors connected to the input structure. The selectable values on these resistors

are 10 kΩ, 100 kΩ, and 1 MΩ. The internal resistors can be configured as either Pull-up or Pull-downs.

5.5 FAST PULL-UP/DOWN DURING POWER-UP

During power-up, IO Pull-up/down resistance will switch to 2.6 kΩ initially and then it will switch to normal setting value. This

function is enabled by register [778].

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5.6 GPI STRUCTURE

5.6.1 GPI Structure (for GPI0)

Non-Schmitt

Trigger Input

Input Mode [1:0]

00: Digital In without Schmitt Trigger, wosmt_en = 1, OE=0

01: Digital In with Schmitt Trigger, smt_en = 1, OE = 0

10: Low Voltage Digital In mode, lv_en = 1, OE = 0

11: Reserved

WOSMT_EN

SMT_EN

OE

Schmitt

Trigger Input

Digital IN

Note 1: OE cannot be selected by user

Note 2: OE is Matrix output, Digital In is Matrix input

Low Voltage

Input

LV_EN

OE

Floating

PAD

s0

s1

s2

s3

V_DD

s1

s0

900 kΩ

Res_sel

90 kΩ

10 kΩ

[1:0]

00: Floating

01: 10 kΩ

10: 100 kΩ

11: 1 MΩ

Pull-up_EN

Figure 3: IO0 GPI Structure Diagram

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5.7 GPIO WITH I²C MODE IO STRUCTURE

5.7.1 GPIO with I²C Mode Structure (for GPIO0 and GPIO1)

IO6, IO7 Mode [2:0]

00: Digital Input without Schmitt Trigger

01: Reserved

10: Low Voltage Digital Input

11: Reserved

Non-Schmitt

Trigger Input

register [790]=1: Open-Drain NMOS for GPIO0

register [796]=1: Open-Drain NMOS for GPIO1

WOSMT_EN

OE

Digital IN

Low Voltage

Input

Note 1: OE cannot be selected by user and is controlled by register.

Digital In is Matrix input.

Note 2: GPIO0 and GPIO1 do not support Push-Pull and PMOS

Open-Drain modes.

LV_EN

Note 3: It is possible to apply an input voltage higher than V_DDto

GPIO0 and GPIO1. However, this voltage should not exceed 5.5 V.

Note 4: Can be varied over PVT, for reference only

OE

Analog IO

Floating

s0

s1

s2

s3

172 Ω

(Note 4)

s1

s0

900 kΩ

90 kΩ

10 kΩ

Res_sel [1:0]

00: Floating

01: 10 kΩ

Pull-up_EN

10: 100 kΩ

11: 1 MΩ

Digital OUT

OE

OD 3.2x_en

PAD

Figure 4: GPIO with I²C Mode IO Structure Diagram

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5.8 MATRIX OE IO STRUCTURE

5.8.1 Matrix OE IO Structure (for GPIO2, GPIO3, GPIO5, GPIO6. GPIO7, GPIO8, and GPIO9)

Non-Schmitt

Trigger Input

Input Mode [1:0]

00: Digital In without Schmitt Trigger, wosmt_en = 1

01: Digital In with Schmitt Trigger, smt_en = 1

10: Low Voltage Digital In mode, lv_en = 1

11: analog IO mode

WOSMT_EN

SMT_EN

Schmitt

Trigger Input

Digital IN

Output Mode [1:0]

00: Push-Pull 1x mode, pp1x_en = 1

01: Push-Pull 2x mode, pp2x_en = 1, pp1x_en = 1

10: NMOS 1x Open-Drain mode, od1x_en = 1

11: NMOS 2x Open-Drain mode, od2x_en = 1, od1x_en = 1

Low Voltage

Input

Note 1: Digital Out and OE are Matrix Output, Digital In is Matrix Input

Note 2: Can be varied over PVT, for reference only.

LV_EN

Analog IO

Floating

s0

V_DD

s1

s2

s3

s1

s0

172 Ω

(Note 2)

900 kΩ

Res_sel

90 kΩ

10 kΩ

V_DD

[1:0]

00: Floating

01: 10 kΩ

10: 100 kΩ

11: 1 MΩ

Pull-up_EN

Digital OUT

OE

OD1x_EN

PP1x_EN

V_DD

PAD

V_DD

Digital OUT

OE

OD2x_EN

PP2x_EN

Figure 5: Matrix OE IO Structure Diagram

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5.8.2 Matrix OE 4x Drive Structure (for GPIO4)

Input Mode [1:0]

00: Digital In without Schmitt Trigger, wosmt_en = 1

01: Digital In with Schmitt Trigger, smt_en = 1

Non-Schmitt

Trigger Input

10: Low Voltage Digital In mode, lv_en = 1

11: Analog IO mode

WOSMT_EN

OE

Schmitt

Trigger Input

Output Mode [2:0]

Registers [828], [824:823]

Digital IN

000: Push-Pull 1x mode (pp1x_en)

SMT_EN

LV_EN

001: Push-Pull 2x mode (pp2x_en)

010: NMOS 1x Open-Drain mode (od1x_en)

011: NMOS 2x Open-Drain mode (od2x_en)

100: Reserved

101: Push-Pull 4x mode (pp4x_en)

110: Reserved

OE

Low Voltage

Input

111: NMOS 4x Open-Drain mode (od4x_en)

Note 1: Digital Out and OE are Matrix output, Digital In is Matrix input

Note 2: Can be varied over PVT, for reference only

Analog IO

Floating

s0

s1

s2

s3

V_DD

172 Ω

(Note 2)

s1

s0

900 kΩ

Res_sel

90 kΩ

10 kΩ

V_DD

[1:0]

00: Floating

01: 10 kΩ

10: 100 kΩ

11: 1 MΩ

Pull-up_EN

Digital OUT

OE

Digital OUT

OE

OD1x_EN

4x_EN

PP1x_EN

ODn_EN

V_DD

Digital OUT

OE

OD2x_EN

4x_EN

PAD

V_DD

ODn_EN

2x

Digital OUT

OE

Digital OUT

OE

4x_EN

ODn_EN

PP2x_EN

V_DD

2x

Digital OUT

OE

4x_EN

ODn_EN

2x

Digital OUT

OE

PP4x_EN

Figure 6: Matrix OE IO 4x Drive Structure Diagram

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5.9 GPO STRUCTURE

5.9.1 GPO Register OE Structure (for GPO0)

Floating

s0

s1

s2

s3

Output Mode [2:0]

Registers [820], [815:814]

V_DD

000: Push-Pull 1x mode (pp1x_en)

001: Push-Pull 2x mode (pp2x_en)

010: NMOS 1x Open-Drain mode (od1x_en)

011: NMOS 2x Open-Drain mode (od2x_en)

100: Reserved

s1

s0

900 kΩ

Res_sel

[1:0]

90 kΩ

10 kΩ

101: Push-Pull 4x mode (pp4x_en)

110: Reserved

00: Floating

01: 10 kΩ

10: 100 kΩ

11: 1 MΩ

111: NMOS 4x Open-Drain mode (od4x_en)

Pull-up_EN

V_DD

Digital OUT

OE

Digital OUT

OE

OD1x_EN

4x_EN

PP1x_EN

ODn_EN

Digital OUT

OE

V_DD

OD2x_EN

4x_EN

ODn_EN

PAD

V_DD

2x

Digital OUT

OE

2x

Digital OUT

OE

4x_EN

ODn_EN

PP2x_EN

Digital OUT

OE

V_DD

2x

4x_EN

ODn_EN

Digital OUT

OE

2x

PP4x_EN

Figure 7: GPO Register OE 4x Drive Structure Diagram

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5.10 IO TYPICAL PERFORMANCE

140

Push-Pull 4x @ VDD = 5.5 V

Push-Pull 2x @ VDD = 5.5 V

Push-Pull 1x @ VDD = 5.5 V

Push-Pull 4x @ VDD = 3.3 V

Push-Pull 2x @ VDD = 3.3 V

Push-Pull 1x @ VDD = 3.3 V

Push-Pull 4x @ VDD = 2.3 V

Push-Pull 2x @ VDD = 2.3 V

Push-Pull 1x @ VDD = 2.3 V

120

100

80

60

40

20

0

5.35

5.1

4.85

4.6

4.35

4.1

3.85

3.6

3.35

3.1

2.85

2.6

2.35

2.1

1.85

1.6

1.35

1.1

V_OH(V)

Figure 8: Typical High Level Output Current vs. High Level Output Voltage at T = 25 °C

90

80

70

60

50

40

30

20

10

0

Open Drain 1x @ VDD = 5.5 V

Open Drain 1x @ VDD = 3.3 V

Open Drain 1x @ VDD = 2.3 V

Push-Pull 1x @ VDD = 5.5 V

Push-Pull 1x @ VDD = 3.3 V

Push-Pull 1x @ VDD = 2.3 V

0

0.25

0.5

0.75

1

1.25

1.5

1.75

2

2.25

2.5

V_OL(V)

Figure 9: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 °C, Full Range

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30

Open Drain 1x @ VDD = 5.5 V

Open Drain 1x @ VDD = 3.3 V

25

Open Drain 1x @ VDD = 2.3 V

Push-Pull 1x @ VDD = 5.5 V

Push-Pull 1x @ VDD = 3.3 V

20

Push-Pull 1x @ VDD = 2.3 V

15

10

5

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

V_OL(V)

Figure 10: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 °C

160

150

Open Drain 2x @ VDD = 5.5 V

140

Open Drain 2x @ VDD = 3.3 V

130

Open Drain 2x @ VDD = 2.3 V

120

Push-Pull 2x @ VDD = 5.5 V

110

Push-Pull 2x @ VDD = 3.3 V

100

90

80

70

60

50

40

30

20

10

0

Push-Pull 2x @ VDD = 2.3 V

0

0.25

0.5

0.75

1

1.25

1.5

1.75

2

2.25

2.5

V_OL(V)

Figure 11: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 °C, Full Range

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50

Open Drain 2x @ VDD = 5.5 V

Open Drain 2x @ VDD = 3.3 V

Open Drain 2x @ VDD = 2.3 V

Push-Pull 2x @ VDD = 5.5 V

Push-Pull 2x @ VDD = 3.3 V

Push-Pull 2x @ VDD = 2.3 V

45

40

35

30

25

20

15

10

5

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

V_OL(V)

Figure 12: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 °C

240

220

Open Drain 3.2x @ VDD = 5.5 V

200

Open Drain 3.2x @ VDD = 3.3 V

180

Open Drain 3.2x @ VDD = 2.3 V

160

140

120

100

80

60

40

20

0

0.25

0.5

0.75

1

1.25

1.5

1.75

2

2.25

2.5

V_OL(V)

Figure 13: Typical Low Level Output Current vs. Low Level Output Voltage, 3.2x Drive at T = 25 °C, Full Range

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60

55

Open Drain 3.2x @ VDD = 5.5 V

50

Open Drain 3.2x @ VDD = 3.3 V

45

Open Drain 3.2x @ VDD = 2.3 V

40

35

30

25

20

15

10

5

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

V_OL(V)

Figure 14: Typical Low Level Output Current vs. Low Level Output Voltage, 3.2x Drive at T = 25 °C

300

280

Open Drain 4x @ VDD = 5.5 V

260

Open Drain 4x @ VDD = 3.3 V

240

Open Drain 4x @ VDD = 2.3 V

220

200

180

160

140

120

100

80

Push-Pull 4x @ VDD = 5.5 V

Push-Pull 4x @ VDD = 3.3 V

Push-Pull 4x @ VDD = 2.3 V

60

40

20

0

0.25

0.5

0.75

1

1.25

1.5

1.75

2

2.25

2.5

V_OL(V)

Figure 15: Typical Low Level Output Current vs. Low Level Output Voltage, 4x Drive at T = 25 °C, Full Range

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60

Open Drain 4x @ VDD = 5.5 V

55

50

45

40

35

30

25

20

15

10

5

Open Drain 4x @ VDD = 3.3 V

Open Drain 4x @ VDD = 2.3 V

Push-Pull 4x @ VDD = 5.5 V

Push-Pull 4x @ VDD = 3.3 V

Push-Pull 4x @ VDD = 2.3 V

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

V_OL(V)

Figure 16: Typical Low Level Output Current vs. Low Level Output Voltage, 4x Drive at T = 25 °C

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6

Connection Matrix

The Connection Matrix in the SLG46855-A is used to create the internal routing for internal functional macrocells of the device

once it is programmed. The registers are programmed from the one time programmable (OTP) NVM cell during Test Mode

Operation. The output of each functional macrocell within the SLG46855-A has a specific digital bit code assigned to it that is

either set to active “High” or inactive “Low”, based on the design that is created. Once the 2048 register bits within the SLG46855-

A are programmed a fully custom circuit will be created.

The Connection Matrix has 64 inputs and 96 outputs. Each of the 64 inputs to the Connection Matrix is hard-wired to the digital

output of a particular source macrocell, including IO pins, LUTs, analog comparators, other digital resources, such as V_DDand

GND. The input to a digital macrocell uses a 6-bit register to select one of these 64 input lines.

For a complete list of the SLG46855-A’s register table, see Section 17.

Matrix Input Signal

N

Functions

GND

0

1

2

3

GPIO1 Digital In

GPIO2 Digital In

GPIO3 Digital In

nRST_core

V_DD

62

63

Matrix Inputs

0

1

2

95

N

Registers

registers [5:0]

registers [11:6]

registers [17:12]

registers [575:570]

Matrix Out: Multi3_lut3_in2

Matrix OUT: IN0 of

LUT2_0 or Clock

Input of DFF0

Matrix OUT: IN1 of

LUT2_0 or Data

Input of DFF0

Matrix Out: IN0 of

LUT2_1 or Clock

Input of PGen

Function

Matrix Outputs

Figure 17: Connection Matrix

Function

Connection Matrix

GPIO8

GPIO7

LUT

GPIO7

GPIO8

GPIO9

LUT

GPIO9

Figure 18: Connection Matrix Example

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

6.1 MATRIX INPUT TABLE

Table 23: Matrix Input Table

Matrix Decode

Matrix Input

Matrix Input Signal Function

Number

5

0

1

4

0

1

0

3

0

1

0

1

0

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

GND

1

LUT2_0/DFF0 output

LUT2_1/DFF1 output

LUT2_2/DFF2 output

LUT2_3/PGen output

LUT3_0/DFF3 output

LUT3_1/DFF4 output

LUT3_2/DFF5 output

LUT3_3/DFF6 output

LUT3_4/DFF7 output

LUT3_5/DFF8 output

LUT3_6/DFF9 output

LUT3_7/DFF10 output

LUT3_8/DFF11 output

CNT0 output

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

MF0_LUT4/DFF_OUT

CNT1 output

MF1_LUT3/DFF_OUT

CNT2 output

MF2_LUT3/DFF_OUT

CNT3 output

MF3_LUT3/DFF_OUT

CNT4 output

MF4_LUT3/DFF_OUT

CNT5 output

MF5_LUT3/DFF_OUT

CNT6 output

MF6_LUT3/DFF_OUT

CNT7 output

MF7_LUT3/DFF_OUT

LUT3_16/Ripple CNT/Pipe Delay_out0

Ripple CNT/Pipe Delay_out1

GPIO0 digital input or I²C_virtual_0 Input

GPIO1 digital input or I²C_virtual_1 Input

I²C_virtual_2 Input

I²C_virtual_3 Input

I²C_virtual_4 Input

I²C_virtual_5 Input

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Table 23: Matrix Input Table(Continued)

Matrix Decode

Matrix Input

Matrix Input Signal Function

Number

5

1

4

0

1

3

0

1

0

1

2

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

I²C_virtual_6 Input

I²C_virtual_7 Input

Ripple CNT_out2

LUT4_0/DFF12 output

Programmable Delay Edge Detect Output

Edge Detect Filter Output

GPI0 Digital Input

GPIO2 Digital Input

GPIO3,Digital Input

GPIO4 Digital Input

GPIO5 Digital Input

GPIO6 Digital Input

GPIO7 Digital Input

GPIO8 Digital Input

GPIO9, Digital Input

Oscillator0 output 0

Oscillator1 output 0

Oscillator2 output

ACMP0 Output (normal speed)

ACMP1 Output (normal speed)

ACMP2 Output (low speed)

ACMP3 output (low speed)

Oscillator0 output 1

Oscillator1 output 1

POR OUT

V_DD

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6.2 MATRIX OUTPUT TABLE

Table 24: Matrix Output Table

Register Bit

Matrix Output

Number

Matrix Output Signal Function

Address

[5:0]

IN0 of LUT2_0 or Clock Input of DFF0

IN1 of LUT2_0 or Data Input of DFF0

IN0 of LUT2_1 or Clock Input of DFF1

IN1 of LUT2_1 or Data Input of DFF1

IN0 of LUT2_2 or Clock Input of DFF2

IN1 of LUT2_2 or Data Input of DFF2

IN0 of LUT2_3 or Clock Input of PGen

IN1 of LUT2_3 or nRST of PGen

0

[11:6]

1

[17:12]

2

[23:18]

3

[29:24]

4

[35:30]

5

[41:36]

6

[47:42]

7

[53:48]

IN0 of LUT3_0 or CLK Input of DFF3

IN1 of LUT3_0 or Data of DFF3

8

[59:54]

9

[65:60]

IN2 of LUT3_0 or nRST (nSET) of DFF3

IN0 of LUT3_1 or CLK Input of DFF4

IN1 of LUT3_1 or Data of DFF4

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

[71:66]

[77:72]

[83:78]

IN2 of LUT3_1 or nRST (nSET) of DFF4

IN0 of LUT3_2 or CLK Input of DFF5

IN1 of LUT3_2 or Data of DFF5

[89:84]

[95:90]

[101:96]

[107:102]

[113:108]

[119:114]

[125:120]

[131:126]

[137:132]

[143:138]

[149:144]

[155:150]

[161:156]

[167:162]

[173:168]

[179:174]

[185:180]

[191:186]

[197:192]

[203:198]

[209:204

IN2 of LUT3_2 or nRST (nSET) of DFF5

IN0 of LUT3_3 or CLK Input of DFF6

IN1 of LUT3_3 or Data of DFF6

IN2 of LUT3_3 or nRST (nSET) of DFF6

IN0 of LUT3_4 or CLK Input of DFF7

IN1 of LUT3_4 or Data of DFF7

IN2 of LUT3_4 or Data of DFF7

IN0 of LUT3_5 or CLK Input of DFF8

IN1 of LUT3_5 or Data of DFF8

IN2 of LUT3_5 or nRST (nSET) of DFF8

IN0 of LUT3_6 or CLK Input of DFF9

IN1 of LUT3_6 or Data of DFF9

IN2 of LUT3_6 or nRST (nSET) of DFF9

IN0 of LUT3_7 or CLK Input of DFF10

IN1 of LUT3_7 or Data of DFF10

IN2 of LUT3_7 or nRST (nSET) of DFF10

IN0 of LUT3_8 or CLK Input of DFF11

IN1 of LUT3_8 or CLK Input of DFF11

IN2 of LUT3_8 or nRST (nSET) of DFF11

IN0 of LUT3_12 or CLK Input of DFF16

Delay4 Input (or Counter4 nRST Input)

[215:210]

[221:216]

IN1 of LUT3_12 or nRST (nSET) of DFF16

Delay4 Input (or Counter4 nRST Input)

36

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Table 24: Matrix Output Table(Continued)

Register Bit

Matrix Output

Number

Matrix Output Signal Function

Address

IN2 of LUT3_12 or Data of DFF16

[227:222]

37

38

39

40

41

42

43

44

45

46

Delay4 Input (or Counter4 nRST Input)

IN0 of LUT3_13 or CLK Input of DFF17

[233:228]

Delay5 Input (or Counter5 nRST Input)

IN1 of LUT3_13 or nRST (nSET) of DFF17

[239:234]

Delay5 Input (or Counter5 nRST Input)

IN2 of LUT3_13 or Data of DFF17

[245:240]

Delay5 Input (or Counter5 nRST Input)

IN0 of LUT3_14 or CLK Input of DFF18

[251:246]

Delay6 Input (or Counter6 nRST Input)

IN1 of LUT3_14 or nRST (nSET) of DFF18

[257:252]

Delay6 Input (or Counter6 nRST Input)

IN2 of LUT3_14 or Data of DFF18

[263:258]

Delay6 Input (or Counter6 nRST Input)

IN0 of LUT3_15 or CLK Input of DFF19

[269:264]

Delay7 Input (or Counter7 nRST Input)

IN1 of LUT3_15 or nRST (nSET) of DFF19

[275:270]

Delay7 Input (or Counter7 nRST Input)

IN2 of LUT3_15 or Data of DFF19

[281:276]

Delay7 Input (or Counter7 nRST Input)

[287:282]

[293:288]

[299:294]

[305:300]

[311:306]

[317:312]

[323:318]

[329:324]

[335:330]

[341:336]

[347:342]

[353:348]

[359:354]

[365:360]

[371:366]

[377:372]

[383:378]

[389:384]

[395:390]

[401:396]

[407:402]

[413:408]

IN0 of LUT3_16 or Input of Pipe Delay or UP signal of RIPP CNT

IN1 of LUT3_16 or nRST of Pipe Delay or nSET of RIPP CNT

IN2 of LUT3_16 or Clock of Pipe Delay_RIPP CNT

IN0 of LUT4_0 or CLK Input of DFF12

IN1 of LUT4_0 or Data of DFF12

IN2 of LUT4_0 or nRST (nSET) of DFF12

IN3 of LUT4_0

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

Programmable delay/edge detect input

Filter/Edge detect input

GPIO0 Digital Output

GPIO1 Digital Output

GPIO2 Digital Output

GPIO2 Digital Output OE

GPIO3, Digital Output

GPIO3, Digital Output OE

GPO0 Digital Output

GPIO4 Digital Output

GPIO4 Digital Output OE

GPIO5 Digital Output

GPIO5 Digital Output OE

GPIO6 Digital Output

GPIO6 Digital Output OE

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Table 24: Matrix Output Table(Continued)

Register Bit

Matrix Output

Number

Matrix Output Signal Function

Address

[419:414]

[425:420]

[431:426]

[437:432]

[443:438]

[449:444]

[455:450]

[461:456]

[467:462]

[473:468]

[479:474]

[485:480]

[491:486]

[497:492]

GPIO7 Digital Output

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

GPIO7 Digital Output OE

GPIO8 Digital Output

GPIO8 Digital Output OE

GPIO9, Digital Output

GPIO9 Digital Output OE

PWR UP of ACMP0_H

PWR UP of ACMP1_H

PWR UP of ACMP2_L

PWR UP of ACMP3_L

Temp sensor, Vref Out_0, Vref Out_1 Power Up

Oscillator0 ENABLE

Oscillator1 ENABLE

Oscillator2 ENABLE

IN0 of LUT4_1 or CLK Input of DFF20

Delay0 Input (or Counter0 nRST Input)

[503:498]

[509:504]

[515:510]

[521:516]

[527:522]

[533:528]

[539:523]

[545:540]

[551:546]

[557:552]

[563:558]

[569:564]

[575:570]

IN1 of LUT4_1 or nRST of DFF20

Delay0 Input (or Counter0 nRST Input)

84

85

86

87

88

89

90

91

92

93

94

95

IN2 of LUT4_1 or nSET of DFF20

Delay0 Input (or Counter0 nRST Input)

IN3 of LUT4_1 or Data of DFF20

Delay0 Input (or Counter0 nRST Input)

IN0 of LUT3_9 or CLK Input of DFF13

Delay1 Input (or Counter1 nRST Input)

IN1 of LUT3_9 or nRST (nSET) of DFF13

Delay1 Input (or Counter1 nRST Input)

IN2 of LUT3_9 or Data of DFF13

Delay1 Input (or Counter1 nRST Input)

IN0 of LUT3_10 or CLK Input of DFF14

Delay2 Input (or Counter2 nRST Input)

IN1 of LUT3_10 or nRST (nSET) of DFF14

Delay2 Input (or Counter2 nRST Input)

IN2 of LUT3_10 or Data of DFF14

Delay2 Input (or Counter2 nRST Input)

IN0 of LUT3_11 or CLK Input of DFF15

Delay3 Input (or Counter3 nRST Input)

IN1 of LUT3_11 or nRST (nSET) of DFF15

Delay3 Input (or Counter3 nRST Input)

IN2 of LUT3_11 or Data of DFF15

Delay3 Input (or Counter3 nRST Input)

Note 1 For each Address, the two most significant bits are unused.

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6.3 CONNECTION MATRIX VIRTUAL INPUTS

As mentioned previously, the Connection Matrix inputs come from the outputs of various digital macrocells on the device. Eight

of the Connection Matrix inputs have the special characteristic that the state of these signal lines comes from a corresponding

data bit written as a register value via I²C. This gives the user the ability to write data via the serial channel, and have this

information translated into signals that can be driven into the Connection Matrix and from the Connection Matrix to the digital

inputs of other macrocells on the device. The I²C address for reading and writing these register values is at byte 0x4C (076).

Six of the eight Connection Matrix Virtual Inputs are dedicated to this virtual input function. An I²C write command to these register

bits will set the signal values going into the Connection Matrix to the desired state. A read command to these register bits will read

either the original data values coming from the NVM memory bits (that were loaded during the initial device startup), or the values

from a previous write command (if that has happened).

Two of the eight Connection Matrix Virtual Inputs are shared with Pin digital inputs (GPIO0Digital or I²C_virtual_0 Input), and

(GPIO1 Digital or I²C_virtual_1 Input). If the virtual input mode is selected, an I²C write command to these register bits will set

the signal values going into the Connection Matrix to the desired state. A read command to these register bits will read either the

original data values coming from the NVM memory bits (that were loaded during the initial device startup), or the values from a

previous write command (if that has happened). The I²C disable/enable register bit [2032] selects whether the Connection Matrix

input comes from the Pin input or from the virtual register:



Select SCL & Virtual Input 0 or GPIO0

Select SDA & Virtual Input 1 or GPIO1

See Table 24 for Connection Matrix Virtual Inputs.

Table 25: Connection Matrix Virtual Inputs

Matrix Input

Register Bit

Addresses (d)

Matrix Input Signal Function

Number

32

I²C_virtual_0 Input

I²C_virtual_1 Input

I²C_virtual_2 Input

I²C_virtual_3 Input

I²C_virtual_4 Input

I²C_virtual_5 Input

I²C_virtual_6 Input

I²C_virtual_7 Input

[608]

[609]

[610]

[611]

[612]

[613]

[614]

[615]

33

34

35

36

37

38

39

6.4 CONNECTION MATRIX VIRTUAL OUTPUTS

The digital outputs of the various macrocells are routed to the Connection Matrix to enable interconnections to the inputs of other

macrocells in the device. At the same time, it is possible to read the state of each of the macrocell outputs as a register value via

I²C. This option, called Connection Matrix Virtual Outputs, allows the user to remotely read the values of each macrocell output.

The I²C addresses for reading these register values are bytes 0x48 (072) to 0x4F (079). Write commands to these same register

values will be ignored (with the exception of the Virtual Input register bits at byte 0x4С (076)).

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7

Combination Function Macrocells

The SLG46855-A has 15 combination function macrocells that can serve more than one logic or timing function. In each case,

they can serve as a Look Up Table (LUT), or as another logic or timing function. See the list below for the functions that can be

implemented in these macrocells.



Three macrocells that can serve as either 2-bit LUT or as D Flip-Flop

Nine macrocells that can serve as either 3-bit LUTs or as D Flip-Flops with Set/Reset Input

One macrocell that can serve as either 3-bit LUT or as Pipe Delay/Ripple Counter

One macrocell that can serve as either 2-bit LUT or as Programmable Pattern Generator (PGen)

One macrocell that can serve as either 4-bit LUT or as D Flip-Flop with Set/Reset Input

Inputs/Outputs for the 15 combination function macrocells are configured from the connection matrix with specific logic functions

being defined by the state of configuration bits.

When used as a LUT to implement combinatorial logic functions, the outputs of the LUTs can be configured to any user defined

function, including the following standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR).

7.1 2-BIT LUT OR D FLIP-FLOP MACROCELLS

There is one macrocell that can serve as either 2-bit LUT or as D Flip-Flop. When used to implement LUT functions, the 2-bit LUT

takes in two input signals from the connection matrix and produce a single output, which goes back into the connection matrix.

When used to implement D Flip-Flop function, the two input signals from the connection matrix go to the data (D) and clock (CLK)

inputs for the Flip-Flop, with the output going back to the connection matrix.

The operation of the D Flip-Flop and LATCH will follow the functional descriptions below:

DFF: CLK is rising edge triggered, then Q = D; otherwise Q will not change

LATCH: when CLK is Low, then Q = D; otherwise Q remains its previous value (input D has no effect on the output, when CLK is

High).

register [1499] DFF or Latch Select

IN1

register [1498] Output Select (Q or nQ)

S0

From Connection Matrix Output [1]

register [1497] DFF Initial Polarity Select

OUT

2-bit LUT0

0: 2-bit LUT0 IN1

1: DFF0 Data

S1

IN0

LUT Truth

Table

To Connection Matrix

Input [1]

S0

S1

4-bits NVM

registers [1499:1496]

0: 2-bit LUT0 Out

1: DFF0 Out

DFF/Latch

Registers

D

S0

S1

From Connection Matrix Output [0]

Q/nQ

DFF0

0: 2-bit LUT0 IN0

1: DFF0 CLK

CLK

1-bit NVM

register [1488]

Figure 19: 2-bit LUT0 or DFF0

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register [1503] DFF or Latch Select

register [1502] Output Select (Q or nQ)

register [1501] DFF Initial Polarity Select

IN1

S0

From Connection Matrix Output [3]

OUT

2-bit LUT1

0: 2-bit LUT1 IN1

1: DFF1 Data

S1

IN0

LUT Truth

Table

To Connection Matrix

S0

Input [2]

4-bits NVM

registers [1503:1500]

S1

0: 2-bit LUT1 Out

1: DFF1 Out

DFF/Latch

Registers

D

S0

S1

From Connection Matrix Output [2]

Q/nQ

DFF1

0: 2-bit LUT1 IN0

1: DFF1 CLK

CLK

1-bit NVM

register [1489]

Figure 20: 2-bit LUT1 or DFF1

register [1507] DFF or Latch Select

IN1

register [1506] Output Select (Q or

S0

S1

From Connection Matrix Output [5]

nQ)

OUT

register [1505] DFF Initial Polarity Se-

2-bit LUT2

lect

0: 2-bit LUT2 IN1

1: DFF2 Data

IN0

LUT Truth

Table

To Connection Matrix

S0

Input [3]

4-bits NVM

registers [1507:1504]

S1

0: 2-bit LUT2 Out

1: DFF2 Out

DFF/Latch

Registers

D

S0

S1

From Connection Matrix Output [4]

Q/nQ

DFF2

0: 2-bit LUT2 IN0

1: DFF2 CLK

CLK

1-bit NVM

register [1490]

Figure 21: 2-bit LUT2 or DFF2

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7.1.1 2-Bit LUT or D Flip-Flop Macrocell Used as 2-Bit LUT

Table 26: 2-bit LUT0 Truth Table

IN1

0

IN0

0

OUT

register [1496]

register [1497]

register [1498]

register [1499]

LSB

0

1

0

1

MSB

Table 27: 2-bit LUT1 Truth Table

IN1

0

IN0

0

OUT

register [1500]

register [1501]

register [1502]

register [1503]

LSB

0

1

0

1

MSB

Table 28: 2-bit LUT2 Truth Table

IN1

0

IN0

0

OUT

register [1504]

register [1505]

register [1506]

register [1507]

LSB

0

1

0

1

MSB

This macrocell, when programmed for a LUT function, uses a 4-bit register to define their output function:

2-Bit LUT0 is defined by registers [1499:1496]

2-Bit LUT1 is defined by registers [1503:1500]

2-Bit LUT2 is defined by registers [1507:1504]

Table 28 shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be created

within each of the 2-bit LUT logic cells

Table 29: 2-bit LUT Standard Digital Functions

Function

AND-2

MSB

LSB

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

NAND-2

OR-2

NOR-2

XOR-2

XNOR-2

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7.1.2 Initial Polarity Operations

V_DD

Data

Clock

POR

Initial Polarity: High

Q with nReset (Case 1)

Initial Polarity: Low

Q with nReset (Case 1)

Figure 22: DFF Polarity Operations

7.2 2-BIT LUT OR PROGRAMMABLE PATTERN GENERATOR

The SLG46855-A has one combination function macrocell that can serve as a logic or timing function. This macrocell can serve

as a Look Up Table (LUT), or Programmable Pattern Generator (PGen).

When used to implement LUT functions, the 2-bit LUT takes in two input signals from the connection matrix and produces a single

output, which goes back into the connection matrix. When used as a LUT to implement combinatorial logic functions, the outputs

of the LUT can be configured to any user defined function, including the following standard digital logic devices (AND, NAND,

OR, NOR, XOR, XNOR). The user can also define the combinatorial relationship between inputs and outputs to be any selectable

function.

It is possible to define the RST level for the PGen macrocell. There are both high level reset (RST) and a low level reset (nRST)

options available, which are selected by register [1409]. When operating as a Programmable Pattern Generator, the output of the

macrocell will clock out a sequence of two to sixteen bits that are user selectable in their bit values, and user selectable in the

number of bits (up to sixteen) that are output before the pattern repeats.

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From Connection Matrix Output [6]

From Connection Matrix Output [7]

In0

In1

OUT

2-bit LUT3

LUT Truth

Table

To Connection Matrix Input [4]

S0

S1

registers [1387:1384]

0: 2-bit LUT3 OUT

1: PGen OUT

Pattern

size

nRST/RST

CLK

PGen

OUT

PGen

Data

register [1408]

registers [1407:1392]

Figure 23: 2-bit LUT3 or PGen

V

DD

t

nRST

CLK

OUT

1

2

6

8

16 17

3

5

7

0

4

9

11

10

14 15

12 13

t

D7

D6

D5

D10

D8

D4

D3

D2

D1

D15

D11

D9

D0

D15

D14

D13

D12

D0

t

Figure 24: PGen Timing Diagram

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7.2.1 2-Bit LUT or PGen Macrocell Used as 2-Bit LUT

Table 30: 2-bit LUT1 Truth Table

IN1

0

IN0

0

OUT

register [1384]

register [1385]

register [1386]

register [1387]

LSB

0

1

0

1

MSB

This macrocell, when programmed for a LUT function, uses a 4-bit register to define their output function:

2-Bit LUT3 is defined by registers [1387:1384]

Table 30 shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be created

within each of the 2-bit LUT logic cells.

Table 31: 2-bit LUT Standard Digital Functions

Function

AND-2

MSB

LSB

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

NAND-2

OR-2

NOR-2

XOR-2

XNOR-2

7.3 3-BIT LUT OR D FLIP-FLOP WITH SET/RESET MACROCELLS

There are nine macrocells that can serve as either 3-bit LUTs or as D Flip-Flops with Set/Reset inputs. When used to implement

LUT functions, the 3-bit LUTs each take in three input signals from the connection matrix and produce a single output, which goes

back into the connection matrix. When used to implement D Flip-Flop function, the three input signals from the connection matrix

go to the data (D) and clock (CLK), and Reset/Set (nRST/nSET) inputs for the Flip-Flop, with the output going back to the

connection matrix. It is possible to define the active level for the reset/set input of DFF/LATCH macrocell. There are both active

high level reset/set (RST/SET) and active low level reset/set (nRST/nSET) options available which are selected by register [1445].

DFF3 operation will flow the functional description below:



If register [1443] = 0, and the CLK is rising edge triggered, then Q = D, otherwise Q will not change.

If register [1443] = 1, then data from D is written into the DFF by the rising edge on CLK and output to Q by the falling edge on

CLK.

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register [1447] DFF or Latch Select

register [1446] Output Select (Q or nQ)

register [1445] DFF Initial Polarity Select

register [1444] Q1 or Q2 Select

register [1443] DFF nRST or nSET Select

register [1442] Active level selection for RST/

SET

IN2

IN1

From Connection

Matrix Output [10]

S0

S1

OUT

3-bit LUT0

IN0

LUT Truth

Table

From Connection

Matrix Output [9]

To Connection Matrix

S0

S1

Input [5]

S0

S1

8-bits NVM

registers [1447:1440]

From Connection

Matrix Output [8]

S0

S1

DFF/Latch

Registers

0

1

Q/nQ

DFF

D

Q

D

Q

nRST/

CL

nSET

nRST/

nSET

CL

nRST/nSET

CLK

register [1444]

1-bit NVM

register [1415]

Figure 25: 3-bit LUT0 or DFF3

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register [1359] DFF or Latch Select

register [1358] Output Select (Q or nQ)

register [1357] DFF Initial Polarity Select

register [1356] DFF nRST or nSET Select

register [1355] Active level selection for RST/

SET

IN2

IN1

From Connection

Matrix Output [13]

S0

S1

OUT

3-bit LUT1

IN0

LUT Truth

Table

From Connection

Matrix Output [12]

To Connection Matrix

S0

S1

Input [6]

S0

8-bits NVM

registers [1359:1352]

S1

DFF/Latch

Registers

D

From Connection

Matrix Output [11]

S0

S1

^nRST/nSETDFF4

Q/nQ

RST/SET

CLK

1-bit NVM

register [1388]

Figure 26: 3-bit LUT1 or DFF4

register [1367] DFF or Latch Select

register [1366] Output Select (Q or nQ)

register [1365] DFF Initial Polarity Select

register [1364] DFF nRST or nSET Select

register [1363] Active level selection for RST/

SET

IN2

From Connection

Matrix Output [16]

S0

S1

IN1

IN0

OUT

3-bit LUT2

LUT Truth

Table

From Connection

Matrix Output [15]

To Connection Matrix

S0

S1

S0

S1

Input [7]

8-bits NVM

registers [1367:1360]

DFF/Latch

Registers

D

From Connection

Matrix Output [14]

S0

S1

^nRST/nSETDFF5

RST/SET

Q/nQ

CLK

1-bit NVM

register [1389]

Figure 27: 3-bit LUT2 or DFF5

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register [1375] DFF or Latch Select

register [1374] Output Select (Q or nQ)

register [1373] DFF Initial Polarity Select

register [1372] DFF nRST or nSET Select

register [1371] Active level selection for RST/

SET

IN2

IN1

From Connection

Matrix Output [19]

S0

S1

OUT

3-bit LUT3

IN0

LUT Truth

Table

From Connection

Matrix Output [18]

To Connection Matrix

S0

S1

S0

S1

Input [8]

8-bits NVM

registers [1375:1368]

DFF

Registers

D

From Connection

Matrix Output [17]

S0

S1

nRST/nSET

RST/SET

DFF6

Q/nQ

CLK

1-bit NVM

register [1390]

Figure 28: 3-bit LUT3 or DFF6

register [1383] DFF or Latch Select

register [1382] Output Select (Q or nQ)

register [1381] DFF Initial Polarity Select

register [1380] DFF nRST or nSET Select

register [1379] Active level selection for RST/

SET

IN2

From Connection

Matrix Output [22]

S0

S1

IN1

IN0

OUT

3-bit LUT4

LUT Truth

Table

From Connection

Matrix Output [21]

To Connection Matrix

S0

S1

S0

S1

Input [9]

8-bits NVM

registers [1383:1376]

DFF/Latch

Registers

D

From Connection

Matrix Output [20]

S0

S1

nRST/nSET

RST/SET

DFF7

Q/nQ

CLK

1-bit NVM

register [1391]

Figure 29: 3-bit LUT4 or DFF7

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register [1463] DFF or Latch Select

register [1462] Output Select (Q or nQ)

register [1461] DFF Initial Polarity Select

register [1460] DFF nRST or nSET Select

register [1459] Active level selection for RST/

SET

IN2

IN1

From Connection

Matrix Output [25]

S0

S1

OUT

3-bit LUT5

IN0

LUT Truth

Table

From Connection

Matrix Output [24]

To Connection Matrix

S0

S1

S0

S1

Input [10]

8-bits NVM

registers [1463:1456]

DFF

Registers

D

From Connection

Matrix Output [23]

S0

S1

nRST/nSET

RST/SET

DFF8

Q/nQ

CLK

1-bit NVM

register [1492]

Figure 30: 3-bit LUT5 or DFF8

register [1471] DFF or Latch Select

register [1470] Output Select (Q or nQ)

register [1469] DFF Initial Polarity Select

register [1468] DFF nRST or nSET Select

register [1467] Active level selection for RST/

SET

IN2

From Connection

Matrix Output [28]

S0

S1

IN1

IN0

OUT

3-bit LUT6

LUT Truth

Table

From Connection

Matrix Output [27]

To Connection Matrix

S0

S1

S0

S1

Input [11]

8-bits NVM

registers [1471:1464]

DFF/Latch

Registers

D

From Connection

Matrix Output [26]

S0

S1

nRST/nSET

RST/SET

DFF9

Q/nQ

CLK

1-bit NVM

register [1493]

Figure 31: 3-bit LUT6 or DFF9

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register [1479] DFF or Latch Select

register [1478] Output Select (Q or nQ)

register [1477] DFF Initial Polarity Select

register [1476] DFF nRST or nSET Select

register [1475] Active level selection for RST/

SET

IN2

IN1

From Connection

Matrix Output [31]

S0

S1

OUT

3-bit LUT7

IN0

LUT Truth

Table

From Connection

Matrix Output [30]

To Connection Matrix

S0

S1

S0

S1

Input [12]

8-bits NVM

registers [1479:1472]

DFF

Registers

D

From Connection

Matrix Output [29]

S0

S1

^nRST/nSETDFF10

RST/SET

Q/nQ

CLK

1-bit NVM

register [1494]

Figure 32: 3-bit LUT7 or DFF10

register [1487] DFF or Latch Select

register [1486] Output Select (Q or nQ)

register [1485] DFF Initial Polarity Select

register [1484] DFF nRST or nSET Select

register [1483] Active level selection for RST/

SET

IN2

From Connection

Matrix Output [34]

S0

S1

IN1

IN0

OUT

3-bit LUT8

LUT Truth

Table

From Connection

Matrix Output [33]

To Connection Matrix

S0

S1

S0

S1

Input [13]

8-bits NVM

registers [1487:1480]

DFF

Registers

D

From Connection

Matrix Output [32]

S0

S1

^nRST/nSETDFF11

RST/SET

Q/nQ

CLK

1-bit NVM

register [1495]

Figure 33: 3-bit LUT8 or DFF11

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7.3.1 3-Bit LUT or D Flip-Flop Macrocells Used as 3-Bit LUTs

Table 32: 3-bit LUT0 Truth Table

Table 36: 3-bit LUT4 Truth Table

IN2

0

IN1

0

IN0

0

OUT

IN2

0

IN1

0

IN0

0

OUT

register [1440]

register [1441]

register [1442]

register [1443]

register [1444]

register [1445]

register [1446]

register [1447]

LSB

register [1376]

register [1377]

register [1378]

register [1379]

register [1380]

register [1381]

register [1382]

register [1383]

LSB

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

MSB

LSB

1

MSB

LSB

Table 33: 3-bit LUT1 Truth Table

Table 37: 3-bit LUT5 Truth Table

IN2

0

IN1

0

IN0

0

OUT

IN2

0

IN1

0

IN0

0

OUT

register [1352]

register [1353]

register [1354]

register [1355]

register [1356]

register [1357]

register [1358]

register [1359]

register [1356]

register [1357]

register [1358]

register [1359]

register [1360]

register [1361]

register [1362]

register [1363]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

MSB

LSB

1

MSB

LSB

Table 34: 3-bit LUT2 Truth Table

Table 38: 3-bit LUT6 Truth Table

IN2

0

IN1

0

IN0

0

OUT

IN2

0

IN1

0

IN0

0

OUT

register [1360]

register [1361]

register [1362]

register [1363]

register [1364]

register [1365]

register [1366]

register [1367]

register [1364]

register [1365]

register [1366]

register [1367]

register [1368]

register [1369]

register [1370]

register [1371]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

MSB

LSB

1

MSB

LSB

Table 35: 3-bit LUT3 Truth Table

Table 39: 3-bit LUT7 Truth Table

IN2

0

IN1

0

IN0

0

OUT

IN2

0

IN1

0

IN0

0

OUT

register [1368]

register [1369]

register [1370]

register [1371]

register [1372]

register [1373]

register [1374]

register [1375]

register [1472]

register [1473]

register [1474]

register [1475]

register [1476]

register [1477]

register [1478]

register [1479]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

MSB

1

MSB

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Table 40: 3-bit LUT8 Truth Table

IN2

0

IN1

0

IN0

0

OUT

register [1480]

register [1481]

register [1482]

register [1483]

register [1484]

register [1485]

register [1486]

register [1487]

LSB

0

1

0

1

0

1

0

1

0

1

0

1

MSB

Each macrocell, when programmed for a LUT function, uses a 8-bit register to define their output function:

3-Bit LUT0 is defined by registers [1447:1440]

3-Bit LUT1 is defined by registers [1359:1352]

3-Bit LUT2 is defined by registers [1367:1360]

3-Bit LUT3 is defined by registers [1375:1368]

3-Bit LUT4 is defined by registers [1383:1376]

3-Bit LUT5 is defined by registers [1463:1456]

3-Bit LUT6 is defined by registers [1471:1464]

3-Bit LUT7 is defined by registers [1479:1472]

3-Bit LUT8 is defined by registers [1487:1480]

Table 40 shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be created

within each of the four 3-bit LUT logic cells.

Table 41: 3-bit LUT Standard Digital Functions

Function

AND-3

MSB

LSB

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

NAND-3

OR-3

NOR-3

XOR-3

XNOR-3

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7.3.2 Initial Polarity Operations

V_DD

Data

Clock

POR

Initial Polarity: High

nReset (Case 1)

Q with nReset (Case 1)

nReset (Case 2)

Q with nReset (Case 2)

Initial Polarity: Low

nReset (Case 1)

Q with nReset (Case 1)

nReset (Case 2)

Q with nReset (Case 2)

Figure 34: DFF Polarity Operations with nReset

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V_DD

Data

Clock

POR

Initial Polarity: High

nSet (Case 1)

Q with nSet (Case 1)

nSet (Case 2)

Q with nSet (Case 2)

Initial Polarity: Low

nSet (Case 1)

Q with nSet (Case 1)

nSet (Case 2)

Q with nSet (Case 2)

Figure 35: DFF Polarity Operations with nSet

7.4 4-BIT LUT OR D FLIP-FLOP WITH SET/RESET MACROCELL

There is one macrocell that can serve as either a 4-bit LUT or as a D Flip-Flop with Set/Reset inputs. When used to implement

LUT functions, the 4-bit LUT takes in four input signals from the connection matrix and produce a single output, which goes back

into the connection matrix. When used to implement D Flip-Flop function, the input signals from the connection matrix go to the

data (D) and clock (CLK), and Reset/Set (nRST/nSET) inputs for the Flip-Flop, with the output going back to the connection matrix.



If register [1436] = 0, and the CLK is rising edge triggered, then Q = D, otherwise Q will not change.

If register [1436] = 1, then data from D is written into the DFF by the rising edge on CLK and output to Q by the falling edge on

CLK.

It is possible to define the active level for the reset/set input of DFF/LATCH macrocell. There are both active high level reset/set

(RST/SET) and active low level reset/set (nRST/nSET) options available which are selected by register [1434].

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From Connection

register [1439] DFF or Latch Select

S0

S1

Matrix Output [53]

register [1438] Output Select (Q or nQ)

register [1437] DFF Initial Polarity Select

register [1436] Q1 or Q2 Select

register [1435] DFF nRST or nSET Select

register [1434] Active level selection for RST/SET

IN3

IN2

IN1

From Connection

Matrix Output [52]

S0

S1

OUT

4-bit LUT0

IN0

LUT Truth

Table

From Connection

Matrix Output [51]

To Connection Matrix

S0

S1

Input [41]

S0

16-bits NVM

registers [1439:1424]

S1

DFF/Latch

Registers

D

From Connection

Matrix Output [50]

S0

S1

^nRST/nSETDFF12

RST/SET

Q/nQ

Q1/Q2

CLK

Select

register [1436]

1-bit NVM

register [1414]

Figure 36: 4-bit LUT0 or DFF12

7.4.1 4-Bit LUT Macrocell Used as 4-Bit LUT

Table 42: 4-bit LUT0 Truth Table

IN3

0

IN2

0

IN1

0

IN0

0

OUT

register [1424]

register [1425]

register [1426]

register [1427]

register [1428]

register [1429]

register [1430]

register [1431]

register [1432]

register [1433]

register [1434]

register [1435]

register [1436]

register [1437]

register [1438]

register [1439]

LSB

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

MSB

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This macrocell, when programmed for a LUT function, uses a 16-bit register to define their output function:

4-Bit LUT0 is defined by registers [1439:1424]

Table 43: 4-bit LUT Standard Digital Functions

Function

AND-4

MSB

LSB

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

NAND-4

OR-4

NOR-4

XOR-4

XNOR-4

7.5 3-BIT LUT OR PIPE DELAY/RIPPLE COUNTER MACROCELL

There is one macrocell that can serve as either a 3-bit LUT or as a Pipe Delay/Ripple Counter.

When used to implement LUT functions, the 3-bit LUT takes in three input signals from the connection matrix and produces a

single output, which goes back into the connection matrix.

When used as a Pipe Delay, there are three inputs signals from the matrix, Input (IN), Clock (CLK), and Reset (nRST). The Pipe

Delay cell is built from 16 D Flip-Flop logic cells that provide the three delay options, two of which are user selectable. The DFF

cells are tied in series where the output (Q) of each delay cell goes to the next DFF cell input (IN). Both of the two outputs (OUT0

and OUT1) provide user selectable options for 1 – 16 stages of delay. There are delay output points for each set of the OUT0 and

OUT1 outputs to a 4-input mux that is controlled by registers [1419:1416] for OUT0 and registers [1423:1420] for OUT1. The 4-

input mux is used to control the selection of the amount of delay.

The overall time of the delay is based on the clock used in the SLG46855-A design. Each DFF cell has a time delay of the inverse

of the clock time (either external clock or the internal Oscillator within the SLG46855-A). The sum of the number of DFF cells used

will be the total time delay of the Pipe Delay logic cell. OUT1 Output can be inverted (as selected by register [1413]).

In the Ripple Counter mode there are 3 options for setting which use 7 bits. There are 3 bits to set nSET value (SV) in range from

0 to 7. This value will be set into the Ripple Counter outputs when nSET input goes LOW. End value (EV) will use 3 bits for setting

output code, which will be last code in the cycle. After reaching the EV, the Ripple Counter goes to the first code by the rising

edge on CLK input. The Functionality mode option uses 1 bit. This setting defines how exactly Ripple Counter will operate.

The user can select one of the functionality modes by register: RANGE or FULL. If the RANGE option is selected, the count starts

from SV. If UP input is LOW the count goes down: SV→EV→EV-1 to SV+1→SV, and others (if SV is smaller than EV), or SV→SV-

1 to EV+1→EV→SV (if SV is bigger than EV). If UP input is HIGH, count starts from SV up to EV, and others.

In the FULL range configuration the Ripple Counter functions as follows. If UP input is LOW, the count starts from SV and goes

down to 0. Then current counter value jumps to EV and goes down to 0, and others.

If UP input is HIGH, count goes up starting from SV. Then current counter value jumps to 0 and counts up to EV, and others. See

Ripple Counter functionality example in Figure 38.

Every step is executed by the rising edge on CLK input.

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registers [1423:1416]

From Connection

Matrix Output [47]

IN0

From Connection

Matrix Output [48]

IN1

IN2

OUT

3-bit LUT16

From Connection

Matrix Output [49]

Pipe Delay ^{registers [1423:1420]}

register [1413]

0

1

0

1

OUT2

OUT1

To Connection

Matrix Input [40]

register [1412]

From Connection

Matrix Output [47]

IN

From Connection

Matrix Output [48]

nRST

16 Flip-Flops

0

OUT1

From Connection

Matrix Output [49]

CLK

To Connection

Matrix Input [31]

1

register [1412]

OUT0

0

OUT0

To Connection

Matrix Input [30]

0

1

registers [1419:1416]

1 Pipe OUT

register [1411]

Ripple Counter

3 Flip-Flops

UP

From Connection

Matrix Output [47]

UP/DOWN

Control

OUT0

D

Q

DFF1

CLK

From Connection

Matrix Output [49]

CL

nQ

nSET

From Connection

Matrix Output [48]

SET

OUT1

OUT2

Control

D

Q

DFF2

CL

nQ

Mode & SET/END

Value Control

D

Q

DFF3

nQ

CL

registers [1422:1416]

Figure 37: 3-bit LUT16/Pipe Delay/Ripple Counter

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Figure 38: Example: Ripple Counter Functionality

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7.5.1 3-Bit LUT or Pipe Delay Macrocells Used as 3-Bit LUT

Table 44: 3-bit LUT16 Truth Table

IN2

0

IN1

0

IN0

0

OUT

register [1416]

register [1417]

register [1418]

register [1419]

register [1420]

register [1421]

register [1422]

register [1423]

0

1

0

1

0

1

0

1

0

1

0

1

Each macrocell, when programmed for a LUT function, uses a 8-bit register to define their output function:

3-Bit LUT16 is defined by registers [1423:1416]

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8

Multi-Function Macrocells

The SLG46855-A has 8 Multi-Function macrocells that can serve more than one logic or timing function. In each case, they can

serve as a LUT, DFF with flexible settings, or as CNT/DLY with multiple modes, such as One Shot, Frequency Detect, Edge

Detect, and others. Also, the macrocell is capable to combine those functions: LUT/DFF connected to CNT/DLY or CNT/DLY

connected to LUT/DFF, see Figure 39.

See the list below for the functions that can be implemented in these macrocells:



Seven macrocells that can serve as 3-bit LUTs/D Flip-Flops and as 8-Bit Counter/Delays

One macrocell that can serve as a 4-bit LUT/D Flip-Flop and as 16-Bit Counter/Delay/FSM

To Connection Matrix

From Connection

Matrix

To Connection

Matrix

From Connection

Matrix

To Connection

Matrix

LUT

or

DFF

LUT

or

DFF

CNT/DLY

Figure 39: Possible Connections Inside Multi-Function Macrocell

Inputs/Outputs for the 8 Multi-Function function macrocells are configured from the connection matrix with specific logic functions

being defined by the state of NVM bits.

When used as a LUT to implement combinatorial logic functions, the outputs of the LUTs can be configured to any user defined

function, including the following standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR).

8.1 3-BIT LUT OR DFF/LATCH WITH 8-BIT COUNTER/DELAY MACROCELLS

There are seven macrocells that can serve as 3-bit LUTs/D Flip-Flops and as 8-Bit Counter/Delays.

When used to implement LUT functions, the 3-bit LUTs each take in three input signals from the connection matrix and produce

a single output, which goes back into the connection matrix or can be connected to CNT/DLY's input.

When used to implement D Flip-Flop function, the three input signals from the connection matrix go to the data (D), clock (CLK),

and Reset/Set (nRST/nSET) inputs of the Flip-Flop, with the output going back to the connection matrix or to the CNT/DLY's input.

When used to implement Counter/Delays, each macrocell has a dedicated matrix input connection. For flexibility, each of these

macrocells has a large selection of internal and external clock sources, as well as the option to chain from the output of the

previous (N-1) CNT/DLY macrocell, to implement longer count/delay circuits. These macrocells can also operate in a One-Shot

mode, which will generate an output pulse of user-defined width. They can also operate in a Frequency Detection or Edge

Detection mode.

Counter/Delay macrocell has an initial value, which define its initial value after GPAK is powered up. It is possible to select initial

Low or initial High, as well as initial value defined by a Delay In signal.

For example, in case initial LOW option is used, the rising edge delay will start operation.

For timing diagrams refer to sections 7.1 and 8.3.

Note: After two DFF – counters initialize with counter data = 0 after POR.

Initial state = 1 – counters initialize with counter data = 0 after POR.Initial state = 0 And After two DFF is bypass – counters

initialize with counter data after POR.

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CNT6 and CNT7 current count value can be read via I²C. However, it is possible to change the counter data (value counter starts

operating from) for any macrocell using I²C write commands. In this mode, it is possible to load count data immediately (after two

DFF) or after counter ends counting. See Section 15.6.1 for further details.

8.1.1 3-Bit LUT or 8-Bit CNT/DLY Block Diagrams

register [1215] DFF or Latch Select

register [1214] Output Select (Q or

From Connection

Matrix Output [89]

nQ)

register [1213] (nRST or nSET)

from matrix Output

register [1212] DFF Initial Polarity

Select

IN2

IN1

IN0

S0

S1

3-bit LUT9

S0

S1

OUT

LUT Truth

Table

From Connection

Matrix Output [88]

To Connection

S0

S1

S0

S1

Matrix Input [17]

8-bits NVM

registers [1215:1208]

S1

DFF

Registers

D

From Connection

Matrix Output [87]

S0

S1

S0

S1

nRST/nSET

CLK

DFF/

Latch13

Q/nQ

register [1053]

LUT/DFF Sel

registers [1223:1216]

registers [1052:1049]

Mode Sel

CNT

Data

ext_CLK

To Connection

Matrix Input [16]

0

S0

OUT

CNT/DLY1

DLY_IN/CNT Reset

S0

S1

S2

S1

S2

S3

Config

Data

0

S3

registers [1066:1054]

Figure 40: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT9/DFF13, CNT/DLY1)

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register [1231] DFF or Latch Select

register [1230] Output Select (Q or

nQ)

From Connection

register [1229] (nRST or nSET)

from matrix Output

Matrix Output [92]

IN2

S0

3-bit LUT10

S0

S1

register [1228] DFF Initial Polarity

Select

OUT

IN1

IN0

S1

LUT Truth

Table

From Connection

Matrix Output [91]

To Connection

S0

S1

S0

S1

Matrix Input [19]

8-bits NVM

registers [1231:1224]

S1

DFF

Registers

D

From Connection

Matrix Output [90]

S0

S1

S0

S1

DFF/

Latch14

nRST/nSET

CLK

Q/nQ

register [1071]

LUT/DFF Sel

registers [1239:1232]

registers [1067:1070]

Mode Sel

CNT

Data

ext_CLK

To Connection

Matrix Input [18]

0

S0

OUT

CNT/DLY2

DLY_IN/CNT Reset

S0

S1

S2

S1

S2

S3

Config

Data

0

S3

registers [1084:1072]

Figure 41: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT10/DFF14, CNT/DLY2)

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register [1247] DFF or Latch Select

register [1246] Output Select (Q or

nQ)

register [1245] (nRST or nSET)

from matrix Output

register [1244] DFF Initial Polarity

Select

From Connection

Matrix Output [95]

IN2

S0

3-bit LUT11

S0

S1

OUT

IN1

IN0

S1

LUT Truth

Table

From Connection

Matrix Output [94]

To Connection

S0

S1

S0

S1

Matrix Input [21]

8-bits NVM

registers [1247:1240]

S1

DFF

Registers

D

From Connection

Matrix Output [93]

S0

S1

S0

S1

DFF/

Latch15

nRST/nSET

Q/nQ

CLK

register [1087]

LUT/DFF Sel

registers [1255:1248]

registers [1095:1092]

Mode Sel

CNT

Data

ext_CLK

To Connection

Matrix Input [20]

0

S0

OUT

CNT/DLY3

DLY_IN/CNT Reset

S0

S1

S2

S1

S2

S3

Config

Data

0

S3

registers [1102:1096], [1091:1085]

Figure 42: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT11/DFF15, CNT/DLY3)

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register [1263] DFF or Latch Select

register [1262] Output Select (Q or

nQ)

From Connection

Matrix Output [37]

register [1261] (nRST or nSET)

from matrix Output

IN2

S0

3-bit LUT12

S0

S1

register [1260] DFF Initial Polarity

Select

OUT

IN1

IN0

S1

LUT Truth

Table

From Connection

Matrix Output [36]

To Connection

S0

S1

S0

S1

Matrix Input [23]

8-bits NVM

registers [1263:1256]

S1

DFF

Registers

D

From Connection

Matrix Output [35]

S0

S1

S0

S1

_nRST/nSETDFF/

Q/nQ

Latch16

CLK

register [1107]

LUT/DFF Sel

registers [1271:1264]

registers [1108:1111]

Mode Sel

CNT

Data

ext_CLK

To Connection

Matrix Input [22]

0

S0

OUT

CNT/DLY4

DLY_IN/CNT Reset

S0

S1

S2

S1

S2

S3

Config

Data

0

S3

registers [1120:1112], [1106:1103]

Figure 43: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT12/DFF16, CNT/DLY4)

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register [1279] DFF or Latch Select

register [1278] Output Select (Q or

nQ)

register [1277] (nRST or nSET)

from matrix Output

register [1276] DFF Initial Polarity

Select

From Connection

Matrix Output [40]

IN2

S0

3-bit LUT13

S0

S1

OUT

IN1

IN0

S1

LUT Truth

Table

From Connection

Matrix Output [39]

To Connection

S0

S1

S0

S1

Matrix Input [25]

8-bits NVM

registers [1279:1272]

S1

DFF

Registers

D

From Connection

Matrix Output [38]

S0

S1

S0

S1

DFF/

Latch17

nRST/nSET

Q/nQ

CLK

register [1134]

LUT/DFF Sel

registers [1127:1126],

[1133:1132]

registers [1287:1280]

Mode Sel

CNT

Data

ext_CLK

To Connection

Matrix Input [24]

0

S0

OUT

CNT/DLY5

DLY_IN/CNT Reset

S0

S1

S2

S1

S2

S3

Config

Data

0

S3

registers [1125:1121], [1131:1128],

[1138:1135]

Figure 44: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT13/DFF17, CNT/DLY5)

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register [1295] DFF or Latch Select

register [1294] Output Select (Q or

nQ)

From Connection

register [1293] (nRST or nSET)

from matrix Output

Matrix Output [43]

IN2

S0

3-bit LUT14

S0

S1

register [1292] DFF Initial Polarity

Select

OUT

IN1

IN0

S1

LUT Truth

Table

From Connection

Matrix Output [42]

To Connection

S0

S1

S0

S1

Matrix Input [27]

8-bits NVM

registers [1295:1288]

S1

DFF

Registers

D

From Connection

Matrix Output [41]

S0

S1

S0

S1

DFF/

Latch18

nRST/nSET

Q/nQ

CLK

register [1152]

LUT/DFF Sel

registers [1303:1296]

registers [1150:1148]

Mode Sel

CNT

Data

ext_CLK

To Connection

Matrix Input [26]

0

S0

OUT

CNT/DLY6

DLY_IN/CNT Reset

S0

S1

S2

S1

S2

S3

Config

Data

0

S3

registers [1156:1153], [1147:1139]

Figure 45: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT14/DFF18, CNT/DLY6)

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register [1311] DFF or Latch Select

register [1310] Output Select (Q or

nQ)

register [1309] (nRST or nSET) from

matrix Output

register [1308] DFF Initial Polarity Se-

lect

From Connection

Matrix Output [46]

IN2

S0

3-bit LUT15

S0

S1

OUT

IN1

IN0

S1

LUT Truth

Table

From Connection

Matrix Output [45]

To Connection

S0

S1

S0

S1

Matrix Input [29]

8-bits NVM

registers [1311:1304]

S1

DFF

Registers

D

From Connection

Matrix Output [44]

S0

S1

S0

S1

DFF/

Latch19

nRST/nSET

CLK

Q/nQ

register [1161]

LUT/DFF Sel

registers [1319:1312]

registers [1165:1162]

Mode Sel

CNT

Data

ext_CLK

To Connection

Matrix Input [28]

0

S0

OUT

CNT/DLY7

DLY_IN/CNT Reset

S0

S1

S2

S1

S2

S3

Config

Data

0

S3

registers [1174:1166], [1160:1157]

Figure 46: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT15/DFF19, CNT/DLY7)

As shown in Figures 24-30 there is a possibility to use LUT/DFF and CNT/DLY simultaneously.

Note: It is not possible to use LUT and DFF at once, one of these macrocells must be selected.



Case 1. LUT/DFF in front of CNT/DLY. Three input signals from the connection matrix go to previously selected LUT or DFF's

inputs and produce a single output which goes to a CND/DLY input. In its turn Counter/Delay's output goes back to the matrix.

Case 2. CNT/DLY in front of LUT/DFF. Two input signals from the connection matrix go to CND/DLY's inputs (IN and CLK). Its

output signal can be connected to any input of previously selected LUT or DFF, after which the signal goes back to the matrix.

Case 3. Single LUT/DFF or CNT/DLY. Also, it is possible to use a standalone LUT/DFF or CNT/DLY. In this case, all inputs

and output of the macrocell are connected to the matrix.

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8.1.2 3-Bit LUT or CNT/DLYs Used as 3-Bit LUTs

Table 45: 3-bit LUT9 Truth Table

Table 49: 3-bit LUT13 Truth Table

IN2

0

IN1

0

IN0

0

OUT

IN2

0

IN1

0

IN0

0

OUT

register [1208]

register [1209]

register [1210]

register [1211]

register [1212]

register [1213]

register [1214]

register [1215]

LSB

register [1272]

register [1273]

register [1274]

register [1275]

register [1276]

register [1277]

register [1278]

register [1279]

LSB

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

MSB

LSB

1

MSB

LSB

Table 46: 3-bit LUT10 Truth Table

Table 50: 3-bit LUT14 Truth Table

IN2

0

IN1

0

IN0

0

OUT

IN2

0

IN1

0

IN0

0

OUT

register [1224]

register [1225]

register [1226]

register [1227]

register [1228]

register [1229]

register [1230]

register [1231]

register [1288]

register [1289]

register [1290]

register [1291]

register [1292]

register [1293]

register [1294]

register [1295]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

MSB

LSB

1

MSB

LSB

Table 47: 3-bit LUT11 Truth Table

Table 51: 3-bit LUT15 Truth Table

IN2

0

IN1

0

IN0

0

OUT

IN2

0

IN1

0

IN0

0

OUT

register [1240]

register [1241]

register [1242]

register [1243]

register [1244]

register [1245]

register [1246]

register [1247]

register [1304]

register [1305]

register [1306]

register [1307]

register [1308]

register [1309]

register [1310]

register [1311]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

MSB

LSB

1

MSB

Table 48: 3-bit LUT12 Truth Table

IN2

0

IN1

0

IN0

0

OUT

register [1256]

register [1257]

register [1258]

register [1259]

register [1260]

register [1261]

register [1262]

register [1263]

0

1

0

1

0

1

0

1

0

1

0

1

MSB

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Each macrocell, when programmed for a LUT function, uses a 8-bit register to define their output function:

3-Bit LUT9 is defined by registers [1215:1208]

3-Bit LUT10 is defined by registers [1231:1224]

3-Bit LUT11 is defined by registers [1247:1240]

3-Bit LUT12 is defined by registers [1263:1256]

3-Bit LUT13 is defined by registers [1279:1272]

3-Bit LUT14 is defined by registers [1295:1288]

3-Bit LUT15 is defined by registers [1311:1304]

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8.2 4-BIT LUT OR DFF/LATCH WITH 16-BIT COUNTER/DELAY MACROCELL

There is one macrocell that can serve as either 4-bit LUT/D Flip-Flops or as 16-bit Counter/Delay.

When used to implement LUT function, the 4-bit LUT takes in four input signals from the Connection Matrix and produces a single

output, which goes back into the Connection Matrix.

When used to implement D Flip-Flop function, the two input signals from the connection matrix go to the data (D) and clock (CLK)

inputs for the Flip-Flop, with the output going back to the connection matrix.

When used to implement 16-Bit Counter/Delay function, two of the four input signals from the connection matrix go to the external

clock (EXT_CLK) and reset (DLY_IN/CNT Reset) for the Counter/Delay, with the output going back to the connection matrix.

This macrocell has an optional Finite State Machine (FSM) function. There are two additional matrix inputs for Up and Keep to

support FSM functionality

This macrocell can also operate in a one-shot mode, which will generate an output pulse of user-defined width.

This macrocell can also operate in a frequency detection or edge detection mode.

This macrocell can have its active count value read via I²C. See Section 15.6.1 for further details.

Note: After two DFF – counters initialize with counter data = 0 after POR.

Initial state = 1 – counters initialize with counter data = 0 after POR.

Initial state = 0 And After two DFF is bypass – counters initialize with counter data after POR.

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8.2.1 4-Bit LUT or DFF/LATCH with 16-Bit CNT/DLY Block Diagram

From Connection

Matrix Output [57]

IN3

register [1367] DFF or Latch Se-

S0

S1

lect

register [1366] DFF Output Select

(Q or nQ)

register [1365] DFF Initial Polarity

Select

S1

S0

S1

S0

IN2

IN1

From Connection

Matrix Output [56]

0

4-bit LUT1

S1

S0

S1

S0

0

OUT

IN0

LUT Truth

Table

From Connection

Matrix Output [55]

S1

S0

To Connection

S0

S1

S0

Matrix Input [15]

registers [1217:1216] =

00, 10, 11

16-bits NVM

registers [1367:1352]

1

S1

From Connection

Matrix Output [54]

DFF

D

S1

S0

Registers

S0

S1

S0

nSET

Q/nQ

DFF17

1

nRST

CLK

LUT/DFF Sel

register [1220]

registers [1222:1221]

registers [1383:1368]

CNT

registers [1219:1216]

Mode Selection

0

S0

S1

S2

S3

Data

ext_CLK

CMO* [56]

CMO* [55]

S0

S1

To Connection

Matrix Input [14]

S0

0

S0

S1

S2

S3

CMO* [57]

CMO* [56]

CMO* [55]

CMO* [54]

S1

S2

S3

OUT

CNT/DLY0

DLY_IN/CNT Reset

CMO* [55]

S1

S0

From Connection

Matrix Output [56]

0

KEEP

UP

From Connection

Matrix Output [57]

FSM

S1

S0

Config

Data

0

Note: CMO - Connection Matrix Output

registers [1238:1223],

[1337:1336]

registers [1217:1216] = 01

Figure 47: 4-bit LUT1 or CNT/DLY0

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8.2.2 4-Bit LUT or 16-Bit Counter/Delay Macrocells Used as 4-Bit LUTs

Table 52: 4-bit LUT1 Truth Table

IN3

0

IN2

0

IN1

0

IN0

0

OUT

register [1176]

register [1177]

register [1178]

register [1179]

register [1180]

register [1181]

register [1182]

register [1183]

register [1184]

register [1185]

register [1186]

register [1187]

register [1188]

register [1189]

register [1190]

register [1191]

LSB

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

MSB

This macrocell, when programmed for a LUT function, uses a 16-bit register to define their output function:

4-Bit LUT1 is defined by registers [1191:1176]

Table 53: 4-bit LUT Standard Digital Functions

Function

AND-4

MSB

LSB

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

NAND-4

OR-4

NOR-4

XOR-4

XNOR-4

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8.3 CNT/DLY/FSM TIMING DIAGRAMS

8.3.1 Delay Mode CNT/DLY0 to CNT/DLY7

Delay In

Asynchronous delay variable

OSC: force power-on

(always running)

Delay Output

delay = period x (counter data + 1) + variable

variable is from 0 to 1 clock period

delay = period x (counter data + 1) + variable

variable is from 0 to 1 clock period

Delay In

offset

OSC: auto power-on

(powers up from delay in)

Delay Output

delay = offset + period x (counter data + 1)

See offset in table 11

delay = offset + period x (counter data + 1)

See offset in table 11

Figure 48: Delay Mode Timing Diagram, Edge Select: Both, Counter Data: 3

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The macrocell shifts the respective edge to a set time and restarts by appropriate edge. It works as a filter, if the input signal is

shorter than the delay time.

Delay time

One-Shot/Freq. DET/Delay IN

t

Delay time

Delay Function

Rising Edge Detection

t

Delay Function

Falling Edge Detection

t

Delay Function

Both Edge Detection

t

Figure 49: Delay Mode Timing Diagram for Different Edge Select Mode

8.3.2 Count Mode (Count Data: 3), Counter Reset (Rising Edge Detect) CNT/DLY0 to CNT/DLY7

RESET_IN

CLK

Counter OUT

4 CLK period pulse

Count start in first rising edge CLK

Figure 50: Counter Mode Timing Diagram without Two DFFs Synced Up

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.

RESET_IN

CLK

Counter OUT

4 CLK period pulse

Count start in 0 CLK after reset

Figure 51: Counter Mode Timing Diagram with Two DFFs Synced Up

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8.3.3 One-Shot Mode CNT/DLY0 to CNT/DLY7

This macrocell will generate a pulse whenever a selected edge is detected on its input. Register bits set the edge selection. The

pulse width determines by counter data and clock selection properties. The output pulse polarity (non-inverted or inverted) is

selected by register bit. Any incoming edges will be ignored during the pulse width generation. The following diagram shows one-

shot function for non-inverted output.

Delay time

One-Shot/Freq. DET/Delay IN

t

Delay time

One-Shot Function

Rising Edge Detection

t

One-Shot Function

Falling Edge Detection

t

One-Shot Function

Both Edge Detection

t

Figure 52: One-Shot Function Timing Diagram

This macrocell generates a high level pulse with a set width (defined by counter data) when detecting the respective edge. It does

not restart while pulse is high.

8.3.4 Frequency Detection Mode CNT/DLY0 to CNT/DLY7

Rising Edge: The output goes high if the time between two successive edges is less than the delay. The output goes low if the

second rising edge has not come after the last rising edge in specified time.

Falling Edge: The output goes high if the time between two falling edges is less than the set time. The output goes low if the

second falling edge has not come after the last falling edge in specified time.

Both Edge: The output goes high if the time between the rising and falling edges is less than the set time, which is equivalent to

the length of the pulse. The output goes low if after the last rising/falling edge and specified time, the second edge has not come.

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Delay time

One-Shot/Freq. DET/Delay IN

t

Delay time

Frequency Detector Function

Rising Edge Detection

Frequency Detector Function

Falling Edge Detection

t

Frequency Detector Function

Both Edge Detection

Figure 53: Frequency Detection Mode Timing Diagram

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8.3.5 Edge Detection Mode CNT/DLY1 to CNT/DLY7

The macrocell generates high level short pulse when detecting the respective edge. See Table 12.

Delay time

One-Shot/Freq. DET/Delay IN

t

Edge Detector Function

Rising Edge Detection

Edge Detector Function

Falling Edge Detection

t

Edge Detector Function

Both Edge Detection

Figure 54: Edge Detection Mode Timing Diagram

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8.3.6 Delayed Edge Detection Mode CNT/DLY0 to CNT/DLY7

In Delayed Edge Detection Mode, High level short pulses are generated on the macrocell output after the configured delay time,

if the corresponding edge was detected on the input.

If the input signal is changed during the set delay time, the pulse will not be generated. See Figure 55.

Delay time

One-Shot/Freq. DET/Delay IN

Delay time

Delayed Edge Detector Function

t

Rising Edge Detection

Delayed Edge Detector Function

Falling Edge Detection

t

Delayed Edge Detector Function

Both Edge Detection

Figure 55: Delayed Edge Detection Mode Timing Diagram

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8.3.7 CNT/FSM Mode CNT/DLY0

RESET IN

KEEP

COUNT END

CLK

3

2

1

0

3

2

1

0

3

2

1

3

2

1

0

Q

Note: Q = current counter value

Figure 56: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP = 0) for Counter Data = 3

SET IN

KEEP

COUNT END

CLK

2

1

0

3

2

1

0

3

2

1

2

1

0

3

Q

Note: Q = current counter value

Figure 57: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced On, UP = 0) for Counter Data = 3

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RESETI N

KEEP

COUNT END

CLK

65535

65533 65534

5

6

7

8

9

3

4

5

3

4

5

1

2

3

4

0

Q

Note: Q = current counter value

Figure 58: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP = 1) for Counter Data = 3

SET IN

KEEP

COUNT END

CLK

65533 65534 65535

3

4

5

8

9

10 11 12

3

4

5

4

5

6

7

3

Q

Note: Q = current counter value

Figure 59: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator Is Forced On, UP = 1) for Counter Data = 3

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8.3.8 Difference in Counter Value for Counter, Delay, One-Shot, and Frequency Detect Modes

There is a difference in counter value for Counter and Delay/One-Shot/Frequency Detect modes. The counter value is shifted for

two rising edges of the clock signal in Delay/One-Shot/Frequency Detect modes compared to Counter mode. See Figure 60:

One-Shot/Freq. SET/Delay IN

CLK

CNT Out

3

2

1

0

CNT Data

3

2

DLY Out

Delay Data

3

2

1

3

One-Shot Out

One-Shot Data

3

2

1

3

Figure 60: Counter Value, Counter Data = 3

8.4 WAKE AND SLEEP CONTROLLER

The SLG46855-A has a Wake and Sleep function for all ACMPs. The macrocell CNT/DLY0 can be reconfigured for this purpose

registers [1032:1031] = 11 and register [1046] = 1. The WS serves for power saving, it allows to switch on and off selected ACMPs

on selected bit of 16-bit counter.

Note 1: BG/Analog_Good time is long and should be considered in wake and sleep timing in case it dynamically powers on/off.

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Note 2: Wake time should be long enough to make sure ACMP and Vref have enough time to get a sample before going to sleep.

Power Control

From Connection Matrix Output [80] for 2 kHz OSC0

WS Controller

OSC

CNT0_out

CNT_end

CNT

To Connection Matrix Input [14]

ck

Divider

CK_OSC

Analog Control Block

ACMPx WS EN:

registers [687], [688]

[695], [647]

4

bg/regulator

pdb

From Connection

Matrix Output [78:75]

WS_out

WS_PD

(from OSC PD)

ACMPs_PD

4

WS_out

WS_PD to W&S out

state selection

registers [1038:1035]

WS clock freq. selection

registers [1207:1192]

WS ratio control data

ACMPs

register [689]

WS mode: normal or short wake

Note: WS_PD is High at WS OSC

ACMP0..3 OUT

4

+

-

0

1

(2 kHz OSC0) power-down

4

To Connection

Matrix Input

[56:59]

ACMPs_PD

WS_out

BG/Analog_Good

Figure 61: Wake/Sleep Controller

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time between Reset goes low

and 1st WS clock rsing edge

Force Wake

CNT_RST

(From Connection Matrix)

ACMP_PD is High

(From Connection Matrix)

CNT0_out

(To Connection Matrix)

WS_out

(internal signal)

Data is latched

BG/Analog_Good

(internal signal)

Sleep Mode

ACMP Latches Last Data

Normal ACMP

Operation

ACMP follows input

Sleep Mode

ACMP Latches New Data

Normal ACMP

Sleep Mode

ACMP Latches

New Data

Operation

ACMP follows input

BG/Analog

Startup time*

BG/Analog

Startup time*

Note: CNT0_out is a delayed WS_out signal for 1us to make sure the data is correct during LATCH.

Figure 62: Wake/Sleep Timing Diagram, Normal Wake Mode, Counter Reset is Used

time between Reset goes low

and 1st WS clock rsing edge

Force Wake

CNT_RST

(From Connection Matrix)

ACMP_PD is High

(From Connection Matrix)

CNT0_out

(To Connection Matrix)

WS_out

(internal signal)

Data is latched

BG/Analog_Good

(internal signal)

Sleep Mode

ACMP Latches New Data

Normal ACMP

Operation for short time

ACMP follows inout

Sleep Mode

ACMP Latches

New Data

ACMP Latches Last Data

Normal ACMP

Operation for short time

ACMP follows inout

BG/Analog

Startup time*

BG/Analog

Startup time*

Note: CNT0_out is a delayed WS_out signal for 1us to make sure the data is correct during LATCH.

Figure 63: Wake/Sleep Timing Diagram, Short Wake Mode, Counter Reset is Used

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time between Reset goes low

and 1st WS clock rsing edge

Force Sleep

CNT_SET

(From Connection Matrix)

ACMP_PD is High

(From Connection Matrix)

CNT0_out

(To Connection Matrix)

WS_out

(internal signal)

Data is latched

BG/Analog_Good

(internal signal)

Sleep Mode

ACMP Latches Last Data

Normal ACMP

Operation

ACMP follows input

Sleep Mode

ACMP Latches New Data

BG/Analog

Startup time*

Note: CNT0_out is a delayed WS_out signal for 1us to make sure the data is correct during LATCH.

Figure 64: Wake/Sleep Timing Diagram, Normal Wake Mode, Counter Set is Used

time between Reset goes low

and 1st WS clock rsing edge

Force Sleep

CNT_RST

(From Connection Matrix)

ACMP_PD is High

(From Connection Matrix)

CNT0_out

(To Connection Matrix)

WS_out

(internal signal)

Data is latched

BG/Analog_Good

(internal signal)

Sleep Mode

ACMP Latches New Data

ACMP Latches Last Data

Normal ACMP

Operation for short time

ACMP follows inout

BG/Analog

Startup time*

Note: CNT0_out is a delayed WS_out signal for 1us to make sure the data is correct during LATCH.

Figure 65: Wake/Sleep Timing Diagram, Short Wake Mode, Counter Set is Used

Note: If low power BG is powered on/off by WS, the wake time should be longer than 2.1 ms. The BG/analog start up time will

take maximal 2 ms. Therefore, 8 periods of the Oscillator0 is recommended for the wake time, when BG is configured to Auto

Power mode. If low power BG is always on, Oscillator0 period is longer than required wake time. The BG/analog start up time will

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take maximal 450 us for ACMP0/1 and a shorter time for ACMP2/3. The short wake mode can be used to reduce the current

consumption.

To use any ACMP under WS controller, the following settings must be done:



ACMP Power Up Input from matrix = 1 (for each ACMP separately);

CNT/DLY0 must be set to Wake and Sleep Controller function (for all ACMP);

Register WS → enable (for each ACMP separately);

CNT/DLY0 set/reset input = 0 (for all ACMP).

The user can select a period of time while the ACMP is sleeping in a range of 1 - 65535 clock cycles. Before they are sent to

sleep their outputs are latched, so the ACMPs remain their state (High or Low) while sleeping.

WS controller has the following settings:



Wake and Sleep Output State (High/Low)

If OSC is powered off (Power-down option is selected; Power-down input = 1) and Wake and Sleep Output State = High, the

ACMP is continuously on.

If OSC is powered off (Power-down option is selected; Power-down input = 1) and Wake and Sleep Output State = Low, the

ACMP is continuously off.

Both cases WS function is turned off.



Counter Data (Range: 1 - 65535)

User can select wake and sleep ratio of the ACMP; counter data = sleep time, one clock = wake time.

Q mode - defines the state of WS counter data when Set/Reset signal appears Reset - when active signal appears, the WS

counter will reset to zero and High level signal on its output will turn on the ACMPs. When Reset signal goes out, the WS

counter will go Low and turn off the ACMP until the counter counts up to the end. Set - when active signal appears, the WS

counter will stop and Low level signal on its output will turn off the ACMP. When Set signal goes out, the WS counter will go on

counting and High level signal will turn on the ACMP while counter is counting up to the end.

Note: The OSC0 matrix power-down to control ACMP WS is not supported for short wait time option.



Edge Select defines the edge for Q mode

High level Set/Reset - switches mode Set/Reset when level is High

Note: Q mode operates only in case of "High Level Set/Reset”.



Wake time selection - time required for wake signal to turn the ACMPxH on

Normal Wake Time - when WS signal is High, it takes BG/analog start up time to turn the ACMPs on. They will stay on until

WS signal is Low again. Wake time is one clock period. It should be longer than BG turn on time and minimal required com-

paring time of the ACMP.

Short Wake Time - when WS signal is High, it takes BG/analog start up time to turn the ACMPs on. They will stay on for 1 µs

and turn off regardless of WS signal. The WS signal width does not matter.



Keep - pauses counting while Keep = 1

Up - reverses counting

If Up = 1, CNT is counting up from user selected value to 65535.

If Up = 0, CNT is counting down from user selected value to 0.

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9

Analog Comparators

There are two High Speed and two Low Power Rail-to-Rail General Purpose Analog Comparators (ACMP) macrocells in the

SLG46855-A. In order for the ACMP cells to be used in a GreenPAK design, the power up signals (ACMP0H PWR UP, ACMP1H

PWR UP, ACMP2L PWR UP, and ACMP3L PWR UP) need to be active. By connecting to signals coming from the Connection

Matrix, it is possible to have each ACMP be ON continuously, OFF continuously, or switched on periodically based on a digital

signal coming from the Connection Matrix. When ACMP is powered down, its output is low.

Two of the four General Purpose Analog Comparators are optimized for high speed operation (ACMP0H and ACMP1H), and two

other are optimized for low power operation (ACMP2L and ACMP3L).

Each of the ACMP cells has a positive input signal that can be provided by a variety of external sources, and can also have a

selectable gain stage (1x, 0.5x, 0.33x, 0.25x) before connection to the analog comparator. The gain divider is unbuffered and has

input resistance of 2 MΩ (typ) for 0.5x, 0.33x, 0.25x, and 10 GΩ for 1x. Each of the ACMP cells has a negative input signal that

is either created from an internal Vref or provided by any external source (GPIO2 and GPO0). Note that the external Vref signal

is filtered with a 2nd order low pass filter with 8 kHz typical bandwidth, see Figure 66 to Figure 69.

Input bias current < 1 nA (typ).

PWR UP = 1 => ACMP is powered up.

PWR UP = 0 => ACMP is powered down.

During power-up, the ACMP output will remain LOW, and then becomes valid in 37 μs (max) after power up signal goes high for

ACMP0H and ACMP1H, and becomes valid 294 μs (max) after power up signal goes high for ACMP2L and ACMP3L.

Each High Speed ACMP (ACMP0H and ACMP1H) has an optional Rail-to-Rail Input Buffer, which can be used along with the

Gain divider to increase ACMP input resistance. However, Input buffer will increase an input offset voltage.

Each cell also has a hysteresis selection, to offer hysteresis of (0, 32, 64, 192) mV. The hysteresis option is available when using

an internal Vref only.

The ACMP0H has an additional option of connecting an internal 100 μA current source to its positive input, register [690]. It is

also possible to connect the 100 μA current source to each next ACMP via an internal analog MUX.

ACMP0H IN+ options are GPIO4, buffered GPIO4, V_DD, 100 µA Current Source

ACMP1H IN+ options are GPIO5, buffered GPIO5, ACMP0H IN+ MUX output

ACMP2L IN+ options are GPIO6, ACMP0H IN+ MUX output, ACMP1H IN+ MUX output

ACMP3L IN+ options are GPIO7, ACMP2L IN+ MUX output, Temp Sensor OUT

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9.1 ACMP0H BLOCK DIAGRAM

to ACMP1H, ACMP2L, AC-

V_DD= 1.8 V

MP3L’s MUX input

registers [652:651]

100 µA

Current

Source

register [690]

en

Hysteresis

Selection

registers [697:696]

ACMP

Ready

01

00

10

GPIO4: ACMP0H(+)

Selectable

Gain

+

To Connection

Matrix Input [56]

0

1

Internal V_DD2.3V ~ 5.5 V

Vref

-

PWR UP

Latch

HighSpeed

ACMP

*GPIO4 _aio_en; registers [656]; [654]

register [687]

W/S Control

Ext. Vref0 (GPIO2)

111111

LPF*

From Connection

Matrix Output [75]

111110-

000000

Internal

Vref

Note*: 2nd order low pass filter

with typical bandwidth 8 kHz

registers [703:698]

Figure 66: ACMP0H Block Diagram

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9.2 ACMP1H BLOCK DIAGRAM

to ACMP2L’s MUX input

registers [660:659]

Hysteresis

Selection

registers [705:704]

ACMP

Ready

00

01

10

GPIO5: ACMP1H(+)

Selectable

Gain

+

-

To Connection

Matrix Input [57]

0

1

ACMP0H IN+ MUX Output

Vref

PWR UP

Latch

HighSpeed

ACMP

*GPIO5_aio_en; registers [661], [657]

register [688]

W/S Control

Ext. Vref0 (GPIO2)

0

LPF*

111111

Ext. Vref1 (GPO0)

1

register [644]

From Connection

Matrix Output [76]

111110-

000000

Internal

Vref

Note*: 2nd order low pass filter

with typical bandwidth 8 kHz

registers [711:706]

Figure 67: ACMP1H Block Diagram

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9.3 ACMP2L BLOCK DIAGRAM

registers [666:665]

Hysteresis

Selection

registers [713:712]

GPIO6: ACMP2L(+)

ACMP

Ready

00

from ACMP0H’s MUX output

Selectable

Gain

+

01

To Connection

Matrix Input [58]

0

1

from ACMP1H’s MUX output

10

Vref

-

PWR UP

Latch

Low Power

ACMP

*GPIO6_aio_en; registers [664], [663]

register [695]

W/S Control

Ext.Vref0 (GPIO2)

0

LPF*

111111

Ext. Vref1 (GPO0)

1

register [645]

111110-

000000

From Connection

Matrix Output [77]

Low

Power

Internal

Vref

Note*: 2nd order low pass filter

with typical bandwidth 8 kHz

registers [719:714]

Figure 68: ACMP2L Block Diagram

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9.4 ACMP3L BLOCK DIAGRAM

registers [670:669]

Hysteresis

Selection

registers [721:720]

GPIO7: ACMP3L(+)

ACMP

Ready

00

01

10

ACMP2L IN+ MUX Output

Selectable

Gain

+

-

To Connection

Matrix Input[59]

0

1

Vref

PWR UP

Latch

Low Power

ACMP

*GPIO7_aio_en; registers [693], [673]

register [647]

W/S Control

Ext. Vref0 (GPIO2)

0

LPF*

111111

Ext. Vref1 (GPO0)

1

register [646]

From Connection

Low

Matrix Output [78]

111110-

000000

Power

Internal

Vref

Low Power

ACMP

Note*: 2nd order low pass filter

with typical bandwidth 8 kHz

registers [727:722]

Figure 69: ACMP3L Block Diagram

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9.5 ACMP TYPICAL PERFORMANCE

6

5

4

High To Low, Overdrive = 5 mV

High To Low, Overdrive = 10 mV

High To Low, Overdrive = 100 mV

Low to High, Overdrive = 5 mV

Low to High, Overdrive = 10 mV

Low to High, Overdrive = 100 mV

3

2

1

0

32

480

1024

Vref (mV)

1600

2016

Figure 70: Typical Propagation Delay vs. Vref for ACMPxH at T = 25 °C, Gain = 1, Hysteresis = 0

150

High To Low, Overdrive = 5 mV

Low to High, Overdrive = 5 mV

130

High To Low, Overdrive = 10 mV

Low to High, Overdrive = 10 mV

High To Low, Overdrive = 100 mV

Low to High, Overdrive = 100 mV

110

90

70

50

30

10

32

480

1024

1600

2016

Vref (mV)

Figure 71: Typical Propagation Delay vs. Vref for ACMPxL at T = 25 °C, Gain = 1, Hysteresis = 0

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25

T = -40 °C

T = 25 °C

20

T = 105 °C

15

10

5

0

2.3

2.6

2.9

3.2

3.5

3.8

V_DD(V)

4.1

4.4

4.7

5.0

5.3

Figure 72: ACMPxH Power-On Delay vs. V_DD

.

200

T = -40 °C

T = 25 °C

T = 105 °C

180

160

140

120

100

80

60

2.3

2.6

2.9

3.2

3.5

3.8

V_DD(V)

4.1

4.4

4.7

5.0

5.3

Figure 73: ACMPxL Power-On Delay vs. V_DD

.

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8

6

4

2

0

-2

-4

-6

-8

32

480

1024

1600

2016

Vref (mV)

Figure 74: ACMPxH Input Offset Voltage vs. Vref at T = -40 °C to 105 °C

5

4

3

2

1

0

-1

-2

-3

-4

32

480

1024

1600

2016

Vref (mV)

Figure 75: ACMPxL Input Offset Voltage vs. Vref at T = -40 °C to 105 °C

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10 Programmable Delay/Edge Detector

The SLG46855-A has a programmable time delay logic cell that can generate a delay that is selectable from one of four timings

(time2) configured in the GreenPAK Designer. The programmable time delay cell can generate one of four different delay patterns,

rising edge detection, falling edge detection, both edge detection, and both edge delay. These four patterns can be further

modified with the addition of delayed edge detection, which adds an extra unit of delay, as well as glitch rejection during the delay

period. See Figure 76 for further information.

Note: The input signal must be longer than the delay, otherwise it will be filtered out.

registers [1453:1452]

Delay Value Selection

registers [1455:1454]

Edge Mode Selection

To Connection

Matrix Input [42]

Programmable

From Connection Matrix Output [54]

IN

OUT

Delay

Figure 76: Programmable Delay

10.1 PROGRAMMABLE DELAY TIMING DIAGRAM - EDGE DETECTOR OUTPUT

width

IN

time1

Rising Edge Detector

time1

Falling Edge Detector

Edge Detector

Output

Both Edge Detector

Both Edge Delay

time2

time1 is a fixed value

time2 delay value is selected via register

Figure 77: Edge Detector Output

Please refer to Table 12.

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11 Additional Logic Function. Deglitch Filter

The SLG46855-A has one Deglitch Filter macrocell with inverter function that is connected directly to the Connection Matrix inputs

and outputs. In addition, this macrocell can be configured as an Edge Detector, with the following settings:



Rising Edge Detector

Falling Edge Detector

Both Edge Detector

Both Edge Delay

Filter

R

From Connection Matrix

Output [55]

C

To Connection Matrix

Input [43]

Edge

Detector

Logic

register [1448]

registers [1451:1450]

register [1449]

Figure 78: Deglitch Filter/Edge Detector

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12 Voltage Reference

12.1 VOLTAGE REFERENCE OVERVIEW

The SLG46855-A has a Voltage Reference (Vref) macrocell to provide references to the four analog comparators. This macrocell

can supply a user selection of fixed voltage references, or temperature sensor output. The macrocell also has the option to output

reference voltages on GPIO8 and GPIO9. See Table 53 for the available selections for each analog comparator.

Also see Figure 79, which shows the reference output structure.

12.2 VREF SELECTION TABLE

Table 54: Vref Selection Table

SEL[5:0]

0

Vref

0.032

0.064

0.096

0.128

0.16

SEL[5:0]

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

Vref

1.056

1.088

1.12

1

2

3

1.152

1.184

1.216

1.248

1.28

4

5

0.192

0.224

0.256

0.288

0.32

6

7

8

1.312

1.344

1.376

1.408

1.44

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

0.352

0.384

0.416

0.448

0.48

1.472

1.504

1.536

1.568

1.6

0.512

0.544

0.576

0.608

0.64

1.632

1.664

1.696

1.728

1.76

0.672

0.704

0.736

0.768

0.8

1.792

1.824

1.856

1.888

1.92

0.832

0.864

0.896

0.928

0.96

1.952

1.984

2.016

External

0.992

1.024

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12.3 VREF BLOCK DIAGRAM

External Vref

registers [703:698]

(GPIO2,

None

00

01

10

11

GPO0)

ACMP0H_Vref0

GPIO8_aio_en

VrefOut_0 (GPIO8)

1

0

OP

pd

registers [711:706]

ACMP1H_Vref0

registers [679:678]

register [677]

Temp Sensor

register [648]

0

From Matrix

Output [79]

1

register [649]

None

00

01

10

11

registers [719:714]

GPIO9_aio_en

VrefOut_1 (GPIO9)

1

0

OP

pd

ACMP2L_Vref1

registers [727:722]

registers [682:681]

ACMP3L_Vref1

register [680]

register [650]

0

1

From Matrix

Output [79]

register [694]

Figure 79: Voltage Reference Block Diagram

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12.4 VREF LOAD REGULATION

Note 1 It is not recommended to use Vref connected to external pin without buffer.

Note 2 Vref buffer performance is not guaranteed at V_DD< 2.7 V.

350

300

250

200

150

100

VDD = 5 V

VDD = 3.3 V

VDD = 2.5 V

50

0

1

2

3

4

5

6

7

8

9

10

I, mA

Figure 80: Typical Load Regulation, Vref = 320 mV, T = -40 °C to +105 °C, Buffer - Enabled

700

600

500

400

300

200

VDD = 5 V

VDD = 3.3 V

VDD = 2.5 V

100

0

1

2

3

4

5

6

7

8

9

10

I, mA

Figure 81: Typical Load Regulation, Vref = 640 mV, T = -40 °C to +105 °C, Buffer - Enabled

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1400

1200

1000

800

600

400

VDD = 5 V

VDD = 3.3 V

VDD = 2.5 V

200

0

1

2

3

4

5

6

7

8

9

10

I, mA

Figure 82: Typical Load Regulation, Vref = 1280 mV, T = -40 °C to +105 °C, Buffer - Enabled

2100

1800

1500

1200

900

600

VDD = 5 V

VDD = 3.3 V

VDD = 2.5 V

300

0

1

2

3

4

5

6

7

8

9

10

I, mA

Figure 83: Typical Load Regulation, Vref = 2016 mV, T = -40 °C to +105 °C, Buffer - Enabled

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13 Clocking

13.1 OSC GENERAL DESCRIPTION

The SLG46855-A has three internal oscillators to support a variety of applications:



Oscillator0 (2.048 kHz)

Oscillator1 (2.048 MHz)

Oscillator2 (25 MHz).

There are two divider stages for each oscillator that gives the user flexibility for introducing clock signals to connection matrix, as

well as various other macrocells. The pre-divider (first stage) for Oscillator allows the selection of /1, /2, /4 or /8 to divide down

frequency from the fundamental. The second stage divider has an input of frequency from the pre-divider, and outputs one of

eight different frequencies divided by /1, /2, /3, /4, /8, /12, /24 or /64 on Connection Matrix Input lines [53], [54], and [55]. Please

see Figure 87 for more details on the SLG46855-A clock scheme.

Oscillator2 (25 MHz) has an additional function of 100 ns delayed startup, which can be enabled/disabled by register [749]. This

function is recommended to use when analog blocks are used along with the Oscillator.

The Matrix Power-down/Force On function allows switching off or force on the oscillator using an external pin. The Matrix Power-

down/Force On (Connection Matrix Output [80], [81], [82]) signal has the highest priority. The OSC operates according to the

following table:

Table 55: Oscillator Operation Mode Configuration Settings

OSC Enable

Signal from

CNT/DLY

Register:

Power-Down

or Force On by

Matrix Input

OSC

Operation

Mode

Signal From

Connection

Matrix

Register: Auto

Power-On or

Force On

External Clock

Selection

POR

Macrocells

0

1

X

1

X

OFF

Internal OSC is

OFF, logic is ON

1

0

1

0

1

X

1

X

OFF

ON

CNT/DLY re-

quires OSC

1

0

X

0

CNT/DLY does

not require OSC

OFF

Note 1 The OSC will run only when any macrocell that uses OSC is powered on.

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13.2 OSCILLATOR0 (2.048 KHZ)

From Connection Matrix

Output [80]

PWR_DWN/Force On

Matrix Output control register [751]

OSC Power Mode

register [750]

2.048 kHz Pre-divided Clock

PWR DOWN/

FORCE ON

registers [755:754]

OSC0

Auto Power-On

Force Power-On

(2.048 kHz) ^OUT

0

1

0

1

DIV /1 /2 /4 /8

0

1

Ext. Clock

Pre-divider

/ 2

/ 3

2

3

4

5

6

7

EXT_CLK Sel register [752]

To Connection Matrix

Input [53]

/ 4

OUT0

/ 8

OUT1

To Connection Matrix

Input [60]

/ 12

/ 24

/ 64

registers [758:756]

registers [766:764]

Second Stage

Divider

Figure 84: Oscillator0 Block Diagram

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13.3 OSCILLATOR1 (2.048 MHZ)

From Connection Matrix

Output [81]

PWR_DWN/Force On

Matrix Output control register [729]

OSC Power Mode

register [728]

2.048 MHz Pre-divided Clock

PWR DOWN/

FORCE ON

registers [732:731]

OSC1

Auto Power-On

Force Power-On

(2.048 MHz)^OUT

0

1

DIV /1 /2 /4 /8

0

1

Ext. Clock

Pre-divider

1

/ 2

/ 3

2

3

4

5

6

EXT_CLK Sel register [730]

To Connection Matrix

Input [54]

/ 4

OUT0

/ 8

OUT1

To Connection Matrix

Input [61]

/ 12

/ 24

/ 64

7

registers [735:733]

registers [762:760]

Second Stage

Divider

Figure 85: Oscillator1 Block Diagram

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13.4 OSCILLATOR2 (25 MHZ)

From Connection Matrix

Output [82]

PWR_DWN/Force On

Matrix Output control register [741]

OSC Power Mode

register [740]

25 MHz Pre-divided Clock

PWR DOWN/

FORCE ON

registers [745:744]

OSC2

(25 MHz)

Auto Power-On

Force Power-On

OUT

0

1

Startup delay

DIV /1 /2 /4 /8

0

1

register [749]

Pre-divider

1

/ 2

/ 3

Ext. Clock

2

3

4

5

6

EXT_CLK Sel register [742]

To Connection Matrix

Input [55]

/ 4

/ 8

/ 12

/ 24

/ 64

7

registers [748:746]

Second Stage

Divider

Figure 86: Oscillator2 Block Diagram

13.5 CNT/DLY CLOCK SCHEME

Each CNT/DLY within Multi-Function macrocell has its own additional clock divider connected to oscillators pre-divider. Available

dividers are:



OSC0/1, OSC0/8, OSC0/64, OSC0/512, OSC0/4096, OSC0/32768, OSC0/262144

OSC1/1, OSC1/8, OSC1/64, OSC1/512

OSC2/1, OSC2/4

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registers [3:0]

0

1

25 MHz Pre-divided clock

Div4

2

Div8

Div64

Div512

3

4

5

6

CNT/DLY/

ONESHOT/

FREQ_DET/

2.048 MHz Pre-divided clock

DLY_EDGE_DET

Div8

Div64

7

8

CNT overflow

2.048 kHz Pre-divided clock

Div512

9

Div4096

Div32768

Div262144

10

11

12

13

14

15

CNT (x-1) overflow

from Connection Matrix Out

(separate for each CNT/DLY macrocell)

CNT0/CNT1/CNT2/CNT3/

CNT4/CNT5/CNT6/CNT7

none

Figure 87: Clock Scheme

13.6 EXTERNAL CLOCKING

The SLG46855-A supports several ways to use an external, higher accuracy clock as a reference source for internal operations.

13.6.1 GPI0 Source for Oscillator0 (2.048 kHz)

When register [752] is set to 1, an external clocking signal on GPI0 will be routed in place of the internal oscillator derived 2.048

kHz clock source. See Figure 84. The low and high limits for external frequency that can be selected are 0 MHz and 10 MHz.

13.6.2 GPIO2 Source for Oscillator1 (2.048 MHz)

When register [730] is set to 1, an external clocking signal on GPIO2 will be routed in place of the internal oscillator derived

2.048 MHz clock source. See Figure 85. The low and high limits for external frequency that can be selected are 0 MHz and

10 MHz.

13.6.3 GPIO8 Source for Oscillator 2 (25 MHz)

When register [742] is set to 1, an external clocking signal on GPIO8 will be routed in place of the internal oscillator derived 25

MHz clock source. See Figure 86. The external frequency range is 0 MHz to 20 MHz at V_DD= 2.3 V, 30 MHz at V_DD= 3.3 V, 50

MHz at V_DD= 5.0 V.

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13.7 OSCILLATORS POWER-ON DELAY

OSC enable

Power-On

Delay

CLK

Figure 88: Oscillator Startup Diagram

Note 1 OSC power mode: “Auto Power-On”.

Note 2 “OSC enable” signal appears when any macrocell that uses OSC is powered on.

1000

950

900

850

800

750

700

650

600

550

500

2.4

2.7

3

3.3

3.6

3.9

4.2

4.5

4.8

5.1

5.4

V_DD(V)

Figure 89: Oscillator0 Maximum Power-On Delay vs. V_DDat T = 25 °C, OSC0 = 2.048 kHz

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560

540

520

500

480

460

440

420

400

2.4

2.7

3

3.3

3.6

3.9

4.2

4.5

4.8

5.1

5.4

V_DD(V)

Figure 90: Oscillator1 Maximum Power-On Delay vs. V_DDat T = 25 °C, OSC1 = 2.048 MHz

180

160

140

120

100

80

60

40

20

0

2.4

2.7

3

3.3

3.6

3.9

4.2

4.5

4.8

5.1

5.4

V_DD(V)

Figure 91: Oscillator2 Maximum Power-On Delay vs. V_DDat T = 25 °C, OSC2 = 25 MHz

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13.8 OSCILLATORS ACCURACY

Note: OSC power setting: Force Power-On; Clock to matrix input - enable; Bandgap: turn on by register - enable.

2.15

2.1

2.05

2

1.95

1.9

1.85

1.8

Fmax @ VDD = 2.3 V to 5.5 V

1.75

Ftyp @ VDD = 3.3 V

1.7

Fmin @ VDD = 2.3 V to 5.5 V

1.65

T (°C)

Figure 92: Oscillator0 Frequency vs. Temperature, OSC0 = 2.048 kHz

2.1

2.08

2.06

2.04

2.02

2

1.98

1.96

Fmax @ VDD = 5.5 V

Fmax @ VDD = 3.3 V

1.94

1.92

1.9

Fmax @ VDD = 2.3 V

Ftyp @ VDD = 3.3 V

Fmin @ VDD = 5.5 V

Fmin @ VDD = 3.3 V

1.88

T (°C)

Figure 93: Oscillator1 Frequency vs. Temperature, OSC1 = 2.048 MHz

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25.9

25.7

25.5

25.3

25.1

24.9

24.7

24.5

24.3

24.1

Fmax @ VDD = 5.5 V

Fmax @ VDD = 3.3 V

Fmax @ VDD = 2.3 V

23.9

Ftyp @ VDD = 3.3 V

23.7

Fmin @ VDD = 5.5 V

23.5

23.3

Fmin @ VDD = 3.3 V

Fmin @ VDD = 2.3 V

T (°C)

Figure 94: Oscillator2 Frequency vs. Temperature, OSC2 = 25 MHz

18

16

14

12

10

8

2.048 kHz Total Error @ VDD = 2.3 V to 5.5 V

25 MHz Total Error @ VDD = 2.3 V to 5.5 V

2.048 MHz Total Error @ VDD = 2.3 V to 5.5 V

6

4

2

0

T (°C)

Figure 95: Oscillators Total Error vs. Temperature

Note: For more information see Section 3.9.

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14 Power-On Reset

The SLG46855-A has a Power-On Reset (POR) macrocell to ensure correct device initialization and operation of all macrocells

in the device. The purpose of the POR circuit is to have consistent behavior and predictable results when the V_DDpower is first

ramping to the device, and also while the V_DDis falling during Power-down. To accomplish this goal, the POR drives a defined

sequence of internal events that trigger changes to the states of different macrocells inside the device, and finally to the state of

the IOs.

14.1 GENERAL OPERATION

The SLG46855-A is guaranteed to be powered down and non-operational when the V_DDvoltage (voltage on PIN1) is less than

Power-Off Threshold (see in Table 6), but not less than -0.6 V. Another essential condition for the chip to be powered down is that

no voltage higher (Note) than the V_DDvoltage is applied to any other PIN. For example, if V_DDvoltage is 0.3 V, applying a voltage

higher than 0.3 V to any other PIN is incorrect, and can lead to incorrect or unexpected device behavior.

Note: There is a 0.6 V margin due to forward drop voltage of the ESD protection diodes.

To start the POR sequence in the SLG46855-A, the voltage applied on the V_DDshould be higher than the Power-On threshold

(Note). The full operational V_DDrange for the SLG46855-A is 2.3 V to 5.5 V. This means that the V_DDvoltage must ramp up to

the operational voltage value, but the POR sequence will start earlier, as soon as the V_DDvoltage rises to the Power-On threshold.

After the POR sequence has started, the SLG46855-A will have a typical period of time to go through all the steps in the sequence

(noted in the datasheet for that device), and will be ready and completely operational after the POR sequence is complete.

Note: The Power-On threshold is defined in Table 6.

To power down the chip the V_DDvoltage should be lower than the operational and to guarantee that chip is powered down it

should be less than Power-Off Threshold.

All PINs are in high impedance state when the chip is powered down and while the POR sequence is taking place. The last step

in the POR sequence releases the IO structures from the high impedance state, at which time the device is operational. The pin

configuration at this point in time is defined by the design programmed into the chip. Also, as it was mentioned before the voltage

on PINs can’t be bigger than the V_DD, this rule also applies to the case when the chip is powered on.

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14.2 POR SEQUENCE

The POR system generates a sequence of signals that enable certain macrocells. The sequence is shown in Figure 96.

V_DD

t

POR_NVM

(reset for NVM)

NVM_ready_out

POR_GPI

(reset for input enable)

POR_LUT

(reset for LUT/FILTER)

POR_CORE

(reset for DLY/OSC/DFF/LATCH/

Pipe DLY/ACMP/

Edge Detector in Filter)

POR_OUT

(generate low to high to matrix)

POR_GPO

(reset for output enable)

Figure 96: POR Sequence

As can be seen from Figure 96 after the V_DDhas start ramping up and crosses the Power-On threshold, first, the on-chip NVM

memory is reset. Next, the chip reads the data from NVM, and transfers this information to a CMOS LATCH that serves to configure

each macrocell, and the Connection Matrix which routes signals between macrocells. The third stage causes the reset of the input

pins, and then to enable them. After that, the LUTs are reset and become active. After LUTs the Delay cells, OSCs, DFFs,

LATCHES, and Pipe Delay are initialized. Only after all macrocells are initialized internal POR signal (POR macrocell output) goes

from LOW to HIGH. The last portion of the device to be initialized are the output pins, which transition from high impedance to

active at this point.

The typical time that takes to complete the POR sequence varies by device type in the GreenPAK family. It also depends on many

environmental factors, such as: slew rate, V_DDvalue, temperature, and even will vary from chip to chip (process influence).

14.3 MACROCELLS OUTPUT STATES DURING POR SEQUENCE

To have a full picture of SLG46855-A operation during powering and POR sequence, review the overview the macrocell output

states during the POR sequence (Figure 97 describes the output signals states).

First, before the NVM has been reset, all macrocells have their output set to logic LOW (except the output pins which are in high

impedance state). On the next step, some of the macrocells start initialization: input pins output state becomes LOW; LUTs also

output LOW. Only P_DLY macrocell configured as edge detector becomes active at this time. After that input pins are enabled.

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Next, only LUTs are configured. Next, all other macrocells are initialized. After macrocells are initialized, internal POR matrix signal

switches from LOW to HIGH. The last are output pins that become active and determined by the input signals.

V_DD

Guaranteed HIGH before POR_GPI

Unpredictable

t

V_DD_out

to matrix

t

Input PIN _out

to matrix

Unpredictable

Determined by External Signal

Determined by Input signals

LUT/FILTER_out

to matrix

Determined by input signals

OUT = IN without Delay

t

Programmable Delay_out

to matrix

Determined by Input signals

Starts to detect input edges

Determined by initial state

DFF/LATCH/ACMP/

Edge Detector in

Filter_out to matrix

Determined by Input signals

Determined by input signals

OUT = IN without Delay

Delay_out

to matrix

Determined by Input signals

Starts to detect input edges

POR_out

to matrix

Unpredictable

Ext. GPO

Tri-state

Determined by input signals

Output State Unpredictable

Figure 97: Internal Macrocell States During POR Sequence

14.3.1 Initialization

All internal macrocells by default have initial low level. Starting from indicated power-up time of 1.56 V to 2.03 V, macrocells in

SLG46855-A are powered on while forced to the reset state. All outputs are in Hi-Z and chip starts loading data from NVM. Then

the reset signal is released for internal macrocells and they start to initialize according to the following sequence:

1. Input pins, ACMP, Pull-up/down.

2. LUTs.

3. DFFs, Delays/Counters, Pipe Delay.

4. POR output to matrix.

5. Output pin corresponds to the internal logic.

The Vref output pin driving signal can precede POR output signal going high by 3 µs to 5 µs. The POR signal going high indicates

the mentioned power-up sequence is complete.

Note: The maximum voltage applied to any pin should not be higher than the V_DDlevel. There are ESD Diodes between pin →

V_DDand pin → GND on each pin. So, if the input signal applied to pin is higher than V_DD, then current will sink through the diode

to V_DD. Exceeding V_DDresults in leakage current on the input pin, and V_DDwill be pulled up, following the voltage on the input

pin.There is no effect from input pin when input voltage is applied at the same time as V_DD

.

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14.3.2 Power-Down

V_DD(V)

2 V

1.63 V

0.83 V

1 V Vref Out Signal

1 V

Time

Not guaranteed output state

Figure 98: Power-Down

During power-down, macrocells in SLG46855-A are powered off after V_DDfalling down below Power-Off Threshold. Please note

that during a slow rampdown, outputs can possibly switch state during this time.

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2

15 I C Serial Communications Macrocell

15.1 I²C SERIAL COMMUNICATIONS MACROCELL OVERVIEW

In the standard use case for the GreenPAK devices, the configuration choices made by the user are stored as bit settings in the

Non-Volatile Memory (NVM), and this information is transferred at startup time to volatile RAM registers that enable the configu-

ration of the macrocells. Other RAM registers in the device are responsible for setting the connections in the Connection Matrix

to route signals in the manner most appropriate for the user’s application.

The I²C Serial Communications Macrocell in this device allows an I²C bus Master to read and write this information via a serial

channel directly to the RAM registers, allowing the remote re-configuration of macrocells, and remote changes to signal chains

within the device.

An I²C bus Master is also able to read and write other register bits that are not associated with NVM memory. As an example,

the input lines to the Connection Matrix can be read as digital register bits. These are the signal outputs of each of the macrocells

in the device, giving an I²C bus Master the capability to remotely read the current value of any macrocell.

The user has the flexibility to control read access and write access via registers bits registers [1967:1965]. See Section 15.5 for

more details on I²C read/write memory protection.

15.2 I²C SERIAL COMMUNICATIONS DEVICE ADDRESSING

Each command to the I²C Serial Communications macrocell begins with a Control Byte. The bits inside this Control Byte are

shown in Figure 99. After the Start bit, the first four bits are a control code. Each bit in a control code can be sourced independently

from the register or by value defined externally GPI0, GPIO2, GPIO4, and GPIO5. The LSB of the control code is defined by the

value of GPI0, while the MSB is defined by the value of GPIO5. The address source (either register bit or PIN) for each bit in the

control code is defined by registers [2027:2024]. This gives the user flexibility on the chip level addressing of this device and other

devices on the same I²C bus. The Block Address is the next three bits (A10, A9, A8), which will define the most significant bits

in the addressing of the data to be read or written by the command. The last bit in the Control Byte is the R/W bit, which selects

whether a read command or write command is requested, with a “1” selecting for a Read command, and a “0” selecting for a Write

command. This Control Byte will be followed by an Acknowledge bit (ACK), which is sent by this device to indicate successful

communication of the Control Byte data.

In the I²C-bus specification and user manual, there are two groups of eight addresses (0000 xxx and 1111 xxx) that are reserved

for the special functions, such as a system General Call address. If the user of this device choses to set the Control Code to either

“1111” or “0000” in a system with other slave device, please consult the I²C-bus specification and user manual to understand the

addressing and implementation of these special functions, to insure reliable operation.

In the read and write command address structure, there are a total of 11 bits of addressing, each pointing to a unique byte of

information, resulting in a total address space of 2K bytes. Of this 2K byte address space, the valid addresses accessible to the

I²C Macrocell on the SLG46855-A are in the range from 0 (0x00) to 255 (0xFF). The MSB address bits (A10, A9, and A8) will be

“0” for all commands to the SLG46855-A.

With the exception of the Current Address Read command, all commands will have the Control Byte followed by the Word

Address. Figure 99 shows this basic command structure.

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Start

bit

Acknowledge

bit

Control Byte

Word Address

A

10

A

9

A

8

A

7

A

0

S

X

R/W ACK

Control

Code

Block

Address

Not used, set t

o 0

Read/Write bit

(1 = Read, 0 = Write)

Figure 99: Basic Command Structure

15.3 I²C SERIAL GENERAL TIMING

General timing characteristics for the I²C Serial Communications macrocell are shown in Figure 100. Timing specifications can

be found in the AC Characteristics section.

t_HIGH

t_F

t_R

t_LOW

SCL

t_{SU STA}

t_{HD DAT}

t_{HD STA}

t_{SU DAT}

t_{SU STO}

SDA IN

t_BUF

t_AA

t_DH

SDA OUT

Figure 100: I²C General Timing Characteristics

15.4 I²C SERIAL COMMUNICATIONS COMMANDS

15.4.1 Byte Write Command

Following the Start condition from the Master, the Control Code [4 bits], the Block Address [3 bits], and the R/W bit (set to “0”) are

placed onto the I²C bus by the Master. After the SLG46855-A sends an Acknowledge bit (ACK), the next byte transmitted by the

Master is the Word Address. The Block Address (A10, A9, A8), combined with the Word Address (A7 through A0), together set

the internal address pointer in the SLG46855-A, where the data byte is to be written. After the SLG46855-A sends another

Acknowledge bit, the Master will transmit the data byte to be written into the addressed memory location. The SLG46855-A again

provides an Acknowledge bit and then the Master generates a Stop condition. The internal write cycle for the data will take place

at the time that the SLG46855-A generates the Acknowledge bit.

It is possible to latch all IOs during I²C write command, register [1961] = 1 - Enable. It means that IOs will remain their state until

the write command is done.

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Acknowledge

bit

Acknowledge

bit

Start

bit

Acknowledge

bit

Bus Activity

Control Byte

Word Address

Data

A

10

A

9

A

8

A

7

A

0

D

7

D

0

S

X

W

ACK

SDA LINE

P

Control

Code

Block

Address

Stop

bit

Not used, set to

0

R/W bit = 0

Figure 101: Byte Write Command, R/W = 0

15.4.2 Sequential Write Command

The write Control Byte, Word Address, and the first data byte are transmitted to the SLG46855-A in the same way as in a Byte

Write command. However, instead of generating a Stop condition, the Bus Master continues to transmit data bytes to the

SLG46855-A. Each subsequent data byte will increment the internal address counter, and will be written into the next higher byte

in the command addressing. As in the case of the Byte Write command, the internal write cycle will take place at the time that the

SLG46855-A generates the Acknowledge bit.

Acknowledge

bit

Start

bit

Bus Activity

SDA LINE

Not used, se

Data (n + 1)

Data (n + x)

Control Byte

Word Address (n)

Data (n)

A

10

A

9

A

8

ACK

P

S

X

W

ACK

Control

Code

Block

Address

Stop

bit

t to 0

Write bit

Figure 102: Sequential Write Command

15.4.3 Current Address Read Command

The Current Address Read Command reads from the current pointer address location. The address pointer is incremented at the

first STOP bit following any write control byte. For example, if a Sequential Read command (which contains a write control byte)

reads data up to address n, the address pointer would get incremented to n + 1 upon the STOP of that command. Subsequently,

a Current Address Read that follows would start reading data at n + 1. The Current Address Read Command contains the Control

Byte sent by the Master, with the R/W bit = “1”. The SLG46855-A will issue an Acknowledge bit, and then transmit eight data bits

for the requested byte. The Master will not issue an Acknowledge bit, and follow immediately with a Stop condition.

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Start

bit

Acknowledge

bit

Stop

bit

Bus Activity

Control Byte

Data (n)

A

10

A

9

A

8

S

X

R

ACK

SDA LINE

P

Control

Code

Block

Address

No ACK

bit

Not used, set to

0

R/W bit = 1

Figure 103: Current Address Read Command, R/W = 1

15.4.4 Random Read Command

The Random Read command starts with a Control Byte (with R/W bit set to “0”, indicating a write command) and Word Address

to set the internal byte address, followed by a Start bit, and then the Control Byte for the read (exactly the same as the Byte Write

command). The Start bit in the middle of the command will halt the decoding of a Write command, but will set the internal address

counter in preparation for the second half of the command. After the Start bit, the Bus Master issues a second control byte with

the R/W bit set to “1”, after which the SLG46855-A issues an Acknowledge bit, followed by the requested eight data bits.

Acknowledge

Stop

bit

Start

bit

Bus Activity

Data (n)

Control Byte

Word Address (n)

Control Byte

A

10

A

9

A

8

A

10

A

8

A

9

S

ACK

X

R ACK

P

SDA LINE

S

X

W

ACK

Control

Code

Block

Address

Control

Code

Block

Address

No ACK

bit

Not used, set to

0

Write bit

Read bit

Figure 104: Random Read Command

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15.4.5 Sequential Read Command

The Sequential Read command is initiated in the same way as a Random Read command, except that once the SLG46855-A

transmits the first data byte, the Bus Master issues an Acknowledge bit as opposed to a Stop condition in a random read. The

Bus Master can continue reading sequential bytes of data, and will terminate the command with a Stop condition.

Acknowledge

Start

bit

Bus Activity

Data (n + 2)

Data (n + x)

Control Byte

Data (n)

Data (n + 1)

A

10

A

9

A

8

ACK

P

SDA LINE

S

X

X X X

R

ACK

Control

Code

Block

Address

Stop

bit

No ACK

bit

Read bit

Figure 105: Sequential Read Command

15.4.6 I²C Serial Reset Command

If I²C serial communication is established with the device, it is possible to reset the device to initial power up conditions, including

configuration of all macrocells, and all connections provided by the Connection Matrix. This is implemented by setting

register [1960] I²C reset bit to “1”, which causes the device to re-enable the Power-On Reset (POR) sequence, including the

reload of all register data from NVM. During the POR sequence, the outputs of the device will be in tri-state. After the reset has

taken place, the contents of register [1960] will be set to “0” automatically. The Figure 106 illustrates the sequence of events for

this reset function.

Acknowledge

bit

Acknowledge

bit

Start

bit

Acknowledge

bit

Bus Activity

Control Byte

Word Address

Data

A

10

A

9

A

8

A

7

A

0

D

7

D

0

S

X

W

ACK

SDA LINE

P

Internal Reset bit

Control

Code

Block

Address

Stop

bit

Not used, se

t to 0

Write bit

by I2C Stop Signal

Reset-bit register output

DFF output gated by stop signal

Internal POR for core only

Figure 106: Reset Command Timing

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15.5 I²C SERIAL COMMAND REGISTER MAP

There are seven read/write protect modes for the design sequence from being corrupted or copied. See Table 55 for details.

Table 56: Read/Write Protection Options

Protection Modes Configuration

Partly

Lock

Partly

Lock

Read/

Write

Data

Output

From

Lock

Read2/

Write

Lock

Read

Lock

Write

Register

Address

Configurations

Unlocked

(Mode 0) (Mode1) (Mode2) (Mode3) (Mode4) (Mode5) (Mode 6)

I²C Byte Write Bit

Masking

R/W

W

R

-

Memory

F6

(section 15.6.3)

I²C Serial Reset

Command

(section 15.4.6)

R/W

W

R

-

Memory

Macrocell

F5,b'0

F5,b'1

4C

Outputs Latching

During I²C Write

Connection Matrix

Virtual Inputs

(section 6.3)

ConfigurationBits for

All Macrocells

(IO Pins, ACMPs,

Combination

Function Macrocells,

etc.)

R/W

W

-

W

R

-

Memory

Macrocells Inputs

Configuration

(Connection Matrix

Outputs, section 6.2)

0~47

Protection Mode

Enable

R

Memory

F5,b'3

Protection Mode

Selection

R/W

F5,b'7~5

Macrocells Output

Values (Connection

MatrixInputs,section

6.1)

48~4B;

4D~4F

R

-

R

-

Macrocell

Counter Current

Value

A5,A6

(for 16-bit CNT)

Counter Current

Value

(for 8-bit CNT)

I²C Control Code

(section 15.2)

R

-

R

-

Macrocell

Memory

A7,A8

R

FD,b'3~0

Pin Slave Address

Select

I²C Disable/Enable

R

Memory

FD,b'7~4

FE,b'0

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R/W

W

R

Allow Read and Write Data

Allow Write Data Only

Allow Read Data Only

-

The Data is protected for Read and Write

It is possible to read some data from macrocells, such as counter current value, connection matrix, and connection matrix virtual

inputs. The I²C write will not have any impact on data in case data comes from macrocell output, except Connection Matrix Virtual

Inputs. The silicon identification service bits allows identifying silicon family, its revision, and others.

See Section 17 for detailed information on all registers.

15.6 I²C ADDITIONAL OPTIONS

When Output latching during I²C write, register [1961] = 1 allows all PINs output value to be latched until I²C write is done. It will

protect the output change due to configuration process during I²C write in case multiple register bytes are changed. Inputs and

internal macrocells retain their status during I²C write.

If the user sets GPIO0 and GPIO1 function to a selection other than SDA and SCL, all access via I²C will be disabled.

Note: Any write commands that come to the device via I²C that are not blocked, based on the protection bits, will change the

contents of the RAM register bits that mirror the NVM bits. These write commands will not change the NVM bits themselves, and

a POR event will restore the register bits to original programmed contents of the NVM.

See Section 17 for detailed information on all registers.

15.6.1 Reading Counter Data via I²C

The current count value in three counters in the device can be read via I²C. The counters that have this additional functionality

are 16-bit CNT0, and 8-bit counters CNT6 and CNT7.

15.6.2 I²C Expander

In addition to the eight Connection Matrix Virtual Inputs, the SLG46855-A chip has four pins which can be used as an I²C

Expander. These four pins are GPO0, GPIO6, GPIO7, and GPIO8.

Each of these pins can be used as an I²C Expander output or used as a normal pin. Also, each of these four expander outputs

have initial state settings which are specified in registers [1959:1952].

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15.6.3 I²C Byte Write Bit Masking

The I²C macrocell inside SLG46855-A supports masking of individual bits within a byte that is written to the RAM memory space.

This function is supported across the entire RAM memory space. To implement this function, the user performs a Byte Write

Command (see Section 15.4.1 for details) on the I²C Byte Write Mask Register (address 0F6H) with the desired bit mask pattern.

This sets a bit mask pattern for the target memory location that will take effect on the next Byte Write Command to this register

byte. Any bit in the mask that is set to “1” in the I²C Byte Write Mask Register will mask the effect of changing that particular bit

in the target register, during the next Byte Write Command. The contents of the I²C Byte Write Mask Register are reset (set to

00h) after valid Byte Write Command. If the next command received by the device is not a Byte Write Command, the effect of the

bit masking function will be aborted, and the I²C Byte Write Mask Register will be reset with no effect. Figure 107 shows an

example of this function.

User Actions



Byte Write Command, Address = F6h, Data = 11110000b [sets mask bits]

Byte Write Command, Address = 74h, Data = 10101010b [writes data with mask]

Memory Address 74h (original contents)

Mask to choose bit from new

write command

1

0

1

0

Mask to choose bit from

original register contents

Memory Address 74h (new data in write command)

0

1

0

1

0

1

Bit from new write command

Memory Address F6h (mask register)

1

0

Bit from original register

contents

Memory Address 74h (new contents after write command)

1

0

1

0

1

0

Figure 107: Example of I²C Byte Write Bit Masking

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16 Analog Temperature Sensor

The SLG46855-A has an Analog Temperature sensor (TS) with an output voltage linearly-proportional to the Centigrade tempera-

ture. The TS cell shares buffer with Vref 0, so it is impossible to use both cells simultaneously, its output can be connected directly

to the GPIO8 or to the ACPM3_L positive input. Using buffer causes low-output impedance, linear output, and makes interfacing

to readout or control circuitry especially easy. The TS is rated to operate over a -40 °C to 105 °C temperature range. The error in

the whole temperature range does not exceed ±1.5 %. For more detail refer to section 3.11.

The equation below calculates the typical analog voltage passed from the TS to the ACMPs' IN+ source input for V_DD= 2.3 V to

5.5 V. It is important to note that there will be a chip to chip variation of about ±2 °C.

V_TS1= -2.3 x T + 906.2

V_TS2= -2.8 x T + 1094.3

where:

V

_TS1(mV) - TS Output Voltage, range 1

_TS2(mV) - TS Output Voltage, range 2

T (°C) - Temperature

Temperature hysteresis can be setup by enabling the GreenPAK's internal ACMP hysteresis.

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register [675]

TS

register [674]

TS_ON

0

TS_En

From Connection Matrix Output [9]

1

V_DD

register [679]

register [678]

registers [679:678] force to “11” when TS is ON

OUT

11

10

01

00

+

-

Vref0

GPIO8

registers [851:850]=11

register [693] =1

ACMP3_L in+

Output Range Control

register [676]

ACMP1H Vref

ACMP0H Vref

none

0

1

Enable Temp. Sensor

register [674]=1

Closed

Figure 108: Analog Temperature Sensor Structure Diagram

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1.25

1.2

Range 2

Range 1

1.15

1.1

1.05

1

0.95

0.9

0.85

0.8

0.75

0.7

0.65

T (°C)

Figure 109: TS Output vs. Temperature, V_DD= 2.3 V to 5.5 V

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17 Register Definitions

17.1 REGISTER MAP

Table 57: Register Map

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

Matrix Output

0

1

2

OUT0:

IN0 of LUT2_0 or Clock Input of DFF0

3

4

0

5

6

LUT2_0 & DFF0

7

8

OUT1

IN1 of LUT2_0 or Data Input of DFF0

9

10

11

12

1

13

14

15

16

17

18

OUT2:

IN0 of LUT2_1 or Clock Input of DFF1

LUT2_1 & DFF1

19

20

2

OUT3:

IN1 of LUT2_1 or Data Input of DFF1

21

22

23

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Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

Byte

OUT4:

IN0 of LUT2_2 or Clock Input of DFF2

3

LUT2_2 & DFF2

OUT5:

IN1 of LUT2_2 or Data Input of DFF2

4

5

6

7

8

OUT6:

IN0 of LUT2_3 or Clock Input of PGen

LUT2_3 & PGen

OUT7:

IN1 of LUT2_3 or nRST of PGen

OUT8:

IN0 of LUT3_0 or CLK Input of DFF3

OUT9:

LUT3_0 & DFF3

IN1 of LUT3_0 or Data of DFF3

OUT10:

IN2 of LUT3_0 or nRST (nSET) of DFF3

OUT11:

LUT3_1 & DFF4

IN0 of LUT3_1 or CLK Input of DFF4

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Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

72

Byte

73

74

OUT12:

IN1 of LUT3_1 or Data of DFF4

75

76

9

77

78

LUT3_1 & DFF4

79

80

OUT13:

IN2 of LUT3_1 or nRST (nSET) of DFF4

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

A

B

C

D

E

OUT14:

IN0 of LUT3_2 or CLK Input of DFF5

OUT15:

IN1 of LUT3_2 or Data of DFF5

LUT3_2 & DFF5

OUT16:

IN2 of LUT3_2 or nRST (nSET) of DFF5

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

OUT17:

IN0 of LUT3_3 or CLK Input of DFF6

OUT18:

IN1 of LUT3_3 or Data of DFF6

LUT3_3 & DFF6

OUT19:

IN2 of LUT3_3 or nRST (nSET) of DFF6

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Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

OUT20:

IN0 of LUT3_4 or CLK Input of DFF7

F

OUT21:

IN1 of LUT3_4 or Data of DFF7

LUT3_4 & DFF7

10

11

12

13

14

OUT22:

IN2 of LUT3_4 or nRST (nSET) of DFF7

OUT23:

IN0 of LUT3_5 or CLK Input of DFF8

OUT24:

IN1 of LUT3_5 or Data of DFF8

LUT3_5 & DFF8

OUT25:

IN2 of LUT3_5 or nRST (nSET) of DFF8

OUT26:

IN0 of LUT3_6 or CLK Input of DFF9

LUT3_6 & DFF9

OUT27:

IN1 of LUT3_6 or Data of DFF9

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Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

OUT28:

LUT3_6 & DFF9

IN2 of LUT3_6 or nRST (nSET) of DFF9

15

OUT29:

IN0 of LUT3_7 or CLK Input of DFF10

16

17

18

19

1A

OUT30:

LUT3_7 & DFF10

IN1 of LUT3_7 or Data of DFF10

OUT31:

IN2 of LUT3_7 or nRST (nSET) of DFF10

OUT32:

IN0 of LUT3_8 or CLK Input of DFF11

OUT33:

LUT3_8 & DFF11

IN1 of LUT3_8 or Data of DFF11

OUT34:

IN2 of LUT3_8 or nRST (nSET) of DFF11

OUT35:

Multi_function4

IN0 of LUT3_12 or CLK Input of DFF16

Delay4 Input (or Counter4 nRST Input)

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Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

251

252

253

254

255

256

257

258

259

260

261

262

263

OUT36:

IN1 of LUT3_12 or nRST (nSET) of DFF16

Delay4 Input (or Counter4 nRST Input)

1B

Multi_function4

OUT37:

IN2 of LUT3_12 or Data of DFF16

Delay4 Input (or Counter4 nRST Input)

1C

1D

1E

1F

20

OUT38:

IN0 of LUT3_13 or CLK Input of DFF17

Delay5 Input (or Counter5 nRST Input)

OUT39:

Multi_function5

IN1 of LUT3_13 or nRST (nSET) of DFF17

Delay5 Input (or Counter5 nRST Input)

OUT40:

IN2 of LUT3_13 or Data of DFF17

Delay5 Input (or Counter5 nRST Input)

OUT41:

IN0 of LUT3_14 or CLK Input of DFF18

Delay6 Input (or Counter6 nRST Input)

OUT42:

Multi_function6

IN1 of LUT3_14 or nRST (nSET) of DFF18

Delay6 Input (or Counter6 nRST Input)

OUT43:

IN2 of LUT3_14 or Data of DFF18

Delay6 Input (or Counter6 nRST Input)

Datasheet

17-Jun-2021

Revision 3.0

138 of 199

CFR0011-120-00

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

264

265

266

267

268

269

270

271

272

273

274

275

276

277

278

279

280

281

282

283

284

285

286

287

288

289

290

291

292

293

294

295

296

297

298

299

300

301

302

303

304

305

306

307

308

309

310

311

OUT44:

IN0 of LUT3_15 or CLK Input of DFF19

Delay7 Input (or Counter7 nRST Input)

21

OUT45:

Multi_function7

IN1 of LUT3_15 or nRST (nSET) of DFF19

Delay7 Input (or Counter7 nRST Input)

22

23

24

25

26

OUT46:

IN2 of LUT3_15 or Data of DFF19

Delay7 Input (or Counter7 nRST Input)

OUT47:

IN0 of LUT3_16 or Input of Pipe Delay or UP signal of RIPP

CNT

OUT48:

LUT3_16 & Pipe Delay (RIPP CNT)

IN1 of LUT3_16 or nRST of Pipe Delay or nSET of RIPP CNT

OUT49:

IN2 of LUT3_16 or Clock of Pipe

Delay_RIPP CNT

OUT50:

IN0 of LUT4_0 or CLK Input of DFF12

LUT4_DFF12

OUT51:

IN1 of LUT4_0 or Data of DFF12

Datasheet

17-Jun-2021

Revision 3.0

139 of 199

CFR0011-120-00

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

312

313

314

315

316

317

318

319

320

321

322

323

324

325

326

327

328

329

330

331

332

333

334

335

336

337

338

339

340

341

342

343

344

345

346

347

348

349

350

351

352

353

354

355

356

357

358

359

OUT52:

IN2 of LUT4_0 or nRST (nSET) of DFF12

27

LUT4_DFF12

OUT53:

IN3 of LUT4_0

28

29

2A

2B

2C

Programmable delay

Filter/Edge Detect

GPIO0

OUT54: Programmable delay/edge detect input

OUT55: Filter/Edge detect input

OUT56: GPIO0 DOUT

GPIO1

OUT57: GPIO1 DOUT

OUT58: GPIO2 DOUT

GPIO2

OUT59: GPIO2 DOUT OE

Datasheet

17-Jun-2021

Revision 3.0

140 of 199

CFR0011-120-00

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

360

361

362

363

364

365

366

367

368

369

370

371

372

373

374

375

376

377

378

379

380

381

382

383

384

385

386

387

388

389

390

391

392

393

394

395

396

397

398

399

400

401

402

403

404

405

406

407

OUT60: GPIO3 DOUT and Input of Power Switch ON0

2D

GPIO3 DOUT and Input of Power Switch ON0

OUT61: GPIO3 DOUT OE

OUT62: GPO0 DOUT and Input of Power Switch ON1

OUT63: GPIO4 DOUT

2E

2F

30

31

32

GPO0 and Input of Power Switch ON1

GPIO4

OUT64: GPIO4 DOUT OE

OUT65: GPIO5 DOUT

GPIO5

OUT66: GPIO5 DOUT OE

OUT67: GPIO6 DOUT

GPIO6

Datasheet

17-Jun-2021

Revision 3.0

141 of 199

CFR0011-120-00

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

408

409

410

411

412

413

414

415

416

417

418

419

420

421

422

423

424

425

426

427

428

429

430

431

432

433

434

435

436

437

438

439

440

441

442

443

444

445

446

447

448

449

450

451

452

453

454

455

GPIO6

OUT68: GPIO6 DOUT OE

33

OUT69: GPIO7 DOUT

OUT70: GPIO7 DOUT OE

OUT71: GPIO8 DOUT

OUT72: GPIO8 DOUT OE

OUT73: GPIO9 DOUT

OUT74: GPIO9 DOUT OE

34

35

36

37

38

GPIO7

GPIO8

GPIO9

OUT75:

PWR UP of ACMP0H

ACMP0H

Datasheet

17-Jun-2021

Revision 3.0

142 of 199

CFR0011-120-00

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

456

457

458

459

460

461

462

463

464

465

466

467

468

469

470

471

472

473

474

475

476

477

478

479

480

481

482

483

484

485

486

487

488

489

490

491

492

493

494

495

496

497

498

499

500

501

502

503

OUT76:

ACMP1H

PWR UP of ACMP1H

39

OUT77:

PWR UP of ACMP2L

ACMP2L

ACMP3L

Temp Sensor

OSC0

3A

3B

3C

3D

3E

OUT78:

PWR UP of ACMP3L

OUT79:

Temp sensor, Vref Out_0, Vref Out_1 Power Up

OUT80: OSC0 ENABLE

OUT81: OSC1 ENABLE

OUT82: OSC2 ENABLE

OSC1

OSC2

OUT83:

Multi_function0

IN0 of LUT4_1 or CLK Input of DFF20

Delay0 Input (or Counter0 nRST Input)

Datasheet

17-Jun-2021

Revision 3.0

143 of 199

CFR0011-120-00

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

504

505

506

507

508

509

510

511

512

513

514

515

516

517

518

519

520

521

522

523

524

525

526

527

528

529

530

531

532

533

534

535

536

537

538

539

540

541

542

543

544

545

546

547

548

549

550

551

OUT84:

IN1 of LUT4_1 or nRST of DFF20

Delay0 Input (or Counter0 nRST Input)

Delay/Counter0 External CLK source

3F

OUT85:

IN2 of LUT4_1 or nSET of DFF20

Delay0 Input (or Counter0 nRST Input)

Delay/Counter0 External CLK source

KEEP Input of FSM0

Multi_function0

40

41

42

43

44

OUT86:

IN3 of LUT4_1 or Data of DFF20

Delay0 Input (or Counter0 nRST Input)

UP Input of FSM0

OUT87:

IN0 of LUT3_9 or CLK Input of DFF13

Delay1 Input (or Counter1 nRST Input)

OUT88:

Multi_function1

IN1 of LUT3_9 or nRST (nSET) of DFF13

Delay1 Input (or Counter1 nRST Input)

OUT89:

IN2 of LUT3_9 or Data of DFF13

Delay1 Input (or Counter1 nRST Input)

OUT90:

IN0 of LUT3_10 or CLK Input of DFF14

Delay2 Input (or Counter2 nRST Input)

Multi_function2

OUT91:

IN1 of LUT3_10 or nRST (nSET) of DFF14

Delay2 Input (or Counter2 nRST Input)

Datasheet

17-Jun-2021

Revision 3.0

144 of 199

CFR0011-120-00

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

552

553

554

555

556

557

558

559

560

561

562

563

564

565

566

567

568

569

570

571

572

573

574

575

576

577

578

579

580

581

582

583

584

585

586

587

588

589

590

591

592

593

594

595

596

597

598

599

OUT92:

Multi_function2

IN2 of LUT3_10 or Data of DFF14

Delay2 Input (or Counter2 nRST Input)

45

OUT93:

IN0 of LUT3_11 or CLK Input of DFF15

Delay3 Input (or Counter3 nRST Input)

46

47

48

49

4A

OUT94:

Multi_function3

IN1 of LUT3_11 or nRST (nSET) of DFF15

Delay3 Input (or Counter3 nRST Input)

OUT95:

IN2 of LUT3_11 or Data of DFF15

Delay3 Input (or Counter3 nRST Input)

Matrix Input 0

Matrix Input 1

Matrix Input 2

Matrix Input 3

Matrix Input 4

Matrix Input 5

Matrix Input 6

Matrix Input 7

Matrix Input 8

Matrix Input 9

Matrix Input 10

Matrix Input 11

Matrix Input 12

Matrix Input 13

Matrix Input 14

Matrix Input 15

Matrix Input 16

Matrix Input 17

Matrix Input 18

Matrix Input 19

Matrix Input 20

Matrix Input 21

Matrix Input 22

Matrix Input 23

GND

LUT2_0/DFF0 output

LUT2_1/DFF1 output

LUT2_2/DFF2 output

LUT2_3/PGen output

LUT3_0/DFF3 output

LUT3_1/DFF4 output

LUT3_2/DFF5 output

LUT3_3/DFF6 output

LUT3_4/DFF7 output

LUT3_5/DFF8 output

LUT3_6/DFF9 output

LUT3_7/DFF10 output

LUT3_8/DFF11 output

CNT0 output

MF0_LUT4/DFF_OUT

CNT1 output

MF1_LUT3/DFF_OUT

CNT2 output

MF2_LUT3/DFF_OUT

CNT3 output

MF3_LUT3/DFF_OUT

CNT4 output

MF4_LUT3/DFF_OUT

Datasheet

17-Jun-2021

Revision 3.0

145 of 199

CFR0011-120-00

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

600

601

602

603

604

605

606

607

608

609

610

611

612

613

614

615

616

617

618

619

620

621

622

623

624

625

626

627

628

629

630

631

632

633

634

635

636

637

638

639

Matrix Input 24

Matrix Input 25

Matrix Input 26

Matrix Input 27

Matrix Input 28

Matrix Input 29

Matrix Input 30

Matrix Input 31

Matrix Input 32

Matrix Input 33

Matrix Input 34

Matrix Input 35

Matrix Input 36

Matrix Input 37

Matrix Input 38

Matrix Input 39

Matrix Input 40

Matrix Input 41

Matrix Input 42

Matrix Input 43

Matrix Input 44

Matrix Input 45

Matrix Input 46

Matrix Input 47

Matrix Input 48

Matrix Input 49

Matrix Input 50

Matrix Input 51

Matrix Input 52

Matrix Input 53

Matrix Input 54

Matrix Input 55

Matrix Input 56

Matrix Input 57

Matrix Input 58

Matrix Input 59

Matrix Input 60

Matrix Input 61

Matrix Input 62

Matrix Input 63

CNT5 output

MF5_LUT3/DFF_OUT

CNT6 output

MF6_LUT3/DFF_OUT

CNT7 output

MF7_LUT3/DFF_OUT

LUT3_16/Ripple CNT/Pipe Delay_out0

Ripple CNT/Pipe Delay_out1

GPIO0 digital input or I2C_virtual_0 Input

GPIO1 digital input or I2C_virtual_1 Input

I2C_virtual_2 Input

I2C_virtual_3 Input

I2C_virtual_4 Input

I2C_virtual_5 Input

I2C_virtual_6 Input

I2C_virtual_7 Input

Ripple CNT_out2

LUT4_0/DFF12 output

Programmable Delay Edge Detect Output

Edge Detect Filter Output

GPI0 Digital Input

GPIO2 Digital Input

Power Switch ON0, GPIO3 Digital Input

GPIO4 Digital Input

GPIO5 Digital Input

GPIO6 Digital Input

GPIO7 Digital Input

GPIO8 Digital Input

GPIO9 Digital Input

OSC0 output 0

4B

4C

4D

4E

4F

OSC1 output 0

OSC2 output

ACMP0H Output (normal speed)

ACMP1H Output (normal speed)

ACMP2L Output (low speed)

ACMP3L output (low speed)

OSC0 output 1

OSC1 output 1

Matrix nRST

V_DD

Datasheet

17-Jun-2021

Revision 3.0

146 of 199

CFR0011-120-00

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

0: CHOP enable

1: chopper off

640

BG CHOP OFF

641

642

BG Chopper clock test enable

Bandgap internal voltage output to IO enable 1: enable

1: enable

0: always on

643

644

645

646

647

648

649

Bandgap power-down control

1: power-down if no function enable it (ACMP, Vref, TS)

0: from GPIO2

1: from GPO0

0: from GPIO2

1: from GPO0

0: from GPIO2

1: from GPO0

1: enable

0: disable

50

ACMP1H external Vref0 source selection

ACMP2L external Vref1 source selection

ACMP3L external Vref1 source selection

ACMP3L wake sleep enable

1: on

0: off

VrefO0 register Power-On/Off

0: come from register [648]

1: come from matrix out92

VrefO0 power-down selection

1: on

0: off

00: 0 mV

650

651

VrefO1 register Power-On/Off

51

01: 32 mV

10: 64 mV

11: 192 mV

ACMP0H hysteresis

652

653

654

655

656

Reserved

ACMP0_H input buffer enable

Reserved

1: enable

ACMP0H input tie to V_DDenable

ACMP1_H positive input come from AC-

MP0_H's input mux output enable; 1:enable

657

658

659

Reserved

00: 0 mV

01: 32 mV

10: 64 mV

11: 192 mV

52

ACMP1H hysteresis

660

661

662

ACMP1H input buffer enable

Reserved

1: enable

ACMP2L positive input come from ACMP0H's

input mux output enable

ACMP2L positive input come from ACMP1H's

input mux output enable

663

1: enable

664

665

00: 0 mV

01: 32 mV

10: 64 mV

11: 192 mV

ACMP2L hysteresis

666

667

668

669

Reserved

53

00: 0 mV

01: 32 mV

10: 64 mV

11: 192 mV

ACMP3_L hysteresis

Reserved

670

671

Datasheet

17-Jun-2021

Revision 3.0

147 of 199

CFR0011-120-00

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

672

Reserved

ACMP3_L positive input come from ACMP2L's

input mux output enable

673

674

675

676

1: enable

0: Power-down

1: Power-On

0: come from register

1: come from Matrix

0: range 1 (0.62V ~ 0.99V (TYP))

1: range 2 (0.75V ~ 1.2V (TYP))

0: disable

1: enable

Temp sensor register pdb control

Temp sensor register pdb select

Temp sensor range select

Vref0 output OP

54

677

678

00: None

01: ACMP0H Vref

10: ACMP1H Vref

11: temp sensor

Vref0 input selection

679

0: disable

1: enable

680

Vref1 output OP

681

682

00: None

01: ACMP2L Vref

10: ACMP3L Vref

Vref1 input selection

55

683

684

685

686

687

688

0000: 1.194, 0001:1.195, 0011:1.196, 0100:1.197,

0101:1.198, 0110:1.199 0111:1.2, 1000:1.201, 1001:1.202,

1010:1.203, 1011:1.204, 1100:1.205, 1101:1.206,

1110:1.207, 1111:1.208

VBG fine tune selection

ACMP0H Wake/Sleep enable

ACMP1H Wake/Sleep enable

0: short time

1: normal w/s

689

ACMP Wake/Sleep time selection

690

691

692

ACMP0H 100 uA current source enable

Reserve for ACMP

Reserved

56

ACMP3L input come from Temp sensor output

enable

693

694

0: come from register [650]

1: come from matrix OUT92

0: disable

1: enable

VrefO1 power-down selection

ACMP2L wake sleep enable

695

696

ACMP gain divider select:

00: 1x

ACMP0H Gain divider

01:0.5x

697

10:0.33x

11:0.25x

698

699

700

701

702

703

57

ACMP Vref select:

000000: 32mV ~

ACMP0H Vref0

111110: 2.016V/step = 32 mV

111111: External Vref

Datasheet

17-Jun-2021

Revision 3.0

148 of 199

CFR0011-120-00

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

704

ACMP gain divider select:

00: 1x

ACMP1H Gain divider

01:0.5x

705

10:0.33x

11:0.25x

706

707

708

709

710

711

712

58

ACMP Vref select:

000000: 32 mV ~ 1

ACMP1H Vref0

11110: 2.016V/step = 32mV

111111: External Vref

ACMP gain divider select:

00: 1x

ACMP2L Gain divider

ACMP2L Vref1

01:0.5x

713

10:0.33x

11:0.25x

714

715

716

717

718

719

720

59

ACMP Vref select:

000000: 32 mV ~

111110: 2.016V/step = 32mV

111111: External Vref

ACMP gain divider select:

00: 1x

ACMP3L Gain divider

ACMP3L Vref1

01:0.5x

721

10:0.33x

11:0.25x

722

723

724

725

726

727

5A

ACMP Vref select:

000000: 32 mV ~

111110: 2.016V/step = 32mV

111112: External Vref

OSC1

when matrix output enable/pd control signal = 0:

0: auto on by delay cells

728

729

OSC1 turn on by register

1: always on

0: matrix down

1: matrix on

0: internal OSC1

1: external clock from GPIO2

00: div 1

01: div 2

10: div 4

11: div 8

matrix power-down or on select

external clock source enable

730

731

5B

post divider ratio control

732

733

734

735

000: /1, 001:/2 , 010:/4, 011: /3, 100: /8, 101: /12, 110: /24,

111: /64

matrix divider ratio control

matrix out enable

0: disable

1: enable

736

737

738

739

Reserved

5C

Datasheet

17-Jun-2021

Revision 3.0

149 of 199

CFR0011-120-00

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

OSC2

when matrix output enable/pd control signal = 0:

0: auto on by delay cells

1: always on

740

OSC2 turn on by register

0: matrix down

1: matrix on

0: internal OSC2

1: external clock from GPIO8

0: disable

1: enable

00: div 1

01: div 2

10: div 4

11: div 8

741

742

matrix power-down or on select

external clock source enable

matrix out enable

5C

743

744

5D

post divider ratio control

745

746

747

748

000: /1, 001:/2 , 010:/4, 011: /3, 100: /8, 101: /12, 110: /24,

111: /64

matrix divider ratio control

startup delay with 100 ns

0: enable

1: disable

749

OSC0

when matrix output enable/pd control signal = 0:

0: auto on by delay cells

1: always on

750

OSC0 turn on by register

5D

0: matrix down

1: matrix on

0: internal OSC0

1: external clock from GPIO

0: disable

1: enable

00: div 1

01: div 2

10: div 4

11: div 8

751

752

matrix power-down or on select

external clock source enable

matrix out enable

753

754

post divider ratio control

matrix divider ratio control

755

5E

756

757

758

000: /1, 001:/2 , 010:/4, 011: /3, 100: /8, 101: /12, 110: /24,

111: /64

enable OSC0 output gating by wake_sleep sig-

nal

0: no gating

759

(note: the wake_sleep clock is separated path, 1: enable

so it is not gated)

760

761

762

000: /1, 001:/2 , 010:/4, 011: /3, 100: /8, 101: /12, 110: /24,

matrix divider ratio control

2nd output to matrix enable

matrix divider ratio control

2nd output to matrix enable

111: /64

0: disable

1: enable

763

5F

764

765

766

000: /1, 001:/2 , 010:/4, 011: /3, 100: /8, 101: /12, 110: /24,

111: /64

0: disable

1: enable

767

Datasheet

17-Jun-2021

Revision 3.0

150 of 199

CFR0011-120-00

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

768

769

770

771

772

773

774

775

776

777

Reserved

60

61

0: disable

1: enable

778

IO fast Pull-up/down enable

GPI0

779

780

781

782

00: digital without Schmitt Trigger

01: digital with Schmitt Trigger

10: low voltage digital in

11: analog IO

00: floating

01: 10K

10: 100K

11: 1M

input mode configuration

61

Pull-up/down resistance selection

Pull-up/down selection

0: Pull-down

1: Pull-up

783

GPIO0

784

785

00: digital in without Schmitt Trigger

01: digital in with Schmitt Trigger

(when register [2032] = 1)

10: low voltage digital in

11: Reserved

input mode configuration

786

787

00: floating

01: 10K

10: 100K

11: 1M

Pull-up/down resistance selection

62

0: Pull-down

1: Pull-up

0: I2C fast mode+ (3.2x drivability)

1: I2C standard/fast mode

0: digital input

1: digital output (3.2x Open-Drain NMOS)

788

789

790

Pull-up/down selection

I²C mode selection

I/O selection

GPIO1

62

791

792

00: digital without Schmitt Trigger

01: digital in with Schmitt Trigger

(when register [2032] = 1)

10: low voltage digital in

11: Reserved

input mode configuration

793

794

00: floating

01: 10K

Pull-up/down resistance selection

Pull-up/down selection

10: 100K

11: 1M

63

0: Pull-down

1: Pull-up

795

0: digital input

1: digital output (3.2x Open-Drain NMOS)

796

797

I/O selection

Reserved

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

GPIO2

798

799

800

801

802

803

00: digital without Schmitt Trigger

01: digital with Schmitt Trigger

10: low voltage digital in

11: analog IO

00: Push-Pull 1x

01: Push-Pull 2x

10: 1x Open-Drain

11: 2x Open-Drain

00: floating

01: 10K

10: 100K

11: 1M

63

input mode configuration

output mode configuration

64

Pull-up/down resistance selection

Pull-up/down selection

0: Pull-down

1: Pull-up

804

GPIO3

805

806

807

808

809

810

00: digital without Schmitt Trigger

01: digital with Schmitt Trigger

10: low voltage digital in

11: analog IO

00: Push-Pull 1x

01: Push-Pull 2x

10: 1x Open-Drain

11: 2x Open-Drain

00: floating

01: 10K

10: 100K

11: 1M

input mode configuration

output mode configuration

64

65

Pull-up/down resistance selection

Pull-up/down selection

65

GPO0

65

0: Pull-down

1: Pull-up

811

812

813

814

Reserved

00: Push-Pull 1x

01: Push-Pull 2x

10: 1x Open-Drain

11: 2x Open-Drain

00: floating

01: 10K

10: 100K

11: 1M

output mode configuration

815

816

817

Pull-up/down resistance selection

0: Pull-down

1: Pull-up

0: output disable (input mode)

1: output enable

0: disable

1: enable

818

819

820

Pull-up/down selection

output enable

4x drive

66

GPIO4

Datasheet

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

821

00: digital without Schmitt Trigger

01: digital with Schmitt Trigger

10: low voltage digital in

11: analog IO

00: Push-Pull 1x

01: Push-Pull 2x

10: 1x Open-Drain

11: 2x Open-Drain

00: floating

01: 10K

10: 100K

11: 1M

input mode configuration

output mode configuration

Pull-up/down resistance selection

66

822

823

824

825

826

67

0: Pull-down

1: Pull-up

0: disable

1: enable

827

828

Pull-up/down selection

4x drive

GPIO5

829

830

831

832

833

834

00: digital without Schmitt Trigger

01: digital with Schmitt Trigger

10: low voltage digital in

11: analog IO

00: Push-Pull 1x

01: Push-Pull 2x

10: 1x Open-Drain

11: 2x Open-Drain

00: floating

01: 10K

10: 100K

11: 1M

input mode configuration

output mode configuration

67

68

Pull-up/down resistance selection

Pull-up/down selection

0: Pull-down

1: Pull-up

835

GPIO6

836

837

838

839

840

841

00: digital without Schmitt Trigger

01: digital with Schmitt Trigger

10: low voltage digital in

11: analog IO

00: Push-Pull 1x

01: Push-Pull 2x

10: 1x Open-Drain

11: 2x Open-Drain

00: floating

01: 10K

10: 100K

11: 1M

input mode configuration

output mode configuration

68

Pull-up/down resistance selection

Pull-up/down selection

69

0: Pull-down

1: Pull-up

842

GPIO7

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

843

00: digital without Schmitt Trigger

01: digital with Schmitt Trigger

10: low voltage digital in

11: analog IO

00: Push-Pull 1x

01: Push-Pull 2x

10: 1x Open-Drain

11: 2x Open-Drain

00: floating

01: 10K

10: 100K

11: 1M

input mode configuration

output mode configuration

844

845

846

847

848

69

Pull-up/down resistance selection

Pull-up/down selection

6A

0: Pull-down

1: Pull-up

849

GPIO8

850

851

852

853

854

855

00: digital without Schmitt Trigger

01: digital with Schmitt Trigger

10: low voltage digital in

11: analog IO

00: Push-Pull 1x

01: Push-Pull 2x

10: 1x Open-Drain

11: 2x Open-Drain

00: floating

01: 10K

10: 100K

11: 1M

input mode configuration

output mode configuration

6A

Pull-up/down resistance selection

Pull-up/down selection

0: Pull-down

1: Pull-up

6B

856

GPIO9

857

858

859

860

861

862

00: digital without Schmitt Trigger

01: digital with Schmitt Trigger

10: low voltage digital in

11: analog IO

00: Push-Pull 1x

01: Push-Pull 2x

10: 1x Open-Drain

11: 2x Open-Drain

00: floating

01: 10K

10: 100K

11: 1M

input mode configuration

output mode configuration

6B

Pull-up/down resistance selection

Pull-up/down selection

0: Pull-down

1: Pull-up

863

864

865

866

867

868

869

870

871

Reserved

6C

Datasheet

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

872

873

874

875

876

877

878

879

880

881

882

883

884

885

886

887

888

889

890

891

892

893

894

895

896

897

898

899

900

901

902

903

904

905

906

907

908

909

910

911

912

913

914

915

916

917

918

919

Reserved

6D

6E

6F

70

71

72

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

920

921

922

923

924

925

926

927

928

929

930

931

932

933

934

935

936

937

938

939

940

941

942

943

944

945

946

947

948

949

950

951

952

953

954

955

956

957

958

959

960

961

962

963

964

965

966

967

Reserved

73

74

75

76

77

78

Datasheet

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

968

969

970

971

972

973

974

975

976

977

978

979

980

981

982

983

984

985

986

987

988

989

990

991

992

993

994

995

996

997

998

999

1000

1001

1002

1003

1004

1005

1006

1007

1008

1009

1010

1011

1012

1013

1014

1015

Reserved

79

7A

7B

7C

7D

7E

Datasheet

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SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1016

1017

1018

1019

1020

1021

1022

1023

Reserved

7F

0000000: Matrix A - In3; Matrix B - In2; Matrix C - In1;

Single 4-bit LUT

Matrix D - In0

(DLY_IN - LOW)

0010000: Matrix A - D; Matrix B - nSET; Matrix C - nRST;

Single DFF w RST and SET

Single CNT/DLY

Matrix D - CLK

(DLY_IN - LOW)

0000001: Matrix A - UP (CNT); Matrix B - KEEP (CNT);

Matrix C - EXT_CLK (CNT); Matrix D - DLY_IN (CNT)

(DLY_OUT connected to LUT/DFF)

0000010: Matrix A - DLY_IN; Matrix B - In2; Matrix C - In1;

Matrix D - In0

CNT/DLY → LUT

CNT/DLY → DFF

CNT/DLY → LUT

CNT/DLY → DFF

(DLY_OUT connected to In3)

0010010:MatrixA- DLY_IN; Matrix B -nSET; Matrix C - nRST;

Matrix D - CLK

(DLY_OUT connected to D)

0100010: Matrix A - DLY_IN; Matrix B - EXT_CLK (CNT);

Matrix C - In1; Matrix D - In0

(DLY_OUT connected to In3; In2 - LOW)

0110010: Matrix A - DLY_IN; Matrix B - EXT_CLK (CNT);

Matrix C - nRST; Matrix D - CLK

(DLY_OUT connected to D; nSET - HIGH)

80 1030:1024

1000010: Matrix A - DLY_IN; Matrix B - In2;

Matrix C - EXT_CLK (CNT);

CNT/DLY → LUT

CNT/DLY → DFF

Matrix D - In0

(DLY_OUT connected to In3; In1 - LOW)

1010010: Matrix A - DLY_IN; Matrix B - nSET;

Matrix C - EXT_CLK (CNT);

Matrix D - CLK

(DLY_OUT connected to D; nRST - HIGH)

0000110: Matrix A - In3; Matrix B - DLY_IN; Matrix C - In1;

Matrix D - In0

CNT/DLY → LUT

CNT/DLY → DFF

(DLY_OUT connected to In2)

0010110: Matrix A - D; Matrix B - DLY_IN; Matrix C - nRST;

Matrix D - CLK

(DLY_OUT connected to nSET)

1000110: Matrix A - In3; Matrix B - DLY_IN;

Matrix C - EXT_CLK (CNT);

CNT/DLY → LUT

Matrix D - In0

(DLY_OUT connected to In2; In1 - LOW)

Datasheet

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1010110: MatrixA- D; Matrix B - DLY_IN; Matrix C - EXT_CLK

(CNT);

Matrix D - CLK

CNT/DLY → DFF

(DLY_OUT connected to nSET; nRST - HIGH)

0001010: Matrix A - In3; Matrix B - In2; Matrix C - DLY_IN;

Matrix D - In0

CNT/DLY → LUT

CNT/DLY → DFF

(DLY_OUT connected to In1)

0011010: Matrix A - D; Matrix B - nSET; Matrix C - DLY_IN;

Matrix D - CLK

(DLY_OUT connected to nRST)

0101010: Matrix A - In3; Matrix B - EXT_CLK (CNT);

Matrix C - DLY_IN;

CNT/DLY → LUT

Matrix D - In0

(DLY_OUT connected to In1; In2 - LOW)

0111010: Matrix A - D; Matrix B - EXT_CLK (CNT);

Matrix C - DLY_IN; Matrix D - CLK

CNT/DLY → DFF

CNT/DLY → LUT

CNT/DLY → DFF

(DLY_OUT connected to nRST; nSET - HIGH)

0001110: Matrix A - In3; Matrix B - In2; Matrix C - In1;

Matrix D - DLY_IN

(DLY_OUT connected to In0)

0011110: Matrix A - D; Matrix B - nSET; Matrix C - nRST;

Matrix D - DLY_IN

(DLY_OUT connected to CLK)

80 1030:1024

0101110: Matrix A - In3; Matrix B - EXT_CLK (CNT);

Matrix C - In1;

CNT/DLY → LUT

CNT/DLY → DFF

CNT/DLY → LUT

Matrix D - DLY_IN

(DLY_OUT connected to In0; In2 - LOW)

0111110: Matrix A - D; Matrix B - EXT_CLK (CNT);

Matrix C - nRST; Matrix D - DLY_IN

(DLY_OUT connected to CLK; nSET - HIGH)

1001110: Matrix A - In3; Matrix B - In2; Matrix C - EXT_CLK

(CNT);

Matrix D - DLY_IN

(DLY_OUT connected to In0; In1 - LOW)

1011110: Matrix A - D; Matrix B - nSET; Matrix C - EXT_CLK

(CNT); Matrix D - DLY_IN

CNT/DLY → DFF

LUT → CNT/DLY

DFF → CNT/DLY

LUT → CNT/DLY

(DLY_OUT connected to CLK; nRST - HIGH)

0000011: Matrix A - In3; Matrix B - In2; Matrix C - In1;

Matrix D - In0

(LUT_OUT connected to DLY_IN)

0010011: Matrix A - D; Matrix B - nSET; Matrix C - nRST;

Matrix D - CLK

(DFF_OUT connected to DLY_IN)

0100011: Matrix A - In3; Matrix B - EXT_CLK (CNT);

Matrix C - In1; Matrix D - In0

(LUT_OUT connected to DLY_IN; In2 - LOW)

Datasheet

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

0110011: Matrix A - D; Matrix B - EXT_CLK (CNT);

Matrix C - nRST; Matrix D - CLK

(DFF_OUT connected to DLY_IN; nSET - HIGH)

DFF → CNT/DLY

1000011: Matrix A - In3; Matrix B - In2; Matrix C - EXT_CLK

(CNT); Matrix D - In0

(LUT_OUT connected to DLY_IN; In1 - LOW)

1030:1024 LUT → CNT/DLY

80

1010011: Matrix A - D; Matrix B - nSET; Matrix C - EXT_CLK

(CNT); Matrix D - CLK

DFF → CNT/DLY

1031

(DFF_OUT connected to DLY_IN; nRST - HIGH)

00: DLY

01: one shot

10: frequency det

11: CNT register [1040] = 0

DLY/CNT0 Mode Selection

1032

1033

1034

00: both edge

01: falling edge

DLY/CNT0 edge Mode Selection

10: rising edge

11: High Level Reset (only in CNT mode)

1035

1036

1037

Clock source sel[3:0]

0000: 25M(OSC2);

0001: 25M/4;

0010: 2M(OSC1);

0011: 2M/8;

0100: 2M/64;

81

0101: 2M/512;

0110: 2K(OSC0);

0111: 2K/8;

DLY/CNT0 Clock Source Select

1000: 2K/64;

1038

1001: 2K/512;

1010: 2K/4096;

1011: 2K/32768;

1100: 2 K/262144;

1101: CNT7_END;

1110: External;

1111: Not used

0: Reset to 0

1: Set to data

0: normal

1: DLY function edge detection

(registers [1032:1031] = 00)

0: bypass

1: after two DFF

0: bypass

1: after two DFF

00: bypass the initial

01: initial 0

10: initial 1

11: initial 1

0: low

1: high

1039

1040

1041

FSM0 SET/RST Selection

CNT0 DLY EDET FUNCTION Selection

UP signal SYNC selection

Keep signal SYNC selection

1042

1043

82

CNT0 initial value selection

1044

1045

Wake sleep power-down state selection

wake sleep mode selection

0: Default Mode

1: Wake Sleep Mode

(registers [1032:1031] = 11)

0: Default Output

1: Inverted Output

1046

1047

CNT0 output pol selection

Datasheet

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

0: bypass

1048

CNT0 CNT mode SYNC selection

Single 3-bit LUT

1: after two DFF

00000: Matrix A - In2; Matrix B - In1;

Matrix C - In0

(DLY_IN - LOW)

10000: Matrix A - D; Matrix B - nSET/nRST; Matrix C - CLK

(DLY_IN - LOW)

00001: Matrix A- DLY_IN (CNT); Matrix B - EXT_CLK (CNT);

Matrix C - NC

(DLY_OUT connected to LUT/DFF)

Single DFF w RST and SET

Single CNT/DLY

00010: Matrix A - DLY_IN; Matrix B - In1; Matrix C - In0

(DLY_OUT connected to In2)

CNT/DLY → LUT

10010: Matrix A - DLY_IN; Matrix B - nSET/nRST;

Matrix C - CLK

(DLY_OUT connected to D)

CNT/DLY → DFF

1053:1049

83

00110: Matrix A - In2; Matrix B - DLY_IN; Matrix C - In0

(DLY_OUT connected to In1)

10110: Matrix A - D; Matrix B - DLY_IN; Matrix C - CLK

(DLY_OUT connected to nSET/nRST)

CNT/DLY → LUT

CNT/DLY → DFF

01010: Matrix A - In2; Matrix B - In1;

Matrix C - DLY_IN

(DLY_OUT connected to In0)

CNT/DLY → LUT

11010: Matrix A- D; Matrix B - nSET/nRST; Matrix C - DLY_IN

(DLY_OUT connected to CLK)

00011: Matrix A - In2; Matrix B - In1; Matrix C - In0

(LUT_OUT connected to DLY_IN)

10011: Matrix A - D; Matrix B - nSET/nRST; Matrix C - CLK

(DFF_OUT connected to DLY_IN)

CNT/DLY → DFF

LUT → CNT/DLY

DFF → CNT/DLY

1054

1055

1056

0000: both edge Delay;

0001: falling edge delay;

0010: rising edge delay:

0011: both edge One Shot;

0100: falling edge One Shot;

0101: rising edge One Shot;

0110: both edge freq detect;

0111: falling edge freq detect;

1000: rising edge freq detect;

1001: both edge detect;

1010: falling edge detect;

1011: rising edge detect;

1100: both edge reset CNT;

1101: falling edge reset CNT;

1110: rising edge reset CNT;

1111: high level reset CNT

CNT1 function and edge mode selection

1057

84

1058

1059

00: bypass the initial

01: initial 0

CNT1 initial value selection

10: initial 1

11: initial 1

Datasheet

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SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1060

1061

1062

Clock source sel[3:0]

0000: 25M(OSC2);

0001: 25M/4;

0010: 2M(OSC1);

0011:2M/8;

0100: 2M/64;

0101: 2M/512;

0110:2K(OSC0);

0111: 2K/8;

84

DLY/CNT1 Clock Source Select

1000:2K/64;

1063

1001: 2K/512;

1010: 2K/4096;

1011:2K/32768;

1100: 2K/262144;

1101: CNT0_END;

1110: External;

1111: Not used

0: Default Output

1: Inverted Output

0: bypass

1: after two DFF

1064

1065

CNT1 output pol selection

CNT1 CNT mode SYNC selection

0: normal

1066

CNT1 DLY EDET FUNCTION Selection

1: DLY function edge detection

(registers[1057:1054]=0000/0001/0010)

00000: Matrix A - In2; Matrix B - In1;

Matrix C - In0

(DLY_IN - LOW)

Single 3-bit LUT

10000: Matrix A - D; Matrix B - nSET/nRST; Matrix C - CLK

(DLY_IN - LOW)

00001: Matrix A- DLY_IN (CNT); Matrix B - EXT_CLK (CNT);

Matrix C - NC

(DLY_OUT connected to LUT/DFF)

Single DFF w RST and SET

Single CNT/DLY

00010: Matrix A - DLY_IN; Matrix B - In1; Matrix C - In0

(DLY_OUT connected to In2)

CNT/DLY → LUT

85

10010: Matrix A - DLY_IN; Matrix B - nSET/nRST;

Matrix C - CLK

(DLY_OUT connected to D)

CNT/DLY → DFF

1071:1067

00110: Matrix A - In2; Matrix B - DLY_IN; Matrix C - In0

(DLY_OUT connected to In1)

10110: Matrix A - D; Matrix B - DLY_IN; Matrix C - CLK

(DLY_OUT connected to nSET/nRST)

CNT/DLY → LUT

CNT/DLY → DFF

01010: Matrix A - In2; Matrix B - In1;

Matrix C - DLY_IN

(DLY_OUT connected to In0)

CNT/DLY → LUT

11010: Matrix A- D; Matrix B - nSET/nRST; Matrix C - DLY_IN

(DLY_OUT connected to CLK)

00011: Matrix A - In2; Matrix B - In1; Matrix C - In0

(LUT_OUT connected to DLY_IN)

10011: Matrix A - D; Matrix B - nSET/nRST; Matrix C - CLK

(DFF_OUT connected to DLY_IN)

CNT/DLY → DFF

LUT → CNT/DLY

DFF → CNT/DLY

Datasheet

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Revision 3.0

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SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1072

00: bypass the initial

01: initial 0

CNT2 initial value selection

10: initial 1

1073

11: initial 1

1074

1075

1076

0000: both edge Delay;

0001: falling edge delay;

0010: rising edge delay:

0011: both edge One Shot;

0100: falling edge One Shot;

0101: rising edge One Shot;

0110: both edge freq detect;

0111: falling edge freq detect;

1000: rising edge freq detect;

1001: both edge detect;

1010: falling edge detect;

1011: rising edge detect;

1100: both edge reset CNT;

1101: falling edge reset CNT;

1110: rising edge reset CNT;

1111: high level reset CNT

86

CNT2 function and edge mode selection

1077

1078

1079

1080

Clock source sel[3:0]

0000: 25M(OSC2);

0001: 25M/4;

0010: 2M(OSC1);

0011:2M/8;

0100: 2M/64;

0101: 2M/512;

0110:2K(OSC0);

0111: 2K/8;

DLY/CNT2 Clock Source Select

1000:2K/64;

1081

1001: 2K/512;

1010: 2K/4096;

1011:2K/32768;

1100: 2K/262144;

1101: CNT1_END;

1110: External;

1111: Not used

87

1082

1083

CNT2 output pol selection

CNT2 CNT mode SYNC selection

0: Default Output, 1: Inverted Output

0: bypass; 1: after two DFF

0: normal; 1: DLY function edge detection(regis-

ters[1077:1074] = 0000/0001/0010)

1084

CNT2 DLY EDET FUNCTION Selection

1085

1086

1087

1088

1089

1090

CNT3 initial value selection

Multi3 register configure

00:bypass the initial; 01: initial 0; 10: initial 1; 11: initial 1

refer to byte 88

0000: both edge Delay;

0001: falling edge delay;

0010: rising edge delay:

0011: both edge One Shot;

0100: falling edge One Shot;

0101: rising edge One Shot;

0110: both edge freq detect;

0111: falling edge freq detect;

1000: rising edge freq detect;

1001: both edge detect;

1010: falling edge detect;

1011: rising edge detect;

1100: both edge reset CNT;

1101: falling edge reset CNT;

1110: rising edge reset CNT;

1111: high level reset CNT

88

CNT3 function and edge mode selection

1091

Datasheet

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Revision 3.0

163 of 199

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SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

00000: Matrix A - In2; Matrix B - In1;

Matrix C - In0

(DLY_IN - LOW)

Single 3-bit LUT

10000: Matrix A - D; Matrix B - nSET/nRST; Matrix C - CLK

(DLY_IN - LOW)

00001: Matrix A- DLY_IN (CNT); Matrix B - EXT_CLK (CNT);

Matrix C - NC

(DLY_OUT connected to LUT/DFF)

Single DFF w RST and SET

Single CNT/DLY

00010: Matrix A - DLY_IN; Matrix B - In1; Matrix C - In0

(DLY_OUT connected to In2)

CNT/DLY → LUT

10010: Matrix A - DLY_IN; Matrix B - nSET/nRST;

Matrix C - CLK

CNT/DLY → DFF

1087,

(DLY_OUT connected to D)

88 1093:1092,

00110: Matrix A - In2; Matrix B - DLY_IN; Matrix C - In0

(DLY_OUT connected to In1)

1095:1094 CNT/DLY → LUT

10110: Matrix A - D; Matrix B - DLY_IN; Matrix C - CLK

(DLY_OUT connected to nSET/nRST)

01010: Matrix A - In2; Matrix B - In1;

Matrix C - DLY_IN

(DLY_OUT connected to In0)

CNT/DLY → DFF

CNT/DLY → LUT

11010: Matrix A- D; Matrix B - nSET/nRST; Matrix C - DLY_IN

(DLY_OUT connected to CLK)

00011: Matrix A - In2; Matrix B - In1; Matrix C - In0

(LUT_OUT connected to DLY_IN)

10011: Matrix A - D; Matrix B - nSET/nRST; Matrix C - CLK

(DFF_OUT connected to DLY_IN)

CNT/DLY → DFF

LUT → CNT/DLY

DFF → CNT/DLY

1096

1097

1098

Clock source sel[3:0]

0000: 25M(OSC2); 0001: 25M/4;

0010: 2M(OSC1); 0011:2M/8;

0100: 2M/64; 0101: 2M/512;

0110:2K(OSC0); 0111: 2K/8;

1000:2K/64; 1001: 2K/512;

1010: 2K/4096; 1011:2K/32768;

1100: 2K/262144; 1101: CNT2_END;

1110: External; 1111: Not used

DLY/CNT3 Clock Source Select

1099

89

0: Default Output

1: Inverted Output

1100

CNT3 output pol selection

0: bypass

1101

1102

1103

CNT3 CNT mode SYNC selection

1: after two DFF

0: normal

CNT3 DLY EDET FUNCTION Selection

CNT4 CNT mode SYNC selection

1: DLY function edge detection

(registers[1091:1088]=0000/0001/0010)

0: bypass

1: after two DFF

Datasheet

17-Jun-2021

Revision 3.0

164 of 199

CFR0011-120-00

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1104

00: bypass the initial

01: initial 0

CNT4 initial value selection

10: initial 1

1105

1106

11: initial 1

0: normal

1: DLY function edge detection

(registers[1119:1116]=0000/0001/0010)

CNT4 DLY EDET FUNCTION Selection

00000: Matrix A - In2; Matrix B - In1;

Matrix C - In0

(DLY_IN - LOW)

Single 3-bit LUT

10000: Matrix A - D; Matrix B - nSET/nRST; Matrix C - CLK

(DLY_IN - LOW)

00001: Matrix A- DLY_IN (CNT); Matrix B - EXT_CLK (CNT);

Matrix C - NC

(DLY_OUT connected to LUT/DFF)

Single DFF w RST and SET

Single CNT/DLY

00010: Matrix A - DLY_IN; Matrix B - In1; Matrix C - In0

(DLY_OUT connected to In2)

10010: Matrix A - DLY_IN; Matrix B - nSET/nRST;

Matrix C - CLK

(DLY_OUT connected to D)

00110: Matrix A - In2; Matrix B - DLY_IN; Matrix C - In0

(DLY_OUT connected to In1)

10110: Matrix A - D; Matrix B - DLY_IN; Matrix C - CLK

(DLY_OUT connected to nSET/nRST)

CNT/DLY → LUT

8A

CNT/DLY → DFF

1111:1107

CNT/DLY → LUT

CNT/DLY → DFF

01010: Matrix A - In2; Matrix B - In1;

Matrix C - DLY_IN

(DLY_OUT connected to In0)

CNT/DLY → LUT

11010: Matrix A- D; Matrix B - nSET/nRST; Matrix C - DLY_IN

(DLY_OUT connected to CLK)

00011: Matrix A - In2; Matrix B - In1; Matrix C - In0

(LUT_OUT connected to DLY_IN)

10011: Matrix A - D; Matrix B - nSET/nRST; Matrix C - CLK

(DFF_OUT connected to DLY_IN)

CNT/DLY → DFF

LUT → CNT/DLY

DFF → CNT/DLY

1112

1113

1114

Clock source sel[3:0]

0000: 25M(OSC2);

0001: 25M/4;

0010: 2M(OSC1);

0011:2M/8;

0100: 2M/64;

0101: 2M/512;

0110:2K(OSC0);

0111: 2K/8;

8B

DLY/CNT4 Clock Source Select

1000:2K/64;

1115

1001: 2K/512;

1010: 2K/4096;

1011:2K/32768;

1100: 2K/262144;

1101: CNT3_END;

1110: External;

1111: Not used

Datasheet

17-Jun-2021

Revision 3.0

165 of 199

CFR0011-120-00

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1116

1117

1118

0000: both edge Delay;

0001: falling edge delay;

0010: rising edge delay:

0011: both edge One Shot;

0100: falling edge One Shot;

0101: rising edge One Shot;

0110: both edge freq detect;

0111: falling edge freq detect;

1000: rising edge freq detect;

1001: both edge detect;

1010: falling edge detect;

1011: rising edge detect;

1100: both edge reset CNT;

1101: falling edge reset CNT;

1110: rising edge reset CNT;

1111: high level reset CNT

8B

CNT4 function and edge mode selection

1119

0: Default Output

1: Inverted Output

1120

CNT4 output pol selection

1121

1122

1123

0000: both edge Delay;

0001: falling edge delay;

0010: rising edge delay:

0011: both edge One Shot;

0100: falling edge One Shot;

0101: rising edge One Shot;

0110: both edge freq detect;

0111: falling edge freq detect;

1000: rising edge freq detect;

1001: both edge detect;

1010: falling edge detect;

1011: rising edge detect;

1100: both edge reset CNT;

1101: falling edge reset CNT;

1110: rising edge reset CNT;

1111: high level reset CNT

0: Default Output

1: Inverted Output

00000: Matrix A - In2; Matrix B - In1;

Matrix C - In0

(DLY_IN - LOW)

CNT5 function and edge mode selection

1124

1125

CNT5 output pol selection

Single 3-bit LUT

8C

10000: Matrix A - D; Matrix B - nSET/nRST; Matrix C - CLK

(DLY_IN - LOW)

00001: Matrix A- DLY_IN (CNT); Matrix B - EXT_CLK (CNT);

Matrix C - NC

(DLY_OUT connected to LUT/DFF)

Single DFF w RST and SET

Single CNT/DLY

00010: Matrix A - DLY_IN; Matrix B - In1; Matrix C - In0

(DLY_OUT connected to In2)

10010: Matrix A - DLY_IN; Matrix B - nSET/nRST;

Matrix C - CLK

(DLY_OUT connected to D)

CNT/DLY → LUT

1134,

1127:1126,

1133:1132

CNT/DLY → DFF

00110: Matrix A - In2; Matrix B - DLY_IN; Matrix C - In0

(DLY_OUT connected to In1)

10110: Matrix A - D; Matrix B - DLY_IN; Matrix C - CLK

(DLY_OUT connected to nSET/nRST)

CNT/DLY → LUT

CNT/DLY → DFF

01010: Matrix A - In2; Matrix B - In1;

Matrix C - DLY_IN

(DLY_OUT connected to In0)

CNT/DLY → LUT

Datasheet

17-Jun-2021

Revision 3.0

166 of 199

CFR0011-120-00

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

11010: Matrix A- D; Matrix B - nSET/nRST; Matrix C - DLY_IN

(DLY_OUT connected to CLK)

00011: Matrix A - In2; Matrix B - In1; Matrix C - In0

(LUT_OUT connected to DLY_IN)

10011: Matrix A - D; Matrix B - nSET/nRST; Matrix C - CLK

(DFF_OUT connected to DLY_IN)

CNT/DLY → DFF

1134,

8C 1127:1126, LUT → CNT/DLY

1133:1132

DFF → CNT/DLY

1128

1129

1130

Clock source sel[3:0]

0000: 25M(OSC2);

0001: 25M/4;

0010: 2M(OSC1);

0011:2M/8;

0100: 2M/64;

0101: 2M/512;

0110:2K(OSC0);

0111: 2K/8;

DLY/CNT5 Clock Source Select

1000:2K/64;

8D

1131

1135

1001: 2K/512;

1010: 2K/4096;

1011:2K/32768;

1100: 2K/262144;

1101: CNT4_END;

1110: External;

1111: Not used

0: normal;

1: DLY function edge detection

(registers[1124:1121]=0000/0001/0010)

0: bypass;

1: after two DFF

00: bypass the initial

01: initial 0

10: initial 1

11: initial 1

CNT5 DLY EDET FUNCTION Selection

CNT5 CNT mode SYNC selection

1136

1137

CNT5 initial value selection

1138

1139

1140

1141

0000: both edge Delay;

0001: falling edge delay;

0010: rising edge delay:

0011: both edge One Shot;

0100: falling edge One Shot;

0101: rising edge One Shot;

0110: both edge freq detect;

0111: falling edge freq detect;

1000: rising edge freq detect;

1001: both edge detect;

1010: falling edge detect;

1011: rising edge detect;

1100: both edge reset CNT;

1101: falling edge reset CNT;

1110: rising edge reset CNT;

1111: high level reset CNT

8E

CNT6 function and edge mode selection

1142

1143

0: Default Output

1: Inverted Output

CNT6 output pol selection

Datasheet

17-Jun-2021

Revision 3.0

167 of 199

CFR0011-120-00

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1144

1145

1146

Clock source sel[3:0]

0000: 25M(OSC2);

0001: 25M/4;

0010: 2M(OSC1);

0011:2M/8;

0100: 2M/64;

0101: 2M/512;

0110:2K(OSC0);

0111: 2K/8;

DLY/CNT6 Clock Source Select

1000:2K/64;

1147

1001: 2K/512;

1010: 2K/4096;

1011:2K/32768;

1100: 2K/262144;

1101: CNT5_END;

1110: External;

1111: Not used

00000: Matrix A - In2; Matrix B - In1;

Matrix C - In0

(DLY_IN - LOW)

Single 3-bit LUT

10000: Matrix A - D; Matrix B - nSET/nRST; Matrix C - CLK

(DLY_IN - LOW)

00001: Matrix A- DLY_IN (CNT); Matrix B - EXT_CLK (CNT);

Matrix C - NC

(DLY_OUT connected to LUT/DFF)

Single DFF w RST and SET

Single CNT/DLY

8F

00010: Matrix A - DLY_IN; Matrix B - In1; Matrix C - In0

(DLY_OUT connected to In2)

CNT/DLY → LUT

10010: Matrix A - DLY_IN; Matrix B - nSET/nRST;

Matrix C - CLK

CNT/DLY → DFF

1152,

(DLY_OUT connected to D)

1149:1148,

00110: Matrix A - In2; Matrix B - DLY_IN; Matrix C - In0

(DLY_OUT connected to In1)

1151:1150 CNT/DLY → LUT

10110: Matrix A - D; Matrix B - DLY_IN; Matrix C - CLK

(DLY_OUT connected to nSET/nRST)

CNT/DLY → DFF

01010: Matrix A - In2; Matrix B - In1;

Matrix C - DLY_IN

(DLY_OUT connected to In0)

CNT/DLY → LUT

11010: Matrix A- D; Matrix B - nSET/nRST; Matrix C - DLY_IN

(DLY_OUT connected to CLK)

00011: Matrix A - In2; Matrix B - In1; Matrix C - In0

(LUT_OUT connected to DLY_IN)

10011: Matrix A - D; Matrix B - nSET/nRST; Matrix C - CLK

(DFF_OUT connected to DLY_IN)

CNT/DLY → DFF

LUT → CNT/DLY

DFF → CNT/DLY

0: normal

1153

CNT6 DLY EDET FUNCTION Selection

1: DLY function edge detection (registers[1142:1139]=0000/

0001/0010)

90

0: bypass

1154

1155

CNT6 CNT mode SYNC selection

CNT6 initial value selection

1: after two DFF

00: bypass the initial

01: initial 0

10: initial 1

11: initial 1

00: bypass the initial

01: initial 0

10: initial 1

11: initial 1

1156

1157

1158

CNT7 initial value selection

0: bypass

1: after two DFF

1159

CNT7 CNT mode SYNC selection

Datasheet

17-Jun-2021

Revision 3.0

168 of 199

CFR0011-120-00

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

0: normal

1160

CNT7 DLY EDET FUNCTION Selection

1: DLY function edge detection (registers [1174:1171]=0000/

0001/0010)

00000: Matrix A - In2; Matrix B - In1;

Matrix C - In0

(DLY_IN - LOW)

Single 3-bit LUT

10000: Matrix A - D; Matrix B - nSET/nRST; Matrix C - CLK

(DLY_IN - LOW)

00001: Matrix A- DLY_IN (CNT); Matrix B - EXT_CLK (CNT);

Matrix C - NC

(DLY_OUT connected to LUT/DFF)

Single DFF w RST and SET

Single CNT/DLY

00010: Matrix A - DLY_IN; Matrix B - In1; Matrix C - In0

(DLY_OUT connected to In2)

CNT/DLY → LUT

10010: Matrix A - DLY_IN; Matrix B - nSET/nRST;

Matrix C - CLK

CNT/DLY → DFF

91

(DLY_OUT connected to D)

1161,

1165:1162

00110: Matrix A - In2; Matrix B - DLY_IN; Matrix C - In0

(DLY_OUT connected to In1)

10110: Matrix A - D; Matrix B - DLY_IN; Matrix C - CLK

(DLY_OUT connected to nSET/nRST)

CNT/DLY → LUT

CNT/DLY → DFF

01010: Matrix A - In2; Matrix B - In1;

Matrix C - DLY_IN

(DLY_OUT connected to In0)

CNT/DLY → LUT

11010: Matrix A- D; Matrix B - nSET/nRST; Matrix C - DLY_IN

(DLY_OUT connected to CLK)

00011: Matrix A - In2; Matrix B - In1; Matrix C - In0

(LUT_OUT connected to DLY_IN)

10011: Matrix A - D; Matrix B - nSET/nRST; Matrix C - CLK

(DFF_OUT connected to DLY_IN)

CNT/DLY → DFF

LUT → CNT/DLY

DFF → CNT/DLY

Datasheet

17-Jun-2021

Revision 3.0

169 of 199

CFR0011-120-00

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1166

1167

1168

Clock source sel[3:0]

0000: 25M(OSC2);

0001: 25M/4;

91

0010: 2M(OSC1);

0011:2M/8;

0100: 2M/64;

0101: 2M/512;

0110:2K(OSC0);

0111: 2K/8;

DLY/CNT7 Clock Source Select

1000:2K/64;

1169

1001: 2K/512;

1010: 2K/4096;

1011: 2K/32768;

1100: 2K/262144;

1101: CNT6_END;

1110: External;

1111: Not used

0: Default Output

1: Inverted Output

0000: both edge Delay;

0001: falling edge delay;

0010: rising edge delay:

0011: both edge One Shot;

0100: falling edge One Shot;

0101: rising edge One Shot;

0110: both edge freq detect;

0111: falling edge freq detect;

1000: rising edge freq detect;

1001: both edge detect;

1010: falling edge detect;

1011: rising edge detect;

1100: both edge reset CNT;

1101: falling edge reset CNT;

1110: rising edge reset CNT;

1111: high level reset CNT

1170

CNT7 output pol selection

CNT7 function and edge mode selection

Reserved

1171

1172

1173

92

1174

1175

1176

1177

1178

1179

1180

1181

1182

1183

1184

1185

1186

1187

1188

1189

1190

1191

93

[15]:LUT4_1 [15]/DFF20 or LATCH Select

0: DFF function, 1: LATCH function

[14]:LUT4_1 [14]/DFF20 Output Select

0: Q output, 1: QB output

Multi0_LUT4_DFF setting

[13]:LUT4_1 [13]/DFF20 Initial Polarity Select

0: Low, 1: High

[12:0]:LUT4_1 [12:0]

94

Datasheet

17-Jun-2021

Revision 3.0

170 of 199

CFR0011-120-00

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1192

1193

1194

1195

1196

1197

1198

1199

1200

1201

1202

1203

1204

1205

1206

1207

1208

1209

1210

1211

1212

1213

1214

1215

1216

1217

1218

1219

1220

1221

1222

1223

1224

1225

1226

1227

1228

1229

1230

1231

1232

1233

1234

1235

1236

1237

1238

1239

95

REG_CNT0_D[15:0]

Data[15:0]

96

97

98

99

9A

[7]:LUT3_9 [7]/DFF13 or LATCH Select

0: DFF function, 1: LATCH function

[6]:LUT3_9 [6]/DFF13 Output Select

0: Q output, 1: QB output

Multi1_LUT3_DFF setting

[5]:LUT3_9 [5]/DFF13

0: nRST from Matrix Output, 1: nSET from Matrix Output

[4]:LUT3_9 [4]/DFF13 Initial Polarity Select

0: Low, 1: High

[3:0]:LUT3_9 [3:0]

REG_CNT1_D[7:0]

Data[7:0]

[7]:LUT3_10 [7]/DFF14 or LATCH Select

0: DFF function, 1: LATCH function

[6]:LUT3_10[6]/DFF14 Output Select

0: Q output, 1: QB output

Multi2_LUT3_DFF setting

[5]:LUT3_10 [5]/DFF14

0: nRST from Matrix Output, 1: nSET from Matrix Output

[4]:LUT3_10 [4]/DFF14 Initial Polarity Select

0: Low, 1: High

[3:0]:LUT3_10 [3:0]

REG_CNT2_D[7:0]

Data[7:0]

Datasheet

17-Jun-2021

Revision 3.0

171 of 199

CFR0011-120-00

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1240

1241

1242

1243

1244

1245

1246

1247

1248

1249

1250

1251

1252

1253

1254

1255

1256

1257

1258

1259

1260

1261

1262

1263

1264

1265

1266

1267

1268

1269

1270

1271

1272

1273

1274

1275

1276

1277

1278

1279

1280

1281

1282

1283

1284

1285

1286

1287

[7]:LUT3_11 [7]/DFF15 or LATCH Select

0: DFF function, 1: LATCH function

[6]:LUT3_11[6]/DFF15 Output Select

0: Q output, 1: QB output

9B

Multi3_LUT3_DFF setting

[5]:LUT3_11 [5]/DFF15

0: nRST from Matrix Output, 1: nSET from Matrix Output

[4]:LUT3_11 [4]/DFF15 Initial Polarity Select

0: Low, 1: High

[3:0]:LUT3_11 [3:0]

9C

9D

9E

9F

A0

REG_CNT3_D[7:0]

Data[7:0]

[7]:LUT3_12 [7]/DFF16 or LATCH Select

0: DFF function, 1: LATCH function

[6]:LUT3_12[6]/DFF16 Output Select

0: Q output, 1: QB output

Multi4_LUT3_DFF setting

[5]:LUT3_12 [5]/DFF16

0: nRST from Matrix Output, 1: nSET from Matrix Output

[4]:LUT3_12 [4]/DFF16 Initial Polarity Select

0: Low, 1: High

[3:0]:LUT3_12 [3:0]

REG_CNT4_D[7:0]

Data[7:0]

[7]:LUT3_13 [7]/DFF17 or LATCH Select

0: DFF function, 1: LATCH function

[6]:LUT3_13[6]/DFF17 Output Select

0: Q output, 1: QB output

Multi5_LUT3_DFF setting

[5]:LUT3_13 [5]/DFF17

0: nRST from Matrix Output, 1: nSET from Matrix Output

[4]:LUT3_13 [4]/DFF17 Initial Polarity Select

0: Low, 1: High

[3:0]:LUT3_13 [3:0]

REG_CNT5_D[7:0]

Data[7:0]

Datasheet

17-Jun-2021

Revision 3.0

172 of 199

CFR0011-120-00

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1288

1289

1290

1291

1292

1293

1294

1295

1296

1297

1298

1299

1300

1301

1302

1303

1304

1305

1306

1307

1308

1309

1310

1311

1312

1313

1314

1315

1316

1317

1318

1319

1320

1321

1322

1323

1324

1325

1326

1327

1328

1329

1330

1331

1332

1333

1334

1335

[7]:LUT3_14 [7]/DFF18 or LATCH Select

0: DFF function, 1: LATCH function

[6]:LUT3_14[6]/DFF18 Output Select

0: Q output, 1: QB output

A1

Multi6_LUT3_DFF setting

[5]:LUT3_14 [5]/DFF18

0: nRST from Matrix Output, 1: nSET from Matrix Output

[4]:LUT3_14 [4]/DFF18 Initial Polarity Select

0: Low, 1: High

[3:0]:LUT3_14 [3:0]

A2

A3

A4

A5

A6

REG_CNT6_D[7:0]

Data[7:0]

[7]:LUT3_15 [7]/DFF19 or LATCH Select

0: DFF function, 1: LATCH function

[6]:LUT3_15[6]/DFF19 Output Select

0: Q output, 1: QB output

Multi7_LUT3_DFF setting

[5]:LUT3_15 [5]/DFF19

0: nRST from Matrix Output, 1: nSET from Matrix Output

[4]:LUT3_15 [4]/DFF19 Initial Polarity Select

0: Low, 1: High

[3:0]:LUT3_15 [3:0]

REG_CNT7_D[7:0]

Data[7:0]

CNT0 (16bits) Counted Value

Virtual Input

Datasheet

17-Jun-2021

Revision 3.0

173 of 199

CFR0011-120-00

SLG46855-A

Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1336

1337

1338

1339

1340

1341

1342

1343

1344

1345

1346

1347

1348

1349

1350

1351

1352

1353

1354

1355

1356

1357

1358

A7

CNT6 (8bits) Counted Value

Virtual Input

A8

CNT7 (8bits) Counted Value

Virtual Input

[7]:LUT3_1 [7]/DFF4 or LATCH Select

0: DFF function, 1: LATCH function

[6]:LUT3_1 [6]/DFF4 Output Select

0: Q output, 1: QB output

[5]:LUT3_1 [5]/DFF4 Initial Polarity Select

0: Low, 1: High

[4]:LUT3_1 [4]/DFF4

0: nRST from Matrix Output, 1: nSET from Matrix Output

[3]:LUT3_1 [3]/DFF4 Active level selection for RST/SET

0: Active low level reset/set, 1: Active high level reset/set

[2:0]: LUT3_1 [2:0]

A9

LUT3_1_DFF4 setting

1359

1360

1361

1362

1363

1364

1365

1366

[7]:LUT3_2 [7]/DFF5 or LATCH Select

0: DFF function, 1: LATCH function

[6]:LUT3_2 [6]/DFF5 Output Select

0: Q output, 1: QB output

[5]:LUT3_2 [5]/DFF5 Initial Polarity Select

0: Low, 1: High

AA

LUT3_2_DFF5 setting

[4]:LUT3_2 [4]/DFF5

0: nRST from Matrix Output, 1: nSET from Matrix Output

[3]:LUT3_2 [3]/DFF5 Active level selection for RST/SET

0: Active low level reset/set, 1: Active high level reset/set

[2:0]: LUT3_2 [2:0]

1367

1368

1369

1370

1371

1372

1373

1374

[7]:LUT3_3 [7]/DFF6 or LATCH Select

0: DFF function, 1: LATCH function

[6]:LUT3_3 [6]/DFF6 Output Select

0: Q output, 1: QB output

[5]:LUT3_3 [5]/DFF6 Initial Polarity Select

0: Low, 1: High

AB

LUT3_3_DFF6 setting

[4]:LUT3_3 [4]/DFF6

0: nRST from Matrix Output, 1: nSET from Matrix Output

[3]:LUT3_3 [3]/DFF6 Active level selection for RST/SET

0: Active low level reset/set, 1: Active high level reset/set

[2:0]: LUT3_3 [2:0]

1375

Datasheet

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Revision 3.0

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1376

1377

1378

1379

1380

1381

1382

[7]:LUT3_4 [7]/DFF7 or LATCH Select

0: DFF function, 1: LATCH function

[6]:LUT3_4 [6]/DFF7 Output Select

0: Q output, 1: QB output

[5]:LUT3_4 [5]/DFF7 Initial Polarity Select

0: Low, 1: High

AC

LUT3_4_DFF7 setting

[4]:LUT3_4 [4]/DFF7

0: nRST from Matrix Output, 1: nSET from Matrix Output

[3]:LUT3_4 [3]/DFF7 Active level selection for RST/SET

0: Active low level reset/set, 1: Active high level reset/set

[2:0]: LUT3_4 [2:0]

1383

1384

1385

1386

1387

LUT2_3_VAL or PGen_data

LUT2_3[3:0] or PGen 4bit counter data[3:0]

0: LUT3_1

1: DFF4

0: LUT3_2

1: DFF5

0: LUT3_3

1: DFF6

0: LUT3_4

1: DFF7

1388

1389

1390

1391

LUT3_1 or DFF4 Select

LUT3_2 or DFF5 Select

LUT3_3 or DFF6 Select

LUT3_4 or DFF7 Select

AD

1392

1393

1394

1395

1396

1397

1398

1399

1400

1401

1402

1403

1404

1405

1406

1407

AE

PGen data

PGen Data[15:0]

AF

Datasheet

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

0: LUT2_3

1: PGen

1408

1409

1410

1411

1412

1413

1414

1415

LUT2_3 or PGen Select

Active level selection for RST/SET for LUT2_3 0: Active low level reset/set

or PGen 1: Active high level reset/set

Activelevelselection for RST/SETfor LUT3_16 0: Active low level reset/set

or Pipe Delay/RIPP CNT 1: Active high level reset/set

Out of LUT3_16 or Out0 of Pipe Delay/RIPP 0: LUT3_16

CNT Select

1: OUT0 of Pipe Delay or RIPP CNT

0: Pipe delay mode selection

1: Ripple Counter mode selection

0: Non-inverted

1: Inverted

0: LUT4_0

1: DFF12

0: LUT3_0

1: DFF3

B0

PIPE_RIPP_CNT_S

Pipe Delay OUT1 Polarity Select

LUT4_0 or DFF12 Select

LUT3_0 or DFF3 Select

1416

1417

1418

1419

1420

1421

1422

1423

1424

1425

1426

1427

1428

1429

1430

1431

1432

1433

1434

1435

1436

1437

1438

1439

1440

1441

1442

1443

1444

1445

1446

[7:4]: LUT3_8 [7:4]/REG_S1[3:0] pipe delay out1 sel

[3:0]: LUT3_8 [3:0]/REG_S0[3:0] pipe delay out0 sel

at RIPP CNT mode:

LUT value or pipe delay out sel or nSET/END

value

B1

B2

B3

bit[1418:1416] is the nSET value

bit[1421:1419] is the END value

bit[1422] is the range control: 0 full cycle, 1 range cycle

bit[1423] Not used

[15]:LUT4_0 [15]/DFF12 or LATCH Select

0: DFF function, 1: LATCH function

[14]:LUT4_0 [14]/DFF12 Output Select

0: Q output, 1: QB output

[13]:LUT4_0 [13]/DFF12 Initial Polarity Select

0: Low, 1: High

[12]:LUT4_0 [12]/DFF12 stage selection

0: Q of first DFF; 1 Q of second DFF

[11]:LUT4_0 [11]/DFF12

0: nRST from Matrix Output, 1: nSET from Matrix Output

[10]:LUT4_0 [10]/DFF12 Active level selection for RST/SET

0: Active low level reset/set, 1: Active high level reset/set

[9:0]: LUT4_0 [9:0]

LUT4_0_DFF12 setting

[7]:LUT3_0 [7]/DFF3 or LATCH Select

0: DFF function, 1: LATCH function

[6]:LUT3_0 [6]/DFF3 Output Select

0: Q output, 1: QB output

[5]:LUT3_0 [5]/DFF3 Initial Polarity Select

0: Low, 1: High

[4]:LUT3_0 [4]/DFF3stage selection

0: Q of first DFF; 1 Q of second DFF

[3]:LUT3_0 [3]/DFF3

0: nRST from Matrix Output, 1: nSET from Matrix Output

[2]:LUT3_0 [2]/DFF3 Active level selection for RST/SET

0: Active low level reset/set, 1: Active high level reset/set

[1:0]: LUT3_0 [1:0]

B4

LUT3_0_DFF3 setting

1447

Datasheet

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

0, filter

1448

Filter or Edge Detector selection

Output Polarity Select

1, edge det

0: output non-invert

1: output invert

00: Rising Edge Det

01: Falling Edge Det

10: Both Edge Det

11: Both Edge DLY

1449

1450

Select the edge mode

1451

1452

1453

1454

1455

B5

00: 125 ns

Delay Value Select for Programmable Delay & 01: 250 ns

Edge Detector

10: 375 ns

11: 500 ns

00: Rising Edge Detector

Select the Edge Mode of Programmable Delay 01: Falling Edge Detector

& Edge Detector

10: Both Edge Detector

11: Both Edge Delay

1456

1457

1458

1459

1460

1461

1462

[7]:LUT3_5 [7]/DFF8 or LATCH Select

0: DFF function, 1: LATCH function

[6]:LUT3_5 [6]/DFF8 Output Select

0: Q output, 1: QB output

[5]:LUT3_5 [5]/DFF8 Initial Polarity Select

0: Low, 1: High

B6

B7

B8

B9

LUT3_5_DFF8 setting

[4]:LUT3_5 [4]/DFF8

0: nRST from Matrix Output, 1: nSET from Matrix Output

[3]:LUT3_5 [3]/DFF8 Active level selection for RST/SET

0: Active low level reset/set, 1: Active high level reset/set

[2:0]: LUT3_5 [2:0]

1463

1464

1465

1466

1467

1468

1469

1470

[7]:LUT3_6 [7]/DFF9 or LATCH Select

0: DFF function, 1: LATCH function

[6]:LUT3_6 [6]/DFF9 Output Select

0: Q output, 1: QB output

[5]:LUT3_6 [5]/DFF9 Initial Polarity Select

0: Low, 1: High

[4]:LUT3_6 [4]/DFF9

0: nRST from Matrix Output, 1: nSET from Matrix Output

[3]:LUT3_6 [3]/DFF9 Active level selection for RST/SET

0: Active low level reset/set, 1: Active high level reset/set

[2:0]: LUT3_6 [2:0]

[7]:LUT3_7 [7]/DFF10 or LATCH Select

0: DFF function, 1: LATCH function

[6]:LUT3_7 [6]/DFF10 Output Select

0: Q output, 1: QB output

[5]:LUT3_7 [5]/DFF10 Initial Polarity Select

0: Low, 1: High

[4]:LUT3_7 [4]/DFF10

0: nRST from Matrix Output, 1: nSET from Matrix Output

[3]:LUT3_7 [3]/DFF10 Active level selection for RST/SET

0: Active low level reset/set, 1: Active high level reset/set

[2:0]: LUT3_7 [2:0]

[7]:LUT3_8 [7]/DFF11 or LATCH Select

0: DFF function, 1: LATCH function

[6]:LUT3_8 [6]/DFF11 Output Select

0: Q output, 1: QB output

[5]:LUT3_8 [5]/DFF11 Initial Polarity Select

0: Low, 1: High

[4]:LUT3_8 [4]/DFF11

LUT3_6_DFF9 setting

LUT3_7_DFF10 setting

LUT3_8_DFF11 setting

1471

1472

1473

1474

1475

1476

1477

1478

1479

1480

1481

1482

1483

1484

1485

1486

0: nRST from Matrix Output, 1: nSET from Matrix Output

[3]:LUT3_8 [3]/DFF11 Active level selection for RST/SET

0: Active low level reset/set, 1: Active high level reset/set

[2:0]: LUT3_8 [2:0]

1487

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Revision 3.0

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Auto Grade GreenPAK Programmable Mixed-Signal Matrix

Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

0: LUT2_0

1: DFF0

0: LUT2_1

1: DFF1

1488

1489

LUT2_0 or DFF0 Select

LUT2_1 or DFF1 Select

0: LUT2_2

1: DFF2

1490

1491

1492

LUT2_2 or DFF2 Select

Reserved

BA

0: LUT3_5

1: DFF8

LUT3_5 or DFF8 Select

0: LUT3_6

1: DFF9

0: LUT3_7

1: DFF10

0: LUT3_8

1: DFF11

1493

1494

1495

LUT3_6 or DFF9 Select

LUT3_7 or DFF10 Select

LUT3_8 or DFF11 Select

1496

1497

1498

[3]:LUT2_0 [3]/DFF0 or LATCH Select

0: DFF function, 1: LATCH function

[2]:LUT2_0 [2]/DFF0 Output Select

0: Q output, 1: QB output

LUT2_0/DFF0 setting

LUT2_1/DFF1 setting

LUT2_2/DFF2 setting

[1]:LUT2_0 [1]/DFF0 Initial Polarity Select

0: Low, 1: High

1499

[0]:LUT2_0 [0]

BB

1500

1501

1502

[3]:LUT2_1 [3]/DFF1 or LATCH Select

0: DFF function, 1: LATCH function

[2]:LUT2_1 [2]/DFF1 Output Select

0: Q output, 1: QB output

[1]:LUT2_1 [1]/DFF1 Initial Polarity Select

0: Low, 1: High

[0]:LUT2_1 [0]

[3]:LUT2_2 [3]/DFF2 or LATCH Select

0: DFF function, 1: LATCH function

[2]:LUT2_2 [2]/DFF2 Output Select

0: Q output, 1: QB output

[1]:LUT2_2 [1]/DFF2 Initial Polarity Select

0: Low, 1: High

[0]:LUT2_2 [0]

1503

1504

1505

1506

1507

BC

1508

1509

1510

1511

1512

1513

1514

1515

1516

1517

1518

1519

Reserved

BD

Datasheet

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Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1520

1521

1522

1523

1524

1525

1526

1527

1528

1529

1530

1531

1532

1533

1534

1535

1536

1537

1538

1539

1540

1541

1542

1543

1544

1545

1546

1547

1548

1549

1550

1551

1552

1553

1554

1555

1556

1557

1558

1559

1560

1561

1562

1563

1564

1565

1566

1567

Reserved

BE

Reserved

BF

C0

C1

C2

C3

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Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1568

1569

1570

1571

1572

1573

1574

1575

1576

1577

1578

1579

1580

1581

1582

1583

1584

1585

1586

1587

1588

1589

1590

1591

1592

1593

1594

1595

1596

1597

1598

1599

1600

1601

1602

1603

1604

1605

1606

1607

1608

1609

1610

1611

1612

1613

1614

1615

Reserved

C4

C5

C6

C7

C8

C9

Datasheet

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Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1616

1617

1618

1619

1620

1621

1622

1623

1624

1625

1626

1627

1628

1629

1630

1631

1632

1633

1634

1635

1636

1637

1638

1639

1640

1641

1642

1643

1644

1645

1646

1647

1648

1649

1650

1651

1652

1653

1654

1655

1656

1657

1658

1659

1660

1661

1662

1663

Reserved

CA

CB

CC

CD

CE

CF

Datasheet

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Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1664

1665

1666

1667

1668

1669

1670

1671

1672

1673

1674

1675

1676

1677

1678

1679

1680

1681

1682

1683

1684

1685

1686

1687

1688

1689

1690

1691

1692

1693

1694

1695

1696

1697

1698

1699

1700

1701

1702

1703

1704

1705

1706

1707

1708

1709

1710

1711

Reserved

D0

D1

D2

D3

D4

D5

Datasheet

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Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1712

1713

1714

1715

1716

1717

1718

1719

1720

1721

1722

1723

1724

1725

1726

1727

1728

1729

1730

1731

1732

1733

1734

1735

1736

1737

1738

1739

1740

1741

1742

1743

1744

1745

1746

1747

1748

1749

1750

1751

1752

1753

1754

1755

1756

1757

1758

1759

Reserved

D6

D7

D8

D9

DA

DB

Datasheet

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Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1760

1761

1762

1763

1764

1765

1766

1767

1768

1769

1770

1771

1772

1773

1774

1775

1776

1777

1778

1779

1780

1781

1782

1783

1784

1785

1786

1787

1788

1789

1790

1791

1792

1793

1794

1795

1796

1797

1798

1799

1800

1801

1802

1803

1804

1805

1806

1807

Reserved

DC

DD

DE

DF

E0

E1

Datasheet

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Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1808

1809

1810

1811

1812

1813

1814

1815

1816

1817

1818

1819

1820

1821

1822

1823

1824

1825

1826

1827

1828

1829

1830

1831

1832

1833

1834

1835

1836

1837

1838

1839

1840

1841

1842

1843

1844

1845

1846

1847

1848

1849

1850

1851

1852

1853

1854

1855

Reserved

E2

E3

E4

E5

E6

E7

Datasheet

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Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1856

1857

1858

1859

1860

1861

1862

1863

1864

1865

1866

1867

1868

1869

1870

1871

1872

1873

1874

1875

1876

1877

1878

1879

1880

1881

1882

1883

1884

1885

1886

1887

1888

1889

1890

1891

1892

1893

1894

1895

1896

1897

1898

1899

1900

1901

1902

1903

Reserved

E8

E9

EA

EB

EC

ED

Datasheet

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Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1904

1905

1906

1907

1908

1909

1910

1911

1912

1913

1914

1915

1916

1917

1918

1919

1920

1921

1922

1923

1924

1925

1926

1927

1928

1929

1930

1931

1932

1933

1934

1935

1936

1937

1938

1939

1940

1941

1942

1943

1944

1945

1946

1947

1948

1949

1950

1951

Reserved

EE

EF

F0

F1

F2

F3

Datasheet

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Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1952

GPO0 I2C output expander data

GPO0 I2C output expander select

0: GPO0 output come from matrix

1: GPO0 output is register

1953

1954

GPIO6 I2C output expander data

0: GPIO6 output come from matrix

1: GPIO6 output is register

1955

1956

1957

1958

1959

GPIO6 I2C output expander select

GPIO7 I2C output expander data

GPIO7 I2C output expander select

GPIO8 I2C output expander data

GPIO8 I2C output expander select

F4

0: GPIO7 output come from matrix

1: GPIO7 output is register

0: GPIO8 output come from matrix

1: GPIO8 output is register

I2C reset bit with reloading NVM into Data

register (soft reset)

0: Keep existing condition

1: Reset execution

1960

0: Disable

1: Enable

1961

1962

1963

IO Latching Enable During I2C Write Interface

Reserved

0: Disable

1: Enable

Protect mode enable

F5

1964

1965

1966

Reserved

Register protection mode bit 0

Register protection mode bit 1

000: all open read/write (mode 0);

001: partly lock read (mode 1);

010: partly lock read2 (mode 2);

011: partly lock read2/write (mode 3);

100: all lock read (mode 4);

1967

Register protection mode bit 2

101: all lock write (mode 5);

110: all lock read/write (mode 6).

1968

1969

1970

1971

1972

1973

1974

1975

1976

1977

1978

1979

1980

1981

1982

1983

1984

1985

1986

1987

1988

1989

1990

1991

1: mask

0: overwrite

F6

F7

F8

I²C write mask bits

Reserved

Datasheet

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Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

1992

Reserved

1993

1994

1995

1996

1997

1998

1999

2000

2001

2002

2003

2004

2005

2006

2007

2008

2009

2010

2011

2012

2013

2014

2015

2016

2017

2018

2019

2020

2021

2022

2023

2024

2025

2026

2027

Reserved

F9

FA

FB

FC

Reserved

I²C slave address

0: from register [2024]

1: from GPI0

0: from register [2025]

1: from GPIO2

0: from register [2026]

1: from GPIO4

0: from register [2027]

1: from GPIO5

2028

2029

2030

2031

Slave address selection bit0

Slave address selection bit1

Slave address selection bit2

Slave address selection bit3

FD

Datasheet

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Table 57: Register Map (Continued)

Address

Signal Function

Register Bit Definition

Register

Bit

Byte

0: I2C operation enable; matrix in 32(33) select

I2C_virtual_0(1) Input

1: I2C operation disable; matrix in 32(33) select

GPIO0(GPIO1) digital input

2032

I2C operation disable bit

2033

2034

2035

2036

2037

2038

2039

2040

2041

2042

2043

2044

2045

2046

2047

Reserved

FE

FF

Reserved

Datasheet

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18 Package Top Marking Definitions

18.1 FCQFN 14L 3MM X 3 MM 0.65P FCD

PPPPP

DDLLL

Part Code

Date Code + Lot Number

Country + Revision

Pin 1 Identifier

ARR

Datasheet

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19 Package Information

19.1 PACKAGE OUTLINES FOR FCQFN 14L 3.0 MM X 3.0 MM X 0.55 MM 0.65P FC PACKAGE

Detail A

Top View

Bottom View

Wettable Flank

Detail A

Terminal Cross Section

Controlling Dimensions: mm

Marking View

Standard Tolerance: ±0.05

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19.2 FCQFN HANDLING

Be sure to handle FCQFN package only in a clean, ESD-safe environment. Tweezers or vacuum pick-up tools are suitable for

handling. Do not handle FCQFN package with fingers as this can contaminate the package pins and interface with solder re-

flow.

19.3 SOLDERING INFORMATION

Please see IPC/JEDEC J-STD-020: latest revision for re-flow profile based on package volume of 2.64 mm³(nominal) for

FCQFN 14L Package. More information can be found at www.jedec.org.

20 Ordering Information

Part Number

Type

SLG46855-AP

SLG46855-APTR

14-pin FCQFN

14-pin FCQFN - Tape and Reel (5k units)

20.1 TAPE AND REEL SPECIFICATIONS

Max Units

Leader (min)

Length

Trailer (min)

Length

Nominal

# of

Pins

Reel &

Hub Size

(mm)

Tape Part

Width Pitch

(mm) (mm)

Package Type

Package Size

(mm)

per Reel per Box

Pockets

(mm)

FCQFN 14L

3 mm x 3 mm

0.65P FC Green

14 3.0 x 3.0 x0.55 5000

10000 330/102

50

400

50

400

12

8

20.2 CARRIER TAPE DRAWING AND DIMENSIONS

Index Hole Index Hole

PocketBTMPocketBTM Pocket Index Hole Pocket Index Hole

to Tape

Edge

to Pocket Tape Width

Center

(mm)

Length

(mm)

Width

(mm)

Depth

(mm)

Pitch

(mm)

Pitch Diameter

(mm)

Package Type

(mm)

A0

B0

K0

P0

P1

D0

E

F

W

FCQFN 14L

3.0 mm x 3.0mm

0.65P FC Green

3.3

0.8

4

8

1.5

1.75

5.5

12

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21 Layout Guidelines

21.1 FCQFN 14L 3 MM X 3 MM X 0.5 MM 0.65P FC GREEN

Unit: mm

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Glossary

A

ACK

Acknowledge bit

ACMP

ACMPH

ACMPL

ADAS

Analog Comparator

Analog Comparator High Speed

Analog Comparator Low Power

Advanced Driver Assistance Systems

B

BG

Bandgap

C

CLK

CMO

CNT

Clock

Connection matrix output

Counter

D

DFF

DLY

D Flip-Flop

Delay

E

ESD

EV

Electrostatic discharge

End Value

F

FSM

Finite State Machine

G

GPI

GPIO

GPO

General Purpose Input

General Purpose Input/Output

General Purpose Output

I

IN

IO

Input

Input/Output

L

LPF

LSB

Low Pass Filter

Least Significant Bit

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LUT

LV

Look Up Table

Low Voltage

M

MSB

MUX

Most Significant Bit

Multiplexer

N

NPR

nRST

NVM

Non-Volatile Memory Read/Write/Erase Protection

Reset

Non-Volatile Memory

O

OD

Open-Drain

OE

Output Enable

Oscillator

OSC

OTP

OUT

one time programmable

Output

P

PD

Power-down

PGen

POR

PP

Pattern Generator

Power-On Reset

Push-Pull

PWR

P DLY

Power

Programmable Delay

R

R/W

Read/Write

S

SCL

SDA

SLA

SMT

SV

I²C Clock Input

I²C Data Input/Output

Slave Address

With Schmitt Trigger

nSET Value

T

TS

Temperature Sensor

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V

Vref

Voltage Reference

W

WOSMT

WS

Without Schmitt Trigger

Wake and Sleep Controller

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Revision History

Revision

Date

Description

3.0

17-Jun-2021

Final version

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Status Definitions

Revision Datasheet Status

Product Status

Definition

1.<n>

Target

Development

This datasheet contains the design specifications for product development.

Specifications may change in any manner without notice.

2.<n>

Preliminary

Qualification

Production

This datasheet contains the specifications and preliminary characterization

data for products in pre-production. Specifications may be changed at any

time without notice in order to improve the design.

3.<n>

4.<n>

Final

This datasheet contains the final specifications for products in volume

production. The specifications may be changed at any time in order to

improve the design, manufacturing and supply. Major specification

changes are communicated via Customer Product Notifications. Datasheet

changes are communicated via www.dialog-semiconductor.com.

Obsolete

Archived

This datasheet contains the specifications for discontinued products. The

information is provided for reference only.

Disclaimer

Unless otherwise agreed in writing, the Dialog Semiconductor products (and any associated software) referred to in this document are not designed, authorized or warranted

to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of a Dialog Semiconductor product (or

associated software) can reasonably be expected to result in personal injury, death or severe property or environmental damage. Dialog Semiconductor and its suppliers

accept no liability for inclusion and/or use of Dialog Semiconductor products (and any associated software) in such equipment or applications and therefore such inclusion

and/or use is at the customer's own risk.

Information in this document is believed to be accurate and reliable. However, Dialog Semiconductor does not give any representations or warranties, express or implied, as

to the accuracy or completeness of such information. Dialog Semiconductor furthermore takes no responsibility whatsoever for the content in this document if provided by any

information source outside of Dialog Semiconductor.

Dialog Semiconductor reserves the right to change without notice the information published in this document, including, without limitation, the specification and the design of

the related semiconductor products, software and applications. Notwithstanding the foregoing, for any automotive grade version of the device, Dialog Semiconductor

reserves the right to change the information published in this document, including, without limitation, the specification and the design of the related semiconductor products,

software and applications, in accordance with its standard automotive change notification process.

Applications, software, and semiconductor products described in this document are for illustrative purposes only. Dialog Semiconductor makes no representation or warranty

that such applications, software and semiconductor products will be suitable for the specified use without further testing or modification. Unless otherwise agreed in writing,

such testing or modification is the sole responsibility of the customer and Dialog Semiconductor excludes all liability in this respect.

Nothing in this document may be construed as a license for customer to use the Dialog Semiconductor products, software and applications referred to in this document. Such

license must be separately sought by customer with Dialog Semiconductor.

All use of Dialog Semiconductor products, software and applications referred to in this document are subject to Dialog Semiconductor's Standard Terms and Conditions

of Sale, available on the company website (www.dialog-semiconductor.com) unless otherwise stated.

Dialog, Dialog Semiconductor and the Dialog logo are trademarks of Dialog Semiconductor Plc or its subsidiaries. All other product or service names and marks are

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Contacting Dialog Semiconductor

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199

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型号：	SLG46855-AP
厂家：	Dialog Semiconductor
描述：	Auto Grade GreenPAK Programmable Mixed-Signal Matrix
文件：	总199页 (文件大小：2424K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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