SLG46880 [DIALOG]
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous State Machine and Dual Supply;
| 型号： | SLG46880 |
| 厂家： | 
Dialog Semiconductor |
| 描述： | GreenPAK Programmable Mixed-Signal Matrix with Asynchronous State Machine and Dual Supply |
| 文件： | 总353页 (文件大小：4101K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
General Description
The GPAK product family is based around Dialog Semiconductor's proprietary Zero Static Power ASM (Asynchronous State
Machine). This machine is fault tolerant and operates continuously over a wide voltage range with very low latency. The
SLG46880/81 provides a small, low power component for commonly used Mixed-Signal functions. The user creates their
circuit design by programming the one time Non-Volatile Memory (NVM) to configure the interconnect logic, the IO Pins, and
the macrocells of the SLG46880/81. This highly versatile device allows a wide variety of Mixed-Signal functions to be designed
within a very small, low power single integrated circuit.
Key Features
Two High Speed General Purpose Rail-to-Rail Analog
Comparators (ACMPxH)
Two Low Power General Purpose Rail-to-Rail Analog
Comparators (ACMPxL)
Crystal Oscillator
Analog Temperature Sensor
Power-On Reset
Wide Range Power Supply
Two Voltage References
2.5 V (±8 %) to 5 V (±10 %) VDD
2.5 V (±8 %) to 5 V (±10 %) VDD2 (VDD2 ≤ VDD) for
SLG46880
Two Vref Outputs
Twelve Combination Function Macrocells
One Selectable DFF/LATCH or 2-bit LUT
Four Selectable DFF/LATCHES or 3-bit LUTs
One Selectable Pipe Delay or Ripple Counter, or 3-bit
LUT
1 V (±5 %) to 1.8 V (±10%) VDD2 for SLG46881
Operating Temperature Range: -40 °C to 85 °C
RoHS Compliant/Halogen-Free
32-pin STQFN: 4 mm x 4 mm x 0.55 mm, 0.4 mm pitch
One Selectable Programmable Pattern Generator or
2-bit LUT
Four Selectable 8-bit CNT/DLYs or 3-bit LUTs
One Selectable 16-bit CNT/DLY or 4-bit LUT
Asynchronous State Machine
Twelve States
Four Dynamic Memory Macrocells
f(1) Computation Macrocell with Dedicated ACMP
Serial Communications
I2C Protocol Interface
Programmable Delay with Edge Detector Output
Deglitch Filter or Edge Detector
Three Oscillators
2.048 kHz Oscillator
2.048 MHz Oscillator
25 MHz Oscillator
Applications
Personal Computers and Servers
PC Peripherals
Consumer Electronics
Data Communications Equipment
Handheld and Portable Electronics
Smartphones and Fitness Bands
Notebook and Tablet PCs
Datasheet
25-Feb-2021
Revision 3.12
1 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Contents
General Description.................................................................................................................................................................1
Key Features.............................................................................................................................................................................1
Applications..............................................................................................................................................................................1
1 Block Diagram ......................................................................................................................................................................9
2 Pinout ..................................................................................................................................................................................10
2.1 Pin Configuration - STQFN- 32L .........................................................................................................................10
3 Characteristics ...................................................................................................................................................................12
3.1 Absolute Maximum Ratings .................................................................................................................................12
3.2 Electrostatic Discharge Ratings ...........................................................................................................................12
3.3 Recommended Operating Conditions .................................................................................................................12
3.4 Electrical Characteristics ......................................................................................................................................13
3.5 Timing Characteristics ..........................................................................................................................................23
3.6 Oscillator Characteristics .....................................................................................................................................27
3.7 Analog Comparator Characteristics ....................................................................................................................29
3.8 Analog Temperature Sensor Characteristics .......................................................................................................31
4 User Programmability ........................................................................................................................................................34
5 IO Pins .................................................................................................................................................................................35
5.1 IO Pins .................................................................................................................................................................35
5.2 Pull-Up/Down Resistors .......................................................................................................................................35
5.3 100 ns Debounce Delay .......................................................................................................................................35
5.4 Fast Pull-up/down during Power-up .....................................................................................................................35
5.5 Digital Input Latch ................................................................................................................................................35
5.6 GPO Output Skew ................................................................................................................................................36
5.7 Ultra-Low Power Digital Input (SLG46881 only) ..................................................................................................36
5.8 GPI IO Structure (VDD) ........................................................................................................................................37
5.9 GPI with Input Latch IO Structure (VDD) .............................................................................................................39
5.10 GPI with I2C Mode IO Structure (VDD) ...............................................................................................................41
5.11 GPIO with Matrix OE IO Structure (VDD or VDD2) ..............................................................................................43
5.12 GPIO with Matrix OE and Input Latch IO Structure (VDD or VDD2) ....................................................................45
5.13 GPI with Input Latch and Crystal Input IO Structure (VDD) ................................................................................47
5.14 GPO Register OE IO Structure (VDD or VDD2) ...................................................................................................49
5.15 IO Typical Performance .....................................................................................................................................50
6 Connection Matrix ..............................................................................................................................................................53
6.1 Matrix Input Table ................................................................................................................................................54
6.2 Matrix Output Table .............................................................................................................................................55
6.3 Connection Matrix Virtual Inputs ..........................................................................................................................58
6.4 Connection Matrix Virtual Outputs .......................................................................................................................58
7 Combination Function Macrocells ....................................................................................................................................59
7.1 2-Bit LUT or D Flip-Flop Macrocells .....................................................................................................................59
7.2 2-bit LUT or Programmable Pattern Generator ....................................................................................................61
7.3 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells .............................................................................................63
7.4 3-Bit LUT or Pipe Delay/Ripple Counter Macrocell ..............................................................................................69
7.5 3-Bit LUT or 8-Bit Counter/Delay Macrocells .......................................................................................................73
7.6 CNT/DLY/FSM Timing Diagrams .........................................................................................................................78
7.7 4-Bit LUT or 16-Bit Counter/Delay Macrocell .......................................................................................................87
7.8 Wake and Sleep Controller ..................................................................................................................................90
8 Analog Comparators ..........................................................................................................................................................95
8.1 ACMP0H Block Diagram .....................................................................................................................................96
8.2 ACMP1H Block Diagram .....................................................................................................................................97
8.3 ACMP2L Block Diagram .....................................................................................................................................98
8.4 ACMP3L Block Diagram .....................................................................................................................................99
8.5 ACMP Typical Performance ...............................................................................................................................100
9 Programmable Delay/Edge Detector ..............................................................................................................................104
9.1 Programmable Delay Timing Diagram - Edge Detector Output .........................................................................104
10 Additional Logic Function .............................................................................................................................................105
Datasheet
25-Feb-2021
Revision 3.12
2 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
10.1 Deglitch Filter/Edge Detector ...........................................................................................................................105
11 Voltage Reference ..........................................................................................................................................................106
11.1 Voltage Reference Overview ...........................................................................................................................106
11.2 Vref Selection Table ........................................................................................................................................106
11.3 Truth Table for Vref0 Buffer and Output Switch Control ..................................................................................107
11.4 Truth Table for Vref1 Buffer and Output Switch Control ..................................................................................107
11.5 Vref Block Diagram .........................................................................................................................................108
11.6 Vref Load Regulation .......................................................................................................................................109
12 Clocking ..........................................................................................................................................................................111
12.1 General Description .........................................................................................................................................111
12.2 Oscillator0 (2.048 kHz) .....................................................................................................................................112
12.3 Oscillator1 (2.048 MHz) ...................................................................................................................................113
12.4 Oscillator2 (25 MHz) ........................................................................................................................................114
12.5 Clock Scheme ..................................................................................................................................................114
12.6 Crystal Oscillator ..............................................................................................................................................116
12.7 External Clocking .............................................................................................................................................116
12.8 Oscillators Power-On Delay .............................................................................................................................117
12.9 Oscillators Accuracy .........................................................................................................................................119
13 Power-On Reset ..............................................................................................................................................................122
13.1 General Operation ............................................................................................................................................122
13.2 POR Sequence ................................................................................................................................................123
13.3 Macrocells Output States During POR Sequence ...........................................................................................123
14 Asynchronous State Machine Subsystem ...................................................................................................................126
14.1 ASM Subsystem Overview ...............................................................................................................................126
14.2 ASM Subsystem Input Signals .........................................................................................................................128
14.3 ASM Subsystem Output Signals ......................................................................................................................131
14.4 Basic ASM_Subsystem Timing ........................................................................................................................133
14.5 ASM Power Considerations .............................................................................................................................134
14.6 Asynchronous State Machines vs. Synchronous State Machines ...................................................................135
14.7 ASM Special Case Timing Considerations ......................................................................................................135
15 Asynchronous State Machine Macrocell .....................................................................................................................141
15.1 Asynchronous State Machine Overview ..........................................................................................................141
15.2 ASM Macrocell Input Signals ...........................................................................................................................142
15.3 ASM Logical vs. Physical Design .....................................................................................................................145
16 Dynamic Memory Macrocell ..........................................................................................................................................147
16.1 Dynamic Memory Macrocell Overview .............................................................................................................147
16.2 DM0_0 and DM0_1 Macrocell Architecture .....................................................................................................148
16.3 DM1_0 and DM1_1 Macrocell Architecture .....................................................................................................149
16.4 DMx_x Macrocell Input Signals ........................................................................................................................150
16.5 DMx_x Macrocell Output Signals .....................................................................................................................152
17 f(1) Computation Macrocell ...........................................................................................................................................154
17.1 f(1) Computation Macrocell Overview ..............................................................................................................154
17.2 f(1) Computation Macrocell Architecture .........................................................................................................155
17.3 f(1) Computation Macrocell Input Signals ........................................................................................................155
17.4 f(1) Computation Macrocell Output Signals .....................................................................................................157
17.5 f(1) Command Registers ..................................................................................................................................157
17.6 f(1) Typical Performance ..................................................................................................................................164
18 Matrix Interface Macrocells ...........................................................................................................................................165
18.1 MI0, MI1, and MI2 Macrocell Architecture ........................................................................................................165
18.2 MIx Macrocell Input Signals .............................................................................................................................166
18.3 MIx Macrocell Output Signals ..........................................................................................................................166
19 I2C Serial Communications Macrocell ..........................................................................................................................167
19.1 I2C Serial Communications Macrocell Overview ..............................................................................................167
19.2 I2C Serial Communications Device Addressing ...............................................................................................167
19.3 I2C Serial General Timing ................................................................................................................................168
19.4 I2C Serial Communications Commands ...........................................................................................................168
19.5 I2C Serial Command Register Map ..................................................................................................................172
Datasheet
25-Feb-2021
Revision 3.12
3 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
19.6 I2C Additional Options ......................................................................................................................................173
20 Analog Temperature Sensor .........................................................................................................................................176
21 Register Definitions .......................................................................................................................................................179
21.1 Register Map ....................................................................................................................................................179
22 Package Top Marking System Definition ....................................................................................................................343
23 Package Information ......................................................................................................................................................344
23.1 STQFN Handling ..............................................................................................................................................345
23.2 Soldering Information .......................................................................................................................................345
24 Ordering Information .....................................................................................................................................................345
24.1 Tape and Reel Specifications ..........................................................................................................................345
24.2 Carrier Tape Drawing and Dimensions ............................................................................................................345
25 Layout Guidelines ..........................................................................................................................................................347
Glossary................................................................................................................................................................................348
Revision History ..................................................................................................................................................................351
Datasheet
25-Feb-2021
Revision 3.12
4 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Figures
Figure 1: Block Diagram............................................................................................................................................................ 9
Figure 2: Steps to Create a Custom GreenPAK Device.......................................................................................................... 34
Figure 3: Digital Input Latch Timing Diagram.......................................................................................................................... 35
Figure 4: Output Skew Timing Diagram.................................................................................................................................. 36
Figure 5: SLG46880 GPI IO Structure Diagram...................................................................................................................... 37
Figure 6: SLG46881 GPI IO Structure Diagram...................................................................................................................... 38
Figure 7: SLG46880 GPI with Input LATCH Structure Diagram ............................................................................................. 39
Figure 8: SLG46881 GPI with Input LATCH Structure Diagram ............................................................................................. 40
Figure 9: SLG46880 GPI with I2C Mode IO Structure Diagram .............................................................................................. 41
Figure 10: SLG46881 GPI with I2C Mode IO Structure Diagram ............................................................................................ 42
Figure 11: SLG46880 GPIO with Matrix OE IO Structure Diagram......................................................................................... 43
Figure 12: SLG46881 GPIO with Matrix OE IO Structure Diagram......................................................................................... 44
Figure 13: SLG46880 GPIO with Matrix OE and Input LATCH IO Structure Diagram............................................................ 45
Figure 14: SLG46881 GPIO with Matrix OE and Input LATCH IO Structure Diagram............................................................ 46
Figure 15: SLG46880 GPI with Input LATCH and Crystal Input IO Structure Diagram .......................................................... 47
Figure 16: SLG46881 GPI with Input LATCH and Crystal Input IO Structure Diagram .......................................................... 48
Figure 17: SLG46880/81 GPO Register OE IO Structure Diagram ........................................................................................ 49
Figure 18: Typical High Level Output Current vs. High Level Output Voltage at T = 25 °C.................................................... 50
Figure 19: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 °C, Full Range................... 50
Figure 20: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 °C ...................................... 51
Figure 21: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 °C, Full Range................... 51
Figure 22: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 °C ...................................... 52
Figure 23: Connection Matrix.................................................................................................................................................. 53
Figure 24: Connection Matrix Example................................................................................................................................... 53
Figure 25: 2-bit LUT0 or DFF0................................................................................................................................................ 59
Figure 26: DFF Polarity Operations......................................................................................................................................... 61
Figure 27: 2-bit LUT1 or PGen................................................................................................................................................ 62
Figure 28: PGen Timing Diagram............................................................................................................................................ 62
Figure 29: 3-bit LUT0 or DFF1................................................................................................................................................ 64
Figure 30: 3-bit LUT1 or DFF2................................................................................................................................................ 65
Figure 31: 3-bit LUT2 or DFF3................................................................................................................................................ 65
Figure 32: 3-bit LUT3 or DFF4................................................................................................................................................ 66
Figure 33: DFF Polarity Operations with nReset..................................................................................................................... 68
Figure 34: DFF Polarity Operations with nSet......................................................................................................................... 69
Figure 35: 3-bit LUT8/Pipe Delay/Ripple Counter................................................................................................................... 71
Figure 36: Example: Ripple Counter Functionality.................................................................................................................. 72
Figure 37: 3-bit LUT4 or CNT/DLY1........................................................................................................................................ 74
Figure 38: 3-bit LUT5 or CNT/DLY2........................................................................................................................................ 75
Figure 39: 3-bit LUT6 or CNT/DLY3........................................................................................................................................ 75
Figure 40: 3-bit LUT7 or CNT/DLY4........................................................................................................................................ 76
Figure 41: Delay Mode Timing Diagram, Edge Select: Both, Counter Data: 3 ....................................................................... 78
Figure 42: Delay Mode Timing Diagram for Different Edge Select Modes.............................................................................. 79
Figure 43: Counter Mode Timing Diagram without Two DFFs Synced Up ............................................................................. 79
Figure 44: Counter Mode Timing Diagram with Two DFFs Synced Up .................................................................................. 80
Figure 45: One-Shot Function Timing Diagram....................................................................................................................... 80
Figure 46: Frequency Detection Mode Timing Diagram.......................................................................................................... 81
Figure 47: Edge Detection Mode Timing Diagram.................................................................................................................. 82
Figure 48: Delayed Edge Detection Mode Timing Diagram.................................................................................................... 83
Figure 49: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP = 0) for Counter Data = 3.... 84
Figure 50: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced On, UP = 0) for Counter Data = 3 ........ 84
Figure 51: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP = 1) for Counter Data = 3.... 85
Figure 52: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced On, UP = 1) for Counter Data = 3 ........ 85
Figure 53: Counter Value, Counter Data = 3........................................................................................................................... 86
Figure 54: 4-bit LUT0 or CNT/DLY0........................................................................................................................................ 88
Figure 55: WS Controller......................................................................................................................................................... 90
Datasheet
25-Feb-2021
Revision 3.12
5 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Figure 56: Wake/Sleep Timing Diagram, Normal Wake Mode, Counter Reset is Used ......................................................... 91
Figure 57: Wake/Sleep Timing Diagram, Short Wake Mode, Counter Reset is Used ............................................................ 91
Figure 58: Wake/Sleep Timing Diagram, Normal Wake Mode, Counter Set is Used ............................................................. 92
Figure 59: Wake/Sleep Timing Diagram, Short Wake Mode, Counter Set is Used ................................................................ 92
Figure 60: ACMP0H Block Diagram........................................................................................................................................ 96
Figure 61: ACMP1H Block Diagram........................................................................................................................................ 97
Figure 62: ACMP2L Block Diagram ........................................................................................................................................ 98
Figure 63: ACMP3L Block Diagram ........................................................................................................................................ 99
Figure 64: Typical Propagation Delay vs. Vref for ACMPxH at T = 25 °C, Gain = 1, Buffer - Disabled, Hysteresis = 0 ....... 100
Figure 65: Typical Propagation Delay vs. Vref for ACMPxL at T = 25 °C, Gain = 1, Buffer - Disabled, Hysteresis = 0........ 100
Figure 66: ACMPxH Power-On Delay vs. VDD ..................................................................................................................................................... 101
Figure 67: ACMPxL Power-On Delay vs. VDD...................................................................................................................................................... 101
Figure 68: ACMPxH Input Offset Voltage vs. Vref at T = -40 °C to 85 °C, Input Buffer Disabled......................................... 102
Figure 69: ACMPxL Input Offset Voltage vs. Vref at T = -40 °C to 85 °C, Input Buffer Disabled.......................................... 102
Figure 70: ACMP Input Current Source vs. Input Voltage at T = -40 °C to 85 °C, VDD = 3.3 V ............................................ 103
Figure 71: Programmable Delay ........................................................................................................................................... 104
Figure 72: Edge Detector Output .......................................................................................................................................... 104
Figure 73: Deglitch Filter/Edge Detector............................................................................................................................... 105
Figure 74: Voltage Reference Block Diagram....................................................................................................................... 108
Figure 75: Typical Load Regulation, Vref = 320 mV, T = -40 °C to +85 °C, Buffer - Enable................................................. 109
Figure 76: Typical Load Regulation, Vref = 640 mV, T = -40 °C to +85 °C, Buffer - Enable................................................. 109
Figure 77: Typical Load Regulation, Vref = 1280 mV, T = -40 °C to +85 °C, Buffer - Enable............................................... 110
Figure 78: Typical Load Regulation, Vref = 2016 mV, T = -40 °C to +85 °C, Buffer - Enable............................................... 110
Figure 79: Oscillator0 Block Diagram.................................................................................................................................... 112
Figure 80: Oscillator1 Block Diagram.................................................................................................................................... 113
Figure 81: Oscillator2 Block Diagram.................................................................................................................................... 114
Figure 82: Clock Scheme...................................................................................................................................................... 115
Figure 83: Crystal OSC Block Diagram................................................................................................................................. 116
Figure 84: External Crystal Connection................................................................................................................................. 116
Figure 85: Oscillator Startup Diagram................................................................................................................................... 117
Figure 86: Oscillator0 Maximum Power-On Delay vs. VDD at T = 25 °C, OSC0 = 2.048 kHz............................................... 118
Figure 87: Oscillator1 Maximum Power-On Delay vs. VDD at T = 25 °C, OSC1 = 2.048 MHz ............................................. 118
Figure 88: Oscillator2 Maximum Power-On Delay vs. VDD at T = 25 °C, OSC2 = 25 MHz .................................................. 119
Figure 89: Oscillator0 Frequency vs. Temperature, OSC0 = 2.048 kHz............................................................................... 119
Figure 90: Oscillator1 Frequency vs. Temperature, OSC1 = 2.048 MHz.............................................................................. 120
Figure 91: Oscillator2 Frequency vs. Temperature, OSC2 = 25 MHz................................................................................... 120
Figure 92: Oscillators Total Error vs. Temperature............................................................................................................... 121
Figure 93: POR Sequence.................................................................................................................................................... 123
Figure 94: Internal Macrocell States during POR Sequence................................................................................................. 124
Figure 95: Power-Down......................................................................................................................................................... 125
Figure 96: Asynchronous State Machine State Transitions .................................................................................................. 127
Figure 97: Connection Matrix to ASM Subsystem................................................................................................................. 128
Figure 98: ASM Subsystem Input Signals............................................................................................................................. 130
Figure 99: Maximum 7 State Transitions out of a Given State.............................................................................................. 131
Figure 100: Maximum 11 State Transitions into Given State................................................................................................ 131
Figure 101: ASM Subsystem Input Signals........................................................................................................................... 132
Figure 102: State Transition.................................................................................................................................................. 133
Figure 103: State Transition Timing...................................................................................................................................... 134
Figure 104: State Transition.................................................................................................................................................. 134
Figure 105: State Transition Timing and Power Consumption.............................................................................................. 135
Figure 106: State Transition.................................................................................................................................................. 136
Figure 107: State Transition Pulse Input Timing................................................................................................................... 136
Figure 108: State Transition - Competing Inputs................................................................................................................... 137
Figure 109: State Transition Timing - Competing Inputs Indeterminate................................................................................ 137
Figure 110: State Transition Timing - Competing Inputs Determinable ................................................................................ 138
Figure 111: State Transition - Sequential.............................................................................................................................. 138
Figure 112: State Transition - Sequential Timing.................................................................................................................. 139
Datasheet
25-Feb-2021
Revision 3.12
6 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Figure 113: State Transition - Closed Cycling....................................................................................................................... 139
Figure 114: State Transition - Closed Cycling Timing........................................................................................................... 140
Figure 115: Asynchronous State Machine State Transitions ................................................................................................ 141
Figure 116: 12 State ASM Macrocell..................................................................................................................................... 142
Figure 117: ASM Macrocell Input Signals............................................................................................................................. 143
Figure 118: ASM Macrocell Output Signals .......................................................................................................................... 145
Figure 119: DM0_0/DM0_1................................................................................................................................................... 148
Figure 120: DM1_0/DM1_1................................................................................................................................................... 149
Figure 121: DM0_0/DM0_1 Inputs........................................................................................................................................ 150
Figure 122: DM1_0/DM1_1 Inputs........................................................................................................................................ 151
Figure 123: DM0_0/DM0_1 Outputs ..................................................................................................................................... 152
Figure 124: DM1_0/DM1_1 Outputs ..................................................................................................................................... 153
Figure 125: f(1) Computation Macrocell Architecture............................................................................................................ 155
Figure 126: f(1) Computation Macrocell Input Signals .......................................................................................................... 156
Figure 127: f(1) Computation Macrocell Output Signals ....................................................................................................... 157
Figure 128: f(1) Flowchart for Rising Edge Deglitch.............................................................................................................. 162
Figure 129: f(1) Flowchart for Average Function for Captured Data..................................................................................... 163
Figure 130: ACMP4F Power-On Delay vs. VDD................................................................................................................................................... 164
Figure 131: ACMP4F Input Offset Voltage vs. Vref at T = -40 °C to 85 °C, Input Buffer Disabled ....................................... 164
Figure 132: MIx Macrocell Architecture................................................................................................................................. 165
Figure 133: Basic Command Structure................................................................................................................................. 168
Figure 134: I2C General Timing Characteristics.................................................................................................................... 168
Figure 135: Byte Write Command, R/W = 0.......................................................................................................................... 169
Figure 136: Sequential Write Command............................................................................................................................... 169
Figure 137: Current Address Read Command, R/W = 1....................................................................................................... 170
Figure 138: Random Read Command .................................................................................................................................. 170
Figure 139: Sequential Read Command............................................................................................................................... 171
Figure 140: Reset Command Timing .................................................................................................................................... 171
Figure 141: Example of I2C Byte Write Bit Masking.............................................................................................................. 175
Figure 142: Analog Temperature Sensor Structure Diagram................................................................................................ 177
Figure 143: TS Output vs. Temperature, VDD = 2.3 V to 5.5 V............................................................................................. 178
Datasheet
25-Feb-2021
Revision 3.12
7 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Tables
Table 1: Functional Pin Description..........................................................................................................................................10
Table 2: Pin Type Definitions ...................................................................................................................................................11
Table 3: Absolute Maximum Ratings........................................................................................................................................12
Table 4: Electrostatic Discharge Ratings .................................................................................................................................12
Table 5: Recommended Operating Conditions for SLG46880/81............................................................................................12
Table 6: EC for SLG46880 at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted.......................................13
Table 7: EC for SLG46881 at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted.......................................15
Table 8: EC of the I2C Pins at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted ......................................19
Table 9: I2C Pins Timing Characteristics at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted..................20
Table 10: Asynchronous State Machine Specifications at T = 25 °C.......................................................................................20
Table 11: Typical Current Estimated for Each Macrocell at T = -40 °C to +85 °C ...................................................................22
Table 12: Typical Delay Estimated for Each Macrocell at T = 25 °C........................................................................................23
Table 13: Typical Delay Estimated for F(1) at T = 25 °C..........................................................................................................24
Table 14: Programmable Delay Expected Delays and Widths (Typical) T = 25 °C .................................................................25
Table 15: Typical Filter Rejection Pulse Width at T = 25 °C ....................................................................................................26
Table 16: Typical Counter/Delay Offset Measurements at T = 25 °C ......................................................................................26
Table 17: Oscillator0 2.048 kHz Frequency Limits...................................................................................................................27
Table 18: Oscillator0 2.048 kHz Frequency Error (Error Calculated Relative to Nominal Value) ............................................27
Table 19: Oscillator1 2.048 MHz Frequency Limits..................................................................................................................27
Table 20: Oscillator1 2.048 MHz Frequency Error (Error Calculated Relative to Nominal Value) ...........................................27
Table 21: Oscillator2 25 MHz Frequency Limits.......................................................................................................................28
Table 22: Oscillator2 25 MHz Frequency Error (Error Calculated Relative to Nominal Value) ................................................28
Table 23: Oscillators Power-On Delay at T = 25 °C, OSC Power Mode: "Auto Power-On".....................................................28
Table 24: ACMP Specifications at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted................................29
Table 25: TS Output vs Temperature (Output range 1)............................................................................................................31
Table 26: TS Output vs Temperature (Output Range 2) ..........................................................................................................32
Table 27: TS Output Error (Output Range 1)...........................................................................................................................32
Table 28: TS Output Error (Output Range 2)...........................................................................................................................33
Table 29: Matrix Input Table.....................................................................................................................................................54
Table 30: Matrix Output Table..................................................................................................................................................55
Table 31: Connection Matrix Virtual Inputs ..............................................................................................................................58
Table 32: 2-bit LUT0 Truth Table.............................................................................................................................................60
Table 33: 2-bit LUT Standard Digital Functions .......................................................................................................................60
Table 34: 2-bit LUT1 Truth Table.............................................................................................................................................63
Table 35: 2-bit LUT Standard Digital Functions .......................................................................................................................63
Table 36: 3-bit LUT0 Truth Table.............................................................................................................................................67
Table 37: 3-bit LUT1 Truth Table.............................................................................................................................................67
Table 38: 3-bit LUT2 Truth Table.............................................................................................................................................67
Table 39: 3-bit LUT3 Truth Table.............................................................................................................................................67
Table 40: 3-bit LUT Standard Digital Functions .......................................................................................................................67
Table 41: 3-bit LUT8 Truth Table.............................................................................................................................................72
Table 42: 3-bit LUT4 Truth Table.............................................................................................................................................77
Table 43: 3-bit LUT5 Truth Table.............................................................................................................................................77
Table 44: 3-bit LUT6 Truth Table.............................................................................................................................................77
Table 45: 3-bit LUT7 Truth Table.............................................................................................................................................77
Table 46: 4-bit LUT0 Truth Table.............................................................................................................................................89
Table 47: 4-bit LUT Standard Digital Functions .......................................................................................................................89
Table 48: WS Register Settings...............................................................................................................................................94
Table 49: Vref Selection Table...............................................................................................................................................106
Table 50: VrefO0 Truth Table.................................................................................................................................................107
Table 51: VrefO1 Truth Table.................................................................................................................................................107
Table 52: Oscillator Operation Mode Configuration Settings.................................................................................................111
Table 53: External Components Selection Table...................................................................................................................116
Table 54: Read/Write Protection Options...............................................................................................................................172
Table 55: ASM Current State Bits Configuration....................................................................................................................173
Table 56: Register Map..........................................................................................................................................................179
Datasheet
25-Feb-2021
Revision 3.12
8 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
1
Block Diagram
VDD
GPO7
GND1
GPO6
GPO5
GPIO11
GPIO10
GPIO9
GPI7
GPI6
GPO0
Temp
Sensor
Crystal
Osc
Combination Function Macrocells
Vref
POR
GPIO0
3bit
LUT3_0
or DFF1
2-bit
LUT2_0
or DFF0
2-bit
LUT2_1
or PGen
Additional Logic
Function
FILTER with
Edge Detect
GPIO1
GPI5
GPI4
3-bit
3-bit
LUT3_3
or DFF4
3-bit
LUT3_1
or DFF2
LUT3_2
or DFF3
ACMP2L
ACMP3L
ACMP0H
3-bit
LUT3_4 or
CNT/DLY1
3-bit
LUT3_5 or
CNT/DLY2
3-bit
LUT3_6 or
CNT/DLY3
Programmable
Delay
GPIO2
ACMP1H
GPI0
3-bit
LUT3_7 or
CNT/DLY4
4-bit
LUT4_0 or
CNT/DLY0
3-bitLUT3_8
or Pipe
Delay/Ripple
I2C Serial
Communication
GPIO8
GPIO7
GPIO6
ASM Subsystem
GPI1
DM0_0
DM1_0
f(1)
DM0_1
Oscillators
12
State
ASM
DM1_1
ACMP4F
2.048
kHz
2.048
MHz
25
MHz
GPI2/SDA
GPI3/SCL
GPIO3
GPO4
GPIO5
GPO1
GPIO4
GPO2
VDD2
GND
GPO3
Figure 1: Block Diagram
Datasheet
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Revision 3.12
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CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
2
Pinout
2.1 PIN CONFIGURATION - STQFN- 32L
31 30 29
26 25
24
32
28 27
GPO0
GPI7
1
GPIO0
2
23
22
21
20
19
GPI6
GPI5
GPIO1
GPIO2
3
4
5
GPI4
TP
GPI0
GPIO8
GPIO7
GPIO6
GPO4
6
7
GPI1
GPI2/SDA
GPI3/SCL
18
17
8
9
16
10 11 12 13 14 15
Legend:
TP- Thermal Pad
GPI - General Purpose Input
STQFN-32
(Top View)
GPO - General Purpose Output
GPIO - General Purpose Input/
Output
Table 1: Functional Pin Description
STQFN
Pin Name Functions
Pin #
1
GPO0
General Purpose Output or ACMP4F Input 1 or ASM1 output
2
3
4
GPIO0
GPIO1
GPIO2
General Purpose IO or ACMP4F Input 2
General Purpose IO or ACMP4F Input 3
General Purpose IO or VrefO1 or Din LATCH (en1)
5
GPI0
GPI1
General Purpose Input or Din LATCH (en0)/EXT_CLK0
6
General Purpose Input or Din LATCH (en0)/EXT_CLK1/Vref IN
7
GPI2/SDA General Purpose Input/I2C SDA
GPI3/SCL General Purpose Input/I2C SCL
8
9
GPIO3
GPIO4
GPIO5
GPO1
GPO2
GND
General Purpose IO or Din LATCH (en1)
General Purpose IO or I2C exp0 output
General Purpose IO or I2C exp1 output
General Purpose Output or ASM2 output
General Purpose Output or ASM3 output
Ground
10
11
12
13
14
15
16
VDD2
Power Supply
GPO3
General Purpose Output or ASM4 output
Datasheet
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Revision 3.12
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CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 1: Functional Pin Description(Continued)
STQFN
Pin Name Functions
Pin #
17
18
19
20
21
22
23
24
25
GPO4
GPIO6
GPIO7
GPIO8
GPI4
General Purpose Output or ASM5 output
General Purpose IO or Din LATCH (en1) or I2C exp2 output
General Purpose IO or Din LATCH (en1) or I2C exp3 output
General Purpose IO or ACMP4F Input 7
General Purpose Input (XTAL IN) or Din LATCH (en0)/EXT_CLK2
General Purpose Input (XTAL OUT) or Din LATCH (en0)/EXT_CLK3
General Purpose Input or ACMP4F Input 4
GPI5
GPI6
GPI7
General Purpose Input or ACMP4F Input 5
GPIO9
General Purpose IO or ACMP4F Input 6 or VrefO0
26
27
28
GPIO10 General Purpose IO or ACMP0H
GPIO11
GPO5
General Purpose IO or ACMP1H
General Purpose Output or ACMP2L or ASM6 output
29
30
31
GPO6
GND
VDD
General Purpose Output or ACMP3L or ASM7 output
Ground
Power Supply
32
GPO7
TP
General Purpose Output or ACMP4F Input 0 or ASM0 output
Thermal Pad. Must be connected to GND externally
TP
Table 2: Pin Type Definitions
Pin Type
VDD
Description
Power Supply
GPI
General Purpose Input
General Purpose Input/Output
General Purpose Output
Ground
GPIO
GPO
GND
Datasheet
25-Feb-2021
Revision 3.12
11 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
3
Characteristics
3.1 ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, so functional operation of the device at these or any other conditions beyond those indicated in the operational
sections of the specification are not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect
device reliability.
Table 3: Absolute Maximum Ratings
Parameter
Supply Voltage on VDD relative to GND
DC Input Voltage
Min
Max
Unit
V
-0.3
7
GND - 0.5 V VDD + 0.5 V
V
Maximum Average or DC Current
(Through VDD or GND pin)
--
90
mA
Current at Input Pin
Input Leakage Current (Absolute Value)
Storage Temperature Range
Junction Temperature
-1.0
--
1.0
1000
150
mA
nA
°C
-65
--
150
°C
Moisture Sensitivity Level
1
3.2 ELECTROSTATIC DISCHARGE RATINGS
Table 4: Electrostatic Discharge Ratings
Parameter
Min
2000
1300
Max
--
Unit
V
ESD Protection (Human Body Model)
ESD Protection (Charged Device Model)
--
V
3.3 RECOMMENDED OPERATING CONDITIONS
Table 5: Recommended Operating Conditions for SLG46880/81
Parameter
Condition
Min
2.3
Max
5.5
Unit
V
Supply Voltage (VDD
)
Supply Voltage 2 (VDD2
Supply Voltage 2 (VDD2
Operating Temperature
)
)
VDD2 ≤ VDD for SLG46880
VDD2 ≤ VDD for SLG46881
2.3
5.5
V
0.95
-40
1.98
85
V
°C
Maximal Voltage Applied to any PIN in High
Impedance State
VDD+0.3
(Note 1)
--
0.1
0
V
µF
V
Capacitor Value at VDD
--
Allowable Input Voltage at Analog
Pins
Analog Input Common Mode Range
VDD
Note 1 GPIs 0, 1, 2, 3, 4, 5, 6, 7, GPIOs 0, 1, 2, 3, 8, 9, 10, 11, GPOs 0, 5, 6, 7 are powered from VDD and GPIOs 4, 5, 6, 7,
GPOs 1, 2, 3, 4 are powered from VDD2
Datasheet
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Revision 3.12
12 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
3.4 ELECTRICAL CHARACTERISTICS
Table 6: EC for SLG46880 at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted
Parameter Description
Condition
Min
Typ
Max
Unit
0.7x
VDD
(Note 1)
VDD+
0.3
(Note 1)
Logic Input (Note 2)
--
V
0.8x
VDD
(Note 1)
VDD+
0.3
(Note 1)
VIH
HIGH-Level Input Voltage
Logic Input with Schmitt Trigger
Low-Level Logic Input (Note 2)
Logic Input (Note 2)
--
--
--
V
V
V
VDD
+
1.25
0.3
(Note 1)
0.3x
VDD
(Note 1)
GND-
0.3
0.2x
VDD
(Note 1)
GND-
0.3
VIL
LOW-Level Input Voltage
Logic Input with Schmitt Trigger
--
--
V
V
GND-
0.3
Low-Level Logic Input (Note 2)
0.5
VDD = 2.5 V ± 8 %
VDD = 3.3 V ± 10 %
VDD = 5 V ± 10 %
0.32
0.36
0.46
0.43
0.46
0.58
0.56
0.57
0.74
V
V
V
Schmitt Trigger Hysteresis
Voltage
VHYS
Push-Pull, IOH = 100 µA, 1x Drive,
VDD = 2.5 V ± 8 % (Note 1)
2.286
2.704
4.154
2.294
2.857
4.329
--
2.292
2.790
4.247
2.297
2.896
4.373
0.006
0.158
0.212
0.003
0.079
0.099
0.003
0.063
0.079
--
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Push-Pull, IOH = 3 mA, 1x Drive,
VDD =VDD2 = 3.3 V ± 10 % (Note 1)
--
Push-Pull, IOH = 5 mA, 1x Drive,
VDD = VDD2 = 5 V ± 10 % (Note 1)
--
VOH
HIGH-Level Output Voltage
Push-Pull, IOH = 100 µA, 2x Drive,
VDD = 2.5 V ± 8 % (Note 1)
--
Push-Pull, IOH = 3 mA, 2x Drive,
VDD = VDD2 = 3.3 V ± 10 % (Note 1)
--
Push-Pull, IOH = 5 mA, 2x Drive,
VDD = VDD2 = 5 V ± 10 % (Note 1)
--
Push-Pull, IOL= 100 µA, 1x Drive,
VDD = VDD2 = 2.5 V ± 8 % (Note 1)
0.025
0.217
0.297
0.013
0.107
0.136
0.011
0.087
0.114
Push-Pull, IOL = 3 mA,1x Drive,
VDD = VDD2 = 3.3 V ± 10 % (Note 1)
--
Push-Pull, IOL= 5 mA, 1x Drive,
VDD = VDD2 = 5 V ± 10 % (Note 1)
--
Push-Pull, IOL = 100 µA, 2x Drive,
VDD = VDD2 = 2.5 V ± 8 % (Note 1)
--
Push-Pull, IOL= 3 mA, 2x Drive,
VDD = VDD2 = 3.3 V ± 10 % (Note 1)
VOL
LOW-Level Output Voltage
--
Push-Pull, IOL = 5 mA, 2x Drive,
VDD = VDD2 = 5 V ± 10 % (Note 1)
--
NMOS OD, IOL = 100 µA, 1x Drive,
VDD = VDD2 = 2.5 V ± 8 % (Note 1)
--
NMOS OD, IOL = 3 mA, 1x Drive,
VDD = VDD2 = 3.3 V ± 10 % (Note 1)
--
NMOS OD, IOL = 5 mA, 1x Drive,
VDD = VDD2 = 5 V ± 10 % (Note 1)
--
Datasheet
25-Feb-2021
Revision 3.12
13 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 6: EC for SLG46880 at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
Unit
NMOS OD, IOL = 100 µA, 2x Drive,
VDD = VDD2 = 2.5 V ± 8 % (Note 1)
--
0.001
0.002
V
NMOS OD, IOL = 3 mA, 2x Drive,
VDD = VDD2 = 3.3 V ± 10 % (Note 1)
VOL
LOW-Level Output Voltage
--
0.033
0.041
2.14
0.046
0.061
--
V
NMOS OD, IOL = 5 mA, 2x Drive,
VDD = VDD2 = 5 V ± 10 % (Note 1)
--
V
Push-Pull, VOH = VDD - 0.2, 1x Drive,
VDD = VDD2 = 2.5 V ± 8 % (Note 1)
1.55
5.54
19.89
3.08
10.92
38.89
1.66
5.26
7.15
3.32
10.40
14.06
4.15
12.90
16.98
7.89
24.47
31.20
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Push-Pull, VOH = 2.4 V, 1x Drive,
VDD = VDD2 = 3.3 V ± 10 % (Note 1)
7.48
--
Push-Pull, VOH = 2.4 V, 1x Drive,
VDD = VDD2 = 5 V ± 10 % (Note 1)
24.83
4.21
--
HIGH-Level Output Current
(Note 3)
IOH
Push-Pull, VOH = VDD - 0.2, 2x Drive,
VDD = VDD2 = 2.5 V ± 8 % (Note 1)
--
Push-Pull, VOH = 2.4 V, 2x Drive,
VDD = VDD2 = 3.3 V ± 10 % (Note 1)
14.72
48.60
2.19
--
Push-Pull, VOH = 2.4 V, 2x Drive,
VDD = VDD2 = 5 V ± 10 % (Note 1)
--
Push-Pull, VOL = 0.15 V, 1x Drive,
VDD = VDD2 = 2.5 V ± 8 % (Note 1)
--
Push-Pull, VOL = 0.4 V, 1x Drive,
VDD = VDD2 = 3.3 V ± 10 % (Note 1)
7.00
--
Push-Pull, VOL = 0.4 V, 1x Drive,
VDD = VDD2 = 5 V ± 10 % (Note 1)
9.76
--
Push-Pull, VOL = 0.15 V, 2x Drive,
VDD = VDD2 = 2.5 V ± 8 % (Note 1)
4.29
--
Push-Pull, VOL = 0.4 V, 2x Drive,
VDD = VDD2 = 3.3 V ± 10 % (Note 1)
13.69
18.98
5.38
--
Push-Pull, VOL = 0.4 V, 2x Drive,
VDD = VDD2 = 5 V ± 10 % (Note 1)
--
LOW-Level Output Current
(Note 3)
IOL
NMOS OD, VOL = 0.15 V, 1x Drive,
VDD = VDD2 = 2.5 V ± 8 % (Note 1)
--
NMOS OD, VOL = 0.4 V, 1x Drive,
VDD = VDD2 = 3.3 V ± 10 % (Note 1)
17.14
23.70
10.40
33.02
45.10
--
NMOS OD, VOL = 0.4 V, 1x Drive,
VDD = VDD2 = 5 V ± 10 % (Note 1)
--
NMOS OD, VOL = 0.15 V, 2x Drive,
VDD = VDD2 = 2.5 V ± 8 % (Note 1)
--
NMOS OD, VOL = 0.4 V, 2x Drive,
VDD = VDD2 = 3.3 V ± 10 % (Note 1)
--
NMOS OD, VOL = 0.4 V, 2x Drive,
VDD = VDD2 = 5 V ± 10 % (Note 1)
--
TSU
TWR
Startup Time
From VDD rising past PONTHR
--
--
1.13
--
1.72
20
ms
ms
ms
V
NVM Page Write Time
NVM Page Erase Time
Power-On Threshold
TER
--
--
20
PONTHR
VDD Level Required to Start Up the Chip
1.64
1.84
2.11
VDD Level Required to Switch Off the
Chip
POFFTHR Power-Off Threshold
0.98
1.25
1.49
V
Datasheet
25-Feb-2021
Revision 3.12
14 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 6: EC for SLG46880 at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
Unit
1 M for Pull-up: VIN = GND;
for Pull-down: VIN = VDD
0.74
1.04
1.50
MΩ
Pull-up or Pull-down
Resistance
100 k for Pull-up: VIN = GND;
for Pull-down: VIN = VDD
RPULL
87
7
104
132
17
kΩ
10 k For Pull-up: VIN = GND;
for Pull-down: VIN = VDD
10
4
kΩ
CIN
Input Capacitance
pF
Note 1 GPIs 0, 1, 2, 3, 4, 5, 6, 7, GPIOs 0, 1, 2, 3, 8, 9, 10, 11, GPOs 0, 5, 6, 7 are powered from VDD and GPIOs 4, 5, 6, 7,
GPOs 1, 2, 3, 4 are powered from VDD2.
Note 2 No hysteresis.
Note 3 DC or average current through any pin should not exceed value given in Absolute Maximum Conditions.
Table 7: EC for SLG46881 at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted
Parameter Description
Condition
Min
Typ
Max
Unit
0.7x
VDD
VDD
0.3
+
Logic Input (Note 2)
--
V
0.8x
VDD
VDD
0.3
+
Logic Input with Schmitt Trigger
Low-Level Logic Input (Note 2)
Ultra-Low Power Digital Input (Note 2)
Ultra-Low Power Digital Input (Note 2)
Logic Input (Note 2)
--
--
--
--
--
--
--
--
--
V
V
HIGH-Level Input Voltage
(GPIs 0, 1, 2, 3, 4, 5, 6, 7,
GPIOs 0, 1, 2, 3, 8, 9, 10, 11)
VIH1
VIH2
VIL1
VDD
0.3
+
1.25
0.7x
VDD2
VDD2
0.3
+
+
HIGH-Level Input Voltage
(GPIOs 4, 5, 6, 7)
0.7x
VDD2
VDD2
0.3
V
V
V
V
V
V
GND-
0.3
0.3x
VDD
GND-
0.3
0.2x
VDD
Logic Input with Schmitt Trigger
Low-Level Logic Input (Note 2)
Ultra-Low Power Digital Input (Note 2)
Ultra-Low Power Digital Input (Note 2)
LOW-Level Input Voltage
(GPIs 0, 1, 2, 3, 4, 5, 6, 7,
GPIOs 0, 1, 2, 3, 8, 9, 10, 11)
GND-
0.3
0.5
GND-
0.3
0.42x
VDD2
LOW-Level Input Voltage
(GPIOs 4, 5, 6, 7)
GND-
0.3
0.42x
VDD2
VIL2
Schmitt Trigger Hysteresis
Voltage
(GPIs 0, 1, 2, 3, 4, 5, 6, 7,
GPIOs 0, 1, 2, 3, 8, 9, 10, 11)
VDD = 2.5 V ± 8 %
VDD = 3.3 V ± 10 %
VDD = 5 V ± 10 %
0.27
0.32
0.42
0.43
0.46
0.58
0.59
0.59
0.76
V
V
V
VHYS1
Datasheet
25-Feb-2021
Revision 3.12
15 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 7: EC for SLG46881 at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
Unit
Push-Pull, IOH = 100 µA, 1x Drive,
VDD = 2.5 V ± 8 %
2.29
2.49
--
V
Push-Pull, IOH = 3 mA, 1x Drive,
VDD = 3.3 V ± 10 %
2.69
4.14
2.29
2.85
4.32
0.923
1.479
1.780
0.937
1.489
1.789
--
3.11
4.77
--
--
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Push-Pull, IOH = 5 mA, 1x Drive,
VDD = 5 V ± 10 %
HIGH-Level Output Voltage
(GPIOs 0, 1, 2, 3, 8, 9, 10, 11,
GPOs 0, 5, 6, 7)
VOH1
Push-Pull, IOH = 100 µA, 2x Drive,
VDD = 2.5 V ± 8 %
2.50
--
Push-Pull, IOH = 3 mA, 2x Drive,
VDD = 3.3 V ± 10 %
3.21
--
Push-Pull, IOH = 5 mA, 2x Drive,
VDD = 5 V ± 10 %
4.88
--
Push-Pull, IOH = 100 µA, 1x Drive,
VDD2 = 1.0 V ± 5 %
0.957
1.486
1.886
0.966
1.493
1.893
0.006
0.156
0.197
0.003
0.078
0.100
0.003
0.062
0.080
0.001
0.032
0.042
--
Push-Pull, IOH = 100 µA, 1x Drive,
VDD2 = 1.5 V ± 5 %
--
Push-Pull, IOH = 100 µA, 1x Drive,
VDD2 = 1.8 V ± 10 %
--
HIGH-Level Output Voltage
(GPIOs 4, 5, 6, 7, GPOs 1, 2,
3, 4)
VOH2
Push-Pull, IOH = 100 µA, 2x Drive,
VDD2 = 1.0 V ± 5 %
--
Push-Pull, IOH = 100 µA, 2x Drive,
VDD2 = 1.5 V ± 5 %
--
Push-Pull, IOH = 100 µA, 2x Drive,
VDD2 = 1.8 V ± 10 %
--
Push-Pull, IOL= 100 µA, 1x Drive,
VDD = 2.5 V ± 8 %
0.012
0.233
0.295
0.005
0.116
0.151
0.004
0.094
0.122
0.002
0.051
0.067
Push-Pull, IOL = 3 mA,1x Drive,
VDD = 3.3 V ± 10 %
--
Push-Pull, IOL= 5 mA, 1x Drive,
VDD = 5 V ± 10 %
--
Push-Pull, IOL = 100 µA, 2x Drive,
VDD = 2.5 V ± 8 %
--
Push-Pull, IOL= 3 mA, 2x Drive,
VDD = 3.3 V ± 10 %
--
Push-Pull, IOL = 5 mA, 2x Drive,
VDD = 5 V ± 10 %
--
LOW-Level Output Voltage
(GPIOs 0, 1, 2, 3, 8, 9, 10, 11,
GPOs 0, 5, 6, 7)
VOL1
NMOS OD, IOL = 100 µA, 1x Drive,
VDD = 2.5 V ± 8 %
--
NMOS OD, IOL = 3 mA, 1x Drive,
VDD = 3.3 V ± 10 %
--
NMOS OD, IOL = 5 mA, 1x Drive,
VDD = 5 V ± 10 %
--
NMOS OD, IOL = 100 µA, 2x Drive,
VDD = 2.5 V ± 8 %
--
NMOS OD, IOL = 3 mA, 2x Drive,
VDD = 3.3 V ± 10 %
--
NMOS OD, IOL = 5 mA, 2x Drive,
VDD = 5 V ± 10 %
--
Datasheet
25-Feb-2021
Revision 3.12
16 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 7: EC for SLG46881 at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
Unit
Push-Pull, IOL= 100 µA, 1x Drive,
VDD2 = 1.0 V ± 5 %
--
0.015
0.022
V
Push-Pull, IOL= 100 µA, 1x Drive,
VDD2 = 1.5 V ± 5 %
--
--
0.012
0.011
0.007
0.006
0.006
0.015
0.012
0.011
0.007
0.006
0.006
2.37
0.018
0.017
0.011
0.011
0.008
0.022
0.018
0.017
0.011
0.010
0.008
--
V
V
Push-Pull, IOL= 100 µA, 1x Drive,
VDD2 = 1.8 V ± 10 %
Push-Pull, IOL = 100 µA, 2x Drive,
VDD2 = 1.0 V ± 5 %
--
V
Push-Pull, IOL = 100 µA, 2x Drive,
VDD2 = 1.5 V ± 5 %
--
V
Push-Pull, IOL = 100 µA, 2x Drive,
VDD2 = 1.8 V ± 10 %
--
V
LOW-Level Output Voltage
(GPIOs 4, 5, 6, 7, GPOs 1, 2,
3, 4)
VOL2
NMOS OD, IOL = 100 µA, 1x Drive,
VDD2 = 1.0 V ± 5 %
--
V
NMOS OD, IOL = 100 µA, 1x Drive,
VDD2 = 1.5 V ± 5 %
--
V
NMOS OD, IOL = 100 µA, 1x Drive,
VDD2 = 1.8 V ± 10 %
--
V
NMOS OD, IOL = 100 µA, 2x Drive,
VDD2 = 1.0 V ± 5 %
--
V
NMOS OD, IOL = 100 µA, 2x Drive,
VDD2 = 1.5 V ± 5 %
--
V
NMOS OD, IOL = 100 µA, 2x Drive,
VDD2 = 1.8 V ± 10 %
--
V
Push-Pull, VOH = VDD - 0.2, 1x Drive,
VDD = 2.5 V ± 8 %
1.48
5.30
19.27
2.91
10.47
37.75
1.16
2.84
3.55
2.32
5.57
6.99
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Push-Pull, VOH = 2.4 V, 1x Drive,
VDD = 3.3 V ± 10 %
11.12
30.24
4.67
--
Push-Pull, VOH = 2.4 V, 1x Drive,
VDD = 5 V ± 10 %
--
HIGH-Level Output Current
(GPIOs 0, 1, 2, 3, 8, 9, 10, 11,
GPOs 0, 5, 6, 7) (Note 3)
IOH1
Push-Pull, VOH = VDD - 0.2, 2x Drive,
VDD = 2.5 V ± 8 %
--
Push-Pull, VOH = 2.4 V, 2x Drive,
VDD = 3.3 V ± 10 %
21.89
59.04
1.55
--
Push-Pull, VOH = 2.4 V, 2x Drive,
VDD = 5 V ± 10 %
--
Push-Pull, VOH = 2/3 VDD2, 1x Drive,
VDD2 = 1.0 V ± 5 %
--
Push-Pull, VOH = 2/3 VDD2, 1x Drive,
VDD2 = 1.5 V ± 5 %
3.40
--
Push-Pull, VOH = 2/3 VDD2, 1x Drive,
VDD2 = 1.8 V ± 10 %
4.52
--
HIGH-Level Output Current
(GPIOs 4, 5, 6, 7, GPOs 1, 2,
3, 4) (Note 3)
IOH2
Push-Pull, VOH = 2/3 VDD2, 2x Drive,
VDD2 = 1.0 V ± 5 %
3.07
--
Push-Pull, VOH = 2/3 VDD2, 2x Drive,
VDD2 = 1.5 V ± 5 %
6.74
--
Push-Pull, VOH = 2/3 VDD2, 2x Drive,
VDD2 = 1.8 V ± 10 %
8.95
--
Datasheet
25-Feb-2021
Revision 3.12
17 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 7: EC for SLG46881 at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
Unit
Push-Pull, VOL = 0.15 V, 1x Drive,
VDD = 2.5 V ± 8 %
1.58
2.26
--
mA
Push-Pull, VOL = 0.4 V, 1x Drive,
VDD = 3.3 V ± 10 %
4.94
6.65
3.07
9.63
12.86
3.83
11.92
15.81
7.18
22.17
28.68
1.37
3.26
4.09
2.70
6.42
8.08
1.38
3.24
4.08
2.70
6.43
8.09
7.24
9.82
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Push-Pull, VOL = 0.4 V, 1x Drive,
VDD = 5 V ± 10 %
Push-Pull, VOL = 0.15 V, 2x Drive,
VDD = 2.5 V ± 8 %
4.43
Push-Pull, VOL = 0.4 V, 2x Drive,
VDD = 3.3 V ± 10 %
14.18
19.13
5.55
Push-Pull, VOL = 0.4 V, 2x Drive,
VDD = 5 V ± 10 %
LOW-Level Output Current
(GPIOs 0, 1, 2, 3, 8, 9, 10, 11,
IOL1
NMOS OD, VOL = 0.15 V, 1x Drive,
VDD = 2.5 V ± 8 %
GPOs 0, 5, 6, 7) (Note 3)
NMOS OD, VOL = 0.4 V, 1x Drive,
VDD = 3.3 V ± 10 %
17.72
23.84
10.72
34.11
45.34
1.85
NMOS OD, VOL = 0.4 V, 1x Drive,
VDD = 5 V ± 10 %
NMOS OD, VOL = 0.15 V, 2x Drive,
VDD = 2.5 V ± 8 %
NMOS OD, VOL = 0.4 V, 2x Drive,
VDD = 3.3 V ± 10 %
NMOS OD, VOL = 0.4 V, 2x Drive,
VDD = 5 V ± 10 %
Push-Pull, VOL = 1/3 VDD2, 1x Drive,
VDD2 = 1.0 V ± 5 %
Push-Pull, VOL = 1/3 VDD2, 1x Drive,
VDD2 = 1.5 V ± 5 %
4.00
Push-Pull, VOL = 1/3 VDD2, 1x Drive,
VDD2 = 1.8 V ± 10 %
5.27
Push-Pull, VOL = 1/3 VDD2, 2x Drive,
VDD2 = 1.0 V ± 5 %
3.67
Push-Pull, VOL = 1/3 VDD2, 2x Drive,
VDD2 = 1.5 V ± 5 %
7.93
Push-Pull, VOL = 1/3 VDD2, 2x Drive,
VDD2 = 1.8 V ± 10 %
10.44
1.85
LOW-Level Output Current
(GPIOs 4, 5, 6, 7, GPOs 1, 2,
3, 4) (Note 3)
IOL2
NMOS OD, VOL = 1/3 VDD2, 1x Drive,
VDD2 = 1.0 V ± 5 %
NMOS OD, VOL = 1/3 VDD2, 1x Drive,
VDD2 = 1.5 V ± 5 %
4.00
NMOS OD, VOL = 1/3 VDD2, 1x Drive,
VDD2 = 1.8 V ± 10 %
5.27
NMOS OD, VOL = 1/3 VDD2, 2x Drive,
VDD2 = 1.0 V ± 5 %
3.67
NMOS OD, VOL = 1/3 VDD2, 2x Drive,
VDD2 = 1.5 V ± 5 %
7.92
NMOS OD, VOL = 1/3 VDD2, 2x Drive,
VDD2 = 1.8 V ± 10 %
10.44
TSU
Startup Time
From VDD rising past PONTHR
--
1.13
1.84
1.72
2.11
ms
V
PONTHR
Power-On Threshold
VDD Level Required to Start Up the Chip
1.64
Datasheet
25-Feb-2021
Revision 3.12
18 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 7: EC for SLG46881 at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted(Continued)
Parameter Description
Condition
Min
Typ
Max
Unit
VDD Level Required to Switch Off the
Chip
POFFTHR Power-Off Threshold
0.98
1.25
1.49
V
1 M for Pull-up: VIN = GND;
for Pull-down: VIN = VDD
0.85
87
7
1.048
104.4
10.36
1.05
1.32
131
14
MΩ
kΩ
100 k for Pull-up: VIN = GND;
for Pull-down: VIN = VDD
10 k for Pull-up: VIN = GND;
for Pull-down: VIN = VDD
kΩ
Pull-up or Pull-down
Resistance
RPULL
1 M for Pull-up: VIN = GND;
for Pull-down: VIN = VDD2
0.85
88
9
1.35
150
22
MΩ
kΩ
100 k for Pull-up: VIN = GND;
for Pull-down: VIN = VDD2
112.5
10 k for Pull-up: VIN = GND;
for Pull-down: VIN = VDD2
14.14
4
kΩ
CIN
Input Capacitance
pF
Note 1 GPIs 0, 1, 2, 3, 4, 5, 6, 7, GPIOs 0, 1, 2, 3, 8, 9, 10, 11, GPOs 0, 5, 6, 7 are powered from VDD and GPIOs 4, 5, 6, 7,
GPOs 1, 2, 3, 4 are powered from VDD2
.
Note 2 No hysteresis.
Note 3 DC or average current through any pin should not exceed value given in Absolute Maximum Conditions.
Table 8: EC of the I2C Pins at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted
Fast-Mode
Fast-Mode Plus
Parameter Description
Condition
Unit
Min
Max
Min
Max
LOW-level Input
Voltage
VIL
-0.5
0.3VDD
-0.5
0.3 VDD
V
V
V
HIGH-level Input
Voltage
VIH
0.7VDD
0.05VDD
5.5
--
0.7VDD
5.5
--
HysteresisofSchmitt
Trigger Inputs
VHYS
0.05VDD
(Open-Drain or open
collector) at 3mA sink
current
LOW-Level Output
Voltage 1
VOL1
0
0
0.4
0
0
0.4
V
V
VDD > 2 V
(Open-Drain or open
collector) at 2 mA sink
current
LOW-Level Output
Voltage 2
VOL2
0.2VDD
0.2VDD
VDD ≤ 2 V
VOL = 0.4 V, VDD = 2.3 V
VOL = 0.4 V, VDD = 3.0 V
VOL = 0.4 V, VDD = 4.5 V
VOL= 0.6 V
3
3
3
6
--
--
--
--
19.28
20
--
--
--
--
mA
mA
mA
mA
LOW-Level Output
Current (Note 1)
IOL
20
--
Output Fall Time
from VIHmin to VILmax
(Note 1)
14x
(VDD/5.5 V)
10x
(VDD/5.5 V)
tof
250
120
ns
Datasheet
25-Feb-2021
Revision 3.12
19 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 8: EC of the I2C Pins at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted(Continued)
Fast-Mode
Fast-Mode Plus
Parameter Description
Condition
Unit
Min
Max
Min
Max
Pulse Width of
Spikes that must be
suppressed by the
Input Filter
tSP
0
50
0
50
ns
Input Current each
IO Pin
Ii
0.1VDD < VI < 0.9VDDmax
-10
--
+10
10
-10
--
+10
10
µA
Capacitance for
each IO Pin
Ci
pF
Note 1 Does not meet standard I2C specifications: tof = 20x(VDD/5.5 V) (min); For Fast-mode Plus IOL = 20 mA (min) at
VOL = 0.4 V.
Note 2 For Fast-mode Plus SDA pin must be configured as NMOS 2x Open-Drain, see registers [893] in section 21.
Table 9: I2C Pins Timing Characteristics at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted
Fast-Mode
Fast-Mode
Plus
Parameter Description
Condition/Note
Unit
Min
--
Max
400
--
Min
--
Max
1000
--
FSCL
tLOW
tHIGH
Clock Frequency, SCL
kHz
ns
Clock Pulse Width Low
Clock Pulse Width High
1300
600
--
500
260
--
--
--
ns
V
DD = 2.5 V ± 8 %
95
168
157
156
450
Input Filter Spike Suppression
(SCL, SDA)
tI
VDD = 3.3 V ± 10 %
VDD = 5.0 V ± 10 %
--
95
--
ns
--
111
900
--
tAA
Clock Low to Data Out Valid
--
--
ns
ns
Bus Free Time between Stop and
Start
tBUF
1300
--
500
--
tHD_STA
tSU_STA
tHD_DAT
tSU_DAT
tR
Start Hold Time
Start Set-up Time
Data Hold Time
Data Set-up Time
Inputs Rise Time
Inputs Fall Time
Stop Set-up Time
Data Out Hold Time
600
600
0
--
--
260
260
0
--
--
ns
ns
ns
ns
ns
ns
ns
ns
--
--
100
--
--
50
--
--
300
300
--
120
120
--
tF
--
--
tSU_STO
tDH
600
50
260
50
--
--
Note 1 Timing diagram can be found in the Figure 134.
Table 10: Asynchronous State Machine Specifications at T = 25 °C
Parameter Description
Condition
Min
133
96
Typ
Max
Unit
VDD = 2.5 V ± 8 %
VDD = 3.3 V ± 10 %
VDD = 5.0 V ± 10 %
--
277
190
123
Asynchronous State Machine
tst_out_delay
ns
Output Delay Time
70
--
Datasheet
25-Feb-2021
Revision 3.12
20 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 10: Asynchronous State Machine Specifications at T = 25 °C(Continued)
Parameter Description
Condition
Min
--
Typ
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Max
165
70
Unit
VDD = 2.5 V ± 8 %
VDD = 3.3 V ± 10 %
VDD = 5.0 V ± 10 %
VDD = 2.5 V ± 8 %
VDD = 3.3 V ± 10 %
VDD = 5.0 V ± 10 %
VDD = 2.5 V ± 8 %
VDD = 3.3 V ± 10%
VDD = 5.0 V ± 10 %
VDD = 2.5 V ± 8 %
Asynchronous State Machine
Output Transition Time
tst_out
tst_pulse
tst_comp
--
ns
--
46
28
19
12
--
--
Asynchronous State Machine
Input Pulse Acceptance Time
--
ns
ns
ns
ns
--
10
Asynchronous State Machine
Input Compete Time
--
7
--
5
229
162
119
229
162
119
485
330
208
485
330
208
tst_sequen- Asynchronous State Machine
Sequential Output Delay Time
V
DD = 3.3 V ± 10 %
VDD = 5.0 V ± 10 %
DD = 2.5 V ± 8 %
tial_delay
V
tst_dmlatch_ Asynchronous State Machine
VDD = 3.3 V ± 10 %
VDD = 5.0 V ± 10 %
Dynamic Memory Latch Delay
delay
Datasheet
25-Feb-2021
Revision 3.12
21 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 11: Typical Current Estimated for Each Macrocell at T = -40 °C to +85 °C
Parameter
Description Note
Chip Quiescent (I2C enable)
VDD = 2.5 V VDD = 3.3 V VDD = 5.0 V
Unit
µA
0.11
0.10
0.39
4.03
0.13
0.12
0.43
4.16
0.20
0.20
0.53
4.43
Chip Quiescent (I2C disable)
µA
Vref (SourceNone, SourceTempSensor)
Vref (ACMPxH or ACMPxL, 0.32 mV)
µA
µA
ACMP0H, 100 µA disabled, hysteresis
disabled, gain 1 or 0.25, +IN - GPIO10,
Vref = 32 mV
21.21
24.59
34.97
21.59
24.99
35.67
22.87
26.40
38.02
µA
µA
µA
ACMP0H, 100 µA disabled, hysteresis
disabled, gain 1, Buffered +IN - GPIO10,
Vref = 32 mV
ACMP0,1H, 100 µA disabled, hysteresis
disabled, gain 1, +IN - GPIO10, GPIO11,
Vref = 32 mV
ACMP0,1H 100 µA disabled,
ACMP2, 3L, hysteresis disabled,
gain 1, +IN - GPIO10, GPIO11, GPO5,
GPO6, Vref = 32 mV
36.32
36.96
39.37
µA
ACMP0H, 100 µA disabled, hysteresis
disabled, gain 1, +IN - VDD, Vref = 32 mV
37.06
46.59
38.41
48.00
41.99
51.52
µA
µA
ACMP0H, 100 µA enabled, hysteresis
disabled, gain 1, +IN - GPIO10,
Vref = 32 mV
I
Current
ACMP2L, hysteresis disabled, gain 1 or
0.25, +IN - GPO5, Vref = 32 mV
1.61
1.86
1.65
1.91
1.78
2.04
µA
µA
ACMP2,3L, hysteresis disabled, gain 1,
+IN - GPO5, GPO6, Vref = 32 mV
OSC2 25 MHz, pre-divider = 1
OSC2 25 MHz, pre-divider = 4
OSC2 25 MHz, pre-divider = 8
OSC1 2.048 MHz, pre-divider = 1
OSC1 2.048 MHz, pre-divider = 4
OSC1 2.048 MHz, pre-divider = 8
OSC0 2.048 kHz, pre-divider = 1 or 4 or 8
Push-Pull 1x + 4 pF @ 25 kHz
Push-Pull 1x + 4 pF @ 2 MHz
111.45
42.67
30.94
16.20
13.83
13.42
0.39
150.85
54.93
38.56
17.52
14.37
13.83
0.43
5
244.34
84.46
57.16
20.42
15.60
14.78
0.53
µA
µA
µA
µA
µA
µA
µA
µA
µA
0.4
16
22
47
106
Temperature Sensor, range 0.75 to 1.2,
Source Matrix
4.64
4.60
4.15
4.74
4.71
4.41
4.85
4.82
6.73
µA
µA
µA
Temperature Sensor, range 0.62 to 0.99,
Source Matrix or Register
Temperature Sensor, range 0.62 to 0.99,
Source Matrix or GPIO11
Datasheet
25-Feb-2021
Revision 3.12
22 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
3.5 TIMING CHARACTERISTICS
Table 12: Typical Delay Estimated for Each Macrocell at T = 25 °C
VDD = 2.5 V
VDD = 3.3 V
VDD = 5 V
Parameter Description Note
Unit
Rising Falling Rising Falling Rising Falling
19
20
--
20
19
23
--
13
14
--
15
15
16
--
9
10
--
11
11
11
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
DFF Q
DFF nQ
DFF nRESET Q
DFF nRESET nQ
DFF nSET Q
23
23
--
15
15
--
10
10
--
--
--
--
23
21
20
20
18
24
24
21
21
21
20
17
24
24
18
21
17
15
15
14
14
17
17
16
16
15
15
12
18
17
13
15
12
11
10
10
10
12
13
12
11
11
11
8
DFF nSET nQ
DFF1 Second Q
DFF1 Second nQ
LATCH Q
20
21
18
20
23
24
21
21
20
21
18
22
22
16
18
14
14
13
14
16
16
14
15
14
15
12
16
16
11
13
9
9
9
8
LATCH nQ
11
11
9
LATCH nRESET Q
LATCH nRESET nQ
LATCH nSET Q
LATCH nSET nQ
LATCH1 second Q
LATCH1 second nQ
2-bit LUT
10
9
10
8
11
11
7
13
13
9
3-bit LUT
4-bit LUT
DM 2-bit LUT IN0
9
10
DM 3-bit LUT IN0 to 2-bit LUT IN0
DM 3-bit LUT IN0 to CNT
One Shot to 2-bit LUT IN1
52
55
38
39
26
26
ns
tpd
tpd
tpd
tpd
Delay
Delay
Delay
Delay
17
18
41
19
19
42
12
12
29
14
14
30
8
8
9
ns
ns
ns
DM 3-bit LUT IN1 to 2-bit LUT IN0
DM 3-bit LUT IN2 to 2-bit LUT IN0
10
20
20
DM CNT Edge detect to 2-bit LUT IN1
DM CNT Frequency detect to 2-bit
LUT IN1
54
55
38
39
27
27
ns
tpd
tpd
tpd
tpd
Delay
Delay
Delay
Delay
52
44
42
54
44
37
31
29
38
32
25
21
20
26
22
96
ns
ns
ns
DM CNT One Shot to 2-bit LUT IN1
DM CNT Delay to 2-bit LUT IN1
224
152
Low Voltage Digital input to PP 1x
Digital input to with Schmitt Trigger to
PP 1x
35
37
23
26
16
18
ns
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
35
30
--
37
35
30
--
23
21
--
26
24
21
--
16
14
--
18
17
15
--
ns
ns
ns
ns
ns
ns
ns
ns
Digital input to PP 1x
Digital input to PP 2x
PP 1x 3-State (Z to 0)
PP 1x 3-State (Z to 1)
PP 2x 3-State (Z to 0)
PP 2x 3-State (Z to 1)
Digital input to NMOS 1x
Digital input to NMOS 2x
34
--
23
--
16
--
29
--
20
--
14
--
31
--
22
--
15
--
33
32
23
22
16
15
--
--
--
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 12: Typical Delay Estimated for Each Macrocell at T = 25 °C(Continued)
VDD = 2.5 V
VDD = 3.3 V
VDD = 5 V
Parameter Description Note
Unit
Rising Falling Rising Falling Rising Falling
19
24
31
18
29
29
25
24
25
25
24
25
18
--
18
26
26
18
24
31
--
13
17
22
13
21
21
17
17
18
17
17
17
12
--
14
19
19
14
18
23
--
9
12
16
9
10
15
15
10
13
17
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tpd
tw
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Width
Ripple UP CLK CNT Q0
Ripple UP CLK CNT Q1
Ripple UP CLK CNT Q2
Ripple DOWN CLK CNT Q0
Ripple DOWN CLK CNT Q1
Ripple DOWN CLK CNT Q2
Ripple UP nSET CNT Q0
Ripple UP nSET CNT Q1
Ripple UP nSET CNT Q2
Ripple DOWN nSET CNT Q0
Ripple DOWN nSET CNT Q1
Ripple DOWN nSET CNT Q2
PGen CLK
14
15
11
11
12
11
11
12
8
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
18
20
--
13
15
--
10
11
--
--
PGen nRESET (Z to 0)
PGen nRESET (Z to 1)
Pipe Delay Q
22
22
22
165
145
24
242
241
15
16
16
112
101
16
177
160
10
11
11
71
67
12
129
118
22
24
144
164
25
243
241
16
18
101
113
17
179
160
12
13
68
72
11
130
118
Pipe Delay nQ
Filter Q
Filter nQ
Edge detect
Edge detect Delayed
Edge detect
Table 13: Typical Delay Estimated for F(1) at T = 25 °C
VDD = 2.5 V
159
VDD = 3.3 V
111
VDD = 5 V
71
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
tpd
Description
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Delay
Note
Delay 0
424
362
313
672
1070
4264
65
tpd
Delay 1
786
722
tpd
Delay 10
1185
4395
147
1111
4323
101
tpd
Delay 20
tpd
Delay 100
tpd
LOOP without Delay data
LOOP with 0 Delay data
LOOP with 1 Delay data
LOOP with 10 Delay data
LOOP with 20 Delay data
LOOP with 100 Delay data
INV
159
111
72
tpd
424
362
314
672
1071
4263
70
tpd
785
723
tpd
1186
4395
161
1123
4324
111
tpd
tpd
tpd
160
109
69
tpd
AND
161
109
69
tpd
OR
160
109
69
tpd
XOR
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 13: Typical Delay Estimated for F(1) at T = 25 °C(Continued)
VDD = 2.5 V
VDD = 3.3 V
VDD = 5 V
Unit
ns
Parameter
tpd
Description
Delay
Note
322
163
160
161
74
219
110
109
111
52
137
69
69
70
34
41
LOADx
ns
tpd
Delay
OUTx
ns
tpd
Delay
POP
ns
tpd
Delay
PUSH0
ns
tpd
Delay
RESET (Time for OUT0)
RESET (Time to f1 init)
89
61
ns
tpd
Delay
Table 14: Programmable Delay Expected Delays and Widths (Typical) T = 25 °C
Parameter
tw
Description
Note
VDD = 2.5 V VDD = 3.3 V VDD = 5.0 V Unit
Pulse Width, 1 cell mode: (any) edge detect, edge detect output
Pulse Width, 2 cell mode: (any) edge detect, edge detect output
Pulse Width, 3 cell mode: (any) edge detect, edge detect output
Pulse Width, 4 cell mode: (any) edge detect, edge detect output
325
740
1020
1350
44
150
300
450
600
18
110
225
340
450
14
ns
ns
ns
ns
ns
ns
ns
ns
tw
tw
tw
time1
time1
time1
time1
Delay, 1 cell
Delay, 2 cell
Delay, 3 cell
Delay, 4 cell
mode: (any) edge detect, edge detect output
mode: (any) edge detect, edge detect output
mode: (any) edge detect, edge detect output
mode: (any) edge detect, edge detect output
44
18
14
44
18
14
44
18
14
mode: delayed (any) edge detect, delayed
edge detect output
tw
tw
Pulse Width, 1 cell
Pulse Width, 2 cell
Pulse Width, 3 cell
Pulse Width, 4 cell
Delay, 1 cell
340
670
150
300
450
600
220
220
220
220
110
220
335
450
140
140
140
140
ns
ns
ns
ns
ns
ns
ns
ns
mode: delayed (any) edge detect, delayed
edge detect output
mode: delayed (any) edge detect, delayed
edge detect output
tw
1000
1340
570
mode: delayed (any) edge detect, delayed
edge detect output
tw
mode: delayed (any) edge detect, delayed
edge detect output
time1
time1
time1
time1
mode: delayed (any) edge detect, delayed
edge detect output
Delay, 2 cell
570
mode: delayed (any) edge detect, delayed
edge detect output
Delay, 3 cell
570
mode: delayed (any) edge detect, delayed
edge detect output
Delay, 4 cell
570
time2
time2
time2
time2
Delay, 1 cell
Delay, 2 cell
Delay, 3 cell
Delay, 4 cell
mode: both edge delay, edge detect output
mode: both edge delay, edge detect output
mode: both edge delay, edge detect output
mode: both edge delay, edge detect output
382
713
375
169
318
466
126
237
350
460
ns
ns
ns
ns
1045
1370
mode: both edge delay, delayed edge detect
output
time2
time2
time2
time2
Delay, 1 cell
Delay, 2 cell
Delay, 3 cell
Delay, 4 cell
900
613
520
680
815
250
360
480
600
ns
ns
ns
ns
mode: both edge delay, delayed edge detect
output
1250
1600
1900
mode: both edge delay, delayed edge detect
output
mode: both edge delay, delayed edge detect
output
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 15: Typical Filter Rejection Pulse Width at T = 25 °C
Parameter
VDD = 2.5 V VDD = 3.3 V VDD = 5.0 V
< 123 < 84 < 52
Unit
Filtered Pulse Width
ns
Table 16: Typical Counter/Delay Offset Measurements at T = 25 °C
Parameter
OSC Freq
25 MHz
OSC Power
auto
VDD = 2.5 V VDD = 3.3 V VDD = 5.0 V
Unit
µs
µs
µs
µs
µs
µs
ns
Power-On time
0.13
0.29
663
4
0.13
0.41
570
4
0.13
0.4
Power-On time
2.048 MHz
2.048 kHz
25 MHz
auto
Power-On time
auto
458
8
frequency settling time
frequency settling time
frequency settling time
variable (CLK period)
variable (CLK period)
variable (CLK period)
auto
2.048 MHz
2.048 kHz
25 MHz
auto
0.3
0.4
0.4
auto
660
0-40
0-0.5
0-488
570
0-40
0-0.5
0-488
480
0-40
0-0.5
0-488
forced
forced
forced
2.048 MHz
2.048 kHz
µs
µs
25 MHz/
2.048 kHz
tpd (non-delayed edge)
either
35
14
10
ns
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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3.6 OSCILLATOR CHARACTERISTICS
Table 17: Oscillator0 2.048 kHz Frequency Limits
Temperature Range
Power Supply Range
+25 °C
-40 °C to +85 °C
(VDD), V
Minimum Value, kHz MaximumValue, kHz Minimum Value, kHz MaximumValue, kHz
2.5 V ±8 %
3.3 V ±10 %
5 V ±10 %
2.026
2.025
2.025
2.026
2.025
2.071
2.070
2.071
2.071
2.071
1.907
1.906
1.905
1.906
1.905
2.088
2.088
2.087
2.088
2.088
2.5 V to 4.5 V
2.3 V to 5.5 V
Table 18: Oscillator0 2.048 kHz Frequency Error (Error Calculated Relative to Nominal Value)
Temperature Range
Power Supply Range
(VDD), V
+25 °C
-40 °C to +85 °C
Error
Error
Error
Error
(% at Minimum)
(% at Maximum)
(% at Minimum)
(% at Maximum)
2.5 V ±8 %
3.3 V ±10 %
5 V ±10 %
-1.07 %
-1.09 %
-1.12 %
-1.09 %
-1.12 %
1.12 %
1.09 %
1.11 %
1.10 %
1.12 %
-6.91 %
-6.94 %
-6.96 %
-6.96 %
-6.96 %
1.95 %
1.94 %
1.92 %
2.5 V to 4.5 V
2.3 V to 5.5 V
1.95 %
1.95 %
Table 19: Oscillator1 2.048 MHz Frequency Limits
Temperature Range
Power Supply Range
(VDD), V
+25 °C
-40 °C to +85 °C
Minimum Value,
MHz
Maximum Value,
MHz
Minimum Value,
MHz
Maximum Value,
MHz
2.5 V ±8 %
3.3 V ±10 %
5 V ±10 %
2.021
2.024
2.026
2.022
2.021
2.068
2.069
2.072
2.071
2.072
1.987
1.990
1.994
1.988
1.987
2.088
2.089
2.092
2.090
2.092
2.5 V to 4.5 V
2.3 V to 5.5 V
Table 20: Oscillator1 2.048 MHz Frequency Error (Error Calculated Relative to Nominal Value)
Temperature Range
Power Supply Range
(VDD), V
+25 °C
-40 °C to +85 °C
Error
Error
Error
Error
(% at Minimum)
(% at Maximum)
(% at Minimum)
(% at Maximum)
2.5 V ±8 %
-1.32 %
-1.14 %
0.96 %
1.01 %
-2.98 %
-2.80 %
1.93 %
2.01 %
3.3 V ±10 %
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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Table 20: Oscillator1 2.048 MHz Frequency Error (Error Calculated Relative to Nominal Value)(Continued)
Temperature Range
Power Supply Range
(VDD), V
+25 °C
-40 °C to +85 °C
Error
Error
Error
Error
(% at Minimum)
(% at Maximum)
(% at Minimum)
(% at Maximum)
5 V ±10 %
2.5 V to 4.5 V
2.3 V to 5.5 V
-1.03 %
-1.27 %
-1.32 %
1.18 %
1.09 %
1.18 %
-2.61 %
2.13 %
2.04 %
2.13 %
-2.91 %
-2.98 %
Table 21: Oscillator2 25 MHz Frequency Limits
Power Supply Range
Temperature Range
+25 °C
-40 °C to +85 °C
(VDD), V
Minimum Value,
Maximum Value,
MHz
Minimum Value,
MHz
Maximum Value,
MHz
MHz
2.5 V ±8 %
3.3 V ±10 %
5 V ±10 %
24.588
24.668
24.736
24.620
24.588
25.238
25.261
25.353
25.288
25.353
23.622
23.678
23.723
23.656
23.622
25.669
25.732
25.803
25.769
25.803
2.5 V to 4.5 V
2.3 V to 5.5 V
Table 22: Oscillator2 25 MHz Frequency Error (Error Calculated Relative to Nominal Value)
Temperature Range
Power Supply Range
(VDD), V
+25 °C
-40 °C to +85 °C
Error
Error
Error
Error
(% at Minimum)
(% at Maximum)
(% at Minimum)
(% at Maximum)
2.5 V ±8 %
3.3 V ±10 %
5 V ±10 %
-1.65 %
-1.33 %
-1.06 %
-1.52 %
-1.65 %
0.96 %
1.05 %
1.42 %
1.16 %
1.42 %
-5.51 %
-5.29 %
-5.11 %
-5.38 %
-5.51 %
2.68 %
2.93 %
3.21 %
3.08 %
3.21 %
2.5 V to 4.5 V
2.3 V to 5.5 V
3.6.1 OSC Power-On Delay
Table 23: Oscillators Power-On Delay at T = 25 °C, OSC Power Mode: "Auto Power-On"
Oscillator0
2.048 kHz
Oscillator1
2.048 MHz
Oscillator2
25 MHz
Oscillator2 25MHz
Start with Delay
Power
Supply
Range
(VDD), V
Typical
Maximum
Value, µs
Typical
Maximum
Value, µs
Typical
Maximum
Value, µs
Typical
Maximum
Value, µs
Value, µs
Value, µs
Value, µs
Value, µs
2.3
2.5
2.7
3
702.100
663.423
632.868
597.220
879.295
824.027
779.510
728.822
0.314
0.291
0.274
0.322
0.329
0.308
0.291
0.972
0.034
0.029
0.025
0.021
0.040
0.035
0.029
0.024
0.131
0.130
0.128
0.127
0.142
0.140
0.139
0.137
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 23: Oscillators Power-On Delay at T = 25 °C, OSC Power Mode: "Auto Power-On"(Continued)
Oscillator0
2.048 kHz
Oscillator1
2.048 MHz
Oscillator2
25 MHz
Oscillator2 25MHz
Start with Delay
Power
Supply
Range
(VDD), V
Typical
Maximum
Value, µs
Typical
Maximum
Value, µs
Typical
Maximum
Value, µs
Typical
Maximum
Value, µs
Value, µs
Value, µs
Value, µs
Value, µs
3.3
3.6
4
569.862
548.042
525.124
515.409
502.266
481.578
457.522
690.555
660.574
628.266
615.041
596.996
570.706
539.814
0.411
0.434
0.423
0.418
0.412
0.404
0.397
0.842
0.454
0.441
0.437
0.431
0.422
0.415
0.018
0.015
0.013
0.012
0.011
0.010
0.010
0.020
0.019
0.015
0.015
0.015
0.011
0.010
0.126
0.126
0.126
0.127
0.128
0.129
0.129
0.139
0.139
0.139
0.141
0.142
0.143
0.143
4.2
4.5
5
5.5
3.7 ANALOG COMPARATOR CHARACTERISTICS
Table 24: ACMP Specifications at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted
Parameter
Description
Note
Condition
Min
0
Typ
--
Max
Unit
V
Positive Input
Negative Input
Positive Input
Negative Input
Positive Input
Negative Input
VDD
2.016
VDD
VDD = 2.5 V ± 5 %
0
--
V
ACMP0H, ACMP1H,
ACMP2L, ACMP3L
Input Voltage Range
0
--
V
VACMP
VDD = 3.3 V ± 10 %
0
--
2.016
VDD
V
0
--
V
VDD = 5.0 V ± 10 %
T = 25°C
0
--
2.016
5.68
6.33
5.09
5.55
V
0
--
mV
mV
mV
mV
ACMP0H, ACMP1H
Input Offset Voltage
Vhys = 0 mV, Gain = 1,
Vref = 32 mV to 2016
mV
0
--
Voffset
T = 25 °C
T = 25 °C
0
--
ACMP2L, ACMP3L
Input Offset Voltage
0
--
--
--
--
--
25.0
26.2
36.3
51.4
µs
µs
µs
µs
ACMP0H, ACMP1H
Start Time
ACMPPower-Ondelay,
Minimal required wake
time for the “Wake and
Sleep function”
tstart
T = 25 °C
139.3
144.6
233.3
326.6
ACMP2L, ACMP3L
Start Time
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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Table 24: ACMP Specifications at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted (Continued)
Parameter
Description
Note
Condition
T = 25 °C
T = 25 °C
T = 25 °C
Min
23.60
56.32
189.50
21.16
52.77
180.62
26.46
56.58
185.24
22.28
54.49
183.47
--
Typ
--
Max
36.74
66.79
Unit
mV
VHYS = 32 mV
VHYS = 64 mV
VHYS = 192 mV
VHYS = 32 mV
VHYS = 64 mV
VHYS = 192 mV
VHYS = 32 mV
VHYS = 64 mV
VHYS = 192 mV
VHYS = 32 mV
--
mV
--
196.00 mV
ACMP0H, ACMP1H
Built-in Hysteresis
--
38.84
67.32
mV
mV
--
--
196.00 mV
VHYS
T = 25 °C
T = 25 °C
T = 25 °C
--
34.43
67.38
mV
mV
--
--
197.32 mV
ACMP2L, ACMP3L
Built-in Hysteresis
--
36.86
68.02
mV
mV
V
HYS = 64 mV
--
VHYS = 192 mV
Gain = 1x
--
197.32 mV
100.0
1.0
0.8
1.0
2.53
--
--
ΜΩ
ΜΩ
ΜΩ
ΜΩ
µs
Gain = 0.5x
Gain = 0.33x
Gain = 0.25x
--
Series Input
Resistance
Rsin
PROP
G
--
--
--
--
Gain = 1,
Vref = 32 mV to 2016
mV,
Low to High
High to Low
Low to High
High to Low
Low to High
High to Low
Low to High
High to Low
Low to High
High to Low
Low to High
High to Low
--
4.73
--
--
--
--
--
--
--
--
--
--
--
1.88
1.75
9.48
3.20
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
Overdrive = 5 mV
Propagation Delay,
Response Time
for ACMP0H,
ACMP1H
Gain = 1,
Vref = 32 mV to 2016
mV,
1.36
2.30
Overdrive =10 mV
Gain = 1,
Vref = 32 mV to 2016
mV,
0.81
7.42
0.55
0.84
Overdrive = 100 mV
Gain = 1,
Vref = 32 mV to 2016
mV,
74.91
72.28
49.54
46.92
18.41
16.54
139.75
213.26
70.23
68.44
29.06
26.87
Overdrive = 5 mV
Propagation Delay,
Response Time
for ACMP2L,
Gain = 1,
Vref = 32 mV to 2016
mV,
ACMP3L
Overdrive =10 mV
Gain = 1,
Vref = 32 mV to 2016
mV,
Overdrive = 100 mV
G = 1,
--
1
--
--
--
--
Gain error (including
threshold and internal
Vref error)
G = 0.5,
G = 0.33,
G = 0.25,
0.497
0.330
0.247
0.504
0.337
0.253
Datasheet
25-Feb-2021
Revision 3.12
30 of 353
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© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 24: ACMP Specifications at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted (Continued)
Parameter
Description
Note
Condition
Min
Typ
Max
Unit
Resistance Load =
1 ΜΩ
--
--
5
pF
Resistance Load =
560 κΩ
--
--
--
--
--
--
--
--
10
40
pF
pF
pF
pF
Resistance Load =
100 kΩ
Vref0 Output
Capacitance Loading
Resistance Load =
10 κΩ
Vref
80
Resistance Load =
2 κΩ
120
Resistance Load =
1 κΩ,
Vref = 32 mV to
--
--
150
pF
1024 mV
Resistance Load =
1 ΜΩ
--
--
--
--
--
--
--
--
--
--
15
27
pF
pF
pF
pF
pF
Resistance Load =
560 κΩ
Resistance Load =
100 kΩ
64
Vref1 Output
Capacitance Loading
Resistance Load =
10 κΩ
Vref
120
180
Resistance Load =
2 κΩ
Resistance Load =
1 κΩ,
Vref = 32 mV to
1024 mV
--
--
210
pF
µA
Is
Input Current Source
Vin = VDD - 0.7 V
83.3
95.4
109.8
3.8 ANALOG TEMPERATURE SENSOR CHARACTERISTICS
Temperature Sensor typical nonlinearity ±0.27 % for output range 1 and ±0.29 % for output range 2 at VDD = 3.3 V.
Table 25: TS Output vs Temperature (Output range 1)
VDD = 2.5 V
VDD = 3.3 V
VDD = 5.0 V
Typical, mV Accuracy, %
T, °C
Typical, mV
Accuracy, %
±0.45
Typical, mV
Accuracy, %
±0.45
-40
-30
-20
-10
0
997
973
950
927
905
882
859
836
813
997
973
950
927
905
882
859
836
813
997
973
950
927
905
882
859
836
813
±0.45
±0.22
±0.29
±0.21
±0.30
±0.28
±0.28
±0.21
±0.28
±0.22
±0.22
±0.28
±0.28
±0.21
±0.20
±0.30
±0.30
10
20
30
40
±0.28
±0.28
±0.27
±0.27
±0.21
±0.21
±0.29
±0.28
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
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Table 25: TS Output vs Temperature (Output range 1)(Continued)
VDD = 2.5 V
VDD = 3.3 V
VDD = 5.0 V
T, °C
Typical, mV
Accuracy, %
±0.32
Typical, mV
Accuracy, %
±0.32
Typical, mV
Accuracy, %
±0.32
50
60
70
80
85
790
766
743
719
707
790
766
743
719
707
790
766
743
719
707
±0.52
±0.52
±0.51
±0.62
±0.62
±0.61
±0.82
±0.82
±0.82
±0.82
±0.82
±0.82
Table 26: TS Output vs Temperature (Output Range 2)
VDD = 2.5 V
T, °C
VDD = 3.3 V
VDD = 5.0 V
Typical, mV
1186
1158
1131
1104
1076
1049
1021
994
Accuracy, %
±0.54
±0.29
±0.26
±0.26
±0.37
±0.36
±0.36
±0.24
±0.34
±0.46
±0.63
±0.75
±0.93
±1.02
Typical, mV
1187
1158
1131
1104
1076
1049
1021
994
Accuracy, %
±0.50
±0.29
±0.27
±0.26
±0.37
±0.37
±0.35
±0.25
±0.33
±0.47
±0.64
±0.75
±0.93
±1.03
Typical, mV
1187
1158
1131
1104
1076
1049
1021
994
Accuracy, %
±0.60
±0.29
±0.27
±0.25
±0.37
±0.37
±0.37
±0.25
±0.33
±0.47
±0.64
±0.75
±0.92
±1.02
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
85
966
966
966
938
938
938
910
910
910
881
881
881
852
852
852
838
838
838
Table 27: TS Output Error (Output Range 1)
VDD, V
Error at T
-40 °C, %
±0.44
±0.45
±0.46
±0.45
±0.45
±0.45
±0.45
±0.44
±0.45
±0.45
±0.44
-20 °C, %
±0.28
±0.28
±0.28
±0.29
±0.28
±0.28
±0.28
±0.28
±0.28
±0.29
±0.28
0 °C, %
±0.30
±0.30
±0.30
±0.30
±0.30
±0.31
±0.30
±0.30
±0.30
±0.30
±0.30
20 °C, %
±0.28
±0.27
±0.27
±0.27
±0.27
±0.27
±0.27
±0.28
±0.27
±0.28
±0.28
40 °C, %
±0.29
±0.29
±0.28
±0.28
±0.28
±0.28
±0.28
±0.28
±0.28
±0.28
±0.28
60 °C, %
80 °C, %
±0.82
±0.82
±0.84
±0.82
±0.82
±0.82
±0.82
±0.82
±0.82
±0.82
±0.82
85 °C, %
±0.82
±0.82
±0.84
±0.82
±0.82
±0.82
±0.82
±0.82
±0.82
±0.82
±0.83
2.30
2.50
2.70
3.00
3.30
3.60
4.00
4.20
4.50
5.00
5.50
±0.52
±0.52
±0.52
±0.53
±0.52
±0.53
±0.52
±0.52
±0.51
±0.51
±0.51
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Table 28: TS Output Error (Output Range 2)
Error at T
VDD, V
-40 °C, %
±0.62
±0.54
±0.72
±0.41
±0.50
±0.66
±0.82
±0.43
±0.72
±0.60
±0.58
-20 °C, %
±0.27
±0.26
±0.26
±0.26
±0.27
±0.26
±0.26
±0.27
±0.27
±0.27
±0.27
0 °C, %
±0.37
±0.37
±0.37
±0.37
±0.37
±0.37
±0.37
±0.37
±0.37
±0.37
±0.37
20 °C, %
±0.35
±0.36
±0.36
±0.36
±0.35
±0.36
±0.36
±0.36
±0.37
±0.37
±0.36
40 °C, %
±0.34
±0.34
±0.34
±0.33
±0.33
±0.34
±0.34
±0.34
±0.34
±0.33
±0.34
60 °C, %
±0.63
±0.63
±0.62
±0.64
±0.64
±0.64
±0.64
±0.64
±0.64
±0.64
±0.64
80 °C, %
±0.94
±0.93
±0.94
±0.93
±0.93
±0.93
±0.93
±0.92
±0.92
±0.92
±0.93
85 °C, %
±1.02
±1.02
±1.03
±1.02
±1.03
±1.02
±1.03
±1.02
±1.02
±1.02
±1.03
2.30
2.50
2.70
3.00
3.30
3.60
4.00
4.20
4.50
5.00
5.50
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4
User Programmability
The SLG46880/81 is a user programmable device with a one time programmable (OTP) memory array that is used to configure
the 12 state ASM, logic, and Mixed-Signal circuits. Three of the IO Pins provide a connection for the bit patterns into the OTP on
board memory. A programming development kit allows the user the ability to create initial devices. Once the design is finalized,
the programming code (.gpx file) is forwarded to Dialog Semiconductor to integrate into a production process.
Product
Definition
Customer creates their own design in
GreenPAK Designer
Emulate design to verify behavior
Customers Programs Engineering
Samples with GreenPAK
Development Tools
Customer verifies GreenPAK
in system design
GreenPAK Design
approved
E-mail design file to
CMBUGreenPAK@diasemi.com
Custom GreenPAK part enters production
Figure 2: Steps to Create a Custom GreenPAK Device
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5
IO Pins
5.1 IO PINS
The SLG46880/81 has a total of 12 GPIO, 8 GPI, and 8 GPO pins, which can function either as a user defined Input or Output,
or as a special function (such as outputting the voltage reference), as well as a signal for programming of the on-chip Non Volatile
Memory (NVM). Refer to Section 2 for pin definitions.
GPIs 0, 1, 2, 3, 4, 5, 6, 7, GPIOs 0, 1, 2, 3, 8, 9, 10, 11, GPOs 0, 5, 6, 7 are powered from VDD and GPIOs 4, 5, 6, 7, GPOs 1,
2, 3, 4 are powered from VDD2. All internal macrocells are powered from VDD. Voltage on VDD2 Pin must be less or equal voltage
on VDD Pin.
In case VDD2 floating and any Pin powered from VDD2 is configured as input, ESD pin protection diodes must be considered when
applying an input signal to the pin. This will cause a significant current leakage.
In case VDD2 floating and any Pin powered from VDD2 is configured as Output, the pin will behave as NMOS Open-Drain.
It is not recommended to connect VDD2 to the GND.
5.2 PULL-UP/DOWN RESISTORS
All IO Pins have the option of user-selectable resistors that can be connected to the pin structure. The selectable values on these
resistors are 10 kΩ, 100 kΩ, and 1 MΩ. The internal resistors can be configured as either Pull-up or Pull-downs.
5.3 100 NS DEBOUNCE DELAY
100 ns debounce can be enabled for GPI0, GPI1, GPI5, and GPI6 by setting registers [536], [537], [538], and [539], respectively.
5.4 FAST PULL-UP/DOWN DURING POWER-UP
During power-up, IO Pull-up/down resistance will switch to 2.6 kΩ initially and then it will switch to normal setting value. This
function is enabled by register [670].
5.5 DIGITAL INPUT LATCH
Digital Input Latch can be enabled for GPI0, GPI1, GPI4, GPI5, GPIO2, GPIO3, GPIO6, GPIO7. For timing diagram refer to
Figure 3.
Digital Input
LATCH Enable (LE)
Without LATCH
Normal LATCH
Input Data 0 LATCH
Input Data 1 LATCH
Figure 3: Digital Input Latch Timing Diagram
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5.6 GPO OUTPUT SKEW
Output Skew function can be enabled for GPOs 0 to 7. Once enabled for any GPO (register [671]), Output Skew becomes valid
for all GPOs. All eight GPOs are grouped in pairs: GPO0 and GPO7, GPO1 and GPO2, GPO3 and GPO4, GPO5 and GPO6.
Output Skew allows to delay each pair before setting HIGH or LOW consequently. See Figure 4.
IN
Output Skew Disabled,
all GPOs
Output Skew Enabled,
GPO 0 and GPO 7
Output Skew Enabled,
GPO 1 and GPO 2
Output Skew Enabled,
GPO 3 and GPO 4
Output Skew Enabled,
GPO 5 and GPO 6
Figure 4: Output Skew Timing Diagram
5.7 ULTRA-LOW POWER DIGITAL INPUT (SLG46881 ONLY)
SLG46881 has an Ultra-Low Power Digital Input option that can be applied to GPIOs 0 to 11 and GPIs 1 to 7. Note that when
Ultra-Low Power Digital Input is enabled, Pull-up resistors for GPIOs 0 to 3, 8 to 11, GPIs 1 to 7 switch from VDD to VDD2
.
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5.8 GPI IO STRUCTURE (VDD
)
5.8.1 SLG46880 GPI IO Structure (for GPIs 6, 7)
Non-Schmitt
Trigger Input
Input Mode [1:0]
00: Digital In without Schmitt Trigger, wosmt_en = 1
01: Digital In with Schmitt Trigger, smt_en = 1
10: Low Voltage Digital In mode, lv_en = 1
11: Analog IO mode
register [539]
WOSMT_EN
Schmitt
Trigger Input
Note 1: 100 ns debounce is available for GPI6 only
Note 2: Can be varied over PVT, for reference only
100 ns
Debounce
S1
S0
Digital IN
SMT_EN
LV_EN
Low Voltage
Input
See Note 1
Analog IO
VDD
Floating
s0
s1
s2
s3
VDD
172 Ω
(Note 2)
s1
s0
PAD
900 kΩ
90 kΩ
10 kΩ
Res_sel [1:0]
00: Floating
01: 10 kΩ
Pull-up_EN
10: 100 kΩ
11: 1 MΩ
Figure 5: SLG46880 GPI IO Structure Diagram
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5.8.2 SLG46881 GPI IO Structure (for GPIs 6, 7)
Ultra-Low Power
Digital Input
ULP_EN
Non-Schmitt
Trigger Input
Input Mode [1:0]
00: Digital In without Schmitt Trigger, wosmt_en = 1
01: Digital In with Schmitt Trigger, smt_en = 1
10: Low Voltage Digital In mode, lv_en = 1
11: Analog IO mode
register [539]
WOSMT_EN
Schmitt
Trigger Input
Note 1: 100 ns debounce is available for GPI6 only
Note 2: Can be varied over PVT, for reference only
100 ns
Debounce
S1
S0
Digital IN
SMT_EN
LV_EN
Low Voltage
Input
See Note 1
Analog IO
VDD
172 Ω
(Note 2)
Floating
VDD (or VDD2 when Ultra-Low Power
Digital Input enabled)
s0
s1
s2
s3
PAD
s1
s0
900 kΩ
90 kΩ
10 kΩ
Res_sel [1:0]
00: Floating
01: 10 kΩ
Pull-up_EN
10: 100 kΩ
11: 1 MΩ
Figure 6: SLG46881 GPI IO Structure Diagram
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5.9 GPI WITH INPUT LATCH IO STRUCTURE (VDD
)
5.9.1 SLG46880 GPI with Input LATCH IO Structure (for GPIs 0, 1)
Non-Schmitt
Trigger Input
Latch config
register [536] for GPI0
register [537] for GPI1
00: without latch (S0)
01: normal latch (S1)
10: input data 0 latch (S1)
11: input data 1 latch (S1)
LATCH Config
2-bits
WOSMT_EN
Schmitt
Trigger Input
100 ns
S1
2
D
Debounce
LATCH
Q
S1
S0
EN
S0
SMT_EN
LV_EN
To Matrix
Low Voltage
Input
LATCH_EN
(from Register)
Analog IO
Floating
s0
s1
s2
s3
VDD
172 Ω
(Note 1)
Input Mode [1:0]
00: Digital In without Schmitt Trigger, wosmt_en = 1
01: Digital In with Schmitt Trigger, smt_en = 1
10: Low Voltage Digital In mode, lv_en = 1
11: Analog IO mode
s1
s0
PAD
900 kΩ
90 kΩ
10 kΩ
Note 1: Can be varied over PVT, for reference only
Res_sel [1:0]
00: Floating
01: 10 kΩ
Pull-up_EN
10: 100 kΩ
11: 1 MΩ
Figure 7: SLG46880 GPI with Input LATCH Structure Diagram
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5.9.2 SLG46881 GPI with Input LATCH IO Structure (for GPIs 0, 1)
Ultra-Low Power
Digital Input
ULP_EN
Non-Schmitt
Trigger Input
Latch config
register [536] for GPI0
register [537] for GPI1
LATCH Config
00: without latch (S0)
01: normal latch (S1)
10: input data 0 latch (S1)
11: input data 1 latch (S1)
2-bits
WOSMT_EN
Schmitt
Trigger Input
2
100 ns
Debounce
S1
S0
D
LATCH
Q
S1
S0
EN
SMT_EN
LV_EN
To Matrix
Low Voltage
Input
LATCH_EN
(from Register)
Analog IO
Floating
s0
s1
s2
s3
VDD (or VDD2 when Ultra-Low Power Digital Input enabled)
172 Ω
(Note 2)
s1
s0
Input Mode [1:0]
PAD
00: Digital In without Schmitt Trigger, wosmt_en = 1
01: Digital In with Schmitt Trigger, smt_en = 1
10: Low Voltage Digital In mode, lv_en = 1
11: Analog IO mode
900 kΩ
90 kΩ
10 kΩ
Res_sel [1:0]
00: Floating
01: 10 kΩ
10: 100 kΩ
11: 1 MΩ
Pull-up_EN
Note 1: Ultra-Low Power Digital Input is available for GPI1 only
Note 2: Can be varied over PVT, for reference only
Figure 8: SLG46881 GPI with Input LATCH Structure Diagram
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5.10 GPI WITH I2C MODE IO STRUCTURE (VDD
)
5.10.1 SLG46880 GPI with I2C Mode Structure (for GPIs 2, 3)
PAD
Non-Schmitt
Trigger Input
Input Mode [1:0]
00: Digital In without Schmitt Trigger, wosmt_en = 1
01: Reserved
10: Low Voltage Digital In mode, lv_en = 1
11: Reserved
WOSMT_EN
Digital IN
Low Voltage
Input 1
LV_EN
Floating
s0
VDD
s1
s2
s3
s1
s0
900 kΩ
90 kΩ
10 kΩ
Res_sel [1:0]
00: Floating
01: 10 kΩ
Pull-up_EN
10: 100 kΩ
11: 1 MΩ
I2C SDA Signal
Only used when I2C is
selected
not available for direct user control
Figure 9: SLG46880 GPI with I2C Mode IO Structure Diagram
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5.10.2 SLG46881 GPI with I2C Mode Structure (for GPIs 2, 3)
PAD
Non-Schmitt
Trigger Input
WOSMT_EN
Low Voltage
Input 1
Input Mode [1:0]
00: Digital In without Schmitt Trigger, wosmt_en = 1
01: Reserved
Digital IN
10: Low Voltage Digital In mode, lv_en = 1
11: Reserved
LV_EN
Ultra-Low Power
Digital Input
ULP_EN
Floating
s0
VDD (or VDD2 when Ultra-Low Power Digital Input enabled)
s1
s2
s3
s1
s0
900 kΩ
90 kΩ
10 kΩ
Res_sel [1:0]
00: Floating
01: 10 kΩ
Pull-up_EN
10: 100 kΩ
11: 1 MΩ
I2C SDA Signal
Only used when I2C is
selected
not available for direct user control
Figure 10: SLG46881 GPI with I2C Mode IO Structure Diagram
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5.11 GPIO WITH MATRIX OE IO STRUCTURE (VDD OR VDD2
)
5.11.1 SLG46880 GPIO with Matrix OE IO Structure (for GPIOs 0, 1, 8, 9, 10, 11 with VDD, and GPIOs 4, 5 with VDD2
)
Non-Schmitt
Trigger Input
Input Mode [1:0]
00: Digital In without Schmitt Trigger, wosm t_en = 1
WOSMT_EN
SMT_EN
01: Digital In with Schmitt Trigger, smt_en =1
10: Low Voltage Digital In mode, lv_en = 1
11: analog IO mode
Schmitt
Trigger Input
Output Mode [1:0]
00: Push-Pull 1x mode, pp1x_en = 1
01: Push-Pull 2x mode, pp2x_en = 1, pp1x_en = 1
10: NMOS 1x Open-Drain mode, od1x_en = 1
11: NMOS 2x Open-Drain mode, od2x_en = 1, od1x_en = 1
Digital IN
Note 1: Can be varied over PVT, for reference only.
Low Voltage
Input
LV_EN
Analog IO
Floating
s0
VDD or VDD2
s1
s2
s3
172 Ω
(Note 1)
s1
900 kΩ
90 kΩ
10 kΩ
s0
VDD or VDD2
Res_sel [1:0]
00: Floating
01: 10 kΩ
Pull-up_EN
10: 100 kΩ
11: 1 MΩ
Digital OUT
OE
Digital OUT
OE
OD1x_EN
PP1x_EN
VDD or VDD2
PAD
VDD or VDD2
Digital OUT
Digital OUT
OE
OE
PP2x_EN
OD2x_EN
Figure 11: SLG46880 GPIO with Matrix OE IO Structure Diagram
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5.11.2 SLG46881 GPIO with Matrix OE IO Structure (for GPIOs 0, 1, 8, 9, 10, 11 with VDD, and GPIOs 4, 5 with VDD2
)
Non-Schmitt
Trigger Input
Input Mode [1:0]
00: Digital In without Schmitt Trigger, wosm t_en = 1
01: Digital In with Schmitt Trigger, smt_en =1
10: Low Voltage Digital In mode, lv_en = 1
11: analog IO mode
WOSMT_EN
SMT_EN
Schmitt
Trigger Input
Output Mode [1:0]
Digital IN
00: Push-Pull 1x mode, pp1x_en = 1
01: Push-Pull 2x mode, pp2x_en = 1, pp1x_en = 1
10: NMOS 1x Open-Drain mode, od1x_en = 1
11: NMOS 2x Open-Drain mode, od2x_en = 1, od1x_en = 1
Low Voltage
Input
Note 1: Can be varied over PVT, for reference only.
Note 2: VDD for GPIOs 0, 1, 8, 9, 10, 11 when Ultra-Low Power Digital Input
disabled or VDD2 when Ultra-Low Power Digital Input enabled.
VDD2 for GPIOs 4 and 5.
LV_EN
Ultra-Low Power
Digital Input
ULP_EN
Analog IO
Floating
s0
Note 2
s1
s2
172 Ω
(Note 1)
s1
s3
900 kΩ
90 kΩ
10 kΩ
s0
VDD or VDD2
Res_sel [1:0]
00: Floating
01: 10 kΩ
Pull-up_EN
10: 100 kΩ
11: 1 MΩ
Digital OUT
OE
Digital OUT
OE
OD1x_EN
PP1x_EN
VDD or VDD2
PAD
VDD or VDD2
Digital OUT
Digital OUT
OE
OE
PP2x_EN
OD2x_EN
Figure 12: SLG46881 GPIO with Matrix OE IO Structure Diagram
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5.12 GPIO WITH MATRIX OE AND INPUT LATCH IO STRUCTURE (VDD OR VDD2
)
5.12.1 SLG46880 GPIO with Matrix OE and Input LATCH IO Structure (for GPIOs 2, 3 with VDD, GPIOs 6, 7 with VDD2
)
Non-Schmitt
Trigger Input
Latch config
LATCH Config
2-bits
00: without latch (S0)
01: normal latch (S1)
10: input data 0 latch (S1)
11: input data 1 latch (S1)
Input Mode [1:0]
WOSMT_EN
SMT_EN
00: Digital In without Schmitt Trigger, wosm t_en = 1
01: Digital In with Schmitt Trigger, smt_en =1
10: Low Voltage Digital In mode, lv_en = 1
11: analog IO mode
2
Schmitt
Trigger Input
D
LATCH
Q
S1
S0
EN
To Matrix
Output Mode [1:0]
00: Push-Pull 1x mode, pp1x_en = 1
Low Voltage
Input
01: Push-Pull 2x mode, pp2x_en = 1, pp1x_en = 1
10: NMOS 1x Open-Drain mode, od1x_en = 1
11: NMOS 2x Open-Drain mode, od2x_en = 1, od1x_en = 1
LATCH_EN
(from Register)
Note 1: Can be varied over PVT, for reference only.
LV_EN
Analog IO
Floating
s0
VDD or VDD2
s1
s2
s3
172 Ω
(Note 1)
s1
900 kΩ
90 kΩ
10 kΩ
s0
VDD or VDD2
Res_sel [1:0]
00: Floating
01: 10 kΩ
Pull-up_EN
10: 100 kΩ
11: 1 MΩ
Digital OUT
OE
Digital OUT
OE
OD1x_EN
PP1x_EN
VDD or VDD2
PAD
VDD or VDD2
Digital OUT
OE
Digital OUT
OE
PP2x_EN
OD2x_EN
Figure 13: SLG46880 GPIO with Matrix OE and Input LATCH IO Structure Diagram
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
5.12.2 SLG46881 GPIO with Matrix OE and Input LATCH IO Structure (for GPIOs 2, 3 with VDD, GPIOs 6, 7 with VDD2
)
Non-Schmitt
Trigger Input
Input Mode [1:0]
00: Digital In without Schmitt Trigger, wosm t_en = 1
01: Digital In with Schmitt Trigger, smt_en =1
10: Low Voltage Digital In mode, lv_en = 1
WOSMT_EN
11: analog IO mode
Schmitt
Trigger Input
Latch config
LATCH Config
2-bits
00: without latch (S0)
01: normal latch (S1)
10: input data 0 latch (S1)
11: input data 1 latch (S1)
Output Mode [1:0]
00: Push-Pull 1x mode, pp1x_en = 1
01: Push-Pull 2x mode, pp2x_en = 1, pp1x_en = 1
10: NMOS 1x Open-Drain mode, od1x_en = 1
11: NMOS 2x Open-Drain mode, od2x_en = 1, od1x_en = 1
SMT_EN
2
Low Voltage
Input
D
Note 1: Can be varied over PVT, for reference only.
Note 2: VDD for GPIOs 0, 1, 8, 9, 10, 11 when Ultra-Low Power Digital Input
disabled or VDD2 when Ultra-Low Power Digital Input enabled.
VDD2 for GPIOs 4 and 5.
LATCH
Q
S1
S0
EN
To Matrix
LV_EN
Ultra-Low Power
Digital Input
LATCH_EN
(from Register)
ULP_EN
Analog IO
Floating
s0
Note 2
s1
s2
172 Ω
(Note 1)
s1
s3
900 kΩ
90 kΩ
10 kΩ
s0
VDD or VDD2
Res_sel [1:0]
00: Floating
01: 10 kΩ
Pull-up_EN
10: 100 kΩ
11: 1 MΩ
Digital OUT
OE
Digital OUT
OE
OD1x_EN
PP1x_EN
VDD or VDD2
PAD
VDD or VDD2
Digital OUT
OE
Digital OUT
OE
PP2x_EN
OD2x_EN
Figure 14: SLG46881 GPIO with Matrix OE and Input LATCH IO Structure Diagram
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
5.13 GPI WITH INPUT LATCH AND CRYSTAL INPUT IO STRUCTURE (VDD
)
5.13.1 SLG46880 GPI with Input LATCH and Crystal Input IO Structure (for GPIs 4, 5)
Non-Schmitt
Trigger Input
Latch config
register [538]
LATCH Config
2-bits
00: without latch (S0)
01: normal latch (S1)
10: input data 0 latch (S1)
11: input data 1 latch (S1)
WOSMT_EN
Schmitt
Trigger Input
2
100 ns
Debounce
S1
D
LATCH
Q
S1
S0
EN
S0
SMT_EN
LV_EN
To Matrix
Low Voltage
Input
Note 1
LATCH_EN
(from Register)
Analog IO
Floating
s0
s1
s2
s3
VDD
172 Ω
(Note 2)
Input Mode [1:0]
00: Digital In without Schmitt Trigger, wosmt_en = 1
01: Digital In with Schmitt Trigger, smt_en = 1
10: Low Voltage Digital In mode, lv_en = 1
11: Analog IO mode
s1
s0
PAD
900 kΩ
90 kΩ
10 kΩ
Note 1: 100 ns debounce is available for GPI5 only
Note 2: Can be varied over PVT, for reference only
Res_sel [1:0]
00: Floating
01: 10 kΩ
Pull-up_EN
10: 100 kΩ
11: 1 MΩ
Figure 15: SLG46880 GPI with Input LATCH and Crystal Input IO Structure Diagram
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
5.13.2 SLG46881 GPI with Input LATCH and Crystal Input IO Structure (for GPIs 4, 5)
Ultra-Low Power
Digital Input
ULP_EN
Non-Schmitt
Trigger Input
Latch config
00: without latch (S0)
01: normal latch (S1)
10: input data 0 latch (S1)
11: input data 1 latch (S1)
register [538]
LATCH Config
2-bits
WOSMT_EN
Schmitt
Trigger Input
2
100 ns
S1
S0
Debounce
D
LATCH
Q
S1
S0
EN
SMT_EN
LV_EN
To Matrix
Low Voltage
Input
Note 1
LATCH_EN
(from
Register)
Analog IO
Floating
s0
s1
s2
s3
VDD (or VDD2 when Ultra-Low Power Digital Input enabled)
172 Ω
(Note 2)
s1
s0
Input Mode [1:0]
PAD
00: Digital In without Schmitt Trigger, wosmt_en = 1
01: Digital In with Schmitt Trigger, smt_en = 1
10: Low Voltage Digital In mode, lv_en = 1
11: Analog IO mode
900 kΩ
90 kΩ
10 kΩ
Res_sel [1:0]
00: Floating
01: 10 kΩ
10: 100 kΩ
11: 1 MΩ
Pull-up_EN
Note 1: 100 ns debounce is available for GPI5 only
Note 2: Can be varied over PVT, for reference only
Figure 16: SLG46881 GPI with Input LATCH and Crystal Input IO Structure Diagram
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
5.14 GPO REGISTER OE IO STRUCTURE (VDD OR VDD2
)
5.14.1 GPO Register OE IO Structure (for GPOs 0, 5, 6, 7 for VDD, and GPOs 1, 2, 3, 4 for VDD2
)
Connection Matrix Out
s1
Output Mode [1:0]
00: Push-Pull 1x mode, pp1x_en = 1
Digital Out
01: Push-Pull 2x mode, pp2x_en = 1, pp1x_en = 1
10: NMOS 1x Open-Drain mode, od1x_en = 1
11: NMOS 2x Open-Drain mode, od2x_en = 1, od1x_en = 1
s0
ASM Pin Output
ASM to GPO
0: Matrix Out
1: ASM Pin Out
Floating
s0
s1
s2
s3
VDD or VDD2
s1
s0
900 kΩ
90 kΩ
10 kΩ
VDD or VDD2
Res_sel [1:0]
00: Floating
01: 10 kΩ
Pull-up_EN
10: 100 kΩ
11: 1 MΩ
Digital OUT
OE
Digital OUT
OE
OD1x_EN
PP1x_EN
VDD or VDD2
PAD
VDD or VDD2
Digital OUT
Digital OUT
OE
OE
OD2x_EN
PP2x_EN
Figure 17: SLG46880/81 GPO Register OE IO Structure Diagram
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
5.15 IO TYPICAL PERFORMANCE
ꢆꢀ
ꢍ%ꢎ.Rꢍ%CCꢏꢂ6ꢏꢐꢏꢌꢑꢑꢏYꢏꢅꢏꢌ
ꢍ%ꢎ.Rꢍ%CCꢏꢁ6ꢏꢐꢏꢌꢑꢑꢏYꢏꢅꢏꢌ
ꢍ%ꢎ.Rꢍ%CCꢏꢂ6ꢏꢐꢏꢌꢑꢑꢏYꢏꢃ8ꢃꢏꢌ
ꢍ%ꢎ.Rꢍ%CCꢏꢁ6ꢏꢐꢏꢌꢑꢑꢏYꢏꢃ8ꢃꢏꢌ
ꢍ%ꢎ.Rꢍ%CCꢏꢂ6ꢏꢐꢏꢌꢑꢑꢏYꢏꢂ8ꢅꢏꢌ
ꢍ%ꢎ.Rꢍ%CCꢏꢁ6ꢏꢐꢏꢌꢑꢑꢏYꢏꢂ8ꢅꢏꢌ
ꢅꢀ
ꢄꢀ
ꢃꢀ
ꢂꢀ
ꢁꢀ
ꢀ
ꢅ8ꢀꢀ
ꢄ8ꢇꢅ
ꢄ8ꢅꢀ
ꢄ8ꢂꢅ
ꢄ8ꢀꢀ
ꢃ8ꢇꢅ
ꢃ8ꢅꢀ
ꢃ8ꢂꢅ
ꢃ8ꢀꢀ
ꢂ8ꢇꢅ
ꢂ8ꢅꢀ
ꢂ8ꢂꢅ
ꢂ8ꢀꢀ
ꢁ8ꢇꢅ
ꢁ8ꢅꢀ
ꢁ8ꢂꢅ
ꢌꢉꢊ ^ꢌ_
Figure 18: Typical High Level Output Current vs. High Level Output Voltage at T = 25 °C
Figure 19: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 °C, Full Range
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Figure 20: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 °C
Figure 21: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 °C, Full Range
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Figure 22: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 °C
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
6
Connection Matrix
The Connection Matrix in the SLG46880/81 is used to create the internal routing for internal functional macrocells of the device
once it is programmed. The registers are programmed from the one-time NVM cell during Test Mode Operation. The output of
each functional macrocell within the SLG46880/81 has a specific digital bit code assigned to it that is either set to active “High”
or inactive “Low”, based on the design that is created. Once the 4096 register bits within the SLG46880/81 are programmed a
fully custom circuit will be created.
The Connection Matrix has 64 inputs, 84 outputs and 17 state dependent outputs. Each of the 64 inputs to the Connection Matrix
is hard-wired to the digital output of a particular source macrocell, including IO pins, LUTs, analog comparators, other digital
resources, such as VDD and GND. The input to a digital macrocell uses a 6-bit register to select one of these 64 input lines.
For a complete list of the SLG46880/81’s register table, see Section 21
.
Matrix Input Signal
N
Functions
GND
0
1
2
3
GPIO0 Digital In
GPIO1 Digital In
GPIO2 Digital In
nRST_core (POR)
VDD
62
63
Matrix Inputs
0
1
2
83
N
Registers
register [5:0]
register [11:6]
register [17:12]
registers [503:498]
Matrix OUT: IN0 of
LUT2_0 or Clock
Input of DFF0
Matrix OUT: IN1 of
LUT2_0 or Data
Input of DFF0
Matrix Out: IN0 of
LUT2_1 or Clock
Input of PGen
Function
DM EXT CLK1
Matrix Outputs
Figure 23: Connection Matrix
Function
Connection Matrix
GPIO0
GPIO2
LUT
GPIO0
GPIO2
GPIO6
LUT
GPIO6
Figure 24: Connection Matrix Example
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
6.1 MATRIX INPUT TABLE
Table 29: Matrix Input Table
Matrix Decode
Matrix Input
Matrix Input Signal Function
Number
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
GND
1
GPIO0 Digital Input
2
GPIO1 Digital Input
3
GPIO2 Digital Input
4
GPI0 Digital Input
5
GPI1 Digital Input
6
GPIO3 Digital Input
7
GPIO4 Digital Input
8
LUT2_0/DFF0 Output
9
LUT2_1/PGen Output
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
LUT3_0/DFF1 Output
LUT3_1/DFF2 Output
LUT3_2/DFF3 Output
LUT3_3/DFF4 Output
LUT3_4/CNT_DLY1(8bit) Output
LUT3_5/CNT_DLY2(8bit) Output
LUT3_6/CNT_DLY3(8bit) Output
LUT3_7/CNT_DLY4(8bit) Output
LUT4_0/CNT_DLY0(16bit) Output
LUT3_8/Pipe Delay Output0/Ripple CNT Output0
Pipe Delay Output1/Ripple CNT Output1
Internal 2.048 MHz Osc Output
Internal 2.048 kHz Osc Output
Internal 25 MHz Osc Output
Filter/Edge Detect Output/Ripple CNT Output2
Programmable Delay with Edge Detector Output
F(1) Function Output0
F(1) Function Output1
F(1) Function Output2
DM0_0 Macrocell Output0
DM0_0 Macrocell Output1
DM0_0 Macrocell Output2
GPI2/SDA Digital Input or I2C_virtual_0 Input
GPI3/SCL Digital Input or I2C_virtual_1 Input
I2C_virtual_2 Input
I2C_virtual_3 Input
I2C_virtual_4 Input
I2C_virtual_5 Input
Datasheet
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© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 29: Matrix Input Table(Continued)
Matrix Decode
Matrix Input
Matrix Input Signal Function
Number
5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
I2C_virtual_6 Input
I2C_virtual_7 Input
DM0_1 Macrocell Output0
DM0_1 Macrocell Output1
DM0_1 Macrocell Output2
ASM Connection Matrix Output RAM 0
ASM Connection Matrix Output RAM 1
ASM Connection Matrix Output RAM 2
ASM Connection Matrix Output RAM 0
GPIO5 Digital Input
GPIO6 Digital Input
GPIO7 Digital Input
GPIO8 Digital Input
GPI4 Digital Input/Crystal OSC
GPI5 Digital Input
GPI6 Digital Input
GPI7 Digital Input
GPIO9 Digital Input
ACMP0H Output
ACMP1H Output
ACMP2L Output
ACMP3L output
GPIO10 Digital Input
GPIO11 Digital Input
nRST_core (POR) as matrix input
VDD
6.2 MATRIX OUTPUT TABLE
Table 30: Matrix Output Table
Register Bit
Address
Matrix Output
Number
Matrix Output Signal Function
[5:0]
Matrix Out 0: IN0 of LUT2_0 or Clock Input of DFF0
Matrix Out 1: IN1 of LUT2_0 or Data Input of DFF0
Matrix Out 2: IN0 of LUT2_1 or Clock Input of PGen
Matrix Out 3: IN1 of LUT2_1 or nRST of PGen
0
1
2
3
4
5
6
7
8
[11:6]
[17:12]
[23:18]
[29:24]
[35:30]
[41:36]
[47:42]
[53:48]
Matrix Out 4: IN0 of LUT3_0 or Clock Input of DFF1
Matrix Out 5: IN1 of LUT3_0 or Data Input of DFF1
Matrix Out 6: IN2 of LUT3_0 or nRST (nSET) of DFF1
Matrix Out 7: IN0 of LUT3_1 or Clock Input of DFF2
Matrix Out 8: IN1 of LUT3_1 or Data Input of DFF2
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 30: Matrix Output Table(Continued)
Register Bit
Matrix Output
Number
Matrix Output Signal Function
Address
[59:54]
[65:60]
Matrix Out 9: IN2 of LUT3_1 or nRST (nSET) of DFF2
Matrix Out 10: IN0 of LUT3_2 or Clock Input of DFF3
Matrix Out 11: IN1 of LUT3_2 or Data Input of DFF3
Matrix Out 12: IN2 of LUT3_2 or nRST (nSET) of DFF3
Matrix Out 13: IN0 of LUT3_3 or Clock Input of DFF4
Matrix Out 14: IN1 of LUT3_3 or Data Input of DFF4
Matrix Out 15: IN2 of LUT3_3 or nRST (nSET) of DFF4
Matrix Out 16:IN0 of LUT3_4 or Delay1 Input (or Counter1 nRST Input)
Matrix Out 17:IN1 of LUT3_4 or External Clock1 Input of Delay1 (or Counter1)
Matrix Out 18:IN2 of LUT3_4
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
[71:66]
[77:72]
[83:78]
[89:84]
[95:90]
[101:96]
[107:102]
[113:108]
[119:114]
[125:120]
[131:126]
[137:132]
[143:138]
[149:144]
[155:150]
[161:156]
[167:162]
[173:168]
[179:174]
[185:180]
[191:186]
[197:192]
[203:198]
[209:204]
[215:210]
[221:216]
[227:222]
[233:228]
[239:234]
[245:240]
[251:246]
[257:252]
[263:258]
[269:264]
[275:270]
[281:276]
[287:282]
Matrix Out 19:IN0 of LUT3_5 or Delay2 Input (or Counter2 nRST Input)
Matrix Out 20:IN1 of LUT3_5 or External Clock1 Input of Delay2 (or Counter2)
Matrix Out 21:IN2 of LUT3_5
Matrix Out 22:IN0 of LUT3_6 or Delay3 Input (or Counter3 nRST Input)
Matrix Out 23:IN1 of LUT3_6 or External Clock1 Input of Delay3 (or Counter3)
Matrix Out 24:IN2 of LUT3_6
Matrix Out 25:IN0 of LUT3_7 or Delay4 Input (or Counter4 nRST Input)
Matrix Out 26:IN1 of LUT3_7 or External Clock1 Input of Delay4 (or Counter4)
Matrix Out 27:IN2 of LUT3_7
Matrix Out 28:IN0 of LUT3_8 or Input of Pipe Delay
Matrix Out 29:IN1 of LUT3_8 or nRST of Pipe Delay
Matrix Out 30:IN2 of LUT3_8 or Clock of Pipe Delay
Matrix Out 31:IN0 of LUT4_0 or Delay0 Input (or Counter0 nRST Input)
Matrix Out 32:IN1 of LUT4_0 or External Clock Input of Delay0 (or Counter0)
Matrix Out 33:IN2 of LUT4_0 or UP Input of FSM0
Matrix Out 34:IN3 of LUT4_0 or KEEP Input of FSM0
Matrix Out 35: ACMP0H Power-down
Matrix Out 36: ACMP1H Power-down
Matrix Out 37: ACMP2L Power-down
Matrix Out 38: ACMP3L Power-down
Matrix Out 39: GPO7 DOUT
Matrix Out 40: GPO0 DOUT
Matrix Out 41: GPIO0 DOUT
Matrix Out 42: GPIO0 DOUT OE
Matrix Out 43: GPIO1 DOUT
Matrix Out 44: GPIO1 DOUT OE
Matrix Out 45: GPIO2 DOUT
Matrix Out 46: GPIO2 DOUT OE
Matrix Out 47: GPIO3 DOUT
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 30: Matrix Output Table(Continued)
Register Bit
Matrix Output
Number
Matrix Output Signal Function
Address
[293:288]
[299:294]
[305:300]
[311:306]
[317:312]
[323:318]
[329:324]
[335:330]
[341:336]
[347:342]
[353:348]
[359:354]
[365:360]
[371:366]
[377:372]
[383:378]
[389:384]
[395:390]
[401:396]
[407:402]
[413:408]
[419:414]
[425:420]
[431:426]
[437:432]
[443:438]
[449:444]
[455:450]
[461:456]
[467:462]
[473:468]
[479:474]
[485:480]
[491:486]
[497:492]
[503:498]
Matrix Out 48: GPIO3 DOUT OE
Matrix Out 49: GPIO4 DOUT
Matrix Out 50: GPIO4 DOUT OE
Matrix Out 51: GPIO5 DOUT
Matrix Out 52: GPIO5 DOUT OE
Matrix Out 53: GPO1 DOUT
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
Matrix Out 54: GPO2 DOUT
Matrix Out 55: GPO3 DOUT
Matrix Out 56: GPO4 DOUT
Matrix Out 57: GPIO6 DOUT OE
Matrix Out 58: GPIO6 DOUT
Matrix Out 59: GPIO7 DOUT
Matrix Out 60: GPIO7 DOUT OE
Matrix Out 61: GPIO8 DOUT OE
Matrix Out 62: GPIO8 DOUT
Matrix Out 63: GPIO9 DOUT OE
Matrix Out 64: GPIO9 DOUT
Matrix Out 65: GPIO10 DOUT OE
Matrix Out 66: GPIO10 DOUT
Matrix Out 67: GPIO11 DOUT OE
Matrix Out 68: GPIO11 DOUT
Matrix Out 69: GPO5 DOUT
Matrix Out 70: GPO6 DOUT
Matrix Out 71: ASM nRST
Matrix Out 72: OSC0 ENABLE
Matrix Out 73: OSC1 ENABLE
Matrix Out 74: OSC2 ENABLE
Matrix Out 75: Filter/Edge detect input
Matrix Out 76: F1 interrupt
Matrix Out 77: Programmable delay/edge detect input
Matrix Out 78: Temp sensor/Crystal OSC/Vref Out_0/Vref Out_1 Power Up
Matrix Out 79: GPI LATCH enable
Matrix Out 80: GPIO LATCH enable
Matrix Out 81: BG enable
DM EXT CLK0
DM_EXT_CLK1
Note: For each Address, the two most significant bits are unused.
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6.3 CONNECTION MATRIX VIRTUAL INPUTS
As mentioned previously, the Connection Matrix inputs come from the outputs of various digital macrocells on the device. Eight
of the Connection Matrix inputs have the special characteristic that the state of these signal lines comes from a corresponding
data bit written as a register value via I2C. This gives the user the ability to write data via the serial channel, and have this
information translated into signals that can be driven into the Connection Matrix and from the Connection Matrix to the digital
inputs of other macrocells on the device. The I2C address for reading and writing these register values is at 0x1DB (475).
Six of the eight Connection Matrix Virtual Inputs are dedicated to this virtual input function. An I2C write command to these register
bits will set the signal values going into the Connection Matrix to the desired state. A read command to these register bits will read
either the original data values coming from the NVM memory bits (that were loaded during the initial device startup), or the values
from a previous write command (if that has happened).
Two of the eight Connection Matrix Virtual Inputs are shared with Pin digital inputs (GPI3/SCL Digital Input or I2C_virtual_1 Input),
and (GPI2/SDA Digital Input or I2C_virtual_0 Input). If the virtual input mode is selected, an I2C write command to these register
bits will set the signal values going into the Connection Matrix to the desired state. A read command to these register bits will read
either the original data values coming from the NVM memory bits (that were loaded during the initial device startup), or the values
from a previous write command (if that has happened). The I2C disable/enable register bit [4084] selects whether the Connection
Matrix input comes from the Pin input or from the virtual register.
Select SCL & Virtual Input 1 or GPI3/SCL.
Select SDA & Virtual Input 0 or GPI2/SDA.
See Table 31 for Connection Matrix Virtual Inputs.
Table 31: Connection Matrix Virtual Inputs
Matrix Input
Register Bit
Addresses (d)
Matrix Input Signal Function
Number
32
I2C_virtual_0 Input
I2C_virtual_1 Input
I2C_virtual_2 Input
I2C_virtual_3 Input
I2C_virtual_4 Input
I2C_virtual_5 Input
I2C_virtual_6 Input
I2C_virtual_7 Input
[3800]
[3801]
[3802]
[3803]
[3804]
[3805]
[3806]
[3807]
33
34
35
36
37
38
39
6.4 CONNECTION MATRIX VIRTUAL OUTPUTS
The digital outputs of the various macrocells are routed to the Connection Matrix to enable interconnections to the inputs of other
macrocells in the device. At the same time, it is possible to read the state of each of the macrocell outputs as a register value via
I2C. This option, called Connection Matrix Virtual Outputs, allows the user to remotely read the values of each macrocell output.
The I2C addresses for reading these register values are 0x1D7 (471) to 0x1DE (478). Write commands to these same register
values will be ignored (with the exception of the Virtual Input register bits at 0x1DB (475)).
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7
Combination Function Macrocells
The SLG46880/81 has 12 combination function macrocells that can serve more than one logic or timing function. In each case,
they can serve as a Look Up Table (LUT), or as another logic or timing function. See the list below for the functions that can be
implemented in these macrocells.
One macrocell that can serve as either 2-bit LUT or as D Flip-Flop
Four macrocells that can serve as either 3-bit LUTs or as D Flip-Flops with Set/Reset Input
One macrocell that can serve as either 3-bit LUT or as Pipe Delay/Ripple Counter
One macrocell that can serve as either 2-bit LUT or as Programmable Pattern Generator (PGen)
One macrocell that can serve as either 4-bit LUT or as 16-Bit Counter/Delay/FSM
Four macrocells that can serve as either 3-bit LUTs or as 8-Bit Counter/Delays
Inputs/Outputs for the 12 combination function macrocells are configured from the connection matrix with specific logic functions
which are defined by the state of NVM bits.
When used as a LUT to implement combinatorial logic functions, the outputs of the LUTs can be configured to any user defined
function, including the following standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR). Inputs/Outputs for the 11
combination function macrocells are configured from the connection matrix with specific logic functions being defined by the state
of NVM bits.
7.1 2-BIT LUT OR D FLIP-FLOP MACROCELLS
There is one macrocell that can serve as either 2-bit LUT or as D Flip-Flop. When used to implement LUT functions, the 2-bit LUT
takes in two input signals from the connection matrix and produces a single output, which goes back into the connection matrix.
When used to implement D Flip-Flop function, the two input signals from the connection matrix go to the data (D) and clock (CLK)
inputs for the Flip-Flop, with the output going back to the connection matrix.
The operation of the D Flip-Flop and LATCH will follow the functional descriptions below:
DFF: CLK is rising edge triggered, then Q = D; otherwise Q will not change
LATCH: when CLK is Low, then Q = D; otherwise Q remains its previous value (input D has no effect on the output, when CLK
is High).
register [563] DFF or LATCH Select
IN1
register [562] Output Select (Q or nQ)
S0
From Connection Matrix Output [1]
register [561] DFF Initial Polarity Select
OUT
2-bit LUT0
0: 2-bit LUT0 IN1
1: DFF0 Data
S1
IN0
LUT Truth
Table
To Connection Matrix
Input [8]
S0
S1
4-bits NVM
registers [563:560]
0: 2-bit LUT0 Out
1: DFF0 Out
DFF/Latch
Registers
D
S0
S1
From Connection Matrix Output [0]
Q/nQ
DFF0
0: 2-bit LUT0 IN0
1: DFF0 CLK
CLK
1-bit NVM
register [616]
Figure 25: 2-bit LUT0 or DFF0
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7.1.1 2-Bit LUT or D Flip-Flop Macrocell Used as 2-Bit LUT
Table 32: 2-bit LUT0 Truth Table
IN1
0
IN0
0
OUT
register [560]
register [561]
register [562]
register [563]
LSB
0
1
1
0
1
1
MSB
This macrocell, when programmed for a LUT function, uses a 4-bit register to define their output function:
2-Bit LUT0 is defined by registers [563:560]
Table 33 shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be created
within each of the 2-bit LUT logic cells.
Table 33: 2-bit LUT Standard Digital Functions
Function
AND-2
MSB
LSB
1
0
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
1
0
1
NAND-2
OR-2
NOR-2
XOR-2
XNOR-2
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7.1.2 Initial Polarity Operations
VDD
Data
Clock
POR
Initial Polarity: High
Q with nReset (Case 1)
Initial Polarity: Low
Q with nReset (Case 1)
Figure 26: DFF Polarity Operations
7.2 2-BIT LUT OR PROGRAMMABLE PATTERN GENERATOR
The SLG46880/81 has one combination function macrocell that can serve as a logic or timing function. This macrocell can serve
as a Look Up Table (LUT), or Programmable Pattern Generator (PGen).
When used to implement LUT functions, the 2-bit LUT takes in two input signals from the connection matrix and produces a single
output, which goes back into the connection matrix. When used as a LUT to implement combinatorial logic functions, the outputs
of the LUT can be configured to any user defined function, including the following standard digital logic devices (AND, NAND,
OR, NOR, XOR, XNOR). The user can also define the combinatorial relationship between inputs and outputs to be any selectable
function.
When operating as a Programmable Pattern Generator, the output of the macrocell with clock out a sequence of two to sixteen
bits that are user selectable in their bit values, and user selectable in the number of bits (up to sixteen) that are output before the
pattern repeats.
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From Connection Matrix Output [2]
From Connection Matrix Output [3]
In0
In1
OUT
2-bit LUT1
LUT Truth
Table
To Connection Matrix Input [9]
S0
S1
registers [583:568]
0: 2-bit LUT1 OUT
1: PGen OUT
PGen
Data
nRST
CLK
PGen
OUT
Pattern
size
register [617]
registers [567:564]
Figure 27: 2-bit LUT1 or PGen
VDD
t
t
nRST
CLK
OUT
1
2
6
8
16 17
3
5
7
0
4
9
10 11
14 15
12 13
t
D7
D6
D5
D10
D8
D4
D3
D2
D1
D15
D0
D9
D0
D15
D14
D13
D12
D11
D0
t
Figure 28: PGen Timing Diagram
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7.2.1 2-Bit LUT or PGen Macrocell Used as 2-Bit LUT
Table 34: 2-bit LUT1 Truth Table
IN1
0
IN0
0
OUT
register [564]
register [565]
register [566]
register [567]
LSB
0
1
1
0
1
1
MSB
This macrocell, when programmed for a LUT function, uses a 4-bit register to define their output function:
2-Bit LUT1 is defined by registers [567:564]
Table 35 shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be created
within each of the 2-bit LUT logic cells.
Table 35: 2-bit LUT Standard Digital Functions
Function
AND-2
MSB
LSB
1
0
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
1
0
1
NAND-2
OR-2
NOR-2
XOR-2
XNOR-2
7.3 3-BIT LUT OR D FLIP-FLOP WITH SET/RESET MACROCELLS
There are four macrocells that can serve as either 3-bit LUTs or as D Flip-Flops with Set/Reset inputs. When used to implement
LUT functions, the 3-bit LUTs each take in three input signals from the connection matrix and produce a single output, which goes
back into the connection matrix. When used to implement D Flip-Flop function, the three input signals from the connection matrix
go to the data (D) and clock (CLK), and Reset/Set (nRST/nSET) inputs for the Flip-Flop, with the output going back to the
connection matrix.
DFF1 operation will flow the functional description below:
if register [619] = 0, and the CLK is rising edge triggered, then Q = D, otherwise Q will not change
if register [619] = 1, then data from D is written into the DFF by the rising edge on CLK and output to Q by the falling edge on
CLK
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register [591] DFF or LATCH Select
register [590] Output Select (Q or nQ)
register [589] DFF nRST or nSET Select
register [588] DFF Initial Polarity Select
IN2
IN1
From Connection
Matrix Output [6]
S0
S1
OUT
3-bit LUT0
IN0
LUT Truth
Table
From Connection
Matrix Output [5]
To Connection Matrix
S0
S1
Input [10]
S0
S1
8-bits NVM
registers [591:584]
From Connection
Matrix Output [4]
S0
S1
DFF/Latch
Registers
0
1
Q/nQ
DFF
DFF
D
D
Q
D
Q
nRST/
CL
nSET
nRST/
nSET
CL
nRST/nSET
CLK
register [619]
1-bit NVM
register [618]
Figure 29: 3-bit LUT0 or DFF1
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register [599] DFF or LATCH Select
register [598] Output Select (Q or nQ)
register [597] DFF nRST or nSET Select
register [596] DFF Initial Polarity Select
IN2
IN1
From Connection
Matrix Output [9]
S0
S1
OUT
3-bit LUT1
IN0
LUT Truth
Table
From Connection
Matrix Output [8]
To Connection Matrix
S0
S1
Input [11]
S0
8-bits NVM
registers [599:592]
S1
DFF/Latch
Registers
D
From Connection
Matrix Output [7]
S0
S1
nRST/nSET
CLK
DFF2
Q/nQ
1-bit NVM
register [620]
Figure 30: 3-bit LUT1 or DFF2
register [607] DFF or LATCH Select
register [606] Output Select (Q or nQ)
register [605] DFF nRST or nSET Select
register [604] DFF Initial Polarity Select
IN2
From Connection
Matrix Output [12]
S0
S1
IN1
OUT
3-bit LUT2
IN0
LUT Truth
Table
From Connection
Matrix Output [11]
To Connection Matrix
S0
S1
S0
S1
Input [12]
8-bits NVM
registers [607:600]
DFF/Latch
Registers
D
From Connection
Matrix Output [10]
S0
S1
nRST/nSET
CLK
DFF3
Q/nQ
1-bit NVM
register [621]
Figure 31: 3-bit LUT2 or DFF3
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register [615] DFF or LATCH Select
register [614] Output Select (Q or nQ)
register [613] DFF nRST or nSET Select
register [612] DFF Initial Polarity Select
IN2
IN1
From Connection
Matrix Output [15]
S0
S1
OUT
3-bit LUT3
IN0
LUT Truth
Table
From Connection
Matrix Output [14]
To Connection Matrix
S0
S1
S0
S1
Input [13]
8-bits NVM
registers [615:608]
DFF/Latch
Registers
D
From Connection
Matrix Output [13]
S0
S1
nRST/nSET
CLK
DFF4
Q/nQ
1-bit NVM
register [622]
Figure 32: 3-bit LUT3 or DFF4
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7.3.1 3-Bit LUT or D Flip-Flop Macrocells Used as 3-Bit LUTs
Table 36: 3-bit LUT0 Truth Table
Table 38: 3-bit LUT2 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
register [584]
register [585]
register [586]
register [587]
register [588]
register [589]
register [590]
register [591]
LSB
register [600]
register [601]
register [602]
register [603]
register [604]
register [605]
register [606]
register [607]
LSB
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
MSB
LSB
1
1
1
MSB
LSB
Table 37: 3-bit LUT1 Truth Table
Table 39: 3-bit LUT3 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
register [592]
register [593]
register [594]
register [595]
register [596]
register [597]
register [598]
register [599]
register [608]
register [609]
register [610]
register [611]
register [612]
register [613]
register [614]
register [615]
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
MSB
1
1
1
MSB
Each macrocell, when programmed for a LUT function, uses a 8-bit register to define their output function:
3-Bit LUT0 is defined by registers [591:584]
3-Bit LUT1 is defined by registers [599:592]
3-Bit LUT2 is defined by registers [607:600]
3-Bit LUT3 is defined by registers [615:608]
Table 40 shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be created
within each of the four 3-bit LUT logic cells.
Table 40: 3-bit LUT Standard Digital Functions
Function
AND-3
MSB
LSB
1
0
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
1
0
1
NAND-3
OR-3
NOR-3
XOR-3
XNOR-3
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7.3.2 Initial Polarity Operations
VDD
Data
Clock
POR
Initial Polarity: High
nReset (Case 1)
Q with nReset (Case 1)
nReset (Case 2)
Q with nReset (Case 2)
Initial Polarity: Low
nReset (Case 1)
Q with nReset (Case 1)
nReset (Case 2)
Q with nReset (Case 2)
Figure 33: DFF Polarity Operations with nReset
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VDD
Data
Clock
POR
Initial Polarity: High
nSet (Case 1)
Q with nSet (Case 1)
nSet (Case 2)
Q with nSet (Case 2)
Initial Polarity: Low
nSet (Case 1)
Q with nSet (Case 1)
nSet (Case 2)
Q with nSet (Case 2)
Figure 34: DFF Polarity Operations with nSet
7.4 3-BIT LUT OR PIPE DELAY/RIPPLE COUNTER MACROCELL
There is one macrocell that can serve as either a 3-bit LUT or as a Pipe Delay/Ripple Counter.
When used to implement LUT functions, the 3-bit LUT takes in three input signals from the connection matrix and produces a
single output, which goes back into the connection matrix.
When used as a Pipe Delay, there are three inputs signals from the matrix, Input (IN), Clock (CLK), and Reset (nRST). The Pipe
Delay cell is built from 16 D Flip-Flop logic cells that provide the three delay options, two of which are user selectable. The DFF
cells are tied in series where the output (Q) of each delay cell goes to the next DFF cell input (IN). Both of the two outputs (OUT0
and OUT1) provide user selectable options for 1 to 16 stages of delay. There are delay output points for each set of the OUT0
and OUT1 outputs to a 4-input mux that is controlled by registers [547:544] for OUT0 and registers [551:548] for OUT1. The 4-
input mux is used to control the selection of the amount of delay.
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The overall time of the delay is based on the clock used in the SLG46880/81 design. Each DFF cell has a time delay of the inverse
of the clock time (either external clock or the Oscillator within the SLG46880/81). The sum of the number of DFF cells used will
be the total time delay of the Pipe Delay logic cell. OUT1 Output can be inverted (as selected by register [552]).
In the Ripple Counter mode there are 3 options for setting, which use 7 bits. There are 3 bits to set nSET value (SV) in range
from 0 to 7. It is a value, which will be set into the Ripple Counter outputs when nSET input goes LOW. End value (EV) will use
3 bits for setting outputs code, which will be last code in the cycle. After reaching the EV, the Ripple Counter goes to the first code
by the rising edge on CLK input. The Functionality mode option uses 1 bit. This setting defines how exactly Ripple Counter will
operate.
The user can select one of the functionality modes by register: RANGE or FULL. If the RANGE option is selected, the count starts
from SV. If UP input is LOW the count goes down: SV→EV→EV-1 to SV+1→SV, and others (if SV is smaller than EV), or SV→SV-
1 to EV+1→EV→SV (if SV is bigger than EV). If UP input is HIGH, count starts from SV up to EV, and others.
In the FULL range configuration the Ripple Counter functions as follows. If UP input is LOW, the count starts from SV and goes
down to 0. Then current counter value jumps to EV and goes down to 0, and others.
If UP input is HIGH, count goes up starting from SV. Then current counter value jumps to 0 and counts up to EV, and others. See
Ripple Counter functionality example in Figure 36.
Every step is executed by the rising edge on CLK input.
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registers [551:544]
From Connection
Matrix Output [28]
IN0
From Connection
Matrix Output [29]
IN1
IN2
OUT
3-bit LUT8
From Connection
Matrix Output [30]
registers [551:548]
Pipe Delay
register [552]
Deglitch Filter/
Edge Detector OUT
0
1
0
1
OUT2
OUT1
To Connection
Matrix Input[24]
register [554]
From Connection
Matrix Output [28]
IN
From Connection
Matrix Output [29]
16 Flip-Flops
nRST
0
OUT1
From Connection
Matrix Output [30]
CLK
To Connection
Matrix Input [20]
1
register [554]
OUT0
0
OUT0
To Connection
Matrix Input [19]
0
1
1
registers [547:544]
register [553]
Ripple Counter
3 Flip-Flops
UP
From Connection
Matrix Output [28]
UP/DOWN
Control
OUT0
D
Q
DFF1
CLK
From Connection
Matrix Output [30]
CL
nQ
nSET
From Connection
Matrix Output [29]
SET
OUT1
OUT2
Control
D
Q
DFF2
CL
nQ
Mode & SET/END
Value Control
D
Q
DFF3
nQ
CL
register [550:544]
Figure 35: 3-bit LUT8/Pipe Delay/Ripple Counter
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Figure 36: Example: Ripple Counter Functionality
7.4.1 3-Bit LUT or Pipe Delay Macrocells Used as 3-Bit LUT
Table 41: 3-bit LUT8 Truth Table
IN2
0
IN1
0
IN0
0
OUT
register [544]
register [545]
register [546]
register [547]
register [548]
register [549]
register [550]
register [551]
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
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Each macrocell, when programmed for a LUT function, uses a 8-bit register to define their output function:
3-Bit LUT8 is defined by registers [551:544]
7.5 3-BIT LUT OR 8-BIT COUNTER/DELAY MACROCELLS
There are four macrocells that can serve as either 3-bit LUTs or as Counter/Delays. When used to implement LUT function, the
3-bit LUT takes in three input signals from the connection matrix and produces a single output, which goes back into the connec-
tion matrix. When used to implement 8-Bit Counter/Delay function, two of the three input signals from the connection matrix go
to the external clock (EXT_CLK) and reset (DLY_IN/CNT Reset) inputs for the Counter/Delay, with the output going back to the
connection matrix.
Counter/Delay macrocell has an initial value, which defines its initial value after GPAK is powered up. It is possible to select initial
Low or initial High, as well as initial value defined by a Delay In signal.
For example, in case initial LOW option is used, the rising edge delay will start operation.
These macrocells can also operate in a frequency detection mode.
Delay time and Output Period can be calculated using the following formulas:
Delay time: [(Counter data + 2)/CLK input frequency – Offset (Note)]
Output Period: [(Counter data + 1)/CLK input frequency – Offset (Note)]
One Shot pulse width can be calculated using formula:
Pulse width = [(Counter Data + 2)/CLK input frequency – Offset (Note)]
Note: Offset is the asynchronous time offset between the input signal and the first clock pulse.
Three of the four macrocells can have their active count value read via I2C (CNT0, CNT2, and CNT4). See Section 19.6.1 for
further details.
Note: After two DFF – counters initialize with counter data = 0 after POR.
Initial state = 1 – counters initialize with counter data = 0 after POR.
Initial state = 0 And After two DFF is bypass – counters initialize with counter data after POR.
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7.5.1 3-Bit LUT or 8-Bit CNT/DLY Block Diagrams
From Connection
Matrix Output [18]
IN2
3-bit LUT4
IN1
IN0
From Connection
Matrix Output [17]
S0
S1
OUT
LUT Truth
Table
To Connection
Matrix Input [14]
S0
S1
8-bits NVM
register [3943:3936]
CNT
Data
ext_-
CLK
From Connection
Matrix Output [16]
S0
S1
OUT
CNT/DLY1
DLY_IN/CNT Reset
Config
Data
registers [926:916]
1-bit NVM
register [927]
Figure 37: 3-bit LUT4 or CNT/DLY1
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From Connection
Matrix Output [21]
IN2
3-bit LUT5
IN1
IN0
From Connection
Matrix Output [20]
S0
S1
OUT
LUT Truth
Table
To Connection
Matrix Input [15]
S0
S1
8-bits NVM
registers [3951:3944]
CNT
Data
ext_CLK
From Connection
Matrix Output [19]
S0
S1
OUT
CNT/DLY2
DLY_IN/CNT Reset
Config
Data
registers [939:929]
1-bit NVM
register [940]
Figure 38: 3-bit LUT5 or CNT/DLY2
From Connection
Matrix Output [24]
IN2
3-bit LUT6
IN1
From Connection
Matrix Output [23]
S0
S1
OUT
IN0
LUT Truth
Table
To Connection
Matrix Input [16]
S0
S1
8-bits NVM
registers [3959:3952]
CNT
Data
ext_CLK
From Connection
Matrix Output [22]
S0
S1
OUT
CNT/DLY3
DLY_IN/CNT Reset
Config
Data
registers [953:943]
1-bit NVM
register [954]
Figure 39: 3-bit LUT6 or CNT/DLY3
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From Connection
Matrix Output [27]
IN2
3-bit LUT7
IN1
IN0
From Connection
Matrix Output [26]
S0
S1
OUT
LUT Truth
Table
To Connection
Matrix Input [17]
S0
S1
8-bits NVM
registers [3967:3960]
CNT
Data
ext_CLK
From Connection
Matrix Output [25]
S0
S1
OUT
CNT/DLY4
DLY_IN/CNT Reset
Config
Data
registers [966:956]
1-bit NVM
register [967]
Figure 40: 3-bit LUT7 or CNT/DLY4
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7.5.2 3-Bit LUT or CNT/DLYs Used as 3-Bit LUTs
Table 42: 3-bit LUT4 Truth Table
Table 44: 3-bit LUT6 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
register [3936]
register [3937]
register [3938]
register [3939]
register [3940]
register [3941]
register [3942]
register [3943]
LSB
register [3952]
register [3953]
register [3954]
register [3955]
register [3956]
register [3957]
register [3958]
register [3959]
LSB
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
MSB
LSB
1
1
1
MSB
LSB
Table 43: 3-bit LUT5 Truth Table
Table 45: 3-bit LUT7 Truth Table
IN2
0
IN1
0
IN0
0
OUT
IN2
0
IN1
0
IN0
0
OUT
register [3944]
register [3945]
register [3946]
register [3947]
register [3948]
register [3949]
register [3950]
register [3951]
register [3960]
register [3961]
register [3962]
register [3963]
register [3964]
register [3965]
register [3966]
register [3967]
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
MSB
1
1
1
MSB
Each macrocell, when programmed for a LUT function, uses a 8-bit register to define their output function:
3-Bit LUT4 is defined by registers [3943:3936]
3-Bit LUT5 is defined by registers [3951:3944]
3-Bit LUT6 is defined by registers [3959:3952]
3-Bit LUT7 is defined by registers [3967:3960]
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7.6 CNT/DLY/FSM TIMING DIAGRAMS
7.6.1 Delay Mode CNT/DLY0 to CNT/DLY4
Delay In
Asynchronous delay variable
Asynchronous delay variable
OSC: force Power-On
(always running)
Delay Output
delay = period x (counter data + 1) + variable
variable is from 0 to 1 clock period
delay = period x (counter data + 1) + variable
variable is from 0 to 1 clock period
Delay In
offset
offset
OSC: auto Power-On
(powers up from delay in)
Delay Output
delay = offset + period x (counter data + 1)
See offset in table 13
delay = offset + period x (counter data + 1)
See offset in table 13
Figure 41: Delay Mode Timing Diagram, Edge Select: Both, Counter Data: 3
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The macrocell shifts the respective edge to a set time and restarts by appropriate edge. It works as a filter if the input signal is
shorter than the delay time.
Delay time
Delay time
Delay time
Delay time
Delay time
One-Shot/Freq. DET/Delay IN
t
Delay time
Delay Function
Rising Edge Detection
t
Delay Function
Falling Edge Detection
t
Delay Function
Both Edge Detection
t
Figure 42: Delay Mode Timing Diagram for Different Edge Select Modes
7.6.2 Count Mode (Count Data: 3), Counter Reset (Rising Edge Detect) CNT/DLY0 to CNT/DLY4
RESET_IN
CLK
Counter OUT
4 CLK period pulse
Count start in first rising edge CLK
Figure 43: Counter Mode Timing Diagram without Two DFFs Synced Up
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RESET_IN
CLK
Counter OUT
4 CLK period pulse
Count start in 0 CLK after reset
Figure 44: Counter Mode Timing Diagram with Two DFFs Synced Up
7.6.3 One-Shot Mode CNT/DLY0 to CNT/DLY4
This macrocell will generate a pulse whenever a selected edge is detected on its input. Register bits set the edge selection. The
pulse width determines by counter data and clock selection properties. The output pulse polarity (non-inverted or inverted) is
selected by register bit. Any incoming edges will be ignored during the pulse width generation. The following diagram shows one-
shot function for non-inverted output.
Delay time
Delay time
Delay time
Delay time
Delay time
One-Shot/Freq. DET/Delay IN
t
Delay time
One-Shot Function
Rising Edge Detection
t
One-Shot Function
Falling Edge Detection
t
One-Shot Function
Both Edge Detection
t
Figure 45: One-Shot Function Timing Diagram
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This macrocell generates a high level pulse with a set width (defined by counter data) when detecting the respective edge. It
does not restart while pulse is high.
7.6.4 Frequency Detection Mode CNT/DLY0 to CNT/DLY4
Rising Edge: The output goes high if the time between two successive edges is less than the delay. The output goes low if the
second rising edge has not come after the last rising edge in specified time.
Falling Edge: The output goes high if the time between two falling edges is less than the set time. The output goes low if the
second falling edge has not come after the last falling edge in specified time.
Both Edge: The output goes high if the time between the rising and falling edges is less than the set time, which is equivalent to
the length of the pulse. The output goes low if after the last rising/falling edge and specified time, the second edge has not
come.
Delay time
Delay time
Delay time
Delay time
Delay time
One-Shot/Freq. DET/Delay IN
t
Delay time
Frequency Detector Function
Rising Edge Detection
t
Frequency Detector Function
Falling Edge Detection
t
Frequency Detector Function
Both Edge Detection
t
Figure 46: Frequency Detection Mode Timing Diagram
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7.6.5 Edge Detection Mode CNT/DLY1 to CNT/DLY4
The macrocell generates high level short pulse when detecting the respective edge. See Table 14.
Delay time
Delay time
Delay time
Delay time
Delay time
One-Shot/Freq. DET/Delay IN
t
t
Edge Detector Function
Rising Edge Detection
Edge Detector Function
Falling Edge Detection
t
t
Edge Detector Function
Both Edge Detection
Figure 47: Edge Detection Mode Timing Diagram
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7.6.6 Delayed Edge Detection Mode CNT/DLY0 to CNT/DLY4
In Delayed Edge Detection Mode, High level short pulses are generated on the macrocell output after the configured delay time
if the corresponding edge was detected on the input.
If the input signal is changed during the set delay time, the pulse will not be generated. See Figure 48.
Delay time
Delay time
Delay time
Delay time
Delay time
One-Shot/Freq. DET/Delay IN
t
t
Delay time
Delayed Edge Detector Function
Rising Edge Detection
Delayed Edge Detector Function
Falling Edge Detection
t
t
Delayed Edge Detector Function
Both Edge Detection
Figure 48: Delayed Edge Detection Mode Timing Diagram
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7.6.7 CNT/FSM Mode CNT/DLY0
RESET IN
KEEP
COUNT END
CLK
3
2
1
0
3
2
1
0
3
2
1
3
2
1
0
0
Q
Note: Q = current counter value
Figure 49: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP = 0) for Counter Data = 3
SET IN
KEEP
COUNT END
CLK
2
1
0
3
2
1
0
3
3
2
1
2
1
0
3
3
Q
Note: Q = current counter value
Figure 50: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced On, UP = 0) for Counter Data = 3
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RESETI N
KEEP
COUNT END
CLK
65535
65533 65534
5
6
7
8
9
3
4
5
3
4
5
1
2
3
4
0
Q
Note: Q = current counter value
Figure 51: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP = 1) for Counter Data = 3
SET IN
KEEP
COUNT END
CLK
65533 65534 65535
8
9
10 11 12
3
4
5
3
4
5
4
5
6
7
3
Q
Note: Q = current counter value
Figure 52: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced On, UP = 1) for Counter Data = 3
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7.6.8 Difference in Counter Value for Counter, Delay, One-Shot, and Frequency Detect Modes
There is a difference in counter value for Counter and Delay/One-Shot/Frequency Detect modes. The counter value is shifted for
two rising edges of the clock signal in Delay/One-Shot/Frequency Detect modes compared to Counter mode. See Figure 53.
One-Shot/Freq. SET/Delay IN
CLK
CNT Out
3
2
1
0
0
3
CNT Data
2
DLY Out
3
3
2
Delay Data
1
3
3
3
One-Shot Out
One-Shot Data
3
3
2
3
1
3
3
Figure 53: Counter Value, Counter Data = 3
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7.7 4-BIT LUT OR 16-BIT COUNTER/DELAY MACROCELL
There is one macrocell that can serve as either 4-bit LUT or as 16-bit Counter/Delay. When used to implement LUT function, the
4-bit LUT takes in four input signals from the Connection Matrix and produces a single output, which goes back into the Connection
Matrix. When used to implement 16-Bit Counter/Delay function, two of the four input signals from the connection matrix go to the
external clock (EXT_CLK) and reset (DLY_IN/CNT Reset) for the counter/delay, with the output going back to the connection
matrix.
This macrocell has an optional Finite State Machine (FSM) function. There are two additional matrix inputs for Up and Keep to
support FSM functionality.
This macrocell can also operate in a one-shot mode, which will generate an output pulse of user-defined width.
This macrocell can also operate in a frequency detection or edge detection mode.
This macrocell can have its active count value read via I2C. See Section 19.6.1 for further details.
Note: After two DFF – counters initialize with counter data = 0 after POR.
Initial state = 1 – counters initialize with counter data = 0 after POR.
Initial state = 0 And After two DFF is bypass – counters initialize with counter data after POR.
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7.7.1 4-Bit LUT or 16-Bit CNT/DLY Block Diagram
From Connection
Matrix Output [34]
S0
S1
IN3
From Connection
Matrix Output [33]
S0
S1
IN2
4-bit LUT0
IN1
IN0
From Connection
Matrix Output [32]
S0
S1
OUT
LUT Truth
Table
To Connection
Matrix Input [18]
S0
S1
16-bits NVM
registers [3935:3920]
CNT
Data
ext_CLK
From Connection
Matrix Output [31]
S0
S1
OUT
CNT/DLY0
DLY_IN/CNT Reset
KEEP
UP
FSM
Config
Data
registers [907:896]
1-bit NVM
register [908]
Figure 54: 4-bit LUT0 or CNT/DLY0
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7.7.2 4-Bit LUT or 16-Bit Counter/Delay Macrocells Used as 4-Bit LUTs
Table 46: 4-bit LUT0 Truth Table
IN3
0
IN2
0
IN1
0
IN0
0
OUT
register [3920] LSB
register [3921]
register [3922]
register [3923]
register [3924]
register [3925]
register [3926]
register [3927]
register [3928]
register [3929]
register [3930]
register [3931]
register [3932]
register [3933]
register [3934]
register [3935] MSB
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
This macrocell, when programmed for a LUT function, uses a 16-bit register to define their output function:
4-Bit LUT0 is defined by registers [3935:3920]
Table 47: 4-bit LUT Standard Digital Functions
Function
AND-4
MSB
LSB
1
0
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
1
0
1
NAND-4
OR-4
NOR-4
XOR-4
XNOR-4
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7.8 WAKE AND SLEEP CONTROLLER
The SLG46880/81 has a Wake and Sleep (WS) function for ACMP0H and ACMP1H. The macrocell CNT/DLY0 can be reconfig-
ured for this purpose registers [897:896] = 11 and register [910] = 1. The WS serves for power saving, it allows to switch on and
off selected ACMPs on selected bit of 16-bit counter.
Power Control
From Connection Matrix Output[59] for 2 kHz Low Power Osc.
WS Controller
OSC
CNT0_out
cnt_end
CNT
To Connection Matrix Input [14]
ck
CK_OSC
Divider
Analog Control Block
ACMPxH WS EN [1:0]
registers [663], [664]
2
2
bg/regulator
pd
From Connection
Matrix Output [38:37]
WS_out
WS_PD
WS_PD
(from OSC PD)
ACMPs_PD
WS_out
WS_PD to W&S out
state selection
registers [531:530]
WS clock freq. pre-divider
registers [910]
WS ratio control data
ACMPs
registers [903:900]
WS clock freq. selection
Note: WS_PD is High at WS OSC
ACMPxHOUT
+
-
2
0
1
(2 kHz Low Power OSC) Power-down
2
To Connection
Matrix Input
[57:56]
ACMPxH_PD
WS_out
nRST
BG/Analog_Good
Figure 55: WS Controller
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time between Reset goes low
and 1st WS clock rsing edge
Force Wake
CNT_RST
(From Connection Matrix)
ACMP_PD is High
(From Connection Matrix)
CNT0_out
(To Connection Matrix)
WS_out
(internal signal)
Data is latched
BG/Analog_Good
(internal signal)
Sleep Mode
ACMP Latches Last Data
Normal ACMP
Operation
ACMP follows input
Sleep Mode
ACMP Latches New Data
Normal ACMP
Sleep Mode
ACMP Latches
New Data
Operation
ACMP follows input
BG/Analog
Startup time*
BG/Analog
Startup time*
Note: CNT0_out is a delayed WS_out signal for 1us to make sure the data is correct during latch.
Figure 56: Wake/Sleep Timing Diagram, Normal Wake Mode, Counter Reset is Used
time between Reset goes low
and 1st WS clock rsing edge
Force Wake
CNT_RST
(From Connection Matrix)
ACMP_PD is High
(From Connection Matrix)
CNT0_out
(To Connection Matrix)
WS_out
(internal signal)
Data is latched
Data is latched
BG/Analog_Good
(internal signal)
Sleep Mode
ACMP Latches Last Data
Sleep Mode
ACMP Latches New Data
Normal ACMP
Operation for short time
ACMP follows inout
Sleep Mode
ACMP Latches
New Data
Normal ACMP
Operation for short time
ACMP follows inout
BG/Analog
Startup time*
BG/Analog
Startup time*
Note: CNT0_out is a delayed WS_out signal for 1us to make sure the data is correct during latch.
Figure 57: Wake/Sleep Timing Diagram, Short Wake Mode, Counter Reset is Used
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time between Reset goes low
and 1st WS clock rsing edge
Force Sleep
CNT_SET
(From Connection Matrix)
ACMP_PD is High
(From Connection Matrix)
CNT0_out
(To Connection Matrix)
WS_out
(internal signal)
Data is latched
BG/Analog_Good
(internal signal)
Sleep Mode
ACMP Latches Last Data
Normal ACMP
Operation
ACMP follows input
Sleep Mode
ACMP Latches New Data
BG/Analog
Startup time*
Note: CNT0_out is a delayed WS_out signal for 1us to make sure the data is correct during latch.
Figure 58: Wake/Sleep Timing Diagram, Normal Wake Mode, Counter Set is Used
time between Reset goes low
and 1st WS clock rsing edge
Force Sleep
CNT_RST
(From Connection Matrix)
ACMP_PD is High
(From Connection Matrix)
CNT0_out
(To Connection Matrix)
WS_out
(internal signal)
Data is latched
BG/Analog_Good
(internal signal)
Sleep Mode
Sleep Mode
ACMP Latches New Data
ACMP Latches Last Data
Normal ACMP
Operation for short time
ACMP follows inout
BG/Analog
Startup time*
Note: CNT0_out is a delayed WS_out signal for 1us to make sure the data is correct during latch.
Figure 59: Wake/Sleep Timing Diagram, Short Wake Mode, Counter Set is Used
Note: If low power BG is powered on/off by WS, the wake time should be longer than 2.1 ms. The BG/analog start up time will
take maximal 2 ms. If low power BG is always on, OSC0 period is longer than required wake time. The short wake mode can be
used to reduce the current consumption.
To use any ACMPxH under WS controller the following settings must be done:
ACMPxH Power Up Input from matrix = 1 (for each ACMPxH separately).
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CNT/DLY0 must be set to Wake and Sleep Controller function (for all ACMPxH).
Register WS → enable (for each ACMPxH separately).
CNT/DLY0 set/reset input = 0 (for all ACMPxH).
As the OSC any oscillator with any pre-divider can be used. The user can select a period of time while the ACMPxH is sleeping
in a range of 1 to 65535 clock cycles. Before they are sent to sleep their outputs are latched, so the ACMPs remain their state
(High or Low) while sleeping.
WS controller has the following settings:
Wake and Sleep Output State (High/Low)
If OSC is powered off (Power-down option is selected; Power-down input = 1) and Wake and Sleep Output State = High, the
ACMPxH is continuously on.
If OSC is powered off (Power-down option is selected; Power-down input = 1) and Wake and Sleep Output State = Low, the
ACMPxH is continuously off.
Both cases WS function is turned off.
Counter Data (Range: 1 to 65535)
User can select wake and sleep ratio of the ACMP; counter data = sleep time, one clock = wake time.
Q mode - defines the state of WS counter data when Set/Reset signal appears Reset - when active signal appears, the WS
counter will reset to zero and High level signal on its output will turn on the ACMPs. When Reset signal goes out, the WS
counter will go Low and turn off the ACMPxH until the counter counts up to the end. Set - when active signal appears, the WS
counter will stop and Low level signal on its output will turn off the ACMPxH. When Set signal goes out, the WS counter will go
on counting and High level signal will turn on the ACMPxH while counter is counting up to the end.
Note: The OSC0 matrix power down to control ACMP W/S is not supported for short wait time option.
Edge Select defines the edge for Q mode
High level Set/Reset - switches mode Set/Reset when level is High
Note: Q mode operates only in case of "High Level Set/Reset”.
Wake time selection - time required for wake signal to turn the ACMPxH on
Normal Wake Time - when WS signal is High, it takes BG/analog start up time to turn the ACMPs on. They will stay on until
WS signal is Low again. Wake time is one clock period. It should be longer than BG turn on time and minimal required com-
paring time of the ACMP.
Short Wake Time - when WS signal is High, it takes BG/analog start up time to turn the ACMPs on. They will stay on for 1 µs
and turn off regardless of WS signal. The WS signal width does not matter.
Keep - pauses counting while Keep = 1
Up - reverses counting
If Up = 1, CNT is counting up from user selected value to 65535.
If Up = 0, CNT is counting down from user selected value to 0.
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7.8.1 WS Register Settings
Table 48: WS Register Settings
Register Bit
Address
Signal Function
Register Definition
Counter/delay0
Clock Source Select
registers
[903:900]
0000: OSC2
0001: OSC2 /4
0010: OSC1
0011: OSC1 /8
0100: OSC1 /64
0101: OSC1 /512
0110: OSC0
0111: OSC0 /8
1000: OSC0 /64
1001: OSC0 /512
1010: OSC0 /4096
1011: OSC0 /32768
1100: OSC0 /262144
1101: CNT4 Overflow
1110: External
1111: Reserved
ACMP0H Wake & Sleep
function Enable
register [663]
register [664]
register [909]
0: Disable
1: Enable
ACMP1H Wake & Sleep
function Enable
0: Disable
1: Enable
Wake Sleep Output State
When WS Oscillator
is Power-downif DLY/CNT0
Mode Selection
0: Low
1: High
is "11"
DLY/CNT0
(16bits, [15:0] =
registers
[3935:3920]
1 - 65535
[3935:3920]) Control Data
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8
Analog Comparators
There are four General Purpose Rail-to-Rail Analog Comparator (ACMP) macrocells in the SLG46880/81. In order for the ACMP
cells to be used in a GreenPAK design, the power up signals (ACMP0H PWR UP, ACMP1H PWR UP, ACMP2L PWR UP, and
ACMP3L PWR UP) need to be active. By connecting to signals coming from the Connection Matrix, it is possible to have each
ACMP be on continuously, off continuously, or switched on periodically based on a digital signal coming from the Connection
Matrix. When ACMP is powered down, output is low.
Two of the four General Purpose Rail-to-Rail Analog Comparators are optimized for high speed operation (ACMP0H and
ACMP1H), and two of the four are optimized for low power operation (ACMP2L and ACMP3L).
Each of the ACMP cells has a positive input signal that can be provided by a variety of external sources, and can also have a
selectable gain stage before connection to the analog comparator. Each of the ACMP cells has a negative input signal that is
either created from an internal Vref or provided by way of the external sources.
PWR UP = 1 → ACMP is powered up.
PWR UP = 0 → ACMP is powered down.
During power-up, the ACMP output will remain LOW, and then become valid 51.4 μs (max) after power up signal goes high for
ACMP0H and ACMP1H, and become valid 326.6 μs (max) after power up signal goes high for ACMP2L and ACMP3L. Input bias
current < 1 nA (typ). The Gain divider is unbuffered and consists of 2 MΩ resistors.
Each High Speed ACMP (ACMP0H and ACMP1H) has an optional Rail-to-Rail Input Buffer, which can be used along with the
Gain divider to increase ACMP input resistance. However, Input buffer will increase an input offset voltage.
Each cell also has a hysteresis selection, to offer hysteresis of (0, 32, 64, 192) mV. The hysteresis option is available when using
an internal Vref only.
The ACMP0H has an additional option of connecting an internal 100 μA current source to its positive input, register [666]. It is
also possible to connect the 100 μA current source to each next ACMP via an internal analog MUX.
ACMP0H IN+ options are GPIO10, buffered GPIO10, VDD, 100 µA Current Source
ACMP1H IN+ options are GPIO11, buffered GPIO11, ACMP0H IN+ MUX output
ACMP2L IN+ options are GPO5, ACMP0H IN+ MUX output, ACMP1H IN+ MUX output
ACMP3L IN+ options are GPO6, ACMP2L IN+ MUX output, Temp Sensor OUT
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8.1 ACMP0H BLOCK DIAGRAM
to ACMP1H, ACMP2L,
VDD
ACMP3L’s MUX input
registers [628:627]
100 µA
Current
Source
register [666]
en
Hysteresis
Selection
registers [3889:3888]
01
00
10
BG_ok
GPIO10: ACMP0H(+)
Selectable
Gain
+
-
To Connection
Matrix Input[56]
L/S
0
1
Internal VDD 2.3 V ~ 5.5 V
Vref
PWR UP
HighSpeed
ACMP
Latch
*GPIO10_aio_en; registers [632], [630]
Ext. Vref (GPI7)
register [630]
111111
From Connection
Matrix Output [35]
111110-
000000
Internal
Vref
registers [3895:3890]
Figure 60: ACMP0H Block Diagram
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8.2 ACMP1H BLOCK DIAGRAM
to ACMP2L’s MUX input
registers [636:635]
Hysteresis
Selection
registers [3897:3896]
00
BG_ok
L/S
GPIO11: ACMP1H(+)
Selectable
Gain
+
-
01
10
To Connection
Matrix Input[57]
0
1
ACMP0H IN+ MUX Output
Vref
PWR UP
HighSpeed
ACMP
Latch
*GPIO11_aio_en; registers [637], [633]
register [637]
Ext. Vref (GPI7)
111111
From Connection
Matrix Output [35]
111110-
000000
Internal
Vref
registers [3903:3898]
Figure 61: ACMP1H Block Diagram
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8.3 ACMP2L BLOCK DIAGRAM
registers [642:641]
Hysteresis
Selection
registers [3905:3904]
GPO5: ACMP2L(+)
00
BG_ok
L/S
from ACMP0H’s MUX output
Selectable
Gain
To Connection
Matrix Input[58]
+
01
from ACMP1H’s MUX output
10
Vref
-
PWR UP
Low Power
ACMP
*GPO5_aio_en; registers [640], [639]
Ext. Vref (GPI7)
111111
From Connection
Matrix Output [37]
Low
Power
Internal
Vref
111110-
000000
registers [3911:3906]
Figure 62: ACMP2L Block Diagram
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8.4 ACMP3L BLOCK DIAGRAM
registers [646:645]
Hysteresis
Selection
registers [3913:3912]
GPO6: ACMP3L(+)
00
BG_ok
L/S
ACMP2L IN+ MUX Output
Selectable
Gain
To Connection
Matrix Input[59]
+
01
Temp Sensor
10
Vref
-
PWR UP
Low Power
ACMP
*GPO6_aio_en; registers [649], [669]
Ext. Vref (GPI7)
111111
From Connection
Low
Power
Internal
Vref
Matrix Output [38]
111110-
000000
Low Power
ACMP
registers [3919:3914]
Figure 63: ACMP3L Block Diagram
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8.5 ACMP TYPICAL PERFORMANCE
Figure 64: Typical Propagation Delay vs. Vref for ACMPxH at T = 25 °C, Gain = 1, Buffer - Disabled, Hysteresis = 0
Figure 65: Typical Propagation Delay vs. Vref for ACMPxL at T = 25 °C, Gain = 1, Buffer - Disabled, Hysteresis = 0
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45
40
35
30
25
20
15
10
5
ACMPxH (T = -40 °C)
ACMPxH (T = 25 °C)
ACMPxH (T = 85 °C)
0
2.3 2.5 2.7
2.9
3.1
3.3
3.5 3.7 3.9
VDD (V)
Figure 66: ACMPxH Power-On Delay vs. VDD
4.1
4.3
4.5
4.7 4.9 5.1
5.3
5.5
220
210
200
190
180
170
160
150
140
130
120
110
100
ACMPxL (T = -40 °C)
ACMPxL (T = 25 °C)
ACMPxL (T = 85 °C)
2.3
2.5
2.7
2.9
3.1
3.3 3.5 3.7
3.9
4.1
4.3
4.5
4.7
4.9 5.1 5.3 5.5
VDD (V)
Figure 67: ACMPxL Power-On Delay vs. VDD
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8
6
4
2
0
Upper Limit
Lower Limit
32
256
480
1024
1504
2016
-2
-4
-6
-8
Vref (mV)
Figure 68: ACMPxH Input Offset Voltage vs. Vref at T = -40 °C to 85 °C, Input Buffer Disabled
8
6
4
Upper Limit
Lower Limit
2
0
32
256
480
1024
1504
2016
-2
-4
-6
-8
Vref (mV)
Figure 69: ACMPxL Input Offset Voltage vs. Vref at T = -40 °C to 85 °C, Input Buffer Disabled
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120
100
80
60
40
Max
20
Typical
Min
0
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
Input Voltage (V)
2
2.2 2.4 2.6 2.8
3
3.2 3.4
Figure 70: ACMP Input Current Source vs. Input Voltage at T = -40 °C to 85 °C, VDD = 3.3 V
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9
Programmable Delay/Edge Detector
The SLG46880/81 has a programmable time delay logic cell available that can generate a delay that is selectable from one of
four timings (time1) configured in the GreenPAK Designer. The programmable time delay cell can generate one of four different
delay patterns, rising edge detection, falling edge detection, both edge detection, and both edge delay. These four patterns can
be further modified with the addition of delayed edge detection, which adds an extra unit of delay as well as glitch rejection during
the delay period. See Figure 72 for further information.
Note: The input signal must be longer than the delay, otherwise it will be filtered out.
registers [559:558]
registers [557:556]
Delay Value Selection
Edge Mode Selection
To Connection
Matrix Input [25]
Programmable
From Connection Matrix Output [77]
IN
OUT
Delay
Figure 71: Programmable Delay
9.1 PROGRAMMABLE DELAY TIMING DIAGRAM - EDGE DETECTOR OUTPUT
width
width
IN
time1
Rising Edge Detector
time1
Falling Edge Detector
Edge Detector
Output
Both Edge Detector
Both Edge Delay
time2
time2
time1 is a fixed value
time2 delay value is selected via register
Figure 72: Edge Detector Output
Please refer to Table 14.
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10 Additional Logic Function
The SLG46880/81 has one additional logic function that is connected directly to the Connection Matrix inputs and outputs. There
is one deglitch filter, with edge detector function.
10.1 DEGLITCH FILTER/EDGE DETECTOR
Filter
R
From Connection Matrix
0
Output [75]
C
0
0
1
1
Edge
Detector
Logic
1
To Connection
Matrix
Input [24]
register [540]
registers [543:542]
register [541]
register [554]
Ripple Counter OUT2
Figure 73: Deglitch Filter/Edge Detector
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11 Voltage Reference
11.1 VOLTAGE REFERENCE OVERVIEW
The SLG46880/81 has a Voltage Reference (Vref) Macrocell to provide references to the four analog comparators. This macrocell
can supply a user selection of fixed voltage references, or temperature sensor output. The macrocell also has the option to output
reference voltages on GPIO2 and GPIO9. See Table 49 for the available selections for each analog comparator. Also, see Figure
74, which shows the reference output structure.
11.2 VREF SELECTION TABLE
Table 49: Vref Selection Table
SEL[5:0]
0
Vref
0.032
0.064
0.096
0.128
0.16
SEL[5:0]
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
Vref
1.056
1.088
1.12
1
2
3
1.152
1.184
1.216
1.248
1.28
4
5
0.192
0.224
0.256
0.288
0.32
6
7
8
1.312
1.344
1.376
1.408
1.44
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0.352
0.384
0.416
0.448
0.48
1.472
1.504
1.536
1.568
1.6
0.512
0.544
0.576
0.608
0.64
1.632
1.664
1.696
1.728
1.76
0.672
0.704
0.736
0.768
0.8
1.792
1.824
1.856
1.888
1.92
0.832
0.864
0.896
0.928
0.96
1.952
1.984
2.016
External
0.992
1.024
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11.3 TRUTH TABLE FOR VREF0 BUFFER AND OUTPUT SWITCH CONTROL
Table 50: VrefO0 Truth Table
VrefO0
Source
VrefO0
Buffer
VrefO0
Buffer
Enable
TS PD
Register
Control
GPIO9
Analog Mode
Enable
TS PD
Selection
Selection
Selection
Function
Enable
Matrix
out78
Buffer
state
Output
switch
Note
register
[856:855]= 11,
means enable
register
[623]
register
[655:654]
register
[653]
register
[651]
register
[650]
None
00
01
0
0
0
0
0
0
0
0
0
0
Disable
Disable
Off
Off
Off
Off
VrefO0 is all off
VrefO0 select ACMP0H;
output has no buffer;
pd comes from register
[653]
01
01
01
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
Enable
Disable
Enable
Off
On
On
On
Off
On
VrefO0 select ACMP0H;
output has buffer;
pd comes from register
[653]
ACMP0H_Vref
01
01
01
01
10
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
Disable
Enable
Disable
Enable
Disable
Off
Off
On
On
Off
Off
On
Off
On
Off
VrefO0 select ACMP0H;
output has no buffer;
pd comes from matrix78
VrefO0 select ACMP0H;
output has buffer;
pd comes from matrix78
VrefO0 select ACMP1H;
output has no buffer;
pd comes from register
[653]
10
10
10
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
Enable
Disable
Enable
Off
On
On
On
Off
On
VrefO0 select ACMP1H;
output has buffer;
pd comes from register
[653]
ACMP1H_Vref
10
10
10
10
11
11
11
11
11
11
11
11
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
Disable
Enable
Off
Off
On
On
Off
Off
On
On
Off
Off
On
On
Off
On
Off
On
Off
Off
Off
On
Off
Off
Off
On
VrefO0 select ACMP1H;
output has no buffer;
pd comes from matrix78
VrefO0 select ACMP1H;
output has buffer;
pd comes from matrix78
TS enable comes from
register [650]
TS function
TS enable comes from
Matrix78
11.4 TRUTH TABLE FOR VREF1 BUFFER AND OUTPUT SWITCH CONTROL
Table 51: VrefO1 Truth Table
VrefO1
Source
VrefO1
Buffer
GPIO2
Analog Mode
Enable
Selection Selection
Function
Enable
Buffer
state
Output
switch
Note
registers
[708:707]= 11,
means enable
register
[656]
registers
[658:657]
None
00
01
01
01
01
0
0
0
1
1
Disable
Disable
Enable
Disable
Enable
Off
Off
Off
On
On
Off
Off
On
Off
On
VrefO1 is all off
VrefO1 select ACMP2L; output has no buffer; pd come from register [656]
VrefO1 select ACMP2L; output has buffer; pd come from register [656]
ACMP2L_Vref
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Table 51: VrefO1 Truth Table(Continued)
VrefO1
Source
VrefO1
Buffer
GPIO2
Analog Mode
Enable
Selection Selection
Function
Enable
Buffer
state
Output
switch
Note
registers
[708:707]= 11,
means enable
register
[656]
registers
[658:657]
10
10
10
10
0
0
1
1
Disable
Enable
Disable
Enable
Off
Off
On
On
Off
On
Off
On
VrefO1 select ACMP2L; output has no buffer; pd come from register [656]
VrefO1 select ACMP2L; output has buffer; pd come from register [656]
ACMP3L_Vref
valid output mode
11.5 VREF BLOCK DIAGRAM
registers [3895:3890]
External Vref
(GPI7)
None
00
01
10
11
ACMP0H_Vref
GPIO9_aio_en
1
0
OP
pd
registers [3903:3898]
Vref Out_0 (GPIO9)
ACMP1H_Vref
registers [655:654]
register [653]
Temp Sensor
None
None
00
01
10
11
registers [3911:3906]
GPIO2_aio_en
1
0
OP
pd
Vref Out_1 (GPIO2)
ACMP2L_Vref
registers [3919:3914]
registers [658:657]
ACMP3L_Vref
register [656]
Figure 74: Voltage Reference Block Diagram
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11.6 VREF LOAD REGULATION
Note 1 It is not recommended to use Vref connected to external pin without buffer.
Note 2 Vref buffer performance is not guaranteed at VDD < 2.7 V.
330
320
310
300
290
280
270
260
250
240
VDD=5.5V
VDD=3.3V
VDD=2.7V
I, UA
Figure 75: Typical Load Regulation, Vref = 320 mV, T = -40 °C to +85 °C, Buffer - Enable
650
640
630
620
610
600
590
580
570
560
VDD=5.5V
VDD=3.3V
VDD=2.7V
I, UA
Figure 76: Typical Load Regulation, Vref = 640 mV, T = -40 °C to +85 °C, Buffer - Enable
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1290
1280
1270
1260
1250
1240
1230
1220
1210
1200
VDD=5.5V
VDD=3.3V
VDD=2.7V
I, UA
Figure 77: Typical Load Regulation, Vref = 1280 mV, T = -40 °C to +85 °C, Buffer - Enable
2030
2020
2010
2000
1990
1980
1970
1960
1950
1940
1930
1920
1910
VDD=5.5V
VDD=3.3V
VDD=2.7V
I, UA
Figure 78: Typical Load Regulation, Vref = 2016 mV, T = -40 °C to +85 °C, Buffer - Enable
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12 Clocking
12.1 GENERAL DESCRIPTION
The SLG46880/81 has three internal oscillators to support a variety of applications:
Oscillator0 (2.048 kHz)
Oscillator1 (2.048 MHz)
Oscillator2 (25 MHz)
There are two divider stages for each oscillator that gives the user flexibility for introducing clock signals to connection matrix, as
well as various other Macrocells. The pre-divider (first stage) for Oscillator allows the selection of /1, /2, /4 or /8 to divide down
frequency from the fundamental. The second stage divider has an input of frequency from the pre-divider, and outputs one of
eight different frequencies divided by /1, /2, /3, /4, /8, /12, /24 or /64 on Connection Matrix Input lines [27], [28], and [29]. Please
see Figure 82 for more details on the SLG46880/81 clock scheme.
Oscillator2 (25 MHz) has an additional function of 100 ns delayed startup, which can be enabled/disabled by register [525]. This
function is recommended to use when analog blocks are used along with the Oscillator.
The Matrix Power-down/Force On function allows switching off or force on the oscillator using an external pin. The Matrix Power-
down/Force On (Connection Matrix Output [72], [73], [74]) signal has the highest priority. The OSC operates according to the
Table 52.
Table 52: Oscillator Operation Mode Configuration Settings
OSC Enable
Signal from
CNT/DLY
Register:
Power-Down
or Force On by
Matrix Input
OSC
Operation
Mode
Signal From
Connection
Matrix
Register: Auto
Power-On or
Force On
External Clock
Selection
POR
Macrocells
0
1
X
1
X
X
X
X
X
X
X
X
OFF
Internal OSC is
OFF, logic is ON
1
1
1
0
0
0
1
1
0
0
1
X
X
X
1
X
X
X
OFF
ON
ON
ON
CNT/DLY re-
quires OSC
1
1
0
0
0
0
X
X
0
0
CNT/DLY does
not require OSC
OFF
Note: The OSC will run only when any macrocell that uses OSC is powered on.
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12.2 OSCILLATOR0 (2.048 KHZ)
From Connection Matrix
Output [72]
Power-down/Force On
Matrix Output control register [527]
OSC Power Mode
register [526]
2.048 kHz Pre-divided Clock
PD/FORCE ON
registers [531:530]
OSC0
Auto Power-On
Force Power-On
(2.048 kHz) OUT
0
0
1
WS
DIV /1 /2 /4 /8
Pre-divider
0
1
register [535]
1
/ 2
/ 3
GPI4 Ext. Clock
2
3
4
5
6
Ext. CLK Sel register [528]
To Connection Matrix
Input [22]
/ 4
/ 8
/ 12
/ 24
/ 64
7
registers [534:532]
Second Stage
Divider
Figure 79: Oscillator0 Block Diagram
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12.3 OSCILLATOR1 (2.048 MHZ)
From Connection Matrix
Output [73]
Power-down/Force On
Matrix Output control register [505]
OSC Power Mode
register [504]
2.048 MHz Pre-divided Clock
PD/FORCE ON
registers [508:507]
OSC1
Auto Power-On
Force Power-On
(2.048 MHz)OUT
0
0
1
DIV /1 /2 /4 /8
Pre-divider
0
1
GPI1 Ext. Clock
1
/ 2
/ 3
2
3
4
5
6
Ext. CLK Sel register [506]
To Connection Matrix
Input [21]
/ 4
/ 8
/ 12
/ 24
/ 64
7
registers [511:509]
Second Stage
Divider
Figure 80: Oscillator1 Block Diagram
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12.4 OSCILLATOR2 (25 MHZ)
From Connection Matrix
Output [74]
Power-down/Force On
Matrix Output control register [517]
OSC Power Mode
register [516]
25 MHz Pre-divided Clock
PD/FORCE ON
registers [521:520]
OSC2
(25 MHz)
Auto Power-On
OUT
0
0
Force Power-On
Startup delay
1
DIV /1 /2 /4 /8
Pre-divider
0
1
register [525]
1
/ 2
/ 3
GPI0 Ext. Clock
2
3
4
5
6
Ext. CLK Sel register [518]
To Connection Matrix
Input [23]
/ 4
/ 8
/ 12
/ 24
/ 64
7
registers [524:522]
Second Stage
Divider
Figure 81: Oscillator2 Block Diagram
12.5 CLOCK SCHEME
Each CNT/DLY within Multi-Function macrocell has its own additional clock divider connected to oscillators pre-divider. Available
dividers are:
OSC0/1, OSC0/8, OSC0/64, OSC0/512, OSC0/4096, OSC0/32768, OSC0/262144
OSC1/1, OSC1/8, OSC1/64, OSC1/512
OSC2/1, OSC2/4
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0
1
25 MHz Pre-divided clock
Div4
2
Div8
3
4
5
6
7
8
CNT/DLY/
ONESHOT/
FREQ_DET/
2.048 MHz Pre-divided clock
2.048 kHz Pre-divided clock
Div64
Div512
DLY_EDGE_DET
Div8
Div64
CNT overflow
Div512
9
Div4096
Div32768
Div262144
10
11
12
13
14
15
CNT4 overflow can be used as the clock
source for CNT0/DLY0 or DM00
CNT (x-1) overflow
from Connection Matrix Out
(separate for each CNT/DLY
macrocell)
CNT0/CNT1/CNT2/CNT3/CNT4
0
1
2
3
4
5
from Connection Matrix
Output [82]
Div4
from Connection Matrix
Output [83]
Div8
Div64
Div512
CNT/DLY/
ONESHOT/
FREQ_DET/
DLY_EDGE_DET
6
Div8
Div64
7
8
CNT overflow
Div512
9
Div4096
Div32768
Div262144
10
11
12
13
14
15
DM00_CNT_end can be used as the clock
source for DM01
CNT4 overflow
DM00
0
Div4
1
2
Div8
Div64
Div512
3
4
5
6
CNT/DLY/
ONESHOT/
FREQ_DET/
DLY_EDGE_DET
Div8
Div64
7
8
CNT overflow
Div512
9
Div4096
Div32768
Div262144
10
11
12
13
14
15
DM00_CNToverflow can be used as the clock source for DM01
DM01_CNToverflow can be used as the clock source for DM10
DM10_CNToverflow can be used as the clock source for DM11
DM11_CNToverflow is not connected to any other macrocell
DM_(x-1)_cnt_overflow
DM01/DM10/DM11
Figure 82: Clock Scheme
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12.6 CRYSTAL OSCILLATOR
The Crystal OSC provides high precision and stability of the output frequency. GPI5 and GPI4 are input and output, respectively,
of an inverting amplifier which is configured for use as an On-chip Oscillator, as shown in Figure 84. Either a quartz crystal or a
ceramic resonator may be used. C1 and C2 should always be equal for both crystals and resonators. The optimal value of the
capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the
environment. Refer to Table 53. For the ceramic resonators, the capacitor values given by the manufacturer should be used. It is
possible to use an external clock source, it must be connected to GPI4. In this case no external components are required.
The Power-down Mode is paired with temperature sensor, Section 20. If it is enabled for Crystal OSC, it is not available for Temp
Sensor and vice versa. However, it is possible to enable Power-down Mode for Crystal OSC and Temp Sensor simultaneously.
register [894]
POR
Connection Matrix Output [78]
PWR ON
GPI5
register [895]
Crystal OSC
S1
S0
GPI4
To Connection Matrix Input [51]
Figure 83: Crystal OSC Block Diagram
C1
SLG46880/81
GPI5
R1
1MΩ
Crystal
GPI4
R2
C2
Figure 84: External Crystal Connection
Table 53: External Components Selection Table
f (MHz)
C1, C2
33 pF
22 pF
15 pF
10 pF
R2
5
5 kΩ
10
15
20
1 kΩ
500 Ω
270 Ω
12.7 EXTERNAL CLOCKING
The SLG46880/81 supports several ways to use an external, higher accuracy clock as a reference source for internal opera-
tions.
12.7.1 Crystal OSC Mode
When register [1136] is set to 1, an external crystal can be connected to GPI5 and GPI4 for supplying an accurate clock source.
See Section 12.6. An external clocking signal on GPI4 can be used in place of the crystal. The high and low limits for crystal fre-
quency that can be selected are 40 MHz and 32.75 kHz.
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12.7.2 GPI4 Source for Oscillator0 (2.048 kHz)
When register [528] is set to 1, an external clocking signal on GPI4 will be routed in place of the internal oscillator derived 2.048
kHz clock source. See Figure 79. The high and low limits for external frequency are 0 MHz and 20 MHz.
12.7.3 GPI1 Source for Oscillator1 (2.048 kHz)
When register [506] is set to 1, an external clocking signal on GPI1 will be routed in place of the internal oscillator derived 2.048
MHz clock source. See Figure 80. The high and low limits for external frequency are 0 MHz and 70 MHz.
12.7.4 GPI0 Source for Oscillator2 (25 MHz)
When register [518] is set to 1, an external clocking signal on GPI0 will be routed in place of the internal oscillator derived 25
MHz clock source. See Figure 81. The high and low limits for external frequency are 0 MHz and 80 MHz.
12.8 OSCILLATORS POWER-ON DELAY
OSC enable
Power-On
Delay
CLK
Figure 85: Oscillator Startup Diagram
Note 1 OSC power mode: “Auto Power-On”.
Note 2 “OSC enable” signal appears when any macrocell that uses OSC is powered on.
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900
850
800
750
700
650
600
550
500
2.3
2.5
2.7
3
3.3
3.6
4
4.2
4.5
5
5.5
VDD (V)
Figure 86: Oscillator0 Maximum Power-On Delay vs. VDD at T = 25 °C, OSC0 = 2.048 kHz
1000
800
600
400
200
0
2.3
2.5
2.7
3
3.3
3.6
4
4.2
4.5
5
5.5
VDD (V)
Figure 87: Oscillator1 Maximum Power-On Delay vs. VDD at T = 25 °C, OSC1 = 2.048 MHz
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147
127
107
87
Start with Delay
Normal start
67
47
27
7
2.3
2.5
2.7
3
3.3
3.6
4
4.2
4.5
5
5.5
VDD (V)
Figure 88: Oscillator2 Maximum Power-On Delay vs. VDD at T = 25 °C, OSC2 = 25 MHz
12.9 OSCILLATORS ACCURACY
Note: OSC power setting: Force Power-On; Clock to matrix input - enable; Bandgap: turn on by register - enable.
ꢂ8ꢀ
ꢂ8ꢅꢄꢃ
ꢂ8ꢅꢃ
ꢂ8ꢅꢂꢃ
ꢂ
ꢀ8ꢁꢄꢃ
ꢀ8ꢁꢃ
Fmax @ VDD = (2.5 to 5) V
Ftyp @ VDD = 3.3 V
ꢀ8ꢁꢂꢃ
Fmin @ VDD = (2.5 to 5.5) V
ꢀ8ꢁ
Rꢆꢅ
Rꢇꢅ
Rꢂꢅ
Rꢀꢅ
ꢅ
ꢀꢅ
ꢂꢅ
ꢇꢅ
ꢆꢅ
ꢃꢅ
ꢈꢅ
ꢄꢅ
ꢉꢅ
T (ꢀC)
Figure 89: Oscillator0 Frequency vs. Temperature, OSC0 = 2.048 kHz
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ꢄ8ꢅꢂꢃ
ꢄ8ꢅꢉꢃ
ꢄ8ꢅꢈꢃ
ꢄ8ꢅꢃꢃ
ꢄ8ꢅꢇꢃ
ꢄ8ꢅꢆꢃ
ꢄ8ꢅꢄꢃ
ꢄ8ꢅꢀꢃ
Fmax @ VDD = 5.0 V
Fmax @ VDD = 3.3 V
ꢄ8ꢅꢅꢃ
Fmax @ VDD = 2.5 V
Ftyp @ VDD = 3.3 V
Fmin @ VDD = 5.0 V
Fmin @ VDD = 3.3 V
Fmin @ VDD = 2.5 V
ꢀ8ꢁꢁꢃ
ꢀ8ꢁꢂꢃ
Rꢇꢅ
Rꢆꢅ
Rꢄꢅ
Rꢀꢅ
ꢅ
ꢀꢅ
ꢄꢅ
ꢆꢅ
ꢇꢅ
ꢃꢅ
ꢈꢅ
ꢉꢅ
ꢂꢅ
T (ꢀC)
Figure 90: Oscillator1 Frequency vs. Temperature, OSC1 = 2.048 MHz
25.8
25.6
25.4
25.2
25
24.8
24.6
24.4
24.2
24
Fmax @ VDD = 5.0 V
Fmax @ VDD = 3.3 V
Fmax @ VDD = 2.5 V
Ftyp @ VDD = 3.3 V
Fmin @ VDD = 5.0 V
Fmin @ VDD = 3.3 V
Fmin @ VDD = 2.5 V
23.8
23.6
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
T (ꢀC)
Figure 91: Oscillator2 Frequency vs. Temperature, OSC2 = 25 MHz
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7.5
2.048 kHz Total Error @ VDD = (2.3 to 5.5) V
7
6.5
6
25 MHz Total Error @ VDD = (2.3 to 5.5) V
2.048 MHz Total Error @ VDD = (2.3 to 5.5) V
5.5
5
4.5
4
3.5
3
2.5
2
1.5
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
T (ꢀC)
Figure 92: Oscillators Total Error vs. Temperature
Note: For more information see Section 3.6.
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13 Power-On Reset
The SLG46880/81 has a Power-On Reset (POR) macrocell to ensure correct device initialization and operation of all macrocells
in the device. The purpose of the POR circuit is to have consistent behavior and predictable results when the VDD power is first
ramping to the device, and also while the VDD is falling during Power-down. To accomplish this goal, the POR drives a defined
sequence of internal events that trigger changes to the states of different macrocells inside the device, and finally to the state of
the IO pins.
13.1 GENERAL OPERATION
The SLG46880/81 is guaranteed to be powered down and non-operational when the VDD voltage (voltage on VDD) is less than
Power-Off Threshold (see in Table 3.4 and Table 7), but not less than -0.6 V. Another essential condition for the chip to be powered
down is that no voltage higher (Note) than the VDD voltage is applied to any other PIN. For example, if VDD voltage is 0.3 V,
applying a voltage higher than 0.3 V to any other PIN is incorrect, and can lead to incorrect or unexpected device behavior.
Note: There is a 0.6 V margin due to forward drop voltage of the ESD protection diodes.
To start the POR sequence in the SLG46880/81, the voltage applied on the VDD should be higher than the Power-On threshold
(Note). The full operational VDD range for the SLG46880/81 is 2.3 V to 5.5 V. This means that the VDD voltage must ramp up to
the operational voltage value, but the POR sequence will start earlier, as soon as the VDD voltage rises to the Power-On threshold.
After the POR sequence has started, the SLG46880/81 will have a typical Startup Time (see in Table 6 and Table 7) to go through
all the steps in the sequence, and will be ready and completely operational after the POR sequence is complete.
Note: The Power-On threshold is defined in Table 3.4 and Table 7.
To power down the chip the, VDD voltage should be lower than the operational and to guarantee that chip is powered down, it
should be less than Power-Off Threshold.
All PINs are in high impedance state when the chip is powered down and while the POR sequence is taking place. The last step
in the POR sequence releases the IO structures from the high impedance state, at which time the device is operational. The pin
configuration at this point in time is defined by the design programmed into the chip. Also, as it was mentioned before, the voltage
on PINs can’t be bigger than the VDD, this rule also applies to the case when the chip is powered on.
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13.2 POR SEQUENCE
The POR system generates a sequence of signals that enable certain macrocells. The sequence is shown in Figure 93.
VDD
t
t
t
t
t
t
t
t
POR_NVM
(reset for NVM)
NVM_ready_out
POR_GPI
(reset for input enable)
POR_LUT
(reset for LUT output)
POR_CORE
(reset for DLY/OSC/DFF
/LATCH/Pipe DLY
POR_OUT
(generate low to high to matrix)
POR_GPO
(reset for output enable)
Figure 93: POR Sequence
As can be seen from Figure 93, after the VDD has started ramping up and crossed the Power-On threshold, first, the on-chip NVM
memory is reset. Next, the chip reads the data from NVM, and transfers this information to a CMOS LATCH that serves to configure
each macrocell, and the Connection Matrix which routes signals between macrocells. The third stage causes the reset of the input
pins, and then to enable them. After that, the LUTs are reset and become active. After LUTs, the Delay cells, OSCs, DFFs,
LATCHES, and Pipe Delay are initialized. Only after all macrocells are initialized, internal POR signal (POR macrocell output)
goes from LOW to HIGH (POR_OUT in Figure 93). The last portion of the device to be initialized is the output pins, which transition
from high impedance to active at this point.
The typical time that takes to complete the POR sequence varies by device type in the GreenPAK family. It also depends on many
environmental factors, such as: slew rate, VDD value, temperature, and even will vary from chip to chip (process influence).
13.3 MACROCELLS OUTPUT STATES DURING POR SEQUENCE
To have a full picture of SLG46880/81 operation during powering and POR sequence, refer to Figure 94, which describes the
macrocell output states during the POR sequence.
First, before the NVM has been reset, all macrocells have their output set to logic LOW (except the output pins which are in high
impedance state). On the next step, some of the macrocells start initialization: input pins output state becomes LOW; LUTs also
output LOW. After that input pins are enabled. Next, only LUTs are configured. Then, all other macrocells are initialized. After
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macrocells are initialized, internal POR matrix signal switches from LOW to HIGH. The last are output pins that become active
and determined by the input signals.
VDD
Guaranteed HIGH before POR_GPI
t
VDD_out
to matrix
t
t
Input PIN _out
to matrix
Determined by External Signal
Determined by Input signals
LUT_out
to matrix
t
Programmable Delay_out
to matrix
Determined by Input signals
Starts to detect input edges
t
Determined by initial state
DFF/LATCH_out
to matrix
Determined by Input signals
Determined by initial value
settings
t
t
t
t
Delay_out
to matrix
Determined by Input signals
Starts to detect input edges
POR_out
to matrix
Ext. GPO
Tri-state
Determined by input signals
Output State Unpredictable
Figure 94: Internal Macrocell States during POR Sequence
13.3.1 Initialization
All internal macrocells by default have initial low level. Starting from indicated power-up time of 1.64 V to 2.11 V, macrocells in
SLG46880/81 are powered on while forced to the reset state. All outputs are in Hi-Z and chip starts loading data from NVM. Then
the reset signal is released for internal macrocells and they start to initialize according to the following sequence:
1. Input pins, Pull-up/down.
2. LUTs.
3. DFFs, Delays/Counters, Pipe Delay, OSCs, ACMPs.
4. POR output to matrix.
5. Output pin corresponds to the internal logic.
The Vref output pin driving signal can precede POR output signal going high by 3 µs to 5 µs. The POR signal going high indicates
the mentioned power-up sequence is complete.
Note: The maximum voltage applied to any pin should not be higher than the VDD level. There are ESD Diodes between pin →
VDD and pin → GND on each pin. Exceeding VDD results in leakage current on the input pin, and VDD will be pulled up, following
the voltage on the input pin.
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13.3.2 Power-Down
VDD (V)
2 V
1.49 V
0.98 V
1 V Vref Out Signal
1 V
Time
Not guaranteed output state
Figure 95: Power-Down
During powerdown, macrocells in SLG46880/81 are powered off after VDD falling down below Power-Off Threshold. Please note
that during a slow rampdown, outputs can possibly switch state.
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14 Asynchronous State Machine Subsystem
14.1 ASM SUBSYSTEM OVERVIEW
The Asynchronous State Machine (ASM) Subsystem is designed to allow the user to create state machines with between 2 to 12
states. The user has flexibility to define the available states, the available state transitions, and the input signals (a, b, c …) that
will cause transitions from one state to another state, as shown in Figure 96.
The ASM Sybsystem can persist in 1 of 12 states at any given time and the ASM Current State can be read via I2C. See Section
19.6.2 for details.
The ASM Subsystem includes several discrete macrocells, including the ASM macrocell, four Dynamic Memory (DMx_x) macro-
cells, three Matrix Interface (MIx) macrocells, and one f(1) Computation Macrocell. These macrocells are designed to work as a
system for building user defined state machines. More information on each of these various macrocells can be found in the
following chapters:
ASM Macrocell – Section 15.
Dynamic Memory (DM) Macrocells – Section 16.
f(1) Computation Macrocell – Section 17
Matrix Interface (MI) Macrocells Section 18.
.
The ASM Subsystem has a total of 25 digital input signal lines, as shown in Figure 97, which all come from the Connection Matrix
outputs. Of these 25 digital input signals, 3 are user selectable inputs going directly from the Connection Matrix to the three Matrix
Interface (MI) macrocells. There are a total of 16 input signals that go to the DMx_x macrocell, four per macrocell. There is 1
ASM_nReset input that is for driving a state transition in both the ASM macrocell and the f(1) Computation Macrocell to an Initial/
Reset state. It is possible to use one macrocell only (MI or DM) for state to state transitions. There are 4 digital input signals
coming from the Connection Matrix to the f(1) Computation Macrocell. There is also 1 dedicated Interrupt input signal to the f(1)
Computation Macrocell that will halt any active operations and transfer control back to the ASM macrocell.
There are a total of 8 analog inputs coming from various pins which can be muxed into the positive input for the f(1) Analog
Comparator inside the f(1) Computation Macrocell. The f(1) Analog Comparator can be re-programmed for analog input source
and negative input reference settings. The user selections for both positive input signal and negative reference are included as
part of the information stored in the f(1) Command Register Table. This allows the user to make different analog measurements
that are state dependent in their analog sources and reference settings.
The ASM Subsystem has a total of 21 digital output signal lines, as shown in Figure 97. There are a total of 4 output signals which
go to the Connections Matrix inputs, and from there can be routed to other internal macrocells or pins. The 4 outputs are user
defined for each of the possible 12 states. There are a total of 8 output signals which go directly to the 8 GPOs. The 8 outputs
are user defined for each of the possible 12 states. Each of the three macrocells, DM0_0, DM0_1 and f(1) have three output
signals that go to the Connection Matrix.
In using this macrocell, the user must take into consideration the critical timing required on all input and output signals. The timing
waveforms and timing specifications for this macrocell are all measured relative to the input signals (which come into the macrocell
on the Connection Matrix outputs) and on the outputs from the macrocell (which are direct connections to Connection Matrix
inputs). The user must consider any delays from other logic and internal chip connections, including IO delays, to insure that
signals are properly processed, and state transitions are deterministic.
It is also important to note that the timing for the ASM Subsystem will change based on changes in temperature and system
voltage. The user design that implements a state machine function must take into consideration, and be tolerant of, this variation
The GPAK Designer development tools support user designs for the ASM Subsystem at both the physical level and logic level.
Figure 96 is a representation of the user design at the logical level, and Figure 97 shows the physical resources inside the various
macrocells in the ASM Subsystem. To best utilize this subsystem, the user must develop a logical representation of their desired
state machine, as well as a physical mapping of the input and outputs required for the desired functionality.
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Off
a
d
c
Normal
Speed
Standby
Fault
b
e
f
g
h
High
Speed
Figure 96: Asynchronous State Machine State Transitions
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Analog Inputs to
f(1) Computation Macrocell
ASM Subsystem
8
1
MI2
12 State ASM
Macrocell
1
MI1
1
MI0
4
DM1_0
Connection
Matrix
4
DM1_1
4
Out
DM0_0
4
DM0_1
1
ASM_nReset
1
f1_Interrupt
f(1)
4
In
3
3
3
4
Connection Matrix Output RAM Signals
8
Pin Output RAM Signals
to GPO Pin
Outputs
Figure 97: Connection Matrix to ASM Subsystem
14.2 ASM SUBSYSTEM INPUT SIGNALS
The ASM Subsystem has a total of 25 digital input signal lines, as shown in Figure 98, which all come from the Connection Matrix
outputs. Of these 25 input signals, 3 are user selectable inputs going directly from the Connection Matrix to the three Matrix
Interface (MI) macrocells. There are a total of 16 input signals that go to the DMx_x macrocell, four per macrocell. There is 1
ASM_nReset input that is for driving a state transition in both the ASM macrocell and the f(1) Computation Macrocell to an Initial/
Reset state. There are 4 digital input signals coming from the Connection Matrix to the f(1) Computation Macrocell. There is also
1 dedicated Interrupt input to the f(1) Computation Macrocell that will halt any active operations and transfer control back to the
ASM macrocell. Each of the 25 input signals are level sensitive.
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There are a total of 16 digital input signals to theASM Subsystem which are inputs directly to the DM macrocells. These 16 signals
are shown in Figure 98, highlighted in blue. While there are 4 input signals coming from the Connection Matrix and going to each
DMx_ x macrocell, there is only 1 output signal from each of these macrocells, which goes directly to the ASM macrocell. There
are also 3 signal lines that come directly from the Connection Matrix and go to the three Matrix Interface (MI) macrocells which
can drive state transitions. These signals are shown in Figure 98, highlighted in green. This sets an upper bound on the number
of transitions that the user can select going out of a particular state to be 7, shown in Figure 99. There is no limitation on the
number of unique transitions that can be supported going into a particular state, the user can select to have transitions going from
a state to all other states, shown in Figure 100. Each of these input signals to the ASM macrocell is level sensitive, and active
high. A high level input will trigger a state transition.
There are a total of 8 analog inputs coming from various pins which can be muxed into the positive input for the f(1) Analog
Comparator inside the f(1) Computation Macrocell. These 8 signals are shown in Figure 98, highlighted in pink. The f(1) Analog
Comparator can be re-programmed for analog input source and negative input reference settings. The user selections for both
positive input signal and negative reference are included as part of the information stored in the f(1) Command Register Table.
This allows the user to make different analog measurements that are state dependent in their analog sources and reference
settings.
Also, there are 4 digital inputs that can be connected with any Connection Matrix output by the f(1) Computational Macrocell
commands. These 4 signals are shown in highlighted in light blue.
The ASM macrocell also has a ASM_nReset input. This input to the ASM macrocell is level sensitive and active low. This signal
is shown in Figure 98, highlighted in yellow. An active signal on this input will drive an immediate state transition to the user-
defined Initial/Reset state. The user can choose which state within the ASM Editor inside GPAK Designer will be the reset state.
There is also 1 dedicated f1_Interrupt input to the f(1) Computation Macrocell that will halt any active operations and transfer
control back to the ASM macrocell. This signal is shown in Figure 98, also highlighted in yellow.
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Analog Inputs to
f(1) Computation Macrocell
ASM Subsystem
8
1
MI2
12 State ASM
Macrocell
1
MI1
1
MI0
4
DM1_0
Connection
Matrix
4
DM1_1
4
Out
DM0_0
4
DM0_1
1
ASM_nReset
1
f1_Interrupt
f(1)
4
In
3
3
3
4
Connection Matrix Output RAM Signals
8
Pin Output RAM Signals
to GPO Pin
Outputs
Figure 98: ASM Subsystem Input Signals
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State 1
State 7
State 2
State 0
State 6
State 3
State5
State 4
Figure 99: Maximum 7 State Transitions out of a Given State
State 1
State 11
State 2
State 10
State 9
State 3
State 4
State 0
State 8
State 5
State 7
State 6
Figure 100: Maximum 11 State Transitions into Given State
14.3 ASM SUBSYSTEM OUTPUT SIGNALS
The ASM subsystem has a total of 21 output signal lines, as shown in Figure 101.
There are a total of 4 output signals from the ASM macrocell which go to the Connections Matrix inputs and from there can be
routed to other internal macrocells or pins. These signals are shown in Figure 101, highlighted in green. The 4 outputs are user
defined for each of the possible 12 states. The user selection for the output states is held in the Connection Matrix Output RAM.
There are a total of 8 output signals from the ASM macrocell which go directly to the 8 GPOs. These signals are shown in Figure
101, highlighted in blue. The 8 outputs are user defined for each of the possible 12 states. The user selection for the output states
is held in the Pin Output RAM. Each of these GPOs has a single selection bit which defines the GPO input source as either the
ASM Output RAM signal or the Connection Matrix signal.
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Two of the Dynamic Memory macrocells, DM0_0 and DM0_1, can be used as either a resource for generating input signals for
driving state transitions in the ASM macrocell, or to generate signals for use in other parts of the user design. When used to
generate signals for purposes other than ASM state transitions, each of these macrocells has three output signals that go to the
Connection Matrix, and from there can be routed to other internal macrocells or pins. Each of these macrocells has a total of 3
output signals of this type. These signals are shown in Figure 101, highlighted in yellow.
The f(1) Computation Macrocell has 3 output signals that go to the Connection Matrix, and from there can be routed to other
internal macrocells or pins. These signals are shown in Figure 101, highlighted in pink.
Analog Inputs to
f(1) Computation Macrocell
ASM Subsystem
8
1
MI2
12 State ASM
Macrocell
1
MI1
1
MI0
4
DM1_0
Connection
Matrix
4
DM1_1
4
Out
DM0_0
4
DM0_1
1
ASM_nReset
1
f1_Interrupt
f(1)
4
In
3
3
3
4
Connection Matrix Output RAM Signals
8
Pin Output RAM Signals
to GPO Pin
Outputs
Figure 101: ASM Subsystem Input Signals
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14.4 BASIC ASM_SUBSYSTEM TIMING
The basic state transition timing from input on one of 19 state transition input lines (4 going into each DMx_x and 3 from Connection
Matrix going directly to the ASM macrocell) to the time when the 4 Connection Matrix Output RAM signals and 8 Pin Output RAM
signals change is shown in Figure 102 and Figure 103. The time from a valid input signal to the time that there is a valid change
of state, and valid signals on the 4 Connection Matrix Output RAM signals and 8 Pin Output RAM signals is State Machine Output
Delay Time (Tst_out_delay).
At the point in time that the Connection Matrix Output RAM signals and Pin Output RAM signals are changing, the f(1) Computation
Macrocell is prepared for executing commands coded for the new state, if the user has coded commands to execute. Based on
the chosen commands, the f(1) Computation Macrocell outputs can change a number of times before the f(1) finishes for the new
state. The ASM Subsystem will not be ready for the next state transition until the f(1) Computation Macrocell has completed the
commands for the new state, or until it is reset by asserting the f1_Interrupt input from the Connection Matrix. The period of time
between the input on one of the 7 inputs to the ASM macrocell and the ASM subsystem being ready for the next state transition
input is State Machine Sequential Delay Time (Tst_sequential_delay).
From the input on one of 19 state transition input lines, there is a delay before the outputs are latched from the DM0_0 and DM0_1
macrocells, noted as DM Connection Matrix Output Delay Time (Tst_dmlatch_delay).
During state transitions, there will be no change in output levels on other states than the one state going active→inactive and the
other state going inactive→active
a
State 0
State 1
Figure 102: State Transition
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Tst_output_delay
Tst_sequential_delay
Detect inputs for
next state transition
ASM Input (a)
ASM Pin Output RAM <7:0>
State 0
State 0
State 1
State 1
ASM Connection Matrix Output RAM<3:0>
Tst_dmlatch_delay
KEEP
F(1) Output
(to matrix)
KEEP
DM Output
(to matrix)
State 0
KEEP
State 1
(the output data will be kept
if DM function is not used)
Figure 103: State Transition Timing
14.5 ASM POWER CONSIDERATIONS
A benefit of the asynchronous nature of this macrocell is that it will consume power only during state transitions. Shown in Figure
104 and Figure 105, the current consumption of the macrocell will be a fraction of a µA between state transitions, and will rise
only during state transitions. This is assuming that the DLY/CNT inside each DMx_x macrocells are also in-active. See Table 10
to find average current during state transitions.
a
State 0
State 1
Figure 104: State Transition
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Tst_output_delay
Tst_sequential_delay
Detect inputs for
next state transition
ASM Input (a)
ASM Pin Output RAM <7:0>
State 0
State 0
State 1
State 1
ASM Connection Matrix Output RAM<3:0>
Tst_dmlatch_delay
KEEP
KEEP
F(1) Output
(to matrix)
KEEP
DM Output
(to matrix)
State 0
State 1
Average Active ASM Power
Sub ΞA Inactive Power Consumption
(Assumes that the DLY/CNT inside each
DMx_x is also inactive)
ASM Power Consumption
Figure 105: State Transition Timing and Power Consumption
14.6 ASYNCHRONOUS STATE MACHINES VS. SYNCHRONOUS STATE MACHINES
It is important to note that this macrocell is designed for asynchronous operation, which means the following:
1. No clock source is needed, it reacts only to input signals.
2. The input signals do not have to be synchronized to each other, the macrocell will react to the earliest valid signal for state
transition.
3. This macrocell does not have traditional set-up and hold time specifications which are related to incoming clock, as this
macrocell has no clock source.
4. The macrocell only consumes power while in state transition.
14.7 ASM SPECIAL CASE TIMING CONSIDERATIONS
14.7.1 State Transition Pulse Input Timing
All inputs to the ASM macrocell are level sensitive. If the input to the state machine macrocell for a state transition is a pulse,
there is a minimum pulse width on the input to the state machine macrocell (as measured at the matrix input to the macrocell)
which is guaranteed to result in a state transition shown in Figure 106 and Figure 107. This pulse width is defined by the State
Machine Input Pulse Acceptance Time (Tst_pulse). If a pulse width that is shorter than Tst_pulse is input to the state machine
macrocell, it is indeterminate whether the state transition will happen or not. If a pulse that is rejected (invalid due to the pulse
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width being narrower than the guaranteed minimum of Tst_pulse), this will not stop a valid pulse on another state transition input
that does meet minimum pulse width.
a
State 0
State 1
Figure 106: State Transition
Tst_output_delay
Tst_sequential_delay
Detect inputs for
next state transition
ASM Input (a)
Tst_pulse
Tst_pulse
ASM Pin Output RAM <7:0>
State 0
State 0
State 1
State 1
ASM Connection Matrix Output RAM<3:0>
Tst_dmlatch_delay
KEEP
KEEP
F(1) Output
(to matrix)
State 0
KEEP
State 1
DM Output
(to matrix)
(the output data will be kept
if DM function is not used)
Figure 107: State Transition Pulse Input Timing
14.7.2 State Transition Competing Input Timing
There will be situations where two input signals can be valid inputs that will drive two different state transitions from a given state.
In that sense, the two signals are “competing” (signals a and b in Figure 108), and the signal that arrives sooner should drive the
state transition that will “win”, or drive the state transition. If one signal arrives Tst_comp before the other one, it is guaranteed to
win, and the state transition that it codes for will be taken, as shown in Figure 109. If the two signals arrive within Tst_comp of each
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other, it will be indeterminate which state transition will win, but one of the transitions will take place as long as the winning signal
satisfies the pulse width criteria described in the paragraph above, as shown in Figure 110.
a
b
State 0
State 1
State 2
Figure 108: State Transition - Competing Inputs
Tst_output_delay
Tst_sequential_delay
Detect inputs for
ASM Input (a)
next state transition
ASM Input (b)
Tst_comp
State 0
State 1 or 2
State 1 or 2
ASM Pin Output RAM <7:0>
ASM Connection Matrix Output RAM<3:0>
State 0
Tst_dmlatch_delay
F(1) Output
(to matrix)
KEEP
KEEP
State 0
KEEP
State 1 or 2
DM Output
(to matrix)
(the output data will be kept
if DM function is not used)
Figure 109: State Transition Timing - Competing Inputs Indeterminate
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Tst_output_delay
Tst_sequential_delay
Detect inputs for
next state transition
ASM Input (a)
ASM Input (b)
Tst_comp
State 0
State 0
State 1
State 1
ASM Pin Output RAM <7:0>
ASM Connection Matrix Output RAM<3:0>
Tst_dmlatch_delay
F(1) Output
(to matrix)
KEEP
KEEP
State 0
KEEP
State 1
DM Output
(to matrix)
(the output data will be kept
if DM function is not used)
Figure 110: State Transition Timing - Competing Inputs Determinable
14.7.3 ASM State Transition Sequential Timing
It is possible to have a valid input signal for a transition out from a particular state be active before the state is active. If this is the
case, the macrocell will only stay in that particular state for Tst_sequential_delay time before making the transition to the next state.
An example of this sequential behavior is shown in Figure 111 and the associated timing is shown in Figure 112.
a
b
State 0
State 1
State 2
Figure 111: State Transition - Sequential
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Tst_output_delay
Tst_sequential_delay
Tst_output_delay
Tst_sequential_delay
ASM Input (a)
ASM Input (b)
State 0
State 1
State 1
State 2
State 2
ASM Pin Output RAM <7:0>
ASM Connection Matrix
Output RAM<3:0>
State 0
Tst_dmlatch_delay
Tst_dmlatch_delay
F(1) Output
(to matrix)
KEEP
KEEP
KEEP
DM Output
(to matrix)
State 0
State 1
State 2
KEEP
KEEP
Figure 112: State Transition - Sequential Timing
14.7.4 State Transition Closed Cycling
It is possible to have a closed cycle of state transitions that will run continuously, if there are valid inputs that are active at the
same time. The rate at which the state transitions will take place is determined by Tst_sequential_delay, which determines the timing
from one state transition signal that is accepted (and causes a state transition) to the ASM Subsystem being ready for the next
input signal. The example shown in Figure 113 involves cycling between two states, but any number of two – twelve states can
be included in state transition closed cycling of this nature. Figure 114 shows the associated timing for closed cycling.
a
State 0
State 1
b
Figure 113: State Transition - Closed Cycling
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Tst_output_delay
Tst_sequential_delay
Tst_output_delay
Tst_sequential_delay
Tst_output_delay
Tst_sequential_delay
ASM Input (a)
ASM Input (b)
State 0
State 1
State 1
State 0
State 0
State 1
State 1
ASM Pin Output RAM <7:0>
ASM Connection Matrix
Output RAM<3:0>
State 0
Tst_dmlatch_delay
Tst_dmlatch_delay
Tst_dmlatch_delay
F(1) Output
(to matrix)
KEEP
KEEP
KEEP
KEEP
DM Output
(to matrix)
State 0
KEEP
State 1
KEEP
State 0
KEEP
State 1
Figure 114: State Transition - Closed Cycling Timing
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15 Asynchronous State Machine Macrocell
15.1 ASYNCHRONOUS STATE MACHINE OVERVIEW
The Asynchronous State Machine macrocell is one of several macrocells in the Asynchronous State Machine Subsystem, and
it’s specific role is to hold one active state at a time, and to facility user defined state transitions in a fast and power efficient
manner. This macrocell is designed to allow the user to create state machines with between 2 to 12 states. When combined with
the other macrocells in the ASM subsystem [four Dynamic Memory (DMx_x) macrocells, three Matrix Interface (MIx) macrocells,
and one f(1) Computation Macrocell], the user has flexibility to define the available states, the available state transitions, and the
input signals (a, b, c …) that will cause transitions from one state to another state, as shown in the example in Figure 115.
The ASM macrocell has a total of 8 input signal lines, as shown in Figure 116, which come from a combination of three Matrix
Interface (MI) macrocell outputs and DM macrocell outputs. Of these 8 inputs, 3 are user selectable inputs coming from the three
Matrix Interface (MI) macrocells (one per macrocell) to the ASM macrocell. There are also 4 inputs that come from the DMx_x
macrocells (one per macrocell). There is 1 ASM_nReset input that is for driving a state transition in the ASM macrocell to a user
defined Initial/Reset state.
The ASM macrocell has a total of 12 output signal lines, as shown in Figure 117. There are a total of 4 output signals which go
to the Connections Matrix inputs, and from there can be routed to other internal macrocells or pins. The 4 output signals are user
defined for each of the possible 12 states. There are a total of 8 output signals which go directly to the 8 GPOs. The 8 outputs
are user defined for each of the possible 12 states.
In using this macrocell, the user must take into consideration the critical timing required on all input and output signals. The timing
waveforms and timing specifications for this macrocell are all measured relative to the input signals (which come into the macrocell
on the Connection Matrix outputs) and on the outputs from the macrocell (which are direct connections to Connection Matrix
inputs). The user must consider any delays from other logic and internal chip connections, including IO delays, to insure that
signals are properly processed, and state transitions are deterministic.
It is also important to note that the timing for the ASM Subsystem will change based on changes in temperature and system
voltage. The user design that implements a state machine function must take into consideration, and be tolerant of this variation
The GPAK Designer development tools support user designs for the ASM macrocell at both the physical level and logic level.
Figure 116 is a representation of the user design at the logical level, and Figure 116 shows the physical resources inside the
various macrocells in the ASM Subsystem. To best utilize this subsystem, the user must develop a logical representation of their
desired state machine, as well as a physical mapping of the input and outputs required for the desired functionality.
Off
a
d
c
Normal
Speed
Standby
Fault
b
e
f
g
h
High
Speed
Figure 115: Asynchronous State Machine State Transitions
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State
Dependent
Memory
Connection Matrix
Pin Output
RAM
Output RAM
(12x4)
ASM State
Holding DFFs
from DM
Macrocells
(12x8)
DM0_0
DM0_1
DM1_0
DM1_1
State 0
State 0
State 0
State 1
State 2
State 3
State 4
State 5
State 6
State 7
State 8
State 9
State 10
State 11
Output Bits (4)
Output Bits (8)
State 1
Output Bits (4)
State 1
Output Bits (8)
State 2
Output Bits (4)
State 2
Output Bits (8)
State 3
Output Bits (4)
State 3
Output Bits (8)
State 4
Output Bits (4)
State 4
Output Bits (8)
ASM
Input
Matrix
State 5
Output Bits (4)
State 5
Output Bits (8)
from MI
Macrocell
State 6
Output Bits (4)
State 6
Output Bits (8)
MI0
MI1
MI2
State 7
Output Bits (4)
State 7
Output Bits (8)
State 8
Output Bits (4)
State 8
Output Bits (8)
State 9
Output Bits (4)
State 9
Output Bits (8)
State 10
Output Bits (4)
State 10
Output Bits (8)
State 11
Output Bits (4)
State 11
Output Bits (8)
from Connection
Matrix
ASM_nReset
to Connection
Matrix
to GPO Pin
Outputs
Figure 116: 12 State ASM Macrocell
15.2 ASM MACROCELL INPUT SIGNALS
The ASM macrocell has a total of 8 input signal lines, as shown in Figure 116, which come from a combination of Connection
Matrix outputs and DM macrocell outputs.
There are 3 user selectable input signals that come from the MIx macrocells (one per macrocell) to the ASM macrocell. These
signals are shown in Figure 118, highlighted in green. Each of these input signals are level sensitive and active high. A high level
signal on any of these inputs can be enabled to drive a state transition, depending on the coding in the ASM Input Matrix.
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There are 4 input signals that come from the DMx_x macrocells (one per macrocell). These signals are shown in Figure 118,
highlighted in blue. Each of these input signals are level sensitive and active high. A high level signal on any of these inputs can
be enabled to drive a state transition, depending on the coding in the ASM Input Matrix.
There is 1 ASM_nReset input that is for driving a state transition in the ASM macrocell to an user defined Initial/Reset state. This
signal is shown in Figure 118, highlighted in yellow. This input signal is level sensitive and active low.
State
Dependent
Memory
Connection Matrix
Output RAM
(12x4)
Pin Output
RAM
ASM State
Holding DFFs
from DM
Macrocells
(12x8)
DM0_0
DM0_1
DM1_0
DM1_1
State 0
State 0
State 0
State 1
State 2
State 3
State 4
State 5
State 6
State 7
State 8
State 9
State 10
State 11
Output Bits (4)
Output Bits (8)
State 1
Output Bits (4)
State 1
Output Bits (8)
State 2
Output Bits (4)
State 2
Output Bits (8)
State 3
Output Bits (4)
State 3
Output Bits (8)
State 4
Output Bits (4)
State 4
Output Bits (8)
ASM
Input
Matrix
State 5
Output Bits (4)
State 5
Output Bits (8)
from MI
Macrocell
State 6
Output Bits (4)
State 6
Output Bits (8)
MI0
MI1
MI2
State 7
Output Bits (4)
State 7
Output Bits (8)
State 8
Output Bits (4)
State 8
Output Bits (8)
State 9
Output Bits (4)
State 9
Output Bits (8)
State 10
Output Bits (4)
State 10
Output Bits (8)
State 11
Output Bits (4)
State 11
Output Bits (8)
from Connection
Matrix
ASM_nReset
to Connection
Matrix
to GPO Pin
Outputs
Figure 117: ASM Macrocell Input Signals
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15.2.1 ASM Macrocell Output Signals
The ASM macrocell has a total of 12 output signal lines, as shown in Figure 118.
There are a total of 4 output signals which go to the Connections Matrix inputs, and from there can be routed to other internal
macrocells or pins. These signals are shown in Figure 118, highlighted in green. The 4 outputs are user defined for each of the
possible 12 states. The user defined values for these outputs is stored in the Connection Matrix Output RAM which is 12 x 4 in
size (12 states x 4 outputs), for a total of 48 bits.
There are a total of 8 output signals which go directly to the 8 GPOs. These signals are shown in Figure 118, highlighted in blue.
The 8 outputs are user defined for each of the possible 12 states. The user defined values for these outputs is stored in the Con
nection Matrix Output RAM which is 12 x 8 in size (12 states x 8 outputs), for a total of 96 bits. Each of the 8 GPOs has an inter
-
-
nal mux that will either accept a signal from the outputs defined here, or directly from a Connection Matrix output. This mux in
each GPO is under control of a register bit.
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State
Dependent
Memory
Connection Matrix
Pin Output
RAM
Output RAM
(12x4)
ASM State
Holding DFFs
from DM
Macrocells
(12x8)
DM0_0
DM0_1
DM1_0
DM1_1
State 0
State 0
State 0
State 1
State 2
State 3
State 4
State 5
State 6
State 7
State 8
State 9
State 10
State 11
Output Bits (4)
Output Bits (8)
State 1
Output Bits (4)
State 1
Output Bits (8)
State 2
Output Bits (4)
State 2
Output Bits (8)
State 3
Output Bits (4)
State 3
Output Bits (8)
State 4
Output Bits (4)
State 4
Output Bits (8)
ASM
Input
Matrix
State 5
Output Bits (4)
State 5
Output Bits (8)
from MI
Macrocell
State 6
Output Bits (4)
State 6
Output Bits (8)
MI0
MI1
MI2
State 7
Output Bits (4)
State 7
Output Bits (8)
State 8
Output Bits (4)
State 8
Output Bits (8)
State 9
Output Bits (4)
State 9
Output Bits (8)
State 10
Output Bits (4)
State 10
Output Bits (8)
State 11
Output Bits (4)
State 11
Output Bits (8)
from Connection
Matrix
ASM_nReset
to Connection
Matrix
to GPO Pin
Outputs
Figure 118: ASM Macrocell Output Signals
15.3 ASM LOGICAL VS. PHYSICAL DESIGN
A successful design with the ASM macrocell must include both the logic level design, as well as the physical level design. The
GPAK Designer development software support user designs for the ASM macrocell at both the logic level and physical level.
The logic level design of the user defined state machine takes place inside the ASM Editor. In the ASM Editor, the user can
select and name states, define and name allowed state transitions, define the Initial/Reset state, and define the output values for
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the 8 outputs in the Pin Output RAM and 4 outputs in the Connection Matrix Output RAM. The physical level design takes place
in the general GPAK Designer window, and here the user makes connections for the sources for ASM input signals, as well as
making connections for destinations for ASM output signals.
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16 Dynamic Memory Macrocell
16.1 DYNAMIC MEMORY MACROCELL OVERVIEW
The ASM Sub-System includes several discrete macrocells, including the ASM macrocell, four Dynamic Memory (DMx_x) mac
-
rocells, and one f(1) Computation Macrocell. These macrocells are designed to work as a system for building user defined state
machines.
The Dynamic Memory (DM) macrocells have the characteristic that they can change internal configuration characteristics and
their connections to the Connection Matrix based on the current state of the State Machine (SM) macrocell. This is accomplished
by making different memory register bit settings contained within the macrocell active, based on the current active state of the
SM. This allows the user to “repurpose” the resources inside these macrocells to match the circuit needs in various states.
There are two different types of DM macrocells, which vary slightly in the resources available inside the DM macrocell, as well as
the connectivity to the Connection Matrix. The SLG46880/81 has a total of four DM macrocells. DM0_0 and DM0_1 have the
same structure and resources as each other, and DM1_0 and DM1_1 also have the same structure and resources as each other.
The DM0_x macrocells include all the functionality of the DM1_x macrocells, but they also have an output control capability, which
is optimized for using the output of this macrocell to drive IO pin output states though the Connection Matrix. The DM CNT included
in the DM0_x macrocells has more operating modes than the equivalent structure in the DM1_x macrocells.
Each DM macrocell has a DMx_x Configuration Register Table, which is a bank of 6 DMx_x Configuration Registers. The bits in
these registers hold user selections which define all functional aspects of the behavior for the DM macrocell, including input
connections from the Connection Matrix, DM LUT settings, DM CNT settings, and settings of muxing internal to the DM macrocell.
The fact that there are 6 Configuration Registers means that there can only be a total of six unique configurations for each DMx_x
macrocell. There are a total of twelve states, which means that the user can either re-use the configuration coded in a particular
DMx_x Operating Mode Register in more than one state, or not use some DMx_x macrocells in some states.
Each DM macrocell has a DMx_x Configuration Selection Table, which is a bank of 12 Configuration Selection Registers, one for
each state of the State Machine macrocell. The bits in these registers hold the user’s selection of DM functional behavior, by
mapping to a particular selection in the Configuration Register Table, based on the current state of the State Machine macrocell.
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16.2 DM0_0 AND DM0_1 MACROCELL ARCHITECTURE
DMx Configuration Selection Table
ASM 12 states
to 3 bits output
mapping table
3
12
ASM 12 states
to 2 bits output
mapping table
12
2
from ASM_state
from ASM_state
DMx Configuration Register Table
000
001
010
011
100
101
110
111
Not Used
DM0_x Config. Register0[55:0]
DM0_x Config. Register5[55:0]
Not Used
DM0_0 and DM0_1
Output to
ASM Input
Matrix
8 registers
from
Connection
Matrix
Output
Control
1 register
matrix_out
matrix_out
matrix_out
3-bitDM
LUT
4 registers
S1
S0
OUT0
OUT1
OUT2
2-bitDM
LUT
1 register
18 registers
from
Connection
Matrix
Outputs to
Connection
Matrix
S1
S0
8-bit DLY/
Edge Detect
matrix_out
00: all outputs are kept
01: DMOut bypass to OUT0,
others are kept
10: DMOut bypass to OUT1,
others are kept
11: DMOut bypass to OUT2,
others are kept
Supported Modes: Dly/Counter/One Shot/
Freq. Detect/Edge Detect/Reset Counter
Figure 119: DM0_0/DM0_1
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16.3 DM1_0 AND DM1_1 MACROCELL ARCHITECTURE
DMx Configuration Selection Table
12
3
ASM 12 states to 3 bits
output mapping table
from ASM_state
DMx Configuration Register Table
000
001
010
011
100
101
110
111
Not Used
DM1_x Config. Register0[55:0]
DM1_x Config. Register5[55:0]
Not Used
DM1_0 and DM1_1
8 registers
from
Connection
Matrix
1 register
matrix_out
matrix_out
matrix_out
3-bit DM
LUT
4 registers
S1
S0
Output
to ASM
Input
Matrix
Output
Control
2-bit DM
LUT
1 register
18 registers
from
Connection
Matrix
S1
S0
8-bit DLY/
Edge Detect
matrix_out
Supported Modes: Dly/Counter/One Shot/
Freq. Detect/Edge Detect/Reset Counter
Figure 120: DM1_0/DM1_1
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16.4 DMX_X MACROCELL INPUT SIGNALS
Each DMx_x macrocell has 4 digital input signals coming from the Connection Matrix and from there can be routed to other internal
macrocells or pins. These 4 signals are shown in Figure 121 and Figure 122, highlighted in blue.
DMx Configuration Selection Table
ASM 12 states
to 3 bits output
mapping table
3
12
ASM 12 states
to 2 bits output
mapping table
2
12
from ASM_state
from ASM_state
DMx Configuration Register Table
000
001
010
011
100
101
110
111
Not Used
DM0_x Config. Register0[55:0]
DM0_x Config. Register5[55:0]
Not Used
DM0_0 and DM0_1
Output to
ASM Input
Matrix
8 registers
from
Connection
Matrix
Output
Control
1 register
matrix_out
3-bit DM
LUT
4 registers
matrix_out
matrix_out
S1
S0
OUT0
OUT1
OUT2
2-bitDM
LUT
1 register
18 registers
from
Connection
Matrix
Outputs to
Connection
Matrix
S1
S0
8-bit DLY/
Edge Detect
matrix_out
00: all outputs are kept
01: DMOut bypass to OUT0,
others are kept
10: DMOut bypass to OUT1,
others are kept
11: DMOut bypass to OUT2,
others are kept
Supported Modes: Dly/Counter/One Shot/
Freq. Detect/Edge Detect/Reset Counter
Figure 121: DM0_0/DM0_1 Inputs
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DMx Configuration Selection Table
12
3
ASM 12 states to 3 bits
output mapping table
from ASM_state
DMx Configuration Register Table
000
001
010
011
100
101
110
111
Not Used
DM1_x Config. Regsiter0[55:0]
DM1_x Config. Register5[55:0]
Not Used
DM1_0 and DM1_1
8 registers
from
Connection
Matrix
1 register
matrix_out
matrix_out
matrix_out
3-bit DM
LUT
4 registers
S1
S0
Output
to ASM
Input
Matrix
Output
Control
2-bit DM
LUT
1 register
18 registers
from
Connection
Matrix
S1
S0
8-bit DLY/
Edge Detect
matrix_out
Supported Modes: Dly/Counter/One Shot/
Freq. Detect/Edge Detect/Reset Counter
Figure 122: DM1_0/DM1_1 Inputs
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16.5 DMX_X MACROCELL OUTPUT SIGNALS
Each DMx_ x macrocell has 1 digital output signal, which goes directly to the ASM Input Matrix inside the ASM Macrocell. This
signal is shown in Figure 123 and Figure 124, highlighted in blue.
Additionally, the DM0_0 and DM0_1 Macrocells each have 3 digital output signals which go to the Connection Matrix and from
there can be routed to other internal macrocells or pins. These 3 signals are shown in Figure 123, highlighted in green.
DMx Configuration Selection Table
ASM 12 states
to 3 bits output
mapping table
3
12
ASM 12 states
to 2 bits output
mapping table
2
12
from ASM_state
from ASM_state
DMx Configuration Register Table
000
001
010
011
100
101
110
111
Not Used
DM0_x Config. Register0[55:0]
DM0_x Config. Register5[55:0]
Not Used
DM0_0 and DM0_1
Output to
ASM Input
Matrix
8 registers
from
Connection
Matrix
Output
Control
1 register
matrix_out
matrix_out
matrix_out
3-bit DM
LUT
4 registers
S1
S0
OUT0
OUT1
OUT2
2-bitDM
LUT
1 register
18 registers
from
Connection
Matrix
Outputs to
Connection
Matrix
S1
S0
8-bit DLY/
Edge Detect
matrix_out
00: all outputs are kept
01: DMOut bypass to OUT0,
others are kept
10: DMOut bypass to OUT1,
others are kept
11: DMOut bypass to OUT2,
others are kept
Supported Modes: Dly/Counter/One Shot/
Freq. Detect/Edge Detect/Reset Counter
Figure 123: DM0_0/DM0_1 Outputs
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DMx Configuration Selection Table
12
3
ASM 12 states to 3 bits
output mapping table
from ASM_state
DMx Configuration Register Table
000
001
010
011
100
101
110
111
Not Used
DM1_x Config. Register0[55:0]
DM1_x Config. Register5[55:0]
Not Used
DM1_0 and DM1_1
8 registers
from
Connection
Matrix
1 register
matrix_out
matrix_out
matrix_out
3-bit DM
LUT
4 registers
S1
S0
Output
to ASM
Input
Matrix
Output
Control
2-bit DM
LUT
1 register
18 registers
from
Connection
Matrix
S1
S0
8-bit DLY/
Edge Detect
matrix_out
Supported Modes: Dly/Counter/One Shot/
Freq. Detect/Edge Detect/Reset Counter
Figure 124: DM1_0/DM1_1 Outputs
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17 f(1) Computation Macrocell
17.1 F(1) COMPUTATION MACROCELL OVERVIEW
The f(1) Computation Macrocell consists of a specialized state machine which is optimized for simple data manipulation activities
on single data bit values. The operation of this macrocell can be initiated whenever the ASM Macrocell enters a new state, and
can execute a string of up to 12 commands for loading and storing 1 bit data, as well as doing simple logical functions such as
ANDs, ORs, and XORs.
The only time the f(1) Computation Macrocell will begin to execute instructions is when the ASM Macrocell first enters a new state.
At that point in time, the f(1) Computation Macrocell will execute the user selected commands, if any, that are associated with that
particular ASM state. When the f(1) Computation Macrocell completes the commands, it will then relinquish control back to the
ASM Macrocell. During the time that the f(1) Computation Macrocell is active, there can be no activity in the ASM macrocell (i.e.,
the ASM Macrocell is prevented from any state transition during the time when the f(1) Macrocell is active).
The f(1) Computation Macrocell has two digital inputs, ASM_nReset and f1_Interupt. An active signal on either of these inputs
will immediately halt any command execution for the f(1) Computation Macrocell, and will immediately relinquish control back to
the ASM macrocell.
The f(1) Command Register Table has 4 registers, each of which holds a string of up to 12 commands to run when the f(1)
Computation Macrocell is initiated. These 4 registers allow for 4 different command strings that the user can choose from. The
f(1) Command Selection Table has 12 entries (one per ASM state), which allow the user to select which of the f(1) Command
Registers will be used upon entry into each state. The user can also select that no commands are used in a particular state (one
of the selection options for each entry in the f(1) Command Selection Table), in which case the f(1) Computation Macrocell is
completely bypassed upon entry to that particular state.
There are a total of 8 analog inputs coming from various pins which can be muxed into the positive input for the f(1) Analog
Comparator inside the f(1) Computation Macrocell. The f(1) Analog Comparator can be re-programmed for analog input source
and negative input reference settings. The user selections for both positive input signal and negative reference are included as
part of the information stored in the f(1) Command Register Table. This allows the user to make different analog measurements
that are state dependent in their analog sources and reference settings.
This macrocell also includes a f(1) Memory Stack, which is 1 bit wide by 16 deep memory which is organized as a stack, and can
serve as a data source or data destination for the commands running on the macrocell. LOADx commands will push data down
into the stack. OUTx commands will pop data off the stack, and send to the contents of the Top-Of-Stack to one of three outputs
of the f(1) macrocell to the Connection Matrix. The contents of this memory are not changed during ASM state transitions, and
are only changed by the commands running inside the f(1) Computation Macrocell itself. The initial memory stack values are
loaded from registers [3279:3264].
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17.2 F(1) COMPUTATION MACROCELL ARCHITECTURE
f(1) Command Selection Table
12
3
ASM 12 states to 3 bits
output mapping table
from ASM_state
f(1) Command Register Table
000
001
010
011
100
101
110
111
None
Register0[111:0]
Register1[111:0]
Register2[111:0]
Register3[111:0]
None
None
None
From Connection
Matrix Output
4
f(1) Computation Macrocell
S0
S0
4
GPO8
GPIO9
GPI7
S0
S1
S2
S3
S0
S0
GPI6
ACMP4F
S0
S1
f(1) CMD Configuration
4
f(1) State
Machine
Function
+
-
ACMP4F_out
S1
GPIO1
GPIO0
GPO0
GPO7
To Connection
Matrix Input
S0
S1
S2
S3
f(1) CMD
Configuration
CMIn [28]
OUT2
f(1) CMD
f(1) Memory Stack
Configuration
f(1) CMD Configuration
(1x16)
CMIn [27]
CMIn [26]
OUT1
OUT0
0
Analog
Reference
Selector
S0
From Internal
Vref
1
S62
S63
Ext. Vref (GPI7)
f(1) CMD Configuration
From Connection
Matrix Output
ASM_nRESET
f(1) Interrupt
15
CMOut [71]
CMOut [76]
Figure 125: f(1) Computation Macrocell Architecture
17.3 F(1) COMPUTATION MACROCELL INPUT SIGNALS
The f(1) Computation Macrocell has 6 digital input signals, ASM_nReset, f1_Interupt, and four inputs from Connection Matrix
outputs. An active signal on either of the first 2 inputs will immediately halt any command execution for the f(1) Computation
Macrocell, and will immediately relinquish control back to the ASM macrocell. The ASM_nReset is a level sensitive signal, and
active low. The f1_Interupt is a level sensitive signal, and active high. These signals are shown in Figure 126, highlighted in
blue. Also there are 4 digital inputs from the Connection Matrix, which can be routed to any Connection Matrix outputs from the
f(1) Commands. These signals are shown on Figure 126, highlighted in yellow.
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There are a total of 8 analog inputs coming from various pins which can be muxed into the positive input for the f(1) Analog
Comparator inside the f(1) Computation Macrocell. These signals are shown in Figure 102, highlighted in green. The f(1) Analog
Comparator can be re-programmed for analog input source and negative input reference settings with settings inside the LOADx
command. The user selections for both positive input signal and negative reference are included as part of the information stored
in the f(1) Command Register Table. This allows the user to make different analog measurements that are state dependent in
their analog sources and reference settings.
f(1) Command Selection Table
12
3
ASM 12 states to 3 bits
output mapping table
from ASM_state
f(1) Command Register Table
000
001
010
011
100
101
110
111
None
Register0[111:0]
Register1[111:0]
Register2[111:0]
Register3[111:0]
None
None
None
From Connection
Matrix Output
4
f(1) Computation Macrocell
S0
S0
4
PIN15
PIN18
PIN17
PIN31
S0
S1
S2
S3
S0
S0
ACMP4F
S0
S1
f(1) CMD Configuration
4
f(1) State
Machine
Function
+
-
ACMP4F_out
S1
PIN24
PIN3
PIN23
PIN2
To Connection
Matrix Input
S0
S1
S2
S3
f(1) CMD
Configuration
CMIn [28]
OUT2
f(1) CMD
f(1) Memory Stack
Configuration
f(1) CMD Configuration
(1x16)
CMIn [27]
CMIn [26]
OUT1
OUT0
0
Analog
Reference
Selector
S0
From Internal
Vref
1
S62
S63
Ext. Vref (GPI7)
f(1) CMD Configuration
From Connection
Matrix Output
ASM_nRESET
f(1) Interrupt
15
CMOut [71]
CMOut [76]
Figure 126: f(1) Computation Macrocell Input Signals
The f(1) interrupt signal comes from Connection Matrix Output. The high level f(1) interrupt signal forces the f(1) computation
macrocell to immediately finish command execution and return control to the ASM similar to the END command. It is possible to
load initial memory stack with the f(1) interrupt signal when register [3766] is high.
The ASM_nRESET low level signal forces the ASM macrocell and the f(1) computation macrocell to an initial state and an initial
memory stack value.
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17.4 F(1) COMPUTATION MACROCELL OUTPUT SIGNALS
The f(1) Computation Macrocell has 3 digital output signals that go to the Connection Matrix, and from there can be routed to
other internal macrocells or pins. These signals are shown in Figure 127, highlighted in blue. The state of these output signals
are under user control, and are changed based on the Output commands.
f(1) Command Selection Table
12
3
ASM 12 states to 3 bits
output mapping table
from ASM_state
f(1) Command Register Table
000
001
010
011
100
101
110
111
None
Register0[111:0]
Register1[111:0]
Register2[111:0]
Register3[111:0]
None
None
None
From Connection
Matrix Output
4
f(1) Computation Macrocell
S0
S0
4
GPO8
GPIO9
GPI7
S0
S1
S2
S3
S0
S0
GPI6
ACMP4F
S0
S1
f(1) CMD Configuration
4
f(1) State
Machine
Function
+
-
ACMP4F_out
S1
To Connection
Matrix Input
GPIO1
GPIO0
GPO0
GPO7
S0
S1
S2
S3
f(1) CMD
Configuration
CMIn [28]
OUT2
f(1) CMD
f(1) Memory Stack
Configuration
f(1) CMD Configuration
(1x16)
CMIn [27]
CMIn [26]
OUT1
OUT0
0
Analog
Reference
Selector
S0
From Internal
Vref
1
S62
S63
Ext. Vref (GPI7)
f(1) CMD Configuration
From Connection
Matrix Output
ASM_nRESET
f(1) Interrupt
15
CMOut [71]
CMOut [76]
Figure 127: f(1) Computation Macrocell Output Signals
17.5 F(1) COMMAND REGISTERS
The f(1) Computation Macrocell consists of a specialized state machine which is optimized for simple data manipulation activi
ties on single data bit values. The f(1) Computation Macrocell must be used for accessing the 8:1 analog multiplexer and asso
-
-
ciated analog comparator. The f(1) is also useful for storing state independent values, looping operations such as periodic signal
checks, and for performing simple repetitive logic functions.
The operation of this macrocell can be initiated whenever the ASM Macrocell enters a new state, and can execute a string of up
to 12 commands for loading and storing 1 bit data, as well as doing simple logical functions such as ANDs, ORs, and XORs.
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The f(1) Command Register Table has 4 registers, therefore 4 independent f(1) functions can be defined. Each state of the ASM
can access one of the four f(1) configurable instances of the f(1).
Each of the four f(1) configurations may contain up to 12 commands which run when the f(1) Computation Macrocell is initiated.
The list of available commands is as follows:
Command
Name
Command
Command Description
Loads a one bit value to the top of the memory stack (location 0). During the execution of this
command, all other values are shifted down 1 location, and the value in location 15 is lost. The
data loaded by Load 1 command is defined in the Load 1 register, which defines where the value
is to be loaded from such as a pin, the f(1) comparator, and others.
0000
LOAD1
Loads a one bit value to the top of the memory stack (location 0). During the execution of this
command, all other values are shifted down 1 location, and the value in location 15 is lost. The
data loaded by Load 2 command is defined in the Load 2 register, which defines where the value
is to be loaded from such as a pin, the f(1) comparator, and others.
0001
0010
0011
0100
0101
LOAD2
LOAD3
LOAD4
AND
Loads a one bit value to the top of the memory stack (location 0). During the execution of this
command, all other values are shifted down 1 location, and the value in location 15 is lost. The
data loaded by Load 3 command is defined in the Load 3 register, which defines where the value
is to be loaded from such as a pin, the f(1) comparator, and others.
Loads a one bit value to the top of the memory stack (location 0). During the execution of this
command, all other values are shifted down 1 location, and the value in location 15 is lost. The
data loaded by Load 4 command is defined in the Load 4 register, which defines where the value
is to be loaded from such as a pin, the f(1) comparator, and others.
Performs a logical AND to the top two locations in the memory stack (location 0 and location 1).
During execution of this command, the two values in the top two stack locations are deleted,
and the logical AND result is pushed on the top of stack (location 0). In the process, all other
values in the stack are shifted up 1 location, and a 0 is loaded in location 15.
Performs a logical OR to the top two locations in the memory stack (location 0 and location 1).
During execution of this command, the two values in the top two stack locations are deleted,
and the logical OR result is pushed on the top of stack (location 0). In the process, all other
values in the stack are shifted up 1 location, and a 0 is loaded in location 15.
OR
Performs a logical XOR to the top two locations in the memory stack (location 0 and location 1).
During execution of this command, the two values in the top two stack locations are deleted,
and the logical XOR result is pushed on the top of stack (location 0). In the process, all other
values in the stack are shifted up 1 location, and a 0 is loaded in location 15.
0110
0111
XOR
INV
Performs a logical Invert (INV) to the top location in the memory stack (location 0). During
execution of this command, the value in the top stack location is deleted, and the logical INV
result is pushed on the top of stack. There is no effect on all other values in the stack.
Pushes a 0 into the top location in the memory stack (location 0). During the execution of this
command, all other values are shifted down 1 location, and the value in the location 15 is lost.
1000
1001
PUSH0
POP
During execution of this command, values in the stack are shifted up 1 location, and a 0 is loaded
in location 15.
The execution of commands by the f(1) Computation microcell is delayed by a period of time
defined in the configuration of the delay function. Once this time period is completed, the next
f(1) instruction will execute.
1010
1011
DELAY
If the top location in the memory stack (location 0) is equal to 0, the command execution in the
f(1) Macrocell is delayed by a period of time defined in the configuration of the delay function
and then executes the f(1) sequence at the specified jump location. If the top location in the
memory stack (location 0) is equal to 1, the f(1) Macrocell proceeds with execution of the next
command in sequence.
LOOP with
DELAY
1100
1101
1110
OUT1
OUT2
OUT3
Outputs the top location in the memory stack (location 0) on matrix input OUT1.
Outputs the top location in the memory stack (location 0) on matrix input OUT2.
Outputs the top location in the memory stack (location 0) on matrix input OUT3.
Immediately ends execution of commands by f(1) Macrocell, and control is returned to ASM
Macrocell.
1111
END
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These commands form a machine level language that may be configured within GPAK Designer software using a simple GUI, as
opposed to using a typical text editor. See application examples below:
Example #1: Sensor Application showing the command sequence for a potential use case of the f(1) Macrocell.
f(1) Command
Command
INV
Description
Sequence
1
Change Top Memory location from 0 → 1.
Output a 1 to a pin defined by OUT1 register. This can be used to turn on or bias
an external sensor.
2
3
4
OUT1
DELAY
LOAD1
Wait for a time defined by DELAY register. This can be used to allow sensor to settle.
Capture the output of f(1) ACMP from an analog pin connected to the sensor as
defined by the LOAD1 register.
Capture the output of a pin as defined by the LOAD2 register. This can be used to
check a power good signal.
5
6
LOAD2
AND
Logically AND the top two values of the 1x16 memory that were just loaded with
LOAD1 and LOAD2.
Output the result of sensor output AND power good signal for a control decision for
the ASM.
7
8
OUT2
END
ASM can now act on OUT2 signal.
Example #2: Power Good Application showing the command sequence for a potential use case of the f(1) Macrocell.
f(1) Command
Sequence
Command
Description
1
LOAD1
Capture the output of f(1) ACMP from an analog pin connected to power rail 1 as
defined by the LOAD1 register. A “1” means that power is good on power rail 1.
2
3
4
5
LOAD2
LOAD3
LOAD4
AND
Capture the output of f(1) ACMP from an analog pin connected to power rail 2 as
defined by the LOAD2 register. A “1” means that power is good on power rail 2.
Capture the output of f(1) ACMP from an analog pin connected to power rail 3 as
defined by the LOAD3 register. A “1” means that power is good on power rail 3.
Capture the output of f(1) ACMP from an analog pin connected to power rail 4 as
defined by the LOAD4 register. A “1” means that power is good on power rail 4.
LOAD4 result ANDs with LOAD3 result (LOAD4 & LOAD3). This combines two of
the Power Good signals.
6
7
AND
AND
(LOAD4 & LOAD3) & LOAD2. This combines three of the Power Good signals.
((LOAD4 & LOAD3) & LOAD2) & LOAD1. This combines four of the Power Good
signals.
8
OUT1
Output the Master Power Good signal to a location defined by the OUT1 register.
The LOADx, OUTx, and DELAY/LWD commands are required to be defined before using them.
17.5.1 Delay Command Configuration Bits
The Delay Command is defined by 12 bits. Each of the 4 instances of the f(1) command can configure a new value for the delays.
However, the DELAY and LWD use the same configuration data, so these two delays must be identical.
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Delay Configuration Bits
Configuration Bits
Description
8 Bits
Delay Count (0 .. 255)
Delay Clock
000
OSC2
001
OSC2/4
OSC1
010
3 Bits
011
OSC1/8
OSC1/64
OSC0
100
101
110
OSC0/8
OSC0/64
111
ACMP Shutdown
during Delay
1 Bit
ACMP is shutdown after data Load
17.5.2 LOADx Command Configuration Bits
There are two types of load configuration schemes. One method defines loading from one of eight analog pins via the f(1) ACMP.
The other method defines loading from any of the matrix outputs connected to digital input pins, logic macrocells, ASM outputs,
oscillators, and others. LOAD1 and LOAD2 can only be configured for 4 analog input pins. LOAD3 and LOAD 4 can be configured
for the remaining 4 analog input pins.
LOAD1, 2, 3, 4 Command from f(1) ACMP or Matrix connection. A single bit determines if LOADx takes its value from the f(1)
analog comparator or from a matrix output.
Configuration Bit
Description
1 Bit
1 Bit
1 Bit
1 Bit
LOAD1 Connection
LOAD2 Connection
LOAD3 Connection
LOAD4 Connection
0: Matrix, 1: f(1) ACMP
0: Matrix, 1: f(1) ACMP
0: Matrix, 1: f(1) ACMP
0: Matrix, 1: f(1) ACMP
LOAD1 and LOAD2 Configuration Bits f(1) ACMP input.
Configuration Bits
Description
6 Bits
ACMP Voltage Reference value 000000 is 32 mV, 111111 is 2.048 V
One of four analog input pins
00
01
Analog pin 1
Analog pin 2
Analog pin 3
Analog pin 4
2 Bits
1 Bit
10
11
Reserved
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LOAD3 and LOAD4 Configuration Bits f(1) ACMP input.
Configuration Bits
Description
6 Bits
ACMP Voltage Reference value 000000 is 32 mV, 111111 is 2.048 V
One of four analog input pins
00
01
Analog pin 5
Analog pin 6
Analog pin 7
Analog pin 8
2 Bits
1 Bit
10
11
Reserved
17.5.3 OUTx Command Configuration Bits
Each f(1) instance can be configured to output to up to three matrix inputs using the OUTx command. OUT1, 2, & 3’s initial
condition is two bit selectable. Each time the ASM changes state, the initial condition of the f(1) is re-loaded.
Configuration Bits
Description
00
01
10
11
OUTx equals previous OUTx
OUTx is 0
OUTx is 1
none (high Z)
The only time the f(1) Computation Macrocell will run is when ASM macrocell first enters a new state. At that point in time, the
f(1) Computation Macrocell will execute the user selected commands (based on user selection), and then relinquish control back
to the ASM macrocell. During the time that the f(1) Computation Macrocell is active, there can be no activity in the ASM macrocell
(i.e. no ASM macrocell state change).
The f(1) Computation Macrocell has two digital inputs, ASM_nReset and f1_Interupt. An active signal on either of these inputs
will immediately halt any command execution for the f(1) Computation Macrocell, and will immediately relinquish control back to
the ASM macrocell.
17.5.4 LOOP WITH DELAY Configuration Bits
There is one conditional command LOOP WITH DELAY (LWD) in f(1) computation macrocell. The order of the f(1) command
execution depends on the LWD usage and its configuration. If top value in 1 x 16 memory stack is 0, then the f(1) is delayed
according to the configuration of the f(1) delay function and the f(1) command sequence starting from the location defined by 4-
bit register is executed, otherwise f(1) continues to execute commands one by one.
Configuration Bits
Description
4 bits
Next command location after
LWD command
0000 is the first command in the f(1) sequence, 1011 is the
twelfth last command in the f(1) sequence
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Example #3: Rising Edge Deglitch Application showing the command sequence for a potential use case of the f(1) Macrocell.
f(1) Command
Sequence
Command
Description
1
2
3
4
5
LOAD1
DELAY
LOAD1
DELAY
LOAD1
Capture the output of a pin or any macrocell output defined by the LOAD1 register.
Delay for the time defined by configuration register.
Capture the output of a pin or any macrocell output defined by the LOAD1 register.
Delay for time defined by configuration register.
Capture the output of a pin or any macrocell output defined by the LOAD1 register.
Logically AND the top two values of the 1x16 memory stack, that was loaded
before (LOAD1 & LOAD1 after Delay).
6
7
AND
AND
(LOAD1 & LOAD1 after Delay) & LOAD1 after double Delay.
If the calculated value is 0, then start to execute first command once again, which
8
LWD
is defined by the configuration bits. Otherwise f(1) continues to execute next com
-
mand (command 9).
9
OUT1
END
Output the result value, which is a high level.
ASM can act on any other signals.
10
The following flowchart shows the f(1) rising edge deglitch based on three samples application.
f(1) GO
1
LOAD1
2
DELAY
3LOAD1 (GPIO5)
4
DELAY (5 ms)
5LOAD1 (GPIO5)
6
AND
7
AND
8
TOP VALUE in STACK = 0
LWD
command location=1
delay value=5us
TOP VALUE in STACK = 1
9
OUT1
10
END
f(1) DONE
Figure 128: f(1) Flowchart for Rising Edge Deglitch
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Example #4: Average Function for Captured Data, showing the command sequence for a potential use case of the f(1) Macrocell.
This function requires two f(1) Macrocell command sequences to implement.
f(1) GO
LOAD1
DELAY
LOAD1
DELAY
LOAD1
END
f(1) GO
1
2
3
4
5
6
1
TOP VALUE in STACK = 0
TOP VALUE in STACK = 1
LWD
command location=5
delay value=0
6
2
3
4
5
POP
POP
OR
7
AND
8
OUT1
OUT1
END
9
END
f(1) DONE
f(1) DONE
Figure 129: f(1) Flowchart for Average Function for Captured Data
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17.6 F(1) TYPICAL PERFORMANCE
35
30
25
20
15
10
5
ACMP4F (T = -40 °C)
ACMP4F (T = 25 °C)
ACMP4F (T = 85 °C)
0
2.3
2.5
2.7
3
3.3
3.6
4
4.2
4.5
5
5.5
VDD (V)
Figure 130: ACMP4F Power-On Delay vs. VDD
15
10
5
0
32
480
1024
1504
2016
-5
-10
-15
-20
-25
-30
-35
Upper Limit Internal Vref
Upper Limit External Vref
Lower Limit External Vref
Lower Limit Internal Vref
Vref (mV)
Figure 131: ACMP4F Input Offset Voltage vs. Vref at T = -40 °C to 85 °C, Input Buffer Disabled
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18 Matrix Interface Macrocells
The ASM Sub-System includes several discrete macrocells, including the ASM macrocell, four Dynamic Memory (DMx_x) mac
-
rocells, three Matrix Interface (MI) Macrocells, and one f(1) Computation Macrocell. These macrocells are designed to work as a
system for building user defined state machines.
The Matrix Interface macrocells have the characteristic that they can change internal configuration characteristics and their
connections to the Connection Matrix based on the current state of the State Machine (SM) macrocell. This is accomplished by
making different memory register bit settings contained within the macrocell active, based on the current active state of the SM.
This allows the user to “repurpose” the resources inside these macrocells to match the circuit needs in various states.
The SLG46880/81 has a total of three MI macrocells, MI0, MI1, and MI2.
Each MI macrocell has a MIx Configuration Register Table, which is a bank of 4 MIx Configuration Registers. The bits in these
registers hold user selections which define the input connections from the Connection Matrix. The fact that there are 4 Configu
-
ration Registers means that there can only be a total of four unique configurations for each MIx macrocell. There are a total of
twelve states, which means that the user can either re-use the configuration coded in a particular MIx Operating Mode Register
in more than one state, or not use some MIx macrocells in some states.
Each MI macrocell has a MIx Operating Mode Selection Table, which is a bank of 12 Configuration Selection Registers, one for
each state of the State Machine macrocell. The bits in these registers hold the user’s selection of MI functional behavior (input
selection from Connection Matrix), by mapping to a particular selection in the Configuration Register Table, based on the current
state of the State Machine macrocell.
18.1 MI0, MI1, AND MI2 MACROCELL ARCHITECTURE
MIx Configuration Selection Table
12
2
ASM 12 states to 2 bits
output mapping table
from ASM_state
MIx Configuration Register Table
00
01
10
11
Register0[5:0]
Register1[5:0]
Register2[5:0]
Register3[5:0]
from
Connection
Matrix
MIx Macrocell
matrix_out
Output to
ASM Input
Matrix
Figure 132: MIx Macrocell Architecture
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18.2 MIX MACROCELL INPUT SIGNALS
Each MIx macrocell has a single digital input signal coming from the Connection Matrix and from there can be routed to other
internal macrocells or pins. This signal is shown in Figure 132, highlighted in blue.
18.3 MIX MACROCELL OUTPUT SIGNALS
Each MIx macrocell has a single digital output signal, which goes directly to the ASM Input Matrix inside the ASM Macrocell.
This signal is shown in Figure 132, highlighted in green.
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2
19 I C Serial Communications Macrocell
19.1 I2C SERIAL COMMUNICATIONS MACROCELL OVERVIEW
In the standard use case for the GreenPAK devices, the configuration choices made by the user are stored as bit settings in the
Non-Volatile Memory (NVM), and this information is transferred at startup time to volatile RAM registers that enable the configu
-
ration of the macrocells. Other RAM registers in the device are responsible for setting the connections in the Connection Matrix
to route signals in the manner most appropriate for the user’s application.
The I2C Serial Communications Macrocell in this device allows an I2C bus Master to read and write this information via a serial
channel directly to the RAM registers, allowing the remote re-configuration of macrocells, and remote changes to signal chains
within the device.
An I2C bus Master is also able read and write other register bits that are not associated with NVM memory. As an example, the
input lines to the Connection Matrix can be read as digital register bits. These are the signal output of each of the macrocells in
the device, giving an I2C bus Master the capability to remotely read the current value of any macrocell.
The user has the flexibility to control read access and write access via registers bits registers [4071:4069]. See Section 19.5 for
more details on I2C read/write memory protection.
19.2 I2C SERIAL COMMUNICATIONS DEVICE ADDRESSING
Each command to the I2C Serial Communications macrocell begins with a Control Byte. The bits inside this Control Byte are
shown in Figure 133. After the Start bit, the first four bits are a control code, which can be set by the user in registers [4083:4080]
or value defined externally by GPIs 4, 5, 6, and 7. The LSB of the control code is defined by the value of GPI4, while the MSB is
defined by the value of GPI7. The address source is selected by register [4087]. This gives the user flexibility on the chip level
addressing of this device and other devices on the same I2C bus. The Block Address is the next three bits (A10, A9, A8), which
will define the most significant bits in the addressing of the data to be read or written by the command. The last bit in the Control
Byte is the R/W bit, which selects whether a read command or write command is requested, with a “1” selecting for a Read
command, and a “0” selecting for a Write command. This Control Byte will b followed by an Acknowledge bit (ACK), which is sent
by this device to indicate successful communication of the Control Byte data.
In the I2C-bus specification and user manual, there are two groups of eight addresses (0000 xxx and 1111 xxx) that are reserved
for the special functions, such as a system General Call address. If the user of this device choses to set the Control Code to either
“1111” or “0000” in a system with other slave device, please consult the I2C-bus specification and user manual to understand the
addressing and implementation of these special functions, to insure reliable operation.
In the read and write command address structure, there are a total of 11 bits of addressing, each pointing to a unique byte of
information, resulting in a total address space of 2K bytes. Of this 2K byte address space, the valid addresses accessible to the
I2C Macrocell on the SLG46880/81 are in the range from 0 (00H) to 511 (1FFH). The upper two address bits (A10 and A9) will
be “0” for all commands to the SLG46880/81. The value of Address bit A8 will depend on whether the Bus Master is addressing
the upper or lower half of the 4K bit address space.
With the exception of the Current Address Read command, all commands will have the Control Byte followed by the Word
Address.
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Start
bit
Acknowledge
bit
Control Byte
Word Address
A
10
A
9
A
8
A
7
A
0
S
X
X
X
X
R/W ACK
Control
Code
Block
Address
Not used, set to
0
Read/Write bit
Figure 133: Basic Command Structure
19.3 I2C SERIAL GENERAL TIMING
General timing characteristics for the I2C Serial Communications macrocell are shown in Figure 134. Timing specifications can
be found in the AC Characteristics section.
tHIGH
tF
tR
tLOW
SCL
tSU STA
tHD DAT
tHD STA
tSU DAT
tSU STO
SDA IN
tBUF
tAA
tDH
SDA OUT
Figure 134: I2C General Timing Characteristics
19.4 I2C SERIAL COMMUNICATIONS COMMANDS
19.4.1 Byte Write Command
Following the Start condition from the Master, the Control Code [4 bits], the Block Address [3 bits], and the R/W bit (set to “0”) are
placed onto the I2C bus by the Master. After the SLG46880/81 sends an Acknowledge bit (ACK), the next byte transmitted by the
Master is the Word Address. The Block Address (A10, A9, A8), combined with the Word Address (A7 through A0), together set
the internal address pointer in the SLG46880/81, where the data byte is to be written. After the SLG46880/81 sends another
Acknowledge bit, the Master will transmit the data byte to be written into the addressed memory location. The SLG46880/81 again
provides an Acknowledge bit and then the Master generates a Stop condition. The internal write cycle for the data will take place
at the time that the SLG46880/81 generates the Acknowledge bit.
It is possible to latch all IOs during I2C write command, register [4065] = 1 - Enable. It means that IOs will remain their state until
the write command is done.
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Acknowledge
bit
Acknowledge
bit
Start
bit
Acknowledge
bit
Bus Activity
Control Byte
Word Address
Data
A
10
A
9
A
8
A
7
A
0
D
7
D
0
S
X
X
X
X
W
ACK
ACK
ACK
SDA LINE
P
Control
Code
Block
Address
Stop
bit
Not used, s
et to 0
R/W bit = 0
Figure 135: Byte Write Command, R/W = 0
19.4.2 Sequential Write Command
The write Control Byte, Word Address, and the first data byte are transmitted to the SLG46880/81 in the same way as in a Byte
Write command. However, instead of generating a Stop condition, the Bus Master continues to transmit data bytes to the
SLG46880/81. Each subsequent data byte will increment the internal address counter, and will be written into the next higher byte
in the command addressing. As in the case of the Byte Write command, the internal write cycle will take place at the time that the
SLG46880/81 generates the Acknowledge bit.
Acknowledge
Acknowledge
bit
Start
bit
bit
Bus Activity
Data (n + 1)
Data (n + x)
Control Byte
Word Address (n)
Data (n)
A
10
A
8
A
9
ACK
ACK
P
SDA LINE
S
X
X
X
X
W
ACK
ACK
ACK
Control
Code
Block
Address
Stop
bit
Not used, set
to 0
Write bit
Figure 136: Sequential Write Command
19.4.3 Current Address Read Command
The Current Address Read Command reads from the current pointer address location. The address pointer is incremented at the
first STOP bit following any write control byte. For example, if a Sequential Read command (which contains a write control byte)
reads data up to address n, the address pointer would get incremented to n + 1 upon the STOP of that command. Subsequently,
a Current Address Read that follows would start reading data at n + 1. The Current Address Read Command contains the Control
Byte sent by the Master, with the R/W bit = “1”. The SLG46880/81 will issue an Acknowledge bit, and then transmit eight data bits
for the requested byte. The Master will not issue an Acknowledge bit, and follow immediately with a Stop condition.
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Start
bit
Acknowledge
bit
Stop
bit
Bus Activity
Control Byte
Data (n)
A
10
A
9
A
8
S
X
X
X
X
R
ACK
SDA LINE
P
Control
Code
Block
Address
No Ack
bit
Not used, set t
o 0
R/W bit = 1
Figure 137: Current Address Read Command, R/W = 1
19.4.4 Random Read Command
The Random Read command starts with a Control Byte (with R/W bit set to “0”, indicating a write command) and Word Address
to set the internal byte address, followed by a Start bit, and then the Control Byte for the read (exactly the same as the Byte Write
command). The Start bit in the middle of the command will halt the decoding of a Write command, but will set the internal address
counter in preparation for the second half of the command. After the Start bit, the Bus Master issues a second control byte with
the R/W bit set to “1”, after which the SLG46880/81 issues an Acknowledge bit, followed by the requested eight data bits.
Acknowledge
Stop
bit
Start
bit
bit
Bus Activity
Data (n)
Control Byte
Word Address (n)
Control Byte
A
10
A
9
A
8
A
10
A
9
A
8
S
ACK
1
0
1
0
R ACK
P
SDA LINE
S
X
X
X
X
W
ACK
Control
Code
Block
Address
Read bit
No Ack
bit
Not used, set to
0
Write bit
Figure 138: Random Read Command
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19.4.5 Sequential Read Command
The Sequential Read command is initiated in the same way as a Random Read command, except that once the SLG46880/81
transmits the first data byte, the Bus Master issues an Acknowledge bit as opposed to a Stop condition in a random read. The
Bus Master can continue reading sequential bytes of data, and will terminate the command with a Stop condition.
Acknowledge
Start
bit
bit
Bus Activity
Data (n + 2)
Data (n + x)
Control Byte
Data (n)
Data (n + 1)
A
10
A
9
A
8
ACK
P
SDA LINE
S
X
X
X
X
R
ACK
ACK
ACK
Control
Code
Block
Address
Stop
bit
No Ack
bit
Read bit
Figure 139: Sequential Read Command
19.4.6 I2C Serial Reset Command
If I2C serial communication is established with the device, it is possible to reset the device to initial power up conditions, including
configuration of all macrocells, and all connections provided by the Connection Matrix. This is implemented by setting
register [4064] I2C reset bit to “1”, which causes the device to re-enable the Power-On Reset (POR) sequence, including the
reload of all register data from NVM. During the POR sequence, the outputs of the device will be in tri-state. After the reset has
taken place, the contents of register [4064] will be set to “0” automatically. The timing diagram shown below illustrates the
sequence of events for this reset function.
Acknowledge
bit
Acknowledge
bit
Start
bit
Acknowledge
bit
Bus Activity
Control Byte
Word Address
Data
A
10
A
9
A
8
A
7
A
0
D
7
D
0
S
X
X
X
X
W
ACK
ACK
ACK
SDA LINE
P
Internal Reset bit
Control
Code
Block
Address
Stop
bit
Not used, set to
0
Write bit
by I2C Stop Signal
Reset-bit register output
DFF output gated by stop signal
Internal POR for core only
Figure 140: Reset Command Timing
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19.5 I2C SERIAL COMMAND REGISTER MAP
There are seven read/write protect modes for the design sequence from being corrupted or copied. See Table 54 for details.
Table 54: Read/Write Protection Options
Protection Modes Configuration
Partly
Partly
Lock
Partly
Lock
Lock
Read/
Write
Data
Output
From
Lock
Read2/
Write
Lock
Read
Lock
Write
Register
Address
Configurations
Unlocked
Read1
Read2
(Mode 0) (Mode1) (Mode2) (Mode3) (Mode4) (Mode5) (Mode 6)
I2C Byte Write Bit
Masking
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
R
R
-
-
Memory
Memory
1FD
(section 19.6.4)
I2C Serial Reset
Command
1FC,b'0
(section 19.4.6)
Outputs Latching
During I2C Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
R
R
-
-
Memory
1FC,b'1
f(1) Computation
Macrocell Stack
Macrocell
198~199
Connection Matrix
Virtual Inputs
R/W
R/W
R/W
R/W
R/W
W
R/W
W
W
R
R
-
-
Macrocell
Memory
1DB
(section 6.3)
ConfigurationBits for
All Macrocells
(IO Pins, ACMPs,
-
Combination
FunctionMacrocells,
ASM, etc.)
Macrocells Inputs
Configuration
(Connection Matrix
Outputs, section 6.2)
R/W
R/W
R
W
R
W
R
-
W
R
-
R
R
R
-
R
-
Memory
Memory
Macrocell
0~3E
Protection Mode
Selection
1FC,b'7,6,
5
R
R
Macrocells Output
Values (Connection
MatrixInputs,section
6.1)
1D7~1DA;
1DC~1DE
R
R
Counter Current
Value
1DF,1E0,1
E1,1E2
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
-
R
R
R
R
-
Macrocell
Macrocell
Memory
Memory
ASM Current State
I2C Control Code
(section 19.4)
-
-
1E3,1E4
1FE,b'3~0
1FE,b'4
R
R
R
R
I2C Disable/Enable
R/W
W
Allow Read and Write Data
Allow Write Data Only
Allow Read Data Only
R
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-
The Data is protected for Read and Write
It is possible to read some data from macrocells, such as counter current value, ASM current state, connection matrix, f(1) com
-
putation macrocell stack, and connection matrix virtual inputs. The I2C write will not have any impact on data in case data comes
from macrocell output, except f(1) Computation Macrocell Stack and Connection Matrix Virtual Inputs. The silicon identification
service bits allows identifying silicon family, its revision, and others.
See Section 21 for detailed information on all registers.
19.6 I2C ADDITIONAL OPTIONS
When Output latching during I2C write, register [4065] = 1 allows all PINs output value to be latched until I2C write is done. It will
protect the output change due to configuration process during I2C write in case multiple register bytes are changed. Inputs and
internal macrocells retain their status during I2C write.
If the user sets GPIO0 and GPIO1 function to a selection other than SDA and SCL, all access via I2C will be disabled.
Note: Any write commands that come to the device via I2C that are not blocked, based on the protection bits, will change the
contents of the RAM register bits that mirror the NVM bits. These write commands will not change the NVM bits themselves, and
a POR event will restore the register bits to original programmed contents of the NVM.
See Section 21 for detailed information on all registers.
19.6.1 Reading Counter Data via I2C
The current count value in three counters in the device can be read via I2C. The counters that have this additional functionality
are 16-bit CNT0, and 8-bit counters CNT2 and CNT4.
19.6.2 Reading ASM Current State via I2C
The Current State of the ASM can be read via I2C. There are 12 memory bits located at registers [3875:3864]. Configuration for
each Current State can be found in Table 55.
Table 55: ASM Current State Bits Configuration
ASM Current State Bits Configuration
2
I C
Register
Bit #
ASM
State #
State
0
State
1
State
2
State
3
State
4
State
5
State Stat e State
State
9
State
10
State
11
Address
6
0
0
0
0
0
0
1
0
0
0
0
0
7
0
0
0
0
0
0
0
1
0
0
0
0
8
0
0
0
0
0
0
0
0
1
0
0
0
3864
3865
3866
3867
3868
3869
3870
3871
3872
3873
3874
3875
State 0
State 1
State 2
State 3
State 4
State 5
State 6
State 7
State 8
State 9
State 10
State 11
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1E3
1E4
19.6.3 I2C Expander
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In addition to the eight Connection Matrix Virtual Inputs, the SLG46880/81 chip has four pins which can be used as an I2C
Expander. These four pins are GPIO4, GPIO5, GPIO6, and GPIO7.
Each of these pins can be used as an I2C Expander output or used as a normal pin. Also, each of these four expander outputs
have initial state settings which are specified in registers [3880:3870].
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19.6.4 I2C Byte Write Bit Masking
The I2C macrocell inside SLG46880/81 supports masking of individual bits within a byte that is written to the RAM memory space.
This function is supported across the entire RAM memory space. To implement this function, the user performs a Byte Write
Command (see Section 19.4.1 for details) on the I2C Byte Write Mask Register (address 1FDH) with the desired bit mask pattern.
This sets a bit mask pattern for the target memory location that will take effect on the next Byte Write Command to this register
byte. Any bit in the mask that is set to “1” in the I2C Byte Write Mask Register will mask the effect of changing that particular bit
in the target register, during the next Byte Write Command. The contents of the I2C Byte Write Mask Register are reset (set to
00h) after the Byte Write Command. If the next command received by the device is not a Byte Write Command, the effect of the
bit masking function will be aborted, and the I2C Byte Write Mask Register will be reset with no effect. Figure 141 shows an
example of this function.
User Actions
Byte Write Command, Address = 1FDh, Data = 11110000b [sets mask bits]
Byte Write Command, Address = 74h, Data = 10101010b [writes data with mask]
Memory Address 74h (original contents)
Mask to choose bit from new
write command
1
1
1
1
0
0
1
1
0
0
0
0
Mask to choose bit from
original register contents
Memory Address 74h (new data in write command)
0
1
0
1
0
1
Bit from new write command
Memory Address 1FDh (mask register)
1
1
1
0
0
0
Bit from original register
contents
Memory Address 74h (new contents after write command)
1
1
0
0
1
0
1
0
Figure 141: Example of I2C Byte Write Bit Masking
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20 Analog Temperature Sensor
The SLG46880 has an Analog Temperature sensor (TS) with an output voltage linearly-proportional to the Centigrade tempera
-
ture. The TS cell shares buffer with Vref0, so it is impossible to use both cells simultaneously, its output can be connected directly
to the GPIO9 or to the ACPM3_L positive input. Using buffer causes low-output impedance, linear output, and makes interfacing
to readout or control circuitry especially easy. The TS is rated to operate over a -40 °C to 85 °C temperature range. The error in
the whole temperature range does not exceed ±3.6 %. TS output voltage variation over VDD at constant temperature is less than
±1 %. For more detail refer to Section 3.
The equation below calculates the typical analog voltage passed from the TS to the ACMPs' IN+ source input. It is important to
note that there will be a chip to chip variation of about ±2 °C.
VTS1 = -2.3 x T + 904.6
VTS2 = -2.8 x T + 1076.1
where:
VTS1 (mV) - TS Output Voltage, range 1
V
TS2 (mV) - TS Output Voltage, range 2
T (°C) - Temperature
Temperature hysteresis can be setup by enabling the GreenPAK's internal ACMP hysteresis.
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register [651]
TS
TS_ON
From Connection Matrix Output [78]
1
0
PD
register [650]
register [654]
VDD
registers [655:654] force to “11” when TS is ON
register [655]
TS_ON
11
10
01
00
+
-
Vref0
GPIO9
GPIO9_aio_en
ACMP3_L in+
register [669]=1
register [652]
ACMP1_H Vref
ACMP0_H Vref
none
0
1
TS_ON
Closed
Figure 142: Analog Temperature Sensor Structure Diagram
Note that the Power-Down Mode is paired with Crystal OSC, see Section 12.6. If it is enabled for Temp Sensor, it is not available
for Crystal OSC and vice versa. However, it is possible to enable Power-Down Mode for Crystal OSC and Temp Sensor simulta
-
neously.
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1.2
1.15
1.1
Output Range Ϯ
Output Range ϭ
1.05
1
0.95
0.9
0.85
0.8
0.75
0.7
T (°C)
Figure 143: TS Output vs. Temperature, VDD = 2.3 V to 5.5 V
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21 Register Definitions
21.1 REGISTER MAP
Table 56: Register Map
Address
Signal Function
Register Bit Definition
Byte
Register Bit
0
1
2
OUT0: IN0 of LUT2_0 or Clock Input of DFF0
3
0
4
5
6
7
8
OUT1: IN1 of LUT2_0 or Data Input of DFF0
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
1
2
3
OUT2: IN0 of LUT2_1 or Clock Input of
PGen
OUT3: IN1 of LUT2_1 or nRST of PGen
OUT4: IN0 of LUT3_0 or Clock Input of DFF1
OUT5: IN1 of LUT3_0 or Data Input of DFF1
4
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Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
4
OUT6: IN2 of LUT3_0 or nRST (nSET) of
DFF1
5
OUT7:IN0 of LUT3_1 or Clock Input of DFF2
OUT8:IN1 of LUT3_1 or Data Input of DFF2
6
OUT9:IN2 of LUT3_1 or nRST (nSET) of
DFF2
7
OUT10:IN0 of LUT3_2 or Clock Input of
DFF3
8
OUT11:IN1 of LUT3_2 or Data Input of DFF3
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Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
OUT12:IN2 of LUT3_2 or nRST (nSET) of
DFF3
9
9
OUT13:IN0 of LUT3_3 or Clock Input of
DFF4
A
OUT14:IN1 of LUT3_3 or Data Input of DFF4
B
OUT15:IN2 of LUT3_3 or nRST (nSET) of
DFF4
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Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
96
97
98
OUT16:IN0 of LUT3_4 or Delay1 Input (or
Counter1 nRST Input)
99
C
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
OUT17:IN1 of LUT3_4 or External Clock1
Input of Delay1 (or Counter1)
D
OUT18:IN2 of LUT3_4
E
OUT19:IN0 of LUT3_5 or Delay2 Input (or
Counter2 nRST Input)
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Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
OUT20:IN1 of LUT3_5 or External Clock1
Input of Delay2 (or Counter2)
F
OUT21:IN2 of LUT3_5
10
OUT22:IN0 of LUT3_6 or Delay3 Input (or
Counter3 nRST Input)
11
OUT23:IN1 of LUT3_6 or External Clock1
Input of Delay3 (or Counter3)
OUT24:IN2 of LUT3_6
12
13
OUT25:IN0 of LUT3_7 or Delay4 Input (or
Counter4 nRST Input)
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Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
13
OUT26:IN1 of LUT3_7 or External Clock1
Input of Delay4 (or Counter4)
14
15
16
17
OUT27:IN2 of LUT3_7
OUT28:IN0ofLUT3_8or Inputof PipeDelay
or UP signal of Ripple CNT
OUT29:IN1 of LUT3_8 or nRST of Pipe De
lay or STB of Ripple CNT
-
OUT30:IN2 of LUT3_8 or Clock of Pipe De
lay_Ripple CNT
-
OUT31:IN0 of LUT4_0 or Delay0 Input (or
Counter0 nRST Input)
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Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
OUT32:IN1 of LUT4_0 or External Clock In
put of Delay0 (or Counter0)
-
18
OUT33:IN2 of LUT4_0 or UP Input of FSM0
19
OUT34:IN3 of LUT4_0 or KEEP Input of
FSM0
1A
OUT35:PWR UP of ACMP0_H
OUT36:PWR UP of ACMP1_H
OUT37:PWR UP of ACMP2_L
1B
1C
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Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
1C
OUT38:PWR UP of ACMP3_L
1D
1E
1F
20
OUT39: GPO7 DOUT
OUT40: GPO0 DOUT
OUT41: GPIO0 DOUT
OUT42: GPIO0 DOUT OE
OUT43: GPIO1 DOUT
Datasheet
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186 of 353
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
OUT44:GPIO1 DOUT OE
21
OUT45: GPIO2 DOUT
OUT46: GPIO2 DOUT OE
OUT47: GPIO3 DOUT
22
23
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
OUT48: GPIO3 DOUT OE
24
OUT49: GPIO4 DOUT
OUT50: GPIO4 DOUT OE
OUT51: GPIO5 DOUT
25
26
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
OUT52: GPIO5 DOUT OE
27
OUT53: GPO1 DOUT
OUT54: GPO2 DOUT
OUT55: GPO3 DOUT
28
29
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
OUT56: GPO4 DOUT
2A
OUT57: GPIO6 DOUT OE
OUT58: GPIO6 DOUT
OUT59: GPIO7 DOUT
2B
2C
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
OUT60: GPIO7 DOUT OE
2D
OUT61: GPIO8 DOUT OE
2E
OUT62: GPIO8 DOUT
2F
OUT63: GPIO9 DOUT OE
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
OUT64: GPIO9 DOUT
30
OUT65: GPIO10 DOUT OE
31
OUT66: GPIO10 DOUT
32
OUT67: GPIO11 DOUT OE
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
OUT68: GPIO11 DOUT
33
OUT69: GPO5 DOUT
OUT70: GPO6 DOUT
OUT71: ASM REnSET
34
35
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
OUT72: OSC0 ENABLE
36
OUT73: OSC1 ENABLE
37
OUT74: OSC2 ENABLE
38
OUT75: Filter/Edge detect input
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
OUT76: F1 interrupt
39
OUT77: Programmable delay/edge detect
input
3A
OUT78: Temp sensor/Crystal OSC/Vref
Out_0/Vref Out_1 Power Up
3B
OUT79: GPI LATCH enable
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
OUT80: GPIO LATCH enable
3C
OUT81: BG Power-down
3D
OUT82: DM EXT CLK0
3E
OUT83: DM EXT CLK1
OSC1 turn on by register
when matrix output enable/pd control signal = 0:
0: auto on by delay cells
1: always on
504
505
0: matrix down, and register [504] should set to 1
1: matrix on, and register [504] should set to 0
OSC1 matrix power-down or on select
external clock source enable
0: internal OSC1
1: external clock from GPI1
506
507
00: div 1
01: div 2
10: div 4
11: div 8
post divider ratio control
3F
508
509
510
000: /1
001: /2
010: /4
011: /3
100: /8
101: /12
110: /24
111: /64
matrix divider ratio control
511
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
0: disable
1: enable
512
matrix out enable
513
514
515
Reserved
Reserved
Reserved
when matrix output enable/pd control signal = 0:
0: auto on by delay cells
1: always on
516
OSC2 turn on by register
40
0: matrix down
1: matrix on
517
518
matrix power-down or on select
external clock source enable
matrix out enable
0: internal OSC2
1: external clock from GPI0
0: disable
1: enable
519
520
00: div 1
01: div 2
10: div 4
11: div 8
post divider ratio control
521
522
523
000: /1
001: /2
010: /4
011: /3
100: /8
101: /12
110: /24
111: /64
matrix divider ratio control
524
41
0: enable
1: disable
525
526
100 ns Startup Delay
when matrix output enable/pd control signal = 0:
0: auto on by delay cells
OSC0 turn on by register
1: always on
0: matrix down
1: matrix on
527
528
matrix power-down or on select
external clock source enable
matrix out enable
0: internal OSC0
1: external clock from PIN30
0: disable
1: enable
529
530
00: div 1
01: div 2
10: div 4
11: div 8
post divider ratio control
531
42
532
533
000: /1
001: /2
010: /4
011: /3
100: /8
101: /12
110: /24
111: /64
matrix divider ratio control
Reserved
534
535
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
0: disable
1: enable
536
537
538
539
GPI0 Digital Input 100 ns debounce enable
GPI1 Digital Input 100 ns debounce enable
GPI5 Digital Input 100 ns debounce enable
GPI6 Digital Input 100 ns debounce enable
0: disable
1: enable
0: disable
1: enable
0: disable
1: enable
43
Filter or Edge Detector Select
0: filter
1: edge det
540
Filter or Edge Detector selection
Output Polarity Select
0: Filter/edge detect output
1: Filter/edge detect output inverted
541
542
00: Rising Edges Det
01: Falling Edge Det
10: Both Edge Det
11: Both Edge dly
Select the edge mode
543
544
545
546
547
548
549
550
551
[7:4]: LUT3_8 [7:4]/REG_S1[3:0] pipe delay out1 sel
[3:0]: LUT3_8 [3:0]/REG_S0[3:0] pipe delay out0 sel
LUT value or pipe delay out sel or Nset/END at Ripple CNT mode:
44
value
bit[546:544] is the nSET value.
bit[549:547] is the END value
bit [550] is the range control: 0: full cycle, 1: ranged cycle
bit [551] Not used
0: Non-inverted
1: Inverted
552
553
554
Pipe Delay OUT1 Polarity Select
LUT3_8 or Pipe Delay Select
0: LUT3_8
1: Pipe Delay or Ripple CNT
0: Pipe delay mode selection
1: Ripple Counter mode selection
PIPE_Ripple_CNT_S
Reserved
555
556
45
00: Rising Edge Detector
01: Falling Edge Detector
10: Both Edge Detector
11: Both Edge Delay
Select the Edge Mode of Programmable De
lay & Edge Detector
-
557
558
559
00: 125ns
Delay Value Select for Programmable Delay 01: 250ns
& Edge Detector
10: 375ns
11: 500ns
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
560
561
562
[3]:LUT2_0 [3]/DFF0 or LATCH Select
0: DFF function
1: LATCH function
[2]:LUT2_0 [2]/DFF0 Output Select
0: Q output
LUT2_0/DFF0 setting
1: QB output
[1]:LUT2_0 [1]/DFF0 Initial Polarity Select
0: Low
563
46
1: High
[0]:LUT2_0 [0]
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
LUT2_1_VAL or PGen_data
LUT2_1[3:0] or PGen 4bit counter data[3:0]
47
PGen data
PGen Data[15:0]
48
[7]:LUT3_0 [7]/DFF1 or LATCH Select
0: DFF function
1: LATCH function
[6]:LUT3_0 [6]/DFF1 Output Select
0: Q output
1: QB output
49
LUT3_0_DFF1 setting
[5]:LUT3_0 [5]/DFF1
0: nRST from Matrix Output
1: nSET from Matrix Output
[4]:LUT3_0 [4]/DFF1 Initial Polarity Select
0: Low,
591
1: High
[3:0]: LUT3_0 [3:0]
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
592
593
594
595
596
597
598
[7]:LUT3_1 [7]/DFF2 or LATCH Select
0: DFF function
1: LATCH function
[6]:LUT3_1 [6]/DFF2 Output Select
0: Q output
1: QB output
4A
LUT3_1_DFF2 setting
[5]:LUT3_1 [5]/DFF2
0: nRST from Matrix Output
1: nSET from Matrix Output
[4]:LUT3_1 [4]/DFF2 Initial Polarity Select
0: Low
599
1: High
[3:0]: LUT3_1 [3:0]
600
601
602
603
604
605
606
[7]:LUT3_2 [7]/DFF3 or LATCH Select
0: DFF function,
1: LATCH function
[6]:LUT3_2 [6]/DFF3 Output Select
0: Q output
1: QB output
[5]:LUT3_2 [5]/DFF3
0: nRST from Matrix Output
1: nSET from Matrix Output
[4]:LUT3_2 [4]/DFF3 Initial Polarity Select
0: Low
4B
LUT3_2_DFF3 setting
607
1: High [
3:0]: LUT3_2 [3:0]
608
609
610
611
612
613
614
[7]:LUT3_3 [7]/DFF4 or LATCH Select
0: DFF function
1: LATCH function
[6]:LUT3_3 [6]/DFF4 Output Select
0: Q output
1: QB output
[5]:LUT3_3 [5]/DFF4
0: nRST from Matrix Output
1: nSET from Matrix Output
[4]:LUT3_3 [4]/DFF4 Initial Polarity Select
0: Low
4C
LUT3_3_DFF4 setting
615
1: High
[3:0]: LUT3_3 [3:0]
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
0: LUT2_0
1: DFF0
616
617
618
619
620
621
LUT2_0 or DFF0 Select
LUT2_1 or PGen Select
LUT3_0 or DFF1 Select
DFF1_SECONDQ_Sel
LUT3_1 or DFF2 Select
LUT3_2 or DFF3 Select
0: LUT2_1
1: PGen
0: LUT3_0
1: DFF1
0: Q of first DFF
1 Q of second DFF
4D
0: LUT3_1
1: DFF2
0: LUT3_2
1: DFF3
0: LUT3_3
1: DFF4
622
623
624
625
626
627
LUT3_3 or DFF4 Select
Reserved
0: CHOP enable
1: chopper off
BG CHOP OFF
BG Chopper clock test enable
1: enable
Bandgap internal voltage output to Pin en
able
-
1: enable
00: 0 mV
4E
01: 32 mV
10: 64 mV
11: 192 mV
ACMP0_H hysteresis
628
629
630
Reserved
ACMP0_H input buffer enable
1: enable
631
632
633
Reserved
ACMP0_H input tie to VDD enable
1: enable
1: enable
ACMP1_H positive input come from AC
MP0_H's input mux output enable
-
634
635
Reserved
00: 0 mV
01: 32 mV
10: 64 mV
11: 192 mV
ACMP1_H hysteresis
636
4F
0: disable
1: enable
637
638
639
ACMP1_H input buffer enable
Reserved
ACMP2_L positive input come from AC
MP0_H's input mux output enable
-
1: enable
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
ACMP2_L positive input come from AC
MP1_H's input mux output enable
-
640
641
1: enable
00: 0 mV
01: 32 mV
10: 64 mV
11: 192 mV
ACMP2_L hysteresis
642
643
644
645
Reserved
Reserved
50
00: 0 mV
01: 32 mV
10: 64 mV
11: 192 mV
ACMP3_L hysteresis
646
647
648
Reserved
Reserved
ACMP3_L positive input come from AC
MP2_L's input mux output enable
-
649
650
651
652
1: enable
0: Power-down
1: Power-On
Temp sensor register pd control
Temp sensor register pd select
Temp sensor range select
Vref0 output OP
0: from register
1: from matrix
51
0: range 1 (0.62 V ~ 0.99 V (TYP))
1: range 2 (0.75 V ~ 1.2 V (TYP))
0: disable
1: enable
653
654
00: None
01: ACMP0_H Vref
10: ACMP1_H Vref
11: temp sensor
Vref0 input selection
655
656
0: disable
1: enable
Vref1 output OP
657
658
00: None
01: ACMP2_L Vref
10: ACMP3_L Vref
Vref1 input selection
52
659
660
661
662
663
Reserved
ACMP0_H Wake/sleep enable
1: enable
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
664
ACMP1_H Wake/sleep enable
1: enable
0: short time
1: normal w/s
665
ACMP wake/sleep time selection,
666
667
668
ACMP0_H 100uA current source enable
Reserved for ACMP
1: enable
Reserved
53
ACMP3_L input come from Temp sensor
output enable
669
670
671
1: enable
0: disable
1: enable
IO fast Pull-up/down enable
8 GPO outputs skew enable
0: disable
1: enable
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
672
673
674
675
00: Push-Pull 1x
01: Push-Pull 2x
10: 1x Open-Drain
11: 2x Open-Drain
GPO7output mode configuration
GPO7Pull-up/down resistance selection
00: floating
01: 10K
10: 100K
11: 1M
54
0: Pull-down
1: Pull-up
676
677
GPO7Pull-up/down selection
GPO7digital output source selection
GPO7output enable
0: from matrix
1: from ASM (ASM output to GPO bit[0])
0: disable
1: enable.
678
679
00: Push-Pull 1x
01: Push-Pull 2x
10: 1x Open-Drain
11: 2x Open-Drain
GPO0output mode configuration
680
681
682
00: floating
01: 10K
10: 100K
11: 1M
GPO0Pull-up/down resistance selection
0: Pull-down
1: Pull-up
683
684
685
GPO0Pull-up/down selection
GPO0digital output source selection
GPO0output enable
55
0: from matrix
1: from ASM (ASM output to GPO bit[1])
0: disable
1: enable
GPIO0ultra-low powerdigitalinenable(only 0: disable
686
687
used in SLG46881)
1: enable
00: digital without Schmitt Trigger
01: digital with Schmitt Trigger
10: low voltage digital in
11: analog IO
GPIO0input mode configuration
688
689
690
691
692
00: Push-Pull 1x
01: Push-Pull 2x
10: 1x Open-Drain
11: 2x Open-Drain
GPIO0output mode configuration
00: floating
01: 10K
10: 100K
11: 1M
56
GPIO0Pull-up/down resistance selection
0: Pull-down
1: Pull-up
693
694
695
GPIO0Pull-up/down selection
Reserved
GPIO1 ultra-low powerdigitalinenable(only 0: disable
used in SLG46881) 1: enable
Datasheet
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204 of 353
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© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
696
697
698
699
700
701
00: digital without Schmitt Trigger
01: digital with Schmitt Trigger
10: low voltage digital in
11: analog IO
GPIO1input mode configuration
GPIO1output mode configuration
00: Push-Pull 1x
01: Push-Pull 2x
10: 1x Open-Drain
11: 2x Open-Drain
57
00: floating
01: 10K
10: 100K
GPIO1Pull-up/down resistance selection
11: 1M
0: Pull-down
1: Pull-up
702
703
704
705
GPIO1Pull-up/down selection
Reserved
GPIO2ultra-low powerdigitalinenable(only 0: disable
used in SLG46881)
1: enable
00: without LATCH
01: normal LATCH
10: input data 0 LATCH (when LATCH_en is high)
11: input data 1 LATCH (when LATCH_en is high)
GPIO2digital input LATCH configuration
706
707
708
709
710
711
712
00: digital without Schmitt Trigger
01: digital with Schmitt Trigger
10: low voltage digital in
11: analog IO
58
GPIO2input mode configuration
GPIO2output mode configuration
00: Push-Pull 1x
01: Push-Pull 2x
10: 1x Open-Drain
11: 2x Open-Drain
00: floating
01: 10K
10: 100K
11: 1M
GPIO2Pull-up/down resistance selection
GPIO2Pull-up/down selection
0: Pull-down
1: Pull-up
713
714
00: without LATCH
01: normal LATCH
10: input data 0 LATCH (when LATCH_en is high)
GPI0digital input LATCH configuration
715
716
717
718
719
11: input data 1 LATCH (when LATCH_en is high)
59
00: digital without Schmitt Trigger
01: digital with Schmitt Trigger
10: low voltage digital in
11: analog IO
GPI0input mode configuration
00: floating
01: 10K
10: 100K
11: 1M
GPI0Pull-up/down resistance selection
Datasheet
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Revision 3.12
205 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
0: Pull-down
1: Pull-up
720
GPI0Pull-up/down selection
GPI1 ultra-low power digital in enable (only 0: disable
721
722
used in SLG46881)
1: enable
00: without LATCH
01: normal LATCH
10: input data 0 LATCH (when LATCH_en is high)
11: input data 1 LATCH (when LATCH_en is high)
GPI1digital input LATCH configuration
723
724
725
726
727
5A
00: digital without Schmitt Trigger
01: digital with Schmitt Trigger
10: low voltage digital in
11: analog IO
GPI1input mode configuration
00: floating
01: 10K
10: 100K
GPI1Pull-up/down resistance selection
GPI1Pull-up/down selection
11: 1M
0: Pull-down
1: Pull-up
728
GPI2 ultra-low power digital in enable (only 0: disable
729
730
used in SLG46881)
1: enable
00: digital in without Schmitt Trigger
01: digital in with Schmitt Trigger
(when register [4084] = 1)
10: low voltage digital in
11: Reserved
GPI2/SDA input mode configuration
731
5B
732
733
00: floating
01: 10K
10: 100K
GPI2/SDA Pull-up/down resistance selec
tion
-
11: 1M
0: Pull-down
1: Pull-up
734
GPI2/SDAPull-up/down selection
GPI3 ultra-low power digital in enable (only 0: disable
735
736
used in SLG46881)
1: enable
00: digital in without Schmitt Trigger
01: digital in with Schmitt Trigger
(when register [4084] = 1)
10: low voltage digital in
11: Reserved
GPI3/SCL input mode configuration
737
738
739
00: floating
01: 10K
10: 100K
GPI3/SCLPull-up/down resistance selection
GPI3/SCLPull-up/down selection
11: 1M
5C
0: Pull-down
1: Pull-up
740
GPIO3ultra-low powerdigitalinenable(only 0: disable
741
742
used in SLG46881)
1: enable
00: without LATCH
01: normal LATCH
10: input data 0 LATCH (when LATCH_en is high)
11: input data 1 LATCH (when LATCH_en is high)
GPIO3digital input LATCH configuration
743
Datasheet
25-Feb-2021
Revision 3.12
206 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
744
745
746
747
748
749
00: digital without Schmitt Trigger
01: digital with Schmitt Trigger
10: low voltage digital in
11: analog IO.
GPIO3input mode configuration
GPIO3output mode configuration
00: Push-Pull 1x
01: Push-Pull 2x
10: 1x Open-Drain
11: 2x Open-Drain
5D
00: floating
01: 10K
10: 100K
GPIO3Pull-up/down resistance selection
GPIO3Pull-up/down selection
11: 1M
0: Pull-down
1: Pull-up
750
751
752
753
Reserved
Reserved
00: digital without Schmitt Trigger
01: digital with Schmitt Trigger
10: low voltage digital in
11: analog IO
GPIO4input mode configuration
754
755
756
757
758
00: Push-Pull 1x
01: Push-Pull 2x
10: 1x Open-Drain
11: 2x Open-Drain
GPIO4output mode configuration
GPIO4Pull-up/down resistance selection
5E
00: floating
01: 10K
10: 100K
11: 1M
0: Pull-down
1: Pull-up
759
GPIO4Pull-up/down selection
Reserved
760
761
00: digital without Schmitt Trigger
01: digital with Schmitt Trigger
10: low voltage digital in
11: analog IO
GPIO5input mode configuration
GPIO5output mode configuration
762
763
764
765
766
00: Push-Pull 1x
01: Push-Pull 2x
10: 1x Open-Drain
11: 2x Open-Drain
5F
00: floating
01: 10K
10: 100K
GPIO5Pull-up/down resistance selection
GPIO5Pull-up/down selection
11: 1M
0: Pull-down
1: Pull-up
767
Datasheet
25-Feb-2021
Revision 3.12
207 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
768
769
770
771
00: Push-Pull 1x
01: Push-Pull 2x
10: 1x Open-Drain
11: 2x Open-Drain
GPO1output mode configuration
GPO1Pull-up/down resistance selection
00: floating
01: 10K
10: 100K
11: 1M
60
0: Pull-down
1: Pull-up
772
773
GPO1Pull-up/down selection
GPO1digital output source selection
GPO1output enable
0: from matrix
1: from ASM (ASM output to GPO bit[2])
0: disable
1: enable.
774
775
00: Push-Pull 1x
01: Push-Pull 2x
10: 1x Open-Drain
11: 2x Open-Drain
GPO2output mode configuration
776
777
778
00: floating
01: 10K
10: 100K
11: 1M
GPO2Pull-up/down resistance selection
0: Pull-down
1: Pull-up
779
780
GPO2Pull-up/down selection
GPO2digital output source selection
GPO2output enable
61
0: from matrix
1: from ASM (ASM output to GPO bit[3]).
0: disable
1: enable.
781
782
00: Push-Pull 1x
01: Push-Pull 2x
10: 1x Open-Drain
11: 2x Open-Drain
GPO3output mode configuration
783
784
785
00: floating
01: 10K
10: 100K
GPO3Pull-up/down resistance selection
11: 1M
0: Pull-down
1: Pull-up
786
787
GPO3Pull-up/down selection
GPO3digital output source selection
GPO3output enable
0: from matrix
1: from ASM (ASM output to GPO bit[4]).
62
0: disable
1: enable.
788
789
00: Push-Pull 1x
01: Push-Pull 2x
10: 1x Open-Drain
11: 2x Open-Drain
GPO4output mode configuration
790
791
792
00: floating
01: 10K
10: 100K
11: 1M
GPO4Pull-up/down resistance selection
63
Datasheet
25-Feb-2021
Revision 3.12
208 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
0: Pull-down
1: Pull-up
793
794
795
GPO4Pull-up/down selection
0: from matrix
1: from ASM (ASM output to GPO bit[5]).
GPO4digital output source selection
0: disable
1: enable.
GPO4output enable
Reserved
63
796
797
00: without LATCH
01: normal LATCH
10: input data 0 LATCH (when LATCH_en is high)
11: input data 1 LATCH (when LATCH_en is high)
GPIO6digital input LATCH configuration
GPIO6input mode configuration
798
799
800
801
802
803
804
00: digital without Schmitt Trigger
01: digital with Schmitt Trigger
10: low voltage digital in
11: analog IO.
00: Push-Pull 1x
01: Push-Pull 2x
10: 1x Open-Drain
11: 2x Open-Drain
GPIO6output mode configuration
00: floating
01: 10K
10: 100K
11: 1M.
64
GPIO6Pull-up/down resistance selection
GPIO6Pull-up/down selection
0: Pull-down
1: Pull-up
805
806
807
808
Reserved
Reserved
00: without LATCH
01: normal LATCH
10: input data 0 LATCH (when LATCH_en is high)
11: input data 1 LATCH (when LATCH_en is high)
GPIO7digital input LATCH configuration
GPIO7input mode configuration
809
810
811
812
813
814
815
00: digital without Schmitt Trigger
01: digital with Schmitt Trigger
10: low voltage digital in
11: analog IO
65
00: Push-Pull 1x
01: Push-Pull 2x
10: 1x Open-Drain
11: 2x Open-Drain
GPIO7output mode configuration
GPIO7Pull-up/down resistance selection
00: floating
01: 10K
10: 100K
11: 1M
Datasheet
25-Feb-2021
Revision 3.12
209 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
0: Pull-down
1: Pull-up
816
817
818
819
GPIO7Pull-up/down selection
Reserved
GPIO8ultra-low powerdigitalinenable(only 0: disable
used in SLG46881)
1: enable
00: digital without Schmitt Trigger
01: digital with Schmitt Trigger
10: low voltage digital in
11: analog IO
66
GPIO8input mode configuration
820
821
822
823
824
00: Push-Pull 1x
01: Push-Pull 2x
10: 1x Open-Drain
11: 2x Open-Drain
GPIO8output mode configuration
00: floating
01: 10K
10: 100K
11: 1M
GPIO8Pull-up/down resistance selection
GPIO8Pull-up/down selection
0: Pull-down
1: Pull-up
825
GPI4 ultra-low power digital in enable (only 0: disable
826
827
used in SLG46881)
1: enable
00: without LATCH
67
01: normal LATCH
10: input data 0 LATCH (when LATCH_en is high)
11: input data 1 LATCH (when LATCH_en is high)
GPI4digital input LATCH configuration
828
829
830
831
832
00: digital without Schmitt Trigger
01: digital with Schmitt Trigger
10: low voltage digital in
11: analog IO
GPI4input mode configuration
00: floating
01: 10K
10: 100K
11: 1M
GPI4Pull-up/down resistance selection
GPI4Pull-up/down selection
0: Pull-down
1: Pull-up
833
GPI5 ultra-low power digital in enable (only 0: disable
834
835
used in SLG46881)
1: enable
68
00: without LATCH
01: normal LATCH
10: input data 0 LATCH (when LATCH_en is high)
11: input data 1 LATCH (when LATCH_en is high)
GPI5digital input LATCH configuration
836
837
838
00: digital without Schmitt Trigger
01: digital with Schmitt Trigger
10: low voltage digital in
11: analog IO
GPI5input mode configuration
Datasheet
25-Feb-2021
Revision 3.12
210 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
68
839
00: floating
01: 10K
10: 100K
11: 1M
GPI5Pull-up/down resistance selection
GPI5Pull-up/down selection
840
0: Pull-down
1: Pull-up
69
841
GPI6 ultra-low power digital in enable (only 0: disable
842
843
used in SLG46881)
1: enable
00: digital without Schmitt Trigger
01: digital with Schmitt Trigger
10: low voltage digital in
11: analog IO
GPI6input mode configuration
844
845
846
00: floating
01: 10K
10: 100K
69
GPI6Pull-up/down resistance selection
GPI6Pull-up/down selection
11: 1M
0: Pull-down
1: Pull-up
847
Datasheet
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Revision 3.12
211 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
GPI7 ultra-low power digital in enable (only 0: disable
848
849
used in SLG46881)
1: enable
00: digital without Schmitt Trigger
01: digital with Schmitt Trigger
10: low voltage digital in
11: analog IO
GPI7input mode configuration
850
851
852
00: floating
01: 10K
10: 100K
11: 1M
6A
GPI7Pull-up/down resistance selection
GPI7Pull-up/down selection
0: Pull-down
1: Pull-up
853
GPIO9ultra-low powerdigitalinenable(only 0: disable
854
855
used in SLG46881)
1: enable
00: digital without Schmitt Trigger
01: digital with Schmitt Trigger
10: low voltage digital in
11: analog IO
GPIO9input mode configuration
856
857
858
859
860
00: Push-Pull 1x
01: Push-Pull 2x
10: 1x Open-Drain
11: 2x Open-Drain
GPIO9output mode configuration
00: floating
01: 10K
10: 100K
11: 1M
6B
GPIO9Pull-up/down resistance selection
GPIO9Pull-up/down selection
0: Pull-down
1: Pull-up
861
GPIO10 ultra-low power digital in enable
(only used in SLG46881)
0: disable
1: enable
862
863
00: digital without Schmitt Trigger
01: digital with Schmitt Trigger
10: low voltage digital in
11: analog IO
GPIO10input mode configuration
GPIO10output mode configuration
864
865
866
867
868
00: Push-Pull 1x
01: Push-Pull 2x
10: 1x Open-Drain
11: 2x Open-Drain
00: floating
01: 10K
10: 100K
11: 1M.
6C
GPIO10Pull-up/down resistance selection
GPIO10Pull-up/down selection
0: Pull-down
1: Pull-up
869
870
GPIO11 ultra-low power digital in enable (on
ly used in SLG46881)
-
0: disable
1: enable
Datasheet
25-Feb-2021
Revision 3.12
212 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
6C
871
872
873
874
875
876
00: digital without Schmitt Trigger
01: digital with Schmitt Trigger
10: low voltage digital in
11: analog IO
GPIO11input mode configuration
GPIO11output mode configuration
00: Push-Pull 1x
01: Push-Pull 2x
10: 1x Open-Drain
11: 2x Open-Drain
00: floating
01: 10K
10: 100K
6D
GPIO11Pull-up/down resistance selection
11: 1M
0: Pull-down
1: Pull-up
877
GPIO11Pull-up/down selection
Reserved
878
879
00: Push-Pull 1x
01: Push-Pull 2x
10: 1x Open-Drain
11: 2x Open-Drain
GPO5output mode configuration
880
881
882
00: floating
01: 10K
10: 100K
GPO5Pull-up/down resistance selection
11: 1M
0: Pull-down
1: Pull-up
883
884
GPO5Pull-up/down selection
GPO5digital output source selection
GPO5output enable
6E
0: from matrix
1: from ASM (ASM output to GPO bit[6])
0: disable
1: enable
885
886
00: Push-Pull 1x
01: Push-Pull 2x
10: 1x Open-Drain
11: 2x Open-Drain
GPO6output mode configuration
887
888
889
00: floating
01: 10K
10: 100K
11: 1M
GPO6Pull-up/down resistance selection
0: Pull-down
1: Pull-up
890
891
892
893
GPO6Pull-up/down selection
GPO6digital output source selection
GPO6output enable
0: from matrix
1: from ASM (ASM output to GPO bit[7]).
6F
0: disable
1: enable
0: I2C fast mode +
I2C mode selection
1: I2C standard/fast mode
1: xtal enable is controlled by matrix out78 and matrix
- in51 source is from Xtal OSC
0: xtal is powered down and matrix in51 source is from
XTALenable and matrix in51 source mux se
lect
894
GPI4
Datasheet
25-Feb-2021
Revision 3.12
213 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
0: matrix enable signal (matrix out78) is gated and xtal
is controlled by register [894]
1: matrix enable signal is effective if register [894] = 1
(matrix out78 = 0 → off, matrix out78 = 1 → on)
6F
895
XTAL matrix enable signal gating
DLY/CNT0 Mode Selection
896
897
898
899
00:DLY
01: one shot
10: frequency det
11: cnt register [913] = 0
00:both edge
01: falling edge
10: rising edge
11: High LevelReset (only inCNTmode)
DLY/CNT0 edge Mode Selection
900
901
902
Clock source sel[3:0]
0000: 25M;
0001: 25M/4;
0010: 2.048M
70
0011: 2.048M/8;
0100: 2.048M/64;
0101: 2.048M/512;
0110: 2.048K;
DLY/CNT0 Clock Source Select
0111: 2.048K/8;
1000: 2.048K/64;
1001: 2.048K/512;
1010: 2.048K/4096
1011: 2.048K/32768;
1100: 2.048K/262144;
1101: CNT4_END;
1110: External;
903
904
1111: Not used
0: Reset to 0
1: Set to data
FSM0 SET/RST Selection
CNT0 output pol selection
0: Default Output
1: Inverted Output
905
906
00: bypass the initial
01: initial 0
10: initial 1
CNT0 initial value selection
907
11: initial 1
71
0: LUT4_0
1: DLY/CNT0(16bits)
908
909
910
911
lut4_0 or DLY/CNT0 selection
Wake sleep power-down state selection
wake sleep mode selection
0: (low)
1: (high)
0: Default Mode
1: Wake Sleep Mode (registers [897:896] = 11)
0: bypass
1: after two DFFs
Keep signal SYNC selection
Datasheet
25-Feb-2021
Revision 3.12
214 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
0: bypass
1: after two DFFs
912
913
914
915
UP signal SYNC selection
0: normal
CNT0 DLY EDET FUNCTION Selection
CNT0 CNT mode SYNC selection
CNT1 CNT mode SYNC selection
1: DLY function edge detection (registers [897:896] = 00)
72
0: bypass
1: after two DFFs
0: bypass
1: after two DFFs
916
917
918
Clock source sel[3:0]
0000: 25M;
0001: 25M/4;
0010: 2.048M
0011: 2.048M/8;
0100: 2.048M/64;
0101: 2.048M/512;
0110: 2.048K;
0111: 2.048K/8;
1000: 2.048K/64;
1001: 2.048K/512;
1010: 2.048K/4096
1011: 2.048K/32768;
1100: 2.048K/262144;
1101: CNT0_END;
1110: External;
72
DLY/CNT1 Clock Source Select
919
1111: Not used
920
921
00: bypass the initial
01: initial 0
10: initial 1
CNT1 initial value selection
11: initial 1
922
923
924
0000: Both Edge Delay
0001: Falling Edge Delay
0010: Rising Edge Delay
0011: Both Edge One Shot
0100: Falling Edge One Shot
0101: Rising Edge One Shot
0110: Both Edge Freq Detect
0111: Falling Edge Freq Detect
1000: Rising Edge Freq Detect
1001: Both Edge Detect
1010: Falling Edge Detect
1011: Rising Edge Detect
1100: Both Edge Reset CNT
1101: Falling Edge Reset CNT
1110: Rising Edge Reset CNT
1111: High Level Reset CNT
CNT1 function and edge mode selection
73
925
0: Default Output
1: Inverted Output
926
CNT1 output pol selection
0: LUT3_4
1: DLY/CNT1(8bits)
927
928
LUT3_4 or CNT_1 selection
74
CNT2 CNT mode SYNC selection
0: bypass; 1: after two DFFs
Datasheet
25-Feb-2021
Revision 3.12
215 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
929
930
931
Clock source sel[3:0]
0000: 25M;
0001: 25M/4;
0010: 2.048M
0011: 2.048M/8;
0100: 2.048M/64;
0101: 2.048M/512;
0110: 2.048K;
0111: 2.048K/8;
1000: 2.048K/64;
1001: 2.048K/512;
1010: 2.048K/4096
1011: 2.048K/32768;
1100: 2.048K/262144;
1101: CNT1_END;
1110: External;
DLY/CNT2 Clock Source Select
932
74
1111: Not used
933
934
00: bypass the initial
01: initial 0
10: initial 1
CNT2 initial value selection
11: initial 1
935
936
937
0000: Both Edge Delay
0001: Falling Edge Delay
0010: Rising Edge Delay
0011: Both Edge One Shot
0100: Falling Edge One Shot
0101: Rising Edge One Shot
0110: Both Edge Freq Detect
0111: Falling Edge Freq Detect
1000: Rising Edge Freq Detect
1001: Both Edge Detect
CNT2 function and edge mode selection
1010: Falling Edge Detect
1011: Rising Edge Detect
1100: Both Edge Reset CNT
1101: Falling Edge Reset CNT
1110: Rising Edge Reset CNT
1111: High Level Reset CNT
register [941] = 0
938
75
0: Default Output
1: Inverted Output
939
940
CNT2 output pol selection
LUT3_5 or CNT_2 selection
0: LUT3_5
1: DLY/CNT2(8bits)
0: normal
941
942
CNT2 DLY EDET FUNCTION Selection
CNT3 CNT mode SYNC selection
1: DLY function edge detection
(registers [938:935]=0000/0001/0010)
0: bypass
1: after two DFFs
Datasheet
25-Feb-2021
Revision 3.12
216 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
75
943
944
945
Clock source sel[3:0]
0000: 25M;
0001: 25M/4;
0010: 2.048M
0011: 2.048M/8;
0100: 2.048M/64;
0101: 2.048M/512;
0110: 2.048K;
0111: 2.048K/8;
1000: 2.048K/64;
1001: 2.048K/512;
1010: 2.048K/4096
1011: 2.048K/32768;
1100: 2.048K/262144;
1101: CNT2_END;
1110: External;
DLY/CNT3 Clock Source Select
946
76
1111: Not used
947
948
00: bypass the initial
01: initial 0
10: initial 1
CNT3 initial value selection
11: initial 1
949
950
951
0000: Both Edge Delay
0001: Falling Edge Delay
0010: Rising Edge Delay
0011: Both Edge One Shot
0100: Falling Edge One Shot
0101: Rising Edge One Shot
0110: Both Edge Freq Detect
0111: Falling Edge Freq Detect
1000: Rising Edge Freq Detect
1001: Both Edge Detect
1010: Falling Edge Detect
1011: Rising Edge Detect
1100: Both Edge Reset CNT
1101: Falling Edge Reset CNT
1110: Rising Edge Reset CNT
1111: High Level Reset CNT
CNT3 function and edge mode selection
952
77
0: Default Output
1: Inverted Output
953
954
955
CNT3 output pol selection
0: LUT3_6
1: DLY/CNT3(8bits)
LUT3_6 or CNT_3 selection
CNT4 CNT mode SYNC selection
0: bypass
1: after two DFFs
Datasheet
25-Feb-2021
Revision 3.12
217 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
956
957
958
Clock source sel[3:0]
0000: 25M;
0001: 25M/4;
0010: 2.048M
0011: 2.048M/8;
0100: 2.048M/64;
0101: 2.048M/512;
0110: 2.048K;
0111: 2.048K/8;
1000: 2.048K/64;
1001: 2.048K/512;
1010: 2.048K/4096
1011: 2.048K/32768;
1100: 2.048K/262144;
1101: CNT3_END;
1110: External;
77
DLY/CNT4 Clock Source Select
959
1111: Not used
960
961
00: bypass the initial
01: initial 0
10: initial 1
CNT4 initial value selection
11: initial 1
962
963
964
0000: Both Edge Delay
0001: Falling Edge Delay
0010: Rising Edge Delay
0011: Both Edge One Shot
0100: Falling Edge One Shot
0101: Rising Edge One Shot
0110: Both Edge Freq Detect
0111: Falling Edge Freq Detect
1000: Rising Edge Freq Detect
1001: Both Edge Detect
1010: Falling Edge Detect
1011: Rising Edge Detect
1100: Both Edge Reset CNT
1101: Falling Edge Reset CNT
1110: Rising Edge Reset CNT
1111: High Level Reset CNT
CNT4 function and edge mode selection
78
965
0: Default Output
1: Inverted Output
966
967
CNT4 output pol selection
0: LUT3_7
1: DLY/CNT4(8bits)
LUT3_7 or CNT_4 selection
REG_TEST_EN
79
79
968
969
970
971
972
973
974
975
Reserved
Reserved
Reserved
Reserved
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
976
977
Memory for GPO 0
Memory for GPO 1
Memory for GPO 2
Memory for GPO 3
Memory for GPO 4
Memory for GPO 5
Memory for GPO 6
Memory for GPO 7
Memory for GPO 0
Memory for GPO 1
Memory for GPO 2
Memory for GPO 3
Memory for GPO 4
Memory for GPO 5
Memory for GPO 6
Memory for GPO 7
Memory for GPO 0
Memory for GPO 1
Memory for GPO 2
Memory for GPO 3
Memory for GPO 4
Memory for GPO 5
Memory for GPO 6
Memory for GPO 7
Memory for GPO 0
Memory for GPO 1
Memory for GPO 2
Memory for GPO 3
Memory for GPO 4
Memory for GPO 5
Memory for GPO 6
Memory for GPO 7
Memory for GPO 0
Memory for GPO 1
Memory for GPO 2
Memory for GPO 3
Memory for GPO 4
Memory for GPO 5
Memory for GPO 6
Memory for GPO 7
978
979
7A
ASM State 0 Output Memory for 8 GPOs
980
981
982
983
984
985
986
987
7B
7C
7D
7E
ASM State 1 Output Memory for 8 GPOs
ASM State 2 Output Memory for 8 GPOs
ASM State 3 Output Memory for 8 GPOs
ASM State 4 Output Memory for 8 GPOs
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
Datasheet
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Revision 3.12
219 of 353
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© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
Memory for GPO 0
Memory for GPO 1
Memory for GPO 2
Memory for GPO 3
Memory for GPO 4
Memory for GPO 5
Memory for GPO 6
Memory for GPO 7
Memory for GPO 0
Memory for GPO 1
Memory for GPO 2
Memory for GPO 3
Memory for GPO 4
Memory for GPO 5
Memory for GPO 6
Memory for GPO 7
Memory for GPO 0
Memory for GPO 1
Memory for GPO 2
Memory for GPO 3
Memory for GPO 4
Memory for GPO 5
Memory for GPO 6
Memory for GPO 7
Memory for GPO 0
Memory for GPO 1
Memory for GPO 2
Memory for GPO 3
Memory for GPO 4
Memory for GPO 5
Memory for GPO 6
Memory for GPO 7
Memory for GPO 0
Memory for GPO 1
Memory for GPO 2
Memory for GPO 3
Memory for GPO 4
Memory for GPO 5
Memory for GPO 6
Memory for GPO 7
7F
ASM State 5 Output Memory for 8 GPOs
80
81
82
83
ASM State 6 Output Memory for 8 GPOs
ASM State 7 Output Memory for 8 GPOs
ASM State 8 Output Memory for 8 GPOs
ASM State 9 Output Memory for 8 GPOs
Datasheet
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Revision 3.12
220 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
Memory for GPO 0
Memory for GPO 1
Memory for GPO 2
Memory for GPO 3
84
ASM State 10 Output Memory for 8 GPOs
Memory for GPO 4
Memory for GPO 5
Memory for GPO 6
Memory for GPO 7
Memory for GPO 0
Memory for GPO 1
Memory for GPO 2
Memory for GPO 3
85
86
87
88
ASM State 11 Output Memory for 8 GPOs
Memory for GPO 4
Memory for GPO 5
Memory for GPO 6
Memory for GPO 7
Memory for Matrix input 0
Memory for Matrix input 1
Memory for Matrix input 2
Memory for Matrix input 3
Memory for Matrix input 0
Memory for Matrix input 1
Memory for Matrix input 2
Memory for Matrix input 3
Memory for Matrix input 0
Memory for Matrix input 1
Memory for Matrix input 2
Memory for Matrix input 3
Memory for Matrix input 0
Memory for Matrix input 1
Memory for Matrix input 2
Memory for Matrix input 3
Memory for Matrix input 0
Memory for Matrix input 1
Memory for Matrix input 2
Memory for Matrix input 3
Memory for Matrix input 0
Memory for Matrix input 1
Memory for Matrix input 2
Memory for Matrix input 3
ASM State 0 Output Memory for Matrix Input
ASM State 1 Output Memory for Matrix Input
ASM State 2 Output Memory for Matrix Input
ASM State 3 Output Memory for Matrix Input
ASM State 4 Output Memory for Matrix Input
ASM State 5 Output Memory for Matrix Input
Datasheet
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Revision 3.12
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
Memory for Matrix input 0
Memory for Matrix input 1
Memory for Matrix input 2
Memory for Matrix input 3
Memory for Matrix input 0
Memory for Matrix input 1
Memory for Matrix input 2
Memory for Matrix input 3
Memory for Matrix input 0
Memory for Matrix input 1
Memory for Matrix input 2
Memory for Matrix input 3
Memory for Matrix input 0
Memory for Matrix input 1
Memory for Matrix input 2
Memory for Matrix input 3
Memory for Matrix input 0
Memory for Matrix input 1
Memory for Matrix input 2
Memory for Matrix input 3
Memory for Matrix input 0
Memory for Matrix input 1
Memory for Matrix input 2
Memory for Matrix input 3
ASM State 6 Output Memory for Matrix Input
89
ASM State 7 Output Memory for Matrix Input
ASM State 8 Output Memory for Matrix Input
ASM State 9 Output Memory for Matrix Input
8A
8B
8С
ASM State 10 Output Memory for Matrix In
put
-
ASM State 11 Output Memory for Matrix In
put
-
ASM Initial State Selection
Reserved registers for ASM
0000 → 1011: State 0 → State 11
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
OUT0_Setting0:
REG_MATRIX_IN_SEL[5:0]
6Bit MATRIX_IN_Setting0
8D
OUT0_Setting0:
REG_MATRIX_IN_SEL[11:6]
6Bit MATRIX_IN_Setting1
6Bit MATRIX_IN_Setting2
6Bit MATRIX_IN_Setting3
8E
OUT0_Setting0:
REG_MATRIX_IN_SEL[17:12]
8F
OUT0_Setting0:
REG_MATRIX_IN_SEL[23:18]
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
OUT1_Setting0:
REG_MATRIX_IN_SEL[5:0]
6Bit MATRIX_IN_Setting0
90
OUT1_Setting0:
REG_MATRIX_IN_SEL[11:6]
6Bit MATRIX_IN_Setting1
6Bit MATRIX_IN_Setting2
6Bit MATRIX_IN_Setting3
91
OUT1_Setting0:
REG_MATRIX_IN_SEL[17:12]
92
OUT1_Setting0:
REG_MATRIX_IN_SEL[23:18]
Datasheet
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Revision 3.12
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CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
OUT2_Setting0:
REG_MATRIX_IN_SEL[5:0]
6Bit MATRIX_IN_Setting0
93
OUT2_Setting0:
REG_MATRIX_IN_SEL[11:6]
6Bit MATRIX_IN_Setting1
6Bit MATRIX_IN_Setting2
6Bit MATRIX_IN_Setting3
94
OUT2_Setting0:
REG_MATRIX_IN_SEL[17:12]
95
95
OUT2_Setting0:
REG_MATRIX_IN_SEL[23:18]
00: Settings 0
01: Settings 1
10: Settings 2
11: Settings 3
State0_6BitMatrix_OUT0
4 Settings selection
1201
1202
1203
1204
1205
1206
1207
00: Settings 0
01: Settings 1
10: Settings 2
11: Settings 3
State0_6BitMatrix_OUT1
4 Settings selection
96
00: Settings 0
01: Settings 1
10: Settings 2
11: Settings 3
State0_6BitMatrix_OUT2
4 Settings selection
00: Settings 0
01: Settings 1
10: Settings 2
11: Settings 3
State1_6BitMatrix_OUT0
4 Settings selection
Datasheet
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Revision 3.12
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
00: Settings 0
01: Settings 1
10: Settings 2
11: Settings 3
State1_6BitMatrix_OUT1
4 Settings selection
00: Settings 0
01: Settings 1
10: Settings 2
11: Settings 3
State1_6BitMatrix_OUT2
4 Settings selection
97
00: Settings 0
01: Settings 1
10: Settings 2
11: Settings 3
State2_6BitMatrix_OUT0
4 Settings selection
00: Settings 0
01: Settings 1
10: Settings 2
11: Settings 3
State2_6BitMatrix_OUT1
4 Settings selection
00: Settings 0
01: Settings 1
10: Settings 2
11: Settings 3
State2_6BitMatrix_OUT2
4 Settings selection
00: Settings 0
01: Settings 1
10: Settings 2
11: Settings 3
State3_6BitMatrix_OUT0
4 Settings selection
98
98
00: Settings 0
01: Settings 1
10: Settings 2
11: Settings 3
State3_6BitMatrix_OUT1
4 Settings selection
00: Settings 0
01: Settings 1
10: Settings 2
11: Settings 3
State3_6BitMatrix_OUT2
4 Settings selection
00: Settings 0
01: Settings 1
10: Settings 2
11: Settings 3
State4_6BitMatrix_OUT0
4 Settings selection
00: Settings 0
01: Settings 1
10: Settings 2
11: Settings 3
State4_6BitMatrix_OUT1
4 Settings selection
99
00: Settings 0
01: Settings 1
10: Settings 2
11: Settings 3
State4_6BitMatrix_OUT2
4 Settings selection
00: Settings 0
01: Settings 1
10: Settings 2
11: Settings 3
State5_6BitMatrix_OUT0
4 Settings selection
Datasheet
25-Feb-2021
Revision 3.12
226 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
00: Settings 0
01: Settings 1
10: Settings 2
11: Settings 3
State5_6BitMatrix_OUT1
4 Settings selection
00: Settings 0
01: Settings 1
10: Settings 2
11: Settings 3
State5_6BitMatrix_OUT2
4 Settings selection
9A
00: Settings 0
01: Settings 1
10: Settings 2
11: Settings 3
State6_6BitMatrix_OUT0
4 Settings selection
00: Settings 0
01: Settings 1
10: Settings 2
11: Settings 3
State6_6BitMatrix_OUT1
4 Settings selection
00: Settings 0
01: Settings 1
10: Settings 2
11: Settings 3
State6_6BitMatrix_OUT2
4 Settings selection
00: Settings 0
01: Settings 1
10: Settings 2
11: Settings 3
State7_6BitMatrix_OUT0
4 Settings selection
9B
00: Settings 0
01: Settings 1
10: Settings 2
11: Settings 3
State7_6BitMatrix_OUT1
4 Settings selection
00: Settings 0
01: Settings 1
10: Settings 2
11: Settings 3
State7_6BitMatrix_OUT2
4 Settings selection
00: Settings 0
01: Settings 1
10: Settings 2
11: Settings 3
State8_6BitMatrix_OUT0
4 Settings selection
00: Settings 0
01: Settings 1
10: Settings 2
11: Settings 3
State8_6BitMatrix_OUT1
4 Settings selection
9C
00: Settings 0
01: Settings 1
10: Settings 2
11: Settings 3
State8_6BitMatrix_OUT2
4 Settings selection
00: Settings 0
01: Settings 1
10: Settings 2
11: Settings 3
State9_6BitMatrix_OUT0
4 Settings selection
Datasheet
25-Feb-2021
Revision 3.12
227 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
00: Settings 0
01: Settings 1
10: Settings 2
11: Settings 3
State9_6BitMatrix_OUT1
4 Settings selection
00: Settings 0
01: Settings 1
10: Settings 2
11: Settings 3
State9_6BitMatrix_OUT2
4 Settings selection
9D
00: Settings 0
01: Settings 1
10: Settings 2
11: Settings 3
State10_6BitMatrix_OUT0
4 Settings selection
00: Settings 0
01: Settings 1
10: Settings 2
11: Settings 3
State10_6BitMatrix_OUT1
4 Settings selection
00: Settings 0
01: Settings 1
10: Settings 2
11: Settings 3
State10_6BitMatrix_OUT2
4 Settings selection
00: Settings 0
01: Settings 1
10: Settings 2
11: Settings 3
State11_6BitMatrix_OUT0
4 Settings selection
9E
00: Settings 0
01: Settings 1
10: Settings 2
11: Settings 3
State11_6BitMatrix_OUT1
4 Settings selection
00: Settings 0
01: Settings 1
10: Settings 2
11: Settings 3
State11_6BitMatrix_OUT2
4 Settings selection
Datasheet
25-Feb-2021
Revision 3.12
228 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1272
1273
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 0 011: 6Bit_Matrix_OUT2;
→State 0 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1274
1275
1276
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
9F
ASM Input Matrix (Signal Source for State 0 011: 6Bit_Matrix_OUT2;
→State 1 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1277
1278
1279
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 0 011: 6Bit_Matrix_OUT2;
→State 2 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1280
1281
1282
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 0 011: 6Bit_Matrix_OUT2;
→State 3 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1283
A0
1284
1285
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 0 011: 6Bit_Matrix_OUT2;
→State 4 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1286
1287
1288
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 0 011: 6Bit_Matrix_OUT2;
→State 5 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
A1
1289
Datasheet
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© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1290
1291
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 0 011: 6Bit_Matrix_OUT2;
→State 6 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1292
A1
1293
1294
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 0 011: 6Bit_Matrix_OUT2;
→State 7 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1295
Datasheet
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230 of 353
CFR0011-120-00
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1296
1297
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 0 011: 6Bit_Matrix_OUT2;
→State 8 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1298
1299
1300
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
A2
ASM Input Matrix (Signal Source for State 0 011: 6Bit_Matrix_OUT2;
→State 9 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1301
1302
1303
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 0 011: 6Bit_Matrix_OUT2;
→State 10 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1304
1305
1306
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 0 011: 6Bit_Matrix_OUT2;
→State 11 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1307
000: VSS;
A3
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
011: 6Bit_Matrix_OUT2;
100: DM0_0;
101: DM0_1;
110: DM1_0;
ASM Input Matrix (Signal Source for State 1
→State 10 Transition), bit [2]
Note: This bit, along with
registers [1343:1342], select the signal
source for State 1 to State 10 Transition
1308
111: DM1_1
1309
1310
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 1 011: 6Bit_Matrix_OUT2;
→State 11 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1311
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1312
1313
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 1 011: 6Bit_Matrix_OUT2;
→State 0 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1314
1315
1316
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
A4
ASM Input Matrix (Signal Source for State 1 011: 6Bit_Matrix_OUT2;
→State 1 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1317
1318
1319
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 1 011: 6Bit_Matrix_OUT2;
→State 2 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1320
1321
1322
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 1 011: 6Bit_Matrix_OUT2;
→State 3 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1323
A5
1324
1325
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 1 011: 6Bit_Matrix_OUT2;
→State 4 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1326
1327
1328
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 1 011: 6Bit_Matrix_OUT2;
→State 5 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
A6
1329
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1330
1331
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 1 011: 6Bit_Matrix_OUT2;
→State 6 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1332
A6
1333
1334
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 1 011: 6Bit_Matrix_OUT2;
→State 7 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1335
1336
1337
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 1 011: 6Bit_Matrix_OUT2;
→State 8 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1338
1339
1340
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 1 011: 6Bit_Matrix_OUT2;
A7
→State 9 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1341
1342
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
011: 6Bit_Matrix_OUT2;
100: DM0_0;
101: DM0_1;
110: DM1_0;
ASM Input Matrix (Signal Source for State 1
→State 10 Transition), bits [1:0]
Note: These bits, along with register [1308],
select the signal source for State 1 to State
10 Transition
1343
111: DM1_1
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State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1344
1345
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 2 011: 6Bit_Matrix_OUT2;
→State 0 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1346
1347
1348
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
A8
ASM Input Matrix (Signal Source for State 2 011: 6Bit_Matrix_OUT2;
→State 1 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1349
1350
1351
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 2 011: 6Bit_Matrix_OUT2;
→State 2 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
A9
1352
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1353
1354
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 2 011: 6Bit_Matrix_OUT2;
→State 3 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1355
A9
1356
1357
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 2 011: 6Bit_Matrix_OUT2;
→State 4 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1358
1359
1360
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 2 011: 6Bit_Matrix_OUT2;
→State 5 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1361
1362
1363
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 2 011: 6Bit_Matrix_OUT2;
→State 6 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
AA
1364
1365
1366
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 2 011: 6Bit_Matrix_OUT2;
→State 7 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1367
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1368
1369
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 2 011: 6Bit_Matrix_OUT2;
→State 8 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1370
AB
1371
1372
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 2 011: 6Bit_Matrix_OUT2;
→State 9 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1373
1374
1375
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
AB
ASM Input Matrix (Signal Source for State 2 011: 6Bit_Matrix_OUT2;
→State 10 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1376
1377
1378
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 2 011: 6Bit_Matrix_OUT2;
→State 11 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1379
000: VSS;
AC
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
011: 6Bit_Matrix_OUT2;
100: DM0_0;
101: DM0_1;
110: DM1_0;
ASM Input Matrix (Signal Source for State 3
→State 10 Transition), bit [2]
Note: This bit, along with
registers [1415:1414], select the signal
source for State 3 to State 10 Transition
1380
111: DM1_1
1381
1382
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 3 011: 6Bit_Matrix_OUT2;
→State 11 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1383
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1384
1385
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 3 011: 6Bit_Matrix_OUT2;
→State 0 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1386
1387
1388
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
AD
ASM Input Matrix (Signal Source for State 3 011: 6Bit_Matrix_OUT2;
→State 1 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1389
1390
1391
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 3 011: 6Bit_Matrix_OUT2;
→State 2 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
AE
1392
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1393
1394
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 3 011: 6Bit_Matrix_OUT2;
→State 3 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1395
AE
1396
1397
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 3 011: 6Bit_Matrix_OUT2;
→State 4 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1398
1399
1400
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 3 011: 6Bit_Matrix_OUT2;
→State 5 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1401
1402
1403
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 3 011: 6Bit_Matrix_OUT2;
→State 6 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
AF
1404
1405
1406
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 3 011: 6Bit_Matrix_OUT2;
→State 7 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1407
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1408
1409
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 3 011: 6Bit_Matrix_OUT2;
→State 8 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1410
BO
1411
1412
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 3 011: 6Bit_Matrix_OUT2;
→State 9 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1413
1414
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
011: 6Bit_Matrix_OUT2;
100: DM0_0;
101: DM0_1;
110: DM1_0;
ASM Input Matrix (Signal Source for State 3
→State 10 Transition), bits [1:0]
Note:Thesebits, alongwith registers [1380],
select the signal source for State 3 to State
10 Transition
BO
1415
111: DM1_1
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1416
1417
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 4 011: 6Bit_Matrix_OUT2;
→State 0 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1418
1419
1420
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
B1
ASM Input Matrix (Signal Source for State 4 011: 6Bit_Matrix_OUT2;
→State 1 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1421
1422
1423
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 4 011: 6Bit_Matrix_OUT2;
→State 2 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1424
1425
1426
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 4 011: 6Bit_Matrix_OUT2;
→State 3 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1427
B2
1428
1429
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 4 011: 6Bit_Matrix_OUT2;
→State 4 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1430
1431
1432
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 4 011: 6Bit_Matrix_OUT2;
→State 5 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
B3
1433
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1434
1435
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 4 011: 6Bit_Matrix_OUT2;
→State 6 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1436
B3
1437
1438
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 4 011: 6Bit_Matrix_OUT2;
→State 7 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1439
1440
1441
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 4 011: 6Bit_Matrix_OUT2;
→State 8 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1442
1443
1444
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
B4
ASM Input Matrix (Signal Source for State 4 011: 6Bit_Matrix_OUT2;
→State 9 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1445
1446
1447
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 4 011: 6Bit_Matrix_OUT2;
→State 10 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1448
1449
1450
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
B5
ASM Input Matrix (Signal Source for State 4 011: 6Bit_Matrix_OUT2;
→State 11 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1451
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
011: 6Bit_Matrix_OUT2;
100: DM0_0;
101: DM0_1;
110: DM1_0;
ASM Input Matrix (Signal Source for State 5
→State 10 Transition), bit [2]
Note: This bit, along with
registers [1487:1486], select the signal
source for State 5 to State 10 Transition
1452
111: DM1_1
B5
1453
1454
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 5 011: 6Bit_Matrix_OUT2;
→State 11 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1455
1456
1457
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 5 011: 6Bit_Matrix_OUT2;
→State 0 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1458
1459
1460
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
B6
ASM Input Matrix (Signal Source for State 5 011: 6Bit_Matrix_OUT2;
→State 1 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1461
1462
1463
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 5 011: 6Bit_Matrix_OUT2;
→State 2 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1464
1465
1466
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
B7
ASM Input Matrix (Signal Source for State 5 011: 6Bit_Matrix_OUT2;
→State 3 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1467
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1468
1469
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 5 011: 6Bit_Matrix_OUT2;
→State 4 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
B7
1470
1471
1472
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 5 011: 6Bit_Matrix_OUT2;
→State 5 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1473
1474
1475
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 5 011: 6Bit_Matrix_OUT2;
→State 6 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
B8
1476
1477
1478
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 5 011: 6Bit_Matrix_OUT2;
→State 7 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1479
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1480
1481
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 5 011: 6Bit_Matrix_OUT2;
→State 8 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1482
1483
1484
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 5 011: 6Bit_Matrix_OUT2;
B9
→State 9 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1485
1486
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
011: 6Bit_Matrix_OUT2;
100: DM0_0;
101: DM0_1;
110: DM1_0;
ASM Input Matrix (Signal Source for State 5
→State 10 Transition), bits [1:0]
Note: These bits, along with register [1452],
select the signal source for State 5 to State
10 Transition
1487
111: DM1_1
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1488
1489
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 6 011: 6Bit_Matrix_OUT2;
→State 0 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1490
1491
1492
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
BA
ASM Input Matrix (Signal Source for State 6 011: 6Bit_Matrix_OUT2;
→State 1 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1493
1494
1495
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 6 011: 6Bit_Matrix_OUT2;
→State 2 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1496
1497
1498
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 6 011: 6Bit_Matrix_OUT2;
→State 3 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1499
BB
1500
1501
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 6 011: 6Bit_Matrix_OUT2;
→State 4 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1502
1503
1504
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 6 011: 6Bit_Matrix_OUT2;
→State 5 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
BC
1505
Datasheet
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245 of 353
CFR0011-120-00
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1506
1507
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 6 011: 6Bit_Matrix_OUT2;
→State 6 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1508
BC
1509
1510
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 6 011: 6Bit_Matrix_OUT2;
→State 7 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1511
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1512
1513
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 6 011: 6Bit_Matrix_OUT2;
→State 8 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1514
1515
1516
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
BD
ASM Input Matrix (Signal Source for State 6 011: 6Bit_Matrix_OUT2;
→State 9 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1517
1518
1519
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 6 011: 6Bit_Matrix_OUT2;
→State 10 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1520
1521
1522
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 6 011: 6Bit_Matrix_OUT2;
→State 11 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1523
000: VSS;
BE
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
011: 6Bit_Matrix_OUT2;
100: DM0_0;
101: DM0_1;
110: DM1_0;
ASM Input Matrix (Signal Source for State 7
→State 10 Transition), bit [2]
Note: This bit, along with
registers [1559:1558], select the signal
source for State 7 to State 10 Transition
1524
111: DM1_1
1525
1526
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 7 011: 6Bit_Matrix_OUT2;
→State 11 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1527
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1528
1529
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 7 011: 6Bit_Matrix_OUT2;
→State 0 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1530
1531
1532
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
BF
ASM Input Matrix (Signal Source for State 7 011: 6Bit_Matrix_OUT2;
→State 1 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1533
1534
1535
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 7 011: 6Bit_Matrix_OUT2;
→State 2 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1536
1537
1538
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 7 011: 6Bit_Matrix_OUT2;
→State 3 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1539
CO
1540
1541
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 7 011: 6Bit_Matrix_OUT2;
→State 4 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1542
1543
1544
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 7 011: 6Bit_Matrix_OUT2;
→State 5 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
C1
1545
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1546
1547
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 7 011: 6Bit_Matrix_OUT2;
→State 6 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1548
C1
1549
1550
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 7 011: 6Bit_Matrix_OUT2;
→State 7 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1551
1552
1553
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 7 011: 6Bit_Matrix_OUT2;
→State 8 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1554
1555
1556
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 7 011: 6Bit_Matrix_OUT2;
C2
→State 9 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1557
1558
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
011: 6Bit_Matrix_OUT2;
100: DM0_0;
101: DM0_1;
110: DM1_0;
ASM Input Matrix (Signal Source for State 7
→State 10 Transition), bits [1:0]
Note: These bits, along with register [1524],
select the signal source for State 7 to State
10 Transition
1559
111: DM1_1
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1560
1561
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 8 011: 6Bit_Matrix_OUT2;
→State 0 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1562
1563
1564
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
C3
ASM Input Matrix (Signal Source for State 8 011: 6Bit_Matrix_OUT2;
→State 1 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1565
1566
1567
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 8 011: 6Bit_Matrix_OUT2;
→State 2 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
C4
1568
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1569
1570
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 8 011: 6Bit_Matrix_OUT2;
→State 3 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1571
C4
1572
1573
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 8 011: 6Bit_Matrix_OUT2;
→State 4 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1574
1575
1576
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 8 011: 6Bit_Matrix_OUT2;
→State 5 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1577
1578
1579
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 8 011: 6Bit_Matrix_OUT2;
→State 6 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
C5
1580
1581
1582
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 8 011: 6Bit_Matrix_OUT2;
→State 7 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1583
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1584
1585
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 8 011: 6Bit_Matrix_OUT2;
→State 8Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1586
C6
1587
1588
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 8 011: 6Bit_Matrix_OUT2;
→State 9 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1589
1590
1591
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
C6
ASM Input Matrix (Signal Source for State 8 011: 6Bit_Matrix_OUT2;
→State 10 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1592
1593
1594
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 8 011: 6Bit_Matrix_OUT2;
→State 11 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1595
000: VSS;
C7
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
011: 6Bit_Matrix_OUT2;
100: DM0_0;
101: DM0_1;
110: DM1_0;
ASM Input Matrix (Signal Source for State 9
→State 10 Transition), bit [2]
Note: This bit, along with
registers [1631:1630], select the signal
source for State 9 to State 10 Transition
1596
111: DM1_1
1597
1598
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 9 011: 6Bit_Matrix_OUT2;
→State 11 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1599
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1600
1601
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 9 011: 6Bit_Matrix_OUT2;
→State 0 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1602
1603
1604
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
C8
ASM Input Matrix (Signal Source for State 9 011: 6Bit_Matrix_OUT2;
→State 1 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1605
1606
1607
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 9 011: 6Bit_Matrix_OUT2;
→State 2 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
C9
1608
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1609
1610
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 9 011: 6Bit_Matrix_OUT2;
→State 3 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1611
C9
1612
1613
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 9 011: 6Bit_Matrix_OUT2;
→State 4 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1614
1615
1616
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 9 011: 6Bit_Matrix_OUT2;
→State 5 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1617
1618
1619
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 9 011: 6Bit_Matrix_OUT2;
→State 6 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
CA
1620
1621
1622
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 9 011: 6Bit_Matrix_OUT2;
→State 7 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1623
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1624
1625
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 9 011: 6Bit_Matrix_OUT2;
→State 8 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1626
CB
1627
1628
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 9 011: 6Bit_Matrix_OUT2;
→State 9 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1629
1630
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
011: 6Bit_Matrix_OUT2;
100: DM0_0;
101: DM0_1;
110: DM1_0;
ASM Input Matrix (Signal Source for State 9
→State 10 Transition), bits [1:0]
Note: These bits, along with register [1596],
select the signal source for State 9 to State
10 Transition
CB
1631
111: DM1_1
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1632
1633
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASMInputMatrix(SignalSourceforState10 011: 6Bit_Matrix_OUT2;
→State 0 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1634
1635
1636
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
CC
ASMInputMatrix(SignalSourceforState10 011: 6Bit_Matrix_OUT2;
→State 1 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1637
1638
1639
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASMInputMatrix(SignalSourceforState10 011: 6Bit_Matrix_OUT2;
→State 2 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1640
1641
1642
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 011: 6Bit_Matrix_OUT2;
10 →State 3 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1643
CD
1644
1645
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 011: 6Bit_Matrix_OUT2;
10 →State 4 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1646
1647
1648
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 011: 6Bit_Matrix_OUT2;
10 →State 5 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
CE
1649
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1650
1651
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 011: 6Bit_Matrix_OUT2;
10 →State 6 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1652
CE
1653
1654
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 011: 6Bit_Matrix_OUT2;
10 →State 7 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1655
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1656
1657
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 011: 6Bit_Matrix_OUT2;
10 →State 8 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1658
1659
1660
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
CF
ASM Input Matrix (Signal Source for State 011: 6Bit_Matrix_OUT2;
10 →State 9 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1661
1662
1663
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 011: 6Bit_Matrix_OUT2;
10 →State 10 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1664
1665
1666
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 011: 6Bit_Matrix_OUT2;
10 →State 11 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
D0
1667
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
011: 6Bit_Matrix_OUT2;
100: DM0_0;
101: DM0_1;
110: DM1_0;
ASM InputMatrix (SignalSourceforState 11
→State 10 Transition), bit [2]
Note: This bit, along with
registers [1703:1702], select the signal
source for State 11 to State 10 Transition
1668
111: DM1_1
1669
1670
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 011: 6Bit_Matrix_OUT2;
D0
11 →State 11 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1671
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1672
1673
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 011: 6Bit_Matrix_OUT2;
11 →State 0 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1674
1675
1676
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
D1
ASM Input Matrix (Signal Source for State 011: 6Bit_Matrix_OUT2;
11 →State 1 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1677
1678
1679
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 011: 6Bit_Matrix_OUT2;
11 →State 2 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1680
1681
1682
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 011: 6Bit_Matrix_OUT2;
11 →State 3 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1683
D2
1684
1685
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 011: 6Bit_Matrix_OUT2;
11 →State 4 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1686
1687
1688
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 011: 6Bit_Matrix_OUT2;
11 →State 5 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
D3
1689
Datasheet
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Revision 3.12
259 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1690
1691
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 011: 6Bit_Matrix_OUT2;
11 →State 6 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1692
D3
1693
1694
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 011: 6Bit_Matrix_OUT2;
11 →State 7 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1695
1696
1697
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 011: 6Bit_Matrix_OUT2;
11 →State 8Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1698
1699
1700
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
ASM Input Matrix (Signal Source for State 011: 6Bit_Matrix_OUT2;
D4
11 →State 9 Transition)
100: DM0_0;
101: DM0_1;
110: DM1_0;
111: DM1_1
1701
1702
000: VSS;
001: 6Bit_Matrix_OUT0;
010: 6Bit_Matrix_OUT1;
011: 6Bit_Matrix_OUT2;
100: DM0_0;
101: DM0_1;
110: DM1_0;
ASM InputMatrix (SignalSourceforState 11
→State 10 Transition), bits [1:0]
Note: These bits, along with register [1668],
select the signal source for State 11 to State
10 Transition
1703
111: DM1_1
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
DM0_0 Configuration Register 0
IN0 of LUT3
REG_MATRIX_LUT3_IN0_SEL[5:0]
D5
DM0_0 Configuration Register 0
IN1 of LUT3
REG_MATRIX_LUT3_IN1_SEL[5:0]
REG_MATRIX_LUT3_IN2_SEL[5:0]
DM Delay input
D6
D6
DM0_0 Configuration Register 0
IN2 of LUT3
D7
DM0_0 Configuration Register 0
DLY input from matrix
REG_VAL_LUT3[0]
REG_VAL_LUT3[1]
REG_VAL_LUT3[2]
REG_VAL_LUT3[3]
REG_VAL_LUT3[4]
REG_VAL_LUT3[5]
REG_VAL_LUT3[6]
REG_VAL_LUT3[7]
DM0_0 Configuration Register 0
Data of LUT3
D8
Datasheet
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Revision 3.12
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1736
1737
1738
1739
1740
1741
1742
REG_VAL_LUT2[0]
REG_VAL_LUT2[1]
REG_VAL_LUT2[2]
REG_VAL_LUT2[3]
DM0_0 Configuration Register 0
Data of LUT2
Clock source sel[3:0]
0000: 25M;
0001: 25M/4;
0010: 2.048M
0011: 2.048M/8;
0100: 2.048M/64;
0101: 2.048M/512;
0110: 2.048K;
0111: 2.048K/8;
1000: 2.048K/64;
1001: 2.048K/512;
1010: 2.048K/4096
1011: 2.048K/32768;
1100: 2.048K/262144;
1101: CNT_END;
1110: External;
D9
DM0_0 Configuration Register 0
Clock source selection
1743
1111: External
1744
1745
1746
1747
1748
1749
1750
1751
DM0_0 Configuration Register 0
Data of Delay
DA
Data[7:0]
Datasheet
25-Feb-2021
Revision 3.12
262 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1752
00: bypass the initial
01: initial 0
10: initial 1
DM0_0 Configuration Register 0
DLY input initial selection
1753
11: initial 1
1754
1755
1756
0000: Both Edge Delay
0001: Falling Edge Delay
0010: Rising Edge Delay
0011: Both Edge One Shot
0100: Falling Edge One Shot
0101: Rising Edge One Shot
0110: Both Edge Freq Detect
0111: Falling Edge Freq Detect
1000: Rising Edge Freq Detect
1001: Both Edge Detect
1010: Falling Edge Detect
1011: Rising Edge Detect
1100: Both Edge Reset CNT
1101: Falling Edge Reset CNT
1110: Rising Edge Reset CNT
1111: High Level Reset CNT
DM0_0 Configuration Register 0
DLY/CNT Function selection
DB
1757
DM0_0 Configuration Register 0
MUX1 selection for LUT2
0: from LUT3
1: from matrix (DLY IN)
1758
1759
DM0_0 Configuration Register 0
MUX2 selection for DLY input
0: from matrix (DLY IN)
1: from LUT3
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
DM0_0 Configuration Register 1
IN0 of LUT3
REG_MATRIX_LUT3_IN0_SEL[5:0]
REG_MATRIX_LUT3_IN1_SEL[5:0]
DC
DD
DM0_0 Configuration Register 1
IN1 of LUT3
Datasheet
25-Feb-2021
Revision 3.12
263 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
DD
DM0_0 Configuration Register 1
IN2 of LUT3
REG_MATRIX_LUT3_IN2_SEL[5:0]
DE
DM0_0 Configuration Register 1
DLY input from matrix
DM Delay input
REG_VAL_LUT3[0]
REG_VAL_LUT3[1]
REG_VAL_LUT3[2]
REG_VAL_LUT3[3]
REG_VAL_LUT3[4]
REG_VAL_LUT3[5]
REG_VAL_LUT3[6]
REG_VAL_LUT3[7]
REG_VAL_LUT2[0]
REG_VAL_LUT2[1]
REG_VAL_LUT2[2]
REG_VAL_LUT2[3]
DM0_0 Configuration Register 1
Data of LUT3
DF
DM0_0 Configuration Register 1
Data of LUT2
Clock source sel[3:0]
0000: 25M;
0001: 25M/4;
0010: 2.048M
0011: 2.048M/8;
0100: 2.048M/64;
0101: 2.048M/512;
0110: 2.048K;
0111: 2.048K/8;
1000: 2.048K/64;
1001: 2.048K/512;
1010: 2.048K/4096
1011: 2.048K/32768;
1100: 2.048K/262144;
1101: CNT_END;
1110: External;
E0
DM0_0 Configuration Register 1
Clock source selection
1799
1111: External
Datasheet
25-Feb-2021
Revision 3.12
264 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1800
1801
1802
1803
1804
1805
1806
1807
1808
DM0_0 Configuration Register 1
Data of Delay
E1
Data[7:0]
00: bypass the initial
01: initial 0
10: initial 1
DM0_0 Configuration Register 1
DLY input initial selection
1809
11: initial 1
1810
1811
1812
0000: Both Edge Delay
0001: Falling Edge Delay
0010: Rising Edge Delay
0011: Both Edge One Shot
0100: Falling Edge One Shot
0101: Rising Edge One Shot
0110: Both Edge Freq Detect
0111: Falling Edge Freq Detect
1000: Rising Edge Freq Detect
1001: Both Edge Detect
1010: Falling Edge Detect
1011: Rising Edge Detect
1100: Both Edge Reset CNT
1101: Falling Edge Reset CNT
1110: Rising Edge Reset CNT
1111: High Level Reset CNT
DM0_0 Configuration Register 1
DLY/CNT Function selection
E2
1813
DM0_0 Configuration Register 1
MUX1 selection for LUT2
0: from LUT3
1: from matrix (DLY IN)
1814
1815
DM0_0 Configuration Register 1
MUX2 selection for DLY input
0: from matrix (DLY IN)
1: from LUT3
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
DM0_0 Configuration Register 2
IN0 of LUT3
REG_MATRIX_LUT3_IN0_SEL[5:0]
REG_MATRIX_LUT3_IN1_SEL[5:0]
E3
E4
DM0_0 Configuration Register 2
IN1 of LUT3
Datasheet
25-Feb-2021
Revision 3.12
265 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
E4
DM0_0 Configuration Register 2
IN2 of LUT3
REG_MATRIX_LUT3_IN2_SEL[5:0]
E5
DM0_0 Configuration Register 2
DLY input from matrix
DM Delay input
REG_VAL_LUT3[0]
REG_VAL_LUT3[1]
REG_VAL_LUT3[2]
REG_VAL_LUT3[3]
REG_VAL_LUT3[4]
REG_VAL_LUT3[5]
REG_VAL_LUT3[6]
REG_VAL_LUT3[7]
REG_VAL_LUT2[0]
REG_VAL_LUT2[1]
REG_VAL_LUT2[2]
REG_VAL_LUT2[3]
DM0_0 Configuration Register 2
Data of LUT3
E6
DM0_0 Configuration Register 2
Data of LUT2
Clock source sel[3:0]
0000: 25M;
0001: 25M/4;
0010: 2.048M
0011: 2.048M/8;
0100: 2.048M/64;
0101: 2.048M/512;
0110: 2.048K;
0111: 2.048K/8;
1000: 2.048K/64;
1001: 2.048K/512;
1010: 2.048K/4096
1011: 2.048K/32768;
1100: 2.048K/262144;
1101: CNT_END;
1110: External;
E7
DM0_0 Configuration Register 2
Clock source selection
1855
1111: External
Datasheet
25-Feb-2021
Revision 3.12
266 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1856
1857
1858
1859
1860
1861
1862
1863
1864
DM0_0 Configuration Register 2
Data of Delay
E8
Data[7:0]
00: bypass the initial
01: initial 0
10: initial 1
DM0_0 Configuration Register 2
DLY input initial selection
1865
11: initial 1
1866
1867
1868
0000: Both Edge Delay
0001: Falling Edge Delay
0010: Rising Edge Delay
0011: Both Edge One Shot
0100: Falling Edge One Shot
0101: Rising Edge One Shot
0110: Both Edge Freq Detect
0111: Falling Edge Freq Detect
1000: Rising Edge Freq Detect
1001: Both Edge Detect
1010: Falling Edge Detect
1011: Rising Edge Detect
1100: Both Edge Reset CNT
1101: Falling Edge Reset CNT
1110: Rising Edge Reset CNT
1111: High Level Reset CNT
DM0_0 Configuration Register 2
DLY/CNT Function selection
E9
1869
DM0_0 Configuration Register 2
MUX1 selection for LUT2
0: from LUT3
1: from matrix (DLY IN)
1870
1871
DM0_0 Configuration Register 2
MUX2 selection for DLY input
0: from matrix (DLY IN)
1: from LUT3
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
DM0_0 Configuration Register 3
IN0 of LUT3
REG_MATRIX_LUT3_IN0_SEL[5:0]
REG_MATRIX_LUT3_IN1_SEL[5:0]
EA
EB
DM0_0 Configuration Register 3
IN1 of LUT3
Datasheet
25-Feb-2021
Revision 3.12
267 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
EB
DM0_0 Configuration Register 3
IN2 of LUT3
REG_MATRIX_LUT3_IN2_SEL[5:0]
EC
DM0_0 Configuration Register 3
DLY input from matrix
DM Delay input
REG_VAL_LUT3[0]
REG_VAL_LUT3[1]
REG_VAL_LUT3[2]
REG_VAL_LUT3[3]
REG_VAL_LUT3[4]
REG_VAL_LUT3[5]
REG_VAL_LUT3[6]
REG_VAL_LUT3[7]
REG_VAL_LUT2[0]
REG_VAL_LUT2[1]
REG_VAL_LUT2[2]
REG_VAL_LUT2[3]
DM0_0 Configuration Register 3
Data of LUT3
ED
DM0_0 Configuration Register 3
Data of LUT2
Clock source sel[3:0]
0000: 25M;
0001: 25M/4;
0010: 2.048M
0011: 2.048M/8;
0100: 2.048M/64;
0101: 2.048M/512;
0110: 2.048K;
0111: 2.048K/8;
1000: 2.048K/64;
1001: 2.048K/512;
1010: 2.048K/4096
1011: 2.048K/32768;
1100: 2.048K/262144;
1101: CNT_END;
1110: External;
EE
DM0_0 Configuration Register 3
Clock source selection
1911
1111: External
Datasheet
25-Feb-2021
Revision 3.12
268 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1912
1913
1914
1915
1916
1917
1918
1919
1920
DM0_0 Configuration Register 3
Data of Delay
EF
Data[7:0]
00: bypass the initial
01: initial 0
10: initial 1
DM0_0 Configuration Register 3
DLY input initial selection
1921
11: initial 1
1922
1923
1924
0000: Both Edge Delay
0001: Falling Edge Delay
0010: Rising Edge Delay
0011: Both Edge One Shot
0100: Falling Edge One Shot
0101: Rising Edge One Shot
0110: Both Edge Freq Detect
0111: Falling Edge Freq Detect
1000: Rising Edge Freq Detect
1001: Both Edge Detect
1010: Falling Edge Detect
1011: Rising Edge Detect
1100: Both Edge Reset CNT
1101: Falling Edge Reset CNT
1110: Rising Edge Reset CNT
1111: High Level Reset CNT
DM0_0 Configuration Register 3
DLY/CNT Function selection
F0
1925
DM0_0 Configuration Register 3
MUX1 selection for LUT2
0: from LUT3
1: from matrix (DLY IN)
1926
1927
DM0_0 Configuration Register 3
MUX2 selection for DLY input
0: from matrix (DLY IN)
1: from LUT3
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
DM0_0 Configuration Register 4
IN0 of LUT3
REG_MATRIX_LUT3_IN0_SEL[5:0]
REG_MATRIX_LUT3_IN1_SEL[5:0]
F1
F2
DM0_0 Configuration Register 4
IN1 of LUT3
Datasheet
25-Feb-2021
Revision 3.12
269 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
F2
DM0_0 Configuration Register 4
IN2 of LUT3
REG_MATRIX_LUT3_IN2_SEL[5:0]
F3
DM0_0 Configuration Register 4
DLY input from matrix
DM Delay input
REG_VAL_LUT3[0]
REG_VAL_LUT3[1]
REG_VAL_LUT3[2]
REG_VAL_LUT3[3]
REG_VAL_LUT3[4]
REG_VAL_LUT3[5]
REG_VAL_LUT3[6]
REG_VAL_LUT3[7]
REG_VAL_LUT2[0]
REG_VAL_LUT2[1]
REG_VAL_LUT2[2]
REG_VAL_LUT2[3]
DM0_0 Configuration Register 4
Data of LUT3
F4
DM0_0 Configuration Register 4
Data of LUT2
Clock source sel[3:0]
0000: 25M;
0001: 25M/4;
0010: 2.048M
0011: 2.048M/8;
0100: 2.048M/64;
0101: 2.048M/512;
0110: 2.048K;
0111: 2.048K/8;
1000: 2.048K/64;
1001: 2.048K/512;
1010: 2.048K/4096
1011: 2.048K/32768;
1100: 2.048K/262144;
1101: CNT_END;
1110: External;
F5
DM0_0 Configuration Register 4
Clock source selection
1967
1111: External
Datasheet
25-Feb-2021
Revision 3.12
270 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1968
1969
1970
1971
1972
1973
1974
1975
1976
DM0_0 Configuration Register 4
Data of Delay
F6
Data[7:0]
00: bypass the initial
01: initial 0
10: initial 1
DM0_0 Configuration Register 4
DLY input initial selection
1977
11: initial 1
1978
1979
1980
0000: Both Edge Delay
0001: Falling Edge Delay
0010: Rising Edge Delay
0011: Both Edge One Shot
0100: Falling Edge One Shot
0101: Rising Edge One Shot
0110: Both Edge Freq Detect
0111: Falling Edge Freq Detect
1000: Rising Edge Freq Detect
1001: Both Edge Detect
1010: Falling Edge Detect
1011: Rising Edge Detect
1100: Both Edge Reset CNT
1101: Falling Edge Reset CNT
1110: Rising Edge Reset CNT
1111: High Level Reset CNT
DM0_0 Configuration Register 4
DLY/CNT Function selection
F7
1981
DM0_0 Configuration Register 4
MUX1 selection for LUT2
0: from LUT3
1: from matrix (DLY IN)
1982
1983
DM0_0 Configuration Register 4
MUX2 selection for DLY input
0: from matrix (DLY IN)
1: from LUT3
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
DM0_0 Configuration Register 5
IN0 of LUT3
REG_MATRIX_LUT3_IN0_SEL[5:0]
REG_MATRIX_LUT3_IN1_SEL[5:0]
F8
F9
DM0_0 Configuration Register 5
IN1 of LUT3
Datasheet
25-Feb-2021
Revision 3.12
271 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
F9
DM0_0 Configuration Register 5
IN2 of LUT3
REG_MATRIX_LUT3_IN2_SEL[5:0]
FA
DM0_0 Configuration Register 5
DLY input from matrix
DM Delay input
REG_VAL_LUT3[0]
REG_VAL_LUT3[1]
REG_VAL_LUT3[2]
REG_VAL_LUT3[3]
REG_VAL_LUT3[4]
REG_VAL_LUT3[5]
REG_VAL_LUT3[6]
REG_VAL_LUT3[7]
REG_VAL_LUT2[0]
REG_VAL_LUT2[1]
REG_VAL_LUT2[2]
REG_VAL_LUT2[3]
DM0_0 Configuration Register 5
Data of LUT3
FB
DM0_0 Configuration Register 5
Data of LUT2
Clock source sel[3:0]
0000: 25M;
0001: 25M/4;
0010: 2.048M
0011: 2.048M/8;
0100: 2.048M/64;
0101: 2.048M/512;
0110: 2.048K;
0111: 2.048K/8;
1000: 2.048K/64;
1001: 2.048K/512;
1010: 2.048K/4096
1011: 2.048K/32768;
1100: 2.048K/262144;
1101: CNT_END;
1110: External;
FC
DM0_0 Configuration Register 5
Clock source selection
2023
1111: External
Datasheet
25-Feb-2021
Revision 3.12
272 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
2024
2025
2026
2027
2028
2029
2030
2031
2032
DM0_0 Configuration Register 5
Data of Delay
FD
Data[7:0]
00: bypass the initial
01: initial 0
10: initial 1
DM0_0 Configuration Register 5
DLY input initial selection
2033
11: initial 1
2034
2035
2036
0000: Both Edge Delay
0001: Falling Edge Delay
0010: Rising Edge Delay
0011: Both Edge One Shot
0100: Falling Edge One Shot
0101: Rising Edge One Shot
0110: Both Edge Freq Detect
0111: Falling Edge Freq Detect
1000: Rising Edge Freq Detect
1001: Both Edge Detect
1010: Falling Edge Detect
1011: Rising Edge Detect
1100: Both Edge Reset CNT
1101: Falling Edge Reset CNT
1110: Rising Edge Reset CNT
1111: High Level Reset CNT
DM0_0 Configuration Register 5
DLY/CNT Function selection
FE
2037
DM0_0 Configuration Register 5
MUX1 selection for LUT2
0: from LUT3
1: from matrix (DLY IN)
2038
2039
DM0_0 Configuration Register 5
MUX2 selection for DLY input
0: from matrix (DLY IN)
1: from LUT3
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
FF
Reserved
DM0_1 Configuration Register 0
IN0 of LUT3
100
REG_MATRIX_LUT3_IN0_SEL[5:0]
Datasheet
25-Feb-2021
Revision 3.12
273 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
100
DM0_1 Configuration Register 0
IN1 of LUT3
REG_MATRIX_LUT3_IN1_SEL[5:0]
101
DM0_1 Configuration Register 0
IN2 of LUT3
REG_MATRIX_LUT3_IN2_SEL[5:0]
102
DM0_1 Configuration Register 0
DLY input from matrix
DM Delay input
REG_VAL_LUT3[0]
REG_VAL_LUT3[1]
REG_VAL_LUT3[2]
REG_VAL_LUT3[3]
REG_VAL_LUT3[4]
REG_VAL_LUT3[5]
REG_VAL_LUT3[6]
REG_VAL_LUT3[7]
REG_VAL_LUT2[0]
REG_VAL_LUT2[1]
REG_VAL_LUT2[2]
REG_VAL_LUT2[3]
DM0_1 Configuration Register 0
Data of LUT3
103
104
DM0_1 Configuration Register 0
Data of LUT2
Datasheet
25-Feb-2021
Revision 3.12
274 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
2084
2085
2086
Clock source sel[3:0]
0000: 25M;
0001: 25M/4;
0010: 2.048M
0011: 2.048M/8;
0100: 2.048M/64;
0101: 2.048M/512;
0110: 2.048K;
0111: 2.048K/8;
1000: 2.048K/64;
1001: 2.048K/512;
1010: 2.048K/4096
1011: 2.048K/32768;
1100: 2.048K/262144;
1101: CNT_END;
1110: External;
DM0_1 Configuration Register 0
Clock source selection
104
2087
1111: External
2088
2089
2090
2091
2092
2093
2094
2095
2096
DM0_1 Configuration Register 0
Data of Delay
105
Data[7:0]
00: bypass the initial
01: initial 0
10: initial 1
DM0_1 Configuration Register 0
DLY input initial selection
2097
11: initial 1
2098
2099
2100
0000: Both Edge Delay
0001: Falling Edge Delay
0010: Rising Edge Delay
0011: Both Edge One Shot
0100: Falling Edge One Shot
0101: Rising Edge One Shot
0110: Both Edge Freq Detect
0111: Falling Edge Freq Detect
1000: Rising Edge Freq Detect
1001: Both Edge Detect
1010: Falling Edge Detect
1011: Rising Edge Detect
1100: Both Edge Reset CNT
1101: Falling Edge Reset CNT
1110: Rising Edge Reset CNT
1111: High Level Reset CNT
DM0_1 Configuration Register 0
DLY/CNT Function selection
106
2101
DM0_1 Configuration Register 0
MUX1 selection for LUT2
0: from LUT3
1: from matrix (DLY IN)
2102
2103
DM0_1 Configuration Register 0
MUX2 selection for DLY input
0: from matrix (DLY IN)
1: from LUT3
Datasheet
25-Feb-2021
Revision 3.12
275 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
DM0_1 Configuration Register 1
IN0 of LUT3
REG_MATRIX_LUT3_IN0_SEL[5:0]
107
DM0_1 Configuration Register 1
IN1 of LUT3
REG_MATRIX_LUT3_IN1_SEL[5:0]
REG_MATRIX_LUT3_IN2_SEL[5:0]
DM Delay input
108
DM0_1 Configuration Register 1
IN2 of LUT3
109
DM0_1 Configuration Register 1
DLY input from matrix
REG_VAL_LUT3[0]
REG_VAL_LUT3[1]
REG_VAL_LUT3[2]
REG_VAL_LUT3[3]
REG_VAL_LUT3[4]
REG_VAL_LUT3[5]
REG_VAL_LUT3[6]
REG_VAL_LUT3[7]
REG_VAL_LUT2[0]
REG_VAL_LUT2[1]
REG_VAL_LUT2[2]
REG_VAL_LUT2[3]
DM0_1 Configuration Register 1
Data of LUT3
10A
10B
DM0_1 Configuration Register 1
Data of LUT2
Datasheet
25-Feb-2021
Revision 3.12
276 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
2140
2141
2142
Clock source sel[3:0]
0000: 25M;
0001: 25M/4;
0010: 2.048M
0011: 2.048M/8;
0100: 2.048M/64;
0101: 2.048M/512;
0110: 2.048K;
0111: 2.048K/8;
1000: 2.048K/64;
1001: 2.048K/512;
1010: 2.048K/4096
1011: 2.048K/32768;
1100: 2.048K/262144;
1101: CNT_END;
1110: External;
DM0_1 Configuration Register 1
Clock source selection
10B
2143
1111: External
2144
2145
2146
2147
2148
2149
2150
2151
2152
DM0_1 Configuration Register 1
Data of Delay
10C
Data[7:0]
00: bypass the initial
01: initial 0
10: initial 1
DM0_1 Configuration Register 1
DLY input initial selection
2153
11: initial 1
2154
2155
2156
0000: Both Edge Delay
0001: Falling Edge Delay
0010: Rising Edge Delay
0011: Both Edge One Shot
0100: Falling Edge One Shot
0101: Rising Edge One Shot
0110: Both Edge Freq Detect
0111: Falling Edge Freq Detect
1000: Rising Edge Freq Detect
1001: Both Edge Detect
1010: Falling Edge Detect
1011: Rising Edge Detect
1100: Both Edge Reset CNT
1101: Falling Edge Reset CNT
1110: Rising Edge Reset CNT
1111: High Level Reset CNT
DM0_1 Configuration Register 1
DLY/CNT Function selection
10D
2157
DM0_1 Configuration Register 1
MUX1 selection for LUT2
0: from LUT3
1: from matrix (DLY IN)
2158
2159
DM0_1 Configuration Register 1
MUX2 selection for DLY input
0: from matrix (DLY IN)
1: from LUT3
Datasheet
25-Feb-2021
Revision 3.12
277 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
DM0_1 Configuration Register 2
IN0 of LUT3
REG_MATRIX_LUT3_IN0_SEL[5:0]
10E
DM0_1 Configuration Register 2
IN1 of LUT3
REG_MATRIX_LUT3_IN1_SEL[5:0]
REG_MATRIX_LUT3_IN2_SEL[5:0]
DM Delay input
10F
DM0_1 Configuration Register 2
IN2 of LUT3
110
DM0_1 Configuration Register 2
DLY input from matrix
REG_VAL_LUT3[0]
REG_VAL_LUT3[1]
REG_VAL_LUT3[2]
REG_VAL_LUT3[3]
REG_VAL_LUT3[4]
REG_VAL_LUT3[5]
REG_VAL_LUT3[6]
REG_VAL_LUT3[7]
REG_VAL_LUT2[0]
REG_VAL_LUT2[1]
REG_VAL_LUT2[2]
REG_VAL_LUT2[3]
DM0_1 Configuration Register 2
Data of LUT3
111
112
DM0_1 Configuration Register 2
Data of LUT2
Datasheet
25-Feb-2021
Revision 3.12
278 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
2196
2197
2198
Clock source sel[3:0]
0000: 25M;
0001: 25M/4;
0010: 2.048M
0011: 2.048M/8;
0100: 2.048M/64;
0101: 2.048M/512;
0110: 2.048K;
0111: 2.048K/8;
1000: 2.048K/64;
1001: 2.048K/512;
1010: 2.048K/4096
1011: 2.048K/32768;
1100: 2.048K/262144;
1101: CNT_END;
1110: External;
DM0_1 Configuration Register 2
Clock source selection
112
2199
1111: External
2200
2201
2202
2203
2204
2205
2206
2207
2208
DM0_1 Configuration Register 2
Data of Delay
113
Data[7:0]
00: bypass the initial
01: initial 0
10: initial 1
DM0_1 Configuration Register 2
DLY input initial selection
2209
11: initial 1
2210
2211
2212
0000: Both Edge Delay
0001: Falling Edge Delay
0010: Rising Edge Delay
0011: Both Edge One Shot
0100: Falling Edge One Shot
0101: Rising Edge One Shot
0110: Both Edge Freq Detect
0111: Falling Edge Freq Detect
1000: Rising Edge Freq Detect
1001: Both Edge Detect
1010: Falling Edge Detect
1011: Rising Edge Detect
1100: Both Edge Reset CNT
1101: Falling Edge Reset CNT
1110: Rising Edge Reset CNT
1111: High Level Reset CNT
DM0_1 Configuration Register 2
DLY/CNT Function selection
114
2213
DM0_1 Configuration Register 2
MUX1 selection for LUT2
0: from LUT3
1: from matrix (DLY IN)
2214
2215
DM0_1 Configuration Register 2
MUX2 selection for DLY input
0: from matrix (DLY IN)
1: from LUT3
Datasheet
25-Feb-2021
Revision 3.12
279 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
DM0_1 Configuration Register 3
IN0 of LUT3
REG_MATRIX_LUT3_IN0_SEL[5:0]
115
DM0_1 Configuration Register 3
IN1 of LUT3
REG_MATRIX_LUT3_IN1_SEL[5:0]
REG_MATRIX_LUT3_IN2_SEL[5:0]
DM Delay input
116
DM0_1 Configuration Register 3
IN2 of LUT3
117
DM0_1 Configuration Register 3
DLY input from matrix
REG_VAL_LUT3[0]
REG_VAL_LUT3[1]
REG_VAL_LUT3[2]
REG_VAL_LUT3[3]
REG_VAL_LUT3[4]
REG_VAL_LUT3[5]
REG_VAL_LUT3[6]
REG_VAL_LUT3[7]
REG_VAL_LUT2[0]
REG_VAL_LUT2[1]
REG_VAL_LUT2[2]
REG_VAL_LUT2[3]
DM0_1 Configuration Register 3
Data of LUT3
118
119
DM0_1 Configuration Register 3
Data of LUT2
Datasheet
25-Feb-2021
Revision 3.12
280 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
2252
2253
2254
Clock source sel[3:0]
0000: 25M;
0001: 25M/4;
0010: 2.048M
0011: 2.048M/8;
0100: 2.048M/64;
0101: 2.048M/512;
0110: 2.048K;
0111: 2.048K/8;
1000: 2.048K/64;
1001: 2.048K/512;
1010: 2.048K/4096
1011: 2.048K/32768;
1100: 2.048K/262144;
1101: CNT_END;
1110: External;
DM0_1 Configuration Register 3
Clock source selection
119
2255
1111: External
2256
2257
2258
2259
2260
2261
2262
2263
2264
DM0_1 Configuration Register 3
Data of Delay
11A
Data[7:0]
00: bypass the initial
01: initial 0
10: initial 1
DM0_1 Configuration Register 3
DLY input initial selection
2265
11: initial 1
2266
2267
2268
0000: Both Edge Delay
0001: Falling Edge Delay
0010: Rising Edge Delay
0011: Both Edge One Shot
0100: Falling Edge One Shot
0101: Rising Edge One Shot
0110: Both Edge Freq Detect
0111: Falling Edge Freq Detect
1000: Rising Edge Freq Detect
1001: Both Edge Detect
1010: Falling Edge Detect
1011: Rising Edge Detect
1100: Both Edge Reset CNT
1101: Falling Edge Reset CNT
1110: Rising Edge Reset CNT
1111: High Level Reset CNT
DM0_1 Configuration Register 3
DLY/CNT Function selection
11B
2269
DM0_1 Configuration Register 3
MUX1 selection for LUT2
0: from LUT3
1: from matrix (DLY IN)
2270
2271
DM0_1 Configuration Register 3
MUX2 selection for DLY input
0: from matrix (DLY IN)
1: from LUT3
Datasheet
25-Feb-2021
Revision 3.12
281 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
DM0_1 Configuration Register 4
IN0 of LUT3
REG_MATRIX_LUT3_IN0_SEL[5:0]
11C
DM0_1 Configuration Register 4
IN1 of LUT3
REG_MATRIX_LUT3_IN1_SEL[5:0]
REG_MATRIX_LUT3_IN2_SEL[5:0]
DM Delay input
11D
DM0_1 Configuration Register 4
IN2 of LUT3
11E
DM0_1 Configuration Register 4
DLY input from matrix
REG_VAL_LUT3[0]
REG_VAL_LUT3[1]
REG_VAL_LUT3[2]
REG_VAL_LUT3[3]
REG_VAL_LUT3[4]
REG_VAL_LUT3[5]
REG_VAL_LUT3[6]
REG_VAL_LUT3[7]
REG_VAL_LUT2[0]
REG_VAL_LUT2[1]
REG_VAL_LUT2[2]
REG_VAL_LUT2[3]
DM0_1 Configuration Register 4
Data of LUT3
11F
120
DM0_1 Configuration Register 4
Data of LUT2
Datasheet
25-Feb-2021
Revision 3.12
282 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
2308
2309
2310
Clock source sel[3:0]
0000: 25M;
0001: 25M/4;
0010: 2.048M
0011: 2.048M/8;
0100: 2.048M/64;
0101: 2.048M/512;
0110: 2.048K;
0111: 2.048K/8;
1000: 2.048K/64;
1001: 2.048K/512;
1010: 2.048K/4096
1011: 2.048K/32768;
1100: 2.048K/262144;
1101: CNT_END;
1110: External;
DM0_1 Configuration Register 4
Clock source selection
120
2311
1111: External
2312
2313
2314
2315
2316
2317
2318
2319
2320
DM0_1 Configuration Register 4
Data of Delay
121
Data[7:0]
00: bypass the initial
01: initial 0
10: initial 1
DM0_1 Configuration Register 4
DLY input initial selection
2321
11: initial 1
2322
2323
2324
0000: Both Edge Delay
0001: Falling Edge Delay
0010: Rising Edge Delay
0011: Both Edge One Shot
0100: Falling Edge One Shot
0101: Rising Edge One Shot
0110: Both Edge Freq Detect
0111: Falling Edge Freq Detect
1000: Rising Edge Freq Detect
1001: Both Edge Detect
1010: Falling Edge Detect
1011: Rising Edge Detect
1100: Both Edge Reset CNT
1101: Falling Edge Reset CNT
1110: Rising Edge Reset CNT
1111: High Level Reset CNT
DM0_1 Configuration Register 4
DLY/CNT Function selection
122
2325
DM0_1 Configuration Register 4
MUX1 selection for LUT2
0: from LUT3
1: from matrix (DLY IN)
2326
2327
DM0_1 Configuration Register 4
MUX2 selection for DLY input
0: from matrix (DLY IN)
1: from LUT3
Datasheet
25-Feb-2021
Revision 3.12
283 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
DM0_1 Configuration Register 5
IN0 of LUT3
REG_MATRIX_LUT3_IN0_SEL[5:0]
123
DM0_1 Configuration Register 5
IN1 of LUT3
REG_MATRIX_LUT3_IN1_SEL[5:0]
REG_MATRIX_LUT3_IN2_SEL[5:0]
DM Delay input
124
125
126
DM0_1 Configuration Register 5
IN2 of LUT3
DM0_1 Configuration Register 5
DLY input from matrix
REG_VAL_LUT3[0]
REG_VAL_LUT3[1]
REG_VAL_LUT3[2]
REG_VAL_LUT3[3]
REG_VAL_LUT3[4]
REG_VAL_LUT3[5]
REG_VAL_LUT3[6]
REG_VAL_LUT3[7]
DM0_1 Configuration Register 5
Data of LUT3
Datasheet
25-Feb-2021
Revision 3.12
284 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
2360
2361
2362
2363
2364
2365
2366
REG_VAL_LUT2[0]
REG_VAL_LUT2[1]
REG_VAL_LUT2[2]
REG_VAL_LUT2[3]
DM0_1 Configuration Register 5
Data of LUT2
Clock source sel[3:0]
0000: 25M;
0001: 25M/4;
0010: 2.048M
0011: 2.048M/8;
0100: 2.048M/64;
0101: 2.048M/512;
0110: 2.048K;
0111: 2.048K/8;
1000: 2.048K/64;
1001: 2.048K/512;
1010: 2.048K/4096
1011: 2.048K/32768;
1100: 2.048K/262144;
1101: CNT_END;
1110: External;
127
DM0_1 Configuration Register 5
Clock source selection
2367
1111: External
2368
2369
2370
2371
2372
2373
2374
2375
2376
DM0_1 Configuration Register 5
Data of Delay
128
Data[7:0]
00: bypass the initial
01: initial 0
10: initial 1
DM0_1 Configuration Register 5
DLY input initial selection
2377
11: initial 1
2378
2379
2380
0000: Both Edge Delay
0001: Falling Edge Delay
0010: Rising Edge Delay
0011: Both Edge One Shot
0100: Falling Edge One Shot
0101: Rising Edge One Shot
0110: Both Edge Freq Detect
0111: Falling Edge Freq Detect
1000: Rising Edge Freq Detect
1001: Both Edge Detect
129
DM0_1 Configuration Register 5
DLY/CNT Function selection
2381
2382
1010: Falling Edge Detect
1011: Rising Edge Detect
1100: Both Edge Reset CNT
1101: Falling Edge Reset CNT
1110: Rising Edge Reset CNT
1111: High Level Reset CNT
DM0_1 Configuration Register 5
MUX1 selection for LUT2
0: from LUT3
1: from matrix (DLY IN)
Datasheet
25-Feb-2021
Revision 3.12
285 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
DM0_1 Configuration Register 5
MUX2 selection for DLY input
0: from matrix (DLY IN)
1: from LUT3
129
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
DM1_0 Configuration Register 0
IN0 of LUT3
REG_MATRIX_LUT3_IN0_SEL[5:0]
REG_MATRIX_LUT3_IN1_SEL[5:0]
REG_MATRIX_LUT3_IN2_SEL[5:0]
DM Delay input
12A
12B
12C
DM1_0 Configuration Register 0
IN1 of LUT3
DM1_0 Configuration Register 0
IN2 of LUT3
DM1_0 Configuration Register 0
DLY input from matrix
REG_VAL_LUT3[0]
REG_VAL_LUT3[1]
REG_VAL_LUT3[2]
REG_VAL_LUT3[3]
REG_VAL_LUT3[4]
REG_VAL_LUT3[5]
REG_VAL_LUT3[6]
REG_VAL_LUT3[7]
REG_VAL_LUT2[0]
REG_VAL_LUT2[1]
REG_VAL_LUT2[2]
REG_VAL_LUT2[3]
DM1_0 Configuration Register 0
Data of LUT3
12D
12E
DM1_0 Configuration Register 0
Data of LUT2
Datasheet
25-Feb-2021
Revision 3.12
286 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
2420
2421
2422
Clock source sel[3:0]
0000: 25M;
0001: 25M/4;
0010: 2.048M
0011: 2.048M/8;
0100: 2.048M/64;
0101: 2.048M/512;
0110: 2.048K;
0111: 2.048K/8;
1000: 2.048K/64;
1001: 2.048K/512;
1010: 2.048K/4096
1011: 2.048K/32768;
1100: 2.048K/262144;
1101: CNT_END;
1110: External;
DM1_0 Configuration Register 0
Clock source selection
12E
2423
1111: External
2424
2425
2426
2427
2428
2429
2430
2431
2432
DM1_0 Configuration Register 0
Data of Delay
12F
Data[7:0]
00: bypass the initial
01: initial 0
10: initial 1
DM1_0 Configuration Register 0
DLY input initial selection
2433
11: initial 1
2434
2435
2436
0000: Both Edge Delay
0001: Falling Edge Delay
0010: Rising Edge Delay
0011: Both Edge One Shot
0100: Falling Edge One Shot
0101: Rising Edge One Shot
0110: Both Edge Freq Detect
0111: Falling Edge Freq Detect
1000: Rising Edge Freq Detect
1001: Both Edge Detect
1010: Falling Edge Detect
1011: Rising Edge Detect
1100: Both Edge Reset CNT
1101: Falling Edge Reset CNT
1110: Rising Edge Reset CNT
1111: High Level Reset CNT
DM1_0 Configuration Register 0
DLY/CNT Function selection
130
2437
DM1_0 Configuration Register 0
MUX1 selection for LUT2
0: from LUT3
1: from matrix (DLY IN)
2438
2439
DM1_0 Configuration Register 0
MUX2 selection for DLY input
0: from matrix (DLY IN)
1: from LUT3
Datasheet
25-Feb-2021
Revision 3.12
287 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
DM1_0 Configuration Register 1
IN0 of LUT3
REG_MATRIX_LUT3_IN0_SEL[5:0]
131
DM1_0 Configuration Register 1
IN1 of LUT3
REG_MATRIX_LUT3_IN1_SEL[5:0]
REG_MATRIX_LUT3_IN2_SEL[5:0]
DM Delay input
132
DM1_0 Configuration Register 1
IN2 of LUT3
133
DM1_0 Configuration Register 1
DLY input from matrix
REG_VAL_LUT3[0]
REG_VAL_LUT3[1]
REG_VAL_LUT3[2]
REG_VAL_LUT3[3]
REG_VAL_LUT3[4]
REG_VAL_LUT3[5]
REG_VAL_LUT3[6]
REG_VAL_LUT3[7]
REG_VAL_LUT2[0]
REG_VAL_LUT2[1]
REG_VAL_LUT2[2]
REG_VAL_LUT2[3]
DM1_0 Configuration Register 1
Data of LUT3
134
135
DM1_0 Configuration Register 1
Data of LUT2
Datasheet
25-Feb-2021
Revision 3.12
288 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
2476
2477
2478
Clock source sel[3:0]
0000: 25M;
0001: 25M/4;
0010: 2.048M
0011: 2.048M/8;
0100: 2.048M/64;
0101: 2.048M/512;
0110: 2.048K;
0111: 2.048K/8;
1000: 2.048K/64;
1001: 2.048K/512;
1010: 2.048K/4096
1011: 2.048K/32768;
1100: 2.048K/262144;
1101: CNT_END;
1110: External;
DM1_0 Configuration Register 1
Clock source selection
135
2479
1111: External
2480
2481
2482
2483
2484
2485
2486
2487
2488
DM1_0 Configuration Register 1
Data of Delay
136
Data[7:0]
00: bypass the initial
01: initial 0
10: initial 1
DM1_0 Configuration Register 1
DLY input initial selection
2489
11: initial 1
2490
2491
2492
0000: Both Edge Delay
0001: Falling Edge Delay
0010: Rising Edge Delay
0011: Both Edge One Shot
0100: Falling Edge One Shot
0101: Rising Edge One Shot
0110: Both Edge Freq Detect
0111: Falling Edge Freq Detect
1000: Rising Edge Freq Detect
1001: Both Edge Detect
1010: Falling Edge Detect
1011: Rising Edge Detect
1100: Both Edge Reset CNT
1101: Falling Edge Reset CNT
1110: Rising Edge Reset CNT
1111: High Level Reset CNT
DM1_0 Configuration Register 1
DLY/CNT Function selection
137
2493
DM1_0 Configuration Register 1
MUX1 selection for LUT2
0: from LUT3
1: from matrix (DLY IN)
2494
2495
DM1_0 Configuration Register 1
MUX2 selection for DLY input
0: from matrix (DLY IN)
1: from LUT3
Datasheet
25-Feb-2021
Revision 3.12
289 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
DM1_0 Configuration Register 2
IN0 of LUT3
REG_MATRIX_LUT3_IN0_SEL[5:0]
138
DM1_0 Configuration Register 2
IN1 of LUT3
REG_MATRIX_LUT3_IN1_SEL[5:0]
REG_MATRIX_LUT3_IN2_SEL[5:0]
DM Delay input
139
DM1_0 Configuration Register 2
IN2 of LUT3
13A
DM1_0 Configuration Register 2
DLY input from matrix
REG_VAL_LUT3[0]
REG_VAL_LUT3[1]
REG_VAL_LUT3[2]
REG_VAL_LUT3[3]
REG_VAL_LUT3[4]
REG_VAL_LUT3[5]
REG_VAL_LUT3[6]
REG_VAL_LUT3[7]
REG_VAL_LUT2[0]
REG_VAL_LUT2[1]
REG_VAL_LUT2[2]
REG_VAL_LUT2[3]
DM1_0 Configuration Register 2
Data of LUT3
13B
13C
DM1_0 Configuration Register 2
Data of LUT2
Datasheet
25-Feb-2021
Revision 3.12
290 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
2532
2533
2534
Clock source sel[3:0]
0000: 25M;
0001: 25M/4;
0010: 2.048M
0011: 2.048M/8;
0100: 2.048M/64;
0101: 2.048M/512;
0110: 2.048K;
0111: 2.048K/8;
1000: 2.048K/64;
1001: 2.048K/512;
1010: 2.048K/4096
1011: 2.048K/32768;
1100: 2.048K/262144;
1101: CNT_END;
1110: External;
DM1_0 Configuration Register 2
Clock source selection
13C
2535
1111: External
2536
2537
2538
2539
2540
2541
2542
2543
2544
DM1_0 Configuration Register 2
Data of Delay
13D
Data[7:0]
00: bypass the initial
01: initial 0
10: initial 1
DM1_0 Configuration Register 2
DLY input initial selection
2545
11: initial 1
2546
2547
2548
0000: Both Edge Delay
0001: Falling Edge Delay
0010: Rising Edge Delay
0011: Both Edge One Shot
0100: Falling Edge One Shot
0101: Rising Edge One Shot
0110: Both Edge Freq Detect
0111: Falling Edge Freq Detect
1000: Rising Edge Freq Detect
1001: Both Edge Detect
1010: Falling Edge Detect
1011: Rising Edge Detect
1100: Both Edge Reset CNT
1101: Falling Edge Reset CNT
1110: Rising Edge Reset CNT
1111: High Level Reset CNT
DM1_0 Configuration Register 2
DLY/CNT Function selection
13E
2549
DM1_0 Configuration Register 2
MUX1 selection for LUT2
0: from LUT3
1: from matrix (DLY IN)
2550
2551
DM1_0 Configuration Register 2
MUX2 selection for DLY input
0: from matrix (DLY IN)
1: from LUT3
Datasheet
25-Feb-2021
Revision 3.12
291 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
DM1_0 Configuration Register 3
IN0 of LUT3
REG_MATRIX_LUT3_IN0_SEL[5:0]
13F
DM1_0 Configuration Register 3
IN1 of LUT3
REG_MATRIX_LUT3_IN1_SEL[5:0]
REG_MATRIX_LUT3_IN2_SEL[5:0]
DM Delay input
140
DM1_0 Configuration Register 3
IN2 of LUT3
141
DM1_0 Configuration Register 3
DLY input from matrix
REG_VAL_LUT3[0]
REG_VAL_LUT3[1]
REG_VAL_LUT3[2]
REG_VAL_LUT3[3]
REG_VAL_LUT3[4]
REG_VAL_LUT3[5]
REG_VAL_LUT3[6]
REG_VAL_LUT3[7]
REG_VAL_LUT2[0]
REG_VAL_LUT2[1]
REG_VAL_LUT2[2]
REG_VAL_LUT2[3]
DM1_0 Configuration Register 3
Data of LUT3
142
143
DM1_0 Configuration Register 3
Data of LUT2
Datasheet
25-Feb-2021
Revision 3.12
292 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
2588
2589
2590
Clock source sel[3:0]
0000: 25M;
0001: 25M/4;
0010: 2.048M
0011: 2.048M/8;
0100: 2.048M/64;
0101: 2.048M/512;
0110: 2.048K;
0111: 2.048K/8;
1000: 2.048K/64;
1001: 2.048K/512;
1010: 2.048K/4096
1011: 2.048K/32768;
1100: 2.048K/262144;
1101: CNT_END;
1110: External;
DM1_0 Configuration Register 3
Clock source selection
143
2591
1111: External
2592
2593
2594
2595
2596
2597
2598
2599
2600
DM1_0 Configuration Register 3
Data of Delay
144
Data[7:0]
00: bypass the initial
01: initial 0
10: initial 1
DM1_0 Configuration Register 3
DLY input initial selection
2601
11: initial 1
2602
2603
2604
0000: Both Edge Delay
0001: Falling Edge Delay
0010: Rising Edge Delay
0011: Both Edge One Shot
0100: Falling Edge One Shot
0101: Rising Edge One Shot
0110: Both Edge Freq Detect
0111: Falling Edge Freq Detect
1000: Rising Edge Freq Detect
1001: Both Edge Detect
1010: Falling Edge Detect
1011: Rising Edge Detect
1100: Both Edge Reset CNT
1101: Falling Edge Reset CNT
1110: Rising Edge Reset CNT
1111: High Level Reset CNT
DM1_0 Configuration Register 3
DLY/CNT Function selection
145
2605
DM1_0 Configuration Register 3
MUX1 selection for LUT2
0: from LUT3
1: from matrix (DLY IN)
2606
2607
DM1_0 Configuration Register 3
MUX2 selection for DLY input
0: from matrix (DLY IN)
1: from LUT3
Datasheet
25-Feb-2021
Revision 3.12
293 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
DM1_0 Configuration Register 4
IN0 of LUT3
REG_MATRIX_LUT3_IN0_SEL[5:0]
146
DM1_0 Configuration Register 4
IN1 of LUT3
REG_MATRIX_LUT3_IN1_SEL[5:0]
REG_MATRIX_LUT3_IN2_SEL[5:0]
DM Delay input
147
DM1_0 Configuration Register 4
IN2 of LUT3
148
DM1_0 Configuration Register 4
DLY input from matrix
REG_VAL_LUT3[0]
REG_VAL_LUT3[1]
REG_VAL_LUT3[2]
REG_VAL_LUT3[3]
REG_VAL_LUT3[4]
REG_VAL_LUT3[5]
REG_VAL_LUT3[6]
REG_VAL_LUT3[7]
REG_VAL_LUT2[0]
REG_VAL_LUT2[1]
REG_VAL_LUT2[2]
REG_VAL_LUT2[3]
DM1_0 Configuration Register 4
Data of LUT3
149
14A
DM1_0 Configuration Register 4
Data of LUT2
Datasheet
25-Feb-2021
Revision 3.12
294 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
2644
2645
2646
Clock source sel[3:0]
0000: 25M;
0001: 25M/4;
0010: 2.048M
0011: 2.048M/8;
0100: 2.048M/64;
0101: 2.048M/512;
0110: 2.048K;
0111: 2.048K/8;
1000: 2.048K/64;
1001: 2.048K/512;
1010: 2.048K/4096
1011: 2.048K/32768;
1100: 2.048K/262144;
1101: CNT_END;
1110: External;
DM1_0 Configuration Register 4
Clock source selection
14A
2647
1111: External
2648
2649
2650
2651
2652
2653
2654
2655
2656
DM1_0 Configuration Register 4
Data of Delay
14B
Data[7:0]
00: bypass the initial
01: initial 0
10: initial 1
DM1_0 Configuration Register 4
DLY input initial selection
2657
11: initial 1
2658
2659
2660
0000: Both Edge Delay
0001: Falling Edge Delay
0010: Rising Edge Delay
0011: Both Edge One Shot
0100: Falling Edge One Shot
0101: Rising Edge One Shot
0110: Both Edge Freq Detect
0111: Falling Edge Freq Detect
1000: Rising Edge Freq Detect
1001: Both Edge Detect
1010: Falling Edge Detect
1011: Rising Edge Detect
1100: Both Edge Reset CNT
1101: Falling Edge Reset CNT
1110: Rising Edge Reset CNT
1111: High Level Reset CNT
DM1_0 Configuration Register 4
DLY/CNT Function selection
14C
2661
DM1_0 Configuration Register 4
MUX1 selection for LUT2
0: from LUT3
1: from matrix (DLY IN)
2662
2663
DM1_0 Configuration Register 4
MUX2 selection for DLY input
0: from matrix (DLY IN)
1: from LUT3
Datasheet
25-Feb-2021
Revision 3.12
295 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
DM1_0 Configuration Register 5
IN0 of LUT3
REG_MATRIX_LUT3_IN0_SEL[5:0]
14D
DM1_0 Configuration Register 5
IN1 of LUT3
REG_MATRIX_LUT3_IN1_SEL[5:0]
REG_MATRIX_LUT3_IN2_SEL[5:0]
DM Delay input
14E
DM1_0 Configuration Register 5
IN2 of LUT3
14F
DM1_0 Configuration Register 5
DLY input from matrix
REG_VAL_LUT3[0]
REG_VAL_LUT3[1]
REG_VAL_LUT3[2]
REG_VAL_LUT3[3]
REG_VAL_LUT3[4]
REG_VAL_LUT3[5]
REG_VAL_LUT3[6]
REG_VAL_LUT3[7]
REG_VAL_LUT2[0]
REG_VAL_LUT2[1]
REG_VAL_LUT2[2]
REG_VAL_LUT2[3]
DM1_0 Configuration Register 5
Data of LUT3
150
151
DM1_0 Configuration Register 5
Data of LUT2
Datasheet
25-Feb-2021
Revision 3.12
296 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
2700
2701
2702
Clock source sel[3:0]
0000: 25M;
0001: 25M/4;
0010: 2.048M
0011: 2.048M/8;
0100: 2.048M/64;
0101: 2.048M/512;
0110: 2.048K;
0111: 2.048K/8;
1000: 2.048K/64;
1001: 2.048K/512;
1010: 2.048K/4096
1011: 2.048K/32768;
1100: 2.048K/262144;
1101: CNT_END;
1110: External;
DM1_0 Configuration Register 5
Clock source selection
151
2703
1111: External
2704
2705
2706
2707
2708
2709
2710
2711
2712
DM1_0 Configuration Register 5
Data of Delay
152
Data[7:0]
00: bypass the initial
01: initial 0
10: initial 1
DM1_0 Configuration Register 5
DLY input initial selection
2713
11: initial 1
2714
2715
2716
0000: Both Edge Delay
0001: Falling Edge Delay
0010: Rising Edge Delay
0011: Both Edge One Shot
0100: Falling Edge One Shot
0101: Rising Edge One Shot
0110: Both Edge Freq Detect
0111: Falling Edge Freq Detect
1000: Rising Edge Freq Detect
1001: Both Edge Detect
1010: Falling Edge Detect
1011: Rising Edge Detect
1100: Both Edge Reset CNT
1101: Falling Edge Reset CNT
1110: Rising Edge Reset CNT
1111: High Level Reset CNT
DM1_0 Configuration Register 5
DLY/CNT Function selection
153
2717
DM1_0 Configuration Register 5
MUX1 selection for LUT2
0: from LUT3
1: from matrix (DLY IN)
2718
2719
DM1_0 Configuration Register 5
MUX2 selection for DLY input
0: from matrix (DLY IN)
1: from LUT3
Datasheet
25-Feb-2021
Revision 3.12
297 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
DM1_1 Configuration Register 0
IN0 of LUT3
REG_MATRIX_LUT3_IN0_SEL[5:0]
154
DM1_1 Configuration Register 0
IN1 of LUT3
REG_MATRIX_LUT3_IN1_SEL[5:0]
REG_MATRIX_LUT3_IN2_SEL[5:0]
DM Delay input
155
DM1_1 Configuration Register 0
IN2 of LUT3
156
DM1_1 Configuration Register 0
DLY input from matrix
REG_VAL_LUT3[0]
REG_VAL_LUT3[1]
REG_VAL_LUT3[2]
REG_VAL_LUT3[3]
REG_VAL_LUT3[4]
REG_VAL_LUT3[5]
REG_VAL_LUT3[6]
REG_VAL_LUT3[7]
REG_VAL_LUT2[0]
REG_VAL_LUT2[1]
REG_VAL_LUT2[2]
REG_VAL_LUT2[3]
DM1_1 Configuration Register 0
Data of LUT3
157
158
DM1_1 Configuration Register 0
Data of LUT2
Datasheet
25-Feb-2021
Revision 3.12
298 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
2756
2757
2758
Clock source sel[3:0]
0000: 25M;
0001: 25M/4;
0010: 2.048M
0011: 2.048M/8;
0100: 2.048M/64;
0101: 2.048M/512;
0110: 2.048K;
0111: 2.048K/8;
1000: 2.048K/64;
1001: 2.048K/512;
1010: 2.048K/4096
1011: 2.048K/32768;
1100: 2.048K/262144;
1101: CNT_END;
1110: External;
DM1_1 Configuration Register 0
Clock source selection
158
2759
1111: External
2760
2761
2762
2763
2764
2765
2766
2767
2768
DM1_1 Configuration Register 0
Data of Delay
159
Data[7:0]
00: bypass the initial
01: initial 0
10: initial 1
DM1_1 Configuration Register 0
DLY input initial selection
2769
11: initial 1
2770
2771
2772
0000: Both Edge Delay
0001: Falling Edge Delay
0010: Rising Edge Delay
0011: Both Edge One Shot
0100: Falling Edge One Shot
0101: Rising Edge One Shot
0110: Both Edge Freq Detect
0111: Falling Edge Freq Detect
1000: Rising Edge Freq Detect
1001: Both Edge Detect
1010: Falling Edge Detect
1011: Rising Edge Detect
1100: Both Edge Reset CNT
1101: Falling Edge Reset CNT
1110: Rising Edge Reset CNT
1111: High Level Reset CNT
DM1_1 Configuration Register 0
DLY/CNT Function selection
15A
2773
DM1_1 Configuration Register 0
MUX1 selection for LUT2
0: from LUT3
1: from matrix (DLY IN)
2774
2775
DM1_1 Configuration Register 0
MUX2 selection for DLY input
0: from matrix (DLY IN)
1: from LUT3
Datasheet
25-Feb-2021
Revision 3.12
299 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
DM1_1 Configuration Register 1
IN0 of LUT3
REG_MATRIX_LUT3_IN0_SEL[5:0]
15B
DM1_1 Configuration Register 1
IN1 of LUT3
REG_MATRIX_LUT3_IN1_SEL[5:0]
REG_MATRIX_LUT3_IN2_SEL[5:0]
DM Delay input
15C
DM1_1 Configuration Register 1
IN2 of LUT3
15D
DM1_1 Configuration Register 1
DLY input from matrix
REG_VAL_LUT3[0]
REG_VAL_LUT3[1]
REG_VAL_LUT3[2]
REG_VAL_LUT3[3]
REG_VAL_LUT3[4]
REG_VAL_LUT3[5]
REG_VAL_LUT3[6]
REG_VAL_LUT3[7]
REG_VAL_LUT2[0]
REG_VAL_LUT2[1]
REG_VAL_LUT2[2]
REG_VAL_LUT2[3]
DM1_1 Configuration Register 1
Data of LUT3
15E
15F
DM1_1 Configuration Register 1
Data of LUT2
Datasheet
25-Feb-2021
Revision 3.12
300 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
2812
2813
2814
Clock source sel[3:0]
0000: 25M;
0001: 25M/4;
0010: 2.048M
0011: 2.048M/8;
0100: 2.048M/64;
0101: 2.048M/512;
0110: 2.048K;
0111: 2.048K/8;
1000: 2.048K/64;
1001: 2.048K/512;
1010: 2.048K/4096
1011: 2.048K/32768;
1100: 2.048K/262144;
1101: CNT_END;
1110: External;
DM1_1 Configuration Register 1
Clock source selection
15F
2815
1111: External
2816
2817
2818
2819
2820
2821
2822
2823
2824
DM1_1 Configuration Register 1
Data of Delay
160
Data[7:0]
00: bypass the initial
01: initial 0
10: initial 1
DM1_1 Configuration Register 1
DLY input initial selection
2825
11: initial 1
2826
2827
2828
0000: Both Edge Delay
0001: Falling Edge Delay
0010: Rising Edge Delay
0011: Both Edge One Shot
0100: Falling Edge One Shot
0101: Rising Edge One Shot
0110: Both Edge Freq Detect
0111: Falling Edge Freq Detect
1000: Rising Edge Freq Detect
1001: Both Edge Detect
1010: Falling Edge Detect
1011: Rising Edge Detect
1100: Both Edge Reset CNT
1101: Falling Edge Reset CNT
1110: Rising Edge Reset CNT
1111: High Level Reset CNT
DM1_1 Configuration Register 1
DLY/CNT Function selection
161
2829
DM1_1 Configuration Register 1
MUX1 selection for LUT2
0: from LUT3
1: from matrix (DLY IN)
2830
2831
DM1_1 Configuration Register 1
MUX2 selection for DLY input
0: from matrix (DLY IN)
1: from LUT3
Datasheet
25-Feb-2021
Revision 3.12
301 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
DM1_1 Configuration Register 2
IN0 of LUT3
REG_MATRIX_LUT3_IN0_SEL[5:0]
162
DM1_1 Configuration Register 2
IN1 of LUT3
REG_MATRIX_LUT3_IN1_SEL[5:0]
REG_MATRIX_LUT3_IN2_SEL[5:0]
DM Delay input
163
DM1_1 Configuration Register 2
IN2 of LUT3
164
DM1_1 Configuration Register 2
DLY input from matrix
REG_VAL_LUT3[0]
REG_VAL_LUT3[1]
REG_VAL_LUT3[2]
REG_VAL_LUT3[3]
REG_VAL_LUT3[4]
REG_VAL_LUT3[5]
REG_VAL_LUT3[6]
REG_VAL_LUT3[7]
REG_VAL_LUT2[0]
REG_VAL_LUT2[1]
REG_VAL_LUT2[2]
REG_VAL_LUT2[3]
DM1_1 Configuration Register 2
Data of LUT3
165
166
DM1_1 Configuration Register 2
Data of LUT2
Datasheet
25-Feb-2021
Revision 3.12
302 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
2868
2869
2870
Clock source sel[3:0]
0000: 25M;
0001: 25M/4;
0010: 2.048M
0011: 2.048M/8;
0100: 2.048M/64;
0101: 2.048M/512;
0110: 2.048K;
0111: 2.048K/8;
1000: 2.048K/64;
1001: 2.048K/512;
1010: 2.048K/4096
1011: 2.048K/32768;
1100: 2.048K/262144;
1101: CNT_END;
1110: External;
DM1_1 Configuration Register 2
Clock source selection
166
2871
1111: External
2872
2873
2874
2875
2876
2877
2878
2879
2880
DM1_1 Configuration Register 2
Data of Delay
167
Data[7:0]
00: bypass the initial
01: initial 0
10: initial 1
DM1_1 Configuration Register 2
DLY input initial selection
2881
11: initial 1
2882
2883
2884
0000: Both Edge Delay
0001: Falling Edge Delay
0010: Rising Edge Delay
0011: Both Edge One Shot
0100: Falling Edge One Shot
0101: Rising Edge One Shot
0110: Both Edge Freq Detect
0111: Falling Edge Freq Detect
1000: Rising Edge Freq Detect
1001: Both Edge Detect
1010: Falling Edge Detect
1011: Rising Edge Detect
1100: Both Edge Reset CNT
1101: Falling Edge Reset CNT
1110: Rising Edge Reset CNT
1111: High Level Reset CNT
DM1_1 Configuration Register 2
DLY/CNT Function selection
168
2885
DM1_1 Configuration Register 2
MUX1 selection for LUT2
0: from LUT3
1: from matrix (DLY IN)
2886
2887
DM1_1 Configuration Register 2
MUX2 selection for DLY input
0: from matrix (DLY IN)
1: from LUT3
Datasheet
25-Feb-2021
Revision 3.12
303 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
DM1_1 Configuration Register 3
IN0 of LUT3
REG_MATRIX_LUT3_IN0_SEL[5:0]
169
DM1_1 Configuration Register 3
IN1 of LUT3
REG_MATRIX_LUT3_IN1_SEL[5:0]
REG_MATRIX_LUT3_IN2_SEL[5:0]
DM Delay input
16A
DM1_1 Configuration Register 3
IN2 of LUT3
16B
DM1_1 Configuration Register 3
DLY input from matrix
REG_VAL_LUT3[0]
REG_VAL_LUT3[1]
REG_VAL_LUT3[2]
REG_VAL_LUT3[3]
REG_VAL_LUT3[4]
REG_VAL_LUT3[5]
REG_VAL_LUT3[6]
REG_VAL_LUT3[7]
REG_VAL_LUT2[0]
REG_VAL_LUT2[1]
REG_VAL_LUT2[2]
REG_VAL_LUT2[3]
DM1_1 Configuration Register 3
Data of LUT3
16C
16D
DM1_1 Configuration Register 3
Data of LUT2
Datasheet
25-Feb-2021
Revision 3.12
304 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
2924
2925
2926
Clock source sel[3:0]
0000: 25M;
0001: 25M/4;
0010: 2.048M
0011: 2.048M/8;
0100: 2.048M/64;
0101: 2.048M/512;
0110: 2.048K;
0111: 2.048K/8;
1000: 2.048K/64;
1001: 2.048K/512;
1010: 2.048K/4096
1011: 2.048K/32768;
1100: 2.048K/262144;
1101: CNT_END;
1110: External;
DM1_1 Configuration Register 3
Clock source selection
16D
2927
1111: External
2928
2929
2930
2931
2932
2933
2934
2935
2936
DM1_1 Configuration Register 3
Data of Delay
16E
Data[7:0]
00: bypass the initial
01: initial 0
10: initial 1
DM1_1 Configuration Register 3
DLY input initial selection
2937
11: initial 1
2938
2939
2940
0000: Both Edge Delay
0001: Falling Edge Delay
0010: Rising Edge Delay
0011: Both Edge One Shot
0100: Falling Edge One Shot
0101: Rising Edge One Shot
0110: Both Edge Freq Detect
0111: Falling Edge Freq Detect
1000: Rising Edge Freq Detect
1001: Both Edge Detect
1010: Falling Edge Detect
1011: Rising Edge Detect
1100: Both Edge Reset CNT
1101: Falling Edge Reset CNT
1110: Rising Edge Reset CNT
1111: High Level Reset CNT
DM1_1 Configuration Register 3
DLY/CNT Function selection
16F
2941
DM1_1 Configuration Register 3
MUX1 selection for LUT2
0: from LUT3
1: from matrix (DLY IN)
2942
2943
DM1_1 Configuration Register 3
MUX2 selection for DLY input
0: from matrix (DLY IN)
1: from LUT3
Datasheet
25-Feb-2021
Revision 3.12
305 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
DM1_1 Configuration Register 4
IN0 of LUT3
REG_MATRIX_LUT3_IN0_SEL[5:0]
170
DM1_1 Configuration Register 4
IN1 of LUT3
REG_MATRIX_LUT3_IN1_SEL[5:0]
REG_MATRIX_LUT3_IN2_SEL[5:0]
DM Delay input
171
DM1_1 Configuration Register 4
IN2 of LUT3
172
DM1_1 Configuration Register 4
DLY input from matrix
REG_VAL_LUT3[0]
REG_VAL_LUT3[1]
REG_VAL_LUT3[2]
REG_VAL_LUT3[3]
REG_VAL_LUT3[4]
REG_VAL_LUT3[5]
REG_VAL_LUT3[6]
REG_VAL_LUT3[7]
REG_VAL_LUT2[0]
REG_VAL_LUT2[1]
REG_VAL_LUT2[2]
REG_VAL_LUT2[3]
DM1_1 Configuration Register 4
Data of LUT3
173
174
DM1_1 Configuration Register 4
Data of LUT2
Datasheet
25-Feb-2021
Revision 3.12
306 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
2980
2981
2982
Clock source sel[3:0]
0000: 25M;
0001: 25M/4;
0010: 2.048M
0011: 2.048M/8;
0100: 2.048M/64;
0101: 2.048M/512;
0110: 2.048K;
0111: 2.048K/8;
1000: 2.048K/64;
1001: 2.048K/512;
1010: 2.048K/4096
1011: 2.048K/32768;
1100: 2.048K/262144;
1101: CNT_END;
1110: External;
DM1_1 Configuration Register 4
Clock source selection
174
2983
1111: External
2984
2985
2986
2987
2988
2989
2990
2991
2992
DM1_1 Configuration Register 4
Data of Delay
175
Data[7:0]
00: bypass the initial
01: initial 0
10: initial 1
DM1_1 Configuration Register 4
DLY input initial selection
2993
11: initial 1
2994
2995
2996
0000: Both Edge Delay
0001: Falling Edge Delay
0010: Rising Edge Delay
0011: Both Edge One Shot
0100: Falling Edge One Shot
0101: Rising Edge One Shot
0110: Both Edge Freq Detect
0111: Falling Edge Freq Detect
1000: Rising Edge Freq Detect
1001: Both Edge Detect
1010: Falling Edge Detect
1011: Rising Edge Detect
1100: Both Edge Reset CNT
1101: Falling Edge Reset CNT
1110: Rising Edge Reset CNT
1111: High Level Reset CNT
DM1_1 Configuration Register 4
DLY/CNT Function selection
176
2997
DM1_1 Configuration Register 4
MUX1 selection for LUT2
0: from LUT3
1: from matrix (DLY IN)
2998
2999
DM1_1 Configuration Register 4
MUX2 selection for DLY input
0: from matrix (DLY IN)
1: from LUT3
Datasheet
25-Feb-2021
Revision 3.12
307 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
DM1_1 Configuration Register 5
IN0 of LUT3
REG_MATRIX_LUT3_IN0_SEL[5:0]
177
DM1_1 Configuration Register 5
IN1 of LUT3
REG_MATRIX_LUT3_IN1_SEL[5:0]
REG_MATRIX_LUT3_IN2_SEL[5:0]
DM Delay input
178
DM1_1 Configuration Register 5
IN2 of LUT3
179
DM1_1 Configuration Register 5
DLY input from matrix
REG_VAL_LUT3[0]
REG_VAL_LUT3[1]
REG_VAL_LUT3[2]
REG_VAL_LUT3[3]
REG_VAL_LUT3[4]
REG_VAL_LUT3[5]
REG_VAL_LUT3[6]
REG_VAL_LUT3[7]
REG_VAL_LUT2[0]
REG_VAL_LUT2[1]
REG_VAL_LUT2[2]
REG_VAL_LUT2[3]
DM1_1 Configuration Register 5
Data of LUT3
17A
17B
DM1_1 Configuration Register 5
Data of LUT2
Datasheet
25-Feb-2021
Revision 3.12
308 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
3036
3037
3038
Clock source sel[3:0]
0000: 25M;
0001: 25M/4;
0010: 2.048M
0011: 2.048M/8;
0100: 2.048M/64;
0101: 2.048M/512;
0110: 2.048K;
0111: 2.048K/8;
1000: 2.048K/64;
1001: 2.048K/512;
1010: 2.048K/4096
1011: 2.048K/32768;
1100: 2.048K/262144;
1101: CNT_END;
1110: External;
DM1_1 Configuration Register 5
Clock source selection
17B
3039
1111: External
3040
3041
3042
3043
3044
3045
3046
3047
3048
DM1_1 Configuration Register 5
Data of Delay
17C
Data[7:0]
00: bypass the initial
01: initial 0
10: initial 1
DM1_1 Configuration Register 5
DLY input initial selection
3049
11: initial 1
3050
3051
3052
0000: Both Edge Delay
0001: Falling Edge Delay
0010: Rising Edge Delay
0011: Both Edge One Shot
0100: Falling Edge One Shot
0101: Rising Edge One Shot
0110: Both Edge Freq Detect
0111: Falling Edge Freq Detect
1000: Rising Edge Freq Detect
1001: Both Edge Detect
1010: Falling Edge Detect
1011: Rising Edge Detect
1100: Both Edge Reset CNT
1101: Falling Edge Reset CNT
1110: Rising Edge Reset CNT
1111: High Level Reset CNT
DM1_1 Configuration Register 5
DLY/CNT Function selection
17D
3053
DM1_1 Configuration Register 5
MUX1 selection for LUT2
0: from LUT3
1: from matrix (DLY IN)
3054
3055
DM1_1 Configuration Register 5
MUX2 selection for DLY input
0: from matrix (DLY IN)
1: from LUT3
Datasheet
25-Feb-2021
Revision 3.12
309 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
DM0_0 Selection Register State 0, bit [0]
DM0_0 Selection Register State 1, bit [0]
DM0_0 Selection Register State 2, bit [0]
DM0_0 Selection Register State 3, bit [0]
DM0_0 Selection Register State 4, bit [0]
DM0_0 Selection Register State 5, bit [0]
DM0_0 Selection Register State 6, bit [0]
DM0_0 Selection Register State 7, bit [0]
DM0_0 Selection Register State 8, bit [0]
DM0_0 Selection Register State 9, bit [0]
DM0_0 Selection Register State 10, bit [0]
DM0_0 Selection Register State 11, bit [0]
DM0_0 Selection Register State 0, bit [1]
DM0_0 Selection Register State 1, bit [1]
DM0_0 Selection Register State 2, bit [1]
DM0_0 Selection Register State 3, bit [1]
DM0_0 Selection Register State 4, bit [1]
DM0_0 Selection Register State 5, bit [1]
DM0_0 Selection Register State 6, bit [1]
DM0_0 Selection Register State 7, bit [1]
DM0_0 Selection Register State 8, bit [1]
DM0_0 Selection Register State 9, bit [1]
DM0_0 Selection Register State 10, bit [1]
DM0_0 Selection Register State 11, bit [1]
DM0_0 Selection Register State 0, bit [2]
DM0_0 Selection Register State 1, bit [2]
DM0_0 Selection Register State 2, bit [2]
DM0_0 Selection Register State 3, bit [2]
DM0_0 Selection Register State 4, bit [2]
DM0_0 Selection Register State 5, bit [2]
DM0_0 Selection Register State 6, bit [2]
DM0_0 Selection Register State 7, bit [2]
DM0_0 Selection Register State 8, bit [2]
DM0_0 Selection Register State 9, bit [2]
DM0_0 Selection Register State 10, bit [2]
DM0_0 Selection Register State 11, bit [2]
selection bit[2:0]:
000: Not Used
17E
001: DM0_0 Configuration Register 0
010: DM0_0 Configuration Register 1
011: DM0_0 Configuration Register 2
100: DM0_0 Configuration Register 3
101: DM0_0 Configuration Register 4
110: DM0_0 Configuration Register 5
111: Not Used
17F
selection bit[2:0]:
000: Not Used
001: DM0_0 Configuration Register 0
010: DM0_0 Configuration Register 1
011: DM0_0 Configuration Register 2
100: DM0_0 Configuration Register 3
101: DM0_0 Configuration Register 4
110: DM0_0 Configuration Register 5
111: Not Used
180
selection bit[2:0]:
000: Not Used
181
182
001: DM0_0 Configuration Register 0
010: DM0_0 Configuration Register 1
011: DM0_0 Configuration Register 2
100: DM0_0 Configuration Register 3
101: DM0_0 Configuration Register 4
110: DM0_0 Configuration Register 5
111: Not Used
Datasheet
25-Feb-2021
Revision 3.12
310 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
DM0_0 Output Configuration Selection Reg
ister State 0, bit [0]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
DM0_0 Output Configuration Selection Reg
ister State 1, bit [0]
182
DM0_0 Output Configuration Selection Reg
ister State 2, bit [0]
DM0_0 Output Configuration Selection Reg
ister State 3, bit [0]
DM0_0 Output Configuration Selection Reg
ister State 4, bit [0]
control bit[1:0]:
00:DM out0/1/2 keep
01:DM out bypass to out0, out1/2 keep
10: DM out bypass to out1, out0/2 keep
11: DM out bypass to out2, out0/1 keep
DM0_0 Output Configuration Selection Reg
ister State 5, bit [0]
DM0_0 Output Configuration Selection Reg
ister State 6, bit [0]
DM0_0 Output Configuration Selection Reg
ister State 7, bit [0]
183
DM0_0 Output Configuration Selection Reg
ister State 8, bit [0]
DM0_0 Output Configuration Selection Reg
ister State 9, bit [0]
DM0_0 Output Configuration Selection Reg
ister State 10, bit [0]
DM0_0 Output Configuration Selection Reg
ister State 11, bit [0]
DM0_0 Output Configuration Selection Reg
ister State 0, bit [1]
DM0_0 Output Configuration Selection Reg
ister State 1, bit [1]
DM0_0 Output Configuration Selection Reg
ister State 2, bit [1]
DM0_0 Output Configuration Selection Reg
ister State 3, bit [1]
184
DM0_0 Output Configuration Selection Reg
ister State 4, bit [1]
control bit[1:0]:
00:DM out0/1/2 keep
01:DM out bypass to out0, out1/2 keep
10: DM out bypass to out1, out0/2 keep
11: DM out bypass to out2, out0/1 keep
DM0_0 Output Configuration Selection Reg
ister State 5, bit [1]
DM0_0 Output Configuration Selection Reg
ister State 6, bit [1]
DM0_0 Output Configuration Selection Reg
ister State 7, bit [1]
DM0_0 Output Configuration Selection Reg
ister State 8, bit [1]
DM0_0 Output Configuration Selection Reg
ister State 9, bit [1]
185
DM0_0 Output Configuration Selection Reg
ister State 10, bit [1]
DM0_0 Output Configuration Selection Reg
ister State 11, bit [1]
Datasheet
25-Feb-2021
Revision 3.12
311 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151
DM1_0 Selection Register State 0, bit [0]
DM1_0 Selection Register State 1, bit [0]
DM1_0 Selection Register State 2, bit [0]
DM1_0 Selection Register State 3, bit [0]
DM1_0 Selection Register State 4, bit [0]
DM1_0 Selection Register State 5, bit [0]
DM1_0 Selection Register State 6, bit [0]
DM1_0 Selection Register State 7, bit [0]
DM1_0 Selection Register State 8, bit [0]
DM1_0 Selection Register State 9, bit [0]
DM1_0 Selection Register State 10, bit [0]
DM1_0 Selection Register State 11, bit [0]
DM1_0 Selection Register State 0, bit [1]
DM1_0 Selection Register State 1, bit [1]
DM1_0 Selection Register State 2, bit [1]
DM1_0 Selection Register State 3, bit [1]
DM1_0 Selection Register State 4, bit [1]
DM1_0 Selection Register State 5, bit [1]
DM1_0 Selection Register State 6, bit [1]
DM1_0 Selection Register State 7, bit [1]
DM1_0 Selection Register State 8, bit [1]
DM1_0 Selection Register State 9, bit [1]
DM1_0 Selection Register State 10, bit [1]
DM1_0 Selection Register State 11, bit [1]
DM1_0 Selection Register State 0, bit [2]
DM1_0 Selection Register State 1, bit [2]
DM1_0 Selection Register State 2, bit [2]
DM1_0 Selection Register State 3, bit [2]
DM1_0 Selection Register State 4, bit [2]
DM1_0 Selection Register State 5, bit [2]
DM1_0 Selection Register State 6, bit [2]
DM1_0 Selection Register State 7, bit [2]
DM1_0 Selection Register State 8, bit [2]
DM1_0 Selection Register State 9, bit [2]
DM1_0 Selection Register State 10, bit [2]
DM1_0 Selection Register State 11, bit [2]
185
selection bit[2:0]:
000: Not Used
001: DM1_0 Configuration Register 0
010: DM1_0 Configuration Register 1
011: DM1_0 Configuration Register 2
100: DM1_0 Configuration Register 3
101: DM1_0 Configuration Register 4
110: DM1_0 Configuration Register 5
111: Not Used
186
187
188
189
selection bit[2:0]:
000: Not Used
001: DM1_0 Configuration Register 0
010: DM1_0 Configuration Register 1
011: DM1_0 Configuration Register 2
100: DM1_0 Configuration Register 3
101: DM1_0 Configuration Register 4
110: DM1_0 Configuration Register 5
111: Not Used
selection bit[2:0]:
000: Not Used
001: DM1_0 Configuration Register 0
010: DM1_0 Configuration Register 1
011: DM1_0 Configuration Register 2
100: DM1_0 Configuration Register 3
101: DM1_0 Configuration Register 4
110: DM1_0 Configuration Register 5
111: Not Used
Datasheet
25-Feb-2021
Revision 3.12
312 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
DM0_1 Selection Register State 0, bit [0]
DM0_1 Selection Register State 1, bit [0]
DM0_1 Selection Register State 2, bit [0]
DM0_1 Selection Register State 3, bit [0]
DM0_1 Selection Register State 4, bit [0]
DM0_1 Selection Register State 5, bit [0]
DM0_1 Selection Register State 6, bit [0]
DM0_1 Selection Register State 7, bit [0]
DM0_1 Selection Register State 8, bit [0]
DM0_1 Selection Register State 9, bit [0]
DM0_1 Selection Register State 10, bit [0]
DM0_1 Selection Register State 11, bit [0]
DM0_1 Selection Register State 0, bit [1]
DM0_1 Selection Register State 1, bit [1]
DM0_1 Selection Register State 2, bit [1]
DM0_1 Selection Register State 3, bit [1]
DM0_1 Selection Register State 4, bit [1]
DM0_1 Selection Register State 5, bit [1]
DM0_1 Selection Register State 6, bit [1]
DM0_1 Selection Register State 7, bit [1]
DM0_1 Selection Register State 8, bit [1]
DM0_1 Selection Register State 9, bit [1]
DM0_1 Selection Register State 10, bit [1]
DM0_1 Selection Register State 11, bit [1]
DM0_1 Selection Register State 0, bit [2]
DM0_1 Selection Register State 1, bit [2]
DM0_1 Selection Register State 2, bit [2]
DM0_1 Selection Register State 3, bit [2]
DM0_1 Selection Register State 4, bit [2]
DM0_1 Selection Register State 5, bit [2]
DM0_1 Selection Register State 6, bit [2]
DM0_1 Selection Register State 7, bit [2]
DM0_1 Selection Register State 8, bit [2]
DM0_1 Selection Register State 9, bit [2]
DM0_1 Selection Register State 10, bit [2]
DM0_1 Selection Register State 11, bit [2]
selection bit[2:0]:
000: Not Used
18A
001: DM0_1 Configuration Register 0
010: DM0_1 Configuration Register 1
011: DM0_1 Configuration Register 2
100: DM0_1 Configuration Register 3
101: DM0_1 Configuration Register 4
110: DM0_1 Configuration Register 5
111: Not Used
18B
selection bit[2:0]:
000: Not Used
001: DM0_1 Configuration Register 0
010: DM0_1 Configuration Register 1
011: DM0_1 Configuration Register 2
100: DM0_1 Configuration Register 3
101: DM0_1 Configuration Register 4
110: DM0_1 Configuration Register 5
111: Not Used
18C
selection bit[2:0]:
000: Not Used
18D
18E
001: DM0_1 Configuration Register 0
010: DM0_1 Configuration Register 1
011: DM0_1 Configuration Register 2
100: DM0_1 Configuration Register 3
101: DM0_1 Configuration Register 4
110: DM0_1 Configuration Register 5
111: Not Used
Datasheet
25-Feb-2021
Revision 3.12
313 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
DM0_1 Output Configuration Selection Reg
ister State 0, bit [0]
-
-
-
-
-
-
-
-
-
-
-
-
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
DM0_1 Output Configuration Selection Reg
ister State 1, bit [0]
18E
DM0_1 Output Configuration Selection Reg
ister State 2, bit [0]
DM0_1 Output Configuration Selection Reg
ister State 3, bit [0]
DM0_1 Output Configuration Selection Reg
ister State 4, bit [0]
control bit[1:0]:
00:DM out0/1/2 keep
01:DM out bypass to out0, out1/2 keep
10: DM out bypass to out1, out0/2 keep
11: DM out bypass to out2, out0/1 keep
DM0_1 Output Configuration Selection Reg
ister State 5, bit [0]
DM0_1 Output Configuration Selection Reg
ister State 6, bit [0]
DM0_1 Output Configuration Selection Reg
ister State 7, bit [0]
18F
DM0_1 Output Configuration Selection Reg
ister State 8, bit [0]
DM0_1 Output Configuration Selection Reg
ister State 9, bit [0]
DM0_1 Output Configuration Selection Reg
ister State 10, bit [0]
DM0_1 Output Configuration Selection Reg
ister State 11, bit [0]
Datasheet
25-Feb-2021
Revision 3.12
314 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
DM0_1 Output Configuration Selection Reg
ister State 0, bit [1]
-
-
-
-
-
-
-
-
-
-
-
-
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
DM0_1 Output Configuration Selection Reg
ister State 1, bit [1]
DM0_1 Output Configuration Selection Reg
ister State 2, bit [1]
DM0_1 Output Configuration Selection Reg
ister State 3, bit [1]
190
DM0_1 Output Configuration Selection Reg
ister State 4, bit [1]
control bit[1:0]:
00:DM out0/1/2 keep
01:DM out bypass to out0, out1/2 keep
10: DM out bypass to out1, out0/2 keep
11: DM out bypass to out2, out0/1 keep
DM0_1 Output Configuration Selection Reg
ister State 5, bit [1]
DM0_1 Output Configuration Selection Reg
ister State 6, bit [1]
DM0_1 Output Configuration Selection Reg
ister State 7, bit [1]
DM0_1 Output Configuration Selection Reg
ister State 8, bit [1]
DM0_1 Output Configuration Selection Reg
ister State 9, bit [1]
DM0_1 Output Configuration Selection Reg
ister State 10, bit [1]
191
DM0_1 Output Configuration Selection Reg
ister State 11, bit [1]
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
DM1_1 Selection Register State 0, bit [0]
DM1_1 Selection Register State 1, bit [0]
DM1_1 Selection Register State 2, bit [0]
DM1_1 Selection Register State 3, bit [0]
DM1_1 Selection Register State 4, bit [0]
DM1_1 Selection Register State 5, bit [0]
DM1_1 Selection Register State 6, bit [0]
DM1_1 Selection Register State 7, bit [0]
DM1_1 Selection Register State 8, bit [0]
DM1_1 Selection Register State 9, bit [0]
DM1_1 Selection Register State 10, bit [0]
DM1_1 Selection Register State 11, bit [0]
selection bit[2:0]:
000: Not Used
001: DM1_1 Configuration Register 0
010: DM1_1 Configuration Register 1
011: DM1_1 Configuration Register 2
100: DM1_1 Configuration Register 3
101: DM1_1 Configuration Register 4
110: DM1_1 Configuration Register 5
111: Not Used
192
Datasheet
25-Feb-2021
Revision 3.12
315 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
DM1_1 Selection Register State 0, bit [1]
DM1_1 Selection Register State 1, bit [1]
DM1_1 Selection Register State 2, bit [1]
DM1_1 Selection Register State 3, bit [1]
DM1_1 Selection Register State 4, bit [1]
DM1_1 Selection Register State 5, bit [1]
DM1_1 Selection Register State 6, bit [1]
DM1_1 Selection Register State 7, bit [1]
DM1_1 Selection Register State 8, bit [1]
DM1_1 Selection Register State 9, bit [1]
DM1_1 Selection Register State 10, bit [1]
DM1_1 Selection Register State 11, bit [1]
DM1_1 Selection Register State 0, bit [2]
DM1_1 Selection Register State 1, bit [2]
DM1_1 Selection Register State 2, bit [2]
DM1_1 Selection Register State 3, bit [2]
DM1_1 Selection Register State 4, bit [2]
DM1_1 Selection Register State 5, bit [2]
DM1_1 Selection Register State 6, bit [2]
DM1_1 Selection Register State 7, bit [2]
DM1_1 Selection Register State 8, bit [2]
DM1_1 Selection Register State 9, bit [2]
DM1_1 Selection Register State 10, bit [2]
DM1_1 Selection Register State 11, bit [2]
selection bit[2:0]:
000: Not Used
193
001: DM1_1 Configuration Register 0
010: DM1_1 Configuration Register 1
011: DM1_1 Configuration Register 2
100: DM1_1 Configuration Register 3
101: DM1_1 Configuration Register 4
110: DM1_1 Configuration Register 5
111: Not Used
194
selection bit[2:0]:
000: Not Used
001: DM1_1 Configuration Register 0
010: DM1_1 Configuration Register 1
011: DM1_1 Configuration Register 2
100: DM1_1 Configuration Register 3
101: DM1_1 Configuration Register 4
110: DM1_1 Configuration Register 5
111: Not Used
195
0: initial 0
1: initial 1
3248
3249
DM0_0 function 4 outputs initial value
DM0_1 function 4 outputs initial value
0: initial 0
1: initial 1
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
196
197
Vrefo0 register Power-down signal
0: Power-down, 1: Power-On
3260
3261
VrefO0 register PD control
VrefO0 PD control select
Vrefo0 pd selection
0: from register [3260], 1: from matrix out 78
Datasheet
25-Feb-2021
Revision 3.12
316 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
Vrefo1 register Power-down signal
0: Power-down, 1: Power-On
3262
3263
VrefO1 register PD control
VrefO1 PD control select
197
Vrefo1 pd selection
0: from register [3262], 1: from matrix out 78
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
Bit0 (top memory)
Bit1
Bit2
Bit3
198
F1 stack memory, lower byte
Bit4
Bit5
Bit6
Bit7
Bit8
Bit9
Bit10
Bit11
Bit12
Bit13
Bit14
Bit15
199
F1 stack memory, higher byte
00: aio0
01: aio1
10: aio2
11: aio3
aio0-3 input selection load 1
ACMP4_F Vref selection load 1
aio0-3 input selection load 2
ACMP4_F Vref selection load 2
aio4-7 input selection load 3
3281
3282
3283
3284
3285
3286
3287
3288
"F1 input selection load 1" bit = 0:
Matrix input select: 000000: Matrix in0; ~ 111111: Matrix
in63
"F1 input selection load 1" bit = 1:
ACMP Vref select:
000000: 32 mV ~ 111110: 2.016 V/step = 32 mV;
111111: External Vref
19A
00: aio0
01: aio1
10: aio2
11: aio3
3289
3290
3291
3292
3293
3294
3295
3296
"F1 input selection load 1" bit = 0:
Matrix input select: 000000: Matrix in0; ~ 111111: Matrix
in63
"F1 input selection load 1" bit = 1:
ACMP Vref select:
19B
19C
000000: 32 mV ~ 111110: 2.016 V/step = 32 mV;
111111: External Vref
00: aio4
01: aio5
10: aio6
11: aio7
3297
Datasheet
25-Feb-2021
Revision 3.12
317 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
3298
3299
3300
3301
3302
3303
3304
"F1 input selection load 1" bit = 0:
Matrix input select: 000000: Matrix in0; ~ 111111: Matrix
in63
"F1 input selection load 1" bit = 1:
ACMP Vref select:
19C
ACMP4_F Vref selection load 3
000000: 32 mV ~ 111110: 2.016 V/step = 32 mV;
111111: External Vref
00: aio4
01: aio5
10: aio6
11: aio7
aio4-7 input selection load 4
3305
3306
3307
3308
3309
3310
3311
"F1 input selection load 1" bit = 0:
Matrix input select: 000000: Matrix in0; ~ 111111: Matrix
in63
"F1 input selection load 1" bit = 1:
ACMP Vref select:
000000: 32 mV ~ 111110: 2.016 V/step = 32 mV;
111111: External Vref
19D
ACMP4_F Vref selection load 4
0: from matrix
1: from ACMP4_F
3312
3313
3314
3315
F1 input selection load 1
F1 input selection load 2
F1 input selection load 3
0: from matrix
1: from ACMP4_F
0: from matrix
1: from ACMP4_F
0: from matrix
1: from ACMP4_F
F1 input selection load 4
Reserved
19E
3316
3317
3318
000: OSC2
001: OSC2/4
010: OSC1
011: OSC1/8
100: OSC1/64
101: OSC0
delay clock source selection
3319
110: OSC0/8
111: OSC0/64
3320
3321
3322
3323
3324
3325
3326
3327
3328
3329
3330
3331
19F
1A0
F1 delay data
Data[7:0]
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
F1 CMD1 selection
loop;1100:out1;1101:out2;1110:out3; 1111:end.
Datasheet
25-Feb-2021
Revision 3.12
318 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
3332
3333
3334
3335
3336
3337
3338
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
1A0
F1 CMD2 selection
loop;1100:out1;1101:out2;1110:out3; 1111:end.
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
F1 CMD3 selection
F1 CMD4 selection
F1 CMD5 selection
F1 CMD6 selection
F1 CMD7 selection
F1 CMD8 selection
F1 CMD9 selection
F1 CMD10 selection
F1 CMD11 selection
loop;1100:out1;1101:out2;1110:out3; 1111:end.
1A1
1A2
1A3
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
loop;1100:out1;1101:out2;1110:out3; 1111:end.
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
loop;1100:out1;1101:out2;1110:out3; 1111:end.
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
loop;1100:out1;1101:out2;1110:out3; 1111:end.
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
loop;1100:out1;1101:out2;1110:out3; 1111:end.
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
loop;1100:out1;1101:out2;1110:out3; 1111:end.
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
loop;1100:out1;1101:out2;1110:out3; 1111:end.
1A4
1A5
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
loop;1100:out1;1101:out2;1110:out3; 1111:end.
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
loop;1100:out1;1101:out2;1110:out3; 1111:end.
Datasheet
25-Feb-2021
Revision 3.12
319 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
3372
3373
3374
3375
3376
3377
3378
3379
3380
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
1A5
F1 CMD12 selection
loop;1100:out1;1101:out2;1110:out3; 1111:end.
0000:CMD1;0001:CMD2;0010:CMD3;0011:CMD4;010
0:CMD5;0101:CMD6:or;0110:CMD7;0111:CMD8;1000:
CMD9;1001:CMD10;1010:CMD11;1011:CMD12
loop with delay to location selection
00: keep
01: 0
10: 1
1A6
output mux1 initial state setting
output mux2 initial state setting
3381
3382
3383
3384
3385
11: none
00: keep
01: 0
10: 1
11: none
00: keep
01: 0
10: 1
output mux3 initial state setting
11: none
0: no reset stack memory
1: reset stack memory
3386
interrupt reset stack memory enable
1A7
3387
3388
3389
3390
3391
3392
Reserved
Reserved
Reserved
Reserved
Reserved
00: aio0
01: aio1
10: aio2
11: aio3
aio0-3 input selection load 1
ACMP4_F Vref selection load 1
aio0-3 input selection load 2
3393
3394
3395
3396
3397
3398
3399
3400
"F1 input selection load 1" bit = 0:
Matrix input select: 000000: Matrix in0; ~ 111111: Matrix
in63
"F1 input selection load 1" bit = 1:
ACMP Vref select:
000000: 32 mV ~ 111110: 2.016 V/step = 32 mV;
111111: External Vref
1A8
1A9
00: aio0
01: aio1
10: aio2
11: aio3
3401
Datasheet
25-Feb-2021
Revision 3.12
320 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
3402
3403
3404
3405
3406
3407
3408
"F1 input selection load 1" bit = 0:
Matrix input select: 000000: Matrix in0; ~ 111111: Matrix
in63
"F1 input selection load 1" bit = 1:
ACMP Vref select:
1A9
ACMP4_F Vref selection load 2
000000: 32 mV ~ 111110: 2.016 V/step = 32 mV;
111111: External Vref
00: aio4
01: aio5
10: aio6
11: aio7
aio4-7 input selection load 3
ACMP4_F Vref selection load 3
aio4-7 input selection load 4
ACMP4_F Vref selection load 4
3409
3410
3411
3412
3413
3414
3415
3416
"F1 input selection load 1" bit = 0:
Matrix input select: 000000: Matrix in0; ~ 111111: Matrix
in63
"F1 input selection load 1" bit = 1:
ACMP Vref select:
000000: 32 mV ~ 111110: 2.016 V/step = 32 mV;
111111: External Vref
1AA
00: aio4
01: aio5
10: aio6
11: aio7
3417
3418
3419
3420
3421
3422
3423
"F1 input selection load 1" bit = 0:
Matrix input select: 000000: Matrix in0; ~ 111111: Matrix
in63
"F1 input selection load 1" bit = 1:
ACMP Vref select:
000000: 32 mV ~ 111110: 2.016 V/step = 32 mV;
111111: External Vref
1AB
0: from matrix
1: from ACMP4_F
3424
3425
3426
3427
F1 input selection load 1
F1 input selection load 2
F1 input selection load 3
0: from matrix
1: from ACMP4_F
0: from matrix
1: from ACMP4_F
0: from matrix
1: from ACMP4_F
F1 input selection load 4
Reserved
1AC
3428
3429
3430
000: OSC2
001: OSC2/4
010: OSC1
011: OSC1/8
100: OSC1/64
101: OSC0
delay clock source selection
3431
110: OSC0/8
111: OSC0/64
Datasheet
25-Feb-2021
Revision 3.12
321 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467
3468
3469
3470
3471
1AD
F1 delay data
Data[7:0]
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
F1 CMD1 selection
F1 CMD2 selection
F1 CMD3 selection
F1 CMD4 selection
F1 CMD5 selection
F1 CMD6 selection
F1 CMD7 selection
F1 CMD8 selection
loop;1100:out1;1101:out2;1110:out3; 1111:end.
1AE
1AF
1B0
1B1
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
loop;1100:out1;1101:out2;1110:out3; 1111:end.
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
loop;1100:out1;1101:out2;1110:out3; 1111:end.
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
loop;1100:out1;1101:out2;1110:out3; 1111:end.
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
loop;1100:out1;1101:out2;1110:out3; 1111:end.
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
loop;1100:out1;1101:out2;1110:out3; 1111:end.
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
loop;1100:out1;1101:out2;1110:out3; 1111:end.
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
loop;1100:out1;1101:out2;1110:out3; 1111:end.
Datasheet
25-Feb-2021
Revision 3.12
322 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
3472
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
F1 CMD9 selection
loop;1100:out1;1101:out2;1110:out3; 1111:end.
1B2
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
F1 CMD10 selection
loop;1100:out1;1101:out2;1110:out3; 1111:end.
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
F1 CMD11 selection
loop;1100:out1;1101:out2;1110:out3; 1111:end.
1B3
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
F1 CMD12 selection
loop;1100:out1;1101:out2;1110:out3; 1111:end.
0000:CMD1;0001:CMD2;0010:CMD3;0011:CMD4;010
0:CMD5;0101:CMD6:or;0110:CMD7;0111:CMD8;1000:
CMD9;1001:CMD10;1010:CMD11;1011:CMD12
loop with delay to location selection
00: keep
01: 0
10: 1
1B4
output mux1 initial state setting
output mux2 initial state setting
3493
3494
3495
3496
3497
11: none
00: keep
01: 0
10: 1
11: none
00: keep
01: 0
10: 1
output mux3 initial state setting
11: none
0: no reset stack memory
1: reset stack memory.
3498
interrupt reset stack memory enable
1B5
3499
3500
3501
3502
3503
3504
Reserved
Reserved
Reserved
Reserved
Reserved
00: aio0
01: aio1
10: aio2
11: aio3
1B6
aio0-3 input selection load 1
3505
Datasheet
25-Feb-2021
Revision 3.12
323 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
3506
3507
3508
3509
3510
3511
3512
"F1 input selection load 1" bit = 0:
Matrix input select: 000000: Matrix in0; ~ 111111: Matrix
in63
"F1 input selection load 1" bit = 1:
ACMP Vref select:
1B6
ACMP4_F Vref selection load 1
000000: 32 mV ~ 111110: 2.016 V/step = 32 mV;
111111: External Vref
00: aio0
01: aio1
10: aio2
11: aio3
aio0-3 input selection load 2
ACMP4_F Vref selection load 2
aio4-7 input selection load 3
ACMP4_F Vref selection load 3
aio4-7 input selection load 4
ACMP4_F Vref selection load 4
3513
3514
3515
3516
3517
3518
3519
3520
"F1 input selection load 1" bit = 0:
Matrix input select: 000000: Matrix in0; ~ 111111: Matrix
in63
"F1 input selection load 1" bit = 1:
ACMP Vref select:
000000: 32 mV ~ 111110: 2.016 V/step = 32 mV;
111111: External Vref
1B7
00: aio4
01: aio5
10: aio6
11: aio7
3521
3522
3523
3524
3525
3526
3527
3528
"F1 input selection load 1" bit = 0:
Matrix input select: 000000: Matrix in0; ~ 111111: Matrix
in63
"F1 input selection load 1" bit = 1:
ACMP Vref select:
000000: 32 mV ~ 111110: 2.016 V/step = 32 mV;
111111: External Vref
1B8
00: aio4
01: aio5
10: aio6
11: aio7
3529
3530
3531
3532
3533
3534
3535
"F1 input selection load 1" bit = 0:
Matrix input select: 000000: Matrix in0; ~ 111111: Matrix
in63
"F1 input selection load 1" bit = 1:
ACMP Vref select:
1B9
000000: 32 mV ~ 111110: 2.016 V/step = 32 mV;
111111: External VRE
0: from matrix
1: from ACMP4_F
3536
3537
3538
F1 input selection load 1
F1 input selection load 2
F1 input selection load 3
0: from matrix
1: from ACMP4_F
1BA
0: from matrix
1: from ACMP4_F
0: from matrix
1: from ACMP4_F
3539
3540
F1 input selection load 4
Reserved
Datasheet
25-Feb-2021
Revision 3.12
324 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
3541
3542
000: OSC2
001: OSC2/4
010: OSC1
011: OSC1/8
100: OSC1/64
101: OSC0
1BA
delay clock source selection
3543
110: OSC0/8
111: OSC0/64
3544
3545
3546
3547
3548
3549
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568
3569
3570
3571
3572
3573
3574
3575
1BB
1BC
1BD
1BE
F1 delay data
Data[7:0]
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
F1 CMD1 selection
F1 CMD2 selection
F1 CMD3 selection
F1 CMD4 selection
F1 CMD5 selection
F1 CMD6 selection
loop;1100:out1;1101:out2;1110:out3; 1111:end.
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
loop;1100:out1;1101:out2;1110:out3; 1111:end.
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
loop;1100:out1;1101:out2;1110:out3; 1111:end.
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
loop;1100:out1;1101:out2;1110:out3; 1111:end.
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
loop;1100:out1;1101:out2;1110:out3; 1111:end.
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
loop;1100:out1;1101:out2;1110:out3; 1111:end.
Datasheet
25-Feb-2021
Revision 3.12
325 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
3576
3577
3578
3579
3580
3581
3582
3583
3584
3585
3586
3587
3588
3589
3590
3591
3592
3593
3594
3595
3596
3597
3598
3599
3600
3601
3602
3603
3604
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
1BF
F1 CMD7 selection
loop;1100:out1;1101:out2;1110:out3; 1111:end.
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
1BF
1C0
F1 CMD8 selection
loop;1100:out1;1101:out2;1110:out3; 1111:end.
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
F1 CMD9 selection
loop;1100:out1;1101:out2;1110:out3; 1111:end.
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
F1 CMD10 selection
F1 CMD11 selection
loop;1100:out1;1101:out2;1110:out3; 1111:end.
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
loop;1100:out1;1101:out2;1110:out3; 1111:end.
1C1
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
F1 CMD12 selection
loop with delay to location selection
loop;1100:out1;1101:out2;1110:out3; 1111:end.
0000:CMD1;0001:CMD2;0010:CMD3;0011:CMD4;010
0:CMD5;0101:CMD6:or;0110:CMD7;0111:CMD8;1000:
CMD9;1001:CMD10;1010:CMD11;1011:CMD12
00: keep
01: 0
10: 1
1C2
output mux1 initial state setting
output mux2 initial state setting
3605
3606
3607
11: none
00: keep
01: 0
10: 1
11: none
Datasheet
25-Feb-2021
Revision 3.12
326 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1C3
1C3
3608
00: keep
01: 0
10: 1
output mux3 initial state setting
3609
11: none
0: no reset stack memory
1: reset stack memory
3610
interrupt reset stack memory enable
3611
3612
3613
3614
3615
3616
Reserved
Reserved
Reserved
Reserved
Reserved
00: aio0
01: aio1
10: aio2
11: aio3
aio0-3 input selection load 1
ACMP4_F Vref selection load 1
aio0-3 input selection load 2
ACMP4_F Vref selection load 2
aio4-7 input selection load 3
ACMP4_F Vref selection load 3
3617
3618
3619
3620
3621
3622
3623
3624
"F1 input selection load 1" bit = 0:
Matrix input select: 000000: Matrix in0; ~ 111111: Matrix
in63
"F1 input selection load 1" bit = 1:
ACMP Vref select:
000000: 32 mV ~ 111110: 2.016 V/step = 32 mV;
111111: External Vref
1C4
1C5
1C6
00: aio0
01: aio1
10: aio2
11: aio3
3625
3626
3627
3628
3629
3630
3631
3632
"F1 input selection load 1" bit = 0:
Matrix input select: 000000: Matrix in0; ~ 111111: Matrix
in63
"F1 input selection load 1" bit = 1:
ACMP Vref select:
000000: 32 mV ~ 111110: 2.016 V/step = 32 mV;
111111: External Vref
00: aio4
01: aio5
10: aio6
11: aio7
3633
3634
3635
3636
3637
3638
3639
"F1 input selection load 1" bit = 0:
Matrix input select: 000000: Matrix in0; ~ 111111: Matrix
in63
"F1 input selection load 1" bit = 1:
ACMP Vref select:
000000: 32 mV ~ 111110: 2.016 V/step = 32 mV;
111111: External Vref
Datasheet
25-Feb-2021
Revision 3.12
327 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
3640
00: aio4
01: aio5
10: aio6
11: aio7
aio4-7 input selection load 4
3641
3642
3643
3644
3645
3646
3647
"F1 input selection load 1" bit = 0:
Matrix input select: 000000: Matrix in0; ~ 111111: Matrix
in63
"F1 input selection load 1" bit = 1:
ACMP Vref select:
000000: 32 mV ~ 111110: 2.016 V/step = 32 mV;
111111: External Vref
1C7
ACMP4_F Vref selection load 4
0: from matrix
1: from ACMP4_F
3648
3649
3650
3651
F1 input selection load 1
F1 input selection load 2
F1 input selection load 3
1C8
0: from matrix
1: from ACMP4_F
0: from matrix
1: from ACMP4_F
0: from matrix
1: from ACMP4_F
F1 input selection load 4
Reserved
3652
3653
3654
000: OSC2
001: OSC2/4
010: OSC1
1C8
011: OSC1/8
100: OSC1/64
101: OSC0
delay clock source selection
3655
110: OSC0/8
111: OSC0/64
3656
3657
3658
3659
3660
3661
3662
3663
3664
3665
3666
3667
3668
3669
3670
3671
1C9
F1 delay data
Data[7:0]
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
F1 CMD1 selection
F1 CMD2 selection
loop;1100:out1;1101:out2;1110:out3; 1111:end.
1CA
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
loop;1100:out1;1101:out2;1110:out3; 1111:end.
Datasheet
25-Feb-2021
Revision 3.12
328 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
3672
3673
3674
3675
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685
3686
3687
3688
3689
3690
3691
3692
3693
3694
3695
3696
3697
3698
3699
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710
3711
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
F1 CMD3 selection
loop;1100:out1;1101:out2;1110:out3; 1111:end.
1CB
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
F1 CMD4 selection
F1 CMD5 selection
F1 CMD6 selection
F1 CMD7 selection
F1 CMD8 selection
F1 CMD9 selection
F1 CMD10 selection
F1 CMD11 selection
F1 CMD12 selection
loop;1100:out1;1101:out2;1110:out3; 1111:end.
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
1CC
1CC
loop;1100:out1;1101:out2;1110:out3; 1111:end.
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
loop;1100:out1;1101:out2;1110:out3; 1111:end.
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
loop;1100:out1;1101:out2;1110:out3; 1111:end.
1CD
1CE
1CF
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
loop;1100:out1;1101:out2;1110:out3; 1111:end.
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
loop;1100:out1;1101:out2;1110:out3; 1111:end.
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
loop;1100:out1;1101:out2;1110:out3; 1111:end.
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
loop;1100:out1;1101:out2;1110:out3; 1111:end.
0000:load1;0001:load2;0010:load3;0011:load4;0100:a
nd;0101:or;0110:xor;0111:inv;1000:push0;1001:pop;10
10:delay;1011:delay with
loop;1100:out1;1101:out2;1110:out3; 1111:end.
Datasheet
25-Feb-2021
Revision 3.12
329 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
3712
3713
3714
3715
3716
0000: CMD1; 0001: CMD2; 0010: CMD3; 0011: CMD4;
0100: CMD5; 0101: CMD6 or; 0110: CMD7; 0111:
CMD8; 1000: CMD9; 1001: CMD10; 1010: CMD11;
1011: CMD12
loop with delay to location selection
00: keep
01: 0
10: 1
1D0
output mux1 initial state setting
output mux2 initial state setting
3717
3718
3719
3720
3721
11: none
00: keep
01: 0
10: 1
11: none
00: keep
01: 0
10: 1
1D1
1D1
output mux3 initial state setting
11: none
0: no reset stack memory
1: reset stack memory
3722
interrupt reset stack memory enable
3723
3724
3725
3726
3727
Reserved
Reserved
Reserved
Reserved
Reserved
Datasheet
25-Feb-2021
Revision 3.12
330 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
3728
3729
000: none
001: setting 0
010: setting 1
011: setting 2
100: setting 3
101: none
F1 state0 setting selection
3730
110: none
111: none
3731
3732
000: none
1D2
001: setting 0
010: setting 1
011: setting 2
100: setting 3
101: none
110: none
111: none
F1 state 1 setting selection
F1 state 2 setting selection
F1 state 3 setting selection
F1 state 4 setting selection
3733
3734
3735
000: none
001: setting 0
010: setting 1
011: setting 2
100: setting 3
101: none
110: none
111: none
3736
3737
3738
000: none
001: setting 0
010: setting 1
011: setting 2
100: setting 3
101: none
110: none
111: none
1D3
3739
3740
3741
000: none
001: setting 0
010: setting 1
011: setting 2
100: setting 3
101: none
3742
110: none
111: none
Datasheet
25-Feb-2021
Revision 3.12
331 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
1D3
3743
3744
000: none
001: setting 0
010: setting 1
011: setting 2
100: setting 3
101: none
F1 state 5 setting selection
3745
110: none
111: none
3746
3747
000: none
001: setting 0
010: setting 1
011: setting 2
100: setting 3
101: none
F1 state 6 setting selection
1D4
3748
110: none
111: none
3749
3750
000: none
001: setting 0
010: setting 1
011: setting 2
100: setting 3
101: none
F1 state 7 setting selection
3751
110: none
111: none
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
3752
3753
000: none
001: setting 0
010: setting 1
011: setting 2
100: setting 3
101: none
F1 state 8 setting selection
3754
110: none
111: none
3755
3756
000: none
1D5
001: setting 0
010: setting 1
011: setting 2
100: setting 3
101: none
110: none
111: none
F1 state 9 setting selection
F1 state 10 setting selection
F1 state 11 setting selection
3757
3758
3759
000: none
001: setting 0
010: setting 1
011: setting 2
100: setting 3
101: none
110: none
111: none
3760
3761
3762
000: none
1D6
001: setting 0
010: setting 1
011: setting 2
100: setting 3
101: none
3763
110: none
111: none.
3764
3765
3766
3767
3768
3769
3770
3771
3772
3773
3774
3775
Reserved
Reserved
1D6
1D7
register interrupt
Reserved
1: interrupt active
Matrix Input 0
Matrix Input 1
Matrix Input 2
Matrix Input 3
Matrix Input 4
Matrix Input 5
Matrix Input 6
Matrix Input 7
GND
GPIO0 Digital Input
GPIO1 Digital Input
GPIO2 Digital Input
GPI0 Digital Input
GPI1 Digital Input
GPIO3 Digital Input
GPIO4 Digital Input
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
3776
3777
3778
3779
3780
3781
3782
3783
3784
3785
3786
3787
3788
3789
3790
3791
3792
3793
3794
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804
3805
3806
3807
3808
3809
3810
3811
3812
3813
3814
3815
Matrix Input 8
Matrix Input 9
Matrix Input 10
Matrix Input 11
Matrix Input 12
Matrix Input 13
Matrix Input 14
Matrix Input 15
Matrix Input 16
Matrix Input 17
Matrix Input 18
Matrix Input 19
Matrix Input 20
Matrix Input 21
Matrix Input 22
Matrix Input 23
Matrix Input 24
Matrix Input 25
Matrix Input 26
Matrix Input 27
Matrix Input 28
Matrix Input 29
Matrix Input 30
Matrix Input 31
Matrix Input 32
Matrix Input 33
Matrix Input 34
Matrix Input 35
Matrix Input 36
Matrix Input 37
Matrix Input 38
Matrix Input 39
Matrix Input 40
Matrix Input 41
Matrix Input 42
Matrix Input 43
Matrix Input 44
Matrix Input 45
Matrix Input 46
Matrix Input 47
LUT2_0/DFF0 Output
LUT2_1/PGen Output
LUT3_0/DFF1 Output
LUT3_1/DFF2 Output
1D8
LUT3_2/DFF3 Output
LUT3_3/DFF4 Output
LUT3_4/CNT_DLY1(8bit) Output
LUT3_5/CNT_DLY2(8bit) Output
LUT3_6/CNT_DLY3(8bit) Output
LUT3_7/CNT_DLY4(8bit) Output
LUT4_0/CNT_DLY0(16bit) Output
LUT3_8/Pipe Delay Output0/Ripple CNT Output0
Pipe Delay Output1/Ripple CNT Output1
Internal OSC1 2.048 MHz Output
Internal OSC0 2.048 kHz Output
Internal OSC2 25 MHz Output
Filter0/Edge Detect0 Output/Ripple CNT Output2
Programmable Delay with Edge Detector Output
F(1) Function Output0
1D9
F(1) Function Output1
1DA
F(1) Function Output2
DM0_0 Block Output0
DM0_0 Block Output1
DM0_0 Block Output2
GPI2/SDA Digital Input or I2C_virtual_0 Input
GPI3/SCL Digital Input or I2C_virtual_1 Input
I2C_virtual_2 Input
I2C_virtual_3 Input
I2C_virtual_4 Input
I2C_virtual_5 Input
I2C_virtual_6 Input
I2C_virtual_7 Input
1DB
1DB
DM0_1 Macrocell Output0
DM0_1 Macrocell Output1
DM0_1 Macrocell Output2
ASM Connection Matrix Output RAM 0
ASM Connection Matrix Output RAM 1
ASM Connection Matrix Output RAM 2
ASM Connection Matrix Output RAM 0
GPIO5 Digital Input
1DC
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
3816
3817
3818
3819
3820
3821
3822
3823
3824
3825
3826
3827
3828
3829
3830
3831
3832
3833
3834
3835
3836
3837
3838
3839
3840
3841
3842
3843
3844
3845
3846
3847
3848
3849
3850
3851
3852
3853
3854
3855
Matrix Input 48
Matrix Input 49
Matrix Input 50
Matrix Input 51
Matrix Input 52
Matrix Input 53
Matrix Input 54
Matrix Input 55
Matrix Input 56
Matrix Input 57
Matrix Input 58
Matrix Input 59
Matrix Input 60
Matrix Input 61
Matrix Input 62
Matrix Input 63
GPIO6 Digital Input
GPIO7 Digital Input
GPIO8 Digital Input
GPI4 Digital Input
GPI5 Digital Input
GPI6 Digital Input
GPI7 Digital Input
GPIO9 Digital Input
ACMP0H Output
ACMP1H Output
ACMP2L Output
1DD
ACMP3L output
1DE
1DF
1E0
1E1
GPIO10 Digital Input
GPIO11 Digital Input
nRST_core (POR) as matrix input
VDD
CNT0 (16bits) Counted Value
CNT2 (8bits) Counted Value
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
3856
3857
3858
3859
3860
3861
3862
3863
3864
3865
3866
3867
3868
3869
3870
3871
3872
3873
3874
3875
3876
3877
3878
3879
3880
1E2
CNT4 (8bits) Counted Value
1E3
ASM state read back
1E4
GPIO4 I2C output expander data
GPIO4 I2C output expander select
GPIO5 I2C output expander data
GPIO5 I2C output expander select
GPIO6 I2C output expander data
GPIO6 I2C output expander select
GPIO7 I2C output expander data
GPIO7 I2C output expander select
0: GPIO4 output from matrix
1: GPIO4 output is register
3881
3882
3883
3884
3885
3886
3887
0: GPIO5 output from matrix
1: GPIO5 output is register
1E5
0: GPIO6 output from matrix
1: GPIO6 output is register
0: GPIO7 output from matrix
1: GPIO7 output is register
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
3888
ACMP gain divider select:
00: 1x
ACMP0_H Gain divider
01: 0.5x
10: 0.33x
3889
11: Reserved
3890
3891
3892
3893
3894
3895
3896
1E6
ACMP Vref select:
000000: 32 mV ~
111110: 2.016 V/step = 32 mV
111111: External Vref
ACMP0_H Vref
ACMP gain divider select:
00: 1x
1E7
1E7
ACMP1_H Gain divider
ACMP1_H Vref
01: 0.5x
10: 0.33x
11: Reserved
3897
3898
3899
3900
3901
3902
3903
3904
ACMP Vref select:
000000: 32 mV ~
111110: 2.016 V/step = 32 mV
111111: External Vref
ACMP gain divider select:
00: 1x
ACMP2_L Gain divider
ACMP2_L Vref
01: 0.5x
10: 0.33x
11: Reserved
3905
3906
3907
3908
3909
3910
3911
3912
1E8
ACMP Vref select:
000000: 32 mV ~
111110: 2.016 V/step = 32 mV
111111: External Vref
ACMP gain divider select:
00: 1x
ACMP3_L Gain divider
ACMP3_L Vref
01: 0.5x
10: 0.33x
11: Reserved
3913
3914
3915
3916
3917
3918
3919
1E9
ACMP Vref select:
000000: 32 mV ~
111110: 2.016 V/step = 32 mV
111111: External Vref
Datasheet
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Revision 3.12
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© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
3920
3921
3922
3923
3924
3925
3926
3927
3928
3929
3930
3931
3932
3933
3934
3935
3936
3937
3938
3939
3940
3941
3942
3943
3944
3945
3946
3947
3948
3949
3950
3951
3952
3953
3954
3955
3956
3957
3958
3959
1EA
REG_LUT4_0_D0[15:0]
Data[15:0]
1EB
1EC
1ED
1EE
REG_LUT3_4_D1[7:0]
REG_LUT3_5_D2[7:0]
REG_LUT3_6_D3[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
3960
3961
3962
3963
3964
3965
3966
3967
3968
3969
3970
3971
3972
3973
3974
3975
3976
3977
3978
3979
3980
3981
3982
3983
3984
3985
3986
3987
3988
3989
3990
3991
3992
3993
3994
3995
3996
3997
3998
3999
1EF
REG_LUT3_7_D4[7:0]
Data[7:0]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1F0
1F1
1F2
1F3
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
4000
4001
4002
4003
4004
4005
4006
4007
4008
4009
4010
4011
4012
4013
4014
4015
4016
4017
4018
4019
4020
4021
4022
4023
4024
4025
4026
4027
4028
4029
4030
4031
4032
4033
4034
4035
4036
4037
4038
4039
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1F4
1F5
1F6
1F7
1F8
Reserved
Reserved
Reserved
Reserved
Reserved
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
4040
4041
4042
4043
4044
4045
4046
4047
4048
4049
4050
4051
4052
4053
4054
4055
4056
4057
4058
4059
4060
4061
4062
4063
8-bit Pattern ID Byte 0 (From NVM):
ID[23:16]
1F9
1FA
Reserved
1FB
Reserved
I2C reset bit with reloading NVM into Data 0: Keep existing condition
4064
register (soft reset)
1:Resetexecution
IO Latching Enable During I2C Write Inter
face
-
0: Disable
1: Enable
4065
4066
4067
Reserved
0: Disable
1: Enable
1FС
protect mode enable
4068
4069
4070
4071
Reserved
register protection mode bit 0
register protection mode bit 1
register protection mode bit 2
000: all open read/write (mode 0); 001: partly lock read
(mode1);010:partlylockread2(mode2);011:partlylock
read2/write (mode 3);100: all lock read (mode 4); 101:
all lock write (mode 5); 110: all lock read/write (mode 6).
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Table 56: Register Map (Continued)
Address
Register Bit
Signal Function
Register Bit Definition
Byte
4072
4073
4074
4075
4076
4077
4078
4079
4080
4081
4082
4083
1: mask
0: overwrite
1FD
I2C write mask bits
I2C slave address
0: I2C operation enable; matrix in 34(35) select I2C_vir
tual_0(1) Input
-
I2C operation disable bit
1FE
4084
1: I2C operation disable; matrix in 34(35) select GPI2(3)
digital input
4085
4086
Reserved
Reserved
0: from Register
1: from Pin
4087
slave address selection
4088
4089
4090
4091
4092
4093
4094
4095
1FF
Reserved
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
22 Package Top Marking System Definition
PPPPPPPPP
Part Code
NNNNNNNNNN
Lot Code
PIN1 Identifier
Date Code
YYWW
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
23 Package Information
STQFN 32L 4 mm x 4 mm 0.4P Package
JEDEC MO-220, Variation WECE
Marking View
BTM View
Side view
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
23.1 STQFN HANDLING
Be sure to handle STQFN package only in a clean, ESD-safe environment. Tweezers or vacuum pick-up tools are suitable for
handling. Do not handle STQFN package with fingers as this can contaminate the package pins and interface with solder reflow.
23.2 SOLDERING INFORMATION
Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 3.85 mm3 (nominal). More
information can be found at www.jedec.org.
24 Ordering Information
Part Number
Type
SLG46880V
32-Pin STQFN
SLG46880VTR
SLG46881V
32-Pin STQFN - Tape and Reel (5k units)
32-Pin STQFN
SLG46881VTR
32-Pin STQFN - Tape and Reel (5k units)
24.1 TAPE AND REEL SPECIFICATIONS
Max Units
per Reel per Box
Leader (min)
Length
Trailer (min)
Nominal
Package Size
(mm)
Reel &
Hub Size
(mm)
Tape
Width Pitch
(mm) (mm)
Part
Package # of
Length
Type
Pins
Pockets
Pockets
(mm)
(mm)
STQFN 32L
4 mm x4mm 32
4 x 4 x 0.55
5,000
10,000
330/100
42
336
42
336
12
8
0.4P Green
24.2 CARRIER TAPE DRAWING AND DIMENSIONS
PocketBTMPocketBTM Pocket Index Hole Pocket Index Hole
Index Hole Index Hole
to Tape
Edge
to Pocket Tape Width
Center
(mm)
Length
(mm)
Width
(mm)
Depth
(mm)
Pitch
(mm)
Pitch
(mm)
Diameter
(mm)
Package
Type
(mm)
(mm)
A0
B0
K0
P0
P1
D0
E
F
W
STQFN 32L
4 mm x4mm
0.4P Green
4.25
4.25
0.75
4
8
1.5
1.75
5.5
12
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Refer to EIA-481 specification
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
25 Layout Guidelines
Units: µm
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Glossary
A
ACK
Acknowledge bit
ACMP
ACMPH
ACMPL
ASM
Analog Comparator
Analog Comparator High Speed
Analog Comparator Low Power
Asynchronous State Machine
B
BG
Bandgap
C
CLK
CMO
CNT
Clock
Connection matrix output
Counter
D
DFF
DLY
DM
D Flip-Flop
Delay
Dynamic Memory
E
EC
Electrical Characteristics
Erase Enable
ERSE
ERSR
ESD
EV
Erase Register
Electrostatic discharge
End Value
F
FSM
Finite State Machine
G
GPI
General Purpose Input
GPIO
GPO
General Purpose Input/Output
General Purpose Output
I
IN
IO
Input
Input/Output
L
LPF
LSB
LUT
LV
Low Pass Filter
Least Significant Bit
Look Up Table
Low Voltage
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
LWD
Loop with Delay
M
MSB
MTP
MUX
Most Significant Bit
Multiple-Time-Programmable
Multiplexer
N
NPR
nRST
NVM
Non-Volatile Memory Read/Write/Erase Protection
Reset
Non-Volatile Memory
O
OD
OE
Open-Drain
Output Enable
Oscillator
OSC
OUT
Output
P
PD
Power-down
PGen
POR
PP
Pattern Generator
Power-On Reset
Push-Pull
PRL
PWR
P DLY
Protect Lock Bit
Power
Programmable Delay
R
RPR
Register Read/Write Protection
Register Read/Write Protection Bit
Register Protection Read/Write/Erase Lock
Read/Write
RPRB
RPRL
R/W
S
SCL
SDA
SLA
SMT
SV
I2C Clock Input
I2C Data Input/Output
Slave Address
With Schmitt Trigger
nSET Value
T
TS
Temperature Sensor
Voltage Reference
V
Vref
Datasheet
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GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
W
WOSMT
WPB
Without Schmitt Trigger
Write Protect Bit
WPR
Write Protection Register
Write Protect Enable
Wake and Sleep Controller
WPRE
WS
Datasheet
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SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Revision History
Revision
Date
Description
Corrected registers [425:420]
Updated ACMP0H Block Diagram
Added description for Internal 100 µA current source
Added note in EC table
3.12
25-Feb-2021
Corrected Figure TS Output vs Temperature
Updated section CNT/DLY/FSM Timing Diagrams
Added note for CNTs
Corrected I2C Byte Write Bit Masking subsection
Fixed typos
Corrected Reset Command Timing figure
Updated PIN Block Diagrams
Updated Typical Counter/Delay Offset
Corrected EC of the I2C Pins Table
Fixed typos
3.11
11-Dec-2019
Corrected Edge Detection Mode Timing Diagram
Corrected Delayed Edge Detection Mode Timing Diagram
Updated subsection Reading Counter Data via I2C
3.10
3.9
3-Jul-2019
4-Jun-2019
Corrected registers [731:730], [737:736], [3831:3768], [4084]
Updated Analog Temperature sensor section
Updated according to Dialog’s Writing Guideline
Fixed typos
Corrected Oscillators names
Updated Ordering Information
Changed I2C Serial Communications Macrocell section structure
Corrected 2-bit LUT1 or PGen Figure
Updated registers [535], [3765:3764]
Added new subsection Electrostatic Discharge Ratings
Fixed typos
3.8
3.7
16-Apr-2019
1-Mar-2019
Removed information about SCL and SDA Pins’ Schmitt Trigger
Corrected Deglitch Filter/Edge Detector Block Diagram
Updated Analog Temperature Sensor Structure Diagram
Corrected register definitions
Fixed typos
Added subsection f(1) Performance
Added subsection IO Pins Performance
Added ACMPs’ hysteresis information
Added additional information about VDD2 to IO Pins section
Added table Typical Delay Estimated for F(1)
Added graph for ACMP Input Current Source
Updated Input Current Source Spec
Added section ACMP Typical Performance
Updated Analog Temperature Sensor Electrical Spec
Added sections Oscillators Power-On Delay and Oscillators Accuracy
Corrected Absolute Maximum Ratings
Updated Typical Delay table
3.6
4-Jan-2019
Updated DM Block Diagrams
Updated ACMP section
Fixed typos
Fixed typos
3.5
14-Sept-2018
Updated Analog Temperature Sensor Structure Diagram
Updated Example of I2C Byte Write Bit Masking
Updated EC for SLG46881
Fixed typos
3.4
3.3
20-Aug-2018
9-Aug-2018
Fixed typos
Datasheet
25-Feb-2021
Revision 3.12
351 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Revision
Date
Description
Updated TS Structure Diagram
Added STQFN Handling section
Updated ACMP Electrical Spec
Fixed formatting
3.2
27-Jul-2018
Updated RPULL in Electrical Spec
3.1
3.0
30-Apr-2018
18-Apr-2018
Updated TS Electrical Spec
Final version
Datasheet
25-Feb-2021
Revision 3.12
352 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
SLG46880/81
GreenPAK Programmable Mixed-Signal Matrix with Asynchronous
State Machine and Dual Supply
Status Definitions
Revision Datasheet Status
Product Status
Definition
1.<n>
Target
Development
This datasheet contains the design specifications for product development.
Specifications may change in any manner without notice.
2.<n>
Preliminary
Qualification
Production
This datasheet contains the specifications and preliminary characterization
data for products in pre-production. Specifications may be changed at any
time without notice in order to improve the design.
3.<n>
4.<n>
Final
This datasheet contains the final specifications for products in volume
production. The specifications may be changed at any time in order to
improve the design, manufacturing and supply. Major specification changes
are communicated via Customer Product Notifications. Datasheet changes
are communicated via www.dialog-semiconductor.com.
Obsolete
Archived
This datasheet contains the specifications for discontinued products. The
information is provided for reference only.
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Datasheet
25-Feb-2021
Revision 3.12
353 of 353
CFR0011-120-00
© 2021 Dialog Semiconductor
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