SLG7NT4192VTR [DIALOG]
Power Good Generator Logic;
| 型号： | SLG7NT4192VTR |
| 厂家： | 
Dialog Semiconductor |
| 描述： | Power Good Generator Logic |
| 文件： | 总11页 (文件大小：1093K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SLG7NT4192
GreenPAK 3™
Power Good Generator Logic
General Description
Pin Configuration
Silego SLG7NT4192 is a low power and small form
device. The SoC is housed in a 2mm x 3mm TQFN
package which is optimal for using with small
devices.
Features
18 17
16
20
19
V3.3A_DSW_PWRGD
RSMRST_PWRGD_N
VBAT_MON
• Low Power Consumption
• Pb-Free / RoHS Compliant
• Halogen-Free
VDD
BC_ACOK_DSW
DPWROK
1
2
3
4
15
14
PWRBTN_EC_IN
V3
BC_ACOK_EC_IN
• TQFN-20 Package
13
5
6
7
SUS_VR_PWRGD
V1
12
SYS_PWROK
GND
Output Summary
11
10
PWRBTN_N
8
9
• 9 Outputs – Open Drain
TQFN-20
TOP VIEW
Silego Technology, Inc.
SLG7NT4192_DS_r011
SLG7NT4192_GP_r002
Preliminary
Rev 0.11
Revised May 27, 2013
SLG7NT4192
Power Good Generator Logic
Block Diagram
SLG7NT4192_DS_r011
Preliminary
Page 2
SLG7NT4192
Power Good Generator Logic
Pin Configuration
Pin #
1
2
3
4
5
6
7
Pin Name
Type
Pin Description
VDD
BC_ACOK_DSW
DPWROK
BC_ACOK_EC_IN
SUS_VR_PWRGD
V1
PWR Supply Voltage
Input
Digital in without Schmitt trigger
Output Open Drain
Output Open Drain
Input
Input
Input
Digital in without Schmitt trigger
Analog Input
Digital in without Schmitt trigger
PWRBTN_N
8
9
VCCST_PWRGD
PWRBTN_DSW_N
V2
GND
SYS_PWROK
V3
PWRBTN_EC_IN
VBAT_MON
RSMRST_PWRGD_N
V3.3A_DSW_PWRGD
ALL_SYS_PWRGD
DDR_VCCIO_PWRGD
PCH_PWROK
Output Open Drain
Output Open Drain
10
11
12
13
14
15
16
17
18
19
20
Input
GND
Analog Input
Ground
Output Open Drain
Input Analog input
Output Open Drain
Input Analog input
Output Open Drain
Input
Digital in without Schmitt trigger
Output Open Drain
Input
Digital in without Schmitt trigger
Output Open Drain
Ordering Information
Part Number
SLG7NT4192V
SLG7NT4192VTR
Package Type
V=TQFN-20
TQFN-20 – Tape and Reel (3k units)
SLG7NT4192_DS_r011
Preliminary
Page 3
SLG7NT4192
Power Good Generator Logic
Absolute Maximum Conditions
Parameter
VHIGH to GND
Min.
-0.3
-0.3
-1.0
-65
--
Max.
7
Unit
V
Voltage at input pins
Current at input pin
Storage temperature range
Junction temperature
7
V
1.0
150
150
mA
°C
°C
Electrical Characteristics
(@ 25°C, unless otherwise stated)
Symbol Parameter
Condition/Note
Min. Typ. Max. Unit
VDD
TA
IQ
Supply Voltage
3.135
-40
--
3.3
25
85
--
3.465
85
V
°C
μA
--
Operating Temperature
Quiescent Current
Static inputs and outputs
Logic Input
--
VIH
VIL
IIH
HIGH-Level Input Voltage
LOW-Level Input Voltage
HIGH-Level Input Current
LOW-Level Input Current
1.8
--
--
Logic Input
--
1.3
1.0
1.0
V
Logic Input Pins; VIN =3.3V
Logic Input Pins; VIN =0V
-1.0
-1.0
--
μA
μA
IIL
--
Open Drain,
IOL = 3 mA, 1X Driver
VOL
IOL
LOW-Level Output Voltage
LOW-Level Output Current
--
0.080 0.15
V
Open Drain, VOL = 0.4 V, 1X Driver
7.3
12
--
--
mA
Maximal Voltage Applied to
any PIN in High-Impedance
State
VO
--
VDD
V
Analog Comparator Reference
Voltage
VACMP0
VACMP1
VACMP2
VACMP3
VHYST
Including ACMP0 voltage reference
Including ACMP1 voltage reference
Including ACMP2 voltage reference
Including ACMP3 voltage reference
ACMP0, ACMP1, ACMP2, ACMP3
ACMP0, ACMP1, ACMP2, ACMP3
T.B.D. 950 T.B.D. mV
T.B.D. 950 T.B.D. mV
T.B.D. 950 T.B.D. mV
T.B.D. 950 T.B.D. mV
Analog Comparator Reference
Voltage
Analog Comparator Reference
Voltage
Analog Comparator Reference
Voltage
Analog Comparator Hysteresis
Voltage
T.B.D.
--
50
±5
T.B.D. mV
-- mV
Analog Comparator Offset
Voltage
VOFFSET
TDLY0
Delay0 Time
T.B.D. 2.5
T.B.D. ms
SLG7NT4192_DS_r011
Preliminary
Page 4
SLG7NT4192
Power Good Generator Logic
TDLY1
TDLY4
TDLY5
TSU
Delay1 Time
Delay4 Time
Delay5 Time
Start up Time
T.B.D. 2.5
T.B.D. ms
T.B.D. ms
T.B.D. ms
T.B.D.
T.B.D.
--
2
10
T.B.D.
--
ms
SLG7NT4192_DS_r011
Preliminary
Page 5
SLG7NT4192
Power Good Generator Logic
SLG7NT4192 Functionality Waveforms
Inputs:
D0 – Pin #15
D1 – Pin #17
D2 – Pin #7
D3 – Pin #6
D4 – Pin #10
D5 – Pin #13
D6 – Pin #2
Outputs:
(VBAT_MON)
(V3.3A_DSW_PWRGD)
(PWRBTN_N)
(V1)
(V2)
(V3)
(BC_ACOK_DSW)
D7 – Pin #3
(DPWROK) with external 5kΩ pull-up resistor
D8 – Pin #16 (RSMRST_PWRGD_N) with external 5kΩ pull-up resistor
D9 – Pin #14 (PWRBTN_EC_IN) with external 5kΩ pull-up resistor
D10 – Pin #9 (PWRBTN_DSW_N) with external 5kΩ pull-up resistor
D11 – Pin #8 (VCCST_PWRGD) with external 5kΩ pull-up resistor
D12 – Pin #18 (ALL_SYS_PWRGD) with external 5kΩ pull-up resistor
D13 – Pin #12 (SYS_PWROK) with external 5kΩ pull-up resistor
D14 – Pin #20 (PCH_PWROK) with external 5kΩ pull-up resistor
D15 – Pin #4 (BC_ACOK_EC_IN) with external 5kΩ pull-up resistor
1. Chip functionality (Pin5 (SUS_VR_PWRGD), Pin19 (DDR_VCCIO_PWRGD) are always HIGH)
SLG7NT4192_DS_r011
Preliminary
Page 6
SLG7NT4192
Power Good Generator Logic
Package Top Marking
Datasheet
Revision
0.11
Programming
Code Number
Part Code
Revision
Date
02
05/27/2013
SLG7NT4192_DS_r011
Preliminary
Page 7
SLG7NT4192
Power Good Generator Logic
Package Drawing and Dimensions
20 Lead TQFN Package
JEDEC MO-220, Variation WCEE
SLG7NT4192_DS_r011
Preliminary
Page 8
SLG7NT4192
Power Good Generator Logic
Tape and Reel Specification
Max Units
Trailer A
Leader B
Pocket (mm)
Nominal
Package
Size (mm)
Reel &
Hub Size
(mm)
# of
Pins
Package Type
Length
Length
per reel per box
Pockets
Pockets
Width
Pitch
(mm)
(mm)
TQFN 20L
2x3mm 0.4P
Green
20
2x3x0.75
3000
3000
178/60
42
168
42
168
8
4
Carrier Tape Drawing and Dimensions
Pocket
Index Hole Index Hole
Pocket
BTM Width
(mm)
Pocket
Depth
(mm)
Index Hole
Pocket
Pitch
(mm)
Index Hole
Diameter
(mm)
BTM
Length
(mm)
to Tape
Edge
to Pocket Tape Width
Center
(mm)
Pitch
(mm)
(mm)
Package
Type
(mm)
A0
B0
K0
P0
P1
D0
E
F
W
TQFN 20L
2x3mm
2.25
3.3
1.1
4
4
1.55
1.75
3.5
8
0.4P Green
Refer to EIA-481 Specifications
Recommended Reflow Soldering Profile
Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 4.50 mm3 (nominal).
More information can be found at www.jedec.org.
SLG7NT4192_DS_r011
Preliminary
Page 9
SLG7NT4192
Power Good Generator Logic
Datasheet Revision History
Date
05/20/2013
05/27/2013
Version
0.1
0.11
Change
New design
Updated design
SLG7NT4192_DS_r011
Preliminary
Page 10
SLG7NT4192
Power Good Generator Logic
Silego Website & Support
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Datasheets and errata, application notes and example designs, user guides, and hardware support documents and the
latest software releases are available at the Silego website or can be requested directly at info@silego.com.
For specific GreenPAK design or applications questions and support please send email requests to
GreenPAK@silego.com
Users of Silego products can receive assistance through several channels:
Contact Your Local Sales Representative
Customers can contact their local sales representative or field application engineer (FAE) for support. Local sales offices
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THIS PRODUCT HAS BEEN DESIGNED AND QUALIFIED FOR THE CONSUMER MARKET. APPLICATIONS OR
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TECHNOLOGY DOES NOT ASSUME ANY LIABILITY ARISING OUT OF SUCH APPLICATIONS OR USES OF ITS
PRODUCTS. SILEGO TECHNOLOGY RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN, FUNCTIONS AND
RELIABILITY WITHOUT NOTICE.
SLG7NT4192_DS_r011
Preliminary
Page 11
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