AP63356QZV-7 [DIODES]
AUTOMOTIVE-COMPLIANT, 32V, 3.5A LOW IQ SYNCHRONOUS BUCK CONVERTER;
| 型号： | AP63356QZV-7 |
| 厂家： | 
DIODES INCORPORATED |
| 描述： | AUTOMOTIVE-COMPLIANT, 32V, 3.5A LOW IQ SYNCHRONOUS BUCK CONVERTER |
| 文件： | 总28页 (文件大小：1657K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AP63356Q/AP63357Q
Green
AUTOMOTIVE-COMPLIANT, 32V, 3.5A LOW IQ SYNCHRONOUS BUCK CONVERTER
Description
Pin Assignments
The AP63356Q/AP63357Q is an automotive-compliant, 3.5A,
synchronous buck converter with a wide input voltage range of 3.8V to
32V. The device fully integrates a 74mΩ high-side power MOSFET
and a 40mΩ low-side power MOSFET to provide high-efficiency step-
down DC-DC conversion.
(Top View)
SW
The AP63356Q/AP63357Q device is easily used by minimizing the
external component count due to its adoption of peak current mode
control along with its integrated loop compensation network.
9
VIN
1
8
GND
The AP63356Q/AP63357Q design is optimized for Electromagnetic
Interference (EMI) reduction. The device has a proprietary gate driver
scheme to resist switching node ringing without sacrificing MOSFET
turn-on and turn-off times, which reduces high-frequency radiated EMI
noise caused by MOSFET switching. AP63356Q/AP63357Q also
EN
FB
2
3
4
7
6
5
NC
BST
PG
features Frequency Spread Spectrum (FSS) with
a switching
COMP
frequency jitter of ±6%, which reduces EMI by not allowing emitted
energy to stay in any one frequency for a significant period of time.
V-DFN3020-13/SWP
(Type A1)
The device is available in a 3mm × 2mm, V-DFN3020-13/SWP (Type
A1), package with wettable flanks.
Applications
Features
12V Automotive Power Systems
Automotive Infotainment
Automotive Instrument Clusters
Automotive Body Electronics and Lighting
Automotive Telematics
AEC-Q100 Qualified with the Following Results
.
.
.
Device Temperature Grade 1: -40°C to +125°C TA Range
Device HBM ESD Classification Level H2
Device CDM ESD Classification Level C5
VIN: 3.8V to 32V
3.5A Continuous Output Current
0.8V ± 1% Reference Voltage
22µA Low Quiescent Current (Pulse Frequency Modulation)
450kHz Switching Frequency
Advanced Driver Assistance Systems
Pulse Width Modulation (PWM) Regardless of Output Load
.
AP63356Q
Supports Pulse Frequency Modulation (PFM)
.
.
AP63357Q
Up to 86% Efficiency at 5mA Light Load
Proprietary Gate Driver Design for Best EMI Reduction
Frequency Spread Spectrum (FSS) to Reduce EMI
Low-Dropout (LDO) Mode
Power Good Indicator with 5MΩ Internal Pull-up
Precision Enable Threshold to Adjust UVLO
Protection Circuitry
.
.
.
.
Undervoltage Lockout (UVLO)
Output Undervoltage Protection (UVP)
Cycle-by-Cycle Peak Current Limit
Thermal Shutdown
Lead-Free Finish; Fully RoHS Compliant (Notes 1 & 2)
Halogen and Antimony Free. “Green” Device (Note 3)
The AP63356Q and AP63357Q are suitable for automotive
applications requiring specific change control; these parts
are AEC-Q100 qualified, PPAP capable, and manufactured in
IATF 16949 certified facilities.
https://www.diodes.com/quality/product-definitions/
Notes:
1. EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant. All applicable RoHS exemptions applied.
2. See https://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green" and
Lead-free.
3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and
<1000ppm antimony compounds.
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AP63356Q/AP63357Q
Document number: DS41948 Rev. 1 - 2
AP63356Q/AP63357Q
Typical Application Circuit
INPUT
VIN
EN
BST
SW
C3
100nF
L
6.8µH
OUTPUT
VOUT
5V
C4
47pF
R1
157kΩ
AP63356Q
AP63357Q
C1
10µF
C2
2 x 22µF
FB
R2
30kΩ
PG
COMP
GND
Figure 1. Typical Application Circuit
VIN = 12V, VOUT = 5V, L = 6.8μH
VIN = 24V, VOUT = 5V, L = 6.8μH
VIN = 12V, VOUT = 3.3V, L = 4.7μH
VIN = 24V, VOUT = 3.3V, L = 4.7μH
100
90
80
70
60
50
40
30
20
10
0
0.001
0.010
0.100
1.000
10.000
IOUT (A)
Figure 2. Efficiency vs. Output Current, AP63356Q
VIN = 12V, VOUT = 5V, L = 6.8μH
VIN = 24V, VOUT = 5V, L = 6.8μH
VIN = 12V, VOUT = 3.3V, L = 4.7μH
VIN = 24V, VOUT = 3.3V, L = 4.7μH
100
90
80
70
60
50
40
30
20
10
0
0.001
0.010
0.100
1.000
10.000
IOUT (A)
Figure 3. Efficiency vs. Output Current, AP63357Q
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AP63356Q/AP63357Q
Document number: DS41948 Rev. 1 - 2
AP63356Q/AP63357Q
Pin Descriptions
Pin Name Pin Number
Function
Power Input. VIN supplies the power to the IC as well as the step-down converter power MOSFETs. Drive VIN with a
3.8V to 32V power source. Bypass VIN to GND with a suitably large capacitor to eliminate noise due to the switching
of the IC. See Input Capacitor section for more details.
VIN
EN
1
2
Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the regulator and low to
turn it off. Connect to VIN or leave floating for automatic startup. The EN has a precision threshold of 1.18V for
programing the UVLO. See Enable section for more details.
Feedback sensing terminal for the output voltage. Connect this pin to the resistive divider of the output.
See Setting the Output Voltage section for more details.
FB
COMP
PG
3
4
5
6
Compensation. Connect the COMP pin to GND to use internal loop compensation. Connect an external RC network
to the COMP pin to adjust the loop response. See External Loop Compensation Design section for more details.
Power-Good. Open-drain power-good output with internal 5M pull-up resistor that is pulled to GND when the output
voltage is out of its regulation limits or during soft-start.
High-Side Gate Drive Boost Input. BST supplies the drive for the high-side N-Channel power MOSFET. A 100nF
capacitor is recommended from BST to SW to power the high-side driver.
No Connect. There is no internal connection to this pin. The pin can be tied to any other pin or left floating.
Power Ground.
BST
NC
7
8
GND
Power Switching Output. SW is the switching node that supplies power to the output. Connect the output LC filter
from SW to the output load.
SW
9
Functional Block Diagram
I1
1.5μA
I2
4μA
VCC
VCC
Regulator
1
VIN
20kΩ
EN
2
+
–
ON
Internal
Reference
0.8V
1.18V
+
CSA
-
RT = 0.2V/A
6
9
BST
SW
+
-
OCP
UVP
Ref
Q1
Q2
SE = 0.83V/T
FB
3
+
+
-
450kHz
Oscillator
UVP
0.64V
0.8V
OSC
VSUM
-
+
+
+
-
Control
Logic
VCC
PWM
Comparator
Internal SS
Error
Amplifier
5MΩ
GND
Detection
Thermal
Shutdown
TSD
OSC
5
8
PG
18kΩ
7.6nF
COMP
4
GND
Figure 4. Functional Block Diagram
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AP63356Q/AP63357Q
Document number: DS41948 Rev. 1 - 2
AP63356Q/AP63357Q
Absolute Maximum Ratings (Note 4) (@ TA = +25°C, unless otherwise specified.)
Symbol
Parameter
Rating
Unit
-0.3 to +35.0 (DC)
-0.3 to +40.0 (400ms)
-0.3 to +35.0
VIN
Supply Pin Voltage
V
VEN
VFB
Enable/UVLO Pin Voltage
Feedback Pin Voltage
V
V
V
V
V
-0.3 to +6.0
Compensation Pin Voltage
Power-Good Pin Voltage
Bootstrap Pin Voltage
-0.3 to +6.0
VCOMP
VPG
-0.3 to +6.0
VBST
VSW - 0.3 to VSW + 6.0
-0.3 to VIN + 0.3 (DC)
-2.5 to VIN + 2.0 (20ns)
-65 to +150
VSW
Switch Pin Voltage
V
TSTG
TJ
Storage Temperature
Junction Temperature
Lead Temperature
°C
°C
°C
+170
+260
TL
ESD Susceptibility (Note 5)
HBM
CDM
Human Body Model
Charged Device Model
±2000
±1000
V
V
Notes:
4. Stresses greater than the Absolute Maximum Ratings specified above can cause permanent damage to the device. These are stress ratings only;
functional operation of the device at these or any other conditions exceeding those indicated in this specification is not implied. Device reliability can
be affected by exposure to absolute maximum rating conditions for extended periods of time.
5. Semiconductor devices are ESD sensitive and can be damaged by exposure to ESD events. Suitable ESD precautions should be taken when
handling and transporting these devices.
Thermal Resistance (Note 6)
Symbol
Parameter
Rating
V-DFN3020-13/SWP
(Type A1)
Unit
θJA
θJC
Junction to Ambient
Junction to Case
25
5
°C/W
V-DFN3020-13/SWP
(Type A1)
°C/W
Note:
6. Test condition for V-DFN3020-13/SWP (Type A1): Device mounted on FR-4 substrate, four-layer PC board, 2oz copper, with minimum recommended
pad layout.
Recommended Operating Conditions (Note 7) (@ TA = +25°C, unless otherwise specified.)
Symbol
VIN
Parameter
Min
3.8
0.8
-40
Max
32
Unit
V
Supply Voltage
Output Voltage
VOUT
TA
VIN
+125
V
Operating Ambient Temperature
Operating Junction Temperature
°C
TJ
-40
+150
°C
Note:
7. The device function is not guaranteed outside of the recommended operating conditions.
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AP63356Q/AP63357Q
Document number: DS41948 Rev. 1 - 2
AP63356Q/AP63357Q
Electrical Characteristics (@ TJ = +25°C, VIN = 12V, unless otherwise specified. Min/Max limits apply across the recommended
operating junction temperature range, -40°C to +150°C, and input voltage range, 3.8V to 32V, unless otherwise specified.)
Symbol
Parameter
Shutdown Supply Current
Conditions
VEN = 0V
Min
Typ
Max
Unit
ISHDN
—
0.6
—
μA
AP63356Q:
—
—
258
22
—
—
μA
μA
VEN = Floating, VFB = 1.0V
Quiescent Supply Current
IQ
AP63357Q:
VEN = Floating, VFB = 1.0V
POR
UVLO
VIN Power-on Reset Rising Threshold
—
—
—
3.3
—
3.5
3.08
74
3.6
—
V
V
VIN Undervoltage Lockout Falling Threshold
High-Side Power MOSFET On-Resistance (Note 8)
RDS(ON)1
—
—
mΩ
Low-Side Power MOSFET On-Resistance (Note 8)
HS Peak Current Limit (Note 8)
LS Valley Current Limit (Note 8)
Oscillator Frequency
—
—
4.0
3.2
400
—
40
5.0
—
6.0
5.2
500
—
mΩ
A
RDS(ON)2
IPEAK_LIMIT
IVALLEY_LIMIT
fSW
From Drain to Source
From Source to Drain
4.2
A
CCM
450
100
0.800
1.18
1.08
5.5
kHz
ns
V
tON_MIN
VFB
Minimum On-Time
—
Feedback Voltage
CCM
0.792
1.15
1.02
—
0.808
1.21
1.14
—
VEN_H
EN Logic High Threshold
—
V
EN Logic Low Threshold
—
V
VEN_L
μA
μA
ms
°C
°C
VEN = 1.5V
EN Input Current
IEN
VEN = 1V
1.0
—
1.5
2.0
—
Soft-Start Time
—
—
—
4
tSS
TSD
THys
Thermal Shutdown (Note 8)
Thermal Shutdown Hysteresis (Note 8)
—
+170
+25
—
—
—
Note:
8. Compliance to the datasheet limits is assured by one or more methods: production test, characterization, and/or design.
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AP63356Q/AP63357Q
Document number: DS41948 Rev. 1 - 2
AP63356Q/AP63357Q
Typical Performance Characteristics (AP63356Q/AP63357Q @ TA = +25°C, VIN = 12V, VOUT = 5V, BOM = Table 1,
unless otherwise specified.)
20
High-Side MOSFET
Low-Side MOSFET
18
16
14
12
10
8
110
100
90
80
70
60
50
40
30
20
10
6
4
2
0
-50 -25
0
25
50
75
100 125 150
-50
-25
0
25
50
75
100 125 150
Temperature (°C)
Temperature (°C)
Figure 5. Power MOSFET RDS(ON) vs. Temperature
Figure 6. ISHDN vs. Temperature
VIN Rising POR
VIN Falling UVLO
3.8
3.7
3.6
3.5
3.4
3.3
3.2
3.1
3.0
2.9
2.8
-50
-25
0
25
50
75
100 125 150
Temperature (°C)
Figure 7. VIN Power-On Reset and UVLO vs. Temperature
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AP63356Q/AP63357Q
Document number: DS41948 Rev. 1 - 2
AP63356Q/AP63357Q
Typical Performance Characteristics (AP63356Q/AP63357Q @ TA = +25°C, VIN = 12V, VOUT = 5V, BOM = Table 1,
unless otherwise specified.) (continued)
VEN (5V/div)
VEN (5V/div)
VOUT (2V/div)
IL (2A/div)
VOUT (2V/div)
IL (2A/div)
VPG (5V/div)
VPG (5V/div)
2ms/div
100μs/div
Figure 8. Startup using EN, IOUT = 3.5A
Figure 9. Shutdown using EN, IOUT = 3.5A
VOUT (2V/div)
VOUT (2V/div)
IL (5A/div)
IL (5A/div)
VPG (5V/div)
VPG (5V/div)
5ms/div
5ms/div
Figure 10. Output Short Protection, IOUT = 3.5A
Figure 11. Output Short Recovery, IOUT = 3.5A
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AP63356Q/AP63357Q
Document number: DS41948 Rev. 1 - 2
AP63356Q/AP63357Q
Typical Performance Characteristics (AP63356Q @ TA = +25°C, VIN = 12V, VOUT = 5V, BOM = Table 1, unless otherwise
specified.)
VOUT = 5V, L = 6.8μH
VOUT = 3.3V, L = 4.7μH
VOUT = 5V, L = 6.8μH
VOUT = 3.3V, L = 4.7μH
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
0.001
0.010
0.100
1.000
10.000
0.001
0.010
0.100
IOUT (A)
1.000
10.000
IOUT (A)
Figure 12. Efficiency vs. Output Current, VIN = 12V
Figure 13. Efficiency vs. Output Current, VIN = 24V
IOUT = 0A
IOUT = 0.5A
IOUT = 3.5A
IOUT = 1.5A
VIN = 12V
VIN = 24V
5.10
5.08
5.06
5.04
5.02
5.00
4.98
4.96
4.94
4.92
4.90
IOUT = 2.5A
5.00
4.98
4.96
4.94
4.92
4.90
4.88
4.86
4.84
4.82
4.80
4
8
12
16
20
24
28
32
36
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VIN (V)
IOUT (A)
Figure 14. Line Regulation
Figure 15. Load Regulation
0.810
0.808
0.806
0.804
0.802
0.800
0.798
0.796
0.794
0.792
0.790
320
315
310
305
300
295
290
285
280
275
270
-50 -25
0
25
50
75 100 125 150
-50 -25
0
25
50
75
100 125 150
Temperature (°C)
Temperature (°C)
Figure 16. Feedback Voltage vs. Temperature
Figure 17. IQ vs. Temperature
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AP63356Q/AP63357Q
Document number: DS41948 Rev. 1 - 2
AP63356Q/AP63357Q
Typical Performance Characteristics (AP63356Q @ TA = +25°C, VIN = 12V, VOUT = 5V, BOM = Table 1, unless otherwise
specified.) (continued)
480
475
470
465
460
455
450
445
440
435
430
500
450
400
350
300
250
200
150
100
50
0
-50 -25
0
25
50
75
100 125 150
0.001
0.010
0.100
1.000
10.000
Temperature (°C)
IOUT (A)
Figure 18. fsw vs. Temperature, IOUT = 0A
Figure 19. fsw vs. Load
VOUT (50mV/div)
VOUT (50mV/div)
IL (2A/div)
IL (2A/div)
VSW (10V/div)
VSW (10V/div)
5μs/div
5μs/div
Figure 20. Output Voltage Ripple, IOUT = 50mA
Figure 21. Output Voltage Ripple, IOUT = 3.5A
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AP63356Q/AP63357Q
Document number: DS41948 Rev. 1 - 2
AP63356Q/AP63357Q
Typical Performance Characteristics (AP63356Q @ TA = +25°C, VIN = 12V, VOUT = 5V, BOM = Table 1, unless otherwise
specified.) (continued)
VOUT (500mV/div)
VOUT (200mV/div)
IOUT (500mA/div)
IOUT (1A/div)
1ms/div
1ms/div
Figure 22. Load Transient, IOUT = 50mA to 500mA to 50mA
Figure 23. Load Transient, IOUT = 2.5A to 3.5A to 2.5A
VOUT (1V/div)
IOUT (2A/div)
1ms/div
Figure 24. Load Transient, IOUT = 50mA to 3.5A to 50mA
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AP63356Q/AP63357Q
Document number: DS41948 Rev. 1 - 2
AP63356Q/AP63357Q
Typical Performance Characteristics (AP63357Q @ TA = +25°C, VIN = 12V, VOUT = 5V, BOM = Table 1, unless otherwise
specified.)
VOUT = 5V, L = 6.8μH
VOUT = 3.3V, L = 4.7μH
VOUT = 5V, L = 6.8μH
VOUT = 3.3V, L = 4.7μH
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
0.001
0.010
0.100
IOUT (A)
1.000
10.000
0.001
0.010
0.100
IOUT (A)
1.000
10.000
Figure 25. Efficiency vs. Output Current, VIN = 12V
Figure 26. Efficiency vs. Output Current, VIN = 24V
IOUT = 0A
IOUT = 0.5A
IOUT = 3.5A
IOUT = 1.5A
VIN = 12V
VIN = 24V
5.04
5.02
5.00
4.98
4.96
4.94
4.92
4.90
4.88
4.86
4.84
IOUT = 2.5A
4.98
4.96
4.94
4.92
4.90
4.88
4.86
4.84
4.82
4.80
4.78
4
8
12
16
20
24
28
32
36
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VIN (V)
IOUT (A)
Figure 27. Line Regulation
Figure 28. Load Regulation
0.810
0.808
0.806
0.804
0.802
0.800
0.798
0.796
0.794
0.792
0.790
65
60
55
50
45
40
35
30
25
20
15
-50 -25
0
25
50
75 100 125 150
-50
-25
0
25
50
75
100 125 150
Temperature (°C)
Temperature (°C)
Figure 29. Feedback Voltage vs. Temperature
Figure 30. IQ vs. Temperature
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AP63356Q/AP63357Q
Document number: DS41948 Rev. 1 - 2
AP63356Q/AP63357Q
Typical Performance Characteristics (AP63357Q @ TA = +25°C, VIN = 12V, VOUT = 5V, BOM = Table 1, unless otherwise
specified.) (continued)
500
VOUT (50mV/div)
IL (1A/div)
450
400
350
300
250
200
150
100
50
VSW (10V/div)
0
0.001
0.010
0.100
1.000
10.000
IOUT (A)
50μs/div
Figure 32. Output Voltage Ripple, IOUT = 50mA
Figure 31. fsw vs. Load
VOUT (50mV/div)
VOUT (500mV/div)
IL (2A/div)
VSW (10V/div)
IOUT (500mA/div)
1ms/div
5μs/div
Figure 33. Output Voltage Ripple, IOUT = 3.5A
Figure 34. Load Transient, IOUT = 50mA to 500mA to 50mA
VOUT (1V/div)
VOUT (500mV/div)
IOUT (2A/div)
IOUT (1A/div)
1ms/div
1ms/div
Figure 35. Load Transient, IOUT = 2.5A to 3.5A to 2.5A
Figure 36. Load Transient, IOUT = 50mA to 3.5A to 50mA
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AP63356Q/AP63357Q
Document number: DS41948 Rev. 1 - 2
AP63356Q/AP63357Q
Application Information
1
Pulse Width Modulation (PWM) Operation
The AP63356Q/AP63357Q device is an automotive-compliant, 3.8V-to-32V input, 3.5A output, EMI friendly, fully integrated synchronous buck
converter. Refer to the block diagram in Figure 4. The device employs fixed-frequency peak current mode control. The internal 450kHz clock’s
rising edge initiates turning on the integrated high-side power MOSFET, Q1, for each cycle. When Q1 is on, the inductor current rises linearly and
the device charges the output capacitor. The current across Q1 is sensed and converted to a voltage with a ratio of RT via the CSA block. The
CSA output is combined with an internal slope compensation, SE, resulting in VSUM. When VSUM rises higher than the COMP node, the device
turns off Q1 and turns on the low-side power MOSFET, Q2. The inductor current decreases when Q2 is on. On the rising edge of next clock cycle,
Q2 turns off and Q1 turns on. This sequence repeats every clock cycle.
The error amplifier generates the COMP voltage by comparing the voltage on the FB pin with an internal 0.8V reference. An increase in load
current causes the feedback voltage to drop. The error amplifier thus raises the COMP voltage until the average inductor current matches the
increased load current. This feedback loop regulates the output voltage. The internal slope compensation circuitry prevents subharmonic
oscillation when the duty cycle is greater than 50% for peak current mode control.
The peak current mode control, integrated loop compensation network, and built-in 4ms soft-start time simplifies the AP63356Q/AP63357Q
footprint as well as minimizes the external component count.
In order to provide a small output ripple during light load conditions, the AP63356Q operates in PWM regardless of output load.
2
Pulse Frequency Modulation (PFM) Operation
In heavy load conditions, the AP63357Q operates in forced PWM mode. As the load current decreases, the internal COMP node voltage also
decreases. At a certain limit, if the load current is low enough, the COMP node voltage is clamped and is prevented from decreasing any further.
The voltage at which COMP is clamped corresponds to the 700mA PFM peak inductor current limit. As the load current approaches zero, the
AP63357Q enters PFM mode to increase the converter power efficiency at light load conditions. When the inductor current decreases to 0mA,
zero cross detection circuitry on the low-side power MOSFET, Q2, forces it off. The buck converter does not sink current from the output when the
output load is light and while the device is in PFM. Because the AP63357Q works in PFM during light load conditions, it can achieve power
efficiency of up to 86% at a 5mA load condition.
The quiescent current of AP63357Q is 22μA typical under a no-load, non-switching condition.
3
Enable
When disabled, the device shutdown supply current is only 1μA. When applying a voltage greater than the EN logic high threshold (typical 1.18V,
rising), the AP63356Q/AP63357Q enables all functions and the device initiates the soft-start phase. The EN pin is a high-voltage pin and can be
directly connected to VIN to automatically start up the device as VIN increases. An internal 1.5µA pull-up current source connected from the
internal LDO-regulated VCC to the EN pin guarantees that if EN is left floating, the device still automatically enables once the voltage reaches the
EN logic high threshold. The AP63356Q/AP63357Q has a built-in 4ms soft-start time to prevent output voltage overshoot and inrush current.
When the EN voltage falls below its logic low threshold (typical 1.08V, falling), the internal SS voltage discharges to ground and device operation
disables.
The EN pin can also be used to program the undervoltage lockout thresholds. See Undervoltage Lockout (UVLO) section for more details.
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Application Information (continued)
4
Electromagnetic Interference (EMI) Reduction with Ringing-Free Switching Node and Frequency Spread Spectrum (FSS)
In some applications, the system must meet EMI standards. In relation to high frequency radiation EMI noise, the switching node’s (SW’s) ringing
amplitude is especially critical. To dampen high frequency radiated EMI noise, the AP63356Q/AP63357Q device implements a proprietary, multi-
level gate driver scheme that achieves a ringing-free switching node without sacrificing the switching node’s rise and fall slew rates as well as the
converter’s power efficiency.
To further improve EMI reduction, the AP663356/AP63357Q device also implements FSS with a switching frequency jitter of ±6%. FSS reduces
conducted and radiated interference at a particular frequency by spreading the switching noise over a wider frequency band and by not allowing
emitted energy to stay in any one frequency for a significant period of time.
5
Adjusting Undervoltage Lockout (UVLO)
Undervoltage lockout is implemented to prevent the IC from insufficient input voltages. The AP63356Q/AP63357Q device has a UVLO comparator
that monitors the input voltage and the internal bandgap reference. The AP63356Q/AP63357Q disables if the input voltage falls below 3.08V. In
this UVLO event, both the high-side and low-side power MOSFETs turn off.
Some applications may desire higher VIN UVLO threshold voltages than is provided by the default setup. A 4µA hysteresis pull-up current source
on the EN pin along with an external resistive divider (R3 and R4) configures the VIN UVLO threshold voltages as shown in Figure 37.
I1
1.5μA
I2
4μA
VIN
R3
20kΩ
EN
+
–
ON
1.18V
R4
Figure 37. Programming UVLO
The resistive divider resistor values are calculated by:
ퟎ. ퟗퟏퟓ ∙ 퐕퐎퐍 − 퐕퐎퐅퐅
퐑ퟑ =
Eq. 1
Eq. 2
ퟒ. ퟏퟐퟕ훍퐀
ퟏ. ퟎퟖ ∙ 퐑ퟑ
퐑ퟒ =
퐕퐎퐅퐅 − ퟏ. ퟎퟖ퐕 + ퟓ. ퟓ훍퐀 ∙ 퐑ퟑ
Where:
VON is the rising edge VIN voltage to enable the regulator and is greater than 3.6V
VOFF is the falling edge VIN voltage to disable the regulator and is greater than 3.18V
6
Power-Good (PG) Indicator and Output Undervoltage Protection (UVP)
The PG pin of AP63356Q/AP63357Q is an open-drain output that is actively held low during the soft-start period until the output voltage reaches
85% of its target value. If the output voltage decreases below its target value by 20%, UVP triggers and PG pulls low until the output returns to its
set value. The PG rising edge transition is delayed by 1.5ms while the PG falling edge is delayed by 220μs to prevent false triggering.
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Application Information (continued)
7
Overcurrent Protection (OCP)
The AP63356Q/AP63357Q has cycle-by-cycle peak current limit protection by sensing the current through the internal high-side power MOSFET,
Q1. While Q1 is on, the internal sensing circuitry monitors its conduction current. Once the current through Q1 exceeds the peak current limit, Q1
immediately turns off. If Q1 consistently hits the peak current limit for 512 cycles, the buck converter enters hiccup mode and shuts down. After
8192 cycles of down time, the buck converter restarts powering up. Hiccup mode reduces the power dissipation in the overcurrent condition.
8
Thermal Shutdown (TSD)
If the junction temperature of the device reaches the thermal shutdown limit of +170°C, the AP63356Q/AP63357Q shuts down both its high-side
and low-side power MOSFETs. When the junction temperature reduces to the required level (+145°C typical), the device initiates a normal power-
up cycle with soft-start.
9
Power Derating Characteristics
To prevent the regulator from exceeding the maximum recommended operating junction temperature, some thermal analysis is required. The
regulator’s temperature rise is given by:
퐓퐑퐈퐒퐄 = 퐏퐃 ∙ (훉퐉퐀)
Eq. 3
Where:
PD is the power dissipated by the regulator
θJA is the thermal resistance from the junction of the die to the ambient temperature
The junction temperature, TJ, is given by:
퐓 = 퐓퐀 + 퐓퐑퐈퐒퐄
퐉
Eq. 4
Where:
TA is the ambient temperature of the environment
For the V-DFN3020-13/SWP (Type A1) package, the θJA is 25°C/W. The actual junction temperature should not exceed the maximum
recommended operating junction temperature of +150°C when considering the thermal design. Figure 38 shows a typical derating curve versus
ambient temperature.
VOUT = 1.2V
VOUT = 2.5V
VOUT = 1.5V
VOUT = 3.3V
VOUT = 1.8V
VOUT = 5V
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
20
40
60
80
100
120
140
160
Ambient Temperature (°C)
Figure 38. Output Current Derating Curve vs. Ambient Temperature, VIN = 12V
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Application Information (continued)
10
Setting the Output Voltage
The AP63356Q/AP63357Q has adjustable output voltages starting from 0.8V using an external resistive divider. An optional external capacitor, C4
in Figure 1, of 10pF to 220pF improves the transient response. The resistor values of the feedback network are selected based on a design trade-
off between efficiency and output voltage accuracy. There is less current consumption in the feedback network for high resistor values, which
improves efficiency at light loads. However, values too high cause the device to be more susceptible to noise affecting its output voltage accuracy.
R1 can be determined by the following equation:
퐕퐎퐔퐓
Eq. 5
퐑ퟏ = 퐑ퟐ ∙ ꢀ
− ퟏꢁ
ퟎ. ퟖ퐕
Table 1 shows a list of recommended component selections for common AP63356Q/AP63357Q output voltages referencing Figure 39 using
internal compensation.
INPUT
VIN
EN
BST
SW
C3
L
OUTPUT
C4
R1
R2
AP63356Q
AP63357Q
C1
C2
FB
PG
COMP
GND
Figure 39. Typical Application Circuit Using Internal Compensation
Table 1. Recommended Components Selections Using Internal Compensation
AP63356Q/AP63357Q
Output Voltage
R1
(kΩ)
15
R2
(kΩ)
30
L
C1
(µF)
10
C2
(µF)
C3
(nF)
100
100
100
100
100
100
100
C4
(pF)
OPEN
OPEN
OPEN
27
(V)
1.2
1.5
1.8
2.5
3.3
5.0
12.0
(µH)
2.2
2.2
2.2
3.3
4.7
6.8
10.0
3 x 22
2 x 22
2 x 22
2 x 22
2 x 22
2 x 22
4 x 22
27
30
10
39
30
10
62
30
10
91
30
10
33
157
422
30
10
47
30
10
OPEN
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Application Information (continued)
10
Setting the Output Voltage (continued)
Table 2 shows a list of recommended component selections for common AP63356Q/AP63357Q output voltages referencing Figure 40 using
external compensation.
INPUT
VIN
EN
BST
SW
C3
L
OUTPUT
C4
R1
R2
AP63356Q
AP63357Q
C1
C2
FB
PG
COMP
R5
C5
GND
C6
Figure 40. Typical Application Circuit Using External Compensation
Table 2. Recommended Components Selections Using External Compensation
AP63356Q/AP63357Q
R1
(k)
62
R2
(k)
30
R5
(k)
27
Output Voltage
(V)
L
(µH)
C1
(µF)
C2
(µF)
C3
(nF)
C4
(pF)
C5
(nF)
C6
(pF)
2.5
3.3
3.3
4.7
10
10
10
10
2 x 22
3 x 22
3 x 22
4 x 22
100
100
100
100
OPEN
OPEN
OPEN
OPEN
3.9
3.3
3.3
6.8
OPEN
OPEN
OPEN
OPEN
91
30
27
5.0
157
422
30
6.8
38
12.0
30
10.0
47
11
Inductor
Calculating the inductor value is a critical factor in designing a buck converter. For most designs, the following equation can be used to calculate
the inductor value:
(
)
퐕퐎퐔퐓 ∙ 퐕퐈퐍 − 퐕퐎퐔퐓
Eq. 6
퐋 =
퐕퐈퐍 ∙ ∆퐈퐋 ∙ 퐟퐬퐰
Where:
∆IL is the inductor current ripple
fSW is the buck converter switching frequency
For AP63356Q/AP63357Q, choose ∆IL to be 30% to 50% of the maximum load current of 3.5A.
The inductor peak current is calculated by:
∆퐈퐋
Eq. 7
퐈퐋
= 퐈퐋퐎퐀퐃 +
퐏퐄퐀퐊
ퟐ
Peak current determines the required saturation current rating, which influences the size of the inductor. Saturating the inductor decreases the
converter efficiency while increasing the temperatures of the inductor and the internal power MOSFETs. Therefore, choosing an inductor with the
appropriate saturation current rating is important. For most applications, it is recommended to select an inductor of approximately 2.2µH to 10µH
with a DC current rating of at least 35% higher than the maximum load current. For highest efficiency, the inductor’s DC resistance should be less
than 30mΩ. Use a larger inductance for improved efficiency under light load conditions.
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Application Information (continued)
12
Input Capacitor
The input capacitor reduces both the surge current drawn from the input supply as well as the switching noise from the device. The input capacitor
must sustain the ripple current produced during the on-time of Q1. It must have a low ESR to minimize power dissipation due to the RMS input
current.
The RMS current rating of the input capacitor is a critical parameter and must be higher than the RMS input current. As a rule of thumb, select an
input capacitor with an RMS current rating greater than half of the maximum load current.
Due to large dI/dt through the input capacitor, electrolytic or ceramic capacitors with low ESR should be used. If using a tantalum capacitor, it must
be surge protected or else capacitor failure could occur. Using a ceramic capacitor of 10µF or greater is sufficient for most applications.
13
Output Capacitor
The output capacitor keeps the output voltage ripple small, ensures feedback loop stability, and reduces both the overshoots and undershoots of
the output voltage during load transients. During the first few microseconds of an increasing load transient, the converter recognizes the change
from steady-state and enters 100% duty cycle to supply more current to the load. However, the inductor limits the change to increasing current
depending on its inductance. Therefore, the output capacitor supplies the difference in current to the load during this time. Likewise, during the first
few microseconds of a decreasing load transient, the converter recognizes the change from steady-state and sets the on-time to minimum to
reduce the current supplied to the load. However, the inductor limits the change in decreasing current as well. Therefore, the output capacitor
absorbs the excess current from the inductor during this time.
The effective output capacitance, COUT, requirements can be calculated from the equations below.
The ESR of the output capacitor dominates the output voltage ripple. The amount of ripple can be calculated by:
ퟏ
Eq. 8
퐕퐎퐔퐓퐑퐢퐩퐩퐥퐞 = ∆퐈퐋 ∙ ꢀ퐄퐒퐑 +
ꢁ
ퟖ ∙ 퐟퐬퐰 ∙ 퐂퐎퐔퐓
An output capacitor with large capacitance and low ESR is the best option. For most applications, a 22µF to 68µF ceramic capacitor is sufficient.
To meet the load transient requirements, the calculated COUT should satisfy the following inequality:
퐋 ∙ 퐈퐓ퟐ퐫퐚퐧퐬
퐋 ∙ 퐈퐓ퟐ퐫퐚퐧퐬
Eq. 9
퐂퐎퐔퐓 > 퐦퐚퐱 ꢂ
,
ꢃ
(
)
∆퐕퐔퐧퐝퐞퐫퐬퐡퐨퐨퐭 ∙ 퐕퐈퐍 − 퐕퐎퐔퐓
∆퐕퐎퐯퐞퐫퐬퐡퐨퐨퐭 ∙ 퐕퐎퐔퐓
Where:
ITrans is the load transient
∆VOvershoot is the maximum output overshoot voltage
∆VUndershoot is the maximum output undershoot voltage
14
Bootstrap Capacitor and Low-Dropout (LDO) Operation
To ensure proper operation, a ceramic capacitor must be connected between the BST and SW pins to supply the drive voltage for the high-side
power MOSFET. A 100nF ceramic capacitor is sufficient. If the bootstrap capacitor voltage falls below 2.3V, the boot undervoltage protection
circuit turns Q2 on for 220ns to refresh the bootstrap capacitor and raise its voltage back above 2.85V. The bootstrap capacitor voltage threshold
is always maintained to ensure enough driving capability for Q1. This operation may arise during long periods of no switching such as in PFM with
light load conditions. Another event that requires the refreshing of the bootstrap capacitor is when the input voltage drops close to the output
voltage. Under this condition, the regulator enters low-dropout mode by holding Q1 on for multiple clock cycles. To prevent the bootstrap capacitor
from discharging, Q2 is forced to refresh. The effective duty cycle is approximately 100% so that it acts as an LDO to maintain the output voltage
regulation.
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Application Information (continued)
15
External Loop Compensation Design
When the COMP pin is not connected to GND, the COMP pin is active for external loop compensation. The regulator uses a constant frequency,
peak current mode control architecture to achieve a fast loop response. The inductor is not considered as a state variable since its peak current is
constant. Thus, the system becomes a single-order system. For loop stabilization, it is simpler to design a Type II compensator for current mode
control than it is to design a Type III compensator for voltage mode control. Peak current mode control has an inherent input voltage feed-forward
function to achieve good line regulation. Figure 41 shows the small signal model of the synchronous buck regulator.
L
ꢀo
ꢆin
ꢆL
ꢈꢉꢊꢄ
1:D
Rc
+
–
ꢀin
ꢂꢃꢄ
RT
Ro
COUT
ꢄ
Fm
K(S)
Ti(S)
SE
+
He(S)
Tv(S)
ꢀcomp
-Av(S)
Figure 41. Small Signal Model of Buck Regulator
Where:
Tv(S) is the voltage loop
Ti(S) is the current loop
K(S) is the voltage sense gain
-Av(S) is the feedback compensation gain
He(S) is the current sampling function
Fm is the PWM comparator gain
Vin is the DC input voltage
D is the duty cycle
Rc is the ESR of the output capacitor, COUT
Ro is the output load resistancevin is the AC small-signal input voltage
ꢀin is the AC small-signal input current
̂
̂
̂
d is the modulation of the duty cycle
̂
ꢀL is the AC small signal of the inductor current
vo is the AC small signal of output voltage
vcomp is the AC small signal voltage of the compensation network
̂
̂
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Application Information (continued)
15
External Loop Compensation Design (continued)
VOUT
R1
SE
+
C4
VSUM
+
–
RT
FB
–
+
PWM
Comparator
gm
VREF
Error
Amplifier
R5
C5
R2
C6
Figure 42. Type ll Compensator
Figure 42 shows a Type ll compensator and its transfer function is expressed in the following equation:
퐒
퐒
ꢄퟏ + 훚 ꢅ ꢄퟏ + 훚
ꢅ
ꢁ
퐠퐦 ∙ 퐑ퟓ
) (
퐳ퟏ
퐳ퟐ
( )
퐀퐯 퐒 ∙ 퐊(퐒) =
Eq. 10
퐒
퐒
(
)
퐒 ∙ 퐂ퟓ + 퐂ퟔ ∙ 퐑ퟏ + 퐑ퟐ
ꢀퟏ + 훚 ꢁ ꢀퟏ + 훚
퐩ퟏ
퐩ퟐ
Where the poles and zeroes are:
ퟏ
Eq. 11
Eq. 12
Eq. 13
Eq. 14
훚퐳ퟏ
훚퐳ퟐ
=
퐑ퟓ ∙ 퐂ퟓ
ퟏ
=
퐑ퟏ ∙ 퐂ퟒ
퐂ퟓ + 퐂ퟔ
훚퐩ퟏ
=
=
퐑ퟓ ∙ 퐂ퟓ ∙ 퐂ퟔ
퐑ퟏ + 퐑ퟐ
훚퐩ퟐ
퐑ퟏ ∙ 퐑ퟐ ∙ 퐂ퟒ
The goal of loop compensation design is to achieve:
High DC Gain
Gain Margin less than -10dB
Phase Margin greater than 45°
Loop Bandwidth Crossover Frequency (fc) less than 10% of fsw
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Application Information (continued)
15
External Loop Compensation Design (continued)
The loop gain at the crossover frequency has unity gain. Therefore, the compensator resistance, R5, is determined by:
ퟐ훑 ∙ 퐟퐜 ∙ 퐕퐎퐔퐓 ∙ 퐂퐎퐔퐓 ∙ 퐑퐓
퐠퐦 ∙ 퐕퐅퐁
훀
= ퟓ. ퟐ퐱ퟏퟎퟑ[ ] ∙ 퐟퐜 ∙ 퐕퐎퐔퐓 ∙ 퐂퐎퐔퐓
퐀
Eq. 15
퐑ퟓ =
Where:
gm is 0.3mS
RT is 0.2V/A
VFB is 0.8V
fc is the desired crossover frequency
Be aware that most ceramic capacitors will degrade with voltage stress or temperature extremes. Refer to its datasheet and use its worst case
capacitance value for calculations.
The compensation capacitors C5 and C6 are then equal to:
퐕퐎퐔퐓 ∙ 퐂퐎퐔퐓
Eq. 16
퐂ퟓ =
퐈퐎퐔퐓 ∙ 퐑ퟓ
퐑퐂 ∙ 퐂퐎퐔퐓
퐑ퟓ
ퟏ
Eq. 17
퐂ퟔ = 퐦퐚퐱 ꢀ
,
ꢁ
훑 ∙ 퐟퐬퐰 ∙ 퐑ퟓ
Where:
IOUT is the output load current
The inclusion of C6 can increase gain margin and can decrease phase margin. In most cases, C6 is optional and may be omitted.
The zero, z2, is optional as it can increase both the phase margin and gain bandwidth and can decrease gain margin. If used, place this zero at
around two to five times fC. Thus, C4 is in the approximate range of:
ퟏ
ퟏ
Eq. 18
퐂ퟒ = ꢆ
,
ꢇ
ퟏퟎ훑 ∙ 퐟퐂 ∙ 퐑ퟏ ퟒ훑 ∙ 퐟퐂 ∙ 퐑ퟏ
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Application Information (continued)
15
External Loop Compensation Design (continued)
The following is an example of how to choose component values for external loop compensation. Actual component values used in the application
circuit may vary slightly from the calculated first-order approximation equations.
Let the following conditions be defined:
VIN = 24V
VOUT = 5V
IOUT = 3.5A
fsw = 450kHz
R1 = 157kΩ
R2 = 30kΩ
L = 6.8µH
COUT = 3 × 22µF (Effectively, COUT ≈ 36µF)
RC ≈ 1mΩ
INPUT
VIN
24V
VIN
BST
SW
C3
100nF
L
6.8µH
OUTPUT
VOUT
5V
EN
R1
157kΩ
C4
AP63356Q
AP63357Q
C1
10µF
COUT
3 x 22µF
FB
R2
30kΩ
PG
COMP
R5
C5
GND
C6
Figure 43. Example Circuit with External Compensation
The calculations of the other component values involved in the external loop compensation, R5 and C5, are required. If the optional C4 and C6
capacitors are used, their calculations are also required.
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Application Information (continued)
15
External Loop Compensation Design (continued)
From Eq. 16, the value of R5 is calculated as:
훀
퐑ퟓ = ퟓ. ퟐ퐱ퟏퟎퟑ[ ] ∙ 퐟퐜 ∙ 퐕퐎퐔퐓 ∙ 퐂퐎퐔퐓
퐀
훀
= ퟓ. ퟐ퐱ퟏퟎퟑ[ ] ∙ ퟒퟓ퐤퐇퐳 ∙ ퟓ퐕 ∙ ퟑퟔ훍퐅
퐀
≈ ퟒퟐ. ퟏ퐤훀
Choose a standard resistor value for R5 close to its calculated value. For example, choose R5 to be 42.2k.
From Eq. 17, C5 is calculated as:
퐕퐎퐔퐓 ∙ 퐂퐎퐔퐓
퐂ퟓ =
퐈퐎퐔퐓 ∙ 퐑ퟓ
ퟓ퐕 ∙ ퟑퟔ훍퐅
=
ퟑ. ퟓ퐀 ∙ ퟒퟐ. ퟏ퐤훀
≈ ퟏ. ퟐ퐧퐅
Choose 1.2nF for C5 since it already is a standard capacitor value.
From Eq. 18, C6 is calculated as:
퐑퐂 ∙ 퐂퐎퐔퐓
퐑ퟓ
ퟏ
퐂ퟔ = 퐦퐚퐱 ꢀ
,
ꢁ
훑 ∙ 퐟퐬퐰 ∙ 퐑ퟓ
ퟏ퐦훀 ∙ ퟑퟔ훍퐅
ퟏ
= 퐦퐚퐱 ꢀ
,
ꢁ
ퟒퟐ. ퟏ퐤훀 훑 ∙ ퟒퟓퟎ퐤퐇퐳 ∙ ퟒퟐ. ퟏ퐤훀
(
)
= 퐦퐚퐱 ퟎ. ퟖ퐩퐅, ퟏퟔ. ퟖ퐩퐅
= ퟏퟔ. ퟖ퐩퐅
C6 is optional. If used, choose a standard capacitor value for C6 close to its calculated value. For example, choose C6 to be 15pF.
From Eq. 19, the approximate range of C4 is calculated as:
ퟏ
ퟏ
퐂ퟒ = ꢆ
= ꢆ
,
ꢇ
ퟏퟎ훑 ∙ 퐟퐂 ∙ 퐑ퟏ ퟒ훑 ∙ 퐟퐂 ∙ 퐑ퟏ
ퟏ
ퟏ
,
ꢇ
ퟏퟎ훑 ∙ ퟒퟓ퐤퐇퐳 ∙ ퟏퟓퟕ퐤훀 ퟒ훑 ∙ ퟒퟓ퐤퐇퐳 ∙ ퟏퟓퟕ퐤훀
= [ퟒ. ퟓ퐩퐅, ퟏퟏ. ퟑ퐩퐅]
C4 is optional. If used, choose a standard capacitor value for C4 that is close to its calculated range. For example, choose C4 to be 10pF.
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AP63356Q/AP63357Q
Document number: DS41948 Rev. 1 - 2
AP63356Q/AP63357Q
Application Information (continued)
15
External Loop Compensation Design (continued)
INPUT
VIN
24V
VIN
BST
SW
C3
100nF
L
6.8µH
OUTPUT
VOUT
5V
EN
C4
10pF
R1
157kΩ
AP63356Q
AP63357Q
C1
10µF
COUT
3 x 22µF
FB
R2
30kΩ
PG
COMP
R5
42.2kΩ
GND
C6
15pF
C5
1.2nF
Figure 44. Example Circuit with Calculated Component Values for External Compensation
The first-order calculated loop response has the following characteristics:
Bandwidth is around 41.7kHz
Phase Margin is around 65.6°
Gain Margin is around -13.2dB
100
80
250
200
150
100
50
60
40
20
0
0
-20
-40
-60
-80
-100
-50
-100
-150
-200
-250
100
1,000
10,000
100,000 1,000,000
100
1,000
10,000
100,000 1,000,000
Frequency (Hz)
Frequency (Hz)
Figure 45. Closed-Loop Bandwidth
Figure 46. Closed-Loop Phase Margin
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Document number: DS41948 Rev. 1 - 2
AP63356Q/AP63357Q
Layout
PCB Layout
1. The AP63356Q/AP63357Q works at 3.5A load current so heat dissipation is a major concern in the layout of the PCB. 2oz copper for both
the top and bottom layers is recommended.
2. Place the input capacitors as closely across VIN and GND as possible.
3. Place the inductor as close to SW as possible.
4. Place the output capacitors as close to GND as possible.
5. Place the feedback components as close to FB as possible.
6. If using four or more layers, use at least the 2nd and 3rd layers as GND to maximize thermal performance.
7. Add as many vias as possible around both the GND pin and under the GND plane for heat dissipation to all the GND layers.
8. Add as many vias as possible around both the VIN pin and under the VIN plane for heat dissipation to all the VIN layers.
9. See Figure 47 for more details.
C1
VIN
GND
EN
SW
PG
VOUT
C
FB
Figure 47. Recommended PCB Layout
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Document number: DS41948 Rev. 1 - 2
AP63356Q/AP63357Q
Ordering Information
AP6335XQ X - X
Product Version
Package
Packing
7 : Tape & Reel
6 : AP63356Q
7 : AP63357Q
ZV: V-DFN3020-13/SWP (Type A1)
Tape and Reel
Part Number
Operation Mode
FSS Feature
Package Code
Quantity
3,000
Part Number Suffix
AP63356QZV-7
AP63357QZV-7
PWM Only
PFM/PWM
Yes
Yes
ZV
ZV
-7
-7
3,000
Marking Information
V-DFN3020-13/SWP (Type A1)
( Top View )
XXX : Identification Code
Y : Year : 0~9
XXX
W : Week : A~Z : 1~26 Week;
Y W X
a~z : 27~52 Week; z Represents
52 and 53 Week
X : Internal Code
Part Number
Package
Identification Code
AP63356QZV-7
AP63357QZV-7
V-DFN3020-13/SWP (Type A1)
V-DFN3020-13/SWP (Type A1)
K4Q
K5Q
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Document number: DS41948 Rev. 1 - 2
AP63356Q/AP63357Q
Package Outline Dimensions
Please see http://www.diodes.com/package-outlines.html for the latest version.
V-DFN3020-13/SWP (Type A1)
b
13
L1
L2
V-DFN3020-13/SWP
(Type A1)
1
12
e1
e2
Dim
A
A1
A3
b
D
E
e
e1
e2
L
L1
L2
Min
0.80
0.00
Max
0.90
0.05
Typ
0.85
0.02
0.203 REF
0.25
E
0.15
0.20
2.00 BSC
3.00 BSC
0.45 BSC
0.575 BSC
0.475 BSC
0.45
DETAIL A
b
e
0.35
0.55
0.40
0.60
0.65
A1
A3
L
0.40± 0.05
1.475 1.575 1.525
D
A
All Dimensions in mm
0.203 REF.
DETAIL A
0.100 REF.
0.05 REF.
Suggested Pad Layout
Please see http://www.diodes.com/package-outlines.html for the latest version.
V-DFN3020-13/SWP (Type A1)
X2
X1(2x)
Value
(in mm)
Dimensions
C
G
X
0.45
0.175
0.60
Y2
Y1(2x)
X1
X2
X3
Y
0.80
0.30
2.30
0.30
Y3
Y1
Y2
Y3
1.450
1.725
2.825
G
C
X(6x)
X3
Y(6x)
Mechanical Data
Moisture Sensitivity: Level 1 per J-STD-020
Terminals: Finish – Matte Tin Plated, Solderable per MIL-STD-202, Method 208
Weight: 0.013 grams (Approximate)
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Document number: DS41948 Rev. 1 - 2
AP63356Q/AP63357Q
IMPORTANT NOTICE
DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
(AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION).
Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other changes
without further notice to this document and any product described herein. Diodes Incorporated does not assume any liability arising out of the
application or use of this document or any product described herein; neither does Diodes Incorporated convey any license under its patent or
trademark rights, nor the rights of others. Any Customer or user of this document or products described herein in such applications shall assume
all risks of such use and will agree to hold Diodes Incorporated and all the companies whose products are represented on Diodes Incorporated
website, harmless against all damages.
Diodes Incorporated does not warrant or accept any liability whatsoever in respect of any products purchased through unauthorized sales channel.
Should Customers purchase or use Diodes Incorporated products for any unintended or unauthorized application, Customers shall indemnify and
hold Diodes Incorporated and its representatives harmless against all claims, damages, expenses, and attorney fees arising out of, directly or
indirectly, any claim of personal injury or death associated with such unintended or unauthorized application.
Products described herein may be covered by one or more United States, international or foreign patents pending. Product names and markings
noted herein may also be covered by one or more United States, international or foreign trademarks.
This document is written in English but may be translated into multiple languages for reference. Only the English version of this document is the
final and determinative format released by Diodes Incorporated.
LIFE SUPPORT
Diodes Incorporated products are specifically not authorized for use as critical components in life support devices or systems without the express
written approval of the Chief Executive Officer of Diodes Incorporated. As used herein:
A. Life support devices or systems are devices or systems which:
1. are intended to implant into the body, or
2. support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the
labeling can be reasonably expected to result in significant injury to the user.
B. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or to affect its safety or effectiveness.
Customers represent that they have all necessary expertise in the safety and regulatory ramifications of their life support devices or systems, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any
use of Diodes Incorporated products in such safety-critical, life support devices or systems, notwithstanding any devices- or systems-related
information or support that may be provided by Diodes Incorporated. Further, Customers must fully indemnify Diodes Incorporated and its
representatives against any damages arising out of the use of Diodes Incorporated products in such safety-critical, life support devices or systems.
Copyright © 2020, Diodes Incorporated
www.diodes.com
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Document number: DS41948 Rev. 1 - 2
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