PA7540S-15L [DIODES]
EE PLD, 15ns, CMOS, PDSO24, 0.300 INCH, LEAD FREE, SOIC-24;
| 型号： | PA7540S-15L |
| 厂家： | 
DIODES INCORPORATED |
| 描述： | EE PLD, 15ns, CMOS, PDSO24, 0.300 INCH, LEAD FREE, SOIC-24 时钟 栅 输入元件 光电二极管 可编程逻辑 |
| 文件： | 总10页 (文件大小：324K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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PA7540 PEEL™ Array
Programmable Electrically Erasable Logic Array
Most Powerful 24-pin PLD Available
CMOS Electrically Erasable Technology
- Reprogrammable in 24-pin DIP, SOIC and
28-pin PLCC packages
- 20 I/Os, 2 inputs/clocks, 40 registers/latches
- 40 logic cell output functions
- PLA structure with true product-term sharing
- Logic functions and registers can be I/O-buried
- Optional JN package for 22V10 power/ground
compatibility
Flexible Logic Cell
Ideal for Combinatorial, Synchronous and
Asynchronous Logic Applications
- 2 output functions per logic cell
- D,T and JK registers with special features
- Independent or global clocks, resets, presets,
clock polarity and output enables
- Sum-of-products logic for output enables
- Integration of multiple PLDs and random logic
- Buried counters, complex state-machines
- Comparators, decoders, multiplexers and other wide-
gate functions
Development and Programmer Support
- Anachip’s WinPLACE Development Software
- Fitters for ABEL, CUPL and other software
- Programming support by popular third-party
programmers
High-Speed Commercial and Industrial Versions
- As fast as 10ns/15ns (tpdi/tpdx), 71.4MHz (fMAX
)
- Industrial grade available for 4.5 to 5.5V VCC and
-40 to +85 °C temperatures
General Description
The PA7540 is a member of the Programmable Electrically presets, clock polarity, and other features, making the
Erasable Logic (PEEL™) Array family based on ICT’s PA7540 suitable for
a
variety of combinatorial,
CMOS EEPROM technology. PEEL™ Arrays free synchronous and asynchronous logic applications. With pin
designers from the limitations of ordinary PLDs by compatibility and super-set functionality to most 24-pin
providing the architectural flexibility and speed needed for PLDs, (22V10, EP610/630, GAL6002), the PA7540 can
today’s programmable logic designs. The PA7540 is by far implement designs that exceed the architectures of such
the most powerful 24-pin PLD available today with 20 I/O devices. The PA7540 supports speeds as fast as
pins, 2 input/global-clocks and 40 registers/latches (20 10ns/15ns (tpdi/tpdx) and 71.46MHz (fMAX) at moderate
buried logic cells and 20 I/O registers/latches). Its logic power consumption 80mA (55mA typical). Packaging
array implements 84 sum-of-products logic functions. The includes 24-pin DIP, SOIC and 28-pin PLCC (see Figure 1).
PA7540’s logic and I/O cells (LCCs, IOCs) are extremely Anachip and popular third-party development tool
flexible offering two output functions per cell (a total of 40 manufacturers provide development and programming
for all 20 logic cells). Logic cells are configurable as D, T, support for the PA7540.
and JK registers with independent or global clocks, resets,
Figure 1. Pin Configuration
Figure 2. Block Diagram
I/CLK1
I/O
1
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I/O
1
24
23
22
21
20
19
18
17
16
15
14
13
2 Input/
I/CLK1
I/O
VCC
I/O
2
Global Clock Pins
2
3
4
5
6
7
8
9
3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
4
Global
Cells
I/O
I/O
5
I/O
I/O
84 (42X2)
Array Inputs
true and
6
I/O
I/O
7
I/O
I/O
8
I/O
I/O
9
I/O
I/O
2
complement
I/O
Cells
(IOC)
10
11
12
I/O
I/O
20 I/O Pins
Global Cells
I/O Cells
I/O
I/O
20
20
I/CLK1
I/O
VCC
I/O
GND
I/CLK2
10
11
12
I/O
I/O
I/O
GND
I/O
I/CLK2
Buried
logic
SOIC
I/O
I/O
Logic
Array
I/O
I/O
DIP
Logic functions
to I/O cells
Logic
I/O
I/O
A
B
C
D
Control
Cells
I/O
I/O
20
20
I/O
I/O
(LCC)
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/CLK2
4
3
2
1
28 27 26
4
3
2
1
28 27 26
4 sum terms
4 product terms
for Global Cells
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
5
6
7
8
9
10
11
25
24
23
22
21
20
19
5
6
7
8
9
10
11
25
24
23
22
21
20
19
20 Logic Control Cells
2 output functions per cell
(40 total output functions possible)
80 sum terms
(four per LCC)
I/O
I/O
NC
I/O
I/O
I/O
PA7540
NC NC
08-14-002A
I/O
I/O
I/O
I/O
I/O
I/O
Logic Control Cells
12 13 14 15 16 1718
12 13 14 15 16 17 18
PLCC-JN
PLCC-J
08-14-001B
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights
under any patent accompany the sale of the product.
Rev. 1.0 Dec 16, 2004
1/10
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Inside the Logic Array
The heart of the PEEL™ Array architecture is based on a needed and not left unutilized or duplicated. Secondly, the
logic array structure similar to that of a PLA (programmable sum-of-products functions provided to the logic cells can be
AND, programmable OR). The logic array implements all used for clocks, resets, presets and output enables instead of
logic functions and provides interconnection and control of just simple product-term control.
the cells. In the PA7540 PEEL™ Array, 42 inputs are
The PEEL™ logic array can also implement logic functions
available into the array from the I/O cells and input/global-
with many product terms within a single-level delay. For
clock pins.
example a 16-bit comparator needs 32 shared product terms
All inputs provide both true and complement signals, which to implement 16 exclusive-OR functions. The PEEL™ logic
can be programmed to any product term in the array. The array easily handles this in a single level delay. Other
PA7540 PEEL™ Arrays contains 84 product terms. All PLDs/CPLDs either run out of product-terms or require
product terms (with the exception of certain ones fed to the expanders or additional logic levels that often slow
global cells) can be programmably connected to any of the performance and skew timing.
sum-terms of the logic control cells (four sum-terms per
logic control cell). Product-terms and sum-terms are also
Logic Control Cell (LCC)
routed to the global cells for control purposes. Figure 3
Logic Control Cells (LCC) are used to allocate and control the
logic functions created in the logic array. Each LCC has four
primary inputs and three outputs. The inputs to each LCC are
complete sum-of-product logic functions from the array, which
can be used to implement combinatorial and sequential logic
functions, and to control LCC registers and I/O cell output
enables.
shows a detailed view of the logic array structure.
From
IO Cells
(IOC) and
I/CLKs
From Global Cell
42 Array Inputs
Preset RegType Reset
System Clock
On/Off
MUX
To
Array
From
Logic
P
D,T,J
Q
Control
MUX
REG
Cells
(LCC)
K
R
A
B
C
D
From
Array
To
Global
Cells
84 Product Terms
To
I/O
Cell
MUX
To
Logic Control
Cells
(LCC)
08-14-004A
Figure 4. Logic Control Cell Block Diagram
84 Sum Terms
08-14-003A
PA7540 Logic Array
As shown in Figure 4, the LCC is made up of three signal
routing multiplexers and a versatile register with synchronous
or asynchronous D, T, or JK registers (clocked-SR registers,
which are a subset of JK, are also possible). See Figure 5.
EEPROM memory cells are used for programming the
desired configuration. Four sum-of-product logic functions
(SUM terms A, B, C and D) are fed into each LCC from the
logic array. Each SUM term can be selectively used for
multiple functions as listed below.
Figure 3 PA7540 Logic Array
True Product-Term Sharing
The PEEL™ logic array provides several advantages over
common PLD logic arrays. First, it allows for true product-
term sharing, not simply product-term steering, as
commonly found in other CPLDs. Product term sharing
ensures that product-terms are used where they are
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Sum-A = D, T, J or Sum-A
can be registered, one output can be combinatorial and the
third, an output enable. The multi-function PEEL™ Array logic
cells are equivalent to two or three macrocells of other PLDs,
which have only one output per cell. They also allow registers
to be truly buried from I/O pins without limiting them to input-
only (see Figure 8 ).
Sum-B = Preset, K or Sum-B
Sum-C = Reset, Clock, Sum-C
Sum-D = Clock, Output Enable
D Register
Q = D after clocked
P
D
Q
Q
Q
Best for storage, simple counters,
shifters and state machines with
few hold (loop) conditions.
From Global Cell
R
I/O Cell Clock
T Register
Q toggles when T = 1
Q holds when T = 0
REG/
Latch
P
R
T
Q
Best for wide binary counters (saves
product terms) and state machines
with many hold (loop) conditions.
To
Array
MUX
Input
JK Register
Q toggles when J/K = 1/1
Q holds when J/K = 0/0
Q = 1
Q = 0
P
R
J
when J/K = 1/0
when J/K = 0/1
K
A,B,C
or
Q
MUX
Combines features of both D and T
registers.
I/O Pin
From
Logic
Control
Cell
08-14-005A
MUX
D
Figure 5. LCC Register Types
0
1
7540 /O Cell (IOC)
SUM-A can serve as the D, T, or J input of the register or a
combinatorial path. SUM-B can serve as the K input, or the
preset to the register, or a combinatorial path. SUM-C can
be the clock, the reset to the register, or a combinatorial
path. SUM-D can be the clock to the register or the output
enable for the connected I/O cell. Note that the sums
controlling clocks, resets, presets and output enables are
complete sum-of-product functions, not just product terms
as with most other PLDs. This also means that any input or
I/O pin can be used as a clock or other control function.
08-14-006A
Figure 6. I/O Cell Block Diagram
IOC Register
D
Q
Q = D after rising edge of clock
holds until next rising edge
IOC Latch
L
Q
Q = L when clock is high
holds value when clock is low
Several signals from the global cell are provided primarily
for synchronous (global) register control. The global cell
signals are routed to all LCCs. These signals include a
high-speed clock of positive or negative polarity, global
preset and reset, and a special register-type control that
selectively allows dynamic switching of register type. This
last feature is especially useful for saving product terms
when implementing loadable counters and state machines
by dynamically switching from D-type registers to load and
T-type registers to count (see Figure 10).
08-14-007A
Figure 7. IOC Register Configurations
I/O Cell (IOC)
All PEEL™ Arrays have I/O cells (IOC) as shown above in
Figure 6. Inputs to the IOCs can be fed from any of the LCCs
in the array. Each IOC consists of routing and control
multiplexers, an input register/transparent latch, a three-state
buffer and an output polarity control. The register/ latch can
be clocked from a variety of sources determined by the global
cell. It can also be bypassed for a non-registered input. The
combination of LCC and IOC allows for multiple buried
registers and logic paths. (See Figure 8).
Multiple Outputs Per Logic Cell
An important feature of the logic control cell is its capability
to have multiple output functions per cell, each operating
independently. As shown in Figure 4, two of the three
outputs can select the Q output from the register or the
Sum A, B or C combinatorial paths. Thus, one LCC output
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Group A & B
LCC Clocks
MUX
MUX
Q
D
CLK1
CLK2
Input with optional
register/latch
I/O
IOC Clocks
PCLK
Reg-Type
LCC Reg-Type
LCC Presets
LCC Resets
I/O with
independent
output enable
Preset
Reset
1
D
Q
A
B
C
D
Global Cell: LCC & IOC
2
08-14-009A
OE
08-14-008A
Figure 9. Global Cells
Reg-Type from Global Cell
Figure 8. LCC & IOC With Two Outputs
Global Cells
The global cells, shown in Figure 9, are used to direct
global clock signals and/or control terms to the LCCs and
IOCs. The global cells allow a clock to be selected from the
CLK1 pin, CLK2 pin, or a product term from the logic array
(PCLK). They also provide polarity control for IOC clocks
enabling rising or falling clock edges for input
registers/latches. Note that each individual LCC clock has
its own polarity control. The global cell includes sum-of-
products control terms for global reset and preset, and a
fast product term control for LCC register-type, used to
save product terms for loadable counters and state
machines (see Figure 10). The PA7540 provides two
global cells that divides the LCC and IOCs into two groups,
A and B. Half of the LCCs and IOCs use global cell A, half
use global cell B. This means, for instance, two high-speed
global clocks can be used among the LCCs.
Register Type Change Feature
Global Cell can dynamically change user-
selected LCC registers from D to T or from D
to JK. This saves product terms for loadable
counters or state machines. Use as D register
to load, use as T or JK to count. Timing allows
dynamic operation.
P
R
D
Q
Example:
Product terms for 10 bit loadable binary counter
P
R
T
Q
D uses 57 product terms (47 count, 10 load)
T uses 30 product terms (10 count, 20 load)
D/T uses 20 product terms (10 count, 10 load)
08-14-010A
Figure 10. Register Type Change Feature
internal signals to be simulated and analyzed via a
waveform display.(See Figures 10)
PEEL™ Array Development Support
Development support for PEEL™ Arrays is provided by
Anachip and manufacturers of popular development tools.
Anachip offers the powerful WinPLACE Development
Software (free to qualified PLD designers).
PEEL™ Array development is also supported by popular
development tools, such as ABEL via Anachip’s PEEL™
Array fitters. A special smart translator utility adds the
capability to directly convert JEDEC files for other devices
into equivalent JEDEC files for pin-compatible PEEL™
Arrays.
The PLACE software includes an architectural editor, logic
compiler, waveform simulator, documentation utility and a
programmer interface. The PLACE editor graphically
illustrates and controls the PEEL™ Array’s architecture,
making the overall design easy to understand, while
allowing the effectiveness of boolean logic equations, state
machine design and truth table entry. The PLACE compiler
performs logic transformation and reduction, making it
possible to specify equations in almost any fashion and fit
the most logic possible in every design. PLACE also
provides a multi-level logic simulator allowing external and
Programming
PEEL™ Arrays are EE-reprogrammable in all package
types, plastic-DIP, PLCC and SOIC. This makes them an
ideal development vehicle for the lab. EE -
reprogrammability is also useful for production, allowing
unexpected changes to be made quickly and without waste.
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Programming of PEEL™ Arrays is supported by many
popular third party programmers.
Design Security and Signature Word
The PEEL™ Arrays provide a special EEPROM security bit
that prevents unauthorized reading or copying of designs.
Once set, the programmed bits of the PEEL™ Arrays
cannot be accessed until the entire chip has been
electrically erased. Another programming feature,
signature word, allows a user-definable code to be
programmed into the PEEL™ Array. The code can be read
back even after the security bit has been set. The signature
word can be used to identify the pattern programmed in the
device or to record the design revision.
Figure 12 - WinPLACE LCC and IOC screen
Figure 11 - WinPLACE Architectural Editor for
PA7540
Figure 13 - WinPLACE waveform and
simulator screen
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This device has been designed and tested for the
specified operating ranges. Improper operation outside of
these levels is not guaranteed. Exposure to absolute
maximum ratings may cause permanent damage.
Table 1. Absolute Maximum Ratings
Symbol
VCC
Parameter
Supply Voltage
Conditions
Relative to Ground
Relative to Ground1
Ratings
-0.5 to + 7.0
-0.5 to VCC + 0.6
±25
Unit
V
VI, VO
IO
Voltage Applied to Any Pin
Output Current
V
Per pin (IOL, IOH
)
mA
°C
TST
Storage Temperature
Lead Temperature
-65 to + 150
+300
TLT
Soldering 10 seconds
°C
Table 2. Operating Ranges
Symbol
Parameter
Conditions
Commercial
Industrial
Min
Max
Unit
4.75
5.25
VCC
Supply Voltage
V
4.5
0
5.5
+70
+85
20
Commercial
Industrial
TA
Ambient Temperature
°C
-40
TR
TF
Clock Rise Time
Clock Fall Time
VCC Rise Time
See Note 2
See Note 2
See Note 2
ns
ns
20
TRVCC
250
ms
Table 3. D.C. Electrical Characteristics
Over the Operating Range
Symbol
VOH
VOHC
VOL
Parameter
Conditions
Min
2.4
Max
Unit
V
Output HIGH Voltage - TTL VCC = Min, IOH = -4.0mA
Output HIGH Voltage -
VCC = Min, IOH = -10µA
CMOS
VCC - 0.3
V
Output LOW Voltage - TTL
VCC = Min, IOL = 16mA
0.5
0.15
VCC + 0.3
0.8
V
Output LOW Voltage -
CMOS
VOLC
VIH
VCC = Min, IOL = -10µA
V
Input HIGH Level
2.0
V
VIL
Input LOW Level
-0.3
V
IIL
Input Leakage Current
Output Leakage Current
±10
±10
-120
80
µA
µA
mA
V
CC = Max, GND ≤VIN ≤VCC
IOZ
I/O = High-Z, GND ≤VO ≤VCC
Output Short Circuit
Current4
ISC
VCC = 5V, VO = 0.5V, TA= 25°C
-30
3,11
VIN = 0V or VCC
-15
ICC
VCC Current
f = 25MHz
55 (typ.)18
mA
11
All outputs disabled4
I-15
90
7
CIN
Input Capacitance5
Output Capacitance5
6
pF
pF
TA = 25°C, VCC = 5.0V @ f = 1 MHz
7
COUT
12
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Table 4. A.C Electrical Characteristics Combinatorial
Over the Operating Range
-15/I-15
Symbol
Parameter6,12
Unit
Min
Max
Propagation delay Internal (tAL + tLC
)
Propagation delay External (tIA + tAL +tLC + tLO
Input or I/O pin to array input
10
15
2
ns
ns
ns
ns
ns
ns
ns
ns
t
PDI
)
t
PDX
t
IA
Array input to LCC
9
1
3
3
t
t
t
AL
LC
LO
LCC input to LCC output10
LCC output to output pin
Output Disable, Enable from LCC output7
Output Disable, Enable from input pin7
t
, t
OD OE
15
t
OX
This device has been designed and tested for the recommended operating conditions. Proper operation outside of these
levels is not guaranteed. Exposure to absolute maximum ratings may cause permanent damage
Figure 14. Combinatorial Timing - Waveforms and Block Diagram
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Table 5. A.C. Electrical Characteristics Sequential
-15/I-15
Symbol
Parameter6,1
Unit
Min
6
Max
Internal set-up to system clock8 - LCC14
ns
t
SCI
(tAL + tSK + tLC - tCK
Input16 (EXT.) set-up to system clock, - LCC (tIA + tSCI
System-clock to Array Int. - LCC/IOC/INC14 (tCK +tLC
)
)
8
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
f
f
f
f
t
t
t
t
t
t
t
t
SCX
COI
COX
HX
)
8
System-clock to Output Ext. - LCC (tCOI + tLO
Input hold time from system clock - LCC
LCC Input set-up to async. clock13 - LCC
Clock at LCC or IOC - LCC output
LCC input hold time from system clock - LCC
Input set-up to system clock - IOC/INC14 (tSK - tCK
)
12
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
MHz
MHz
ns
0
3
1
4
0
4
SK
AK
HK
)
SI
Input hold time from system clock - IOC/INC (tSK - tCK
)
HI
Array input to IOC PCLK clock
6
7
PK
Input set-up to PCLK clock17 - IOC/INC (tSK-tPK-tIA)
0
5
SPI
Input hold from PCLK clock17 - IOC/INC (tPK+tIA-tSK
System-clock delay to LCC/IOC/INC
)
HPI
CK
System-clock low or high pulse width
Max. system-clock frequency Int/Int 1/(tSCI + tCOI
Max. system-clock frequency Ext/Int 1/(tSCX + tCOI
Max. system-clock frequency Int/Ext 1/(tSCI + tCOX
Max. system-clock frequency Ext/Ext 1/(tSCX + tCOX
Max. system-clock toggle frequency 1/(tCW + tCW
LCC presents/reset to LCC output
Input to Global Cell present/reset (tIA + tAL + tPR
Asynch. preset/reset pulse width
Input to LCC Reg-Type (RT)
7
CW
MAX1
MAX2
MAX3
MAX4
TGL
PR
)
71.4
62.5
55.5
50.0
71.4
1
)
)
)
9
)
)
12
ns
ns
ns
ns
ns
ns
µs
ST
8
AW
6
1
7
RT
LCC Reg-Type to LCC output register change
Input to Global Cell register-type change (tRT + tRTV
RTV
RTC
RW
RESET
)
Asynch. Reg-Type pulse width
10
Power-on reset time for registers in clear state2
5
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Figure 15. Sequential Timing – Waveforms and Block Diagram
Notes
1. Minimum DC input is -0.5V, however inputs may under-shoot to -2.0V
for periods less than 20ns.
12. Test loads are specified in Section 5 of the Products Data Book
(1999/2000).
2.Test points for Clock and VCC in tR,tF,tCL,tCH, and tRESET are referenced at
10% and 90% levels.
13. “Async. Clock” refers to the clock from the Sum term (OR gate).
14. The “LCC” term indicates that the timing parameter is applied to the
LCC register. The “LCC/IOC” term indicates that the timing
parameter is applied to both the LCC and IOC registers.
16. The term “input” without any reference to another term refers to an
(external) input pin.
3. I/O pins are 0V or VCC.
4. Test one output at a time for a duration of less than 1 sec.
5. Capacitances are tested on a sample basis.
6. Test conditions assume: signal transition times of 5ns or less from the
10% and 90% points, timing reference levels of 1.5V (unless
otherwise specified).
17. The parameter t
indicates that the PCLK signal to the IOC register
SPI
is always slower than the data from the pin or input by the absolute
7. tOE is measured from input transition to VREF ±0.1V (See test loads at
end of Section 6 for VREF value). tOD is measured from input transition
to VOH -0.1V or VOL +0.1V.
value of (t -t -t ). This means that no set-up time for the data
SK PK IA
from the pin or input is required, i.e. the external data and clock can
be sent to the device simultaneously. Additionally, the data from the
8. DIP: “System-clock” refers to pin 1/13 high speed clocks. PLCC: “Sys-
tem-clock” refers to pin 2/16 high speed clocks.
pin must remain stable for t
arrive at the IOC register.
time, i.e. to wait for the PCLK signal to
HPI
9. For T or JK registers in toggle (divide by 2) operation only.
10. For combinatorial and async-clock to LCC output delay.
11. ICC for a typical application: This parameter is tested with the device
programmed as a 10-bit D-type counter.
18. Typical (typ) ICC is measured at T = 25° C, freq = 25MHZ, V
=
CC
A
5V
Anachip Corp.
www.anachip.com.tw
Rev. 1.0 Dec 16, 2004
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To find out if the package you need is
available, contact Customer Service
Table 6. Ordering Information
Part Number
Speed
Temperature
Package
P24
PA7540P-15 (L)
PA7540J-15 (L)
PA7540JN-15 (L)
PA7540S-15 (L)
PA7540PI-15 (L)
PA7540JI-15 (L)
PA7540JNI-15 (L)
PA7540SI-15 (L)
J28
JN28
S24
P24
J28
JN28
S24
10/15ns
C
10/15ns
I
Figure 16. Part Number
Device
Suffix
PA7540J-15X
Lead Free
L : Lead Free Package
Blank : Normal
Package
P = 300mil DIP
J = Plastic (J) Leaded Chip Carrier (PLCC)
JN = PLCC Alternate Pin Out
Speed
-15 = 10ns/15ns tpd/tpdx
S = SOIC 300 mil Gullwing
Temperature Range
(Blank) = Commercial 0 to 70oC
I = Industrial -40 to +85oC
Anachip Corp.
Head Office,
Anachip USA
2F, No. 24-2, Industry E. Rd. IV, Science-Based
Industrial Park, Hsinchu, 300, Taiwan
Tel: +886-3-5678234
780 Montague Expressway, #201
San Jose, CA 95131
Tel: (408) 321-9600
Fax: (408) 321-9696
Fax: +886-3-5678368
Email: sales_usa@anachip.com
Website: http://www.anachip.com
©2004 Anachip Corp.
Anachip reserves the right to make changes in specifications at any time and without notice. The information furnished by
Anachip in this publication is believed to be accurate and reliable. However, there is no responsibility assumed by Anachip
for its use nor for any infringements of patents or other rights of third parties resulting from its use. No license is granted
under any patents or patent rights of Anachip. Anachip’s products are not authorized for use as critical components in life
support devices or systems.
Marks bearing © or ™ are registered trademarks and trademarks of Anachip Corp.
Anachip Corp.
www.anachip.com.tw
Rev. 1.0 Dec 16, 2004
10/10
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