PI6C49S1510AZDIEX [DIODES]
Low Skew Clock Driver,;型号: | PI6C49S1510AZDIEX |
厂家: | DIODES INCORPORATED |
描述: | Low Skew Clock Driver, 驱动 逻辑集成电路 |
文件: | 总19页 (文件大小:1777K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
A product Line of
Diodes Incorporated
PI6C49S1510A
High Performance Differential Fanout Buffer
Features
Description
ꢀÎ10 differential outputs with 2 banks
e PI6C49S1510A is a high performance fanout buffer device-
which supports up to 1.5GHz frequency. It also integrates a
unique feature with user configurable output signaling standards
on per bank basis which provide great flexibilities to users. e
device also uses Pericom's proprietary input detection technique
to make sure illegal input conditions will be detected and re-
flected by output states. is device is ideal for systems that need
to distribute low jitter clock signals to multiple destinations.
ꢀÎUser configurable output signaling standard for each bank:
LVDS or LVPECL or HCSL
ꢀÎLVCMOS reference output up to 200MHz
ꢀÎUp to 1.5GHz output frequency for differential outputs
ꢀÎUltra low additive phase jitter: < 0.02 ps (typ) (differential
156.25MHz, 12KHz to 20MHz integration range); < 0.01 ps
(typ) (differential 156.25MHz, 10kHz to 1MHz integration
range)
Applications
ꢀÎNetworking systems including switches and Routers
ꢀÎSelectable reference inputs support either single-ended
or differential or Xtal
ꢀÎHigh frequency backplane based computing and telecom
ꢀÎLow skew between outputs within banks (<40ps)
ꢀÎLow delay from input to output (Tpd typ. < 0.9ns)
ꢀÎSeparate Input output supply voltage for level shiꢀing
ꢀÎ2.5V / 3.3V power supply
platforms
ꢀÎIndustrial temperature support
ꢀÎTQFN-48 package
Pin Configuration (48-TQFN)
Block Diagram
OPMODEA[1:0]
48 47 46 45 44 43 42 41 40 39 38 37
1
QA[0:4]
QAO+
QAO-
QA1+
QA1-
36
35
34
33
32
31
30
29
28
27
26
25
QBO+
QBO-
QB1+
QB1-
5
2
3
X1
OSC
X2
4
OPMODEB[1:0]
IN0+
IN0-
5
V
V
DDO
DDO
QB[0:4]
5
6
QA2+
QA2-
QB2+
QB2-
IN1+
IN1-
7
Ref_Out
8
V
V
DDO
DDO
9
QA3+
QA3-
QA4+
QA4-
QB3+
QB3-
QB4+
QB4-
IN_SEL[1:0]
10
11
12
Sync_OE
Iref
Sync
13 14 15 16 17 18 19 20 21 22 23 24
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PI6C49S1510A
Document Number DS40482 Rev 2-2
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PI6C49S1510A
Pin Description
Pin #
Pin Name
Type
Description
QA0+
QA0-
QA1+
QA1-
VDDO
QA2+
QA2-
QA3+
QA3-
QA4+
QA4-
Bank A differential output pair 0. Pin selectable LVPECL/LVDS/HCSL
interface levels.
1,2
Output
Bank A differential output pair 1. Pin selectable LVPECL/LVDS/HCSL
interface levels.
3,4
Output
Power
5,8,29,32,45
6,7
Power supply pins for IO
Bank A differential output pair 2. Pin selectable LVPECL/LVDS/HCSL
interface levels.
Output
Bank A differential output pair 3. Pin selectable LVPECL/LVDS/HCSL
interface levels.
9,10
Output
Output
Bank A differential output pair 4. Pin selectable LVPECL/LVDS/HCSL
interface levels.
11,12
13,18,24,37,43,48 GND
Power
Power supply ground
Output mode select for Bank A. See Table 2 for functions, LVCMOS/
LVTTL interface levels
14,47
OPMODEA
Input Pulldown
15,42
16
Power
Input
Power supply pins
VDD
X1
XTAL input, can also be used as single ended input pin
XTAL output. If X1 is used as a single ended input pin, X2 is to be leꢀ
open
17
X2
Output
Input clock sele ct. See Table 1 for function. LVCMOS/LVTTL interface
levels.
19,22
20
IN_SEL
IN0+
Input Pulldown
Input Pulldown Reference input 0
Pull-up/
21
IN0-
Input
Inverted reference input 0, internal bias to VDD/2
Pulldown
Output mode select for Bank B. See Table 2for functions, LVCMOS/
LVTTL interface levels
23,39
26,25
OPMODEB
Input Pulldown
Output
QB4+
QB4-
QB3+
QB3-
QB2+
QB2-
QB1+
QB1-
Bank B differential output pair 4. Pin selectable LVPECL/LVDS/HCSL
interface levels.
Bank B differential output pair 3. Pin selectable LVPECL/LVDS/HCSL
interface levels.
28,27
31,30
34,33
Output
Output
Output
Bank B differential output pair 2. Pin selectable LVPECL/LVDS/HCSL
interface levels.
Bank B differential output pair 1. Pin selectable LVPECL/LVDS/HCSL
interface levels.
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PI6C49S1510A
Document Number DS40482 Rev 2-2
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PI6C49S1510A
Pinout Description Cont.
Pin #
Pin Name
QB0+
Type
Description
Bank B differential output pair 0. Pin selectable LVPECL/LVDS/HCSL
interface levels.
36,35
Output
QB0-
A fixed precision resistor (475ohm) from this pin to ground provides a
reference current for HCSL mode. If LVPECL or LVDS mode chosen,
pin can be leꢀ open
38
40
Iref
Output
Input
Pull-up/
Pulldown
IN1-
Inverted reference input, internal bias to VDD/2
41
44
46
IN1+
Input
Pulldown Reference input 1
Reference output, CMOS
Ref_Out
Sync_OE
Output
Input
Pulldown Synchronous output enable for Ref_Out, see Table 3 for functions
Function Table
Table 1: Input select function
IN_SEL [1]
IN_SEL [0]
Function
0
0
1
0
IN0 is the selected reference input
IN1 is the selected reference input
XTAL is the selected input
1
X
Table 2: Output Mode select function
OPMODEA/B [1]
OPMODEA/B [0]
Output Bank A / Bank B Mode
0
0
1
1
0
1
0
1
LVPECL
LVDS
HCSL
Hi-Z
Table 3: Reference output enable function
Sync_OE
Ref_Out
0
1
Hi-Z
Output enabled
Table 4: Illegal input level function
Input illegal status
Output status
Input open
Logic Low
Logic Low
Logic Low
Input both high
Input both low
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PI6C49S1510A
Document Number DS40482 Rev 2-2
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PI6C49S1510A
Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested)
Note:
Storage temperature...................................................-55 to +150ºC
Stresses greater than those listed under MAXIMUM
Supply Voltage to Ground Potential (VDD, VDDO)... -0.5 to +4.6V
Inputs (Referenced to GND) ............................. -0.5 to VDD+0.5V
Clock Output (Referenced to GND)................. -0.5 to VDD+0.5V
Latch up..................................................................................200mA
ESD Protection (Input) ..................................2000 V min (HBM)
Junction Temperature ................................................. 125 °C max
RATINGS may cause permanent damage to the device. is
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
Power Supply Characteristics and Operating Conditions
Symbol
Parameter
Test Condition
Min.
2.375
2.375
Typ.
Max.
3.465
3.465
120
Units
Core Supply Voltage
Output Supply Voltage
Core Power Supply Current
V
V
VDD
VDDO
IDD
90
All LVPECL outputs unloaded
All LVDS outputs loaded
150
110
80
190
130
120
85
mA
Output Power Supply Current
IDDO
All HCSL outputs unloaded
Ambient Operating Temperature1
PCB Operating Temperature1
-40
-40
°C
°C
TA
TB
105
Note 1: Either TA or TB used as operating condition
DC Electrical Specifications - Differential Inputs
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Units
uA
uA
PF
Input High current
Input Low current
Input capacitance
Input high voltage
Input low voltage
150
IIH
Input = VDD
Input = GND
-150
IIL
3
CIN
VIH
VIL
V
VDD+0.3
-0.3
0.15
V
Input Differential Amplitude
PK-PK
V
VID
VDD-0.85
VDD-0.85
Common model input voltage
MUX isolation
GND + 0.5
V
VCM
ISOMUX
-89
dBc
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PI6C49S1510A
Document Number DS40482 Rev 2-2
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PI6C49S1510A
DC Electrical Specifications - LVCMOS Inputs
Symbol Parameter
Conditions
Min.
Typ.
Max.
Units
Input High current
150
uA
uA
V
IIH
Input = VDD
Input Low current
Input high voltage
Input low voltage
Input high voltage
Input low voltage
Input = GND
-150
2.0
IIL
VIH
VIL
VIH
VIL
VDD=3.3V
VDD=3.3V
VDD=2.5V
VDD=2.5V
VDD+0.3
0.8
-0.3
1.7
V
V
VDD+0.3
0.7
-0.3
V
DC Electrical Specifications- LVPECL Outputs
Parameter
Description
Conditions
Min.
Typ.
Typ.
Max.
Units
Output High voltage
V
VOH
VDDO-1.4
VDDO-0.9
Output Low voltage
V
VOL
VDDO-2.2
VDDO-1.7
DC Electrical Specifications- LVDS Outputs
Parameter
Description
Conditions
Min.
Max.
Units
Output High voltage
Output Low voltage
1.43
1.0
V
V
V
VOH
VOL
Vocm
Output commode voltage
1.25
Change in Vocm between com-
pletely output states
DVocm
50
mV
W
Ro
Output impedance
85
140
DC Electrical Specifications – HCSL Outputs
Parameter
Description
Conditions
Min.
520
Typ.
Max.
900
Units
mV
Output High voltage
Output Low voltage
VOH
VOL
-150
150
mV
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Document Number DS40482 Rev 2-2
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PI6C49S1510A
DC Electrical Specifications – LVCMOS Output
Parameter Description
Conditions
Min.
2.3
Typ.
Max.
Units
V
V
V
V
V
V
V
V
Ω
Ω
VDDO=3.3V +/-5%, IOH = 8mA
DDO=2.5V +/- 5%, IOH = 8mA
VDDO=3.3V +/-5%, IOL = -8mA
DDO=2.5V +/- 5%, IOL = -8mA
VDDO=3.3V +/-5%, IOH = 24mA
DDO=2.5V +/- 5%, IOH = 16mA
VDDO=3.3V +/-5%, IOL = -24mA
DDO=2.5V +/- 5%, IOL = -16mA
Output High voltage
VOH
VOL
VOH
1.5
V
0.5
0.4
Output Low voltage
Output High voltage
V
2.1
1.5
V
1
Output Low voltage
Output Impedance
VOL
RIUT
0.8
V
VDDO = 3.3V 5%
17
22
VDDO = 2.5V 5%
AC Electrical Specifications – Differential Outputs
Parameter Description
Conditions
Min.
Typ.
Max. Units
LVPECL, LVDS
HCSL
1500
MHz
250
Clock output frequency
FOUT
LVPECL
LVDS
120
120
300
120
120
300
150
150
300
Output rise time
Output fall time
From 20% to 80%
From 80% to 20%
300
700
300
300
700
ps
ps
Tr
HCSL
LVPECL
LVDS
150
150
Tf
HCSL
LVPECL,
HCSL
(<250MHz)
48
52
Frequency<650MHz,
VID ≥ 400mV
LVDS
47
45
45
53
55
55
Frequency<1GHz,
VID ≥ 400mV
LVPECL
LVDS
Output duty cycle
%
TODC
Frequency<1.5GHz,
VID ≥ 400mV
LVDS
40
40
60
60
Frequency<1.5GHz, VID
≥ 400mV
LVPECL
LVPECL outputs @ <1GHz
LVPECL outputs @ >1GHz
LVDS outputs @ <1GHz
LVDS outputs @ >1GHz
500
400
250
250
1100
1000
600
Output swing Single-ended
mV
VPP
550
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PI6C49S1510A
Document Number DS40482 Rev 2-2
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PI6C49S1510A
AC Electrical Specifications – Differential Outputs Cont.
Parameter Description
Conditions
Min.
Typ.
Max. Units
156.25MHz, 12kHz to 20MHz
156.25MHz, 10kHz to 1MHz
HCSL
0.02
0.01
460
ps
ps
Buffer additive jitter RMS
T
j
Absolute crossing voltage
mV
VCROSS
Total variation of crossing
voltage
HCSL
140
40
mV
DVCROSS
10 outputs devices, out-
puts in same tank, with
same load, at DUT.
Output Skew
15
ps
TSK
LVPECL, LVDS @ 3.3V, 100MHz
HCSL @ 3.3V, 100MHz
570
900
ps
ps
ns
ns
ps
Propagation Delay
TPD
Valid to HiZ
80
80
TOD
HiZ to valid
Part to Part Skew1
TOE
80
120
TP2P Skew
AC Electrical Specifications – CMOS
Parameter Description
Conditions
Min.
Typ.
Max. Units
XTAL input
Reference input
XTAL input
Reference input
CL = 10pF
10
50
MHz
MHz
ps
Ref_Out frequency
FOUT
200
0.3
0.03
1.5
Buffer additive jitter RMS
T
j
ps
Rise time, Fall time
Output duty cycle
ns
tr/ tf
TODC
tPD
45
55
%
CL = 10pF
Propagation delay
3.3V, 25MHz
2200
ps
Setup time
300
2
ps
tS
Clock edge to output disable
Clock edge to output enable
Ref_Out
Ref_Out
4
4
cycles
cycles
tSOD
2
tSOE
Notes:
1. is parameter is guaranteed by design
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PI6C49S1510A
Document Number DS40482 Rev 2-2
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PI6C49S1510A
Crystal Characteristics
Parameter
Min.
Typ.
Max.
Units
Mode of Oscillation
Frequency Range
Fundamental
10
10
50
70
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Load Capacitance
pF
18
500
pF
Drive Level
µW
Recommended Crystals
Pericom recommends:
a) GC2500003 XTAL 49S/SMD(4.0 mm), 25M, CL=18pF, +/-30ppm
http://www.pericom.com/pdf/datasheets/se/GC_GF.pdf
b) FY2500091, SMD 5x3.2(4P), 25M, CL=18pF, +/-30ppm
http://www.pericom.com/pdf/datasheets/se/FY_F9.pdf
c) FL2500047, SMD 3.2x2.5(4P), 25M, CL=18pF, +/-20ppm
http://www.pericom.com/pdf/datasheets/se/FL.pdf
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PI6C49S1510A
Document Number DS40482 Rev 2-2
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PI6C49S1510A
Propagation Delay
Output Skew
Output Skew T
SK
Propagation Delay T
PD
V
OH
IN+/IN-
V
OL
T
PLHx
T
PHLx
V
OH
IN+/IN-
QA/QB
tPD
t
PD
CLKn
V
OL
V
OH
T
SK
TSK
V
OH
V
OL
CLKn+1
V
OL
t
R
tF
T
PLHy
TPHLy
T
SK = TPLHy - TPLHx or TSK = TPHLy - TPHLx
Part to Part Skew
Part-to-Part Skew
VOH
IN+/IN-
VOL
T
PLH1
T
PHL1
VOH
Part1 CLK
Part2 CLK
V
OL
TSK
T
SK
VOH
VOL
TPLH2
TPHL2
TSK = TPLH2 - TPLH1 or TSK = TPHL2 - TPHL1
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Document Number DS40482 Rev 2-2
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PI6C49S1510A
LVPECL/ LVDS Output Swing vs. Frequency
LVPECL VPP vs Frequency
LVDS VPP vs Frequency
1000
600
500
400
300
200
100
0
800
600
400
200
0
25
100
125
312.5
625
1000
1500
25
100
125
312.5
625
1000
1500
Frequency (MHz)
Frequency (MHz)
2.5V LVPECL
3.3V LVPECL
2.5V LVDS
3.3V LVDS
Propagation Delay vs Temperature
Propagation Delay vs Temperature
1800
1600
1400
1200
1000
800
600
400
200
0
-40
25
85
Temperature (°C)
LVPECL
LVDS
HCSL
CMOS
1.5GHz LVPECL/ LVDS Waveform
3.3V LVPECL Waveform
2.5V LVPECL Waveform
3.3V LVDS Waveform
2.5V LVDS Waveform
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Document Number DS40482 Rev 2-2
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PI6C49S1510A
Phase Noise and Additive Jitter
Output phase noise (Dark Blue) vs Input Phase noise (light blue)
Additive jitter is calculated at 156.25MHz~27fs RMS (12kHz to 20MHz). Additive jitter = √(Output jitter2 - Input jitter2)
Total phase jitter with 25MHz XTAL ~ 264fs RMS (12kHz ~20MHz)
Configuration Test Load Board Termination for LVPECL/ LVDS Outputs
LVPECL/ LVDS Buffer
VDDQx
Z = 50Ω
o
L = 0 ~ 10 in.
100Ω
Z = 50Ω
o
150Ω*
150Ω*
*Remove for LVDS
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PI6C49S1510A
Document Number DS40482 Rev 2-2
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PI6C49S1510A
Configuration Test Load Board Termination for HCSL Outputs
Rs
33Ω
5%
Clock
TLA
DUT
Rs
33Ω
5%
Clock#
TLB
2pF
5%
2pF
5%
Rp
49.9Ω
1%
Rp
49.9Ω
1%
475Ω
1%
Configuration Test Load Board Termination for LVCMOS Outputs
3.3V ±5%
V
V
DD
DDO
10pF
GND
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Document Number DS40482 Rev 2-2
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Application Information
Wiring the differential input to accept single ended levels
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is gener-
ated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and
R2 might need to be adjusted to postion the V_REF in the center of the input voltage swing. For example, if the input clock swing is
only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R1/R2 = 0.609.
VDD
R1
1K
Single Ended
Clock Input
CLK
/CLK
C1
R2
0.1µ
1K
Figure 1. Single-ended input to Differential input device
Power Supply Filtering Techniques
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. All power pins should be individually connected to the power supply plane through vias, and 0.1μF
an 1μF bypass capacitors should be used for each pin.
VDD
VDD
0.1µF
1µF
VDDO
VDDO
0.1µF
1µF
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Document Number DS40482 Rev 2-2
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Single Ended Input, AC couple
Driving X1 with a Single Ended Input
0.1µF
0.1µF
Rs
X1
X2
CMOS
Clock
50Ω
0.1µF
Rs
0.1µF
CMOS
Clock
50Ω
50Ω
Input
50Ω
Differential
Clock
Input
0.1µF
Single Ended Input, DC couple
Single Ended Input, DC couple
VDD
100Ω
Rs
Rs
CMOS
Clock
CMOS
Clock
50Ω
50Ω
VDD
Differential
Clock
100Ω
Differential
Clock
Input
Input
0.1µF
0.1µF
LVPECL, DC Couple, Thevenin Equivalent
LVPECL, AC Couple, Thevenin Equivalent
VDDO
VDDO
RPU
RPD
RPU
0.1µF
QAn+/ QBn+
QAn+/ QBn+
VDDO
VDDO
RPD
RT
LVPECL
Driver
LVPECL
Driver
Clock
Input
LVPECL
Receiver
100Ω Differential
100Ω Differential
0.1µF
RPU
RPD
RPU
RPD
QAn-/ QBn-
QAn-/ QBn-
RT
VDDO RPU RPD
3.3V 120Ω 82Ω
2.5V 250Ω 62.5Ω
VDDO RT RPU RPD
3.3V 160Ω 120Ω 82Ω
2.5V 91Ω 250Ω 62.5Ω
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Document Number DS40482 Rev 2-2
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LVDS DC Couple
LVDS AC Couple at Load
0.1µF
QAn+/ QBn+
QAn+/ QBn+
kΩ
LVDS
Receiver
LVDS
Driver
LVDS
Driver
100Ω Differential
100Ω
Vbias
100Ω Differential
100Ω
kΩ
QAn-/ QBn-
QAn-/ QBn-
0.1µF
LVDS AC Couple with Internal Termination Single Ended LVPECL, DC Couple
VDDO - 2V
0.1µF
50Ω
QAn+/ QBn+
QAn+/ QBn+
50Ω
50Ω
LVDS
Driver
100Ω Differential
Vbias
50Ω
LVPECL
Driver
VDDO - 2V
QAn-/ QBn-
0.1µF
QAn-/ QBn-
50Ω
Single Ended LVPECL, DC Couple, Thevenin
Equivalent
Single Ended LVPECL, AC Couple, Thevenin
Equivalent
VDDO
RPU
0.1µF
Load
QAn+/ QBn+
50Ω
QAn+/ QBn+
50Ω
RT
50Ω
LVPECL
Driver
VDDO
RPD
LVPECL
Driver
0.1µF
VDDO RPU RPD
VDDO RT
3.3V 160Ω
2.5V 91Ω
RPU
3.3V 120Ω 82Ω
QAn-/ QBn-
2.5V 250Ω 62.5Ω
RT
50Ω
QAn-/ QBn-
RPD
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Document Number DS40482 Rev 2-2
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Clock IC Crystal Input Guide
LVPECL/ LVDS AC and DC input
*Remove for LVDS
0.1uF
(For AC Couple Only)
Clock IC
Rf
IN+
150Ω*
Input
Driver
100Ω Differential
100Ω
C_in
XTL_IN
Cb
C_out
XTL_OUT
IN-
0.1uF
(For AC Couple Only)
150Ω*
Cb
C2
Crystal (CL)
C1
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January 2018
© Diodes Incorporated
PI6C49S1510A
Document Number DS40482 Rev 2-2
16
A product Line of
Diodes Incorporated
PI6C49S1510A
Clock IC Crystal loading cap. design guide
CL =crystal spec. loading cap.
C_in/out = (3~5pF) of IC pin cap.
Cb = PCB trace (2~4pF)
Clock IC
Rf
C_in
XTL_IN
Cb
C_out
XTL_OUT
C1,C2 = load cap. of design
Rd = 50 to 100ohm drive level limit
Cb
C2
Crystal (CL)
C1
Design guide: C1=C2=2 *CL - (Cb +C_in/out) to meet target +/-ppm < 20 ppm
Example1: Select CL=18 pF crystal, C1=C2=2*(18pF) – (4pF+5pF)=27pF, check datasheet too
Example2: For higher frequency crystal (=>20MHz), can use formula C1=C2=2*(CL-6), can do fine tune of C1, C2 for more accurate
ppm if necessary
Thermal Information
Symbol
Description
Condition
ΘJA
ΘJC
23.65 °C/W
9.10 °C/W
Junction-to-ambient thermal resistance
Junction-to-case thermal resistance
Still air
Part Marking
ZD Package
PI6C49S
1510AZDIE
YYWWXX
YY : Year
WW : Workweek
1st X : Assembly Site Code
2nd X : Wafer Site Code
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January 2018
© Diodes Incorporated
PI6C49S1510A
Document Number DS40482 Rev 2-2
17
A product Line of
Diodes Incorporated
PI6C49S1510A
Packaging Mechanical: 48-TQFN (ZD)
16-0151
For latest package info.
please check: http://www.diodes.com/design/support/packaging/pericom-packaging/packaging-mechanicals-and-thermal-characteristics/
Ordering Information
Ordering Code
Package Code Package Type
Operating Temperature
PI6C49S1510AZDIEX
ZD
48-Contact, Very in Quad Flat No-Lead (TQFN)
-40 °C to 85 °C
Notes:
1. EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant. All applicable RoHS exemptions applied.
2. See http://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated’s definitions of Halogen- andAntimony-free, “Green” and Lead-free.
Thermal characteristics can be found on the company web site at www.diodes.com/design/support/packaging/
3. E = Pb-free and Green
4. X suffix = Tape/Reel
www.diodes.com
January 2018
© Diodes Incorporated
PI6C49S1510A
Document Number DS40482 Rev 2-2
18
A product Line of
Diodes Incorporated
PI6C49S1510A
IMPORTANT NOTICE
DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER
THE LAWS OF ANY JURISDICTION).
Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other changes without further no-
tice to this document and any product described herein. Diodes Incorporated does not assume any liability arising out of the application or use of this document or
any product described herein; neither does Diodes Incorporated convey any license under its patent or trademark rights, nor the rights of others. Any Customer
or user of this document or products described herein in such applications shall assume all risks of such use and will agree to hold Diodes Incorporated and all
the companies whose products are represented on Diodes Incorporated website, harmless against all damages.
Diodes Incorporated does not warrant or accept any liability whatsoever in respect of any products purchased through unauthorized sales channel.
Should Customers purchase or use Diodes Incorporated products for any unintended or unauthorized application, Customers shall indemnify and hold Diodes
Incorporated and its representatives harmless against all claims, damages, expenses, and attorney fees arising out of, directly or indirectly, any claim of personal
injury or death associated with such unintended or unauthorized application.
Products described herein may be covered by one or more United States, international or foreign patents pending. Product names and markings noted herein
may also be covered by one or more United States, international or foreign trademarks.
This document is written in English but may be translated into multiple languages for reference. Only the English version of this document is the final and determi-
native format released by Diodes Incorporated.
LIFE SUPPORT
Diodes Incorporated products are specifically not authorized for use as critical components in life support devices or systems without the express written approval
of the Chief Executive Officer of Diodes Incorporated. As used herein:
A. Life support devices or systems are devices or systems which:
1. are intended to implant into the body, or
2. support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably
expected to result in significant injury to the user.
B. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or to affect its safety or effectiveness.
Customers represent that they have all necessary expertise in the safety and regulatory ramifications of their life support devices or systems, and acknowledge
and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of Diodes Incorporated
products in such safety-critical, life support devices or systems, notwithstanding any devices- or systems-related information or support that may be provided by
Diodes Incorporated. Further, Customers must fully indemnify Diodes Incorporated and its representatives against any damages arising out of the use of Diodes
Incorporated products in such safety-critical, life support devices or systems.
Copyright © 2016, Diodes Incorporated
www.diodes.com
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January 2018
© Diodes Incorporated
PI6C49S1510A
Document Number DS40482 Rev 2-2
19
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