PI6LC48P25104LIE [DIODES]

Clock Generator, 187.5MHz, CMOS, PDSO8, 0.173 INCH, GREEN, MO-153F/AA, TSSOP-8;


型号：	PI6LC48P25104LIE
厂家：	DIODES INCORPORATED
描述：	Clock Generator, 187.5MHz, CMOS, PDSO8, 0.173 INCH, GREEN, MO-153F/AA, TSSOP-8 时钟光电二极管外围集成电路晶体
文件：	总7页 (文件大小：629K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PI6LC48P25104

Single Output LVPECL Clock Generator

Features

Description

ꢀÎSingle diﬀerential LVPECL output

ꢀÎOutput frequency range: 145MHz to 187.5MHz

e PI6LC48P25104 is a single output LVPECL synthesizer

optimized to generate Ethernet reference clock frequencies and

is a member of Pericom’s HiFlex family of high performance

clock solutions. Using a 25MHz, it can generate 156.25MHz, or

187.5MHz output. Using other crystal frequencies, it can gener-

ate other popular frequencies for networking and server storage

systems.

ꢀÎRMS phase jitter @ 156.25MHz, using a 25MHz crystal

(12kHz - 20MHz): 0.3ps (typical)

ꢀÎFull 3.3V or 2.5V supply modes

ꢀÎCommercial and industrial operating temperature

ꢀÎAvailable in lead-free package: 8-TSSOP

e PI6LC48P25104 uses Pericom’s proprietary low phase noise

PLL technology to achieve ultra low phase jitter, so it is ideal for

SATA/SAS or Ethernet interface in all kind of systems.

Applications

ꢀÎNetworking systems

ꢀÎServers and Storage systems

Block Diagram

Pin Configuration

XTAL_IN

CLK

OSC

VDDA

GND

VDD

PFD

VCO

XTAL_OUT

CLK#

CLK

XTAL_OUT

XTAL_IN

CLK#

Freq_SEL

www.pericom.com

PI6LC48P25104

Rev. A

07/08/2013

13-0109

PI6LC48P25104

Single Output LVPECL Clock Generator

Pinout Table

Pin No. Pin Name

I/O Type

Description

VDDA

GND

Power

Analog Power Supply

Ground

XTAL_OUT,

XTAL_IN

3, 4

Crystal

Input

Crystal Input and Output

Pull

Down

"LOW", output is multiplied by 6.25, "HIGH", output is multiplied by

7.5.

Freq_SEL

6, 7

CLK#, CLK

VDD

Output

Power

Output Clock

Core Power Supply

Output Frequency Table

Xtal Frequency (MHz)

Freq_SEL

Output Frequency (MHz)

150

21.25

159.375

150

156.25

187.5

159.375

187.5

25.5

Typical Crystal Requirement

Parameter

Minimum

Typical

Maximum

Units

Mode of Oscillation

Fundamental

Freq_SEL = 0

Freq_SEL = 1

23.2

Frequency

MHz

19.33

Equivalent Series Resistance

(ESR)

Shunt Capacitance

Drive Level

Recomended Crystal Specification

Pericom recommends:

a) FL2500047, SMD 3.2x2.5(4P), 25MHz, CL=18pF, +/-20ppm

http://www.pericom.com/pdf/datasheets/se/FL.pdf

b) b) FY2500091, SMD 5x3.2(4P), 25MHz, CL=18pF, +/-30ppm

http://www.pericom.com/pdf/datasheets/se/FY_F9.pdf

www.pericom.com

PI6LC48P25104

Rev. A

07/08/2013

13-0109

PI6LC48P25104

Single Output LVPECL Clock Generator

Maximum Ratings (Over operating free-air temperature range)

Note:

Stresses greater than those listed under MAXIMUM

Storage Temperature.............................................. -65ºC to+155ºC

Ambient Temperature with Power Applied.........-40ºC to+85ºC

3.3V Analog Supply Voltage......................................-0.5 to +3.6V

ESD Protection (HBM) ......................................................... 2000V

RATINGS may cause permanent damage to the device. is

is a stress rating only and functional operation of the device

at these or any other conditions above those indicated in

the operational sections of this speciﬁcation is not implied.

Exposure to absolute maximum rating conditions for

extended periods may aﬀect reliability.

DC Electrical Characteristics

Power Supply DC Characterisitcs, (V_DD= V_DDA, T_A= -40 to 85ºC)

Symbol

Parameter

Condition

Min.

3.135

2.375

Typ

3.3

Max

Units

Core, Analog Supply Voltage

Power Supply Current

3.465

2.625

V_DD,V_DDA

I_GND

2.5

Analog Supply Current

I_DDA

LVPECL DC Electrical Characteristics

Symbol

Parameter

Condition

V_DD= 3.3V

V_DD= 2.5V

V_DD= 3.3V

V_DD= 2.5V

Min.

1.9

Typ

Max

2.4

Units

Output High Voltage⁽¹⁾

V_OH

1.1

1.6

1.2

1.6

Output Low Voltage⁽¹⁾

V_OL

0.4

0.8

Note: 1. LVPECL Termination: Source 150ohm to GND and 100ohm across CLK and CLK#.

LVPECL AC Electrical Characteristics

LVPECL Termination: Source 150ohm to GND and using 0.01uF ac-coupled to 50ohm to GND

Symbol

Parameter

Condition

Min..

Typ.

Max

Units

Output Frequency

145

125

0.30

0.33

187.5

MHz

f_OUT

156.25MHz, (12kHz - 20MHz)

187.5MHz, (12kHz - 20MHz)

20% to 80%

RMS Phase Jitter,

(Random)⁽¹⁾

t_jit(Ø)

Output Rise/Fall Time

Output Duty Cycle

400

t_R/ t_F

o_DC

Note:

1. Please refer to the Phase Noise Plots.

www.pericom.com

PI6LC48P25104

Rev. A

07/08/2013

13-0109

PI6LC48P25104

Single Output LVPECL Clock Generator

Phase Noise Plots

f_OUT= 187.5MHz

f_OUT= 156.25MHz

LVPECL Test Circuit

www.pericom.com

PI6LC48P25104

Rev. A

07/08/2013

13-0109

PI6LC48P25104

Single Output LVPECL Clock Generator

Power Supply Filtering Techniques

As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter perfor-

mance, power supply isolation is required. e PI6LC48P25104 provides separate power supplies to isolate any high switching noise

from the outputs to the internal PLL. V_DDand V_DDAshould be individually connected to the power supply plane through vias, and

0.1μF bypass capacitors should be used for each pin. Figure below illustrates this for a generic V_DDpin and also shows that V_DDA

requires that an additional 10Ω resistor along with a 10μF bypass capacitor be connected to the V_DDApin.

Crystal Input Interface

e clock generator has been characterized with 18pF parallel resonant crystals. e capacitor values shown in the ﬁgure below

were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error.

www.pericom.com

PI6LC48P25104

Rev. A

07/08/2013

13-0109

PI6LC48P25104

Single Output LVPECL Clock Generator

LVCMOS to XTAL Interface

e XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram

is shown in the ﬁgure below. e XTAL_OUT pin can be leꢀ ꢁoating. e input edge rate can be as slow as 10ns. For LVCMOS

signals, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with

the power rail and to reduce noise. is conﬁguration requires that the output impedance of the driver (Ro) plus the series resis-

tance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in

half. is can be done in one of the two ways. First, R1 and R2 in parallel should equal the transmission line empedance. For most

50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. By overdriving the

crystal oscillator, the device will be functional, but note, the device performance is quaranteed by using a quartz crystal.

Thermal Information

Symbol

Q_JA

Description

Condition

Junction-to-ambient thermal resistance

Junction-to-case thermal resistance

Still air

124.0 ^OC/W

37.0 ^OC/W

Q_JC

www.pericom.com

PI6LC48P25104

Rev. A

07/08/2013

13-0109

PI6LC48P25104

Single Output LVPECL Clock Generator

Packaging Mechanical: 8-Contact TSSOP (L)

DATE: 05/03/12

DESCRIPTION: 8 pin, 173mil wide TSSOP

Notes:

1. Refer JEDEC MO-153F/AA

2. Controlling dimensions in millimeters

3. Package outline exclusive of mold flash and metal burr

PACKAGE CODE: L

DOCUMENT CONTROL #: PD-1308

REVISION: F

12-0370

Ordering Information

Ordering Code

Packaging Type

Package Description

Operating Temperature

PI6LC48P25104LE

PI6LC48P25104LIE

Pb-free & Green, 8-pin TSSOP

Commercial

Industrial

Notes:

•ꢀ ermal characteristics can be found on the company web site at www.pericom.com/packaging/

•ꢀ "E" denotes Pb-free and Green

•ꢀ Adding an "X" at the end of the ordering code denotes tape and reel packaging

Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com

www.pericom.com

PI6LC48P25104

Rev. A

07/08/2013

13-0109

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