HMN5128DVLF-85 [DLGHANBIT]

Non-Volatile SRAM MODULE 4Mbit (512K x 8-Bit),32Pin-DIP, 3.3V;


型号：	HMN5128DVLF-85
厂家：	DLG HANBIT
描述：	Non-Volatile SRAM MODULE 4Mbit (512K x 8-Bit),32Pin-DIP, 3.3V 静态存储器
文件：	总6页 (文件大小：564K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DLGHANBIT

DLGHANBIT Confidential

HMN5128DV

Non-Volatile SRAM MODULE 4Mbit (512K x 8-Bit),32Pin-DIP, 3.3V

Part No. HMN5128DV

GENERAL DESCRIPTION

The HMN5128DV Nonvolatile SRAM is a 4,194,304-bit static RAM organized as 524,288 bytes by 8 bits.

The HMN5128DV has a self-contained lithium energy source provide reliable non-volatility coupled with the unlimited write

cycles of standard SRAM and integral control circuitry which constantly monitors the single 3.3V supply for an out-of-

tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on to sustain the

memory until after Vcc returns valid and write protection is unconditionally enabled to prevent garbled data. In addition the

SRAM is unconditionally write-protected to prevent an inadvertent write operation. At this time the integral energy source is

switched on to sustain the memory until after V_CCreturns valid.

The HMN5128DV uses extremely low standby current CMOS SRAM’s, coupled with small lithium coin cells to provide non-

volatility without long write-cycle times and the write-cycle limitations associated with EEPROM.

FEATURES

 Access time : 70, 85ns

PIN ASSIGNMENT

 High-density design : 4Mbit Design

 Battery internally isolated until power is applied

 Industry-standard 32-pin 512K x 8 pinout

 Unlimited write cycles

A₁₈

A₁₆

A₁₄

A₁₂

A₇

A₆

A₅

A₄

A₃

A₂

A₁

A₀

DQ₀

DQ₁

DQ₂

V_SS

V_CC

A₁₅

A₁₇

/WE

A₁₃

A₈

A₉

A₁₁

/OE

A₁₀

/CE

DQ₇

DQ₆

DQ₅

DQ₄

DQ₃

 Data retention in the absence of V_CC

 5-years typical data retention in absence of power

 Automatic write-protection during power-up/power-down

cycles

 Data is automatically protected during power loss

 Conventional SRAM operation; unlimited write cycles

OPTIONS

 Timing

70 ns

MARKING

32-pin Encapsulated Package

-70

-85

85 ns

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HMN5128DV

FUNCTIONAL DESCRIPTION

The HMN5128DV executes a read cycle whenever /WE is inactive(high) and /CE /OE are active(low). The address

specified by the address inputs(A₀-A₁₈) defines which of the 524,288 bytes of data is accessed. Valid data will be available

to the eight data output drivers within t_ACC(access time) after the last address input signal is stable.

When power is valid, the HMN5128DV operates as a standard CMOS SRAM. During power-down and power-up cycles,

the HMN5128DV acts as a nonvolatile memory, automatically protecting and preserving the memory contents.

The HMN5128DV is in the write mode whenever the /WE and /CE signals are in the active (low) state after address inputs

are stable. The later occurring falling edge of /CE or /WE will determine the start of the write cycle. The write cycle is

terminated by the rising edge of /CE or /WE. All address inputs must be kept valid throughout the write cycle. /WE must

return to the high state for a minimum recovery time (t_WR) before another cycle can be initiated. The /OE control signal

should be kept inactive (high) during write cycles to avoid bus contention. However, if the output bus been enabled (/CE

and /OE active) then /WE will disable the outputs in t_ODWfrom its falling edge.

The HMN5128DV provides full functional capability for Vcc greater than 3.0 V and write protects by 2.8 V nominal. Power-

down/power-up control circuitry constantly monitors the Vcc supply for a power-fail-detect threshold V_PFD. When V_CCfalls

below the V_PFDthreshold, the SRAM automatically write-protects the data. All inputs to the RAM become “don’t care” and

all outputs are high impedance. As Vcc falls below approximately 2.5 V, the power switching circuit connects the lithium

energy soure to RAM to retain data. During power-up, when Vcc rises above approximately 2.5 volts, the power switching

circuit connects external Vcc to the RAM and disconnects the lithium energy source. Normal RAM operation can resume

after Vcc exceeds 3.0 volts.

BLOCK DIAGRAM

PIN DESCRIPTION

A₀-A₁₈: Address Input

A₀-A₁₈

/OE

/WE

512K x 8

SRAM

Block

/CE : Chip Enable

DQ₀-DQ₇

V_ss: Ground

Power

/CE _CON

DQ₀-DQ₇: Data In / Data Out

/WE : Write Enable

/OE : Output Enable

/CE

V_CC

Power – Fail

Control

Lithium

Cell

NC : No Connection

V_CC: Power (+3.3V)

URL : www.dlghb.co.kr

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HMN5128DV

TRUTH TABLE

MODE

/OE

/CE

/WE

I/O OPERATION

High Z

POWER

Standby

Active

Not selected

Output disable

Read

High Z

D_OUT

Active

Write

D_IN

Active

ABSOLUTE MAXIMUM RATINGS

PARAMETER

SYMBOL

RATING

CONDITIONS

DC voltage applied on V_CCrelative to V_SS

DC Voltage applied on any pin excluding V_CC

relative to V_SS

V_CC

-0.5V to Vcc+0.5

V_T≤V_CC+0.3

V_T

-0.3V to 4.6V

Operating temperature

T_OPR

T_STG

0 to 70C

Storage temperature

-30C to 80C

NOTE: Permanent device damage may occur if Absolute Maximum Ratings are exceeded.

Functional operation should be restricted to the Recommended DC Operating Conditions detailed in this data sheet.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Not recommend direct soldering by soldering machine, recommend by manual soldering or using socket.

RECOMMENDED DC OPERATING CONDITIONS ( T_A= T_OPR

)

PARAMETER

SYMBOL

MIN

3.0V

TYPICAL

MAX

3.6V

Supply Voltage

V_CC

3.3V

Ground

V_SS

Input high voltage

Input low voltage

V_IH

2.2

Vcc+0.3V

0.6V

V_IL

-0.3

NOTE: Typical values indicate operation at T_A= 25℃

DC ELECTRICAL CHARACTERISTICS (T_A= T_OPR, V_CCmin V_CC≤ V_CCmax

)

PARAMETER

CONDITIONS

SYMBOL

MIN

TYP.

MAX

UNIT

±2.0

Input Leakage Current

V_IN=V_SSto V_CC

I_LI

A

/CE=V_IHor /OE=V_IH

or /WE=V_IL

±2.0

Output Leakage Current

I_LO

A

Output high voltage

Output low voltage

I_OH=-1.0mA

V_OH

V_OL

2.4

I_OL= 2.0mA

0.4

Threshold Select Voltage

Power-fail Deselect Voltage

Standby supply current

V_PFD

I_SB

2.8

2.9

3.0

0.3

(THS = V_SS

/CE=V_IH

)

㎃

/CE≥V_CC-0.2V,

0V≤V_IN≤0.2V,

or V_IN≥V_CC-0.2V

Standby supply current

I_SB1

A

Min.cycle,duty=100%,

/CE=V_IL, I_I/O=0㎃,

㎃

Operating supply current

Supply switch-over voltage

I_CC

A₁₇< V_ILor A₁₇> V_IH,

A₁₈< V_ILor A₁₈> V_IH

V_SO

2.5

NOTE: Typical values indicate operation at T_A= 25℃.

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HMN5128DV

READ CYCLE (T_A= T_OPR, V_CCmin V_CC≤ V_CCmax

)

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNIT

Read Cycle Time

Address access Time

t_RC

t_ACC

t_ACE

t_OE

Chip enable access time

Output enable to output valid

Chip enable to output in high Z

Output enable to output high Z

Output hold from address change

Output enable end to chip select end

t_CHZ

t_OHZ

t_OH

t_OETCE

WRITE CYCLE (T_A= T_OPR, V_ccmin V_cc≤ V_ccmax

)

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNIT

Write Cycle Time

Chip enable to end of write

Address setup time

t_WC

t_CW

t_AS

Address valid to end of write

Write pulse width

t_AW

t_WP

Write recovery time

t_WR

t_DW

Data valid to end of write

Data hold from write time

Output active from end of write

Write end to chip enable end

t_DH

t_OW

t_WETCE

NOTE: 1. A write ends at the transition of /WE low to high.

POWER-DOWN/POWER-UP CYCLE

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP.

MAX

UNIT

㎲

V_PFD(max) to V_PFD(min) V_CCFail Time

V_PFD(max) to V_SSV_CCFail Time

V_PFD(max) to V_PFD(min) V_CCRise Time

t_F

t_FB

t_R

300

150

Delay after Vcc slews down

past V_PFDbefore SRAM is

Write-protected.

㎲

Write Protect Time

t_WPT

250

Chip Enable Recovery

t_CER

t_RB

120

㎲

V_SSto V_PFD(min) V_CCRise Time

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Rev.1.3 (Apr. 2009)

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TIMING WAVEFORM

- Read Cycle

DLGHANBIT Confidential

HMN5128DV

t_RC

Address

t_OD

t_ACC

t_OETCE

/CE

/OE

t_ACE

t_OE

t_OHZ

Data Valid

t_OH

_OUT

High-Z

- Write Cycle

t_WC

Address

t_WR

t_WETCE

t_AW

t_CW

/CE

t_AS

t_WP

/WE

t_DW

t_DH

D_IN

Data-in Valid

t_OW

High-Z

D_OUT

Data Undefined (1)

POWER-DOWN/POWER-UP TIMING

V_CC

t_PF

4.75

V_PFD

4.25

V_SO

t_FS

t_PU

t_CER

t_DR

t_WPT

/CE

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HMN5128DV

PACKAGE DIMENSION

Dimension

Min

Max

1.650

0.700

0.365

0.012

0.008

0.590

0.017

0.090

0.075

0.150

1.710

0.760

0.380

0.013

0.630

0.023

0.110

0.190

All dimensions are in inches.

ORDERING INFORMATION

H M N 5128 D V LF – 70

Speed options : 70 = 70 ns

85 = 85 ns

LF : Lead Free

3.3V Operating, Dip type package

Device : 512K x 8 bit

Nonvolatile SRAM

HANBit Memory Module

7F(#712), 274, Samsung-ro, Suwon-si, Gyeonggi-do, South Korea

TEL : (+82) 31-211-2523 , FAX : (+82) 31-211-2524

EMAIL : dlghbinfo@dlghb.co.kr

http://www.dlghb.co.kr

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Rev.1.3 (Apr. 2009)

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