HMNR88DV [DLGHANBIT]

5.0 or 3.3V, 64K bit (8 Kbit x 8) TIMEKEEPER NVSRAM;


型号：	HMNR88DV
厂家：	DLG HANBIT
描述：	5.0 or 3.3V, 64K bit (8 Kbit x 8) TIMEKEEPER NVSRAM 静态存储器
文件：	总12页 (文件大小：741K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DLGHANBIT

DLGHANBIT Confidential

HMNR88D(V)

5.0 or 3.3V, 64K bit (8 Kbit x 8) TIMEKEEPER NVSRAM

Part No. HMNR88D(V)

GENERAL DESCRIPTION

The HMNR88D(V) TIMEKEEPER SRAM is a 8Kbit x 8 non-volatile static RAM and real time clock organized as 8,192

words by 8 bits. The special DIP package provides a fully integrated battery back-up memory and real time clock solution.

The HMNR88D(V) directly replaces industry standard 8Kbit x 8 SRAMs. It also provides the non-volatility of Flash without

any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed.

FEATURES

■ INTEGRATED LOW POWER SRAM, REAL TIME CLOCK, POWER-FAIL CONTROL CIRCUIT, BATTERY and

CRYSTAL

■ BCD CODED YEAR, MONTH, DAY, DATE, HOURS, MINUTES, and SECONDS

■ AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION VOLTAGES :

(V_PFD= Power-fail Deselect Voltage)

– HMNR88D(V) : V_CC= 4.5 to 5.5V

4.1V ≤ V_PFD≤ 4.5V

– HMNR88D(V)V: V_CC= 3.0 to 3.6V

2.7V ≤ V_PFD≤ 3.0V

■ CONVENTIONAL SRAM OPERATION : UNLIMITED WRITE CYCLES

■ SOFTWARE CONTROLLED CLOCK CALIBRATION FOR HIGH ACCURACY APPLICATIONS

■ 5 YEARS OF DATA RETENTION and CLOCK OPERATION IN THE ABSENCE OF POWER PIN and FUNCTION

COMPATIBLE WITH INDUSTRY STANDARD 8K x 8 SRAMS

■ SELF-CONTAINED BATTERY and CRYSTAL IN DIP PACKAGE

PIN ASSIGNMENT

OPTIONS

 Timing

70 ns

MARKING

/RST

A₁₂

A₇

V_CC

/WE

-70

-85

85 ns

A₈

A₆

A₉

A₅

A₁₁

A₄

/OE

A₁₀

A₃

A₂

A₁

A₀

/CE

DQ₇

DQ₆

DQ₅

DQ₄

DQ₃

DQ₀

DQ₁

DQ₂

V_SS

28-pin Encapsulated Package

URL : www.dlghb.co.kr

Rev. 1.3 (Apr, 2009)

DLG HANBIT Co.,Ltd

DLGHANBIT

DLGHANBIT Confidential

HMNR88D(V)

FUNCTIONAL DESCRIPTION

The HMNR88D(V) is a full function, year 2000 compliant (Y2KC), real–time clock/calendar (RTC) and 8k x 8 non-volatile

static RAM. User access to all registers within the HMNR88D(V) is accomplished with a bytewide interface . The Real-time

clock (RTC) information and control bits reside in the sixteen upper most RAM locations. The RTC registers contain

century, year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the date of

each month and leap year are made automatically. The RTC clock registers are double buffered to avoid access of

incorrect data that can occur during clock update cycles. The double buffered system also prevents time loss as the

timekeeping countdown continues unabated by access to time register data. The HMNR88D(V) also contains its own

power-fail circuitry which deselects the device when the V_CCsupply is in an out of tolerance condition. This feature

prevents loss of data from unpredictable system operation brought on by low V_CCas errant access and update cycles are

avoided.

BLOCK DIAGRAM

16 x 8

OSCILLATOR AND

TIMEKEEPER

CLOCK CHAIN

32.768KHz

CRYSTAL

A0 ~ A12

POWER

8,176 x 8

SRAM ARRAY

DQ0 ~ DQ7

LITHIUM

CELL

V_PFD

/CE

/OE

/WE

VOLTAGE SENSE

AND

SWITCHING

CIRCURITY

Vcc

/RST

Vss

A0-A12 : Address Input

/WE : Write Enable

/OE : Output Enable

/CE : Chip Enable, Low Active

DQ0-DQ7 : Data In / Data Out

V_CC: Power (+5V or +3.3V)

V_ss: Ground

NC : No Connection

/RST : Reset Output (Open drain)

URL : www.dlghb.co.kr

Rev. 1.3 (Apr, 2009)

DLG HANBIT Co.,Ltd

DLGHANBIT

DLGHANBIT Confidential

HMNR88D(V)

Absolute Maximum Ratings

Symbol

Parameter

Value

Unit

°C

T_A

AmbientOperatingTemperature

Storage Temperature(Vcc Off, Oscillator Off)

Lead Solder Temperature for 10 seconds

Input or Output Voltage

0 to 70

T_STG

-30 to 70

260

°C

(1)

T_SLD

V_IO

-0.3 to Vcc+0.3

4.5 to 5.5

3.0 to 3.6

HMNR88D

Supply Voltage

V_CC

HMNR88DV

I_O

Output Current

P_D

Power Dissipation

Note : Permanent device damage may occur if Absolute Maximum Ratings are exceeded.

Functional operation should be restricted to the Recommended DC Operating Conditions detailed in this data sheet.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Not recommend direct soldering by soldering machine, and recommend manual soldering or using socket.

Caution : Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.

Operating and AC Measurement Conditions

Parameter

V_CCSupply Voltage

HMNR88D

4.5 to 5.5

0 to 70

100

HMNR88DV

3.0 to 3.6

0 to 70

Unit

Ambient Operating Temperature

Load Capacitance (C_L)

°C

Input Rise and Fall Times

Input Pulse Voltages

≤ 5

0 to 3

1.5

0 to 3

1.5

Input and Output Timing Ref. Voltages

DC Characteristics

HMNR88D

Typ

HMNR88DV

Symbol

Parameter

Test Condition ⁽¹⁾

Unit

Min

Max

Min

Typ

Max

±1

I_LI

0V ≤ V_IN≤ V_CC

0V ≤V_OUT≤ V_CC

Outputs open

/CE=V_IH

Input Leakage Current

Output Leakage Current

Supply Current

(2)

I_LO

I_CC

I_CC1

I_CC2

Supply Current (Standby) TTL

Supply Current (Standby) CMOS

Battery Current OSC ON

Battery Current OSC

OFF

/CE=V_CC-0.2

575

100

800

575

800

I_BAT

100

V_IL

V_IH

V_OL

Input Low Voltage

-0.3

2.2

0.8

VCC+

0.3

-0.3

2.0

0.8

VCC+

0.3

Input High Voltage

Output Low Voltage

I_OL=2.1mA

0.4

URL : www.dlghb.co.kr

Rev. 1.3 (Apr, 2009)

DLG HANBIT Co.,Ltd

DLGHANBIT

DLGHANBIT Confidential

HMNR88D(V)

Output Low Voltage

I_OL=10mA

0.4

(open drain) (4)

V_OH

V_OHB

I_OUT1

I_OUT2

V_PFD

I_OH=-1.0mA

I_OUT2=-1.0uA

Output High Voltage

2.4

2.0

2.4

2.0

V_OHBattery Back-up

3.6

100

4.5

3.6

V_OUT1> V_CC-0.3

V_OUT2>V_BAT-0.3

V_OUTCurrent (Active)

V_OUTCurrent (Battery Back-up)

Power-fail Deselect Voltage

100

3.0

4.1

4.35

3.0

2.7

2.9

V_PFD

Battery Back-up

V_SO

100

3.0

Switchover Voltage

V_BAT

Battery Voltage

3.0

Note: 1. Valid for Ambient Operating Temperature: TA =0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).

2. Outputs deselected.

OPERATING MODES

The 28-pin, 600mil DIP Hybrid houses a controller chip, SRAM, quartz crystal, and a long life lithium button cell in a single

package. The clock locations contain the year, month, date, day, hour, minute, and second in 24 hour BCD format.

Corrections for 28, 29 (leap year-compliant until the year 2100), 30, and 31 day months are made automatically. Byte

1FF8h is the clock control register. This byte controls user access to the clock information and also stores the clock

calibration setting. The seven clock bytes (1FFFh-1FF9h) are not the actual clock counters, they are memory locations

consisting of READ/WRITE memory cells within the static RAM array. The HMNR88D(V) includes a clock control circuit

which updates the clock bytes with current information once per second. The information can be accessed by the user in

the same manner as any other location in the static memory array. The HMNR88D(V) also has its own Power-Fail Detect

circuit. This control circuitry constantly monitors the supply voltage for an out of tolerance condition.

When V_CCis out of tolerance, the circuit write protects the TIMEKEEPER register data and SRAM, providing data security

in the midst of unpredictable system operation. As V_CCfalls, the control circuitry automatically switches to the battery,

maintaining data and clock operation until valid power is restored.

Operating Modes

Mode

Deselect

WRITE

READ

VCC

/CE

VIH

VIL

/OE

/WE

DQ7 – DQ0

High-Z

DIN

Power

Standby

Active

4.5V to 5.5V

VIL

VIH

VIL

VIH

DOUT

High

Active

3.0V to 3.6V

READ

Active

CMOS

Deselect

V_SOto V_PFD(min)

High

Standby

Battery Back-

≤V_SO(1)

Note : X = V_IHor V_IL; V_SO= Battery Back-up Switchover Voltage.

URL : www.dlghb.co.kr

Rev. 1.3 (Apr, 2009)

DLG HANBIT Co.,Ltd

DLGHANBIT

DLGHANBIT Confidential

HMNR88D(V)

READ Mode

The HMNR88D(V) is in the READ Mode whenever /WE (WRITE Enable) is high and /CE /OE are low. The unique

address specified by the 13 Address Inputs defines which one of the 8,192 bytes of data is to be accessed. Valid data will

be available at the Data I/O pins within Address Access Time (t_AVQV) after the last address input signal is stable, providing

the /CE and /OE access times are also satisfied. If the /CE and /OE access times are not met, valid data will be available

after the latter of the Chip Enable Access Times (t_ELQV) or Output Enable Access Time (t_GLQV). The state of the eight three-

state Data I/O signals is controlled by /CE and /OE. If the outputs are activated before t_AVQV, the data lines will be driven to

an indeterminate state until t_AVQV. If the Address Inputs are changed while /CE and /OE remain active, output data will

remain valid for Output Data Hold Time (t_AXQX) but will go indeterminate until the next Address Access.

READ Mode AC Waveforms

/CE

/OE

Note : /WE = High.

READ Mode AC Characteristics

HMNR88D

-70

HMNR88D(V)V

-85

Symbol

Parameter

Unit

Min

Max

Min

Max

t_AVAV

t_AVQV

t_ELQV

t_GLQV

t_ELQX

t_GLQX

t_EHQZ

t_GHQZ

t_AXQX

READ Cycle Time

Address Valid to Output Valid

Chip Enable Low to Output Valid

Output Enable Low to Output Valid

Chip Enable Low to Output Transition

Output Enable Low to Output Transition

Chip Enable High to Output Hi-Z

Output Enable High to Output Hi-Z

Address Transition to Output Transition

Note: 1.Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).

2. CL = 5pF.

URL : www.dlghb.co.kr

Rev. 1.3 (Apr, 2009)

DLG HANBIT Co.,Ltd

DLGHANBIT

DLGHANBIT Confidential

HMNR88D(V)

WRITE Mode

The HMNR88D(V) is in the WRITE Mode whenever /WE (WRITE Enable) and /CE (Chip Enable) are low state after the

address inputs are stable. The start of a WRITE is referenced from the latter occurring falling edge of /WE or /CE. A

WRITE is terminated by the rising edge of /WE. The addresses must be held valid throughout the cycle. /CE must

return high for a minimum of t_EHAXand /WE must return high for a minimum of t_WHAXfrom write cycle enable prior to the

initiation of another READ or WRITE cycle. Data-in must be valid t_DVWHprior to the end of WRITE and remain valid for

t_WHDXafterward. /OE should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has

been activated by a low on /CE and /OE a low on /WE will disable the outputs t_WLQZafter /WE falls.

WRITE AC Waveforms, WRITE Enable Controlled

WRITE Mode AC Characteristics

HMNR88D

-70

HMNR88DV

-85

Symbol

Parameter⁽¹⁾

Unit

Min

Max

Min

Max

t_AVAV

t_AVWL

t_AVEL

WRITE Cycle Time

Address Valid to WRITE Enable Low

Address Valid to Chip Enable Low

WRITE Enable Pulse Width

t_WLWH

t_ELEH

t_WHAX

t_EHAX

t_DVWH

Chip Enable Low to Chip Enable High

WRITE Enable High to Address Transition

Chip Enable High to Address Transition

Input Valid to WRITE Enable High

t_WHDX

WRITE Enable High to Input Transition

WRITE Enable Low to Output High-Z

Address Valid to WRITE Enable High

(2)

t_WLQZ

t_AVWH

URL : www.dlghb.co.kr

Rev. 1.3 (Apr, 2009)

DLG HANBIT Co.,Ltd

DLGHANBIT

DLGHANBIT Confidential

HMNR88D(V)

(2)

t_WHQX

WRITE Enable High to Output Transition

t_EHAX

t_WHAX

Chip Enable High to Address Transition

Write Enable High to Address Transition

Note :

1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).

2. CL = 5pF.

3. If /CE goes low simultaneously with /WE going low, the outputs remain in the high impedance state.

Data Retention Mode

With valid V_CCapplied, the HMNR88D(V) operates as a conventional Bytewide static RAM. Should the supply voltage

decay, the RAM will automatically deselect, write protecting itself when V_CCfalls between V_PFD(max), V_PFD(min) window.

All outputs become high impedance and all inputs are treated as “Don't care.”

Note : A power failure during a WRITE cycle may corrupt data at the current addressed location, but does not jeopardize

the rest of the RAM's content. At voltages below V_PFD(min), the memory will be in a write protected state, provided the V_CC

fall time is not less than t_F. The HMNR88D(V) may respond to transient noise spikes on V_CCthat cross into the deselect

window during the time the device is sampling V_CC. Therefore, decoupling of the power supply lines is recommended.

When V_CCdrops below V_SO, the control circuit switches power to the internal battery, preserving data and powering the

clock. The internal energy source will maintain data in the HMNR88D(V) for an accumulated period of at least 10 years at

room temperature. As system power rises above V_SO, the battery is disconnected, and the power supply is switched to

external V_CC. Write protection continues until V_CCreaches V_PFD(min) plus t_REC(min). Normal RAM operation can resume

t_RECafter V_CCexceeds V_PFD(max).

Power Down/Up Mode AC Waveforms

URL : www.dlghb.co.kr

Rev. 1.3 (Apr, 2009)

DLG HANBIT Co.,Ltd

DLGHANBIT

DLGHANBIT Confidential

HMNR88D(V)

Power Down/Up AC Characteristics

Symbol

Parameter

V_PFD(max) to V_PFD(min) V_CCFall Time

HMNR88D

HMNR88DV

V_PFD(min) to V_PFD(max) V_CCRise Time

Min

300

Max

Unit

(2)

t_F

(3)

t_FB

V_PFD(min) to V_SSV_CCFall Time

150

t_R

t_REC

t_RB

V_PFD(max) to RST High

200

V_SSto V_PFD(min) V_CCRise Time

Note :

1. Valid for Ambient Operating Temperature: T_A= 0 to 70°C; V_CC= 4.5 to 5.5V or 3.0 to 3.6V (except where noted).

2. V_PFD(max) to V_PFD(min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after

V_CCpasses V_PFD(min).

3. V_PFD(min) to V_SSfall time of less than t_FBmay cause corruption of RAM data.

Power Down/Up Trip Points DC Characteristics

Symbol

Parameter^(1,2)

Min

4.1

2.7

Typ

Max

4.5

Unit

HMNR88D

HMNR88DV

HMNR88D

HMNR88DV

4.35

V_PFD

Power-fail Deselect Voltage

2.9

3.0

V_PFD-100mV

V_SO

Battery Back-up Switchover Voltage

(3)

T_DR

Expected Data Retention Time

YEARS

Note:

1. All voltages referenced to V_SS

2. Valid for Ambient Operating Temperature: T_A= 0 to 70°C; V_CC= 4.5 to 5.5V or 3.0 to 3.6V (except where noted).

3. At 25°C.

Data

Funtion /

Address

Range BCD Format

1FFFh

1FFEh

1FFDh

1FFCh

1FFBh

1FFAh

1FF9h

1FF8h

10Years

Year

00-99

01-12

01-31

01-07

00-23

00-59

10M

Month

Date : Day of Month

Day

Month

Date

10 Date

Day

10 Hours

10 Minutes

Hours(24 Hour Format)

Minutes

Hours

Minutes

Seconds

Control

10 Seconds

Seconds

Calibration

1FF7h

1FF6h

1FF5h

1FF4h

URL : www.dlghb.co.kr

Rev. 1.3 (Apr, 2009)

DLG HANBIT Co.,Ltd

DLGHANBIT

DLGHANBIT Confidential

HMNR88D(V)

1FF3h

1FF2h

1FF1h

1FF0h

1000 Years

100 Years

Century

Flag

00-99

Keys :

S = Sign Bit

BL = Battery Low Flag(Read only)

Z = ’0’ and are Read only

0 = Must be set to ’0’

R = READ Bit

W= WRITE Bit

ST = Stop Bit

Y = ’1’ or ’0’

CLOCK OPERATIONS

The HMNR88D(V) offers 16 internal registers which contain TIMEKEEPER, and Control data. These registers are memory

locations which contain external (user accessible) and internal copies of the data. The external copies are independent of

internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy.

TIMEKEEPER Registers store data in BCD. Control Registers store data in Binary Format.

Reading the Clock

Updates to the TIMEKEEPER registers should be halted before clock data is read to prevent reading data in transition.

The TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so updating the

registers can be halted without disturbing the clock itself. Updating is halted when a ’1’ is written to the READ Bit, D6 in the

Control Register (1FF8h). As long as a ’1’ remains in that position, updating is halted. After a halt is issued, the registers

reflect the count; that is, the day, date, and time that were current at the moment the halt command was is-sued. All of the

TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating occurs

approximately 1 second after the READ Bit is reset to a ’0.’

Setting the Clock

Bit D7 of the Control Register (1FF8h) is the WRITE Bit. Setting the WRITE Bit to a ’1,’ like the READ Bit, halts updates to

the TIMEKEEPER reg-isters. The user can then load them with the correct day, date, and time data in 24-hour BCD

format. Resetting the WRITE Bit to a ’0’ then transfers the values of all time registers (1FFh-1FF9h, 1FF1h) to the actual

TIMEKEEPER counters and allows normal operation to resume. After the WRITE Bit is reset, the next clock update will

occur approximately one second later.

Note: Upon power-up following a power failure, both the WRITE Bit and the READ Bit will be reset to ’0.’

Stopping and Starting the Oscillator

The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the

oscillator can be turned off to minimize current drain on the battery. The STOP Bit is located at Bit D7 within the Seconds

Register (1FF9h). Setting it to a ’1’ stops the oscillator. When reset to a ’0,’ the HMNR88D(V) oscillator starts within one

second.

Note : It is not necessary to set the WRITE Bit when setting or resetting the STOP Bit (ST).

Power-on Reset

The HMNR88D(V) continuously monitors VCC .When VCC falls to the power fail detect trip point, the /RST pulls low (open

URL : www.dlghb.co.kr

Rev. 1.3 (Apr, 2009)

DLG HANBIT Co.,Ltd

DLGHANBIT

DLGHANBIT Confidential

HMNR88D(V)

drain) and remains low on power-up for t_RECafter VCC passes V_PFD(max). /RST is valid for all VCC conditions. The /RST

pin is an open drain output and an appropriate resistor to VCC should be chosen to control rise time.

Calibrating the Clock

The HMNR88D(V) is driven by a quartz controlled oscillator with a nominal frequency of 32,768Hz. The devices are

factory calibrated at 25°C and tested for accuracy. Clock accuracy will not exceed 35 ppm (parts per million) oscillator

frequency error at 25°C, which equates to about ±1.53 minutes per month. When the Calibration circuit is properly

employed, accuracy improves to better than +1/-2 ppm at 25°C. The oscillation rate of crystals changes with temperature.

The HMNR88D(V) design employs periodic counter correction. The calibration circuit adds or subtracts counts from the

oscillator divider circuit at the divide by 256 stage. The number of times pulses are blanked (subtracted, negative

calibration) or split (added, positive calibration) depends upon the value loaded into the five Calibration bits found in the

Control Register.

Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration bits occupy the five lower

order bits (D4-D0) in the Control Register 1FF8h. These bits can be set to represent any value between 0 and 31 in binary

form. Bit D5 is a Sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64

minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or

lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle

will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the

effect of adding 512 or subtracting 256 oscillator cycles for every 125, 829, 120 actual oscillator cycles; that is, +4.068 or -

2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is running at exactly

32,768Hz, each of the 31 increments in the Calibration byte would represent +10.7 or -5.35 seconds per month which

corresponds to a total range of +5.5 or -2.75 minutes per month. One method for ascertaining how much calibration a

given HMNR88D(V) may require involves setting the clock, letting it run for a month and comparing it to a known accurate

reference and recording deviation over a fixed period of time. This allows the designer to give the end user the ability to

calibrate the clock as the environment requires, even if the final product is packaged in a nonuser serviceable enclosure.

The designer could provide a simple utility that accesses the Calibration bits.

Battery Low Warning

The HMNR88D(V) automatically performs battery voltage monitoring upon power-up and at factory-programmed time

intervals of approximately 24 hours. The Battery Low (BL) Bit, Bit D4 of Flags Register 1FF0h, will be asserted if the

battery voltage is found to be less than approximately 2.5V. The BL Bit will remain asserted until completion of battery

replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next

scheduled 24hour interval. If a battery low is generated during a power-up sequence,

this indicates that the battery is below approximately 2.5V and may not be able to maintain data integrity in the SRAM.

Data should be considered suspect and verified as correct. A fresh battery should be installed. If a battery low indication is

generated during the 24-hour interval check, this indicates that the battery is near end of life. However, data is not

compromised due to the fact that a nominal V_CCis supplied.

URL : www.dlghb.co.kr

Rev. 1.3 (Apr, 2009)

DLG HANBIT Co.,Ltd

DLGHANBIT

DLGHANBIT Confidential

HMNR88D(V)

Power Supply Decoupling and Undershoot Protection

Note: I_CCtransients, including those produced by output

switching, can produce voltage fluctuations, resulting in spikes

on the V_CCbus. These transients can be reduced if capacitors

are used to store energy which stabilizes the V_CCbus. The

energy stored in the bypass capacitors will be released as low

going spikes are generated or energy will be absorbed when

overshoots occur. A ceramic bypass capacitor value of 0.1uF

is recommended in order to provide the needed filtering. In

addition to transients that are caused by normal

SRAM operation, power cycling can generate negative

voltage spikes on V_CCthat drive it to values below V_SSby as

much as one volt. These negative spikes can cause data

corruption in the SRAM while in battery backup mode. To

protect from these voltage spikes, ST recommends connecting a schottky diode from V_CCto V_SS(cathode connected to

V_CC, anode to V_SS). (Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for

surface mount).

URL : www.dlghb.co.kr

Rev. 1.3 (Apr, 2009)

DLG HANBIT Co.,Ltd

DLGHANBIT

DLGHANBIT Confidential

HMNR88D(V)

PACKAGE DIMENSION

Dimension

Min

Max

1.450

0.700

0.365

0.012

0.008

0.590

0.017

0.090

0.075

0.150

1.525

0.760

0.380

0.013

0.630

0.023

0.110

0.190

All dimensions are in inches.

ORDERING INFORMATION

H M N R 88 D V LF - 70

Speed options : 70 = 70 ns

85 = 85 ns

LF: Lead-Free

Operating Voltage : Blank = 5V

V = 3.3V

Dip type package

Device : 8K x 8 bit

Nonvolatile Timekeeping SRAM

HANBit Memory Module

7F(#712), 274, Samsung-ro, Suwon-si, Gyeonggi-do, South Korea

TEL : (+82) 31-211-2523 , FAX : (+82) 31-211-2524

EMAIL : dlghbinfo@dlghb.co.kr

http://www.dlghb.co.kr

URL : www.dlghb.co.kr

Rev. 1.3 (Apr, 2009)

DLG HANBIT Co.,Ltd

HMNR88DV [DLGHANBIT]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E