EC24C512AP1GX [E-CMOS]
512K bitsTwo-wire Serial EEPROM;
| 型号： | EC24C512AP1GX |
| 厂家： | 
E-CMOS Corporation |
| 描述： | 512K bitsTwo-wire Serial EEPROM 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总14页 (文件大小：471K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EC24C512A
512K bitsTwo-wire Serial EEPROM
Features
General Description
The EC24C512A provides 524,288 bits of serial ● Wide Voltage Operation - VCC = 1.7V to 5.5V
electrically erasable and programmable read-only ● Operating Ambient Temperature: -40℃to+85℃
memory (EEPROM), organized as 65,536 words ● Internally Organized:
of 8 bits each. The device is optimized for use in
- EC24C512A, 65,536 X 8 (512K bits)
many industrial and commercial applications ● Two-wire Serial Interface
where low-power and low-voltage operation are ● Schmitt Trigger, Filtered Inputs for Noise Suppression
essential. The EC24C512A is available in space- ● Bidirectional Data Transfer Protocol
saving 8-lead PDIP, 8-lead SOP, and 8-lead ● 1 MHz (5V), 400 KHz (1.7V, 2.5V, 2.7V) Compatibility
TSSOP packages and is accessed via a two-wire ● Write Protect Pin for Hardware Data Protection
serial interface. In addition, the EC24C512A is ● 128-byte (512K) Write Modes
available in 1.7V (1.7V to 5.5V) version.
● Partial Page Writes Allowed
● Self-timed Write Cycle (5 ms max)
● High-reliability
- Endurance: 1 Million Write Cycles
- Data Retention: 100 Years
● 8-lead PDIP/SOP/TSSOP package
Pin Configuration
PDIP-8
SOP-8
TSSOP-8
Top-View
Top-View
Top-View
Pin Name
A0 - A2
SDA
Type
Functions
I
Address Inputs
I/O & Open-drain
Serial Data
SCL
I
Serial Clock Input
Write Protect
Ground
WP
I
GND
P
P
VCC
Power Supply
E-CMOS Corp. (www.ecmos.com.tw)
Page 1 of 14
4B12N-Rev.P001
EC24C512A
512K bitsTwo-wire Serial EEPROM
Block Diagram
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E-CMOS Corp. (www.ecmos.com.tw)
Page 2 of 14
4B12N-Rev.P001
EC24C512A
512K bitsTwo-wire Serial EEPROM
Pin Descriptions
DEVICE/PAGE ADDRESSES (A2, A1 and A0): The A2, A1 and A0 pins are device address inputs that are
hard wire for the EC24C512A. Eight 512K devices may be addressed on a single bus system (device
addressing is discussed in detail under the Device Addressing section).
SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and
may be wire-ORed with any number of other open-drain or open- collector devices.
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and
negative edge clock data out of each device.
WRITE PROTECT (WP): The EC24C512A has a Write Protect pin that provides hardware data protection. The
Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write
Protection pin is connected to VCC, the write protection feature is enabled and operates as shown in the
following Table.
Write Protect
Part of the Array Protected
WP Pin Status
EC24C512A
At VCC
Full (512K) Array
At GND
Normal Read / Write Operations
Ordering/ Marking Information
512A＝ 512 Kbit
(65,536×8)
Available package types
Part Number
SOP-8
TSSOP-8
PDIP-8
V
V
EC24C512A
V
E-CMOS Corp. (www.ecmos.com.tw)
Page 3 of 14
4B12N-Rev.P001
EC24C512A
512K bitsTwo-wire Serial EEPROM
Marking Information
Package type
Part Number
EC24C512AM1GX
Marking
Marking Information
SOP-8
512 is the memory of production.
LLLLL is the last five numbers of wafer lot number
YYWW is Date Code.
24C512A
LLLLL
YYWWT
TSSOP-8
EC24C512AE1GX
EC24C512AP1GX
T is tracking Code ,T=X
PDIP-8
Memory Organization
EC24C512A, 512K SERIAL EEPROM: Internally organized with 512 pages of 128 bytes each, the 512K
requires an 16-bit data word address for random word addressing.
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the
SDA pin may change only during SCL low time periods (see to Figure1). Data changes during SCL high
periods will indicate a start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede
any other command (see to Figure 2).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence,
the stop command will place the EEPROM in a standby power mode (see to Figure 2).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit
words. The EEPROM sends a "0" to acknowledge that it has received each word. This happens during the
ninth clock cycle
STANDBY MODE: The EC24C512A features a low-power standby mode which is enabled:
(a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations
MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset
by following these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition.
E-CMOS Corp. (www.ecmos.com.tw)
Page 4 of 14
4B12N-Rev.P001
EC24C512A
512K bitsTwo-wire Serial EEPROM
Figure 1: Data Validity
Figure 2: Start and Stop Definition
Figure 3: Output Acknowledge
E-CMOS Corp. (www.ecmos.com.tw)
Page 5 of 14
4B12N-Rev.P001
EC24C512A
512K bitsTwo-wire Serial EEPROM
Device Addressing
The 512K EEPROM devices all require an 8-bit device address word following a start condition to enable the
chip for a read or write operation (see to Figure 4).
The device address word consists of a mandatory "1", "0" sequence for the first four most significant bits as
shown. This is common to all the Serial EEPROM devices.
The 512K EEPROM uses A2, A1 and A0 device address bits to allow as much as eight devices on the same
bus. These 3 bits must be compared to their corresonding hardwired input pins. The A2, A1 and A0 pins use
an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit
is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the chip will
return to a standby state.
DATA SECURITY: The EC24C512A has a hardware data protection scheme that allows the user to write
protect the entire memory when the WP pin is at VCC.
Write Operations
BYTE WRITE: A write operation requires an 8-bit data word address following the device address word and
acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then clock in
the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0" and the
addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this
time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are
disabled during this write cycle and the EEPROM will not respond until the write is complete (see to Figure 5).
PAGE WRITE: The 512K EEPROM is capable of an 128-byte page write.
A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after
the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the
microcontroller can transmit up to 127(512K) more data words. The EEPROM will respond with a "0" after each
data word received. The microcontroller must terminate the page write sequence with a stop condition (see to
Figure 6).
The data word address lower seven (512K) bits are internally incremented following the receipt of each data
word. The higher data word address bits are not incremented, retaining the memory page row location. When
the word address, internally generated, reaches the page boundary, the following byte is placed at the
beginning of the same page. If more than 128(512K) data words are transmitted to the EEPROM, the data
word address will "roll over" and previous data will be overwritten.
ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are
disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device
address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has
completed will the EEPROM respond with a "0", allowing the read or write sequence to continue.
E-CMOS Corp. (www.ecmos.com.tw)
Page 6 of 14
4B12N-Rev.P001
EC24C512A
512K bitsTwo-wire Serial EEPROM
Figure 4: Device Address
Figure 5: Byte Write
Figure 6: Page Write
Read Operations
Read operations are initiated the same way as write operations with the exception that the read/write select bit
in the device address word is set to "1". There are three read operations: current address read, random
address read and sequential read.
CURRENT ADDRESS READ: The address "roll over" during read is from the last byte of the last memory
page to the first byte of the first page. The address "roll over" during write is from the last byte of the current
page to the first byte of the same page.
Once the device address with the read/write select bit set to "1" is clocked in and acknowledged by the
EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an
input "0" but does generate a following stop condition (see Figure 7 ).
E-CMOS Corp. (www.ecmos.com.tw)
Page 7 of 14
4B12N-Rev.P001
EC24C512A
512K bitsTwo-wire Serial EEPROM
RANDOM READ: A random read requires a "dummy" byte write sequence to load in the data word address.
Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the
microcontroller must generate another start condition. The microcontroller now initiates a current address read
by sending a device address with the read/write select bit high. The EEPROM acknowledges the device
address and serially clocks out the data word. The microcontroller does not respond with a "0" but does
generate a following stop condition (see Figure 8 ).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address
read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the
EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out
sequential data words. When the memory address limit is reached, the data word address will "roll over" and
the sequential read will continue. The sequential read operation is terminated when the microcontroller does
not respond with a "0" but does generate a following stop condition (see to Figure 9).
Figure 7: Current Address Read
Figure 8: Random Read
E-CMOS Corp. (www.ecmos.com.tw)
Page 8 of 14
4B12N-Rev.P001
EC24C512A
512K bitsTwo-wire Serial EEPROM
Figure 9: Sequential Read
Electrical Characteristics
Absolute Maximum Stress Ratings
DC Supply Voltage ---------------------------------------------------------------------------------------- -0.3V to +6.5V
Input / Output Voltage ------------------------------------------------------------------------------------- GND-0.3V to VCC+0.3V
Operating Ambient Temperature ---------------------------------------------------------------------- -40°C to +85°C
Storage Temperature ------------------------------------------------------------------------------------- -65°C to +150°C
Comments
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this device at these or any other conditions above those
indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may affect device reliability.
DC Electrical Characteristics
Applicable over recommended operating range from: TA = -40°C to +85°C , VCC = +1.7V to +5.5V
(unless otherwise noted)
Parameter
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Current VCC = 5.0V
Supply Current VCC = 5.0V
Standby Current VCC = 1.7V
Standby Current VCC = 2.5V
Standby Current VCC = 2.7V
Standby Current VCC = 5.0V
Input Leakage Current
Output Leakage Current
Input Low Level
Input High Level
Input Low Level
Input High Level
Output Low Level VCC =5.0V
Output Low Level VCC =3.0V
Output Low Level VCC =1.7V
Symbol
VCC1
VCC2
VCC3
VCC4
ICC1
ICC2
ISB1
ISB2
ISB3
ISB4
ILI
ILO
VIL1
VIH1
VIL2
VIH2
VOL3
VOL2
VOL1
Min.
1.7
2.5
2.7
4.5
-
-
-
-
-
-
-
-
Typ.
-
-
-
-
0.4
2.0
0.6
1.0
1.0
2.0
0.10
0.05
-
-
-
-
-
-
-
Max.
5.5
5.5
5.5
5.5
1.0
3.0
1.0
2.0
2.0
5.0
3.0
3.0
Unit
V
V
V
V
mA
mA
μA
μA
μA
μA
μA
μA
V
V
V
V
V
V
V
Condition
READ at 400 kHz
WRITE at 400 kHz
VIN = VCC or GND
VIN = VCC or GND
VIN = VCC or GND
VIN = VCC or GND
VIN = VCC or GND
VOUT = VCC or GND
VCC = 1.8V to 5.5V
VCC = 1.8V to 5.5V
VCC = 1.7V
-0.3
VCCx0.7
-0.3
VCCx0.7
VCCx0.3
VCC+0.3
VCCx0.2
VCC+0.3
0.4
VCC = 1.7V
IOL = 3.0 mA
IOL = 2.1 mA
IOL = 0.15 mA
0.4
0.2
E-CMOS Corp. (www.ecmos.com.tw)
Page 9 of 14
4B12N-Rev.P001
EC24C512A
512K bitsTwo-wire Serial EEPROM
Pin Capacitance
Applicable over recommended operating range from TA = 25°C , f = 1.0 MHz, VCC = +1.7V
Parameter
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL)
Symbol
CI/O
Min.
-
-
Typ.
-
-
Max.
8
6
Unit
pF
pF
Condition
VI/O = 0V
VIN = 0V
CIN
AC Electrical Characteristics
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +1.7V to +5.5V, CL = 1 TTL
Gate and 100 pF (unless otherwise noted)
1.7V≦VCC < 2.5V
2.5V≦VCC ≦5.5V
Typ. Max.
Parameter
Symbol
Units
Min. Typ. Max. Min.
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time
Clock Low to Data Out Valid
Time the bus must be free before
a new transmission can start
Start Hold Time
Start Setup Time
Data In Hold Time
Data In Setup Time
Inputs Rise Time(1)
Inputs Fall Time(1)
Stop Setup Time
Data Out Hold Time
Write Cycle Time
5.0V, 25°C, Byte Mode
fSCL
tLOW
tHIGH
tI
-
-
-
-
-
-
400
-
-
50
0.9
-
0.6
0.4
-
-
-
-
-
-
1000
-
-
50
0.9
kHZ
μs
μs
ns
μs
1.2
0.6
-
tAA
0.1
0.05
tBUF
1.2
-
-
0.5
-
-
μs
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
tF
tSU.STO
tDH
0.6
0.6
0
100
-
-
-
-
-
-
-
-
-
-
-
0.25
0.25
0
100
-
-
-
-
-
-
-
-
-
-
μs
μs
μs
ns
μs
ns
μs
ns
ms
-
0.3
300
-
-
5
-
0.3
300
-
-
5
-
-
-
0.25
50
-
0.6
50
-
-
-
tWR
Endurance
3.3
-
3.3
-
1M
-
-
-
Write Cycles
Note
1. This parameter is characterized and is not 100% tested.
2. AC measurement conditions:
RL (connects to VCC): 1.3kΩ (2.5V, 5V), 10kΩ (1.7V)
Input pulse voltages: 0.3 x VCC to 0.7 x VCC
Input rise and fall time:≦50 ns
Input and output timing reference voltages: 0.5 x VCC
The value of RL should be concerned according to the actual loading on the user's system.
E-CMOS Corp. (www.ecmos.com.tw)
Page 10 of 14
4B12N-Rev.P001
EC24C512A
512K bitsTwo-wire Serial EEPROM
Bus Timing
Figure 10: SCL: Serial Clock, SDA: Serial Data I/O
Write Cycle Timing
Figure 11: SCL: Serial Clock, SDA: Serial Data I/O
Note
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal
clear/write cycle.
E-CMOS Corp. (www.ecmos.com.tw)
Page 11 of 14
4B12N-Rev.P001
EC24C512A
512K bitsTwo-wire Serial EEPROM
Mechanical Dimensions
OUTLINE DRAWING PDIP - 8
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
Side View
SYMBOL
MIN
MAX
4.00
-
A
A1
A2
A3
b
3.60
0.51
3.10
1.50
0.44
0.43
3.50
1.70
0.53
0.48
b1
B
1.52 BSC
c
0.25
0.24
.05
0.31
0.26
9.45
6.55
c1
D
E1
e
6.15
2.54 BSC
7.62 BSC
eA
eB
eC
L
7.62
0
9.50
0.94
-
3.00
Section B - B
E-CMOS Corp. (www.ecmos.com.tw)
Page 12 of 14
4B12N-Rev.P001
EC24C512A
512K bitsTwo-wire Serial EEPROM
Mechanical Dimensions
OUTLINE DRAWING SOP-8
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
Side View
SYMBOL
MIN
MAX
1.75
0.25
0.51
0.25
5.10
4.00
6.20
A
A1
B
1.35
0.10
0.31
0.17
4.70
3.80
5.79
C
D
E1
E
e
1.27 BSC
L
θ
0.40
0°
1.27
8°
E-CMOS Corp. (www.ecmos.com.tw)
Page 13 of 14
4B12N-Rev.P001
EC24C512A
512K bitsTwo-wire Serial EEPROM
Mechanical Dimensions
OUTLINE DRAWING TSSOP - 8
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
Side View
SYMBOL
MIN
2.80
6.20
4.20
-
MAX
3.20
6.60
4.60
1.20
1.15
0.30
D
E
E1
A
A2
b
0.80
0.19
e
L
L1
θ
0.65 BSC
1.00 BSC
0.45
0°
0.75
8°
E-CMOS Corp. (www.ecmos.com.tw)
Page 14 of 14
4B12N-Rev.P001
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