EC24C512BR1GR [E-CMOS]
512K bitsTwo-wire Serial EEPROM;
| 型号： | EC24C512BR1GR |
| 厂家： | 
E-CMOS Corporation |
| 描述： | 512K bitsTwo-wire Serial EEPROM 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总13页 (文件大小：427K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EC24C512B
512K bitsTwo-wire Serial EEPROM
General Description
The EC24C512B are EEPROM devices that use device, and a series of data, if appropriate. The
the industrial standard 2-wire interface for EC24C512B also has a Write Protect pin (WP) to allow
communications. The EC24C512B contains a blocking any write operations over specified memory area.
memory array of 512K-bits (65,536x8), which is Under no circumstance, the device will be hung up. In
organized in 128-byte per page. The EEPROM order to refrain the state machine entering into a wrong
can operate in a wide voltage range from 1.7V to state during power-up sequence or a power toggle off-on
5.5V which fits most application. This product can
condition, a power on reset circuit is embedded. During
provide a low-power 2-wire EEPROM solution. power-up, the device does not respond to any instructions
The device is offered in Lead-free, RoHS, halogen until the supply voltage (VCC) has reached an acceptable
free or Green. The available package types are 8- stable level above the reset threshold voltage. Once VCC
pin MSOP . The EC24C512B is compatible with passes the power on reset threshold, the device is reset
the industrial standard 2-wire bus protocol. If in and enters into the Standby mode. This would also avoid
case the bus is not responded, a new sent Op- any inadvertent Write operations during power-up stage.
code command will reset the bus and the device During power-down process, the device will enter into
will respond correctly. The simple bus consists of standby mode, once VCC drops below the power on reset
the Serial Clock wire (SCL) and the Serial Data threshold voltage. In addition, the device will be in standby
wire (SDA).
mode after receiving the Stop command, provided that no
Utilizing such bus protocol, a Master device, such internal write operation is in progress. Nevertheless, it is
as a microcontroller, can usually control one or illegal to send a command unless the VCC is within its
more Slave devices, alike this EC24C512B. The operating level.
bit stream over the SDA line includes a series of
bytes, which identifies a particular Slave device,
an instruction, an address within that Slave
Features
● Page Size: 128 bytes
● Two-Wire Serial Interface, I C TM Compatible
– Bi-directional data transfer protocol
● Wide-voltage Operation
● Page write mode
– Up to 128 bytes per page write
● Self timed write cycle with auto clear: 5ms (max.)
● Filtered inputs for noise suppression
● High-reliability
– VCC = 1.7V to 5.5V
● Speed: 400 KHz (1.7V) and 1 MHz (2.5V~5.5V)
uA, 1.7V
● Operating current (max.): 2 mA, 1.7V
● Hardware Data Protection
– Endurance: 1 million cycles
– Data retention: 100 years
– Write Protect Pin
● Industrial temperature grades
● Packages: MSOP 8L
● Sequential & Random Read Features
● Memory organization: 65,536 x 8 bits
● Lead-free, RoHS, Halogen free, Green
E-CMOS Corp. (www.ecmos.com.tw)
Page 1 of 13
4I09N-Rev.F001
EC24C512B
512K bitsTwo-wire Serial EEPROM
Ordering Information & Marking Information
EC24C XXXB XX X X
R：Tape & Reel
T：Tube
Device Function
512＝512Kbit
(65536×8)
G：Green
R1：MSOP 8L
Industrial Grade: -40°C to +85°C, Lead-free
Package type
Part Number
Marking
Marking Information
512 is the memory of production.
LLLLL is the last five numbers of wafer lot number
YYWW is Date Code.
24C512
LLLLLB
YYWWT
MSOP-8
EC24C512BR1GR
T is tracking Code
Functional Block Diagram
E-CMOS Corp. (www.ecmos.com.tw)
Page 2 of 13
4I09N-Rev.F001
EC24C512B
512K bitsTwo-wire Serial EEPROM
Pin Configuration
(MSOP 8L)
Pin Definition
Pin No.
Pin Name
A0
I/O
Definition
1
2
3
4
5
6
7
8
I
Device Address Input
Device Address Input
Device Address Input
Ground
A1
I
A2
I
GND
SDA
SCL
WP
-
I/O
Serial Address and Data input and Data out put
Serial Clock Input
I
I
-
Write Protect Input
Power Supply
VCC
Pin Descriptions
SCL
When A0, A1, and A2 are left floating, the inputs are
This input clock pin is used to synchronize the data defaulted to zero.
transfer to and from the device.
WP
SDA
WP is the Write Protect pin. While the WP pin is
The SDA is a bi-directional pin used to transfer connected to the power supply of EC24C512B, the entire
addressesand data into and out of the device. The array becomes Write Protected (i.e. the device becomes
SDA pin is an open drain output and can be wired Read only). When WP is tied to Ground or left floating, the
with other open drain or open collector outputs. normal write operations are allowed.
However, the SDA pin requires a pull-up resistor
connected to the power supply.
VCC
Supply voltage
A0, A1, A2
The A0, A1 and A2 are the device address inputs. GND
Typically, the A0, A1, and A2 pins are for hardware Ground of supply voltage
addressing and a total of 8 devices can be connected
on a single bus system.
E-CMOS Corp. (www.ecmos.com.tw)
Page 3 of 13
4I09N-Rev.F001
EC24C512B
512K bitsTwo-wire Serial EEPROM
Device Operation
The
EC24C512B
serial
interface
supports Reset
communications using industrial standard 2-wire bus The EC24C512B contains a reset function in case the 2-
protocol, such as I2C.
wire bus transmission on is accidentally interrupted (e.g.
a power loss), or needs to be terminated mid-stream.
The reset is initiated when the Master device creates a
Start condition. To do this, it may be necessary for the
2-WIRE Bus
The two-wire bus is defined as Serial Data (SDA), and
Serial Clock (SCL). The protocol defines any device that Master device to monitor the SDA line while cycling the
sends data onto the SDA bus as a transmitter, and the
receiving devices as receivers. The bus is controlled by
Master device that generates the SCL, controls the bus
SCL up to nine times.(For each clock signal transition to
High, the Master checks for a High level on SDA.)
access, and generates the Start and Stop conditions. Standby Mode
While in standby mode, the power consumption is
The EC24C512B is the Slave device.
minimal. The EC24C512B enters into standby mode
during one of the following conditions: a) After Power-up,
while no Op-code is sent; b) After the completion of an
operation and followed by the Stop signal, provided that
the previous operation is not Write related; or c) After the
completion of any internal write operations.
The Bus Protocol
Data transfer may be initiated only when the bus is not
busy. During a data transfer, the SDA line must remain
stable whenever the SCL line is high. Any changes in the
SDA line while the SCL line is high will be interpreted as
a Start or Stop condition.
Device Addressing
The Master begins a transmission on by sending a Start
condition, then sends the address of the particular Slave
devices to be communicated. The Slave device address
is 8 bits format as shown in Figure. 5.
The state of the SDA line represents valid data after a
Start condition. The SDA line must be stable for the
duration of the High period of the clock signal. The data
on the SDA line may be changed during the Low period
of the clock signal. There is one clock pulse per bit of
data. Each data transfer is initiated with a Start condition
and terminated by a Stop condition.
The four most significant bits of the Slave address are
fixed (1010) for EC24C512B. The next three bits, A0, A1
and A2, of the Slave address are specifically related to
EEPROM. Up to eight EC24C512B units can be
connected to the 2-wire bus. The last bit of the Slave
address specifies whether a Read or Write operation is to
be performed. When this bit is set to 1, Read operation is
selected. While it is set to 0, Write operation is selected.
After the Master transmits the Start condition and Slave
address byte appropriately, the associated 2-wire Slave
device,EC24C512B, will respond with ACK on the SDA
line.Then EC24C512B will pull down the SDA on the
ninth clock cycle, signaling that it received the eight bits
of data. The EC24C512B then prepares for a Read or
Write operation by monitoring the bus.
Start Condition
The Start condition precedes all commands to the device
and is defined as a High to Low transition of SDA when
SCL is High. The EEPROM monitors the SDA and SCL
lines and will not respond until the Start condition is met.
Stop Condition
The Stop condition is defined as a Low to High transition
of SDA when SCL is High. All operations must end with
a Stop condition.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an ACK. The Acknowledging device
pulls down the SDA line.
E-CMOS Corp. (www.ecmos.com.tw)
Page 4 of 13
4I09N-Rev.F001
EC24C512B
512K bitsTwo-wire Serial EEPROM
Write Operation
Byte Write
This involves issuing the Start condition followed by the
In the Byte Write mode, the Master device sends the Slave address for a Write operation. If the EEPROM is
Start condition and the Slave address information (with still busy with the Write operation, no ACK will be
the R/W set to Zero) to the Slave device. After the Slave returned. If the EC24C512B has completed the Write
generates an ACK, the Master sends the byte address operation, an ACK will be returned and the host can then
that is to be written into the address pointer of the proceed with the next Read or Write operation.
EC24C512B. After receiving another ACK from the
Slave, the Master device transmits the data byte to be Read Operation
written into the address memory location. The Read operations are initiated in the same manner as
EC24C512B acknowledges once more and the Master Write operations, except that the (R/W) bit of the Slave
generates the Stop condition, at which time the device address is set to “1”. There are three Read operation
begins its internal programming cycle. While this internal options: current address read, random address read and
cycle is in progress, the device will not respond to any sequential read.
request from the Master device.
Current Address Read
Page Write
The EC24C512B contains an internal address counter
The EC24C512B is capable of 128-byte Page-Write
which maintains the address of the last byte accessed,
operation. A Page-Write is initiated in the same manner incremented by one. For example, if the previous
as a Byte Write, but instead of terminating the internal operation is either a Read or Write operation addressed
Write cycle after the first data word is transferred, the to the address location n, the internal address counter
Master device can transmit up to 127 more bytes. After would increment to address location n+1. When the
the receipt of each data word, the EEPROM responds EEPROM receives the Slave Addressing Byte with a
immediately with an ACK on SDA line, and the seven Read operation (R/W bit set to “1”), it will respond an
lower order data word address bits are internally ACK and transmit the 8-bit data byte stored at address
incremented by one, while the higher order bits of the location n+1. The Master should not acknowledge the
data word address remain constant. If a byte address is transfer but should generate a Stop condition so the
incremented from the last byte of a page, it returns to the EC24C512B discontinues transmission. If 'n' is the last
first byte of that page. If the Master device should byte of the memory, the data from location '0' will be
transmit more than 128 bytes prior to issuing the Stop transmitted. (Refer to Figure 8. Current Address Read
condition, the address counter will “roll over,” and the
Diagram.)
previously written data will be overwritten. Once all 128
bytes are received and the Stop condition has been sent Random Address Read
by the Master, the internal programming cycle begins. At Selective Read operations allow the Master device to
this point, all received data is written to the EC24C512B select at random any memory location for a Read
in a single Write cycle. All inputs are disabled until operation. The Master device first performs a 'dummy'
completion of the internal Write cycle.
Write operation by sending the Start condition, Slave
address and byte address of the location it wishes to
read. After the EC24C512B acknowledges the byte
Acknowledge (ACK) Polling
The disabling of the inputs can be used to take address, the Master device resends the Start condition
advantage of the typical Write cycle time. Once the Stop and the Slave address, this time with the R/W bit set to
condition is issued to indicate the end of the host's Write one. The EEPROM then responds with its ACK and
operation, the EC24C512B initiates the internal Write sends the data requested. The Master device does not
cycle. ACK polling can be initiated immediately.
send an ACK but will generate a Stop condition. (Refer to
Figure 9. Random Address Read Diagram.)
E-CMOS Corp. (www.ecmos.com.tw)
Page 5 of 13
4I09N-Rev.F001
EC24C512B
512K bitsTwo-wire Serial EEPROM
Sequential Read
Diagrams
Sequential Reads can be initiated as either a Current
followed by a Stop condition. The data output is
Address Read or Random Address Read. After the
sequential, with the data from address n followed by the
EC24C512B sends the initial byte sequence, the Master data from address n+1,n+2 ... etc. The address counter
device now responds with an ACK indicating it requires
additional data from the EC24C512B. The EEPROM
increments by one automatically, allowing the entire
memory contents to be serially read during sequential
continues to output data for each ACK received. The Read operation. When the memory address boundary of
Master device terminates the sequential Read operation the array is reached, the address counter “rolls over” to
by pulling SDA High (no ACK) indicating the last data address 0, and the device continues to output data.
word to be read,
(Refer to Figure 10. Sequential Read Diagram).
Figure 1. Typical System Bus Configuration
EC24C512B
Figure 2. output Acknowledge
Figure 3. Start and Stop Conditions
E-CMOS Corp. (www.ecmos.com.tw)
Page 6 of 13
4I09N-Rev.F001
EC24C512B
512K bitsTwo-wire Serial EEPROM
Figure 4. Data Validity Protocol
Figure 5. Slave Address
Figure 6. Byte Write
Figure 7. Page Write
E-CMOS Corp. (www.ecmos.com.tw)
Page 7 of 13
4I09N-Rev.F001
EC24C512B
512K bitsTwo-wire Serial EEPROM
Figure 8. Current Address Read
Figure 9. Random Address Read
Figure 10. Sequential Read
E-CMOS Corp. (www.ecmos.com.tw)
Page 8 of 13
4I09N-Rev.F001
EC24C512B
512K bitsTwo-wire Serial EEPROM
Timing Diagrams
Figure 11 .Bus Timing
Figure 12. Write Cycle Timing
E-CMOS Corp. (www.ecmos.com.tw)
Page 9 of 13
4I09N-Rev.F001
EC24C512B
512K bitsTwo-wire Serial EEPROM
Electrical Characteristics
Absolute Maximum Ratings
Symbol
VS
Parameter
Value
Unit
V
Supply Voltage
Voltage on Any Pin
Temperature Under Bias
Storage Temperature
Output Current
-0.5 to + 6.5
–0.5 to VCC + 0.5
–55 to +125
–65 to +150
5
V
VP
°C
°C
mA
TBIAS
TSTG
IOUT
Note: Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or any other condition outside those indicated in
the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Operating Range
Range
Ambient Temperature (TA)
VCC
Industrial
–40°C to +85°C
1.7V to 5.5V
Note: ECMOS offers Industrial grade for Commercial applications (0C to +70C).
Capacitance
Symbol
CIN
Parameter[1,2]
Conditions
VIN = 0V
Max.
6
Unit
pF
Input Capacitance
Input / Output
Capacitance
CI/O
VI/O = 0V
8
pF
Note: (1) Tested initially and after any design or process changes that may affect these parameters and not 100% tested.
(2) Test conditions: TA = 25°C, f = 1 MHz, VCC = 5.0V.
E-CMOS Corp. (www.ecmos.com.tw)
Page 10 of 13
4I09N-Rev.F001
EC24C512B
512K bitsTwo-wire Serial EEPROM
DC Electrical Characteristic
Industrial: TA = –40°C to +85°C, VCC = 1.7V ~ 5.5V
Symbol
VCC
VIH
Parameter[1]
VCC
Test Conditions
VIN = VCC max
Min.
Max.
Unit
V
Supply Voltage
1.7
5.5
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output Low Voltage
Standby Current
0.7*VCC
VCC+1
V
VIL
-1
--
0.3* VCC
V
ILI
5V
2
2
μA
μA
V
ILO
5V
--
VOL1
VOL2
ISB1
ISB2
ISB3
1.7V
3V
IOL = 0.15 mA
IOL = 2.1 mA
—
—
—
—
—
—
0.2
0.4
1
V
1.7V
2.5V
5V
VIN = VCC or GND
VIN = VCC or GND
VIN = VCC or GND
Read at 400 KHz
Read at 1 MHz
Read at 1 MHz
Write at 400 KHz
Write at 1 MHz
Write at 1 MHz
μA
μA
μA
mA
mA
mA
mA
mA
mA
Standby Current
2
Standby Current
3
1.7V
2.5V
5.5V
1.7V
2.5V
5.5V
0.5
1
ICC1
ICC2
Read Current
Write Current
1
—
2
3
3
Note: The parameters are characterized but not 100% tested.
E-CMOS Corp. (www.ecmos.com.tw)
Page 11 of 13
4I09N-Rev.F001
EC24C512B
512K bitsTwo-wire Serial EEPROM
AC Electrical Characteristic
Industrial: TA = –40°C to +85°C, Supply voltage = 1.7V to 5.5V
1.7V ≤ VCC<2.5V
2.5V ≤ VCC<4.5V 4.5V ≤ VCC ≤ 5.5V Unit
Symbol
Parameter[1][2]
Min.
Max.
400
—
Min.
Max.
1000
—
Min.
Max.
1000
—
Unit
KHz
ns
FSCL
TLOW
SCK Clock Frequency
Clock Low Period
1200
600
—
400
400
—
400
400
—
THIGH
TR
Clock High Period
—
—
—
ns
Rise Time (SCL and SDA)
Fall Time (SCL and SDA)
Start Condition Setup Time
Stop Condition Setup Time
Start Condition Hold Time
Data In Setup Time
300
300
—
300
100
—
300
100
—
ns
TF
—
—
—
ns
TSU:STA
TSU:STO
THD:STA
TSU:DAT
THD:DAT
600
600
600
100
0
200
200
200
40
200
200
200
40
ns
—
—
—
ns
—
—
—
ns
—
—
—
ns
Data In Hold Time
—
0
—
0
—
ns
Clock to Output Access time
TAA
TDH
100
100
900
50
50
400
50
50
400
ns
ns
(SCL Low to SDA Data Out Valid)
Data Out Hold Time
—
—
—
(SCL Low to SDA Data Out Change)
TWR
Write Cycle Time
Bus Free Time Before New
Transmission
—
5
—
5
—
5
ms
ns
TBUF
1000
—
400
—
400
—
TSU:WP
THD:WP
T
WP pin Setup Time
WP pin Hold Time
600
1200
—
—
—
400
1200
—
—
—
50
400
1200
—
ns
ns
ns
—
Noise Suppression Time
100
50
Note: (1)The parameters are characterized but not 100% tested.
(2)AC measurement conditions:
RL (connects to VCC): 1.3 kΩ (2.5V, 5.0V), 10 kΩ (1.7V)
CL = 100 pF
Input pulse voltages: 0.3*VCC to 0.7*VCC
Input rise and fall times: ≤ 50 ns
Timing reference voltages: half VCC level
E-CMOS Corp. (www.ecmos.com.tw)
Page 12 of 13
4I09N-Rev.F001
EC24C512B
512K bitsTwo-wire Serial EEPROM
MSOP 8L
E-CMOS Corp. (www.ecmos.com.tw)
Page 13 of 13
4I09N-Rev.F001
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