E52141A62CXX2 [ELMOS]
Transceiver compliant with PSI5 standard v1.3 and v2.1;
| 型号： | E52141A62CXX2 |
| 厂家： | 
ELMOS SEMICONDUCTOR AG |
| 描述： | Transceiver compliant with PSI5 standard v1.3 and v2.1 |
| 文件： | 总89页 (文件大小：1865K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
Features
General Description
•
Transceiver compliant with PSI5 standard v1.3 and
v2.1
Provides four independent master channels (up to 6
sensors each)
Supporting 125 Kbit/s and 189 Kbit/s protocols
Supporting synchronous and asynchronous opera-
tion modes
The E521.41 was developed to manage the connection
and communication between a microcontroller unit and
up to 24 sensor satellites.
Data transmission from the sensor to ECU is done by
current modulation on the power supply lines with data
rate of 125 Kbit/s or 189 Kbit/s (Manchester coded).
Data transmission from ECU to sensor is done by
voltage modulation on the power supply. It supports bid-
irectional communication. Two methods are supported:
•
•
•
•
•
•
•
Various diagnostic features
Internal sync-voltage generation
Programmable PSI5 channel-voltage 4.6V to 11V
Automatic threshold adaption to sensor quiescent
current
Reverse polarity protected bus outputs up to 40V
Enables operation in powertrain and chassis control
systems
•
•
tooth gap method
pulse width method
The device is a PSI5 V1.3 and V2.1 compliant trans-
ceiver which provides four independently operating
channels. The channels are able to communicate in low
power-,
•
•
•
•
Developed according to ISO 26262, based on safety standard-, synchronous- and asynchronous operating
mode. The communication to µC is done via the SPI or
UART interface.
requirements rated up to ASIL C.
Operating temperature range -40°C to +125°C
Applications
Ordering Information
•
•
•
Safety (airbag) control systems
Powertrain control systems
Vehicle dynamics control system
Ordering-No.:
E52141A62CXX2
E52141A55E
Features
4-channel
4-channel
Package
QFN20L5
SOIC20
Typical Application Circuit
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
1 / 89
QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
Functional Diagram
VSUPPLY
VBUS
LDO
Control
VG
SYNC CTRL
+
Reverse Prot
Error
Detection
CSYNC
Bus
Enable
+
SIF1
SIF2
CP2
CP1
VSYNC
Charge
Pump
Reverse Prot
VBUS
VDD
Current
Limitation
Active
Discharge
VDD_INT
Bandgap
References
4
4
4
Oscillator
Receiver
Threshold
Adaption
SIF3
SIF4
NCS
SDO / RXD
SDI /TXD
SCLK
SYNC
Control
Manchester
Decoder
Timeslot
Control
UART / SPI
Interface
CFG
Register
Data
Register
Status
Register
NRES
TRIG
E521.41
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Elmos Semiconductor AG
Data Sheet
2 / 89
QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
1 Package Pinout QFN20L5,SO20
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
3 / 89
QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
1.1 Pin Description QFN20L5
Table 1.1-1: Pin Description
No
1
Name
DGND
VDD
Type
Description
S
S
S
Digital voltage supply
Digital voltage supply
Analog ground
2
3
AGND
SIF1
4
HV_A_O Sensor Interface 1
HV_A_O Sensor Interface 3
5
SIF3
6
PGND
CP2
S
Power ground
HV_A_O Sync charge pump fly capacitor
HV_S VBUS voltage
HV_A_O Sync charge pump fly capacitor
HV_S Sync supply voltage
7
8
VBUS
CP1
9
10
11
12
13
CSYNC
SIF4
HV_A_O Sensor Interface 4
SIF2
HV_A_O Sensor Interface 2
VG
HV_A_O Gate voltage for external transistor
14 VSUPPPLY
HV_S
D_I
D_I
D_I
D_I
D_O
D_I
S
Supply voltage
15
16
17
18
NRES
TRIG
Negative reset and test mode pin
Sync pulse trigger input
SPI chip select
NCS
SDI_RXD
SPI or UART data input
SPI or UART data output
SPI clock input
19 SDO_TXD
20
SCLK
EP
QFN20L5 package only
Exposed Pad. Connect to large copper ground plane for optimal heat dissipation.
Connect to GNDA and GNDD.
Note: A = Analog, D = Digital, S = Supply, I = Input, O = Output, B = Bidirectional, HV = High Voltage
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Data Sheet
4 / 89
QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
1.2 Pin Description SO20
Table 1.2-1: Pin Description
No
1
Name
SDO_TXD
SCLK
DGND
VDD
Type
D_O
D_I
S
Description
SPI or UART data output
SPI clock input
2
3
Digital ground
4
S
Digital voltage supply
Analog ground
5
AGND
SIF1
S
6
HV_A_O Sensor Interface 1
HV_A_O Sensor Interface 3
7
SIF3
8
PGND
CP2
S
Power ground
HV_A_O Sync charge pump fly capacitor
HV_S VBUS voltage
HV_A_O Sync charge pump fly capacitor
HV_S Sync supply voltage
9
10
11
12
13
14
15
VBUS
CP1
CSYNC
SIF4
HV_A_O Sensor Interface 4
SIF2
HV_A_O Sensor Interface 2
VG
HV_A_O Gate voltage for external transistor
16 VSUPPPLY
HV_S
D_I
Supply voltage
17
18
19
20
NRES
TRIG
Negative reset and test mode pin
Sync pulse trigger input
SPI chip select
D_I
NCS
D_I
SDI_RXD
D_I
SPI or UART data input
Note: A = Analog, D = Digital, S = Supply, I = Input, O = Output, B = Bidirectional, HV = High Voltage
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
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Data Sheet
5 / 89
QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
2 Application Description
2.1 Application Circuits
2.1.1 Application Circuits
Pin NCS: terminate with GND for UART-mode only, otherwise is used internal pull-up for SPI-mode.
Pin VSUPPLY: terminate with GND if LDO is not used.
Pin VG: terminate with GND if LDO is not used.
Pin CP1: no termination (OPEN) if charge pump is not used.
Pin CP2: no termination (OPEN) if charge pump is not used (must not be connected to GND!!!).
Pin CSYNC: short to VBUS for asynchronous mode.
The CSYNC voltage can be supplied on pin CSYNC (if available on ECU) without using the charge pump.
This option is not shown here.
ECU
NMOS
VSUPPLY
(
eg
.
battery
)
EMC filter
(
C
EMC
REMC
C
K
C
BUS
Power
supply
&
Reset
CP
1
CCP
NRES
VDD
CP
2
V
DD
C
DD
CSYNC
C
SYNC
Ch1_sensor1
Wiring
E521.41A
SIF
SIF
1
2
LW
LW
/2
RW /
RW /
2
2
RE
2
CW
ZS
CE
CL
/2
µ
C
TRIG
SDI
_
RXD
TXD
SIF
SIF
3
SDO
_
Ch4_sensor1
Wiring
SPI
SCLK
NCS
4
RW /
2
LW
LW
/2
RE
2
CW
ZS
CE
CL
RW /2
/2
Ch4_sensor2
ZS
Figure 2.1.1-1: Application Circuit with LDO
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Elmos Semiconductor AG
Data Sheet
6 / 89
QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
ECU
VSUPPLY
(
)
eg . battery
V
BUS_SUP
C
BUS
Power
supply
&
Reset
CP
1
CCP
NRES
VDD
CP2
V
DD
C
DD
CSYNC
C
SYNC
Ch1_sensor1
Wiring
E521.41A
SIF
SIF
1
2
RW
RW
/
2
LW
/2
RE
2
CW
ZS
CE
CL
/2
LW
/2
µ
C
TRIG
SDI
_
RXD
SIF
3
4
Wiring
SDO
_
TXD
Ch4_sensor1
UART
SCLK
NCS
SIF
RW
/
2
2
LW
/
/
2
2
RE
CW
2
ZS
CE
CL
RW/
LW
Ch4_sensor2
ZS
Figure 2.1.1-2: Application Circuit with VBUS Supplied from ECU
Table 2.1.1-1: Application Circuit Electrical Parameter
Description Condition
Capacitance at VDD
Symbol
CVDD
Min
100
Typ
Max
Unit
nF
220
35
ECU bus capacitance
ECU resistor
CE
RE2
CL
15
nF
Ω
2.0
Satellite capacitance
Total bus capacitance
2.2
25
nF
nF
CE+CL_X
(x=1..3)
107
20
LDO Output capacitor
Ceramic capacitor,
ESR<=100m
Ceramic capacitor;
ESR <= 100m
Ceramic capacitor;
ESR <= 100m
CBUS
4.7
μF
Ω
Charge pump fly capacitor
Charge pump storage capacitor
CCP
270
14.1
nF
Ω
CSYNC
20
μF
Ω
VSUPPLY EMC capacitor
VSUPPLY EMC resistor
Single wire resistance
Wire inductance
CEMC
REMC
RW/2
2*(LW/2)
CW
220
0.5
nF
Ω
100
Ω
0
0
8.7
μH
Wire capacitance
600
pF
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Data Sheet
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QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
The device can be supplied via pin VSUPPLY with an appropriate voltage. This voltage supplies an external NMOS
transistor that is driven by an internal LDO via the pin VG.
The following external NMOS transistor are recommended:
•
•
•
•
IRFZ24NS,
BUK7635-55A,
HUFA76409D3ST,
SQD15N06-42L.
The stability of the output voltage can be achieved with an external compensation capacitor CK connected between
pin VG and AGND. In the following table is shown a suitable compensation capacitor CK:
Table 2.1.1-2: Recommended Compensation Capacitor
Transistor
CK
IRFZ24NS
100nF-220nF
100nF-220nF
100nF-220nF
100nF-220nF
BUK7635-55A
HUFA76409D3ST
SQD15N06-42L
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
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Data Sheet
8 / 89
QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
3 Functional Safety
3.1 Functional Safety Requirements
The device fulfils the functional safety requirement up to ASIL-Level C (system) according to ISO 26262, depending
on the safety mechanisms used.
3.2 FMEDA
The following toplevel safety requirements were analysed with FMEDA method:
•
•
TSR1: Transceiver shall avoid transmission of corrupted data to the micro controller interface
TSR2: Transceiver shall avoid storage of corrupted safety related data
3.2.1 Safety Measures mandatory to reach ASIL Level C
Table 3.2.1-1: mandatory safety mechanisms for ASIL C derived from FMEDA
Safety Mechan-
ism
IC / System
level
Description
SM1
SM2
SM3
SM4
IC
IC
Synchronous decoding of input data in Manchester decoder with fixed baud
rate, fixed frame length and fixed bit count. Decoding errors will be indicated
in the error status and potentially corrupted data will be invalidated.
Data consistency check using parity bit or CRC error detection mechanism.
Note: These mechanisms must be enabled by interface configuration options
from system level.
System
Observe failure rate of Manchester decoder or parity/CRC errors on system
level in order to detect channels with latent faults that could degrade the
robustness of decoding or even cause spurious data corruption.
System / IC
Internal supplies and references are monitored cyclically with a sampling
interval of typ. 2ms. Diagnosis block has a separate reference voltage gener-
ation independent from the reference of analyzed signals. Supervisor function
is implemented for the following signals: VBUS, VCSYNC, VSIF1, VSIF2, VSIF3, VSIF4
VDD, VDD_INT, VCP_GATE
,
.
SM5
SM6
SM7
SM8
System
System
System
System
Data consistencies check using CRC error detection mechanism for SPI and
UART.
Configuration data written to registers of the IC shall be (cyclically) verified by
reading them back. Available configuration lock mechanisms shall be used.
Compare the SPI response with the command ( address,
command,CHID,BID, except frame data, register data & XCRC)
Compare the frame ID, ch ID (if not all CH configurations are same) with
respect to the configuration & calculate and compare the 3-bit CRC/parity for
the sensor data
SM9
System
System
If interface/asic error indicated, read the error status registers
SM10
If start-or stop bit in UART is not detected in time uC can detect UART error
on transceiver
SM11
System
Loop Back Diagnosis: Check digital data processing (Manchester decoder /
Data latch / MUX / XCRC / UART/SPI).
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Data Sheet
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QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
4 Operating Conditions
Stresses beyond these absolute maximum ratings listed below may cause permanent damage to the device. These
are stress ratings only; operation of the device at these or any other conditions beyond those listed in the opera-
tional sections of this document is not implied. Exposure to absolute maximum rated conditions for extended peri-
ods may affect device reliability. All voltages referred to V(GND). Currents flowing into terminals are positive, those
drawn out of a terminal are negative.
4.1 Absolute Maximum Ratings
Table 4.1-1: ESD requirements
No.
Description
Condition
Symbol
Min
Max Unit
1
ESD according Human Body Model (HBM),
Q100-002
for pins SIFx; VSUPPLY; (100pF/1.5kΩ)
ESD pins
SIFX,VSUPPL
Y
4000
V
2
3
4
ESD according Human Body Model (HBM),
Q100-002
for all other pins; (100pF/1,5kΩ)
ESD all other 2000
pins
V
V
V
ESD according Charged Device Model (CDM),
Q100-011
Corner pins
ESD corner
pins CDM
750
450
ESD according Charged Device Model (CDM),
Q100-011
Non-corner pins
ESD non
corner pins
CDM
5
6
7
8
9
Input voltage range (supply from ECU)
VBUS voltage range
VSUPPPLY
VBUS
VG
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
40
40
40
40
40
40
V
V
V
V
V
V
NMOS gate voltage at pin VG
Voltage of charge pump fly cap. - negative pin
Voltage of charge pump fly cap. - positive pin
VCP1
VCP2
10 Voltage of charge pump storage capacitor or
CSYNC voltage supply (from ECU)
VSYNC
11 Voltage at sensor interface
X=1-4
VSIF_X
VDD
-0.3
-0.3
40
19
V
V
12 Supply voltage for analog blocks and digital I/O
pins
13 Voltage of digital input pins
14 Voltage of the digital outputs pins
15 Voltage of NRES and testmode pin
16 Junction temperature
VIN_DIG
VOUT_DIG
VNRES
TJ
-0.3
-0.3
-0.3
-40
-40
-40
19
19
V
V
19
V
150
125
125
23
oC
oC
oC
K/W
17 Storage temperature
TSTG
18 Ambient operating temperature range
TAMB
19 Thermal Resistance (junction-ambient) (refer to
application notes of QFN-packages, thermal con-
nection of exposed die pad very important)
RTJA
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Data Sheet
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QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
4.2 Recommended Operating Conditions
Parameters are guaranteed within the range of recommended operating conditions unless otherwise specified.
All voltages are referred to ground (0V). Currents flowing into the circuit have positive values.
The first electrical potential connected to the IC must be GND. (If not specified specify timing sequence of electrical
contacts.)
Table 4.2-1: Recommended Operation Conditions
No.
Description
Condition
Symbol
Min
Typ
Max Unit
1)
1)
1)
1
Input voltage range at pin VSUPPLY
Application with
LDO and
external NMOS
transistor;
low voltage
mode;
VSUPPLY_lp
5.3
19
V
V
V
V
2
3
4
Input voltage range at pin VSUPPLY
Application with
LDO and
external NMOS
transistor;
standard voltage
mode;
VSUPPLY_std
VSUPPLY_inc
VBUS_SUP_lr
6.95
8.0
19
Input voltage range at pin VSUPPLY
Application with
LDO and
external NMOS
transistor;
increased
19
voltage mode;
Input voltage range at pin VBUS limited
range2)
Application with
(externally gen-
erated) available
4.6
5.05
VBUS voltage;
@ ISIFX_OP=0-
25mA
LDO is disabled
5
Input voltage range at pin VBUS full range3) Application with
VBUS_SUP_fr
5.05
11
V
(externally gen-
erated) available
VBUS voltage;
@ ISIFX_OP=0-
65mA
LDO is disabled
6
7
VBUS voltage ripple;
50Hz<f<50kHz3)
Application with
(externally gen-
erated) available
VBUS voltage;
VBUS_SUP_RPL
100 mVpp
LDO is disabled
VBUS voltage ripple;
50kHz<f<500kHz3)
Application with
(externally gen-
erated) available
VBUS voltage;
VBUS_SUP_RPL
40
mVpp
LDO is disabled
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
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Data Sheet
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QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
No.
Description
VCSYNC voltage input range4)
Condition
Symbol
Min
Typ
Max Unit
8
Application with
available VCSYNC
voltage;
VCSYNC
Vt3
+VCSYN
C_DR
35
V
9
VCSYNC voltage ripple
Application with
available VCSYNC
voltage;
VCSYNC_RPL
500 mVpp
10 Digital supply voltage
11 Digital supply voltage
3V3-mode
5V-mode
VDD
VDD
2.97
4.5
3.63
5.5
V
V
5)
12
VBUS voltage
rising slew rate
VBUS_RISE
8/CSYN V/µs
C
13 Sensor quiescent current
14 Sensor quiescent current
15 Sensor sink current
Standard current
Extended current
Low power mode
Common mode
ILOW_std
ILOW_ext
IS_lp
IS_ext
-19.0
-35.0
-4
-4
mA
mA
mA
mA
mA
mA
MHz
Δ
-15.0 -13.0 -11.0
-30.0 -26.0 -22.0
16 Sensor sink current
Δ
17 Sensor interface current, low power mode ISIFX=-(Ilow+
Δ
IS)
IS)
ISIFX_OP_lp
ISIFX_OP_inc
fSCLK_EXT
-50.0
-65.0
13
-4.0
-4.0
32
18 Sensor interface current,increased mode ISIFX=-(Ilow+
Δ
19 Clock frequency depending on UART data UART mode
rate
20 Baud rate
UART mode
fUART
fSCLK_EX
T/5
bps
21 Duty cycle of fSCLK_EXT
UART mode
DCSCLK_EXT
30
70
%
%
22 Frequency deviation of fSCLK_EXT
UART
FDEVSCLK_EXT
-1.5
1.5
mode,maximum
deviation with
one UART tele-
gram (11 bit)
23 SPI frequency
50% duty cycle
fSCLK
0
5
MHz
1) The following external NMOS transistors are recommended: IRFZ24NS, BUK7635-55A, HUFA76409D3ST
and SQD15N06-42L.
The max.input current of VSUPPLY is 350mA (operating mode). Max. value including: 4 sensor interfaces including current modulation, CSYNC
charge pump avg.current, short circuit for one interface and internal current consumption.
2) Limited range of ISIFX: VBUS_min=4.6V with ISIFX_OPM=25mA (ILOW=10mA and ISINK=15mA)
3) Full range of ISIFX operating
4)
V
is the voltage drop between VCSYNC and VSIFx, Vt3 see Figure 6.1.3.6-1
SYNC_DR
5) To limit the current through schottky diodes and VCSYNC capacitor to 8A
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
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Data Sheet
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QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
5 Detailed Electrical Specification
5.1 ANALOG PART
5.1.1 SUPPLY
Table 5.1.1-1: Current Consumption: Electrical Parameter Table
No.
Description
VSUPPLY quiescent current consumption*) 1)
Condition
Symbol
Min
Typ
Max Unit
1
I
Application with
LDO
disabled
IVSUPPLY_Q
15
µA
2
3
IVSUPPLY current consumption operating1)
IVBUS quiescent current consumption
Application with
LDO enabled
IVSUPPLY_OP
IVBUS_Q
0.1
1
1
4
mA
mA
Application with
available VBUS
voltage;
interfaces off
4
5
IVBUS current consumption operating
Application with
available VBUS
voltage;
interfaces on;
without load;
IVBUS_OP
6
14
5
mA
mA
I
CSYNC quiescent current consumption
Application with
available VCSYNC
voltage;
ICSYNC_Q
0.05
interfaces on;
without load;
6
7
Logic supply operating current
Logic supply operating current
VDD=5.5V;NRE
S=0V
IVDD_off
IVDD_on
4
1
10
10
mA
mA
VDD=5.5V;NRE
S=VDD
*) Not tested in production
1)
I
is the current consumption of the pin VSUPPLY
VSUPPLY
5.1.1.1 LDO Control Block
5.1.1.1.1 Electrical Parameter of LDO
Table 5.1.1.1.1-1: Electrical Parameter Table of LDO
No.
Description
Condition
Symbol
Min
Typ
Max Unit
1
Stabilized output voltage of LDO at pin
1)
VBUS
low power mode;
<
VBUS_LP
5.15 - 5.15 5.15 +
2% 2%
V
5mA<=ILOAD_BUS
=350mA;
5.3V<=VSUPPLY<=
19V
2
Stabilized output voltage of LDO at pin
1)
VBUS
standard power
mode;
VBUS_STD
6.65 - 6.65 6.65 +
3% 3%
V
5mA<=ILOAD_BUS
=350mA;
<
6.95V<=VSUPPLY
=19V
<
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
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Data Sheet
13 / 89
QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
No.
Description
Condition
Symbol
Min
Typ
Max Unit
3
Stabilized output voltage of LDO at pin
1)
VBUS
increased power
mode;
VBUS_INC
7.7 -
3%
7.7
7.7 +
3%
V
5mA<=ILOAD_BUS
=350mA;
<
8.0V<=VSUPPLY<=
19V
4
Input voltage ripple rejection ratio for low
frequencies*)
50Hz<=f<=20kH
z;
VBUS_RR_LF
40
dB
VSUPPLY_AC=4VPP;
VSUPPLY_DC>9V;
CBUS=4.7µF;VBU
S=6.65V-setting
5mA<=IBUS<=350
mA;
5
Input voltage ripple rejection ration for high 100kHz<=f<=50
frequencies*)
VBUS_RR_HF
20
dB
0kHz;
VSUPPLY_AC=400m-
VPP;
5.6V<=VSUPPLY<=
6.4V;
C
BUS=4.7µF;VBU
S=5.15V-setting
5mA<=ILOAD_BUS
=350mA;
<
6
7
Line regulation (
VSUPPLY voltage)
Δ
VBUS voltage for variable ILOAD_BUS is con-
stant during test:
VBUS_LIR
-25
-25
0
0
25
25
mV
mV
5mA<=ILOAD_BUS
=350mA;
VSUPPLY varies:
<
5.6V<=VSUPPLY<=
19V
Load regulation (
LOAD_BUS current)
Δ
VBUS voltage for variable VSUPPLY is con-
stant during test:
5.6V<=VSUPPLY<=
VBUS_LOR
I
19V;ILOAD_BUS var-
ies during test:
5mA<=ILOAD_BUS
=350mA
<
8
9
VBUS voltage overshoot*)
VBUS voltage start-up time*) 2)
VBUS_OS
tstart_LDO
VCP_GATE
10
2)
%
V
10 Internal charge pump for LDO
LDO charge
pump output
voltage
10
19
*) Not tested in production
1) trimmed
2) Start-Up time tstart_LDO can be calculated by following formula: tstart_LDO=(VTH+VGS_eff)*CK/IVG_DRV ; for VTH and VGS_eff see NMOS transistor data
sheet; CK is the compensations capacitor connected between VG and AGND; IVG_DRV is the driver charge current.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
14 / 89
QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
5.1.1.1.2 Electrical Parameter Control Voltage
Table 5.1.1.1.2-1: Gate Control Voltage at Pin VG
No.
Description
Condition
Symbol
Min
Typ
Max Unit
1
NMOS gate voltage at pin VG operating
VSUPPLY=5.3V
VG_ON
VBUS
4.5
+
V
2
NMOS gate voltage at pin VG non operating RDG<=500k
between VG and
VSUPPLY
Ω
VG_OFF
1
V
,
250µA current
sink at pin VBUS
(source)
3
4
5
Pull down current in off condition
*)
Clamp voltage VG - VBUS
IVG_PD
VGS_CLAMP
IVG_DRV
30
7
50
80
70
13
µA
V
Driver capability
*) Not tested in production
50
100
µA
5.1.1.2 Charge Pump for Sync Voltage
Table 5.1.1.2-1: Electrical Parameter Table of the Charge Pump for SYNC Voltage
No.
Description
Condition
Symbol
Min
Typ
Max Unit
1
Charge pump output voltage at pin CSYNC ILOAD=0mA
without load*)
VCSYNC_no_ld
2*VBUS
-1.35V
2*VBUS
V
V
V
2
3
Charge pump output voltage at pin CSYNC VBUS=5.05V;
ILOAD=25mA
VCSYNC_lp
VCSYNC_lp
8.65
10.1
in low power mode
Charge pump output voltage at pin CSYNC VBUS=5.05V;
in low power mode
8.6
10.1
ILOAD=28mA
(7mA per SIFx)
4
5
6
Charge pump output voltage at pin CSYNC VBUS=6.45V;
in standard mode LOAD=28mA
(7mA per SIFx)
Charge pump output voltage at pin CSYNC VBUS=7.47V;
VCSYNC_std
11.35
13.34
12.9
14.94
3
V
V
I
VCSYNC_inc
in increased mode
ILOAD=28mA
(7mA per SIFx)
Start-up time for voltage at pin CSYNC*)
Test condition:
80%*VSYNC at
tSTART_CP_CSYNC
ms
tSTART_CP_SYNC
without load at
pin VSYNC
;
;
*) Not tested in production
5.1.2 POR AND POWER-UP SEQUENCE
Table 5.1.2-1: Electrical Parameter Table of POR
No.
1
Description
Power ON reset threshold value
Power OFF reset threshold value
Power ON reset hysteresis*)
Minimum time NRES=low*)
Condition
Related to VDD
Related to VDD
Symbol
VPOR_ON
VPOR_OFF
VPOR_HYS
tNRES_LOW
tPOR_D_LH
Min
2.3
2.2
0.1
1
Typ
Max Unit
2.9
2.7
0.3
10
V
V
V
2
3
4
μs
5
Power ON reset delay time*) 1)
At power-up of
VDD_INT
50
μs
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QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
No.
6
Description
Power OFF reset delay time*)
Input threshold NRES low*)
Input threshold NRES high*)
Pull down resistor NRES
Condition
Symbol
tPOR_D_HL
Min
0.5
0.8
Typ
Max Unit
μs
7
VNRES_low
V
8
VNRES_high
2
V
9
RNRES_PULL_DOWN
70
100
130
kΩ
*) Not tested in production
1) The output voltage of the internal VDD-regulator
5.1.3 PSI5 INTERFACE
5.1.3.1 Interface Driver
Table 5.1.3.1-1: Electrical Parameter Table of the Interface Driver
No.
Description
Condition
Symbol
Min
Typ
Max Unit
VBUS V
1
Voltage at pin SIFx (x=1-4),
low power mode*)
Low voltage mode; VSIFx_lp_VBUS_min 4.543
Test condition for
VSIFX_min measure-
ment:
VBUS=5.05V;
SIFX_OP=65mA and
I
VBUS is supplied dir-
ectly
2
Voltage at pin SIFx (x=1-4), low power Low voltage mode;
mode*)
VSIFx_lp
4.405
5.05
V
VBUS=4.6V..5.05V;
Test condition for
VSIFX_min measure-
ment:
V
BUS=4.6V;
ISIFX_OP=25mA and
VBUS is supplied dir-
ectly
3
Voltage at pin SIFx (x=1-4), common
mode*)
Standard mode;
Condition for
VSIFX_min measure-
ment:
VSIFx_std
5.943
VBUS
V
VBUS=6.45V;
ISIFX_OP=65mA and
VBUS is supplied dir-
ectly
4
Voltage at pin SIFx (x=1-4), common
mode*)
Increased mode;
Condition for
VSIFX_min measure-
ment:
VSIFx_inc
6.963
VBUS
V
VBUS=7.47V;
ISIFX_OP=65mA and
VBUS is supplied dir-
ectly
5
Resistance between pin VBUS and pins
SIFx
ISIFX_OP =65mA,
including temperat-
ure drift and long
term drift
RVBUS_SIFx
4.5
7.8
Ω
*) Not tested in production
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Data Sheet
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QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
5.1.3.2 Over Current Detection and Limitation
Table 5.1.3.2-1: Electrical Parameter Table of the Over Current Detection and Limitation
No.
1
Description
Condition
Symbol
ILIM_SIFx
Min
Typ
Max Unit
Sensor interface current limitation
-130 -100
200
-75
mA
mA
2
Threshold value for detection of SCG "hard
short"(low impedance to GND)*) 1)
ISIFx_HaSh
3
Activation time for over current limitation at
pin SIFx at "hard short"*)
Over current switch off delay*)
t SIFx_ HaSh_act
300
566
ns
4
5
t SIFx_ LIM_act
tOC_SIFx_5ms
491
544
µs
SIFx over current start up delay (default
value:ASIC_CNFG_3:BL_CHANNEL_1-
4=0000)*)
5.007 5.248 5.458
ms
6
SIFx over current start up
delay(ASIC_CNFG_3:BL_CHANNEL_1-
4=1111)*)
tOC_SIFx_10ms
10.014 10.464 10.882 ms
*) Not tested in production
1) SCG:Short to GND
5.1.3.3 Reverse Current Detection and Limitation
5.1.3.3.1 Reverse Current Flow from SIFx to VBUS
Table 5.1.3.3.1-1: Electrical Parameter Table of the Reverse Current Detection and Limitation (Revese Current
Flow from SIFx to VBUS)
No.
Description
Condition
Symbol
Min
Typ
Max Unit
1
Reverse current into SIFx-pin in ON-state equal to
ISIFx_REV_ON
200
mA
ΔVREV_TRIG /RVBUS-
SIFx
2
3
Reverse current into SIFx-pin in OFF-state*)
ISIFx_REV_OFF
ISIFx_REV_THR
1
mA
mA
Threshold value for detection of the
reverse current1)
10
61
30
60
4
5
Activation time for reverse protection at
pins SIFx*)
tSIFx_REV_act
500
100
ns
SIFx reverse current shut-off activation
time (deglitcher)*)
tSIFx_REV_CUR
96
μs
*) Not tested in production
1)
Δ
VREV_TRIG=VBUS-VSIFx in short to VBAT condition
5.1.3.3.2 Reverse Current Flow from SIFx to CSYNC
Table 5.1.3.3.2-1: Electrical Parameter Table of the Reverse Current Detection and Limitation (Reverse Current
Flow from SIFx to CSYNC)
No.
Description
Condition
Symbol
Min
Typ
Max Unit
1
Threshold value for detection of the
reverse current
ICSYNC_REV_THR
-100
-4
mA
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QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
5.1.3.4 Data Comparator
Table 5.1.3.4-1: Electrical Parameter Table of the Data Comparator
No.
Description
Condition
Symbol
Min
Typ
Max Unit
1
Data comparator threshold
low->high transition
Low power mode
ICOMP_th_lp_lh
-8.3
-6.3
-4.3
mA
mA
mA
mA
2
3
4
Data comparator threshold
high->low transition
Low power mode
Common mode
Common mode
ICOMP_th_lp_hl
ICOMP_th_com_lh
ICOMP_th_com_hl
-7.7
-5.7
-3.7
Data comparator threshold
low->high transition
-16.6 -12.6 -8.6
-15.4 -11.4 -7.4
Data comparator threshold
high->low transition
5
6
7
Data comparator hysteresis*)
Data comparator hysteresis*)
Data comparator filter time (deglitcher)*) Manchester code
Low power mode
Common mode
ICOMP_hys_lp
ICOMP_hys_com
IDATA_DGL_lf
0.6
1.2
mA
mA
ns
480
320
750
pattern 125kbps;
2bit deglitcher; res-
olution 250ns;
8
Data comparator filter time (deglitcher)*) Manchester code
IDATA_DGL_hf
500
ns
pattern 189kbps;
2bit deglitcher; res-
olution 167ns;
*) Not tested in production
5.1.3.5 Sync Pulse Generation
5.1.3.5.1 Sync Pulse Generation DC-Parameter
Table 5.1.3.5.1-1: Sync Pulse Generation DC-Parameter
No.
Description
Sync slope reference voltage*)
Condition
Symbol
Min
Typ
Max Unit
1
Referenced to VSIFx
t2 defined by Vt2
;
;
;
Vt0
0.5
V
2
Lower boundary of sync signal sustain Low power mode;
voltage*)
Vt2_lp
2.5
3.5
V
V
Referenced to VSIFx
t2 defined by Vt2
3
4
5
6
Lower boundary of sync signal sustain Common mode;
voltage*)
Referenced to VSIFx
Vt2_com
Vt3_lp
Vt3_com
Vt3_rippple
Upper boundary of sync signal sustain Low power mode
voltage
2.7+VS 3.7+VS 4.3+VS
V
V
IFX
IFX
IFX
Upper boundary of sync signal sustain Common mode
voltage
4.2+VS 4.8+VS 5.5+VS
IFX
IFX
IFX
Ripple of voltage Vt3 Test condition:
(supply rejection between pins CSYNC t=close to end of
and SIFx)*)
100 mVPP
short sync signal
=>t=t0+15 s;
μ
7
8
Current limitation during Sync pulse
slope*)
ICSYNC_LMT
VCSYNC_DR
-210.0 -150.0 -110.0 mA
0.8
CSYNC voltage drop between pin
CSYNC and SIFx
V
*) Not tested in production
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QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
5.1.3.5.2 Sync Pulse Generation AC Parameter
Table 5.1.3.5.2-1: Sync Pulse Generation AC-Parameter
No.
Description
Condition
Symbol
Min
Typ
Max Unit
1
Sync slope rising slew rate
Transition from
Vt0 to Vt2;
24nF<=CBUS<=10
7nF;
4mA<=ISIFx<=35
mA
SRrise
0.43
1.5
V/µs
V/µs
µs
2
3
Sync slope falling slew rate
Transition from
Vt2 to Vt0;
24nF<=CBUS<=10
7nF;
4mA<=ISIFx<=35
mA
SRfall
-1.5
Reference time for Sync slope*) 1)
Reference time
base defined at
Vt0
t0
0
4
5
6
7
8
9
Sync signal earlist start*) 1)
Sync signal sustain time*) 1)
Sync signal sustain time*) 1)
Discharge time limit*) 1)
t1
t03
t13
t04
t14
-1
16
43
µs
µs
µs
µs
µs
µs
Short sync pulse
Long sync pulse
Short sync pulse
Long sync pulse
35
62
Discharge time limit*) 1)
Minimum idle time of Tx_LEN counter*)
tTx_LEN_IDLE
32
*) Not tested in production
1) see timing diagram Figure 6.1.3.6-1
5.1.3.6 Sync Pulse Generation by Pin TRIG
Table 5.1.3.6-1: Trigger via Pin TRIG
No.
Description
Condition
Symbol
Min
Typ
Max Unit
1
Schmitt-Trigger - low input level at pin
TRIG
VSMT_L
0.8
V
2
3
Schmitt-Trigger - high input level at pin
TRIG
VSMT_H
2
V
Trigger pulse at pin TRIG - short SYNC
pulse*)
70% of rising
slope to 30% of
falling slope
ttrig_sh_pulse
10
40
15
45
50
20
μs
4
5
Trigger pulse at pin TRIG - long SYNC
pulse*)
70% of rising
slope to 30% of
falling slope
ttrig_lng_pulse
50
μs
Trigger pulse rise and fall*)
Trigger pulse filter time*)
Transition from
20% to 80%
(and vice versa);
ttrig_RI/RA
ns
6
7
3bit deglitcher;
resolution 1µs
tDGL_trig
tDLY
4.72
5
5.2
μ
s
s
Delay counter to distinguish between
short/long SYNC pulse*)
30
μ
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4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
No.
Description
SYNC pulse delay timer*)
Condition
Symbol
Min
Typ
Max Unit
8
step size = 2µs;
configuration via
UART/SPI with
10bit
tSYNC_DLY
0
8/fCLK_I
NT*(210-
1)
μs
9
SYNC pulse delay from counter*)
tSYNC_DLY_CNT
tSYNC_REP1
32/fCLK_
μs
μs
μs
INT
10 Time between two sync pulses on different
SIFx channels*)
0
11 Sync pulses repetition time on the SIFx
channel*)
limited if charge
pump is used;
Applies for ISIFx_Q
=4...-19mA
tSYNC_REP2_std
200
(standard cur-
rent)
12 Sync pulses repetition time on the SIFx
channel*)
limited if charge
pump is used;
Applies for ISIFx_Q
=4...-35mA
tSYNC_REP2_ext
300
μs
(extended cur-
rent)
13 Pull down resistor pin TRIG, applies for
voltage VTRIG<3.3V
RTRIG_PULL_DOWN
ITRIG_PULL_DOWN
70
10
100
150
60
kΩ
14 Pull down current pin TRIG, applies for
voltage VTRIG>3.3V
*) Not tested in production
μA
5.1.4 CLOCK GENERATION
Table 5.1.4-1: Electrical Parameter Table of the Internal Oscillator
No.
1
Description
Internal oscillator clock frequency1)
Condition
Symbol
fCLK_INT
Min
Typ
Max Unit
11.52 12.00 12.48 MHz
*)
2
Duty cycle of fCLK_INT
DCCLK_INT
40
60
%
*) Not tested in production
1) trimmed
5.1.5 DIAGNOSIS
5.1.5.1 ADC Voltage Measurements
Table 5.1.5.1-1: Electrical Parameter Table of the ADC.
No.
1
Description
Condition
Symbol
VREFH
Min
2.6
Typ
Max Unit
Positive reference voltage
2.7
2.75
250
V
2
Offset measurement of VBUS diagnosis
voltage of ADC output
VBUS=4.6V .. 11V
VBUS=4.6V .. 11V
VCSYNC=8V .. 33V
VCSYNC=8V .. 33V
VBUS_Offset
-450
mV
3
4
5
Gain measurement of VBUS diagnosis
voltage of ADC output
VBUS_Gain
VCSYNC_Offset
VCSYNC_Gain
0.94
-1.8
0.85
1
1
1.06
1.4
VBUS
V
Offset measurement of VCSYNC diagnosis
voltage of ADC output
Gain measurement of VCSYNC diagnosis
voltage of ADC output
1.15 VCSYNC
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Data Sheet
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QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
No.
Description
Condition
Symbol
Min
Typ
Max Unit
6
Offset measurement of VDD diagnosis
voltage of ADC output
VDD=3.0V ..
5.5V
VDDOffset
-400
200
mV
7
8
9
Gain measurement of VDD diagnosis
voltage of ADC output
VDD=3.0V ..
5.5V
VDDGain
VSIFX_Offset
VSIFX_Gain
VCP_LDO
VCP_LDO
VCP_LDO
VDD_INT
0.93
-450
0.94
1
1.07 VDD
Offset measurement of VSIFX diagnosis
voltage of ADC output
VBUS=4.6V .. 11V
250
mV
VBUS
V
Gain measurement of VSIFX diagnosis
voltage of ADC output
VBUS=4.6V .. 11V
1
1.06
10 Measurement of VCP_LDO diagnosis voltage VSUPPPLY=5.3V,VB
of ADC output US=7V
11 Measurement of VCP_LDO diagnosis voltage VSUPPPLY=6.95V,V
of ADC output BUS=7V
12 Measurement of VCP_LDO diagnosis voltage VSUPPPLY=8V,VBUS
of ADC output =7V
10.2 12.2 14.2
12.2 14.2 16.2
13.2 15.2 17.2
V
V
13 Measurement of VDD_INT diagnosis voltage VDD=3.3V
of ADC output
3.0
3.0
3.2
3.2
3.4
3.4
V
14 Measurement of VDD_INT diagnosis voltage VDD=5V
of ADC output
VDD_INT
V
5.1.5.2 Over Temperature Monitoring (OT)
Table 5.1.5.2-1: Electrical Parameter Table of the Over temperature Sensing:
No.
Description
Condition
Symbol
Min
Typ
Max Unit
1
Junction temperature threshold value; low-
>high transition*)
TJ_HI
154
165
174
°C
2
Junction temperature threshold value; high-
>low transition*)
TJ_LI
145
155
165
°C
3
4
Junction temperature hysteresis*)
TJ_HYS
tOT
10
°C
Over temperature filter time (deglitcher)*)
8.1
ms
*) Not tested in production
5.1.5.3 VBUS Over Voltage Monitoring
Table 5.1.5.3-1: VBUS over voltage monitoring
No.
Description
Condition
Symbol
Min
Typ
Max Unit
1
VBUS over voltage comparator - threshold
value
VBUS_OV_THR
11.8
13
V
2
3
VBUS over voltage comparator - hysteresis*)
VBUS over voltage filter time (deglitcher)*)
VBUS_OV_HYS
tVBUS_OV
0.5
61
V
96
100
μs
*) Not tested in production
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Data Sheet
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QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
5.2 DIGITAL PART
5.2.1 SPI
5.2.1.1 DC Electrical Parameter Table of SPI IOs
Table 5.2.1.1-1: DC Electrical Parameter Table of the Digital Inputs and Outputs
No.
1
Description
Condition
Symbol
VTHDIG_L
Min
Typ
Max Unit
Input threshold low SDI_RXD, NCS,SCLK
Input threshold high SDI_RXD, NCS,SCLK
Output voltage SDO_TXD low
0.8
V
2
VTHDIG_H
2
V
V
V
3
ISDO_TXD_L=3.2mA
ISDO_TXD_H=-2mA
VSDO_TXD_L
VSDO_TXD_H
0.4
VDD
4
Output voltage SDO_TXD high
VDD-
0.4V
5
6
Pull Up resistor NCS
Pull Up resistor RXD
RNCS_PULL_UP
70
100
100
130
130
k
Ω
Ω
RSDO_RXD_PULL_UP 70
k
5.2.1.2 AC Electrical Parameter Table of SPI I/Os
Table 5.2.1.2-1: Electrical Parameter Table of SPI
No.
1
Description
Condition
Symbol
fSCLK
Min
0
Typ
Max Unit
SPI frequency*)
5
MHz
ns
2
SDO_TXD rise and fall time*)
20pF...150pF
load
tsdo_trans
5
35
3
4
5
Minimum time CLK=LOW*)
Minimum time CLK=HIGH*)
tclh
tcll
75
75
ns
ns
ns
Propagation delay (SCLK to data at SDO 150pF load; from
active)*)
tpcld
50
75
SCLK=2.3V to
SDO=0.5*VDD_SUP
, applies for
3.3V/5V;
6
7
NCS low to output SDO active*)
150pF load
tcsdv
tsclch
ns
ns
SCLK low before NCS low (setup time
SCLK to NCS change H/L)*)
75
8
9
SCLK change L/H after NCS=low*)
thclcl_app
tscld
600
15
ns
ns
SDI input setup time (SCLK change H/L
after SDI data valid)*)
10 SDI input hold time (SDI data holdafter
SCLK change H/L)*)
thcld
15
ns
11 SCLK low before NCS high*)
12 SCLK high after NCS high*)
13 NCS L/H to SDO@high impedance*)
tsclcl
thclhc
tpchdz
ton_NCS
100
100
ns
ns
ns
ns
75
40
14 NCS min. high time between two consecut-
ive commands*)
15 NCS filter time*)
*) Not tested in production
700
10
tfNCS
ns
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6 Functional Description
6.1 ANALOG PART
6.1.1 SUPPLY
Various supply voltage concepts are supported by the device due to the various possible applications. The device
is supplied via the pin VSUPPLY with an appropriate voltage. This voltage supplies an external transistor that is driven
by an internal LDO via the pin VG. The output of the external transistor is fed back via the pin VBUS to the LDO con-
trol block.
If an external NMOS transistor is used, the internal error amplifier has to be compensated with an external com-
pensation capacitor CK connected between VG and AGND. For low supply voltages VBUS on the ECU, the ASIC can
be supplied directly at pin VBUS with the voltage provided by VSUPPLY, when no voltage drop between the pins VSUP-
PLY and VBUS can be accepted. In this case the LDO must be disabled.
The voltage VCSYNC , which is necessary for providing the sync pulse is generated in the block CHARGE PUMP
FOR SYNC VOLTAGE (CP). The voltage VCSYNC is available at the pin CSYNC. Alternatively, the CSYNC voltage
can be supplied directly at the pin CSYNC with external voltage VCSYNC. The VCSYNC charge pump must be disabled
in this case. The following table gives an overview of possible supply voltage concepts, which can be chosen via
SPI or UART commands.
Table 6.1.1-1: Overview Supply Voltage Concepts
Config
Options
VDD
VSUPPLY
VBUS
VCSYNC
LDO CP
enabled enabled
A
B
C
D
VDD supplied
directly
VSUPPLY
supplied directly
Generated by LDO Generated by
charge pump
YES
YES
NO
YES
NO
VDD supplied
directly
VSUPPLY
supplied directly
Generated by LDO VSYNC supplied
from ECU
VDD supplied
directly
N.A.
VBUS supplied dir-
ectly
Generated by
charge pump
YES
NO
VDD supplied
directly
N.A.
VBUS supplied dir-
ectly
VSYNC supplied
from ECU
NO
6.1.1.1 LDO Control Block
A low drop out regulator (LDO) with external NMOS and compensation capacitor CK is implemented to generate a
stable VBUS voltage out of the input voltage VSUPPLY. A LDO control circuit is implemented to drive the external NMOS
transistor. Three voltage levels for VBUS are configurable via bit combination ASIC_CNFG_1[V_BUS] (see descrip-
tion of register ASIC_CNFG_1 for details). The LDO control circuit is disabled by default value
ASIC_CNFG_1[V_BUS]="00". The voltage loop has be to compensated with an external compensation capacitor
CK at pin VG for stability reasons. The LDO charge pump provides an appropriate voltage VCP_GATE for control of the
external NMOS transistor at pin VG. A gate source voltage clamping to the voltage VGS_CLMP is implemented.
6.1.1.2 Charge Pump for Sync Voltage
A charge pump is used to generate the SYNC pulse voltage from the voltage VBUS. The charge pump consists of
two external capacitors, the fly capacitor CP connected to pins CP1 and CP2, the storage capacitor CSYNC con-
nected to pin CSYNC, two diodes and two high voltage switches inside the IC. The charge pump is configurable via
bit ASIC_CNFG_3[EN_CP_SYNC] (see description of register ASIC_CNFG_3).
•
•
EN_CP_SYNC='0' means disabled
EN_CP_SYNC='1' means enabled
The charge pump circuit is disabled for the asynchronous mode. If the charge pump is not used, then it is not
allowed to connect the pin CSYNC with ground. The diode path from VBUS to CSYNC will result in high current and
destruction of IC.
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6.1.2 POR AND POWER-UP SEQUENCE
The POR-block observes the voltages VDD_INT, VANA, NRES, VAGND and VPGND. It generates the POR-signal. During
the power up time, the following actions take place:
•
•
•
The voltage regulators VDD_INT and VANA provide the voltage VDD_INT and VANA
The bandgap/biasing block provides the voltage VBG and the bias
The internal oscillator starts up and provides a stable clock frequency for the digital part After power-up time, the
rising edge of the NRES determines the interface mode (SPI/UART), depending on the state of the pin NCS.
When NCS is LOW the UART interface is selected. When NCS is HIGH the SPI is chosen. During the power up
time is not allowed to change the logic level of NRES.
6.1.3 PSI5 INTERFACE
6.1.3.1 Interface Driver
Each of the four interfaces provide a voltage VSIFx and a current ISIFx for the connected satellite sensors by "switch-
ing" voltage VBUS to the pin SIFx via internal transistor switches and shunt. The interfaces are short-circuit protected
to VBAT and GND. The four interfaces operate independent from each other. The interfaces can be en-/disabled via
an UART/SPI command with the bits EN_CHx , described in register ASIC_CNFG_3. The default state of the inter-
face is disabled. The current sensing block includes an IBASE tracking function and the DATA-comparator.
Any time a channel is enable by [EN_CHx], a blanking time is started. During this delay time tSIFx_BLANKING, the
Manchester decoder, SYNC pulse generator and overcurrent filter time tOC_SIFx are disabled.
No channel enable possible if following error bits are set to '1':
- ERROR_STATUS_1[VBUS_OV]
- ERROR_STATUS_x[REV_CUR_CHx] if REV_CUR_CH_DIS='1'
- ERROR_STATUS_x[OC_CHx]
- ERROR_STATUS_1[DIAG_OT]
6.1.3.2 Over Current Detection and Limitation
The circuit provides an over current limitation and protection of the interfaces. The current limitation for ISIFx is imple-
mented with a voltage measurement over the shunt resistor RSH and with the control of the transistor T2. If the cur-
rent ISIFx exceeds the threshold current ILMT_SIFx, the comparator output signal isifx_oc_det is set to high. This signal is
filtered in the digital block by a deglitcher with the filter time tSIFX_LIM_act, latched in the register
ERROR_STATUS_x[OC_CHx] and the appropriate channel is disabled ,that means the affected EN_CHx bits are
reset by the device automatically. To switch on the channel again it is essential to read out the appropriate error
register ("clear on read"). To ensure proper over current detection, the threshold value for overcurrent limitation is
higher than the over current detection threshold.
In order to avoid over current switch off during start up (enable of channels), a blanking time of tOC_SIFX_5ms resp.
tOC_SIFX_10ms is implemented. During this time the over current switch off is disabled. The blanking time can be pro-
grammed in the Register ASIC_CONFG_3 BL_ChannelX.
6.1.3.3 Reverse Current Detection and Limitation
The IC provides two different paths of the reverse current protection:
•
•
from pin SIFx to pin VBUS
from pin SIFx to pin CSYNC
6.1.3.3.1 Reverse Current Flow from SIFx to VBUS
The circuit provides the reverse current detection from SIFx pin to VBUS pin. The reverse current detection is
implemented with a voltage measurement over the shunt resistor RSH (like described in the chapter Over current
Detection). If a reverse current is detected the comparator output signal will be set to high. The signal will be
deglitched and latched in the register ERROR_STATUS_x[REV_CUR_CHx]. The affected channel will be disabled
if configuration bit ASIC_CNFG_2 [REV_CUR_CH_DIS] is set to high and the affected EN_CHx bits are reset by
the device automatically.
To switch on the channel again it is essential to read out the appropriate error register ("clear on read").
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6.1.3.3.2 Reverse Current Flow from SIFx to CSYNC
The circuit provides the reverse current detection from pin SIFx to pin CSYNC. The reverse current detection is
implemented with a MOS-transistor. The reverse current protection circuit stops the reverse current from SIFx pin
to CSYNC pin when SIFx becomes higher then CSYNC.
6.1.3.4 Quiescent Current Threshold Tracking
The quiescent current of the circuit is measured and adapted continously during during operation, to avoid corrup-
ted data transmission because of drift or aging processes.
6.1.3.5 Data Comparator
The satellite sensors modulate the current in order to realize a Manchester coded data transmission.
The "low" level of the current is represented by the quiescent current ISAT_Q_range of the sensor, while a "high" level is
created by switching on a current sink to the line, which increases the current to ISAT_OP
.
A current transition in the middle of the bit time represents the logical value of the transferred data. A "high cur-
rent-low current" transition stand for a logical '1', a "low current-high current" transition for a logical '0'.
This current can be detected by measuring the voltage drop via an internal shunt. The current threshold is automat-
ically adapted to the quiescent current of the sensors.
The threshold value is configured with register ASIC_CNFG_1[ΔIs_CHx] with 1bit per SIFx (changed individually).
The default value is ∆Is='0' (common mode). ∆Is='1' means the threshold value for low power mode is choosen
(see register description of ASIC_CNFG1).
ISAT
BIT1
“0”
BIT2
“1”
BIT3
“1”
ISAT_OP
∆
I
ISAT_TH
ISAT_Q_range
t
TBit
Figure 6.1.3.5-1: Current Modulation
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6.1.3.6 Sync Pulse Generation
For PSI5 synchronous mode, the IC generates the SYNC pulse to synchronize the sensors. During SYNC pulse
the voltage level at pins SIFx will be increased for a defined time and then decreased before the sensor to ECU
communication (current modulation) starts. The SYNC pulse is shaped to limit emissions. The SYNC voltage is
either generated by SYNC pulse charge pump or supplied from external via pin CSYNC.
The voltage level Vt3 is configured with the register ASIC_CNFG_1[VSYNC_V3_CHx] with 1 bit per SIFx (channel
individually).
The IC provide a reverse protection for the short circuit to the battery at the interfaces and current limitation of the
SYNC pulse. The current limitation is active during SYNC sustain time only. The current limitation is disabled during
rising/falling slope to guarantee slope at max. load.
There are two ways to generate an event triggered SYNC pulse:
•
•
by trigger voltage pulse at pin TRIG
by UART/SPI command
Long sync pulse [1]
Short sync pulse [0]
Phase
1
Sync
Start
Phase
2
Sync
Slope
Phase
3
Sync
Sustain
Phase
4
Sync
Discharge
VCE max
Upper Boundary
Vt3
Vt2
Lower Boundary
VTRIG
Vt0
VCE Base
t1
t14
t13
t0
t04
t03
t2
Trigger
Point
Figure 6.1.3.6-1: Sync Pulse Timing Diagram
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6.1.3.7 Sync Pulse Generation by Pin TRIG
Following diagram shows the timing requirements for the trigger voltage pulse at pin TRIG with:
•
•
high time ttrig_sh_pulse for a short SYNC pulse
high time ttrig_lo_pulse for a long SYNC pulse
Example: long SYNC pulse
70%
VTRIG
(Pin TRIG)
30%
ttrig_lo_pulse
i_trig
tDGL_itrig
tDGL_itrig
i_trig_f
long pulse (t13 + t1)
SYNC_time
tSYNC_DLY
ATIC158
timer
SYNC_DLY
VSIFx
t
≥
(
tDGL_itrig + 1/fCLK)
Figure 6.1.3.7-1: Long SYNC Pulse Trigger via Pin TRIG
Example: short SYNC pulse
70%
VTRIG
(Pin TRIG)
30%
ttrig_sh_pulse
i_trig
tDGL_itrig
tDGL_itrig
i_trig_f
tSYNC_DLY
short pulse (t03 + t1)
SYNC_time
ATIC158
timer
SYNC_DLY
VSIFx
t
≥
(
tDGL_itrig + 1/fCLK)
Figure 6.1.3.7-2: Short SYNC Pulse Trigger via Pin TRIG
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6.1.3.8 Sync Pulse Generation by UART/SPI Command
Following timing diagrams show the SYNC pulse generation triggered by a UART or SPI command.
syncronizer
1/(fCLK_EXT) + 4/(fCLK_INT
)
Srt D0 …. D7
P
Stp
UART
long pulse (t13 + t1)
short pulse (t03 + t1)
tSYNC_DLY
ATIC158
timer
SYNC_DLY
SYNC_time
VSIFx
Figure 6.1.3.8-1: Short SYNC Ptrigger via UART
3*1/(fCLK_INT
)
SPI NCS
SPI
...SYNC_PULSE
long pulse (t13 + t1)
short pulse (t03 + t1)
tSYNC_DLY
ATIC158
timer
SYNC_DLY
SYNC_time
VSIFx
Figure 6.1.3.8-2: Short SYNC Pulse Trigger via SPI
6.1.4 CLOCK GENERATION
The internal oscillator is the central clock source for the digital part and provides the clock signal required for the
internal charge pumps. The oscillator starts up automatically as soon as VDD_INT and VANA are stable.
An external clock has to be supplied via pin SCLK for UART communication. The ratio between external clock and
UART baud rate is 5/1 ( = 5 times oversampling for UART telegrams on SDI_RXD).
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6.1.5 DIAGNOSIS
6.1.5.1 ADC Voltage Measurements
Several voltage levels can be measured by the ASIC with an analog-digital converter for diagnostic purposes. The
digital values will be written into status registers after conversion. These registers can be read out by the micro con-
troller via UART/SPI.
An 8-bit ADC (Successive Approximation Register concept) is implemented for diagnosis purposes. In total 9
internal voltages are measured sequentially in a repeating (endless) loop. The measurement of one voltage is
called a cycle.
Steps within a cycle:
•
•
•
Voltage is selected via MUX
ADC conversion is performed
Data is transferred into register DIAGNOSIS_ADC_1_2 to DIAGNOSIS_ADC_9_10
One sequence is performed within tCYC. Each measured voltage is stored in a dedicated register. The update rate of
the register values is given by number of voltages multiplied with cycle time -> 9 x tCYC.The ADC sequence starts
with release of reset automatically. For synchronous mode the values at "pin SIFx" can vary between VSIFx and Vt3,
depending whether a SYNC pulse was generated during conversion time or not. For asynchronous mode the
voltage at pin SIFx is measured properly.
The following table shows the voltage divider ratio of the different voltages.
Table 6.1.5.1-1: Voltage Divider Ratio
Voltage
VBUS
Divider ratio
1/5
1/13
1/7
1/5
1/2
1/3
VSYNC
VCP_GATE
VSIFx
VDD_INT
VDD
6.1.5.2 Over Temperature Monitoring (OT)
chThe junction temperature is monitored with a temperature sensor to detect excessive temperature levels. If the
junction temperature exceeds TJ_HI then following protection actions will be processed automatically:
•
•
All SIFx will be disabled -> reset bit ASIC_CNFG_3[EN_CHx]='0'
The affected EN_CHx bits are reset by the device automatically. To switch on the channel again it is essential to
read out the appropriate error register ("clear on read").
•
•
•
SYNC pulse charge pump will be disabled -> reset bit ASIC_CNFG_3[EN_CP_SYNC]='0'
over temperature event is latched in status register ERROR_STATUS_1[DIAG_OT] after tOT (clear on read)
With read of ERROR_STATUS_1[DIAG_OT], the filter timer for tOT is reseted (deglitcher reset), independently of
the current error status.
•
•
If the read cycle of ERROR_STATUS_1[DIAG_OT] is shorter than tOT, the ERROR_STATUS_1[DIAG_OT] bit
will never be set.
The channel will not be enabled automatically, if the error condition disappears.
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6.1.5.3 VBUS Over Voltage Monitoring
A comparator for VBUS over voltage monitoring is implemented to avoid any damage of PSI5 sensors by exceeding
their input voltage range.
If VBUS exceeds the value of VBUS_OV_THR then following protection actions are processed automatically:
•
•
All SIFx will be disabled -> reset bit ASIC_CNFG_3[EN_CHx]='0'
The affected EN_CHx bits are reset by the device automatically. To switch on the channel again it is essential to
read out the appropriate error register ("clear on read").
•
•
•
SYNC pulse charge pump will be disabled -> reset bit ASIC_CNFG_3[EN_CP_SYNC]='0'
The over voltage event is latched in status register ERROR_STATUS_1[VBUS_OV] after tVBUS_OV (clear on read)
With read of ERROR_STATUS_1[VBUS_OV], the filter timer for tVBUS_OV is reseted (deglitcher reset), independ-
ently of the current error status.
•
•
If the read cycle of ERROR_STATUS_1[VBUS_OV] is shorter than tVBUS_OV, the ERROR_STATUS_1[VBUS_OV]
bit will never be set.
The channel will not be enabled automatically, if the error condition disappears.
6.1.5.4 Leakage to GND, Leakage to VBAT and Open Load
The detection of leakage To GND, leakage to VBAT and open load are implemented in the digital logic, based on
the Ibase tracking function.
The digital counter for IBASE indicates a leakage to GND for high counter values (high quiescent current) and the
actual state is latched in status register ERROR_STATUS_x[DIAG_CHx].
For low counter values either a leakage to VBAT or an open load condition is indicated (low or no quiescent curret).
The actual state is latched in status register ERROR_STATUS_x[DIAG_CHx].
The differentiation of leakage to VBAT / open load failure has to be done by the micro controller
via the status of reverse current protection ERROR_STATUS_x[REV_CUR_CHx]
•
•
Reverse current protection not active [REV_CUR_CHx]='0' -> Open Load
Reverse current protection active [REV_CUR_CHx]='1' -> Leakage to VBAT or via ADC voltage measurement at
pins SIFx (if flag [REV_CUR_CHx]='0'),
•
•
VSIFx = VBUS -> Open Load
VSIFx > VBUS -> Leakage to VBAT
6.1.5.5 GND Loss Detection
A comparator for GND loss detection is implemented to detect missing GND connections.
A detected GND loss results in a reset of the IC.
Following GNDs will be monitored:
•
•
AGND
PGND
6.1.5.6 Transfer of Error- and Diagnosis Information to ꢀController
6.1.5.6.1 Error Information
All error analog/digital information are flagged in status registers ERROR_STATUS_1 ... ERROR_STATUS _10.
Every error is latched and is cleared by a read request by SPI or UART.
An overall error information is transmitted to the micro controller, included in some frames (see below) within bits
Err[1:0]. For detailed error information the dedicated status registers shall be read.
•
•
UART: Bits Err[1:0] included in header (UART frame1)
SPI: Bits Err[1:0] included in the first response frame (SPI frame2)
The error information, bits Err[1:0], are transmitted in following messages to the micro controller:
•
•
UART
•
•
Response to Read Command
Transfer PSI5 Data
SPI
•
Responses to commands "cmd_get data_xxbit"
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These responses allows the μController to know which kind of an error occurred.
(All interface errors, shown in the table below, are flagged in registers ERROR_STATUS_3 to
ERROR_STATUS_10.
Register ERROR_STATUS_2 includes an OR-combination of all interface errors, one bit per channel.
E.g. ERROR_STATUS_2[0] includes the OR-combination of bits in registers ERROR_STATUS_3 and
ERROR_STATUS_4 (=error information of channel 1).)
For detailed information see register table.
Note:
It is recommended to read out register ERROR_STATUS_2 if bit Err[0] (interface error) is set in a response of the
transceiver to determine which channels are affected. In register ERROR_STATUS_2 the four LSBs [3:0] belongs
to channel 4, channel 3, channel 2 and channel 1 and the appropriate channel bit is set in case of an interface error
on the affected channel.
Afterwards the micro controller shall read the dedicated registers ERROR_STATUS_3 .. ERROR_STATUS_10
(depend of the affected channels) to get the detailed error information. There are two detailed error registers avail-
able per channel.
If bit Err[1] (asic error) is set in a message to the micro controller register ERROR_STATUS_1 shall be read for
more information.
It is not recommended to read out the appropriate ERROR_STATUS_X with a cycle time of less than 9ms.
Table 6.1.5.6.1-1: Overview of Possible Error Information
TYPE OF ERROR
ASIC
INTERFACE
FRAME 1-6
ERROR STATUS REGISTER
ERROR BIT FLAG
CH1-CH4
UART parity error. x
ASIC
ERROR_STATUS_1[0]
Err[1]
UART framing
error (invalid stop
bit).
x
ERROR_STATUS_1[1]
Err[1]
ASIC
UART/SPI invalid
command
received. ASIC
x
ERROR_STATUS_1[2]
Err[1]
UART/SPI colli-
sion. ASIC
x
x
x
x
ERROR_STATUS_1[3]
ERROR_STATUS_1[4]
ERROR_STATUS_1[5]
ERROR_STATUS_1[6]
Err[1]
Err[1]
Err[1]
Err[1]
SPI clock error.
ASIC
over temperature
shut down. ASIC
VBUS overvoltage.
ASIC
MCD CRC/Parity
Error. Interface
x
x
Ch1: ERROR_STATUS_3[0]/[4]/[8]/[12], Ch1: ERROR_
ERROR_STATUS_4[0]/[4] STATUS_2[0]
Ch2: ERROR_STATUS_5[0]/[4]/[8]/[12], Ch2: ERROR_
ERROR_STATUS_6[0]/[4] STATUS_2[1]
Ch3: ERROR_STATUS_7[0]/[4]/[8]/[12], Ch3: ERROR_
ERROR_STATUS_8[0]/[4] STATUS_2[2]
Ch4: ERROR_STATUS_9[0]/[4]/[8]/[12], Ch4: ERROR_
ERROR_STATUS_10[0]/[4] STATUS_2[3]
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TYPE OF ERROR
ASIC
INTERFACE
CH1-CH4
FRAME 1-6
ERROR STATUS REGISTER
ERROR BIT FLAG
MD framing error
(frame too
x
x
Ch1: ERROR_STATUS_3[1]/[5]/[9]/[13], Ch1: ERROR_
ERROR_STATUS_4[1]/[5] STATUS_2[0]
Ch2: ERROR_STATUS_5[1]/[5]/[9]/[13], Ch2: ERROR_
ERROR_STATUS_6[1]/[5] STATUS_2[1]
Ch3: ERROR_STATUS_7[1]/[5]/[9]/[13], Ch3: ERROR_
ERROR_STATUS_8[1]/[5] STATUS_2[2]
Ch4: ERROR_STATUS_9[1]/[5]/[9]/[13], Ch4: ERROR_
ERROR_STATUS_10[1]/[5] STATUS_2[3]
Ch1: ERROR_STATUS_3[2]/[6]/[10]/[14], Ch1: ERROR_
ERROR_STATUS_4[2]/[6] STATUS_2[0]
Ch2: ERROR_STATUS_5[2]/[6]/[10]/[14], Ch2: ERROR_
ERROR_STATUS_6[2]/[6] STATUS_2[1]
Ch3: ERROR_STATUS_7[2]/[6]/[10]/[14], Ch3: ERROR_
ERROR_STATUS_8[2]/[6] STATUS_2[2]
Ch4: ERROR_STATUS_9[2]/[6]/[10]/[14], Ch4: ERROR_
ERROR_STATUS_10[2]/[6] STATUS_2[3]
Ch1: ERROR_STATUS_3[3]/[7]/[11]/[15], Ch1: ERROR_
ERROR_STATUS_4[3]/[7] STATUS_2[0]
Ch2: ERROR_STATUS_5[3]/[7]/[11]/[15, Ch2: ERROR_
ERROR_STATUS_6[3]/[7] STATUS_2[1]
Ch3: ERROR_STATUS_7[3]/[7]/[11]/[15, Ch3: ERROR_
ERROR_STATUS_8[3]/[7] STATUS_2[2]
Ch4: ERROR_STATUS_9[3]/[7]/[11]/[15, Ch4: ERROR_
long(short, MC
code violation,
compensation win-
dow violation).
Interface
MD no frame
received. Interface
x
x
x
x
x
x
MD unexpected
frame. Interface
x
ERROR_STATUS_10[3]/[7]
STATUS_2[3]
Diagnosis: leakage
to GND / VBAT.
Interface
Ch1: ERROR_STATUS_4[9:8]
Ch2:
ERROR_STATUS_6[9:8]
Ch3:
ERROR_STATUS_8[9:8]
Ch4:
ERROR_STATUS_10[9:8]
Ch1: ERROR_
STATUS_2[0]
Ch2: ERROR_
STATUS_2[1]
Ch3: ERROR_
STATUS_2[2]
Ch4: ERROR_
STATUS_2[3]
overcurrent. Inter-
face
Ch1: ERROR_STATUS_4[10]
Ch2:
ERROR_STATUS_6[10]
Ch3:
ERROR_STATUS_8[10]
Ch4:
ERROR_STATUS_10[10]
Ch1: ERROR_
STATUS_2[0]
Ch2: ERROR_
STATUS_2[1]
Ch3: ERROR_
STATUS_2[2]
Ch4: ERROR_
STATUS_2[3]
Data buffer config-
uration error
(width=96bit).
Interface
Ch1: ERROR_STATUS_4[11]
Ch2:
ERROR_STATUS_6[11]
Ch3:
ERROR_STATUS_8[11]
Ch4:
ERROR_STATUS_10[11]
Ch1: ERROR_
STATUS_2[0]
Ch2: ERROR_
STATUS_2[1]
Ch3: ERROR_
STATUS_2[2]
Ch4: ERROR_
STATUS_2[3]
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TYPE OF ERROR
ASIC
INTERFACE
CH1-CH4
FRAME 1-6
ERROR STATUS REGISTER
ERROR BIT FLAG
Reverse current.
Interface
x
Ch1: ERROR_STATUS_4[12]
Ch2:
ERROR_STATUS_6[12]
Ch3:
ERROR_STATUS_8[12]
Ch4:
ERROR_STATUS_10[12]
Ch1: ERROR_
STATUS_2[0]
Ch2: ERROR_
STATUS_2[1]
Ch3: ERROR_
STATUS_2[2]
Ch4: ERROR_
STATUS_2[3]
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6.2 DIGITAL PART
6.2.1 COMMUNICATION INTERFACE TO MICRO CONTROLLER
As interface to the micro controller, either an UART or SPI interface can be selected. The pins for both interfaces
are shared.
The interface is configurable from μC
•
•
•
•
with rising edge of NRES the UART / SPI interface is latched
depending on state of pin NCS either UART or SPI is selected
NCS = low means UART
NCS = high means SPI
Following pins are used for UART communication:
•
•
•
SDI_RXD
SDO_TXD
SCLK
Following pins are used for SPI communication:
•
•
•
•
SDI_RXD
SDO_TXD
SCLK
NCS
6.2.2 MANCHESTER DECODER
The manchester decoder is compliant to PSI5 1.3 and 2.1. The following interface diagnosis features are suppor-
ted:
•
•
•
•
•
•
wrong data rate
wrong start bit combination
wrong number of data bits
CRC or parity failure
wrong interframe time
no or unexpected frame
6.2.2.1 Manchester Data Handling and Buffer Architecture
For each channel are a MCD_data_buffer with a width of 36bits and a data_buffer with a width of 96bits
implemented.
•
•
Data_buffer (96bit) is used in different configurations for UART / SPI mode (see figure below).
Data_buffer and MCD_data_buffer will be set to default bit value = '1' if the channel is disabled.
•
•
Disabled either by writing bits ASIC_CNFG_3[EN_CHx] via UART/SPI Write_Register command or
by automatically switch-off in an error condition (e.g. over current error).
Channel4
Channel3
Channel2
Channel1
MCD
(manchester
decoder )
bitupload
(withendof
decodedbit )
MCD_
data_buffer
PSI5 DataFrame
(fromsensor)
parallel upload
(endofvalidframe )
data_buffer
width =96bit
width =36bit
Figure 6.2.2.1-1: Buffer Architecture Overview
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6.2.2.1.1 UART DATA BUFFER
UART buffer behavior:
•
•
•
•
•
One frame will be stored
Data will be filled up starting at bit0 (LSB) of buffer
Empty bits will be filled up with default bit value = '1' ('1' not used as frame ID)
Min data length = Fid0...Fid2 + Err0...Err1 + D0...D7 + parity;
Max data length = Fid0...Fid2 + Err0...Err1 + D0...D27 + CRC;
Σ
= 14bit
= 36bit
Σ
'''With an appropriate UART baud rate, the IC transmits the data to the
overwriting.'''
μ
Controller without any
S1 S2
D0 ...Dn
CRC/PAR
PSI5 Data Frame
(from sensor)
MCD shall...
-removestartbits
- addframeidentifier Fid [0:2]
- adderror bitsErr [0:1]
Manchester decoder
MCD_data_buffer
Fid [0..2] Err [0..1]
D0 ...Dn
CRC/PAR
parallel uploadwithvalidstop
conditionofMCD
(endof validframe )
LSB
MSB
data_buffer –
UART configuration
0
data
13...35
14...36
default = ’1'
95
Figure 6.2.2.1.1-1: UART Data Buffer
6.2.2.1.2 SPI DATA BUFFER
SPI data buffer behavior:
•
MCD_data_buffer has a length of 36bit; only the configured nb of bits (according TSx_FLEN) + Err[0:1] + Fid[0:2]
are uploaded into SPI_data_buffer; the remaining bits of MCD_data_buffer are filled up (stuffed) with '1'. A spe-
cial case occurs for SPI_BUFFER_CONFIG =0b00 (48bit): after upload of MCD_data_buffer, bits [0:35] includes
data + stuffing '1', whereas bits [36:47] are stuffed with '0' (described as don't care bits in Figure Figure 6.2.3.9.4-
1). This doesn't matters for other SPI_BUFFER_CONFIG configuration as buffer length is smaller than
MCD_data_buffer length.
•
The data_buffer has to be configured during IC start up, by bits CHx_CFG7[SPI_BUFFER_CONFIG]. The buffer
is divided in blocks with equal number of bits.
Data will be filled up starting at LSB of every individual block
•
•
Unused buffer identifiers (BID[x]) are filled up with value = '1' (per default). A read request will result in
μC can detect that no data were written into this block (wrong BID[x] was
•
Frame identifier - Fid[2:0] ='111'->
read).
Error Bits - Err[1:0] = '11' -> μC has to discard (default values instead of error information)
•
•
It's mandatory to read block wise via commands SPI_Get_Data_xxb according the appropriate buffer
configuration. This means for SPI_BUFFER_CONFIG="11" the command SPI_Get_Data_16b is mandat-
ory.
•
•
After reading, all bits per block will be filled up with default bit value = '1'
During transfer from MCD_data_buffer to data_buffer, an error is flagged in ERROR_STATUS_4/6/8/10[11] =
BUFF_ERR_CHx if number of bits(MCD_data_buffer) > number of bits per BID. In this case no data is trans-
ferred.
•
The data_buffer is completely erased (filled up with default value ='1') if a channel is disabled, e.g. by
ASIC_CNFG_3[EN_CHx]='0', VBUS overvoltage, overtemperature or overcurrent shut down.
The number of PSI5 data bits (payload) per buffer identifier (BID) is shown in the table below for all configurations.
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Figure 6.2.2.1.2-1: SPI Data Buffer
If number of frames higher than number of configured buffers (Fid > BID):
•
•
A buffer has to be used for several frames
Controller has to ensure to read buffer data before new data is loaded, otherwise it's overwritten.
μ
Following example shows buffer configuration CHx_CFG7[SPI_BUFFER_CONFIG]=0b01 with 4 identical PSI5
frames:
Example: 4 frames, including (Fid[0:2] + Err[0:1] + D[0:19] + CRC); ∑ = 28bit
frame1
BID[0]
frame2
frame3
frame4
CHx_CFG7
[SPI_BUFFER_CONFIG]
0
0
27 stuffing 32
3132
BID[1]
59 stuffing 64
63 64
BID[2]
91 stuffing
95
0b01
Figure 6.2.2.1.2-2: SPI Data Buffer incl. 4 Frames
Table 6.2.2.1.2-1: SPI Buffer Configuration
CHx_CFG7 [SPI_BUFFER_CONFIG]
Σ per BID [bit]
FiD + Err [bit]
max payload = PSI5
data w/o start bits
[bit]
0b00
0b01
0b10
0b11
48*
32*
24*
16*
5
5
5
5
43
27
19
11
*: Please note the appropriate SPI_Get_Data_xxb-command selected by the number of bits in this column.
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6.2.2.2 Manchester Bit Encoding
6.2.2.2.1 Definition of data edge / compensation edge
According PSI5 standard, a current transition in the middle of the bit time represents the logical value of the trans-
ferred data (Manchester code) with
"high current -> low current" transition for a logical '1',
"low current -> high current" transition for a logical '0'.
Within this specification, this transition is called data edge; transitions at start / end of the bits are called compens-
ation edge.
6.2.2.2.2 Interpretation with Manchester Decoder
The implemented Manchester Decoder (MCD) state machine converts PSI5 data (transmitted by sensors in
Manchester code) into NRZ code.
The input signal is filtered by the analog datacomparator.
The user is able to configure the time slot in which a data edge / compensation edge is accepted via register
ASIC_CNFG_1[MCD_DATA_CMP_WINDOWS].
In principle, the default configuration is recommended with MCD_DATA_CMP_WINDOWS=0b00.
For certain pattern of electro-magnetic disturbers (from environment) the configuration of MCD_DATA_CMP_WIN-
DOWS=0b01 could improve immunity by decreasing the data edge window, but reduces the range of MCD duty
cycle.
6.2.2.2.3 Definition of Duty Cycle
PSI5 frame @ 125kBit/s
Clock 4MHz 25
Thigh
D0 = '0'
D1='1'
26 27 28 29 30 31 32
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
10 11 12 13 14 15 16 17 18 19 20 21 22
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
Duty cycle
[nb of
samples of 32]
[%]
16
16
11
21
16
11
21
50
16
21
35
65
11,2
20,8
11
Figure 6.2.2.2.3-1: Example MCD Duty Cycle
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6.2.2.2.4 Decoder Error Flags
The following chapter gives some details about the setting of flags MD_PERR_CHx_Fx, MD_FERR_CHx_Fx,
MD_NO_FR_CHx_Fx and MD_UNEX_FR_CHx_Fx.
slot counter
111
000
001
frame
error
PSI5 data
MCD: valid start bit
MD_FERR_CHx_Fx
MD_NO_FR_CHx_Fx
latched
Figure 6.2.2.2.4-1: MD_FERR_CHx_F1
Note that for a special failure condition two error flags for one frame can be set.
Failure condition:
e.g. default IC configuration; PSI5 sensor with 189kbps connected (instead of 125kbps); depending on PSI5 data,
either 1 or 2 error bits are flagged.
slot counter
111
000
001
frame
error
PSI5 data
MCD: valid start bit
MD_FERR_CHx_Fx
MD_NO_FR_CHx_Fx
no start bits detected
in slot 0‚ 00 '
latched
latched
Figure 6.2.2.2.4-2: Set Of Error Flags (2errors; data=0x3FF)
6.2.3 SPI
The SPI communication between one master and multiple slaves can be operated in parallel or in daisy chain.
Parallel Operation
Several SPI-slaves can be connected to one SPI channel. The communication lines SDI_RXD, SDO_TXD and CLK
are shared and every slave has its own chip select line (NCS).
Daisy Chain Operation
Several slaves can be connected to the ꢀC in daisy chain operation to save ꢀC interface pins (one common chip
select line for all slaves in the chain).
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tON_NCS
Data Flow
tSPI_switch
NCS
tsclcl
thclch
tsclch
thclcl_an
tclh
tcll
thclcl_app
SCLK
tpcld
tpchdz
tSPI_switch
tSDO_trans
SDO_
TXD
MSB
LSB
thcld
tcsdv
tscld
SDI_
RXD
MSB
LSB
tSPI_switch
SPI-ECU12-V3.0.vsd
Figure 6.2.3-1: Data Flow Graphic
In case NCS is high, any signals (e.g. very high clock frequencies e.g. 20MHz max.) at the SCLK and SDI_RXD
pins are ignored, and SDO_TXD remains in a high impedance state. After an NCS High to Low transition, the SPI
response word is multiplexed from the latches that were specified by the last command into the shift register, i.e.
the SDO_TXD changes from high impedance state to the state of the MSB of the last addressed SPI register, inde-
pendent of the SPI clock state.
The SCLK pin must be low when NCS switches to low.
At each rising edge of the clock pulse after NCS goes low, the response word is serially shifted out on the
SDO_TXD pin.
At each falling edge of the clock pulse (after NCS goes low) the new control word is serially shifted in on the
SDI_RXD pin. The SPI command bits are decoded to determine the destination address for the data bits. After the
16th (or multiple of 16, for daisy chains) clock cycle, at the next NCS low to high transition, the SPI shift register
data bits are transferred into the latch whose address was decoded from the SPI shift register command bits.
A command is executed after 16 SCLK (or a multiple of 16) and NCS goes high.
During reset, SDO_TXD is forced into a high impedance state and any inputs from SCLK and SDI_RXD are
ignored.
SPI Format
Each device is controlled with a 16 bit control command, see following chapters.
The command is stored in a command register after the rising edge of NCS. The response consists of a 16 bit word
which contains the before requested information like e.g. diagnostic or output state.
Response after Reset or Communication Error
In case of reset or communication error (not valid commands, number of clocks not multiples of 16) following
response will be sent in the next valid SPI frame: "0x0000". The execution of not valid commands is blocked and
command with NCS low without clock are ignored.
Order of MSB/LSB Bit
MSB is sent first.
CRC
SPI Packet Frames from transceiver to μController include a XCRC (see 6.2.5).
Daisy Chain
Daisy chain operation is supported.
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6.2.3.1 Error Handling
Figure 6.2.3.1-1: SPI Error Handling Example 1
1: Examples invalid command for 'Read Sensor Data 16bit':
Figure 6.2.3.1-2: SPI Error Handling Example 2
4a: Example: Command 'SPI_Read_Register' including invalid address A[5:0]:
Figure 6.2.3.1-3: SPI Error Handling Example 3
4b: Example: Command 'SPI_Read_Register' including Stuff
0 (frame n):
Figure 6.2.3.1-4: SPI Error Handling Example 4
4c: Example: Command 'SPI_Read_Register' including Stuff 0 (frame n+1):
Table 6.2.3.1-1: SPI Communication Error
1
invalid commands
ERROR_STATUS_1
[UART_SPI_INV_CMD]
number of clocks NOT multiples ERROR_STATUS_1
of 16 [SPI_CLK_ERR]
command rejected
command rejected
command rejected
2
3a
command 'SPI_Write_Register' ERROR_STATUS_1
including invalid address A[5:0] [UART_SPI_INV_ADDRESS] &
[UART_SPI_INV_CMD]
3b
command 'SPI_Write_Register' No flag
0 (in frame
frame n+1: correct response
frame n+2: wrong XCRC (6bit
stuff is used for calculation)
including stuff
n+1)
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4b
4c
command 'SPI_Read_Register' see #1
including stuff 0 (in frame n)
command 'SPI_Read_Register' no flag
command rejected
frame n+1: correct response
frame n+2: send zero response
including inverted XCRC to uC
including stuff
n+1)
0 (in frame
5a
5b
5c
commands 'SPI_Get_Data_xxb' ERROR_STATUS_1
- NOT according buffer config- [UART_SPI_INV_ADDRESS]
uration
command rejected
command rejected
command rejected
e.g.
SPI_BUFFER_CONFIG="00"
and "SPI_Get_Data_16/24/32b"
commands 'SPI_Get_Data_xxb' see #5a
- according buffer configuration
- including invalid ChID[2:0]
Invalid channel identifier
ChID[2:0]: '000' / '101' / '110' /
'111'
commands 'SPI_Get_Data_
xxb' - according buffer configur-
ation - including invalid BID[2:0]
see #5a
Invalid buffer identifier BID[2:0]
depends on configuration:
e.g.
SPI_BUFFER_CONFIG=0b00
-> '010' / '011' / '100' / '101' /
'110' / '111'
5d
5e
commands 'SPI_Get_Data_
0 (in
see #1
no flag
command rejected
xxb' - including stuff
frame n)
commands 'SPI_Get_Data_
0 (in
frame n+1: correct response
frame n+2 till before the end of
command response: communic-
ation error
xxb' - including stuff
frame n+1)
Last command response: send
zero response including inver-
ted XCRC to uC
5f
commands 'SPI_Get_Data_
xxb' - including correct
SPI_SYNC_PULSE cm with
see #1
frame n+1: correct response
frame n+2 till before the end of
command response: communic-
ation error
4bit stuff
0 (in frame n+1)
Last command response: send
zero response including inver-
ted XCRC to uC
6
command 'SPI_SYNC_PULSE' see #1
- including stuff 0 (in frame n)
command rejected
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9
command 'SPI_SW_RESET' - see #1
including stuff 0 (in frame n)
command rejected
6.2.3.2 Overview of Communication Frames
Table 6.2.3.2-1: Overview of SPI Communication Frames
Communication Commands/Response
SPI Frame n [SPI Packet
SPI Frame n+1 [SPI Packet Frame]
SPI Frame n+2 [SPI
Packet Frame]
SPI Frame n+3 [SPI
Packet Frame]
SPI Frame n+4 [SPI
Packet Frame]
Path
s
Frame]
μC->transceiver
μC->transceiver
μC->transceiver
SPI_NOP
Response
cmd[3:0]; Stuff [11:0]
next cmd
response to previous cmd
cmd[3:0]; A[5:0]; D[15:10]
cmd[3:0]; Stuff [11:0]
D[9:0]; Stuff [5:0]
SPI_Write_Register
SPI_WRITE_Register
SPI_READ_Register
SPI_SYNC_Pulse
SPI_NOP
SPI_SW_Reset
μC->transceiver
Response to
response to previous cmd
cmd[3:0]; A[5:0]; D[15:10];
D[9:0]; XCRC[5:0]
SPI_Write_reg
μ
C->transceiver
C->transceiver
SPI_read_reg
cmd[3:0]; A[5:0]; Stuff[5:0]
response to previous cmd
Stuff[15:0]
next cmd
μ
Response to
cmd[3:0]; A[5:0]; D[15:10]
D[9:0]; XCRC[5:0]
SPI_Read_Register
μC->transceiver
SPI_SYNC_Pulse
cmd[3:0]; ChT[3:0]; ChL[3:0];
Stuf f[3:0]
next cmd
μ
μ
μ
C->transceiver
C->transceiver
C->transceiver
Response
response to previous cmd
response to previous cmd
cmd[3:0]; ChT[3:0]; ChL[3:0]; Stuff[3:0]
cmd[3:0]; Stuff [11:0]
Response
SPI_Get_Data_16b
cmd[3:0]; ChID[2:0]; BID[2:0];
Stuff[5:0]
Stuff[15:0] Optional: SPI_SYNC_Pulse next cmd
cmd[3:0]; ChID[2:0]; BID[2:0]; Stuff[5:0] D[9:0]; XCRC[5:0]
Stuff [15:0] Optional: SPI_SYNC_Pulse Stuff [15:0]
μC->transceiver
μC->transceiver
μC->transceiver
μC->transceiver
μC->transceiver
μC->transceiver
μC->transceiver
Response to
response to previous cmd
SPI_Get_Data_16b
SP_Get_Data_24b
cmd[3:0]; ChID[2:0]; BID[2:0];
Stuff[5:0]
next cmd
Response to
response to previous cmd
cmd[3:0]; CHID[2:0]; BID[2:0] Fid[2:0]; D[17:2]
Err[1:0]; D[18]
D[1:0]; Stuff [7:0];
XCRC[5:0]
SPI_Get_Data_24b
SPI_Get_Data_32b
cmd[3:0]; ChID[2:0]; BID[2:0];
Stuff [5:0]
Stuff [15:0] Optional: SPI_SYNC_Pulse Stuff [15:0]
next cmd
Response to
response to previous cmd
cmd[3:0]; CHID[2:0]; BID[2:0] Fid[2:0]; D[25:10]
Err[1:0]; D[26]
D[9:0]; XCRC[5:0]
Stuff [15:0]
D[25:10]
SPI_Get_Data_32b
SPI_Get_Data_48b
cmd[3:0]; ChID[2:0]; BID[2:0];
Stuff [5:0]
Stuff [15:0] Optional: SPI_SYNC_Pulse Stuff [15:0]
next cmd
Response to
response to previous cmd
cmd[3:0]; CHID[2:0]; BID[2:0] Fid[2:0]; D[41:26]
Err[1:0]; D[42]
D[9:0]; XCRC[5:0]
SPI_Get_Data_48b
μ
C->transceiver
C->transceiver
SPI_SW_Reset
Response
cmd[3:0]; Stuff [11:0]
next cmd
μ
response to previous cmd
cmd[3:0]; Stuff [11:0]
BID = Buffer Identifier
CHID = Channel Identifier
ChTx = Channel Trigger for sync pulse (0=disabled; 1=enabled)
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ChLx = Sync pulse length (0=short; 1=long)
Note:
•
For 'Read Sensor Data xxbit' commands the SPI frame n+1 includes optional the 'SYNC Pulse command'
instead of NOP command to optimize the SPI bandwidth
The idle time between consecutive SPI frames has to fulfill parameter ton_NCS.
•
6.2.3.3 Overview of SPI commands
All valid SPI commands are shown in the table below.
Any other combinations (commands from micro controller) are rejected but flagged in register
ERROR_STATUS_1[UART_SPI_INV_CMD] for diagnosis purpose.
In case of reset or communication error the following response will be sent: 0x0000 in the following valid SPI frame.
Execution of command is blocked.
Chip select (NCS) low without any clock pulses at SCLK will be ignored. Next response to previous valid frame.
Table 6.2.3.3-1: Overview SPI commands
SPI command
SPI_Write_Register
command
bits[15:12]
remaining bits [11:0]
0000 0000 0000
0001
0010
0011
0100
0101
0111
1000
1110
1111
SPI_Read_Register
SPI_Sync_Pulse
SPI_Get_Data_16b
SPI_Get_Data_24b
SPI_Get_Data_32b
SPI_Get_Data_48b
SPI_NOP
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
SPI_SW_Reset
6.2.3.4 No Operation Command
Receiving a NOP command, the IC will perform no operation.
It shall be used to get the last frame of a SPI communication sequence.
The bit configuration of this one frame command is shown in the figure below:
MSB
SPI frame n
LSB
MSB
SPI frame n+1
LSB
idle
idle
1
1
1
0
x
0
x
0
0
0
0
0
x
0
0
x
0
x
0
x
0
x
0
idle
idle
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
idle
idle
SDI_RXD
SDO_TXD
SPI_NOP
Stuff
next cmd
x
x
x
x
x
x
x
x
x
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
SPI_NOP
Response to previous cmd
Stuff
Figure 6.2.3.4-1: SPI NOP Command
6.2.3.5 Write Configuration Register Command
With the command "Write Configuration Register" any 16bit register can be written.
Every command consists of three consecutive SPI frames, shown in the figure below.
As SPI frame n+2 on SDI_RXD are following cmds allowed: SPI_Write_Register, SPI_Read_Register,
SPI_SYNC_Pulse, SPI_NOP or a SPI_SW_Reset.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
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QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
MSB
SPI frame n
A2 A1
Address
LSB
MSB
SPI frame n+1
LSB
idle
idle
0
0
0
1
A5
x
A4
A3
A0 D15 D14 D13 D12 D11 D10 idle
D9
D8
0
D7
0
D6
1
D5
D4
A4
D3
D2
D1
D0
0
0
0
0
0
0
idle
SDI_RXD
SDO_TXD
SPI_Write_Register
Stuff
Data
Data
MSB
LSB
MSB
LSB
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
idle
idle
0
A5
A3 A2
Address
A1
A0 D15 D14 D13 D12 D11 D10 idle
Response to previous cmd
SPI_Write_Register
Data
MSB
SPI frame n+2
LSB
idle
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
SDI_RXD
SDO_TXD
next cmd
MSB
LSB
idle D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X5
X4
X3
X2
X1
X0 idle
XCRC
Data
Figure 6.2.3.5-1: SPI Write Register Command
6.2.3.6 Software Reset Command
With the first execution of the software reset command, all configuration registers are initialized to default values if
bit ASIC_CNFG_1[CNFG_LOCK]='0'.
If bit ASIC_CNFG_1[CNFG_LOCK]='1' all configuration registers are initialized to default values except register
ASIC_CNFG_1 and ASIC_CNFG_2.
With the second execution of the software reset command, the bit ASIC_CNFG_1[CNFG_LOCK] is reset to '0'.
The Software Reset Command includes one SPI Frame only:
MSB
SPI frame n
LSB
MSB
SPI frame n+1
LSB
idle
idle
1
1
1
1
x
0
x
0
0
0
0
0
0
0
x
0
x
0
x
0
x
0
idle
idle
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
idle
idle
SDI_RXD
SDO_TXD
SPI_SW_Reset
Stuff
next cmd
x
x
x
x
x
x
x
x
x
x
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
SPI_SW_Reset
Response to previous cmd
Stuff
Figure 6.2.3.6-1: SPI Software Reset Command
6.2.3.7 Read Configuration Register Command
With the command "Read Configuration Register" any 16bit register can be read.
Every command consists of three consecutive SPI frames.
MSB
SPI frame n
LSB
MSB
SPI frame n+1
LSB
idle
idle
0
0
1
0
A5
x
A4
A3
A2
A1
A0
0
0
x
0
0
0
x
0
idle
idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
idle
SDI_RXD
SDO_TXD
SPI_Read_Register
Address
Stuff
Stuff
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
1
0
A5
A4
A3
A2
A1
A0 D15 D14 D13 D12 D11 D10 idle
Data
Response to previous cmd
SPI_Read_Register
Address
MSB
SPI frame n+2
LSB
idle
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
idle
SDI_RXD
SDO_TXD
next cmd
idle D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X5
X4
X3
X2
X1
X0 idle
XCRC
Data
Figure 6.2.3.7-1: SPI Read Register Command
6.2.3.8 SYNC Pulse Command
Sync pulses with different widths can be triggered by sending the sync pulse command.
For configuration of the sync pulses there are the two bits ChTx and ChLx available.
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Data Sheet
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QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
Bit ChTx determines the generation of the sync pulse on the desired channel and ChLx determines the width of the
pulse, whereas a logical '0' leads to a short and a logical '1' leads to a long sync pulse.
The detailed bit setting is shown in the table below:
Table 6.2.3.8-1: SYNC Pulse Command
SPI command
SYNC Pulse
Command[15:12]
0011
SYNC trigger ChT[11:8]+SYNC length
ChLx[7:4]
Stuffing[3:0]
ChT3 & ChT2 & ChT1 & ChT0 & ChL3 & 0000
ChL2 & ChL1 & ChL0
Long Sync Pulse all Ch
Long Sync Pulse Ch1
Long Sync Pulse Ch2
Long Sync Pulse Ch3
Long Sync Pulse Ch4
Short Sync Pulse all Ch
Short Sync Pulse Ch1
Short Sync Pulse Ch2
Short Sync Pulse Ch3
Short Sync Pulse Ch4
0011
0011
0011
0011
0011
0011
0011
0011
0011
0011
11111111
00010001
00100010
01000100
10001000
11110000
00010000
00100000
01000000
10000000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
Example: e.g. '0011 1001 1001 0000' (MSB->LSB) defines two long SYNC pulses on channel 1 and channel 4.
Note: The application shall ensure to trigger the SYNC pulse generator only once during TSYNC by max. 1 "SYNC
Pulse command" per TSYNC. More trigger commands overwrite the former command (if SYNC pulse delay counter
has not exceeded) or trigger a new SYNC pulse.
MSB
SPI frame n
LSB
MSB
SPI frame n+1
LSB
idle
idle
0
0
1
1
x
x
x
x
x
x
x
x
0
x
0
0
0
idle
idle
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
idle
idle
SDI_RXD
SDO_TXD
ChT3 ChT2 ChT1 ChT0 ChL3 ChL2 ChL1 ChL0
Stuff
next cmd
SPI_SYNC_Pulse
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
1
1
x
x
x
x
x
x
x
x
0
0
0
0
ChT3 ChT2 ChT1 ChT0 ChL3 ChL2 ChL1 ChL0
Response to previous cmd
Stuff
SPI_SYNC_Pulse
Figure 6.2.3.8-1: SPI SYNC Pulse Command
6.2.3.9 Read Sensor Data
Sensor data is requested by executing the "Read Sensor Data" command. The number of SPI frames increases
with the number of requested sensor data bits.
For example, a request of 16 sensor data bits results in a communication with three SPI frames.
The SPI frame 2 has to be filled with stuffing bits or (optional) it can contain the "SYNC Pulse command" to optim-
ize the SPI bandwidth by "Read Sensor Data" command.
It's mandatory to read block wise via commands SPI_Get_Data_xxb according the appropriate buffer con-
figuration. This means for SPI_BUFFER_CONFIG="11" the command SPI_Get_Data_16b is mandatory (see
6.2.2.1.2).
For details of the bit position of PSI5 parity/CRC see 6.2.3.9.1.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
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Data Sheet
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QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
For synchronous PSI5 mode the "SPI_data_buffer" has to be synchronized with the PSI5 data.
It is recommended to read PSI5 data buffer after all PSI5 slots within the current cycle where received.
The SPI read access shall start later than "latest PSI5-slot end" + 3 · tGAP and shall end before "earliest
PSI5-slot end" of the next PSI5 slot.
latest end
SYNC
earliest end
3 · tGAP
PSI5 Bus
voltage
PSI5 Bus
current
slot 2
slot n
slot 1
slot 2
Read sensor data command shall not
start before latest end + 3 · tGAP
Read command shall end
before earliest end
Valid read sensor
data window
NCS
SDI
CMD:
read_sensor_data
slot 1
CMD:
read_sensor_data
slot n
SPI frame
SPI frame
SPI frame
SPI frame
Additional
sensor data
SDO
Previous
response
Previous
response
Response 1.1
Response 1.2
Response n.1
Response n.2
t
Figure 6.2.3.9-1: Valid read sensor data window 1
If data buffer has to be read interleaved within the PSI5 cycle the same constrains have to be considered.
The SPI read access shall start later than "latest PSI5-slot end" + 3 · tGAP and shall end before "earliest
PSI5-slot end" of the next PSI5 slot.
latest end
SYNC
SYNC
earliest end
3 · tGAP
PSI5 Bus
voltage
PSI5 Bus
current
slot 1
slot 2
slot n
Read sensor data command shall not
start before latest end + 3 · tGAP
Read command shall end
before earliest end
Valid read sensor
data window
NCS
SDI
CMD: read_sensor_data_16b
Previous CMD response
SPI frame
SPI frame
SDO
Response 1
Response 2
t
Figure 6.2.3.9-2: Valid read sensor data window 2
For asynchronous sensor mode it is not possible to access the data buffer synchronous to PSI5 data.
In this case it is recommended to use the UART mode.
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Data Sheet
46 / 89
QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
6.2.3.9.1 Read of 16bit (11bit sensor data)
Communication template for 16bit (= 3xFrameID + 2xErrBits + 11 DataBits) is shown in the figure above.
Note: Position of PSI5 parity/CRC bits in data frame is represented by highest 'used' data bit Dx of SPI buffer. See
following examples:
•
•
•
10 bit data + 1 parity bit -> D10 = parity bit
8 bit data + 1 parity bit -> D8 = parity bit
8 bit data + 3 crc bits -> D10=C0, D9=C1, D8=C2
optional to Stuff
MSB
SPI frame n
LSB
MS
LSB
idle
idle
0
1
0
0
x
x
x
x
x
x
0
0
x
0
0
0
x
0
id
idle
x
0
x
0
0
idle
SDI_RXD
SDO_TXD
CHID2 CHID1CHID0 BID2 BID1 BID0
0
Stuff
Stuff
SPI_Get_Data_16b
S
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
1
0
0
x
x
x
x
x
x
x
x
x
D10 idle
CHID2 CHID1CHID0 BID2 BID1 BID0 Fid2 Fid1 Fid0 Err1 Err0
Response to previous cmd
SPI_Get_Data_16b
Cmd Response (copy from read request)
SPI data buffer
MSB
SPI frame n+2
LSB
idle
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
idle
SDI_RXD
SDO_TXD
next cmd
idle D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X5
X4
X3
X2
X1
X0 idle
SPI data buffer
XCRC
Figure 6.2.3.9.1-1: SPI Read Sensor Data 16bit
MSB
LSB
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
SPI_Get_Data_16b;
cmd3
cmd2
cmd1
cmd0
ChId2
ChId1
ChId0
BID2
BID1
BID0
frame1; SDI_RXD
Command
Channel ID
Buffer ID
Stuff
Identifier Ch1
0
0
0
1
0
1
1
0
1
0
1
0
Identifier Ch2
Identifier Ch3
Identifier Ch4
Identifier Buffer0
Identifier Buffer1
Identifier Buffer2
Identifier Buffer3
Identifier Buffer4
Identifier Buffer5
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
Figure 6.2.3.9.1-2: SPI Read Sensor Data 16bit-request at SDI_RXD -1st SPI frame-
MSB
LSB
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
SPI_Get_Data_16b;
frame2; SDO_TXD
cmd3
cmd2
cmd1
cmd0
ChId2
ChId1
ChId0
BID2
BID1
BID0
Fid2
Fid1
Fid0
Err1
Err0
D0
Command
Channel ID
Buffer ID
Frame ID
Error bits
Data
Identifier Ch1
0
0
0
1
0
1
1
0
1
0
1
0
Identifier Ch2
Identifier Ch3
Identifier Ch4
Identifier Buffer0
Identifier Buffer1
Identifier Buffer2
Identifier Buffer3
Identifier Buffer4
Identifier Buffer5
Identifier Frame1
Identifier Frame2
Identifier Frame3
Identifier Frame4
Identifier Frame5
Identifier Frame6
Error bit - no error
Error bit - Interface error
Error bit - ASIC error
Error bit - Interf. + ASIC error
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
0
x
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
0
1
1
0
1
0
1
Figure 6.2.3.9.1-3: Response to SPI Read Sensor Data 16bit at SDO_TXD -2nd SPI frame-
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Data Sheet
47 / 89
QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
6.2.3.9.2 Read of 24bit (19bit sensor data)
Communication template for 24bit (= 3xFrameID + 2xErrBits + 19 DataBits):
optional to Stuff
MSB
SPI frame n
LSB
MSB
LSB
idle
idle
0
1
0
1
x
x
x
x
x
x
0
0
x
0
0
0
x
0
idle
idle
x
0
x
0
0
idle
SDI_RXD
SDO_TXD
CHID2CHID1CHID0 BID2 BID1 BID0
Stuff
Stuff
SPI_Get_Data_24b
SP
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
1
0
1
x
x
x
x
x
x
x
x
x
D18 idle
Data
CHID2 CHID1CHID0 BID2 BID1 BID0 Fid2 Fid1 Fid0 Err1 Err0
Cmd Response (copy from read request)
Response to previous cmd
SPI_Get_Data_24b
SPI data buffer
MSB
SPI frame n+2
LSB
MSB
SPI frame n+3
LSB
idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
idle
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
idle
SDI_RXD
SDO_TXD
Stuff
next cmd
idle D17 D16 D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2 idle D1
D0
0
0
0
0
0
0
0
0
X5
X4
X3
X2
X1
X0 idle
Stuff
XCRC
SPI data buffer
SPI data buffer
Figure 6.2.3.9.2-1: Read Sensor Data 24bit command
6.2.3.9.3 Read of 32bit (27bit sensor data)
Communication template for 32bit (= 3xFrameID + 2xErrBits + 27 DataBits):
optional to Stuff
MSB
SPI frame n
LSB
MSB
LSB
idle
idle
0
1
1
1
x
x
x
x
x
x
0
0
x
0
0
0
x
0
idle
idle
x
0
0
x
0
idle
SDI_RXD
CHID2CHID1CHID0 BID2 BID1 BID0
Stuff
Stuff
SPI_Get_Data_32b
SPI
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
1
1
1
x
x
x
x
x
x
x
x
x
D26 idle
Data
SDO_TXD
CHID2 CHID1CHID0 BID2 BID1 BID0 Fid2 Fid1 Fid0 Err1 Err0
Response to previous cmd
SPI_Get_Data_32b
Cmd Response (copy from read request)
SPI data buffer
MSB
SPI frame n+2
LSB
MSB
SPI frame n+3
LSB
idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
idle
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
idle
SDI_RXD
Stuff
next cmd
idle D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 idle
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X5
X4
X3
X2
X1
X0 idle
SDO_TXD
XCRC
SPI data buffer
SPI data buffer
Figure 6.2.3.9.3-1: Read Sensor Data 32bit command
6.2.3.9.4 Read of 48bit (43bit sensor data)
Position of PSI5 parity/CRC bits -> see 'Read Sensor Data 16bit'
Communication template for 48bit (= 3xFrameID + 2xErrBits + 43 DataBits):
Figure 6.2.3.9.4-1: Read Sensor Data 48bit command
Note: For bits 'don't care' in frame n+1 / n+2 on SDO_TXD there are two scenarios: all 12 bits are either '0' or '1';
for more details see chapter 6.2.2.1.2.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
48 / 89
QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
6.2.4 UART
The UART data rate is derived from an external clock signal fSCLK_UART with DCSCLK_UART at pin SCLK and is calculated
with the following formula fUART
=
.
The external clock has to be supplied permanent.
The bit shift direction supports "Little Endian" format with LSB sent first.
6.2.4.1 Error Handling
Read Register Command
Frame1:
ChID /Cmd
Frame2:
Address /Stuff
SDI_RXD
Invalid
address
Response to Read Register Command
Frame3:
D[7:0]= 0x00
Frame1:
ChID/ Fid/Err
Frame2:Copy
fromreadrequest
Frame4:
D[15:8]= 0x00
Frame5:
Stuff /XCRC
SDO_TXD
Modified data
Figure 6.2.4.1-1: UART Error Handling Example 1
see #3: Command 'UART_Read_Register' including invalid address A[5:0]:
The 'Response to Read Register Command' is uploaded with with data bits D[15:0] = 0x0000.
Read Register Command
Read Register Command
SDI_RXD
Frame1
Frame2
Frame1
Frame2
NO collision;
read reg .cmd decoded
after response finished
Response to Read Register Command
SDO_TXD
Frame4
Frame5
Frame1
Frame2
Frame1
Frame2
Frame3
Read Register Command
Read Register Command
SDI_RXD
Frame1
Frame2
Frame1
Frame2
collision;
read reg .cmd decoded
before responsefinished
Response to Read Register Command
Frame5
SDO_TXD
Frame1
Frame2
Frame3
Frame4
Figure 6.2.4.1-2: UART Error Handling Example 2
see #6: Collision of 'UART_Read_Register' commands:
While read register request command a collision with frames sent by the transceiver might occur.
In case of frames sent to the transceiver at pin RXD while the transceiver is transmitting data on pin TXD the RXD
frame is ignored. To ensure a response from E521.4x device to a "Read Register cmd", the SDO_TXD has to be
idle during decoding of "Read Register cmd". This is feasible if "Transfer of PSI5 data" is predictable.
For systems with asynchronous sensors it is recommended to use only one asynchronous sensor per chip. The
probability of a response to "Read Register cmd" increases with decreased payload on SDO_TXD. The probability
of a response to "Read Register cmd" increases with increased UART baud rate.
To decrease payload the UART idle time can be increased by Register ASIC_CNFG_2 / UART_IDLE_TIME[3:0]
set to maximum value.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
49 / 89
QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
If synchronous mode is used the UART idle time can be predicted.
Example for UART =4MBaud:
•
•
t1 = tnEE (earliest end of frame) = 142us
3 x staggering + 1 UART frame = 3*10us + 55bit*0.25us = 44us => idle time = t1 + t2 = 98us
t2
Figure 6.2.4.1-3: Syncpulse staggering
Table 6.2.4.1-1: UART Error Handling
1
invalid commands
command
ERROR_STATUS_1
[UART_SPI_INV_CMD]
Command rejected
Command rejected
2a
ERROR_STATUS_1
'UART_Write_Register' includ- [UART_SPI_INV_ADDRESS]
ing invalid address A[5:0]
2b
2c
3a
3b
command ERROR_STATUS_1
'UART_Write_Register' includ- [UART_SPI_INV_CMD]
Command rejected
Command rejected
Command rejected
Command rejected
ing ChId
0
command ERROR_STATUS_1
'UART_Write_Register' includ- [UART_SPI_INV_ADDRESS]
ing stuff
0
Command
ERROR_STATUS_1
'UART_Read_Register' includ- [UART_SPI_INV_ADDRESS]
ing invalid address A[5:0]
Command
'UART_Read_Register' includ- [UART_SPI_INV_CMD]
ing ChId
ERROR_STATUS_1
0
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PRODUCTION DATA – Apr 27, 2016
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3c
Command
'UART_Read_Register' includ- [UART_SPI_INV_ADDRESS]
ing stuff
ERROR_STATUS_1
Command rejected
0
4
5
6
Wrong parity bit received
ERROR_STATUS_1
[UART_PERR]
Command rejected
Command rejected
Frame error = invalid stop bit
ERROR_STATUS_1
[UART_FERR]
Collision of
'UART_Read_Register' com-
mands
ERROR_STATUS_1
[UART_SPI_COLLISION]
2nd Command rejected
e.g. read request received while
last read was not completed yet
7
Command 'Short SYNC pulse' ERROR_STATUS_1
including ChId >4 [UART_SPI_INV_CMD]
Command 'Long SYNC pulse' ERROR_STATUS_1
Command rejected
Command rejected
Command rejected
Command rejected
8
including ChId >4
[UART_SPI_INV_CMD]
9
Command 'No SYNC pulse'
0
ERROR_STATUS_1
[UART_SPI_INV_CMD]
including ChId
11
Command 'SW reset' including ERROR_STATUS_1
ChId [UART_SPI_INV_CMD]
0
6.2.4.2 Packet Frame Definition
A frame on the PSI5 interface is represented by a Packet Frame on the transmission line from the transceiver to
the Controller.
Also the commands on the transmission line from the Controller to the transceiver ASIC, as well as the responses,
are represented by a Packet Frame.
A Packet Frame can be a concatenation of 1 to 6 UART Frames.
For ASIC->uC: An idle time from 1 to 16 idle bits (configurable in register ASIC_CNFG_2) is implemented between
consecutive Packet Frames from the UART in order to enable a re-synchronization of the next Packet Frame. The
UART frame following an idle time which is equal or greater than the minimum idle time thus is always be assumed
as the header of the next Packet Frame (default configuration: one bit minimum idle time between two Packet
Frames).
For uC->ASIC: frames can be sent w/o idle time (back-to-back transfer possible)
6.2.4.3 UART Frame Definition
For transceiver to
optional parity bit and 1 stop bit.
For C to transceiver communication a UART frame (inside a packet frame) is composed of 1 start bit, 8 data bits, 1
μC communication a UART frame (inside a packet frame) is composed of 1 start bit, 8 data bits,
μ
parity bit and 1 stop bit.
Odd parity is enabled by default. For transceiver to μC communication the usage of a parity bit is configurable.
There is no idle time between UART frames inside a packet frame (i.e. a stop bit of a UART frame is followed by
the start bit of a potentially following UART frame without any gap).
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4 Channel Multi-Mode PSI5 Transceiver
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Data Transmission
Communication Path
UARTframe
Start (L)
D0
D1
D2
D3
D4
D5
D6
D7
P(odd) Stop (H) idle (H)
idle (H)
µC -> transceiver
LSB
MSB
t
UARTframe (config1)
Start (L)
D0
D1
D2
D3
D4
D5
D6
D7
Stop (H) idle (H)
idle (H)
LSB
MSB
transceiver -> µC
UARTframe (config2)
Start (L)
D0
D1
D2
D3
D4
D5
D6
D7
P(odd) Stop (H) idle (H)
idle (H)
LSB
MSB
t
Figure 6.2.4.3-1: UART Data Transmission
6.2.4.4 Overview of Communication Frames
The defined UART commands and responses, with number of UART frames per packet frame, are shown in the
table below.
•
•
Packet frames from
Packet frames from transceiver to
μ
C to transceiver means downstream
C means upstream
μ
Table 6.2.4.4-1: Overview of Communication Frames
Communication
Commands/Responses
UART Frame 1 [Packet-
UART Frame 2
UART Frame 3
[PacketFrame1]
UART Frame 4
[PacketFrame1]
UART Frame 5 [Pack-
etFrame1]
UART Frame 6
[PacketFrame1]
Path
Frame1]
[PacketFrame1]
μ
μ
μ
μ
μ
μ
C -> transceiver
C -> transceiver
C -> transceiver
C -> transceiver
C -> transceiver
C -> transceiver
UART_Write_Register
UART_Read_Register
UART_Short_SYNC_Pulse
UART_Long_SYNC Pulse
UART_No_SYNC_Pulse
UART_Software_Reset
Response to Read Register
Upload PSI5 data
cmd[4:0], ChId[2:0]
cmd[4:0], ChId[2:0]
cmd[4:0], ChId[2:0]
cmd[4:0], ChId[2:0]
cmd[4:0], ChId[2:0]
Stuff[1:0], A[5:0]
Stuff[1:0], A[5:0]
D[7:0]
D[15:8]
cmd[4:0], ChId[2:0]
Err[1:0], Fid[2:0], ChId[2:0]
Err[1:0], Fid[2:0], ChId[2:0]
transceiver ->
transceiver ->
μ
C
C
CmdRes[7:0]
D[7:0]
D[7:0]
D[15:8]
XCRC[5:0], Stuff[1:0]
μ
x*
x*
x*
x*
Note: x* = depending on definition of the corresponding PSI5 frame
6.2.4.5 Overview of UART Commands
All valid UART commands are shown in the table below. These commands have a hamming distance
other. Any other command from Controller is rejected but flagged in register
ERROR_STATUS_1[UART_SPI_INV_CMD] for diagnosis purpose.
≥2 to each
μ
Table 6.2.4.5-1: UART Command Table
UART Command
UART_Write_Register
UART_Read_Register
Command[7:3]
Channel ID[2:0]
00001
00010
000
000
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UART Command
Command[7:3]
00100
Channel ID[2:0]
UART_Short_Sync_Pulse all Ch
UART_Short_Sync_Pulse Ch1
UART_Short_Sync_Pulse Ch2
UART_Short_Sync_Pulse Ch3
UART_Short_Sync_Pulse Ch4
UART_Long_Sync_Pulse all Ch
UART_Long_Sync_Pulse Ch1
UART_Long_Sync_Pulse Ch2
UART_Long_Sync_Pulse Ch3
UART_Long_Sync_Pulse Ch4
UART_No_Sync_Pulse
000
001
010
011
100
000
001
010
011
100
000
000
00100
00100
00100
00100
00111
00111
00111
00111
00111
10011
10101
UART_Software_Reset
6.2.4.6 Write Register Command
The write register sequence includes 4 UART frames:
UART Frame 1: Command bits cmd[4:0]; Channel Identifier ChId[2:0]
UART Frame 2: Stuffing bits[1:0], Address bits A[5:0]
UART Frame 3: Data Low Byte D[7:0]
UART Frame 4: Data Low Byte D[15:8]
Table 6.2.4.6-1: Write Register Command
Write Register Command
Command [7:3]
Channel ID [2:0]
Write Register Command
00001
000
UART Frame 1
UART Frame 2
UART Frame 3
Parity Stp Srt D0 D1 D2 D3 D4 D5 D6 D7 Parity Stp
Srt
0
0
0
1
0
0
0
0
Parity Stp Srt A0 A1 A2 A3 A4 A5
0
0
C
h
Id
0
C
h
Id
1
C
h
Id
2
C
m
d
0
C
m
d
1
C
m
d
2
C
m
d
3
C m d 4
UART_Write_Register
Address
Data Lo-Byte
Stuff Stuff
UART Frame 4
Srt D8 D9 D10 D11 D12 D13 D14 D15 Parity Stp idle
Data Hi-Byte
Figure 6.2.4.6-1: Write Register Command Packet Frame
6.2.4.7 Read Register Command
The read register sequence includes 2 UART frames:
UART Frame 1: Command bits cmd[4:0]; Channel Identifier ChId[2:0]
UART Frame 2: Stuffing bits[1:0], Address bits A[5:0]
Table 6.2.4.7-1: Read Register Command
Read Register Command
Command [7:3]
Channel ID [2:0]
Read Register Command
00010
000
UART Frame 1
UART Frame 2
Parity Stp Srt A0 A1 A2 A3 A4 A5
Srt
0
0
0
0
1
0
0
0
0
0
Parity Stp idle
C
h
Id
0
C
h
Id
1
C
h
Id
2
C
m
d
0
C
m
d
1
C
m
d
2
C
m
d
3
C m d 4
UART_Read_Register
Address
Stuff Stuff
Figure 6.2.4.7-1: Read Register Command Packet Frame
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6.2.4.8 Short SYNC Pulse Command
The Short SYNC Pulse Command includes 1 UART Frame only:
UART Frame 1: Command bits cmd[4:0]; Channel Identifier ChId[2:0]
Following table shows the configuration of Channel IDs:
Table 6.2.4.8-1: Short SYNC Pulse Command
Short SYNC Pulse Command
Short Sync Pulse all Ch
Command [7:3]
00100
Channel ID [2:0]
000
001
010
011
100
Short Sync Pulse Ch1
00100
Short Sync Pulse Ch2
00100
Short Sync Pulse Ch3
00100
Short Sync Pulse Ch4
00100
UART Frame
Srt
x
x
x
0
0
1
0
0
Parity Stp idle
C
h
Id
0
C
h
Id
1
C
h
Id
2
C
m
d
0
C
m
d
1
C
m
d
2
C
m
d
3
C m d 4
UART_Short_SYNC_Pulse
Figure 6.2.4.8-1: Short SYNC Command Packet Frame
6.2.4.9 Long SYNC Pulse Command
The Long SYNC Pulse Command includes 1 UART frame only:
UART Frame 1: Command bits cmd[4:0]; Channel Identifier ChId[2:0]
Following table shows the configuration of Channel IDs:
Table 6.2.4.9-1: Long SYNC Pulse Command
Long SYNC Pulse Command
Long Sync Pulse all Ch
Command [7:3]
00111
Channel ID [2:0]
000
001
010
011
100
Long Sync Pulse Ch1
00111
Long Sync Pulse Ch2
00111
Long Sync Pulse Ch3
00111
Long Sync Pulse Ch4
00111
UART Frame
Srt
x
x
x
1
1
1
0
0
Parity Stp idle
C
h
Id
0
C
h
Id
1
C
h
Id
2
C
m
d
0
C
m
d
1
C
m
d
2
C
m
d
3
C m d 4
UART_Long_SYNC_Pulse
Figure 6.2.4.9-1: Long SYNC Command Packet Frame
6.2.4.10 No SYNC Pulse Command
For the tooth gap method, if a logical '0' (=absence of SYNC pulse) for ECU to sensor communication is required,
a no sync pulse command can be send by the Controller.
μ
The no sync pulse command includes 1 UART frame only.
UART Frame 1: Command bits cmd[4:0]; Channel Identifier ChId[2:0]
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Table 6.2.4.10-1: No SYNC Pulse Command
No SYNC Pulse Command
Command [7:3]
Channel ID [2:0]
000
No sync pulse
10011
UART Frame
Srt
0
0
0
1
1
0
0
1
Parity Stp idle
C
h
Id
0
C
h
Id
1
C
h
Id
2
C
m
d
0
C
m
d
1
C
m
d
2
C
m
d
3
C m d 4
UART_No_SYNC_Pulse
Figure 6.2.4.10-1: No SYNC Pulse Command Packet Frame
6.2.4.11 Software Reset Command
With the first execution of the software reset command, all configuration registers are initialized to default values if
bit ASIC_CNFG_1[CNFG_LOCK]='0'.
If bit ASIC_CNFG_1[CNFG_LOCK]='1' all configuration registers are initialized to default values except register
ASIC_CNFG_1 and ASIC_CNFG_2.
With the second execution of the software reset command, the bit ASIC_CNFG_1[CNFG_LOCK] is reset to '0'.
The Software Reset Command includes 1 UART frame only:
UART Frame 1: Command bits cmd[4:0]; Channel Identifier ChId[2:0]
Table 6.2.4.11-1: Software Reset Command
Software Reset Command
Command [7:3]
Channel ID [2:0]
Software Reset
10101
000
UART Frame
Srt
0
0
0
1
0
1
0
1
Parity Stp idle
C
h
Id
0
C
h
Id
1
C
h
Id
2
C
m
d
0
C
m
d
1
C
m
d
2
C
m
d
3
C m d 4
UART_SW_Reset
Figure 6.2.4.11-1: Software Reset Command Frame
6.2.4.12 Response to Read Register Command
Each valid read command, received by the transceiver ASIC, results in a response sequence including 5 UART
Frames.
UART Frame 1: Channel Identifier ChId[2:0]; Frame Identifier Fid[2:0]; Error bits Err[1:0]
UART Frame 2: Command response CmdRes[4:0]; Channel Identifier[2:0]= copy from UART frame 1 of read
request
UART Frame 3: Data Low Byte D[7:0]
UART Frame 4: Data Low Byte D[15:8]
UART Frame 5: Stuffing bits Stuff[1:0]; 6bit checksum XCRC[5:0]
Following table shows the bit configuration of UART Frame 1 including ChId, Fid and Err bits.
Table 6.2.4.12-1: Response To Read Command Bit Configuration
Response to Read Register: Configura-
tion of UART Frame 1
Error bits[7:6]
Frame ID[5:3]
Channel ID[2:0]
Error bit - no ASIC error
Error bit - interface error
Error bit - ASIC error
00
01
10
11
000
000
000
000
000
000
000
000
Error bit - ASIC and interface error
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UART Frame 1
UART Frame 2
UART Frame 3
Srt
0
0
0
0
0
0
0
Err1 Stp Srt
0
0
0
0
1
0
0
0
Stp Srt D0 D1 D2 D3 D4 D5 D6 D7 Stp
idle
C
h
Id 0
C
h
Id
1
C
h
Id
2
F
id
0
F
id
1
F
id
2
E
r r 0
C
h
Id
0
C
h
Id
1
C
h
Id
2
C
m
d
0
C
m
d
1
C
m
d
2
C
m
d
3
C m d 4
Packet Frame Header
Data Lo-Byte
Cmd Response (copy from read request)
UART Frame 4
UART Frame 5
Srt D8 D9 D10 D11 D12 D13 D14 D15 Stp Srt
Data Hi-Byte
0
0
X0 X1 X2 X3 X4 X5 Stp idle
XCRC
Stuff Stuff
Figure 6.2.4.12-1: Response to Read Register Command Packet Frame
6.2.4.13 Transfer PSI5 Data
Incoming PSI5 data frames are processed and transmitted to the μController in UART frames.
The sequence includes 3 - 6 UART frames, depending on the length of the corresponding PSI5 frame.
Example: Frame configuration for minimum packet frame (according to v1.3):
UART Frame 1: Channel Identifier ChId[2:0]; Frame Identifier Fid[2:0]; Error bits Err[1:0]
UART Frame 2: Data bits D[7:0]
UART Frame 3: Parity; Stuffing bit Stuff; 6bit checksum XCRC[5:0]
UART Frame 1
UART Frame 2
UART Frame 3
X0 X1 X2 X3 X4 X5 Stp idle
Srt ChId0 ChId1 ChId2 Fid0 Fid1 Fid2 Err0 Err1 Stp Srt D0 D1 D2 D3 D4 D5 D6 D7 Stp Srt Parity
0
idle
Packet Frame Header
PSI5 Message
Stuff
XCRC
Figure 6.2.4.13-1: Example: Upload PSI5 Data Minimum Packet Frame
Example: Frame configuration for maximum Packet Frame (according to v2.0):
UART Frame 1: Channel Identifier ChId[2:0]; Frame Identifier Fid[2:0]; Error bits Err[1:0]
UART Frame 2: Data bits D[7:0]
UART Frame 3: Data bits D[15:8]
UART Frame 4: Data bits D[23:16]
UART Frame 5: Data bits D[27:24]; 3bit checksum C[2:0]; Stuffing bit Stuff
UART Frame 6: Stuffing bits Stuff[1:0]; 6bit checksum XCRC[5:0]
UART Frame 1
UART Frame 2
UART Frame 3
Srt ChId0 ChId1 ChId2 Fid0 Fid1 Fid2 Err0 Err1 Stp Srt D0 D1 D2 D3 D4 D5 D6 D7 Stp Srt D8 D9 D10 D11 D12 D13 D14 D15 Stp
idle
Packet Frame Header
UART Frame 4
PSI5 Message
UART Frame 5
PSI5 Message
UART Frame 6
Srt D16 D17 D18 D19 D20 D21 D22 D23 Stp Srt D24 D25 D26 D27 C2 C1 C0
0
Stp Srt
0
0
X0 X1 X2 X3 X4 X5 Stp idle
PSI5 Message
PSI5 Message
XCRC
Stuff
Stuff Stuff
Figure 6.2.4.13-2: Example: Upload PSI5 Data Maximum Packet Frame
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Following table shows the bit configuration of UART Frame 1 including ChId, Fid and Err bits.
Table 6.2.4.13-1: PSI5 Data UART Frame1 Bit Configuration
PSI5 data: Configuration of UART Frame 1
Identifier for channel0 (diagnosis)
Identifier for channel1
Error bits
xx
Frame ID
xxx
Channel ID
000
001
010
011
100
xxx
xxx
xxx
xxx
xxx
xxx
xxx
xxx
xxx
xxx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
00
01
10
11
xxx
xxx
xxx
xxx
000
001
010
011
100
101
xxx
xxx
xxx
xxx
Identifier for channel2
Identifier for channel3
Identifier for channel4
Identifier for frame1
Identifier for frame2
Identifier for frame3
Identifier for frame4
Identifier for frame5
Identifier for frame6
Error bit - no error
Error bit - Interface error
Error bit - ASIC error
Error bit - Interface + ASIC error
6.2.5 XCRC[5:0] Calculation
A 6-bit XCRC for error detection is calculated and added at the last UART/SPI frame, transferred from transceiver
to C at pin SDO_TXD, for the defined packet frames.
The generator polynomial of the six bit CRC is g(x) = + 1 with a binary CRC initialization value "010101".
μ
+
+
The transmitter extends the data bits by six zeros (= XCRC default condition) as shown in the figures above. This
augmented data word is fed (LSB first) into the shift registers of the CRC generator.
C0
T
C1
T
C2
T
C3
T
C4
T
C5
T
Input data
1*1
+
0*X
+
0*X2
+
1*X3
+
1*X4
+
0*X5
+
1*X6
= 1 + X3 + X4 + X6
Figure 6.2.5-1: XCRC-calculation for SPI frames
UART Packet Frames:
The sequence of bit shift into the register for the CRC calculation is shown in below, starting with LSB first. The
number of stuffing bits varies with the payload (not shown in the figures below).
1. Transfer PSI5 Data
LSB
x
MSB
x x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
0
x
x
x
x
D0 D1 D2 …… Dn-2 Dn-1 C2 C1 C0
….
X0
X5
Channel ID
Frame ID
Error bits
PSI5 frame data P/CRC
Stuffing
XCRC; default = zeros
Figure 6.2.5-2: XCRC: Example Transfer PSI5 Data
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2. Response to Read Register Command
LSB
MSB
0
0
0
0
0
0
0
x
0
0
Channel ID
0
0
1
0
Cmd
0
0
x
x
x
x
x
x
0
0
x
x
x
x
x
x
D0 D1 D2 …… D14 D15
register data
X0
X5
Channel ID
Frame ID
Error bits
Stuffing
XCRC; default = zeros
Cmd Response (copy from read request)
Figure 6.2.5-3: XCRC: Example Response to Read Command
SPI Packet Frames:
The sequence is done in the similar way than for UART Packet frames, except
•
•
Starting with MSB first
Changed payload (e.g. additional Buffer ID, SYNC_LONG bits)
Example Read Sensor Data 24bit:
LSB
MSB
x x
0
0
0
0
0
0
0
x
0
0
0
Channel ID
0
1
0
Cmd
0
0
x
x
x
x
x
x
0
0
x
x
x
x
D0 D1 D2 …… D14 D15
register data
X0
X5
Channel ID
Frame ID
Error bits
Stuffing
XCRC; default = zeros
Cmd Response (copy from read request)
Figure 6.2.5-4: XCRC Example Read Sensor Data 24bit
6.2.6 CONFIGURATION
6.2.6.1 ASIC Configuration
The device can be configured and maintained with configuration, diagnosis and error registers.
Every register contains 16 bits, so only 16 bit read/write requests are processed.
Any of the four device channels can be configured independently by writing the read/write (R/W) configuration
registers ASIC_CNFG_1, ASIC_CNFG_2 and ASIC_CNFG_3.
The following parameters can be modified per channel:
•
•
•
•
•
current threshold for the data comparator (ΔIs_CHx)
sync sustain voltage V3 (VSYNC_V3_CHx)
channel configuration of synchronous / asynchronous mode (ASYNC_CHx)
PSI5 bit time [kbps] / Baud rate per channel (PSI5_BIT_TIME_CHx)
enabling of interfaces SIF_CHx (EN_CHx)
The detailed settings are described in the register table below:
Table 6.2.6.1-1: ASIC CONFIGURATION
Register Name
ASIC_CNFG_1
ASIC_CNFG_2
ASIC_CNFG_3
Address
0x00
Description
ASIC Configuration Register 1
ASIC Configuration Register 2
ASIC Configuration Register 3
0x01
0x02
Reading of unused bits will always return '0' and writing of unused bits don't care. Writing of read-only- or read-on
clear-registers, don't care. For SPI accesses the response via SDO_TXD is the echo of the write request (identic-
ally behaviour than for write on read/write-registers).
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4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
Table 6.2.6.1-2: Register ASIC_CNFG_1 (0x00) ASIC Configuration Register 1
MSB
LSB
Content
CNFG -
_LOC
K
-
-
MCD_DATA_ VSYN VSYN VSYN VSYN
CMP_W[1:0] C_V3 C_V3 C_V3 C_V3 H4
_CH4 _CH3 _CH2 _CH1
Δ
IS_C
Δ
IS_C
Δ
IS_C
Δ
IS_C V_BUS[1:0]
H3
H2
H1
Reset value
Access
0
0
0
0
00
0
0
0
0
0
0
0
0
00
R/W
R
R
R
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
CNFG_LOCK : lock bit for configuration registers
0b0: registers ASIC_CNFG_1 and ASIC_CNFG_2 are not locked, an update is possible
0b1: registers ASIC_CNFG_1 and ASIC_CNFG_2 are locked, no update possible (exception: The 2nd SW_reset com-
mand resets the lock and allows this two registers to be updated)
MCD_DATA_CMP_W[1:0] : Manchester data compare window setting
0b00: DATA_EDGE = 18 clock counts (low sensitive) & COMPENSATION_WINDOW = 23 clock counts
@4MHz: DATA_E=(18*250ns = 4.5us; CMP=23*250ns=5.75us; => Total=10.25us
@6MHz: DATA_E=18*167ns = 3us; CMP=23*167ns=3.83us; => Total = 6.83us
0b01: DATA_EDGE = 12 clock counts (low sensitive) & COMPENSATION_WINDOW = 26 clock counts
@4MHz: DATA_E=12*250ns = 3us; CMP=26*250ns=6.5us; => Total=9.5us
@6MHz: DATA_E=12*167ns = 2us; CMP=26*167ns=4.33us; => Total = 6.33us
0b10: DATA_EDGE = 8 clock counts (low sensitive) & COMPENSATION_WINDOW = 28 clock counts
@4MHz: DATA_E=8*250ns = 2us; CMP=28*250ns=7us; => Total=9us
@6MHz: DATA_E=8*167ns = 1.33us; CMP=28*167ns=4.67us; => Total = 6us
VSYNC_V3_CH4 : sync sustain voltage V3 (VSYNC_V3_CHx)
0b0: V3 = 4.8V typical (common mode)
0b1: V3 = 3.7V typical (low power mode)
VSYNC_V3_CH3 : sync sustain voltage V3 (VSYNC_V3_CHx)
0b0: V3 = 4.8V typical (common mode)
0b1: V3 = 3.7V typical (low power mode)
VSYNC_V3_CH2 : sync sustain voltage V3 (VSYNC_V3_CHx)
0b0: V3 = 4.8V typical (common mode)
0b1: V3 = 3.7V typical (low power mode)
VSYNC_V3_CH1 : sync sustain voltage V3 (VSYNC_V3_CHx)
0b0: V3 = 4.8V typical (common mode)
0b1: V3 = 3.7V typical (low power mode)
∆IS_CH4 : current threshold for the data comparator (
Δ
Δ
Δ
Δ
Is_CHx)
Is_CHx)
Is_CHx)
Is_CHx)
0b0:
0b1:
Δ
IS = 26mA
IS = 13mA
Δ
∆IS_CH3 : current threshold for the data comparator (
0b0:
0b1:
Δ
IS = 26mA
IS = 13mA
Δ
∆IS_CH2 : current threshold for the data comparator (
0b0:
0b1:
Δ
IS = 26mA
IS = 13mA
Δ
∆IS_CH1 : current threshold for the data comparator (
0b0:
0b1:
Δ
IS = 26mA
IS = 13mA
Δ
V_BUS[1:0] : VBUS selection
0b00: LDO disabled; VBUS must be supplied externaly
0b01: VBUS = 5.15V
0b10: VBUS = 6.65V
0b11: VBUS = 7.7V
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
59 / 89
QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
Table 6.2.6.1-3: Register ASIC_CNFG_2 (0x01) ASIC Configuration Register 2
MSB
LSB
Content
-
-
UART_IDLE_TIME[3:0]
REV_ IDAC_ PSI5_ PSI5_ PSI5_ PSI5_ ASYN ASYN ASYN ASYN
CUR_ RES BIT_TI BIT_TI BIT_TI BIT_TI C_CH C_CH C_CH C_CH
CH_DI
S
ME_C ME_C ME_C ME_C 4
H2
3
2
1
H4
H3
H1
Reset value
Access
0
0
0000
R/W
0
0
0
0
0
0
0
0
0
0
R
R
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
UART_IDLE_TIME[3:0] : UART idle time between two consecutive UART packet frames (to enable a re-synchronization)
0b0000: minimum idle time = DEFAULT
0b1111: maximum idle time
REV_CUR_CH_DIS : Disable of channels for reverse current condition
0b0: disabled -> no switch-off of channels by IC (default)
0b1: enabled -> switch-off dedicated channel if REV_CUR_CHx='1'
IDAC_RES : IDAC resolution
0b0: 300 uA per LSB (default)
0b1: 200 uA per LSB
PSI5_BIT_TIME_CH4 : PSI5 bit time
0b0: bit time equal to 8us (=125kbps)
0b1: bit time equal to 5.3us (=189kbps)
PSI5_BIT_TIME_CH3 : PSI5 bit time
0b0: bit time equal to 8us (=125kbps)
0b1: bit time equal to 5.3us (=189kbps)
PSI5_BIT_TIME_CH2 : PSI5 bit time
0b0: bit time equal to 8us (=125kbps)
0b1: bit time equal to 5.3us (=189kbps)
PSI5_BIT_TIME_CH1 : PSI5 bit time
0b0: bit time equal to 8us (=125kbps)
0b1: bit time equal to 5.3us (=189kbps)
ASYNC_CH4 : channel mode configuration
0b0: channel in synchronous configuration
0b1: channel in asynchronous configuration
ASYNC_CH3 : channel mode configuration
0b0: channel in synchronous configuration
0b1: channel in asynchronous configuration
ASYNC_CH2 : channel mode configuration
0b0: channel in synchronous configuration
0b1: channel in asynchronous configuration
ASYNC_CH1 : channel mode configuration
0b0: channel in synchronous configuration
0b1: channel in asynchronous configuration
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
60 / 89
QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
Table 6.2.6.1-4: Register ASIC_CNFG_3 (0x02) ASIC Configuration Register 3
MSB
LSB
Content
-
BL_C BL_C BL_C BL_C GEN_ EN_LOOP[2:0]
HAN- HAN- HAN- HAN- FUSE
NEL4 NEL3 NEL2 NEL1 _RD
EN_C EN_U EN_U EN_C EN_C EN_C EN_C
H2
NC
P_SY ART_ ART_ H4
TXD_ RXD_
PAR- PAR-
H3
H1
ITY
ITY
Reset value
Access
0
0
0
0
0
0
000
0
1
0
0
0
0
0
R
R
R
R
R
R/W R/W
R/W R/W R/W R/W R/W R/W R/W
Bit Description
BL_CHANNEL4 : blanking time of MCD/SYNC generation/ovc after channel enable
0=5ms
1=10ms
BL_CHANNEL3 : blanking time of MCD/SYNC generation/ovc after channel enable
0=5ms
1=10ms
BL_CHANNEL2 : blanking time of MCD/SYNC generation/ovc after channel enable
0=5ms
1=10ms
BL_CHANNEL1 : blanking time of MCD/SYNC generation/ovc after channel enable
0=5ms
1=10ms
GEN_FUSE_RD : Start fuse read out via UART/SPI
0b0: no fuse read out
0b1: start additional fuse read out
EN_LOOP[2:0] : enable channel in loop back test mode
0b000: all Channel in normal operation
0b001: Channel1 loop back test mode enabled
0b010: Channel2 loop back test mode enabled
0b011: Channel3 loop back test mode enabled
0b100: Channel4 loop back test mode enabled
EN_CP_SYNC : Enable Sync pulse charge pump
0b0:disabled
0b1:enabled
EN_UART_TXD_PARITY : Enable parity bit addition for UART Tx frames
0b0:disabled
0b1:enabled
EN_UART_RXD_PARITY : Enable parity check for UART received frames
0b0:disabled
0b1:enabled
EN_CH4 : Enable Interface SIFx
0b0: Disable PSI5 Interface
0b1: Enable PSI5 Interface
EN_CH3 : Enable Interface SIFx
0b0: Disable PSI5 Interface
0b1: Enable PSI5 Interface
EN_CH2 : Enable Interface SIFx
0b0: Disable PSI5 Interface
0b1: Enable PSI5 Interface
EN_CH1 : Enable Interface SIFx
0b0: Disable PSI5 Interface
0b1: Enable PSI5 Interface
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
61 / 89
QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
6.2.6.1.1 Asynchronous mode
Note: Only one sensor allowed per SIFx.
With enable of SIFx via configuration register ASIC_CNFG_3[EN_CHx], the sensor is supplied with voltage VSIFx
and starts to transmit PSI5 sensor frames.
For received frames, the implemented Manchester decoder adds to each valid frame the Fid ="0b001".
For UART interface, the Packet frame is transferred to uC automatically. With appropriate UART baud rate, the IC
transmits the data to the uC without any overwriting.
For SPI interface, the decoded frame is available in BID[0] of SPI data buffer. The uC has to ensure to read BID[0]
before a new PSI5 frame is decoded; otherwise it's overwritten.
6.2.6.2 Timeslot Configuration
For every channel there are seven configuration registers available to configure the following parameters:
•
•
•
•
•
•
•
six independent configurable PSI5 timeslots
timeslot length
frame length
parity or crc selection
error check enabling
desired delay of sync pulse generation
mandatory buffer for SPI access Details are described in the following register table.
Table 6.2.6.2-1: CHANNEL_CONFIGURATION
Register Name
CH1_CFG1
CH1_CFG2
CH1_CFG3
CH1_CFG4
CH1_CFG5
CH1_CFG6
CH1_CFG7
CH2_CFG1
CH2_CFG2
CH2_CFG3
CH2_CFG4
CH2_CFG5
CH2_CFG6
CH2_CFG7
CH3_CFG1
CH3_CFG2
CH3_CFG3
CH3_CFG4
CH3_CFG5
CH3_CFG6
CH3_CFG7
Address
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
Description
Channel 1 Configuration Register 1
Channel 1 Configuration Register 2
Channel 1 Configuration Register 3
Channel 1 Configuration Register 4
Channel 1 Configuration Register 5
Channel 1 Configuration Register 6
Channel 1 Configuration Register 7
Channel 2 Configuration Register 1
Channel 2 Configuration Register 2
Channel 2 Configuration Register 3
Channel 2 Configuration Register 4
Channel 2 Configuration Register 5
Channel 2 Configuration Register 6
Channel 2 Configuration Register 7
Channel 3 Configuration Register 1
Channel 3 Configuration Register 2
Channel 3 Configuration Register 3
Channel 3 Configuration Register 4
Channel 3 Configuration Register 5
Channel 3 Configuration Register 6
Channel 3 Configuration Register 7
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Data Sheet
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QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
Register Name
CH4_CFG1
CH4_CFG2
CH4_CFG3
CH4_CFG4
CH4_CFG5
CH4_CFG6
CH4_CFG7
Address
0x18
Description
Channel 4 Configuration Register 1
0x19
Channel 4 Configuration Register 2
Channel 4 Configuration Register 3
Channel 4 Configuration Register 4
Channel 4 Configuration Register 5
Channel 4 Configuration Register 6
Channel 4 Configuration Register 7
0x1A
0x1B
0x1C
0x1D
0x1E
It is highly recommended, not to change the registers CHX_CFG1(IDAC_CNT_MODE, IDAC_CNT_INC2[1:0],
IDAC_CNT_INC1[1:0]) and CHX_CFG2(IDAC_CNT_DEC2[1:0], IDAC_CNT_DEC1[1:0]) since these registers
control the Ibase tracking function!
Table 6.2.6.2-2: Register CH1_CFG1 (0x03) Channel 1 Configuration Register 1
MSB
LSB
Content
IDAC_ IDAC_CNT_I IDAC_CNT_I EN_E T1_C TS1_FLEN[4:0]
R_CH RC
K
T1_LEN[3:0]
CNT_ NC2[1:0]
MODE
NC1[1:0]
Reset value
Access
0
00
00
0
0
00011
0100
R/W
R/W R/W
R/W
R/W R/W R/W
Bit Description
IDAC_CNT_MODE : reserved
IDAC_CNT_INC2[1:0] : reserved
IDAC_CNT_INC1[1:0] : reserved
EN_ER_CHK : Enable parity/CRC check functionality
0b0: disable functionality
0b1: enable functionality
T1_CRC : PSI5 frame error detection mode of frames starting in timeslot 1
0b0: PSI5 Sensor in parity mode
0b1: PSI5 Sensor in CRC mode
TS1_FLEN[4:0] : PSI5 frame length of frames starting in timeslot 1
frame length includes start bit + data + parity/crc
[TSx_FLEN]16 = [Frame length]10 - [10]10
0x0 = bit length of zero (=no frame)
0x01 - 0x17: Frame length => [11..33] 0x18 - 0x1F: reserved
Default: P10P (Airbag) = 2 + 10 + 1 = 13->0x3
T1_LEN[3:0] : Timeslot 1 Length
0b_nnnn: nnnn x 32 us => [0us..480us]
Default: t = 4*32us = 128us
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Data Sheet
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QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
Table 6.2.6.2-3: Register CH1_CFG2 (0x04) Channel 1 Configuration Register 2
MSB
LSB
Content
-
IDAC_CNT_D IDAC_CNT_D EN_E T2_C TS2_FLEN[4:0]
R_CH RC
K
T2_LEN[3:0]
EC2[1:0]
EC1[1:0]
Reset value
Access
0
01
01
0
0
00011
0101
R/W
R/W R/W
R/W
R/W R/W R/W
Bit Description
IDAC_CNT_DEC2[1:0] : reserved
IDAC_CNT_DEC1[1:0] : reserved
EN_ER_CHK : Enable parity/CRC check functionality
0b0: disable functionality
0b1: enable functionality
T2_CRC : PSI5 frame error detection mode of frames starting in timeslot 2
0b0: PSI5 Sensor in parity mode
0b1: PSI5 Sensor in CRC mode
TS2_FLEN[4:0] : PSI5 frame length of frames starting in timeslot 2
frame length includes start bit + data + parity/crc
[TSx_FLEN]16 = [Frame length]10 - [10]10
0x0 = bit length of zero (=no frame)
0x01 - 0x17: Frame length => [11..33] 0x18-0x1F:reserved Default: P10P (Airbag) = 2 + 10 + 1 = 13->0x3
T2_LEN[3:0] : Timeslot 2 Length
0b_nnnn: nnnn x 32 us => [0us..480us]
Default: t = 5*32us = 160us
Table 6.2.6.2-4: Register CH1_CFG3 (0x05) Channel 1 Configuration Register 3
MSB
LSB
Content
-
-
-
-
-
EN_E T3_C TS3_FLEN[4:0]
R_CH RC
K
T3_LEN[3:0]
Reset value
Access
0
0
0
0
0
0
0
00011
0101
R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
EN_ER_CHK : Enable parity/CRC check functionality
0b0: disable functionality
0b1: enable functionality
T3_CRC : PSI5 frame error detection mode of frames starting in timeslot 3
0b0: PSI5 Sensor in parity mode
0b1: PSI5 Sensor in CRC mode
TS3_FLEN[4:0] : PSI5 frame length of frames starting in timeslot 3
frame length includes start bit + data + parity/crc
[TSx_FLEN]16 = [Frame length]10 - [10]10
0x0 = bit length of zero (=no frame)
0x01 - 0x17: Frame length => [11..33]
0x18 - 0x1F: reserved
Default: P10P (Airbag) = 2 + 10 + 1 = 13->0x3
T3_LEN[3:0] : Timeslot 3 Length
0b_nnnn: nnnn x 32 us => [0us..480us]
Default: t = 5*32us = 160us
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
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Data Sheet
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QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
Table 6.2.6.2-5: Register CH1_CFG4 (0x06) Channel 1 Configuration Register 4
MSB
LSB
Content
-
-
-
-
-
EN_E T4_C TS4_FLEN[4:0]
R_CH RC
K
T4_LEN[3:0]
Reset value
Access
0
0
0
0
0
0
0
00000
0000
R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
EN_ER_CHK : Enable parity/CRC check functionality
0b0: disable functionality
0b1: enable functionality
T4_CRC : PSI5 frame error detection mode of frames starting in timeslot 4
0b0: PSI5 Sensor in parity mode
0b1: PSI5 Sensor in CRC mode
TS4_FLEN[4:0] : PSI5 frame length of frames starting in timeslot 4
frame length includes start bit + data + parity/crc
[TSx_FLEN]16 = [Frame length]10 - [10]10
0x0 = bit length of zero (=no frame)
0x01 - 0x17: Frame length => [11..33]
0x18-0x1F:reserved Default: = 0
T4_LEN[3:0] : Timeslot 4 Length
0b_nnnn: nnnn x 32 us => [0us..480us]
Default: t = 0*32us = 0us
Table 6.2.6.2-6: Register CH1_CFG5 (0x07) Channel 1 Configuration Register 5
MSB
LSB
Content
-
-
-
-
-
EN_E T5_C TS5_FLEN[4:0]
R_CH RC
K
T5_LEN[3:0]
Reset value
Access
0
0
0
0
0
0
0
00000
0000
R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
EN_ER_CHK : Enable parity/CRC check functionality
0b0: disable functionality
0b1: enable functionality
T5_CRC : PSI5 frame error detection mode of frames starting in timeslot 5
0b0: PSI5 Sensor in parity mode
0b1: PSI5 Sensor in CRC mode
TS5_FLEN[4:0] : PSI5 frame length of frames starting in timeslot 5
frame length includes start bit + data + parity/crc
[TSx_FLEN]16 = [Frame length]10 - [10]10
0x0 = bit length of zero (=no frame)
0x01 - 0x17: Frame length => [11..33]
0x18 - 0x1F: reserved
Default: = 0
T5_LEN[3:0] : Timeslot 5 Length
0b_nnnn: nnnn x 32 us => [0us..480us]
Default: t = 0*32us = 0us
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
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Data Sheet
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QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
Table 6.2.6.2-7: Register CH1_CFG6 (0x08) Channel 1 Configuration Register 6
MSB
LSB
Content
-
-
-
-
-
EN_E T6_C TS6_FLEN[4:0]
R_CH RC
K
T6_LEN[3:0]
Reset value
Access
0
0
0
0
0
0
0
00000
0000
R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
EN_ER_CHK : Enable parity/CRC check functionality
0b0: disable functionality
0b1: enable functionality
T6_CRC : PSI5 frame error detection mode of frames starting in timeslot 6
0b0: PSI5 Sensor in parity mode
0b1: PSI5 Sensor in CRC mode
TS6_FLEN[4:0] : PSI5 frame length of frames starting in timeslot 6
frame length includes start bit + data + parity/crc
[TSx_FLEN]16 = [Frame length]10 - [10]10
0x0 = bit length of zero (=no frame)
0x01 - 0x17: Frame length => [11..33]
0x18-0x1F:reserved Default:= 0
T6_LEN[3:0] : Timeslot 6 Length
0b_nnnn: nnnn x 32 us => [0us..480us]
Default: t = 0*32us = 0us
Table 6.2.6.2-8: Register CH1_CFG7 (0x09) Channel 1 Configuration Register 7
MSB
LSB
Content
-
-
-
-
SPI_BUF-
FER_CNFG[1
:0]
SYNC_DLY[9:0]
Reset value
Access
0
0
0
0
11
0000
R/W
R/W R/W R/W R/W R/W
Bit Description
SPI_BUFFER_CNFG[1:0] : SPI buffer (=96bit) configuration
0b00: 48bit/buffer;2 partial buffers; Buffer identifiers[0,1]
0b01: 32bit/buffer;3 partial buffers; Buffer identifiers[0,1,2]
0b10: 24bit/buffer;4 partial buffers; Buffer identifiers[0,1,2,3]
0b11: 16bit/buffer;6 partial buffers; Buffer identifiers[0,1,2,3,4,5](=default)
SYNC_DLY[9:0] : Sync pulse delay
0xnnn: nnn x 8/fCLK_INT =>[0us..682us]
Table 6.2.6.2-9: Register CH2_CFG1 (0x0A) Channel 2 Configuration Register 1
MSB
LSB
Content
IDAC_ IDAC_CNT_I IDAC_CNT_I EN_E T1_C TS1_FLEN[4:0]
R_CH RC
K
T1_LEN[3:0]
CNT_ NC2[1:0]
MODE
NC1[1:0]
Reset value
Access
0
00
00
0
0
00011
0100
R/W
R/W R/W
R/W
R/W R/W R/W
Bit Description
IDAC_CNT_MODE : reserved
IDAC_CNT_INC2[1:0] : reserved
IDAC_CNT_INC1[1:0] : reserved
EN_ER_CHK : see CH1_CFG1
T1_CRC : see CH1_CFG1
TS1_FLEN[4:0] : see CH1_CFG1
T1_LEN[3:0] : see CH1_CFG1
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
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QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
Table 6.2.6.2-10: Register CH2_CFG2 (0x0B) Channel 2 Configuration Register 2
MSB
LSB
Content
-
IDAC_CNT_D IDAC_CNT_D EN_E T2_C TS2_FLEN[4:0]
R_CH RC
K
T2_LEN[3:0]
EC2[1:0]
EC1[1:0]
Reset value
Access
0
01
01
0
0
00011
0101
R/W
R/W R/W
R/W
R/W R/W R/W
Bit Description
IDAC_CNT_DEC2[1:0] : reserved
IDAC_CNT_DEC1[1:0] : reseved
EN_ER_CHK : see CH1_CFG2
T2_CRC : see CH1_CFG2
TS2_FLEN[4:0] : see CH1_CFG2
T2_LEN[3:0] : see CH1_CFG2
Table 6.2.6.2-11: Register CH2_CFG3 (0x0C) Channel 2 Configuration Register 3
MSB
LSB
Content
-
-
-
-
-
EN_E T3_C TS3_FLEN[4:0]
R_CH RC
K
T3_LEN[3:0]
Reset value
Access
0
0
0
0
0
0
0
00011
0101
R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
EN_ER_CHK : see CH1_CFG3
T3_CRC : see CH1_CFG3
TS3_FLEN[4:0] : see CH1_CFG3
T3_LEN[3:0] : see CH1_CFG3
Table 6.2.6.2-12: Register CH2_CFG4 (0x0D) Channel 2 Configuration Register 4
MSB
LSB
Content
-
-
-
-
-
EN_E T4_C TS4_FLEN[4:0]
R_CH RC
K
T4_LEN[3:0]
Reset value
Access
0
0
0
0
0
0
0
00000
0000
R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
EN_ER_CHK : see CH1_CFG4
T4_CRC : see CH1_CFG4
TS4_FLEN[4:0] : see CH1_CFG4
T4_LEN[3:0] : see CH1_CFG4
Table 6.2.6.2-13: Register CH2_CFG5 (0x0E) Channel 2 Configuration Register 5
MSB
LSB
Content
-
-
-
-
-
EN_E T5_C TS5_FLEN[4:0]
R_CH RC
K
T5_LEN[3:0]
Reset value
Access
0
0
0
0
0
0
0
00000
0000
R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
EN_ER_CHK : see CH1_CFG5
T5_CRC : see CH1_CFG5
TS5_FLEN[4:0] : see CH1_CFG5
T5_LEN[3:0] : see CH1_CFG5
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Data Sheet
67 / 89
QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
Table 6.2.6.2-14: Register CH2_CFG6 (0x0F) Channel 2 Configuration Register 6
MSB
LSB
Content
-
-
-
-
-
EN_E T6_C TS6_FLEN[4:0]
R_CH RC
K
T6_LEN[3:0]
Reset value
Access
0
0
0
0
0
0
0
00000
0000
R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
EN_ER_CHK : see CH1_CFG6
T6_CRC : see CH1_CFG6
TS6_FLEN[4:0] : see CH1_CFG6
T6_LEN[3:0] : see CH1_CFG6
Table 6.2.6.2-15: Register CH2_CFG7 (0x10) Channel 2 Configuration Register 7
MSB
LSB
Content
-
-
-
-
SPI_BUF-
FER_CNFG[1
:0]
SYNC_DLY[9:0]
Reset value
Access
0
0
0
0
11
0000
R/W
R/W R/W R/W R/W R/W
Bit Description
SPI_BUFFER_CNFG[1:0] : see CH1_CFG7
SYNC_DLY[9:0] : see CH1_CFG7
Table 6.2.6.2-16: Register CH3_CFG1 (0x11) Channel 3 Configuration Register 1
MSB
LSB
Content
IDAC_ IDAC_CNT_I IDAC_CNT_I EN_E T1_C TS1_FLEN[4:0]
R_CH RC
K
T1_LEN[3:0]
CNT_ NC2[1:0]
MODE
NC1[1:0]
Reset value
Access
0
00
00
0
0
00011
0100
R/W
R/W R/W
R/W
R/W R/W R/W
Bit Description
IDAC_CNT_MODE : reserved
IDAC_CNT_INC2[1:0] : reserved
IDAC_CNT_INC1[1:0] : reserved
EN_ER_CHK : see CH1_CFG1
T1_CRC : see CH1_CFG1
TS1_FLEN[4:0] : see CH1_CFG1
T1_LEN[3:0] : see CH1_CFG1
Table 6.2.6.2-17: Register CH3_CFG2 (0x12) Channel 3 Configuration Register 2
MSB
LSB
Content
-
IDAC_CNT_D IDAC_CNT_D EN_E T2_C TS2_FLEN[4:0]
R_CH RC
K
T2_LEN[3:0]
EC2[1:0]
EC1[1:0]
Reset value
Access
0
01
01
0
0
00011
0101
R/W
R/W R/W
R/W
R/W R/W R/W
Bit Description
IDAC_CNT_DEC2[1:0] : reserved
IDAC_CNT_DEC1[1:0] : reserved
EN_ER_CHK : see CH1_CFG2
T2_CRC : see CH1_CFG2
TS2_FLEN[4:0] : see CH1_CFG2
T2_LEN[3:0] : see CH1_CFG2
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Data Sheet
68 / 89
QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
Table 6.2.6.2-18: Register CH3_CFG3 (0x13) Channel 3 Configuration Register 3
MSB
LSB
Content
-
-
-
-
-
EN_E T3_C TS3_FLEN[4:0]
R_CH RC
K
T3_LEN[3:0]
Reset value
Access
0
0
0
0
0
0
0
00011
0101
R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
EN_ER_CHK : see CH1_CFG3
T3_CRC : see CH1_CFG3
TS3_FLEN[4:0] : see CH1_CFG3
T3_LEN[3:0] : see CH1_CFG3
Table 6.2.6.2-19: Register CH3_CFG4 (0x14) Channel 3 Configuration Register 4
MSB
LSB
LSB
LSB
Content
-
-
-
-
-
EN_E T4_C TS4_FLEN[4:0]
R_CH RC
K
T4_LEN[3:0]
Reset value
Access
0
0
0
0
0
0
0
00000
0000
R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
EN_ER_CHK : see CH1_CFG4
T4_CRC : see CH1_CFG4
TS4_FLEN[4:0] : see CH1_CFG4
T4_LEN[3:0] : see CH1_CFG4
Table 6.2.6.2-20: Register CH3_CFG5 (0x15) Channel 3 Configuration Register 5
MSB
Content
-
-
-
-
-
EN_E T5_C TS5_FLEN[4:0]
R_CH RC
K
T5_LEN[3:0]
Reset value
Access
0
0
0
0
0
0
0
00000
0000
R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
EN_ER_CHK : see CH1_CFG5
T5_CRC : see CH1_CFG5
TS5_FLEN[4:0] : see CH1_CFG5
T5_LEN[3:0] : see CH1_CFG5
Table 6.2.6.2-21: Register CH3_CFG6 (0x16) Channel 3 Configuration Register 6
MSB
Content
-
-
-
-
-
EN_E T6_C TS6_FLEN[4:0]
R_CH RC
K
T6_LEN[3:0]
Reset value
Access
0
0
0
0
0
0
0
00000
0000
R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
EN_ER_CHK : see CH1_CFG6
T6_CRC : see CH1_CFG6
TS6_FLEN[4:0] : see CH1_CFG6
T6_LEN[3:0] : see CH1_CFG6
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Data Sheet
69 / 89
QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
Table 6.2.6.2-22: Register CH3_CFG7 (0x17) Channel 3 Configuration Register 7
MSB
LSB
Content
-
-
-
-
SPI_BUF-
FER_CNFG[1
:0]
SYNC_DLY[9:0]
Reset value
Access
0
0
0
0
11
0000
R/W
R/W R/W R/W R/W R/W
Bit Description
SPI_BUFFER_CNFG[1:0] : see CH3_CFG7
SYNC_DLY[9:0] : see CH3_CFG7
Table 6.2.6.2-23: Register CH4_CFG1 (0x18) Channel 4 Configuration Register 1
MSB
LSB
LSB
LSB
Content
IDAC_ IDAC_CNT_I IDAC_CNT_I EN_E T1_C TS1_FLEN[4:0]
R_CH RC
K
T1_LEN[3:0]
CNT_ NC2[1:0]
MODE
NC1[1:0]
Reset value
Access
0
00
00
0
0
00011
0100
R/W
R/W R/W
R/W
R/W R/W R/W
Bit Description
IDAC_CNT_MODE : reserved
IDAC_CNT_INC2[1:0] : reserved
IDAC_CNT_INC1[1:0] : reserved
EN_ER_CHK : see CH1_CFG1
T1_CRC : see CH1_CFG1
TS1_FLEN[4:0] : see CH1_CFG1
T1_LEN[3:0] : see CH1_CFG1
Table 6.2.6.2-24: Register CH4_CFG2 (0x19) Channel 4 Configuration Register 2
MSB
Content
-
IDAC_CNT_D IDAC_CNT_D EN_E T2_C TS2_FLEN[4:0]
R_CH RC
K
T2_LEN[3:0]
EC2[1:0]
EC1[1:0]
Reset value
Access
0
01
01
0
0
00011
0101
R/W
R/W R/W
R/W
R/W R/W R/W
Bit Description
IDAC_CNT_DEC2[1:0] : reserved
IDAC_CNT_DEC1[1:0] : reserved
EN_ER_CHK : see CH1_CFG2
T2_CRC : see CH1_CFG2
TS2_FLEN[4:0] : see CH1_CFG2
T2_LEN[3:0] : see CH1_CFG2
Table 6.2.6.2-25: Register CH4_CFG3 (0x1A) Channel 4 Configuration Register 3
MSB
Content
-
-
-
-
-
EN_E T3_C TS3_FLEN[4:0]
R_CH RC
K
T3_LEN[3:0]
Reset value
Access
0
0
0
0
0
0
0
00011
0101
R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
EN_ER_CHK : see CH1_CFG3
T3_CRC : see CH1_CFG3
TS3_FLEN[4:0] : see CH1_CFG3
T3_LEN[3:0] : see CH1_CFG3
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Data Sheet
70 / 89
QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
Table 6.2.6.2-26: Register CH4_CFG4 (0x1B) Channel 4 Configuration Register 4
MSB
LSB
Content
-
-
-
-
-
EN_E T4_C TS4_FLEN[4:0]
R_CH RC
K
T4_LEN[3:0]
Reset value
Access
0
0
0
0
0
0
0
00000
0000
R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
EN_ER_CHK : see CH1_CFG4
T4_CRC : see CH1_CFG4
TS4_FLEN[4:0] : see CH1_CFG4
T4_LEN[3:0] : see CH1_CGF4
Table 6.2.6.2-27: Register CH4_CFG5 (0x1C) Channel 4 Configuration Register 5
MSB
LSB
LSB
LSB
Content
-
-
-
-
-
EN_E T5_C TS5_FLEN[4:0]
R_CH RC
K
T5_LEN[3:0]
Reset value
Access
0
0
0
0
0
0
0
00000
0000
R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
EN_ER_CHK : see CH1_CFG5
T5_CRC : see CH1_CFG5
TS5_FLEN[4:0] : see CH1_CFG5
T5_LEN[3:0] : see CH1_CFG5
Table 6.2.6.2-28: Register CH4_CFG6 (0x1D) Channel 4 Configuration Register 6
MSB
Content
-
-
-
-
-
EN_E T6_C TS6_FLEN[4:0]
R_CH RC
K
T6_LEN[3:0]
Reset value
Access
0
0
0
0
0
0
0
00000
0000
R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description
EN_ER_CHK : see CH1_CFG6
T6_CRC : see CH1_CFG6
TS6_FLEN[4:0] : see CH1_CFG6
T6_LEN[3:0] : see CH1_CFG6
Table 6.2.6.2-29: Register CH4_CFG7 (0x1E) Channel 4 Configuration Register 7
MSB
Content
-
-
-
-
SPI_BUF-
FER_CNFG[1
:0]
SYNC_DLY[9:0]
Reset value
Access
0
0
0
0
11
0000
R/W
R/W R/W R/W R/W R/W
Bit Description
SPI_BUFFER_CNFG[1:0] : see CH1_CGF7
SYNC_DLY[9:0] : see CH1_CGF7
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Data Sheet
71 / 89
QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
6.2.6.2.1 Timeslot Length
The timeslotx length (Bit TX_LEN) is used to assign the frame identifier (Fid) to received PSI5 frames.
Tx_LEN is implemented as a counter. Once loaded, it's counting down to 0.
T1_LEN is loaded with start of SYNC pulse (after SYNC_DLY has expired). If T1_LEN has expired, the following
counter T2_LEN is loaded ... until T6_LEN has expired.
For TSX_LEN=0x00(=no frame) the TX_LEN counter is also loaded with 0 and expires with the next 2μs clock
cycle.
The timeslot length (bit TX_LEN) is used to assign the frame identifier (fid) to decoded PSI5 frames. Following two
examples based on PSI5-P10P-500/3L (Airbag), show the correlation of Fid to TX_LEN counter. The Fid is added
to the PSI5 sensor data by the Manchester decoder (MD) once the first start bit (rising slope) is detected.
Example 1, default configuration; T3_LEN expires within frame3.
Figure 6.2.6.2.1-1: Example1: TxLEN Configuration
Example 2 default configuration;T3_LEN expires after frame3;MD_UNEX_FR_CHX_FX is possible:
Note that unexpected frame errors MD_UNEX_FR_CHx_F[4...6] are flagged if 2 valid start bits
are decoded with 2nd start bit occures in T[4...6]_LEN (error condition, either frame too late, unexpected frame or
TX_LEN configured wrong).
Figure 6.2.6.2.1-2: Example2: TxLEN Configuration
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Data Sheet
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QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
For active Tx_LEN counter any SYNC pulse trigger is masked to prevent an abort of Tx_LEN counter. This allows a
faster ECU-2-sensor communication w/o change of register configuration.
The time slot ends with the last edge of the Data protocol.
Note: Decoded Manchester data will be discarded for a SYNC pulse trigger during active Tx_LEN counter to avoid
storage / upload of corrupted data to uC. Error will be flagged in ERROR_STATUS_x[SYNC_DATA_INV_CH1].
With next regular SYNC trigger - after Tx_LEN counter is again in idle state - sensor data is stored / uploaded to
uC.
unexp.
SYNC
t0
SYNC
frame1
frame2
NOResetof FID dueto
unexpectedSYNCpulse
Fid
0b011
idle
0b000
0b001
0b010
Clear onread
Flag
SYNC_DATA_INV_CHx = '1'
Extention possible
until MDC in idle
state
'1' -> discard decoded MCD data
Target: no storage / upload of data to µC with wrong FID
Figure 6.2.6.2.1-3: Example2: TxLEN Configuration: Unexptected Sync Pulse
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Data Sheet
73 / 89
QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
6.2.6.3 Error Registers
There are ten error status registers available for reading, which are cleared on read (clear on read, RC).
The following error information is available:
•
•
•
•
•
•
•
•
•
MD Unexpected frame for each frame and channel
MD No frames for each frame and channel
MD Frame error for each frame and channel
MD Parity error for each frame and channel
Reverse current status of each channel
Buffer configuration error of each channel
Diagnosis status of each channel
Over current status of each channel
UART/SPI status information (invalid address, invalid command, SPI clock erreor, UART read request collision)
Details are described in the following register table.
Table 6.2.6.3-1: Error Status Register
Register Name
ERROR_STATUS_1
ERROR_STATUS_2
ERROR_STATUS_3
ERROR_STATUS_4
ERROR_STATUS_5
ERROR_STATUS_6
ERROR_STATUS_7
ERROR_STATUS_8
ERROR_STATUS_9
ERROR_STATUS_10
Address
Description
0x25
Global ASIC errors
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
Channel errors
Four error bits per frame (1-4) channel 1
Four error bits per frame (5-6) channel 1 and analog errors
Four error bits per frame (1-4)channel 2
Four error bits per frame (5-6)channel 2 and analog errors
Four error bits per frame (1-4)channel 3
Four error bits per frame (5-6)channel 3 and analog errors
Four error bits per frame (1-4)channel 4
Four error bits per frame (5-6)channel 4 and analog errors
Reading of unused bits will always return '0' and writing of unused bits don't care. Writing to read only or read on
clear registers don't care. The SPI echo response to a write request is independently of register type (R/W, R, RC).
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Data Sheet
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QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
Table 6.2.6.3-2: Register ERROR_STATUS_1 (0x25) Global ASIC errors
MSB
LSB
Content
-
-
-
-
-
-
-
-
UART VBUS DIAG_ SPI_C UART UART UART UART
LK_E _SPI_ _SPI_I _FER _PER
_SPI_I _OV OT
NV_A
DDRE
SS
RR
COL- NV_C R
MD
R
LI-
SION
Reset value
Access
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/C
R/C
R/C1 R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
Bit Description
UART_SPI_INV_ADDRESS : UART/SPI address check
0b0: valid address
0b1: invalid address
VBUS_OV : VBUS over voltage bit
0b0: no over voltage; signal vbus_ov_f = 0
0b1: over voltage; signal vbus_ov_f = 1
DIAG_OT : Overtemperatur bit
0b0: no overtemperature; signal i_ot = 0
0b1: overtemperature; signal i_ot = 1
SPI_CLK_ERR : SPI clock error
0b0: no clock error
0b1: SPI clock error (number of clock cycles
16)
UART_SPI_COLLISION : UART/SPI read request collision status latch (clear on read)
0b0: no collision happend
0b1: UART/SPI read request received while last read was not completed yet
UART_SPI_INV_CMD : UART/SPI command error status latch (clear on read)
0b0: no command error
0b1: invalid command
UART_FERR : UART frame error status latch (clear on read)
0b0: no frame error seen
0b1: frame error detected
UART_PERR : UART parity error status latch (clear on read)
0b0: no parity error seen
0b1: parity error detected
Table 6.2.6.3-3: Register ERROR_STATUS_2 (0x26) Channel errors
MSB
LSB
Content
-
-
-
-
-
-
-
-
-
-
-
-
CH_E CH_E CH_E CH_E
RR_4 RR_3 RR_2 RR_1
Reset value
Access
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
Bit Description
CH_ERR_4 : Channel 4 error status (overall)
0b000: all bits of ERROR_STATUS_3 + ERROR_STATUS_4 are equal to '0' (= OR combination of these bits)
0b001: number of bits with '1' of ERROR_STATUS_3 + ERROR_STATUS_4 is higher or equal to 1 (= OR combination of
these bits)
CH_ERR_3 : Channel 3 error status (overall)
0b000: all bits of ERROR_STATUS_7 + ERROR_STATUS_8 are equal to '0' (= OR combination of these bits)
0b001: number of bits with '1' of ERROR_STATUS_7 + ERROR_STATUS_8 is higher or equal to 1 (= OR combination of
these bits)
CH_ERR_2 : Channel 2 error status (overall)
0b000: all bits of ERROR_STATUS_5 + ERROR_STATUS_6 are equal to '0' (= OR combination of these bits)
0b001: number of bits with '1' of ERROR_STATUS_5 + ERROR_STATUS_6 is higher or equal to 1 (= OR combination of
these bits)
CH_ERR_1 : Channel 1 error status (overall)
0b000: all bits of ERROR_STATUS_3 + ERROR_STATUS_4 are equal to '0' (= OR combination of these bits)
0b001: number of bits with '1' of ERROR_STATUS_3 + ERROR_STATUS_4 is higher or equal to 1 (= OR combination of
these bits)
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
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Data Sheet
75 / 89
QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
Table 6.2.6.3-4: Register ERROR_STATUS_3 (0x27) Four error bits per frame (1-4) channel 1
MSB
LSB
Content
MD_U MD_N MD_F MD_P MD_U MD_N MD_F MD_P MD_U MD_N MD_F MD_P MD_U MD_N MD_F MD_P
NEX_ O_FR ERR_ ERR_ NEX_ O_FR ERR_ ERR_ NEX_ O_FR ERR_ ERR_ NEX_ O_FR ERR_ ERR_
FR_C _CH1 FR_C FR_C FR_C _CH1 FR_C FR_C FR_C _CH1 FR_C FR_C FR_C _CH1 FR_C FR_C
H1_F4 _F4
H1_F4 H1_F4 H1_F3 _F3
H1_F3 H1_F3 H1_F2 _F2
H1_F2 H1_F2 H1_F1 _F1
H1_F1 H1_F1
Reset value
Access
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
Bit Description
MD_UNEX_FR_CH1_F4 : Manchester Decoder unexpected frame received
0b0: no unexpected frame received
0b1: unexpected frame received
MD_NO_FR_CH1_F4 : Manchester Decoder no frame received (clear on read)
0b0: frame received (in expected time slot)
0b1: no frame received (in expected time slot)
MD_FERR_FR_CH1_F4 : Manchester Decoder frame error status latch (clear on read)
0b0: no frame error seen
0b1: frame error detected
MD_PERR_FR_CH1_F4 : Manchester Decoder Parity/CRC error status latch (clear on read)
0b0: no parity/CRC error seen
0b1: parity/CRC error detected
MD_UNEX_FR_CH1_F3 : see MD_UNEX_FR_CH1_F4
MD_NO_FR_CH1_F3 : see MD_NO_FR_CH1_F4
MD_FERR_FR_CH1_F3 : see MD_FERR_FR_CH1_F4
MD_PERR_FR_CH1_F3 : see MD_PERR_FR_CH1_F4
MD_UNEX_FR_CH1_F2 : see MD_UNEX_FR_CH1_F4
MD_NO_FR_CH1_F2 : see MD_NO_FR_CH1_F4
MD_FERR_FR_CH1_F2 : see MD_FERR_FR_CH1_F4
MD_PERR_FR_CH1_F2 : see MD_PERR_FR_CH1_F4
MD_UNEX_FR_CH1_F1 : see MD_UNEX_FR_CH1_F4
MD_NO_FR_CH1_F1 : see MD_NO_FR_CH1_F4
MD_FERR_FR_CH1_F1 : see MD_FERR_FR_CH1_F4
MD_PERR_FR_CH1_F1 : see MD_PERR_FR_CH1_F4
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
76 / 89
QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
Table 6.2.6.3-5: Register ERROR_STATUS_4 (0x28) Four error bits per frame (5-6) channel 1 and analog errors
MSB
LSB
Content
-
-
SYNC REV_ BUFF OC_C DIAG_CH1[1: MD_U MD_N MD_F MD_P MD_U MD_N MD_F MD_P
NEX_ O_FR ERR_ ERR_ NEX_ O_FR ERR_ ERR_
FR_C _CH1 FR_C FR_C FR_C _CH1 FR_C FR_C
_DAT CUR_ _ERR H1
CH1 _CH1
0]
A_
INV_C
H1
H1_F6 _F6
H1_F6 H1_F6 H1_F5 _F5
H1_F5 H1_F5
Reset value
Access
0
0
0
0
0
0
00
0
0
0
0
0
0
0
0
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
Bit Description
SYNC_DATA_ INV_CH1 : Reverse current status of channel 1
0b0: no SYNC pulse trigger during active Tx_LEN counter
0b1: SYNC pulse trigger during active Tx_LEN counter occurred
REV_CUR_CH1 : Reverse current status of channel 1
0b0: no reverse current detected
0b1: reverse current detected
BUFF_ERR_CH1 : Data buffer (96bit) configuration error
0b0: no configuration error
0b1: configuration error
OC_CH1 : Channel 1 over current status
0b0: no over current
0b1: over current
DIAG_CH1[1:0] : Channel 1 diagnosis status code (clear on read)
0b00: no error
0b01 leakage to GND
0b10: leakage to VBAT (soft short) / open load
MD_UNEX_FR_CH1_F6 : see MD_UNEX_FR_CH1_F4
MD_NO_FR_CH1_F6 : see MD_NO_FR_CH1_F4
MD_FERR_FR_CH1_F6 : see MD_FERR_FR_CH1_F4
MD_PERR_FR_CH1_F6 : see MD_PERR_FR_CH1_F4
MD_UNEX_FR_CH1_F5 : see MD_UNEX_FR_CH1_F4
MD_NO_FR_CH1_F5 : see MD_NO_FR_CH1_F4
MD_FERR_FR_CH1_F5 : see MD_FERR_FR_CH1_F4
MD_PERR_FR_CH1_F5 : see MD_PERR_FR_CH1_F4
Table 6.2.6.3-6: Register ERROR_STATUS_5 (0x29) Four error bits per frame (1-4)channel 2
MSB
LSB
Content
MD_U MD_N MD_F MD_P MD_U MD_N MD_F MD_P MD_U MD_N MD_F MD_P MD_U MD_N MD_F MD_P
NEX_ O_FR ERR_ ERR_ NEX_ O_FR ERR_ ERR_ NEX_ O_FR ERR_ ERR_ NEX_ O_FR ERR_ ERR_
FR_C _CH2 FR_C FR_C FR_C _CH2 FR_C FR_C FR_C _CH2 FR_C FR_C FR_C _CH2 FR_C FR_C
H2_F4 _F4
H2_F4 H2_F4 H2_F3 _F3
H2_F3 H2_F3 H2_F2 _F2
H2_F2 H2_F2 H2_F1 _F1
H2_F1 H2_F1
Reset value
Access
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
Bit Description
MD_UNEX_FR_CH2_F4 : see MD_UNEX_FR_CH1_F4
MD_NO_FR_CH2_F4 : see MD_NO_FR_CH1_F4
MD_FERR_FR_CH2_F4 : see MD_FERR_FR_CH1_F4
MD_PERR_FR_CH2_F4 : see MD_PERR_FR_CH1_F4
MD_UNEX_FR_CH2_F3 : see MD_UNEX_FR_CH1_F4
MD_NO_FR_CH2_F3 : see MD_NO_FR_CH1_F4
MD_FERR_FR_CH2_F3 : see MD_FERR_FR_CH1_F4
MD_PERR_FR_CH2_F3 : see MD_PERR_FR_CH1_F4
MD_UNEX_FR_CH2_F2 : see MD_UNEX_FR_CH1_F4
MD_NO_FR_CH2_F2 : see MD_NO_FR_CH1_F4
MD_FERR_FR_CH2_F2 : see MD_FERR_FR_CH1_F4
MD_PERR_FR_CH2_F2 : see MD_PERR_FR_CH1_F4
MD_UNEX_FR_CH2_F1 : see MD_UNEX_FR_CH1_F4
MD_NO_FR_CH2_F1 : see MD_NO_FR_CH1_F4
MD_FERR_FR_CH2_F1 : see MD_FERR_FR_CH1_F4
MD_PERR_FR_CH2_F1 : see MD_PERR_FR_CH1_F4
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
77 / 89
QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
Table 6.2.6.3-7: Register ERROR_STATUS_6 (0x2A) Four error bits per frame (5-6)channel 2 and analog errors
MSB
LSB
Content
-
-
SYNC REV_ BUF- OC_C DIAG_CH2[1: MD_U MD_N MD_F MD_P MD_U MD_N MD_F MD_P
NEX_ O_FR ERR_ ERR_ NEX_ O_FR ERR_ ERR_
FR_C _CH2 FR_C FR_C FR_C _CH2 FR_C FR_C
_DAT CUR_ FER_ H2
CH2 ERR_
CH2
0]
A_
INV_C
H2
H2_F6 _F6
H2_F6 H2_F5 H2_F5 _F5
H2_F5 H2_F5
Reset value
Access
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
Bit Description
SYNC_DATA_ INV_CH2 : Reverse current status of channel 2
0b0: no SYNC pulse trigger during active Tx_LEN counter
0b1: SYNC pulse trigger during active Tx_LEN counter occurred
REV_CUR_CH2 : Reverse current status of channel 2
0b0: no reverse current detected
0b1: reverse current detected
BUFFER_ERR_CH2 : Data buffer (96bit) configuration error
0b0: no configuration error
0b1: configuration error
OC_CH2 : Channel 2 over current status
0b0: no over current
0b1: over current
DIAG_CH2[1:0] : Channel 1 diagnosis status code (clear on read)
0b00: no error
0b01 leakage to GND
0b10: leakage to VBAT (soft short) / open load
MD_UNEX_FR_CH2_F6 : see MD_UNEX_FR_CH1_F4
MD_NO_FR_CH2_F6 : see MD_NO_FR_CH1_F4
MD_FERR_FR_CH2_F6 : see MD_FERR_FR_CH1_F4
MD_PERR_FR_CH2_F5 : see MD_PERR_FR_CH1_F4
MD_UNEX_FR_CH2_F5 : see MD_UNEX_FR_CH1_F4
MD_NO_FR_CH2_F5 : see MD_NO_FR_CH1_F4
MD_FERR_FR_CH2_F5 : see MD_FERR_FR_CH1_F4
MD_PERR_FR_CH2_F5 : see MD_PERR_FR_CH1_F4
Table 6.2.6.3-8: Register ERROR_STATUS_7 (0x2B) Four error bits per frame (1-4)channel 3
MSB
LSB
Content
MD_U MD_N MD_F MD_P MD_U MD_N MD_F MD_P MD_U MD_N MD_F MD_P MD_U MD_N MD_F MD_P
NEX_ O_FR ERR_ ERR_ NEX_ O_FR ERR_ ERR_ NEX_ O_FR ERR_ ERR_ NEX_ O_FR ERR_ ERR_
FR_C _CH3 FR_C FR_C FR_C _CH3 FR_C FR_C FR_C _CH3 FR_C FR_C FR_C _CH3 FR_C FR_C
H3_F4 _F4
H3_F4 H3_F4 H3_F3 _F3
H3_F3 H3_F3 H3_F2 _F2
H3_F2 H3_F2 H3_F1 _F1
H3_F1 H3_F1
Reset value
Access
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
Bit Description
MD_UNEX_FR_CH3_F4 : see MD_UNEX_FR_CH1_F4
MD_NO_FR_CH3_F4 : see MD_NO_FR_CH1_F4
MD_FERR_FR_CH3_F4 : see MD_FERR_FR_CH1_F4
MD_PERR_FR_CH3_F4 : see MD_PERR_FR_CH1_F4
MD_UNEX_FR_CH3_F3 : see MD_UNEX_FR_CH1_F4
MD_NO_FR_CH3_F3 : see MD_NO_FR_CH1_F4
MD_FERR_FR_CH3_F3 : see MD_FERR_FR_CH1_F4
MD_PERR_FR_CH3_F3 : see MD_PERR_FR_CH1_F4
MD_UNEX_FR_CH3_F2 : see MD_UNEX_FR_CH1_F4
MD_NO_FR_CH3_F2 : see MD_NO_FR_CH1_F4
MD_FERR_FR_CH3_F2 : see MD_FERR_FR_CH1_F4
MD_PERR_FR_CH3_F2 : see MD_PERR_FR_CH1_F4
MD_UNEX_FR_CH3_F1 : see MD_UNEX_FR_CH1_F4
MD_NO_FR_CH3_F1 : see MD_NO_FR_CH1_F4
MD_FERR_FR_CH3_F1 : see MD_FERR_FR_CH1_F4
MD_PERR_FR_CH3_F1 : see MD_PERR_FR_CH1_F4
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
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Data Sheet
78 / 89
QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
Table 6.2.6.3-9: Register ERROR_STATUS_8 (0x2C) Four error bits per frame (5-6)channel 3 and analog errors
MSB
LSB
Content
-
-
SYNC REV_ BUFF OC_C DIAG_CH3[1: MD_U MD_N MD_F MD_P MD_U MD_N MD_F MD_P
NEX_ O_FR ERR_ ERR_ NEX_ O_FR ERR_ ERR_
FR_C _CH3 FR_C FR_C FR_C _CH3 FR_C FR_C
_DAT CUR_ _ERR H3
CH3 _CH3
0]
A_
INV_C
H3
H3_F6 _F6
H3_F6 H3_F6 H3_F5 _F5
H3_F5 H3_F5
Reset value
Access
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
Bit Description
SYNC_DATA_ INV_CH3 : Reverse current status of channel 3
0b0: no SYNC pulse trigger during active Tx_LEN counter
0b1: SYNC pulse trigger during active Tx_LEN counter occurred
REV_CUR_CH3 : Reverse current status of channel 3
0b0: no reverse current detected
0b1: reverse current detected
BUFF_ERR_CH3 : Data buffer (96bit) configuration error
0b0: no configuration error
0b1: configuration error
OC_CH3 : Channel 3 over current status
0b0: no over current
0b1: over current
DIAG_CH3[1:0] : Channel 3 diagnosis status code (clear on read)
0b00: no error
0b01 leakage to GND
0b10: leakage to VBAT (soft short) / open load
MD_UNEX_FR_CH3_F6 : see MD_UNEX_FR_CH1_F4
MD_NO_FR_CH3_F6 : see MD_NO_FR_CH1_F4
MD_FERR_FR_CH3_F6 : see MD_FERR_FR_CH1_F4
MD_PERR_FR_CH3_F6 : see MD_PERR_FR_CH1_F4
MD_UNEX_FR_CH3_F5 : see MD_UNEX_FR_CH1_F4
MD_NO_FR_CH3_F5 : see MD_NO_FR_CH1_F4
MD_FERR_FR_CH3_F5 : see MD_FERR_FR_CH1_F4
MD_PERR_FR_CH3_F5 : see MD_PERR_FR_CH1_F4
Table 6.2.6.3-10: Register ERROR_STATUS_9 (0x2D) Four error bits per frame (1-4)channel 4
MSB
LSB
Content
MD_U MD_N MD_F MD_P MD_U MD_N MD_F MD_P MD_U MD_N MD_F MD_P MD_U MD_N MD_F -
NEX_ O_FR ERR_ ERR_ NEX_ O_FR ERR_ ERR_ NEX_ O_FR ERR_ ERR_ NEX_ O_FR ERR_ MD_P
FR_C _CH4 FR_C FR_C FR_C _CH4 FR_C FR_C FR_C _CH4 FR_C FR_C FR_C _CH4 FR_C ERR_
H4_F4 _F4
H4_F4 H4_F4 H4_F3 _F3
H4_F3 H4_F3 H4_F2 _F2
H4_F2 H4_F2 H4_F1 _F1
H4_F1 FR_C
H4_F1
Reset value
Access
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit Description
MD_UNEX_FR_CH4_F4 : see MD_UNEX_FR_CH1_F4
MD_NO_FR_CH4_F4 : see MD_NO_FR_CH1_F4
MD_FERR_FR_CH4_F4 : see MD_FERR_FR_CH1_F4
MD_PERR_FR_CH4_F4 : see MD_PERR_FR_CH1_F4
MD_UNEX_FR_CH4_F3 : see MD_UNEX_FR_CH1_F4
MD_NO_FR_CH4_F3 : see MD_NO_FR_CH1_F4
MD_FERR_FR_CH4_F3 : see MD_FERR_FR_CH1_F4
MD_PERR_FR_CH4_F3 : see MD_PERR_FR_CH1_F4
MD_UNEX_FR_CH4_F2 : see MD_UNEX_FR_CH1_F4
MD_NO_FR_CH4_F2 : see MD_NO_FR_CH1_F4
MD_FERR_FR_CH4_F2 : see MD_FERR_FR_CH1_F4
MD_PERR_FR_CH4_F2 : see MD_PERR_FR_CH1_F4
MD_UNEX_FR_CH4_F1 : see MD_UNEX_FR_CH1_F4
MD_NO_FR_CH4_F1 : see MD_NO_FR_CH1_F4
MD_FERR_FR_CH4_F1 : see MD_FERR_FR_CH1_F4
-MD_PERR_FR_CH4_F1 : see MD_PERR_FR_CH1_F4
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
79 / 89
QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
Table 6.2.6.3-11: Register ERROR_STATUS_10 (0x2E) Four error bits per frame (5-6)channel 4 and analog errors
MSB
LSB
Content
-
-
SYNC REV_ BUFF OC_C DIAG_CH4[1: MD_U MD_N MD_F MD_P MD_U MD_N MD_F MD_P
NEX_ O_FR ERR_ ERR_ NEX_ O_FR ERR_ ERR_
FR_C _CH4 FR_C FR_C FR_C _CH4 FR_C FR_C
_DAT CUR_ _ERR H4
CH4 _CH4
0]
A_
INV_C
H4
H4_F6 _F6
H4_F6 H4_F6 H4_F5 _F5
H4_F5 H4_F5
Reset value
Access
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
R/C
Bit Description
SYNC_DATA_ INV_CH4 : Reverse current status of channel 4
0b0: no SYNC pulse trigger during active Tx_LEN counter
0b1: SYNC pulse trigger during active Tx_LEN counter occurred
REV_CUR_CH4 : Reverse current status of channel 4
0b0: no reverse current detected
0b1: reverse current detected
BUFF_ERR_CH4 : Data buffer (96bit) configuration error
0b0: no configuration error
0b1: configuration error
OC_CH4 : Channel 4 over current status
0b0: no over current
0b1: over current
DIAG_CH4[1:0] : Channel 4 diagnosis status code (clear on read)
0b00: no error
0b01 leakage to GND
0b10: leakage to VBAT (soft short) / open load
MD_UNEX_FR_CH4_F6 : see MD_UNEX_FR_CH1_F4
MD_NO_FR_CH4_F6 : see MD_NO_FR_CH1_F4
MD_FERR_FR_CH4_F6 : see MD_FERR_FR_CH1_F4
MD_PERR_FR_CH4_F6 : see MD_PERR_FR_CH1_F4
MD_UNEX_FR_CH4_F5 : see MD_UNEX_FR_CH1_F4
MD_NO_FR_CH4_F5 : see MD_NO_FR_CH1_F4
MD_FERR_FR_CH4_F5 : see MD_FERR_FR_CH1_F4
MD_PERR_FR_CH4_F5 : see MD_PERR_FR_CH1_F4
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
80 / 89
QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
6.2.6.4 Diagnosis Registers
There are 8 (read only, R) registers available for diagnosis purposes.
Following diagnosis informations are available:
•
•
Voltages VDD,VBUS,VSYNC,VDD_INT
Voltages SIFX
Table 6.2.6.4-1: Diagnosis register
Register Name
DIAGNOSIS_ADC_1_2
DIAGNOSIS_ADC_3_4
Address
0x2F
Description
ADC data:VDD_INT,VDD
ADC data:VSIF2,VSIF1
ADC data:VSIF4,VSIF3
ADC data:VSYNC,VBUS
ADC data:VCP_GATE
0x30
DIAGNOSIS:_ADC_5_6 0x31
DIAGNOSIS_ADC_7_8 0x32
DIAGNOSIS_ADC_9_10 0x33
Reading of unused bits will always return '0' and writing of unused bits don't care. Writing to read only or read on
clear registers don't care. The SPI echo response to a write request is independently of register type (R/W, R, RC).
Table 6.2.6.4-2: Register DIAGNOSIS_ADC_1_2 (0x2F) ADC data:VDD_INT,VDD
MSB
LSB
LSB
LSB
Content
ADC_DATA_2[7:0]
ADC_DATA_1[7:0]
Reset value
Access
0
0
R
R
Bit Description
ADC_DATA_2[7:0] : ADC data
Voltage level VDD_INT
ADC_DATA_1[7:0] : ADC data
Voltage level VDD
Table 6.2.6.4-3: Register DIAGNOSIS_ADC_3_4 (0x30) ADC data:VSIF2,VSIF1
MSB
Content
ADC_DATA_4[7:0]
ADC_DATA_3[7:0]
Reset value
Access
0
0
R
R
Bit Description
ADC_DATA_4[7:0] : ADC data
Voltage level VSIF2
ADC_DATA_3[7:0] : ADC data
Voltage level VSIF1
Table 6.2.6.4-4: Register DIAGNOSIS:_ADC_5_6 (0x31) ADC data:VSIF4,VSIF3
MSB
Content
ADC_DATA_6[7:0]
ADC_DATA_5[7:0]
Reset value
Access
0
0
R
R
Bit Description
ADC_DATA_6[7:0] : ADC data
Voltage level VSIF4
ADC_DATA_5[7:0] : ADC data
Voltage level VSIF3
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
81 / 89
QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
Table 6.2.6.4-5: Register DIAGNOSIS_ADC_7_8 (0x32) ADC data:VSYNC,VBUS
MSB
LSB
Content
ADC_DATA_8[7:0]
ADC_DATA_7[7:0]
Reset value
Access
0
0
R
R
Bit Description
ADC_DATA_8[7:0] : ADC data
Voltage level VSYNC
ADC_DATA_7[7:0] : ADC data
Voltage level VBUS
Table 6.2.6.4-6: Register DIAGNOSIS_ADC_9_10 (0x33) ADC data:VCP_GATE
MSB
LSB
Content
-
-
-
-
-
-
-
-
ADC_DATA_9[7:0]
Reset value
Access
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Bit Description
ADC_DATA_9[7:0] : ADC data
Voltage level VCP_GATE
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
82 / 89
QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
7 Package Information
7.1 QFN20L5
All devices are available in a Pb free, RoHs compliant QFN20L5 plastic package according to JEDEC MO-220 K,
variant VHHC-2. The package is classified to Moisture Sensitivity Level 3 (MSL 3) according to JEDEC J-STD-020
with a soldering peak temperature of (260+5)°C.
mm
typ
0.90
inch
typ
0.035
Description
Symbol
min
0.80
max
1.00
min
0.031
max
0.039
Package height
Stand off
A
A1
0.00
--
0.02
0.20 REF
0.30
0.05
--
0.000
--
0.00079
0.0079 REF
0.012
0.002
--
Thickness of terminal leads, including lead finish
Width of terminal leads
A3
b
0.25
--
0.35
--
0.010
--
0.014
--
Package length / width
D / E
D2 / E2
e
5.00 BSC
3.65
0.197 BSC
0.144
Length / width of exposed pad
Lead pitch
3.50
--
3.80
--
0.138
--
0.150
--
0.65 BSC
0.40
0.026 BSC
0.016
Length of terminal for soldering to substrate
L
0.35
0.45
0.014
0.018
Step cut depth (incl. plating layer)
Step cut length (incl. plating layer)
Number of terminal positions
SCD
SCL
N
0.075
0.025
0.100
0.050
20
0.125
0.075
0.003
0.001
0.004
0.002
20
0.005
0.003
Note: the mm values are valid, the inch values contains rounding errors
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
83 / 89
QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
7.2 SOIC20
All devices are available in a Pb free, RoHs compliant SOIC20 plastic package according to JEDEC MS-013-E,
variant AC. The package is classified to Moisture Sensitivity Level 3 (MSL 3) according to JEDEC J-STD-020 with a
soldering peak temperature of (260+5)°C.
Description
Symbol
mm
typ
inch
typ
min
max
min
max
Package height
Stand off
A
--
--
2.65
0.30
--
--
--
0.104
0.012
--
A1
0.10
2.05
0.31
0.20
--
0.004
0.081
0.012
0.008
--
Package body thickness
Width of terminal leads, inclusive lead finish
Thickness of terminal leads, inclusive lead finish
Package length
A2
--
--
b
--
0.51
0.33
--
0.020
0.013
c
--
--
D
12.80 BSC
0.504 BSC
Package width
E
10.30 BSC
0.406 BSC
Package body width
E1
7.50 BSC
0.295 BSC
Lead pitch
e
1.27 BSC
0.050 BSC
Length of terminal for soldering to substrate
body chamfer (45°)
L
h
0.4
0.25
0
--
--
1.27
0.75
8
0.016
0.010
0
--
--
0.050
0.030
8
Angle of lead mounting area
mold release angle
phi [°]
phi1 [°]
N
--
--
5
--
15
5
--
15
Number of terminal positions
20
20
Note: the mm values are valid, the inch values contains rounding errors
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Data Sheet
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QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
WARNING – Life Support Applications Policy
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© Elmos Semiconductor AG, 2016. Reproduction, in part or whole, without the prior written consent of Elmos Semiconductor AG, is prohibited.
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Data Sheet
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QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
8 Index
Table of Content
Features.........................................................................................................................................................................1
Applications...................................................................................................................................................................1
General Description.......................................................................................................................................................1
Ordering Information......................................................................................................................................................1
Typical Application Circuit.............................................................................................................................................1
Functional Diagram........................................................................................................................................................2
1 Package Pinout QFN20L5,SO20...............................................................................................................................3
1.1 Pin Description QFN20L5...................................................................................................................................4
1.2 Pin Description SO20.........................................................................................................................................5
2 Application Description...............................................................................................................................................6
2.1 Application Circuits.............................................................................................................................................6
2.1.1 Application Circuits.....................................................................................................................................6
3 Functional Safety........................................................................................................................................................9
3.1 Functional Safety Requirements........................................................................................................................9
3.2 FMEDA...............................................................................................................................................................9
3.2.1 Safety Measures mandatory to reach ASIL Level C..................................................................................9
4 Operating Conditions................................................................................................................................................10
4.1 Absolute Maximum Ratings..............................................................................................................................10
4.2 Recommended Operating Conditions..............................................................................................................11
5 Detailed Electrical Specification...............................................................................................................................13
5.1 ANALOG PART................................................................................................................................................13
5.1.1 SUPPLY...................................................................................................................................................13
5.1.1.1 LDO Control Block...........................................................................................................................13
5.1.1.1.1 Electrical Parameter of LDO....................................................................................................13
5.1.1.1.2 Electrical Parameter Control Voltage......................................................................................15
5.1.1.2 Charge Pump for Sync Voltage.......................................................................................................15
5.1.2 POR AND POWER-UP SEQUENCE.......................................................................................................15
5.1.3 PSI5 INTERFACE....................................................................................................................................16
5.1.3.1 Interface Driver.................................................................................................................................16
5.1.3.2 Over Current Detection and Limitation............................................................................................17
5.1.3.3 Reverse Current Detection and Limitation.......................................................................................17
5.1.3.3.1 Reverse Current Flow from SIFx to VBUS..............................................................................17
5.1.3.3.2 Reverse Current Flow from SIFx to CSYNC...........................................................................18
5.1.3.4 Data Comparator..............................................................................................................................18
5.1.3.5 Sync Pulse Generation....................................................................................................................18
5.1.3.5.1 Sync Pulse Generation DC-Parameter....................................................................................18
5.1.3.5.2 Sync Pulse Generation AC Parameter....................................................................................19
5.1.3.6 Sync Pulse Generation by Pin TRIG...............................................................................................19
5.1.4 CLOCK GENERATION............................................................................................................................20
5.1.5 DIAGNOSIS.............................................................................................................................................21
5.1.5.1 ADC Voltage Measurements...........................................................................................................21
5.1.5.2 Over Temperature Monitoring (OT).................................................................................................21
5.1.5.3 VBUS Over Voltage Monitoring.......................................................................................................22
5.2 DIGITAL PART.................................................................................................................................................23
5.2.1 SPI............................................................................................................................................................23
5.2.1.1 DC Electrical Parameter Table of SPI IOs.......................................................................................23
5.2.1.2 AC Electrical Parameter Table of SPI I/Os......................................................................................23
6 Functional Description .............................................................................................................................................24
6.1 ANALOG PART................................................................................................................................................24
6.1.1 SUPPLY...................................................................................................................................................24
6.1.1.1 LDO Control Block...........................................................................................................................24
6.1.1.2 Charge Pump for Sync Voltage.......................................................................................................24
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Data Sheet
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QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
6.1.2 POR AND POWER-UP SEQUENCE.......................................................................................................25
6.1.3 PSI5 INTERFACE....................................................................................................................................25
6.1.3.1 Interface Driver.................................................................................................................................25
6.1.3.2 Over Current Detection and Limitation............................................................................................25
6.1.3.3 Reverse Current Detection and Limitation.......................................................................................25
6.1.3.3.1 Reverse Current Flow from SIFx to VBUS..............................................................................25
6.1.3.3.2 Reverse Current Flow from SIFx to CSYNC...........................................................................26
6.1.3.4 Quiescent Current Threshold Tracking............................................................................................26
6.1.3.5 Data Comparator..............................................................................................................................26
6.1.3.6 Sync Pulse Generation....................................................................................................................27
6.1.3.7 Sync Pulse Generation by Pin TRIG...............................................................................................28
6.1.3.8 Sync Pulse Generation by UART/SPI Command............................................................................29
6.1.4 CLOCK GENERATION............................................................................................................................29
6.1.5 DIAGNOSIS.............................................................................................................................................30
6.1.5.1 ADC Voltage Measurements...........................................................................................................30
6.1.5.2 Over Temperature Monitoring (OT).................................................................................................30
6.1.5.3 VBUS Over Voltage Monitoring.......................................................................................................31
6.1.5.4 Leakage to GND, Leakage to VBAT and Open Load......................................................................31
6.1.5.5 GND Loss Detection........................................................................................................................31
6.1.5.6 Transfer of Error- and Diagnosis Information to μController............................................................31
6.1.5.6.1 Error Information......................................................................................................................31
6.2 DIGITAL PART.................................................................................................................................................35
6.2.1 COMMUNICATION INTERFACE TO MICRO CONTROLLER...............................................................35
6.2.2 MANCHESTER DECODER.....................................................................................................................35
6.2.2.1 Manchester Data Handling and Buffer Architecture........................................................................35
6.2.2.1.1 UART DATA BUFFER.............................................................................................................36
6.2.2.1.2 SPI DATA BUFFER.................................................................................................................36
6.2.2.2 Manchester Bit Encoding.................................................................................................................38
6.2.2.2.1 Definition of data edge / compensation edge..........................................................................38
6.2.2.2.2 Interpretation with Manchester Decoder..................................................................................38
6.2.2.2.3 Definition of Duty Cycle...........................................................................................................38
6.2.2.2.4 Decoder Error Flags.................................................................................................................39
6.2.3 SPI............................................................................................................................................................39
6.2.3.1 Error Handling..................................................................................................................................41
6.2.3.2 Overview of Communication Frames...............................................................................................43
6.2.3.3 Overview of SPI commands.............................................................................................................44
6.2.3.4 No Operation Command..................................................................................................................44
6.2.3.5 Write Configuration Register Command..........................................................................................44
6.2.3.6 Software Reset Command...............................................................................................................45
6.2.3.7 Read Configuration Register Command..........................................................................................45
6.2.3.8 SYNC Pulse Command...................................................................................................................45
6.2.3.9 Read Sensor Data............................................................................................................................46
6.2.3.9.1 Read of 16bit (11bit sensor data)............................................................................................48
6.2.3.9.2 Read of 24bit (19bit sensor data)............................................................................................49
6.2.3.9.3 Read of 32bit (27bit sensor data)............................................................................................49
6.2.3.9.4 Read of 48bit (43bit sensor data)............................................................................................49
6.2.4 UART........................................................................................................................................................50
6.2.4.1 Error Handling .................................................................................................................................50
6.2.4.2 Packet Frame Definition...................................................................................................................52
6.2.4.3 UART Frame Definition....................................................................................................................52
6.2.4.4 Overview of Communication Frames...............................................................................................53
6.2.4.5 Overview of UART Commands........................................................................................................53
6.2.4.6 Write Register Command.................................................................................................................54
6.2.4.7 Read Register Command................................................................................................................54
6.2.4.8 Short SYNC Pulse Command..........................................................................................................55
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Data Sheet
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QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
6.2.4.9 Long SYNC Pulse Command..........................................................................................................55
6.2.4.10 No SYNC Pulse Command............................................................................................................55
6.2.4.11 Software Reset Command.............................................................................................................56
6.2.4.12 Response to Read Register Command.........................................................................................56
6.2.4.13 Transfer PSI5 Data........................................................................................................................57
6.2.5 XCRC[5:0] Calculation.............................................................................................................................58
6.2.6 CONFIGURATION...................................................................................................................................59
6.2.6.1 ASIC Configuration..........................................................................................................................59
6.2.6.1.1 Asynchronous mode................................................................................................................63
6.2.6.2 Timeslot Configuration.....................................................................................................................63
6.2.6.2.1 Timeslot Length.......................................................................................................................73
6.2.6.3 Error Registers.................................................................................................................................75
6.2.6.4 Diagnosis Registers.........................................................................................................................82
7 Package Information.................................................................................................................................................84
7.1 QFN20L5..........................................................................................................................................................84
7.2 SOIC20.............................................................................................................................................................85
8 Index.........................................................................................................................................................................87
Illustration Index
Figure 2.1.1-1: Application Circuit with LDO.................................................................................................................6
Figure 2.1.1-2: Application Circuit with VBUS Supplied from ECU...............................................................................7
Figure 6.1.3.5-1: Current Modulation..........................................................................................................................25
Figure 6.1.3.6-1: Sync Pulse Timing Diagram............................................................................................................26
Figure 6.1.3.7-1: Long SYNC Pulse Trigger via Pin TRIG..........................................................................................27
Figure 6.1.3.7-2: Short SYNC Pulse Trigger via Pin TRIG.........................................................................................27
Figure 6.1.3.8-1: Short SYNC Ptrigger via UART.......................................................................................................28
Figure 6.1.3.8-2: Short SYNC Pulse Trigger via SPI..................................................................................................28
Figure 6.2.2.1-1: Buffer Architecture Overview...........................................................................................................34
Figure 6.2.2.1.1-1: UART Data Buffer.........................................................................................................................35
Figure 6.2.2.1.2-1: SPI Data Buffer.............................................................................................................................36
Figure 6.2.2.1.2-2: SPI Data Buffer incl. 4 Frames.....................................................................................................36
Figure 6.2.2.2.3-1: Example MCD Duty Cycle............................................................................................................37
Figure 6.2.2.2.4-1: MD_FERR_CHx_F1.....................................................................................................................38
Figure 6.2.2.2.4-2: Set Of Error Flags (2errors; data=0x3FF).....................................................................................38
Figure 6.2.3-1: Data Flow Graphic..............................................................................................................................39
Figure 6.2.3.1-1: SPI Error Handling Example 1.........................................................................................................40
Figure 6.2.3.1-2: SPI Error Handling Example 2.........................................................................................................40
Figure 6.2.3.1-3: SPI Error Handling Example 3.........................................................................................................40
Figure 6.2.3.1-4: SPI Error Handling Example 4.........................................................................................................40
Figure 6.2.3.4-1: SPI NOP Command.........................................................................................................................43
Figure 6.2.3.5-1: SPI Write Register Command..........................................................................................................44
Figure 6.2.3.6-1: SPI Software Reset Command........................................................................................................44
Figure 6.2.3.7-1: SPI Read Register Command.........................................................................................................44
Figure 6.2.3.8-1: SPI SYNC Pulse Command.............................................................................................................45
Figure 6.2.3.9-1: Valid read sensor data window 1.....................................................................................................46
Figure 6.2.3.9-2: Valid read sensor data window 2.....................................................................................................46
Figure 6.2.3.9.1-1: SPI Read Sensor Data 16bit.........................................................................................................47
Figure 6.2.3.9.1-2: SPI Read Sensor Data 16bit-request at SDI_RXD -1st SPI frame-.............................................47
Figure 6.2.3.9.1-3: Response to SPI Read Sensor Data 16bit at SDO_TXD -2nd SPI frame-..................................47
Figure 6.2.3.9.2-1: Read Sensor Data 24bit command...............................................................................................48
Figure 6.2.3.9.3-1: Read Sensor Data 32bit command...............................................................................................48
Figure 6.2.3.9.4-1: Read Sensor Data 48bit command...............................................................................................48
Figure 6.2.4.1-1: UART Error Handling Example 1.....................................................................................................49
Figure 6.2.4.1-2: UART Error Handling Example 2.....................................................................................................49
Figure 6.2.4.1-3: Syncpulse staggering.......................................................................................................................50
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Data Sheet
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QM-No.: 25DS0109E.06
4 Channel Multi-Mode PSI5 Transceiver
PRODUCTION DATA – Apr 27, 2016
E521.41
Figure 6.2.4.3-1: UART Data Transmission................................................................................................................52
Figure 6.2.4.6-1: Write Register Command Packet Frame.........................................................................................53
Figure 6.2.4.7-1: Read Register Command Packet Frame.........................................................................................53
Figure 6.2.4.8-1: Short SYNC Command Packet Frame............................................................................................54
Figure 6.2.4.9-1: Long SYNC Command Packet Frame.............................................................................................54
Figure 6.2.4.10-1: No SYNC Pulse Command Packet Frame....................................................................................55
Figure 6.2.4.11-1: Software Reset Command Frame.................................................................................................55
Figure 6.2.4.12-1: Response to Read Register Command Packet Frame.................................................................56
Figure 6.2.4.13-1: Example: Upload PSI5 Data Minimum Packet Frame...................................................................56
Figure 6.2.4.13-2: Example: Upload PSI5 Data Maximum Packet Frame..................................................................56
Figure 6.2.5-1: XCRC-calculation for SPI frames.......................................................................................................57
Figure 6.2.5-2: XCRC: Example Transfer PSI5 Data..................................................................................................57
Figure 6.2.5-3: XCRC: Example Response to Read Command.................................................................................58
Figure 6.2.5-4: XCRC Example Read Sensor Data 24bit...........................................................................................58
Figure 6.2.6.2.1-1: Example1: TxLEN Configuration..................................................................................................72
Figure 6.2.6.2.1-2: Example2: TxLEN Configuration..................................................................................................72
Figure 6.2.6.2.1-3: Example2: TxLEN Configuration: Unexptected Sync Pulse.........................................................73
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Data Sheet
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QM-No.: 25DS0109E.06
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