首页 |元器件品牌

EBE11UD8AHWA [ELPIDA]

1GB Unbuffered DDR2 SDRAM DIMM; 1GB无缓冲DDR2 SDRAM DIMM
EBE11UD8AHWA
型号： EBE11UD8AHWA
厂家： ELPIDA MEMORY    ELPIDA MEMORY
描述：

1GB Unbuffered DDR2 SDRAM DIMM
1GB无缓冲DDR2 SDRAM DIMM

动态存储器 双倍数据速率
文件： 总28页 (文件大小：207K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
PRELIMINARY DATA SHEET  
1GB Unbuffered DDR2 SDRAM DIMM  
EBE11UD8AHWA (128M words × 64 bits, 2 Ranks)  
Specifications  
Features  
• Density: 1GB  
• Organization  
⎯ 128M words × 64 bits, 2 ranks  
• Mounting 16 pieces of 512M bits DDR2 SDRAM  
sealed in FBGA  
• Double-data-rate architecture; two data transfers per  
clock cycle  
• The high-speed data transfer is realized by the 4 bits  
prefetch pipelined architecture  
• Bi-directional differential data strobe (DQS and /DQS)  
is transmitted/received with data for capturing data at  
the receiver  
• Package: 240-pin socket type dual in line memory  
module (DIMM)  
• DQS is edge-aligned with data for READs; center-  
aligned with data for WRITEs  
⎯ PCB height: 30.0mm  
⎯ Lead pitch: 1.0mm  
⎯ Lead-free (RoHS compliant)  
• Power supply: VDD = 1.8V 0.1V  
• Data rate: 800Mbps (max.)  
• Differential clock inputs (CK and /CK)  
• DLL aligns DQ and DQS transitions with CK  
transitions  
• Commands entered on each positive CK edge; data  
and data mask referenced to both edges of DQS  
• Four internal banks for concurrent operation  
(components)  
• Data mask (DM) for write data  
• Posted /CAS by programmable additive latency for  
better command and data bus efficiency  
• Interface: SSTL_18  
• Burst lengths (BL): 4, 8  
• /CAS Latency (CL): 3, 4, 5, 6  
• Precharge: auto precharge option for each burst  
access  
• Off-Chip-Driver Impedance Adjustment and On-Die-  
Termination for better signal quality  
• /DQS can be disabled for single-ended Data Strobe  
operation  
• Refresh: auto-refresh, self-refresh  
• Refresh cycles: 8192 cycles/64ms  
⎯ Average refresh period  
7.8μs at 0°C ≤ TC ≤ +85°C  
3.9μs at +85°C < TC ≤ +95°C  
• Operating case temperature range  
⎯ TC = 0°C to +95°C  
Document No. E1028E10 (Ver. 1.0)  
Date Published April 2007 (K) Japan  
Printed in Japan  
URL: http://www.elpida.com  
©Elpida Memory, Inc. 2007  
EBE11UD8AHWA  
Ordering Information  
Component  
Data rate  
Mbps (max.)  
JEDEC speed bin  
(CL-tRCD-tRP)  
Contact  
pad  
Part number  
Package  
Mounted devices  
EBE11UD8AHWA-8E-E 800  
EBE11UD8AHWA-8G-E  
DDR2-800 (5-5-5)  
DDR2-800 (6-6-6)  
EDE5108AHBG-8E-E  
240-pin DIMM  
(lead-free)  
Gold  
EDE5108AHBG-8E-E  
EDE5108AHBG-8G-E  
Pin Configurations  
Front side  
1 pin  
64 pin65 pin  
120 pin  
121 pin  
184 pin 185 pin  
240 pin  
Back side  
Pin name  
A4  
Pin No.  
1
Pin name  
VREF  
VSS  
Pin No.  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
Pin No.  
121  
122  
123  
124  
125  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
Pin name  
VSS  
DQ4  
DQ5  
VSS  
DM0  
NC  
Pin No.  
181  
182  
183  
184  
185  
186  
187  
188  
189  
190  
191  
192  
193  
194  
195  
196  
197  
198  
199  
200  
201  
202  
203  
204  
205  
206  
207  
208  
Pin name  
VDD  
A3  
2
VDD  
3
DQ0  
A2  
A1  
4
DQ1  
VDD  
VDD  
CK0  
5
VSS  
VSS  
6
/DQS0  
DQS0  
VSS  
VSS  
/CK0  
VDD  
A0  
7
VDD  
VSS  
DQ6  
DQ7  
VSS  
DQ12  
DQ13  
VSS  
DM1  
NC  
8
NC  
9
DQ2  
VDD  
VDD  
BA1  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
DQ3  
A10/AP  
BA0  
VSS  
VDD  
/RAS  
/CS0  
VDD  
ODT0  
A13  
DQ8  
VDD  
DQ9  
/WE  
VSS  
/CAS  
VDD  
/DQS1  
DQS1  
VSS  
/CS1  
ODT1  
VDD  
VSS  
CK1  
VDD  
VSS  
DQ36  
DQ37  
VSS  
DM4  
NC  
NC  
/CK1  
VSS  
DQ14  
DQ15  
VSS  
DQ20  
DQ21  
VSS  
DM2  
NC  
NC  
VSS  
VSS  
DQ32  
DQ33  
VSS  
DQ10  
DQ11  
VSS  
/DQS4  
DQS4  
VSS  
DQ16  
DQ17  
VSS  
VSS  
DQ38  
DQ39  
VSS  
DQ44  
DQ34  
DQ35  
VSS  
/DQS2  
DQS2  
VSS  
Preliminary Data Sheet E1028E10 (Ver. 1.0)  
2
EBE11UD8AHWA  
Pin No.  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
Pin name  
VSS  
DQ18  
DQ19  
VSS  
DQ24  
DQ25  
VSS  
/DQS3  
DQS3  
VSS  
DQ26  
DQ27  
VSS  
NC  
Pin No.  
89  
Pin name  
DQ40  
DQ41  
VSS  
Pin No.  
149  
150  
151  
152  
153  
154  
155  
156  
157  
158  
159  
160  
161  
162  
163  
164  
165  
166  
167  
168  
169  
170  
171  
172  
173  
174  
175  
176  
177  
178  
179  
180  
Pin name  
DQ22  
DQ23  
VSS  
DQ28  
DQ29  
VSS  
DM3  
NC  
Pin No.  
209  
210  
211  
212  
213  
214  
215  
216  
217  
218  
219  
220  
221  
222  
223  
224  
225  
226  
227  
228  
229  
230  
231  
232  
233  
234  
235  
236  
237  
238  
239  
240  
Pin name  
DQ45  
VSS  
90  
91  
DM5  
NC  
92  
/DQS5  
DQS5  
VSS  
93  
VSS  
94  
DQ46  
DQ47  
VSS  
95  
DQ42  
DQ43  
VSS  
96  
97  
VSS  
DQ30  
DQ31  
VSS  
NC  
DQ52  
DQ53  
VSS  
98  
DQ48  
DQ49  
VSS  
99  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
CK2  
SA2  
/CK2  
VSS  
NC  
NC  
NC  
VSS  
VSS  
NC  
DM6  
NC  
VSS  
NC  
/DQS6  
DQS6  
VSS  
NC  
VSS  
NC  
VSS  
NC  
DQ54  
DQ55  
VSS  
VSS  
NC  
DQ50  
DQ51  
VSS  
NC  
NC  
VSS  
VDD  
CKE1  
VDD  
NC  
DQ60  
DQ61  
VSS  
VSS  
VDD  
CKE0  
VDD  
NC  
DQ56  
DQ57  
VSS  
DM7  
NC  
/DQS7  
DQS7  
VSS  
NC  
VSS  
NC  
VDD  
A12  
DQ62  
DQ63  
VSS  
VDD  
A11  
DQ58  
DQ59  
VSS  
A9  
A7  
VDD  
A8  
VDDSPD  
SA0  
VDD  
A5  
SDA  
SCL  
A6  
SA1  
Preliminary Data Sheet E1028E10 (Ver. 1.0)  
3
EBE11UD8AHWA  
Pin Description  
Pin name  
Function  
Address input  
Row address  
Column address  
A0 to A13  
A0 to A13  
A0 to A9  
A10 (AP)  
Auto precharge  
BA0, BA1  
Bank select address  
Data input/output  
DQ0 to DQ63  
/RAS  
Row address strobe command  
Column address strobe command  
Write enable  
/CAS  
/WE  
/CS0, /CS1  
Chip select  
CKE0, CKE1  
Clock enable  
CK0 to CK2  
Clock input  
/CK0 to /CK2  
Differential clock input  
Input and output data strobe  
Input mask  
DQS0 to DQS7, /DQS0 to /DQS7  
DM0 to DM7  
SCL  
Clock input for serial PD  
Data input/output for serial PD  
Serial address input  
Power for internal circuit  
Power for serial EEPROM  
Input reference voltage  
Ground  
SDA  
SA0 to SA2  
VDD  
VDDSPD  
VREF  
VSS  
ODT0, ODT1  
NC  
ODT control  
No connection  
Preliminary Data Sheet E1028E10 (Ver. 1.0)  
4
EBE11UD8AHWA  
Serial PD Matrix  
Byte No. Function described  
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments  
Number of bytes utilized by module  
manufacturer  
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
80H  
08H  
128 bytes  
256 bytes  
Total number of bytes in serial PD  
device  
2
3
4
5
6
7
8
Memory type  
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
1
0
0
1
08H  
0EH  
0AH  
61H  
40H  
00H  
05H  
DDR2 SDRAM  
Number of row address  
Number of column address  
Number of DIMM ranks  
Module data width  
14  
10  
2
64  
Module data width continuation  
0
Voltage interface level of this assembly 0  
SSTL 1.8V  
DDR SDRAM cycle time, CL = X  
-8E (CL = 5)  
9
0
0
1
0
0
1
0
1
25H  
2.5ns*1  
-8G (CL = 6)  
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
25H  
40H  
00H  
82H  
08H  
00H  
00H  
2.5ns*1  
0.4ns*1  
None.  
7.8μs  
× 8  
10  
11  
12  
13  
14  
15  
SDRAM access from clock (tAC)  
DIMM configuration type  
Refresh rate/type  
Primary SDRAM width  
Error checking SDRAM width  
Reserved  
None.  
0
SDRAM device attributes:  
Burst length supported  
16  
17  
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0CH  
04H  
4,8  
4
SDRAM device attributes: Number of  
banks on SDRAM device  
SDRAM device attributes:  
/CAS latency  
-8E  
18  
0
0
1
1
1
0
0
0
38H  
3, 4, 5  
-8G  
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
70H  
01H  
02H  
00H  
4, 5, 6  
19  
20  
21  
DIMM Mechanical Characteristics  
DIMM type information  
SDRAM module attributes  
4.00mm max.  
Unbuffered  
Normal  
Weak Driver 50Ω  
ODT Support  
22  
23  
SDRAM device attributes: General  
0
0
0
0
0
0
1
1
03H  
Minimum clock cycle time at CL = X − 1  
-8E (CL = 4)  
0
0
0
0
1
1
1
1
1
0
1
0
0
0
1
0
3DH  
30H  
3.75ns*1  
3.0ns*1  
-8G (CL = 5)  
Maximum data access time (tAC) from  
clock at CL = X − 1  
-8E (CL = 4)  
24  
25  
26  
0
1
0
1
0
0
0
0
50H  
0.5ns*1  
-8G (CL = 5)  
0
0
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
0
0
1
0
1
45H  
50H  
3DH  
0.45ns*1  
5.0ns*1  
Minimum clock cycle time at CL = X − 2  
-8E (CL = 3)  
-8G (CL = 4)  
3.75ns*1  
Maximum data access time (tAC) from  
clock at CL = X − 2  
-8E (CL = 3)  
0
0
1
1
1
0
0
1
0
0
0
0
0
0
0
0
60H  
50H  
0.6ns*1  
0.5ns*1  
-8G (CL = 4)  
Preliminary Data Sheet E1028E10 (Ver. 1.0)  
5
EBE11UD8AHWA  
Byte No. Function described  
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments  
Minimum row precharge time (tRP)  
-8E  
27  
0
0
0
0
0
0
1
1
0
1
1
1
0
1
1
0
1
1
1
0
1
0
0
0
32H  
3CH  
1EH  
12.5ns  
15ns  
-8G  
Minimum row active to row active delay  
(tRRD)  
28  
29  
7.5ns  
Minimum /RAS to /CAS delay (tRCD)  
-8E  
0
0
0
1
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
0
0
1
0
1
32H  
3CH  
2DH  
80H  
17H  
12.5ns  
15ns  
-8G  
Minimum active to precharge time  
(tRAS)  
30  
31  
32  
45ns  
Module rank density  
512M bytes  
0.17ns*1  
Address and command setup time  
before clock (tIS)  
Address and command hold time after  
clock (tIH)  
33  
34  
0
0
0
0
1
0
0
0
0
0
1
1
0
0
1
1
25H  
05H  
0.25ns*1  
0.05ns*1  
Data input setup time before clock  
(tDS)  
35  
36  
Data input hold time after clock (tDH)  
Write recovery time (tWR)  
0
0
0
0
0
1
1
1
0
1
0
1
1
0
0
0
12H  
3CH  
0.12ns*1  
15ns*1  
Internal write to read command delay  
(tWTR)  
37  
0
0
0
1
1
1
1
0
1EH  
7.5ns*1  
Internal read to precharge command  
delay (tRTP)  
38  
39  
40  
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
1
1
1
0
1
0
1
1
0
1
0
0
0
1
1
1
1
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
0
1
1EH  
00H  
30H  
00H  
39H  
3CH  
69H  
7.5ns*1  
TBD  
Memory analysis probe characteristics  
Extension of Byte 41 and 42  
-8E  
-8G  
Undefined  
57.5ns*1  
60ns*1  
Active command period (tRC)  
-8E  
41  
42  
-8G  
Auto refresh to active/  
Auto refresh command cycle (tRFC)  
105ns*1  
43  
SDRAM tCK cycle max. (tCK max.)  
Dout to DQS skew  
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
0
1
0
0
0
0
1
1
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
80H  
14H  
1EH  
00H  
00H  
12H  
8ns*1  
44  
0.20ns*1  
0.30ns*1  
Undefined  
Undefined  
Rev. 1.2  
45  
Data hold skew (tQHS)  
PLL relock time  
46  
47 to 61  
62  
SPD Revision  
Checksum for bytes 0 to 62  
-8E  
63  
0
1
0
1
1
0
0
0
58H  
-8G  
0
0
1
0
×
0
0
0
0
0
0
1
1
0
×
1
1
1
0
0
1
1
1
0
×
0
0
0
1
1
1
1
1
0
×
0
0
0
1
1
1
1
1
0
×
0
0
0
0
0
1
1
1
0
×
1
0
1
0
0
0
1
1
0
×
0
1
0
0
0
0
1
0
0
×
1
0
1
1
1
3CH  
7FH  
FEH  
00H  
××  
64 to 65  
66  
Manufacturer’s JEDEC ID code  
Manufacturer’s JEDEC ID code  
Manufacturer’s JEDEC ID code  
Manufacturing location  
Module part number  
Continuation code  
Elpida Memory  
67 to 71  
72  
(ASCII-8bit code)  
73  
45H  
42H  
45H  
31H  
31H  
E
B
E
1
74  
Module part number  
75  
Module part number  
76  
Module part number  
77  
Module part number  
1
Preliminary Data Sheet E1028E10 (Ver. 1.0)  
6
EBE11UD8AHWA  
Byte No. Function described  
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments  
78  
79  
80  
81  
82  
83  
84  
85  
86  
Module part number  
Module part number  
Module part number  
Module part number  
Module part number  
Module part number  
Module part number  
Module part number  
Module part number  
0
0
0
0
0
0
0
0
0
1
1
0
1
1
1
1
0
0
0
0
1
0
0
0
0
1
1
1
0
1
0
0
1
0
0
1
0
0
1
0
1
0
0
1
1
1
1
0
0
0
1
0
1
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
1
1
1
0
55H  
44H  
38H  
41H  
48H  
57H  
41H  
2DH  
38H  
U
D
8
A
H
W
A
—
8
Module part number  
-8E  
87  
0
1
0
0
0
1
0
1
45H  
E
-8G  
0
0
0
0
0
0
×
×
1
0
1
0
0
0
×
×
0
1
0
1
1
1
×
×
0
0
0
0
1
0
×
×
0
1
0
0
0
0
×
×
1
1
1
0
0
0
×
×
1
0
0
0
0
0
×
×
1
1
1
0
0
0
×
×
47H  
2DH  
45H  
20H  
30H  
20H  
××  
G
88  
Module part number  
Module part number  
Module part number  
Revision code  
—
89  
E
90  
(Space)  
91  
Initial  
92  
Revision code  
(Space)  
93  
Manufacturing date  
Manufacturing date  
Module serial number  
Year code (BCD)  
Week code (BCD)  
94  
××  
95 to 98  
99 to 127 Manufacture specific data  
Note: 1.These specifications are defined based on component specification, not module.  
Preliminary Data Sheet E1028E10 (Ver. 1.0)  
7
EBE11UD8AHWA  
Block Diagram  
/CS1  
/CS0  
R
R
S1  
S1  
S1  
S1  
/DQS0  
DQS0  
DM0  
/DQS4  
DQS4  
DM4  
R
S1  
S1  
R
R
R
DM /CS DQS /DQS  
DM /CS DQS /DQS  
DM /CS DQS /DQS  
DM /CS DQS /DQS  
8
R
S1  
8
R
S1  
D0  
D9  
D4  
D13  
DQ0  
to DQ7  
DQ0  
to DQ7  
DQ0  
to DQ7  
DQ0  
to DQ7  
DQ0 to DQ7  
/DQS1  
DQ32 to DQ39  
R
S1  
R
R
S1  
/DQS5  
DQS5  
DM5  
R
R
S1  
S1  
DQS1  
DM1  
S1  
R
S1  
DM /CS DQS /DQS  
DM /CS DQS /DQS  
DQ0  
DM /CS DQS /DQS  
DQ0  
DM /CS DQS /DQS  
DQ0  
R
S1  
R
S1  
8
8
DQ0  
D1  
DQ8 to DQ15  
/DQS2  
DQ40 to DQ47  
/DQS6  
D10  
D5  
D14  
to DQ7  
to DQ7  
to DQ7  
to DQ7  
R
S1  
R
S1  
R
S1  
R
R
S1  
R
S1  
S1  
DQS2  
DM2  
DQS6  
DM6  
DM /CS DQS /DQS  
/DQS  
/DQS  
/DQS  
DM /CS DQS  
DM /CS DQS  
DM /CS DQS  
8
R
S1  
8
R
S1  
DQ0  
to DQ7  
DQ0  
to DQ7  
DQ0  
to DQ7  
DQ0  
to DQ7  
D11  
D6  
D15  
D2  
DQ48 to DQ55  
/DQS7  
DQ16 to DQ23  
/DQS3  
R
S1  
R
S1  
R
S1  
R
S1  
R
R
S1  
DQS3  
DM3  
DQS7  
DM7  
S1  
DM /CS DQS /DQS  
/DQS  
/DQS  
/DQS  
DM /CS DQS  
DM /CS DQS  
DM /CS DQS  
R
S1  
8
R
S1  
8
D3  
DQ0  
to DQ7  
DQ0  
to DQ7  
DQ0  
to DQ7  
DQ0  
to DQ7  
D12  
D7  
D16  
DQ56 to DQ63  
DQ24 to DQ31  
R
S2  
BA0 to BA1  
A0 to A13  
BA0 to BA1: SDRAMs (D0 to D7, D9 to D16)  
A0 to A13: SDRAMs (D0 to D7, D9 to D16)  
Serial PD  
SDA  
R
S2  
R
S2  
R
S2  
R
S2  
SCL  
SA0  
SA1  
SA2  
SCL  
A0  
SDA  
/RAS  
/CAS  
/WE  
/RAS: SDRAMs (D0 to D7, D9 to D16)  
/CAS: SDRAMs (D0 to D7, D9 to D16))  
/WE: SDRAMs (D0 to D7, D9 to D16)  
U0  
A1  
A2  
WP  
CKE0  
CKE1  
ODT0  
ODT1  
CKE: SDRAMs (D0 to D7)  
CKE: SDRAMs (D9 to D16)  
ODT:SDRAMs (D0 to D7)  
ODT:SDRAMs (D9 to D16)  
Notes :  
1. DQ wiring may be changed within a byte.  
VDDSPD  
VREF  
SPD  
2. DQ, DQS, /DQS, ODT, DM, CKE, /CS relationships  
must be meintained as shown.  
SDRAMs (D0 to D7, D9 to D16)  
SDRAMs (D0 to D7, D9 to D16)  
3. Refer to the appropriate clock wiring topology  
under the DIMM wiring details section of this document.  
VDD  
VSS  
SDRAMs (D0 to D7, D9 to D16)  
* D0 to D15 : 512M bits DDR2 SDRAM  
U0 : 2k bits EEPROM  
Rs1 : 22  
Ω
Rs2 : 7.5  
Ω
Preliminary Data Sheet E1028E10 (Ver. 1.0)  
8
EBE11UD8AHWA  
Logical Clock Net Structure  
6DRAM loads (CK1 and /CK1, CK2 and /CK2)  
DRAM  
R = 200Ω  
DRAM  
DRAM  
DIMM  
R = 200Ω  
connector  
DRAM  
DRAM  
DRAM  
R = 200Ω  
4DRAM loads (CK0 and /CK0)  
R = 200Ω  
DRAM  
DRAM  
C2  
DIMM  
connector  
R = 200Ω  
DRAM  
DRAM  
R = 200Ω  
*C2: 2pF  
Preliminary Data Sheet E1028E10 (Ver. 1.0)  
9
EBE11UD8AHWA  
Electrical Specifications  
• All voltages are referenced to VSS (GND).  
Absolute Maximum Ratings  
Parameter  
Symbol  
VT  
Value  
Unit  
V
Notes  
1
Voltage on any pin relative to VSS  
Supply voltage relative to VSS  
Short circuit output current  
Power dissipation  
–0.5 to +2.3  
–0.5 to +2.3  
50  
VDD  
IOS  
PD  
V
mA  
W
1
8
Operating case temperature  
Storage temperature  
TC  
0 to +95  
–55 to +100  
°C  
°C  
1, 2  
1
Tstg  
Notes: 1. DDR2 SDRAM component specification.  
2. Supporting 0°C to +85°C and being able to extend to +95°C with doubling auto-refresh commands in  
frequency to a 32ms period (tREFI = 3.9μs) and higher temperature self-refresh entry via the control of  
EMRS (2) bit A7 is required.  
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause  
permanent damage. The device is not meant to be operated under conditions outside the limits  
described in the operational section of this specification Exposure to Absolute Maximum Rating  
conditions for extended periods may affect device reliability.  
DC Operating Conditions (TC = 0°C to +85°C) (DDR2 SDRAM Component Specification)  
Parameter  
Symbol  
VDD, VDDQ  
VSS  
min.  
typ.  
1.8  
0
max.  
1.9  
0
Unit  
V
Notes  
4
Supply voltage  
1.7  
0
V
VDDSPD  
VREF  
1.7  
—
3.6  
V
Input reference voltage  
Termination voltage  
DC input logic high  
DC input low  
0.49 × VDDQ  
VREF − 0.04  
VREF + 0.125  
−0.3  
0.50 × VDDQ 0.51 × VDDQ  
V
1, 2  
3
VTT  
VREF  
⎯
VREF + 0.04  
VDDQ + 0.3  
VREF – 0.125  
⎯
V
VIH (DC)  
VIL (DC)  
VIH (AC)  
VIL (AC)  
V
⎯
V
AC input logic high  
AC input low  
VREF + 0.200  
⎯
⎯
V
⎯
VREF − 0.200  
V
Notes: 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically  
the value of VREF is expected to be about 0.5 × VDDQ of the transmitting device and VREF are expected  
to track variations in VDDQ.  
2. Peak to peak AC noise on VREF may not exceed 2% VREF (DC).  
3. VTT of transmitting device must track VREF of receiving device.  
4. VDDQ must be equal to VDD.  
Preliminary Data Sheet E1028E10 (Ver. 1.0)  
10  
EBE11UD8AHWA  
AC Overshoot/Undershoot Specification (DDR2 SDRAM Component Specification)  
Parameter  
Pins  
Specification  
Unit  
V
Command, Address,  
CKE, ODT  
Maximum peak amplitude allowed for overshoot  
Maximum peak amplitude allowed for undershoot  
0.5  
0.5  
V
Maximum overshoot area above VDD  
DDR2-800  
0.66  
V-ns  
Maximum undershoot area below VSS  
DDR2-800  
0.66  
V-ns  
Maximum peak amplitude allowed for overshoot  
Maximum peak amplitude allowed for undershoot  
CK, /CK  
0.5  
0.5  
V
V
Maximum overshoot area above VDD  
DDR2-800  
0.23  
0.23  
V-ns  
V-ns  
Maximum undershoot area below VSS  
DDR2-800  
Maximum peak amplitude allowed for overshoot  
Maximum peak amplitude allowed for undershoot  
DQ, DQS, /DQS,  
0.5  
0.5  
V
V
RDQS, /RDQS, DM  
Maximum overshoot area above VDDQ  
DDR2-800  
0.23  
0.23  
V-ns  
V-ns  
Maximum undershoot area below VSSQ  
DDR2-800  
Maximum amplitude  
Overshoot area  
VDD, VDDQ  
Volts (V)  
VSS, VSSQ  
Undershoot area  
Time (ns)  
Overshoot/Undershoot Definition  
Preliminary Data Sheet E1028E10 (Ver. 1.0)  
11  
EBE11UD8AHWA  
DC Characteristics 1 (TC = 0°C to +85°C, VDD = 1.8V ± 0.1V, VSS = 0V)  
Parameter  
Symbol Grade  
IDD0  
max.  
680  
Unit  
mA  
Test condition  
Operating current  
(ACT-PRE)  
(Another rank is in IDD2P)  
one bank; tCK = tCK (IDD), tRC = tRC (IDD),  
tRAS = tRAS min.(IDD);  
CKE is H, /CS is H between valid commands;  
Address bus inputs are SWITCHING;  
Data bus inputs are SWITCHING  
Operating current  
(ACT-PRE)  
(Another rank is in IDD3N)  
IDD0  
IDD1  
1000  
760  
mA  
mA  
one bank; IOUT = 0mA;  
BL = 4, CL = CL(IDD), AL = 0;  
Operating current  
(ACT-READ-PRE)  
tCK = tCK (IDD), tRC = tRC (IDD),  
tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);  
CKE is H, /CS is H between valid commands;  
Address bus inputs are SWITCHING;  
Data pattern is same as IDD4W  
(Another rank is in IDD2P)  
Operating current  
IDD1  
1080  
160  
mA  
mA  
(ACT-READ-PRE)  
(Another rank is in IDD3N)  
all banks idle;  
tCK = tCK (IDD);  
CKE is L;  
Other control and address bus inputs are STABLE;  
Data bus inputs are FLOATING  
Precharge power-down  
standby current  
IDD2P  
all banks idle;  
tCK = tCK (IDD);  
CKE is H, /CS is H;  
Other control and address bus inputs are STABLE;  
Data bus inputs are FLOATING  
Precharge quiet standby  
current  
IDD2Q  
IDD2N  
448  
560  
mA  
mA  
all banks idle;  
tCK = tCK (IDD);  
CKE is H, /CS is H;  
Idle standby current  
Other control and address bus inputs are SWITCHING;  
Data bus inputs are SWITCHING  
all banks open;  
Fast PDN Exit  
tCK = tCK (IDD);  
MRS(12) = 0  
CKE is L;  
IDD3P-F  
IDD3P-S  
400  
240  
mA  
mA  
Active power-down  
standby current  
Other control and address bus  
Slow PDN Exit  
MRS(12) = 1  
inputs are STABLE;  
Data bus inputs are FLOATING  
all banks open;  
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);  
CKE is H, /CS is H between valid commands;  
Other control and address bus inputs are SWITCHING;  
Data bus inputs are SWITCHING  
Active standby current  
IDD3N  
800  
mA  
Operating current  
all banks open, continuous burst reads, IOUT = 0mA;  
BL = 4, CL = CL(IDD), AL = 0;  
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);  
CKE is H, /CS is H between valid commands;  
Address bus inputs are SWITCHING;  
IDD4R  
IDD4R  
IDD4W  
IDD4W  
1160  
1480  
1200  
1520  
mA  
mA  
mA  
mA  
(Burst read operating)  
(Another rank is in IDD2P)  
Operating current  
(Burst read operating)  
(Another rank is in IDD3N)  
Data pattern is same as IDD4W  
Operating current  
all banks open, continuous burst writes;  
BL = 4, CL = CL(IDD), AL = 0;  
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);  
CKE is H, /CS is H between valid commands;  
Address bus inputs are SWITCHING;  
Data bus inputs are SWITCHING  
(Burst write operating)  
(Another rank is in IDD2P)  
Operating current  
(Burst write operating)  
(Another rank is in IDD3N)  
tCK = tCK (IDD);  
Auto-refresh current  
(Another rank is in IDD2P)  
IDD5  
IDD5  
1640  
1960  
mA  
mA  
Refresh command at every tRFC (IDD) interval;  
CKE is H, /CS is H between valid commands;  
Other control and address bus inputs are SWITCHING;  
Data bus inputs are SWITCHING  
Auto-refresh current  
(Another rank is in IDD3N)  
Preliminary Data Sheet E1028E10 (Ver. 1.0)  
12  
EBE11UD8AHWA  
Parameter  
Symbol Grade  
IDD6  
max.  
96  
Unit  
mA  
Test condition  
Self Refresh Mode;  
CK and /CK at 0V;  
CKE ≤ 0.2V;  
Self-refresh current  
Other control and address bus inputs are FLOATING;  
Data bus inputs are FLOATING  
all bank interleaving reads, IOUT = 0mA;  
BL = 4, CL = CL(IDD), AL = tRCD (IDD) −1 × tCK (IDD);  
tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD),  
tRCD = 1 × tCK (IDD);  
Operating current  
IDD7  
IDD7  
1440  
1760  
mA  
mA  
(Bank interleaving)  
(Another rank is in IDD2P)  
Operating current  
CKE is H, CS is H between valid commands;  
Address bus inputs are STABLE during DESELECTs;  
Data pattern is same as IDD4W;  
(Bank interleaving)  
(Another rank is in IDD3N)  
Notes: 1. IDD specifications are tested after the device is properly initialized.  
2. Input slew rate is specified by AC Input Test Condition.  
3. IDD parameters are specified with ODT disabled.  
4. Data bus consists of DQ, DM, DQS, /DQS, RDQS and /RDQS. IDD values must be met with all  
combinations of EMRS bits 10 and 11.  
5. Definitions for IDD  
L is defined as VIN ≤ VIL (AC) (max.)  
H is defined as VIN ≥ VIH (AC) (min.)  
STABLE is defined as inputs stable at an H or L level  
FLOATING is defined as inputs at VREF = VDDQ/2  
SWITCHING is defined as:  
inputs changing between H and L every other clock cycle (once per two clocks) for address and control  
signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals  
not including masks or strobes.  
6. Refer to AC Timing for IDD Test Conditions.  
AC Timing for IDD Test Conditions  
For purposes of IDD testing, the following parameters are to be utilized.  
DDR2-800  
5-5-5  
5
DDR2-800  
6-6-6  
6
Parameter  
Unit  
tCK  
ns  
CL (IDD)  
tRCD (IDD)  
tRC (IDD)  
12.5  
57.5  
7.5  
15  
60  
ns  
tRRD (IDD)  
tCK (IDD)  
7.5  
ns  
2.5  
2.5  
ns  
tRAS (min.)(IDD)  
tRAS (max.)(IDD)  
tRP (IDD)  
45  
45  
ns  
70000  
12.5  
105  
70000  
15  
ns  
ns  
tRFC (IDD)  
105  
ns  
Preliminary Data Sheet E1028E10 (Ver. 1.0)  
13  
EBE11UD8AHWA  
DC Characteristics 2 (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V)  
(DDR2 SDRAM Component Specification)  
Parameter  
Symbol  
⏐ILI⏐  
Value  
Unit  
Notes  
Input leakage current  
Output leakage current  
2
5
μA  
μA  
VDD ≥ VIN ≥ VSS  
VDDQ ≥ VOUT ≥ VSS  
⏐ILO⏐  
Minimum required output pull-up under AC  
test load  
VOH  
VOL  
VTT + 0.603  
VTT – 0.603  
V
V
5
5
Maximum required output pull-down under  
AC test load  
Output timing measurement reference level VOTR  
0.5 × VDDQ  
+13.4  
V
1
Output minimum sink DC current  
Output minimum source DC current  
IOL  
mA  
mA  
3, 4, 5  
2, 4, 5  
IOH  
–13.4  
Notes: 1. The VDDQ of the device under test is referenced.  
2. VDDQ = 1.7V; VOUT = 1.42V.  
3. VDDQ = 1.7V; VOUT = 0.28V.  
4. The DC value of VREF applied to the receiving device is expected to be set to VTT.  
5. After OCD calibration to 18Ω at TC = 25°C, VDD = VDDQ = 1.8V.  
DC Characteristics 3 (TC = 0°C to +85°C, VDD, VDDQ = 1.8V 0.1V)  
(DDR2 SDRAM Component Specification)  
Parameter  
Symbol  
min.  
max.  
Unit  
V
Notes  
1, 2  
2
AC differential input voltage  
AC differential cross point voltage  
AC differential cross point voltage  
VID (AC)  
VIX (AC)  
VOX (AC)  
0.5  
VDDQ + 0.6  
0.5 × VDDQ − 0.175  
0.5 × VDDQ − 0.125  
0.5 × VDDQ + 0.175  
0.5 × VDDQ + 0.125  
V
V
3
Notes: 1. VID (AC) specifies the input differential voltage |VTR -VCP| required for switching, where VTR is the true  
input signal (such as CK, DQS, RDQS) and VCP is the complementary input signal (such as /CK, /DQS,  
/RDQS). The minimum value is equal to VIH (AC) − VIL (AC).  
2. The typical value of VIX (AC) is expected to be about 0.5 × VDDQ of the transmitting device and VIX (AC)  
is expected to track variations in VDDQ. VIX (AC) indicates the voltage at which differential input signals  
must cross.  
3. The typical value of VOX (AC) is expected to be about 0.5 × VDDQ of the transmitting device and VOX  
(AC) is expected to track variations in VDDQ. VOX (AC) indicates the voltage at which differential output  
signals must cross.  
VDDQ  
VTR  
Crossing point  
VID  
VIX or VOX  
VCP  
VSSQ  
Differential Signal Levels*1, 2  
Preliminary Data Sheet E1028E10 (Ver. 1.0)  
14  
EBE11UD8AHWA  
ODT DC Electrical Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.8V 0.1V)  
(DDR2 SDRAM Component Specification)  
Parameter  
Symbol  
Rtt1(eff)  
Rtt2(eff)  
Rtt3(eff)  
ΔVM  
min.  
60  
typ.  
75  
max.  
90  
Unit  
Ω
Note  
Rtt effective impedance value for EMRS (A6, A2) = 0, 1; 75 Ω  
Rtt effective impedance value for EMRS (A6, A2) = 1, 0; 150 Ω  
Rtt effective impedance value for EMRS (A6, A2) = 1, 1; 50 Ω  
Deviation of VM with respect to VDDQ/2  
1
1
1
1
120  
40  
150  
50  
180  
60  
Ω
Ω
−6  
⎯
+6  
%
Note: 1. Test condition for Rtt measurements.  
Measurement Definition for Rtt (eff)  
Apply VIH (AC) and VIL (AC) to test pin separately, then measure current I(VIH (AC)) and I(VIL (AC)) respectively.  
VIH (AC), and VDDQ values defined in SSTL_18.  
VIH(AC)−VIL(AC)  
Rtt(eff ) =  
I(VIH(AC))−I(VIL(AC))  
Measurement Definition for ΔVM  
Measure voltage (VM) at test pin (midpoint) with no load.  
2×VM  
VDDQ  
⎛
⎜
⎞
⎠
ΔVM =  
−1 ×100  
⎟
⎝
OCD Default Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.8V 0.1V)  
(DDR2 SDRAM Component Specification)  
Parameter  
min.  
12.6  
0
typ.  
18  
⎯
max.  
23.4  
4
Unit  
Ω
Notes  
1, 5  
Output impedance  
Pull-up and pull-down mismatch  
Output slew rate  
Ω
1, 2  
1.5  
⎯
5
V/ns  
3, 4  
Notes: 1. Impedance measurement condition for output source DC current: VDDQ = 1.7V; VOUT = 1420mV;  
(VOUT−VDDQ)/IOH must be less than 23.4Ω for values of VOUT between VDDQ and VDDQ−280mV.  
Impedance measurement condition for output sink DC current: VDDQ = 1.7V; VOUT = 280mV;  
VOUT/IOL must be less than 23.4Ω for values of VOUT between 0V and 280mV.  
2. Mismatch is absolute value between pull up and pull down, both are measured at same temperature and  
voltage.  
3. Slew rate measured from VIL(AC) to VIH(AC).  
4. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate  
as measured from AC to AC. This is guaranteed by design and characterization.  
5. DRAM I/O specifications for timing, voltage, and slew rate are no longer applicable if OCD is changed  
from default settings.  
Preliminary Data Sheet E1028E10 (Ver. 1.0)  
15  
EBE11UD8AHWA  
Pin Capacitance (TA = 25°C, VDD = 1.8V ± 0.1V)  
(DDR2 SDRAM Component Specification)  
Parameter  
Symbol Pins  
min.  
1.0  
max.  
2.0  
Unit  
pF  
Notes  
1
CLK input pin capacitance  
CCK  
CK, /CK  
/RAS, /CAS,  
/WE, /CS,  
Input pin capacitance  
CIN  
1.0  
2.5  
1.75  
3.5  
pF  
pF  
1
2
CKE, ODT,  
Address  
DQ, DQS, /DQS,  
RDQS, /RDQS,  
DM  
Input/output pin capacitance  
CI/O  
Notes: 1. Matching within 0.25pF.  
2. Matching within 0.50pF.  
Preliminary Data Sheet E1028E10 (Ver. 1.0)  
16  
EBE11UD8AHWA  
AC Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.8V 0.1V, VSS, VSSQ = 0V)  
(DDR2 SDRAM Component Specification)  
• New units tCK(avg) and nCK, are introduced in DDR2-800 and DDR2-667  
tCK(avg): actual tCK(avg) of the input clock under operation.  
nCK: one clock cycle of the input clock, counting the actual clock edges.  
-8E, -8G  
Frequency (Mbps)  
Parameter  
800  
Symbol  
CL  
min.  
max.  
Unit  
nCK  
Notes  
5 (-8E)  
6 (-8G)  
5 (-8E)  
6 (-8G)  
/CAS latency  
12.5 (-8E)  
15 (-8G)  
Active to read or write command delay  
Precharge command period  
tRCD  
tRP  
⎯
⎯
⎯
ns  
ns  
ns  
12.5 (-8E)  
15 (-8G)  
57.5(-8E)  
60 (-8G)  
Active to active/auto-refresh command time  
tRC  
DQ output access time from CK, /CK  
DQS output access time from CK, /CK  
CK high-level width  
tAC  
−400  
−350  
0.48  
0.48  
+400  
+350  
0.52  
0.52  
ps  
10  
10  
13  
13  
tDQSCK  
tCH (avg)  
tCL(avg)  
ps  
tCK (avg)  
tCK (avg)  
CK low-level width  
Min. (tCL(abs),  
tCH(abs))  
CK half period  
tHP  
⎯
ps  
6, 13  
Clock cycle time  
tCK (avg)  
tDH (base)  
tDS (base)  
tIPW  
2500  
8000  
⎯
ps  
13  
5
DQ and DM input hold time  
125  
ps  
DQ and DM input setup time  
50  
⎯
ps  
4
Control and Address input pulse width for each input  
DQ and DM input pulse width for each input  
Data-out high-impedance time from CK,/CK  
DQS, /DQS low-impedance time from CK,/CK  
DQ low-impedance time from CK,/CK  
DQS-DQ skew for DQS and associated DQ signals  
DQ hold skew factor  
0.6  
⎯
tCK (avg)  
tDIPW  
0.35  
⎯
tCK (avg)  
tHZ  
⎯
tAC max.  
tAC max.  
tAC max.  
200  
ps  
ps  
ps  
ps  
ps  
ps  
10  
10  
10  
tLZ (DQS)  
tLZ (DQ)  
tDQSQ  
tQHS  
tAC min.  
2 × tAC min.  
⎯
⎯
300  
7
8
DQ/DQS output hold time from DQS  
tQH  
tHP – tQHS  
⎯
DQS latching rising transitions to associated clock  
edges  
tDQSS  
−0.25  
+0.25  
tCK (avg)  
DQS input high pulse width  
DQS input low pulse width  
DQS falling edge to CK setup time  
DQS falling edge hold time from CK  
Mode register set command cycle time  
Write postamble  
tDQSH  
tDQSL  
tDSS  
0.35  
0.35  
0.2  
⎯
tCK (avg)  
tCK (avg)  
tCK (avg)  
tCK (avg)  
nCK  
⎯
⎯
tDSH  
0.2  
⎯
tMRD  
2
⎯
tWPST  
tWPRE  
tIH (base)  
tIS (base)  
tRPRE  
tRPST  
tRAS  
0.4  
0.6  
⎯
tCK (avg)  
tCK (avg)  
ps  
Write preamble  
0.35  
250  
175  
0.9  
Address and control input hold time  
Address and control input setup time  
Read preamble  
⎯
5
⎯
ps  
4
1.1  
0.6  
70000  
⎯
tCK (avg)  
tCK (avg)  
ns  
11  
12  
Read postamble  
0.4  
Active to precharge command  
Active to auto precharge delay  
45  
tRAP  
tRCD min.  
ns  
Preliminary Data Sheet E1028E10 (Ver. 1.0)  
17  
EBE11UD8AHWA  
-8E, -8G  
800  
min.  
7.5  
Frequency (Mbps)  
Parameter  
Symbol  
tRRD  
tCCD  
tWR  
max.  
⎯
Unit  
ns  
Notes  
Active bank A to active bank B command period  
/CAS to /CAS command delay  
Write recovery time  
2
⎯
nCK  
ns  
15  
⎯
WR + RU  
(tRP/tCK(avg))  
Auto precharge write recovery + precharge time  
tDAL  
⎯
nCK  
1, 9  
Internal write to read command delay  
Internal read to precharge command delay  
Exit self-refresh to a non-read command  
Exit self-refresh to a read command  
tWTR  
tRTP  
7.5  
⎯
⎯
⎯
⎯
⎯
⎯
ns  
7.5  
ns  
tXSNR  
tXSRD  
tRFC + 10  
ns  
200  
2
nCK  
nCK  
nCK  
Exit precharge power-down to any non-read command tXP  
Exit active power-down to read command  
tXARD  
2
3
Exit active power-down to read command  
(slow exit/low power mode)  
tXARDS  
8 − AL  
⎯
nCK  
2, 3  
CKE minimum pulse width (high and low pulse width)  
Output impedance test driver delay  
tCKE  
tOIT  
3
⎯
12  
12  
⎯
nCK  
ns  
0
MRS command to ODT update delay  
tMOD  
tRFC  
0
ns  
Auto-refresh to active/auto-refresh command time  
105  
ns  
Average periodic refresh interval  
(0°C ≤ TC ≤ +85°C)  
tREFI  
⎯
⎯
7.8  
3.9  
⎯
μs  
μs  
ns  
(+85°C < TC ≤ +95°C)  
tREFI  
Minimum time clocks remains ON after CKE  
asynchronously drops low  
tIS + tCK(avg) +  
tIH  
tDELAY  
Notes: 1. For each of the terms above, if not already an integer, round to the next higher integer.  
2. AL: Additive Latency.  
3. MRS A12 bit defines which active power down exit timing to be applied.  
4. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the  
VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under test.  
5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the  
VIH(DC) level for a rising signal and VIL(DC) for a falling signal applied to the device under test.  
CK  
DQS  
/CK  
/DQS  
tIS  
tIH  
tIS  
tIH  
tDS tDH  
tDS tDH  
VDDQ  
VDDQ  
VIH (AC)(min.)  
VIH (DC)(min.)  
VREF  
VIH (AC)(min.)  
VIH (DC)(min.)  
VREF  
VIL (DC)(max.)  
VIL (AC)(max.)  
VSS  
VIL (DC)(max.)  
VIL (AC)(max.)  
VSS  
Input Waveform Timing 1 (tDS, tDH)  
Input Waveform Timing 2 (tIS, tIH)  
Preliminary Data Sheet E1028E10 (Ver. 1.0)  
18  
EBE11UD8AHWA  
6. tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not  
an input specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing  
tQH.  
The value to be used for tQH calculation is determined by the following equation;  
tHP = min ( tCH(abs), tCL(abs) ),  
where,  
tCH(abs) is the minimum of the actual instantaneous clock high time;  
tCL(abs) is the minimum of the actual instantaneous clock low time;  
7. tQHS accounts for:  
a. The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the  
input is transferred to the output; and  
b. The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the  
next transition, both of which are independent of each other, due to data pin skew, output pattern effects,  
and p-channel to n-channel variation of the output drivers.  
8. tQH = tHP – tQHS, where:  
tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification  
value under the max column.  
{The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye  
will be.}  
Examples:  
a. If the system provides tHP of 1315ps into a DDR2-667 SDRAM, the DRAM provides tQH of 975ps  
(min.)  
b. If the system provides tHP of 1420ps into a DDR2-667 SDRAM, the DRAM provides tQH of 1080ps  
(min.)  
9. RU stands for round up. WR refers to the tWR parameter stored in the MRS.  
10. When the device is operated with input clock jitter, this parameter needs to be derated by the actual  
tERR(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.)  
For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10per) min. = −272ps and  
tERR(6-10per) max. = +293ps, then tDQSCK min.(derated) = tDQSCK min. − tERR(6-10per) max. =  
−400ps − 293ps = −693ps and tDQSCK max.(derated) = tDQSCK max. − tERR(6-10per) min. = 400ps +  
272ps = +672ps. Similarly, tLZ(DQ) for DDR2-667 derates to tLZ(DQ) min.(derated) = −900ps − 293ps =  
−1193ps and tLZ(DQ) max.(derated)= 450ps + 272ps = +722ps.  
11. When the device is operated with input clock jitter, this parameter needs to be derated by the actual  
tJIT(per) of the input clock. (output deratings are relative to the SDRAM input clock.)  
For example, if the measured jitter into a DDR2-667 SDRAM has tJIT(per) min. = −72ps and  
tJIT(per) max. = +93ps, then tRPRE min.(derated) = tRPRE min. + tJIT(per) min. = 0.9 × tCK(avg) − 72ps  
= +2178ps and tRPRE max.(derated) = tRPRE max. + tJIT(per) max. = 1.1 × tCK(avg) + 93ps = +2843ps.  
12. When the device is operated with input clock jitter, this parameter needs to be derated by the actual  
tJIT(duty) of the input clock. (output deratings are relative to the SDRAM input clock.)  
For example, if the measured jitter into a DDR2-667 SDRAM has tJIT(duty) min. = −72ps and  
tJIT(duty) max. = +93ps, then tRPST min.(derated) = tRPST min. + tJIT(duty) min. = 0.4 × tCK(avg) −  
72ps = +928ps and tRPST max.(derated) = tRPST max. + tJIT(duty) max. = 0.6 × tCK(avg) + 93ps =  
+1592ps.  
13. Refer to the Clock Jitter table.  
Preliminary Data Sheet E1028E10 (Ver. 1.0)  
19  
EBE11UD8AHWA  
ODT AC Electrical Characteristics (DDR2 SDRAM Component Specification)  
Parameter  
Symbol  
tAOND  
tAON  
min.  
max.  
Unit  
tCK  
ps  
Notes  
1, 3  
ODT turn-on delay  
2
2
ODT turn-on  
tAC(min)  
tAC(max) + 700  
ODT turn-on (power down mode)  
ODT turn-off delay  
tAONPD  
tAOFD  
tAOF  
tAC(min) + 2000  
2tCK + tAC(max) + 1000  
ps  
2.5  
2.5  
tCK  
ps  
5
ODT turn-off  
tAC(min)  
tAC(max) + 600  
2, 4, 5  
ODT turn-off (power down mode)  
ODT to power down entry latency  
ODT power down exit latency  
tAOFPD  
tANPD  
tAXPD  
tAC(min) + 2000  
2.5tCK + tAC(max) + 1000  
ps  
3
8
3
8
tCK  
tCK  
Notes: 1. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.  
ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND.  
2. ODT turn off time min is when the device starts to turn off ODT resistance.  
ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.  
3. When the device is operated with input clock jitter, this parameter needs to be derated by the actual  
tERR(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.)  
4. When the device is operated with input clock jitter, this parameter needs to be derated by  
{−tJIT(duty) max. − tERR(6-10per) max. } and { −tJIT(duty) min. − tERR(6-10per) min. } of the actual input  
clock.(output deratings are relative to the SDRAM input clock.)  
For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10per) min. = −272ps,  
tERR(6-10per) max. = +293ps, tJIT(duty) min. = −106ps and tJIT(duty) max. = +94ps, then  
tAOF min.(derated) = tAOF min. + { −tJIT(duty) max. − tERR(6-10per) max. } = −450ps + { −94ps − 293ps}  
= −837ps and tAOF max.(derated) = tAOF max. + { −tJIT(duty) min. − tERR(6-10per) min. } = 1050ps +  
{ 106ps + 272ps} = +1428ps.  
5. For tAOFD of DDR2-667/800, the 1/2 clock of nCK in the 2.5 × nCK assumes a tCH(avg), average input  
clock high pulse width of 0.5 relative to tCK(avg). tAOF min. and tAOF max. should each be derated by  
the same amount as the actual amount of tCH(avg) offset present at the DRAM input with respect to 0.5.  
For example, if an input clock has a worst case tCH(avg) of 0.48, the tAOF min. should be derated by  
subtracting 0.02 × tCK(avg) from it, whereas if an input clock has a worst case tCH(avg) of 0.52,  
the tAOF max. should be derated by adding 0.02 × tCK(avg) to it. Therefore, we have;  
tAOF min.(derated) = tAC min. − [0.5 − Min.(0.5, tCH(avg) min.)] × tCK(avg)  
tAOF max.(derated) = tAC max. + 0.6 + [Max.(0.5, tCH(avg) max.) − 0.5] × tCK(avg)  
or  
tAOF min.(derated) = Min.(tAC min., tAC min. − [0.5 − tCH(avg) min.] × tCK(avg))  
tAOF max.(derated) = 0.6 + Max.(tAC max., tAC max. + [tCH(avg) max. − 0.5] × tCK(avg))  
where tCH(avg) min. and tCH(avg) max. are the minimum and maximum of tCH(avg) actually measured  
at the DRAM input balls.  
Preliminary Data Sheet E1028E10 (Ver. 1.0)  
20  
EBE11UD8AHWA  
AC Input Test Conditions (DDR2 SDRAM Component Specification)  
Parameter  
Symbol  
Value  
0.5 × VDDQ  
1.0  
Unit  
V
Notes  
1
Input reference voltage  
VREF  
Input signal maximum peak to peak swing  
Input signal minimum slew rate  
VSWING(max.)  
SLEW  
V
1
1.0  
V/ns  
2, 3  
Notes: 1. Input waveform timing is referenced to the input signal crossing through the VIH/IL (AC) level applied to  
the device under test.  
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(AC) (min.) for  
rising edges and the range from VREF to VIL(AC) (max.) for falling edges as shown in the below figure.  
3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive  
transitions and VIH(AC) to VIL(AC) on the negative transitions.  
VDDQ  
VIH (AC)(min.)  
VIH (DC)(min.)  
VSWING(max.)  
VREF  
VIL (DC)(max.)  
VIL (AC)(max.)  
VSS  
ΔTF  
VREF  
ΔTR  
−
VIL (AC)(max.)  
VIH (AC) min.  
−
VREF  
Falling slew =  
Rising slew =  
ΔTF  
ΔTR  
AC Input Test Signal Wave forms  
Measurement point  
DQ  
VTT  
RT =25 Ω  
Output Load  
Preliminary Data Sheet E1028E10 (Ver. 1.0)  
21  
EBE11UD8AHWA  
Clock Jitter [DDR2-800]  
-8E, -8G  
800  
Frequency (Mbps)  
Parameter  
Symbol  
min.  
max.  
8000  
100  
Unit  
ps  
Notes  
Average clock period  
Clock period jitter  
tCK (avg)  
tJIT (per)  
2500  
−100  
1
5
ps  
Clock period jitter during  
DLL locking period  
tJIT  
(per, lck)  
−80  
⎯
80  
ps  
ps  
ps  
5
6
6
Cycle to cycle period jitter  
tJIT (cc)  
200  
160  
Cycle to cycle clock period jitter during DLL  
locking period  
tJIT (cc, lck)  
⎯
Cumulative error across 2 cycles  
Cumulative error across 3 cycles  
Cumulative error across 4 cycles  
Cumulative error across 5 cycles  
tERR (2per)  
tERR (3per)  
tERR (4per)  
tERR (5per)  
−150  
−175  
−200  
−200  
150  
175  
200  
200  
ps  
ps  
ps  
ps  
7
7
7
7
Cumulative error across  
n=6,7,8,9,10 cycles  
tERR  
(6-10per)  
−300  
−450  
300  
450  
ps  
ps  
7
7
Cumulative error across  
n=11, 12,…49,50 cycles  
tERR  
(11-50per)  
Average high pulse width  
Average low pulse width  
Duty cycle jitter  
tCH (avg)  
tCL (avg)  
tJIT (duty)  
0.48  
0.48  
−100  
0.52  
0.52  
100  
tCK (avg)  
tCK (avg)  
ps  
2
3
4
Notes: 1. tCK (avg) is calculated as the average clock period across any consecutive 200cycle window.  
N
⎧
⎨
⎩
⎫
⎬
⎭
tCK(avg) =  
tCKj  
N
∑
j =1  
N = 200  
2. tCH (avg) is defined as the average high pulse width, as calculated across any consecutive 200 high  
pulses.  
N
⎧
⎨
⎩
⎫
tCH(avg) =  
tCHj (N ×tCK(avg))  
⎬
∑
j =1  
⎭
N = 200  
3. tCL (avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses.  
N
⎧
⎨
⎩
⎫
tCL(avg) =  
tCLj (N × tCK(avg))  
⎬
∑
j =1  
⎭
N = 200  
4. tJIT (duty) is defined as the cumulative set of tCH jitter and tCL jitter. tCH jitter is the largest deviation of  
any single tCH from tCH (avg). tCL jitter is the largest deviation of any single tCL from tCL (avg).  
tJIT (duty) is not subject to production test.  
tJIT (duty) = Min./Max. of {tJIT (CH), tJIT (CL)}, where:  
tJIT (CH) = {tCHj- tCH (avg) where j = 1 to 200}  
tJIT (CL) = {tCLj − tCL (avg) where j = 1 to 200}  
5. tJIT (per) is defined as the largest deviation of any single tCK from tCK (avg).  
tJIT (per) = Min./Max. of { tCKj − tCK (avg) where j = 1 to 200}  
tJIT (per) defines the single period jitter when the DLL is already locked. tJIT (per, lck) uses the same  
definition for single period jitter, during the DLL locking period only. tJIT (per) and tJIT (per, lck) are not  
subject to production test.  
Preliminary Data Sheet E1028E10 (Ver. 1.0)  
22  
EBE11UD8AHWA  
6. tJIT (cc) is defined as the absolute difference in clock period between two consecutive clock cycles:  
tJIT (cc) = Max. of |tCKj+1 − tCKj|  
tJIT (cc) is defines the cycle to cycle jitter when the DLL is already locked. tJIT (cc, lck) uses the same  
definition for cycle to cycle jitter, during the DLL locking period only. tJIT (cc) and tJIT (cc, lck) are not  
subject to production test.  
7. tERR (nper) is defined as the cumulative error across multiple consecutive cycles from tCK (avg).  
tERR (nper) is not subject to production test.  
n
⎧
⎨
⎫
tERR(nper) =  
tCKj − n×tCK(avg))  
⎬
∑
j =1  
⎩
⎭
2 ≤ n ≤ 50 for tERR (nper)  
8. These parameters are specified per their average values, however it is understood that the following  
relationship between the average timing and the absolute instantaneous timing hold at all times.  
(minimum and maximum of spec values are to be used for calculations in the table below.)  
Parameter  
Symbol  
min.  
max.  
Unit  
Absolute clock period  
tCK (abs) tCK (avg) min. + tJIT (per) min. tCK (avg) max. + tJIT (per) max. ps  
Absolute clock high pulse  
width  
tCH (avg) min. × tCK (avg) min. + tCH (avg) max. × tCK (avg) max.  
tCH (abs)  
tCL (abs)  
ps  
ps  
tJIT (duty) min.  
tCL (avg) min. × tCK (avg) min. + tCL (avg) max. × tCK (avg) max.  
tJIT (duty) min. + tJIT (duty) max.  
+ tJIT (duty) max.  
Absolute clock low pulse  
width  
Example: For DDR2-667, tCH(abs) min. = ( 0.48 × 3000 ps ) - 125ps = 1315ps  
Preliminary Data Sheet E1028E10 (Ver. 1.0)  
23  
EBE11UD8AHWA  
Pin Functions  
CK, /CK (input pin)  
The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross  
point of the CK rising edge and the VREF level. When a read operation, DQSs and DQs are referred to the cross  
point of the CK and the /CK. When a write operation, DMs and DQs are referred to the cross point of the DQS and  
the VREF level. DQSs for write operation are referred to the cross point of the CK and the /CK.  
/CS (input pin)  
When /CS is low, commands and data can be input. When /CS is high, all inputs are ignored. However, internal  
operations (bank active, burst operations, etc.) are held.  
/RAS, /CAS, and /WE (input pins)  
These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels.  
See "Command operation".  
A0 to A13 (input pins)  
Row address (AX0 to AX13) is determined by the A0 to the A13 level at the cross point of the CK rising edge and the  
VREF level in a bank active command cycle. Column address (AY0 to AY9) is loaded via the A0 to the A9 at the  
cross point of the CK rising edge and the VREF level in a read or a write command cycle. This column address  
becomes the starting address of a burst operation.  
A10 (AP) (input pin)  
A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If  
A10 = high when a precharge command is issued, all banks are precharged. If A10 = low when a precharge  
command is issued, only the bank that is selected by BA1, BA0 is precharged. If A10 = high when read or write  
command, auto-precharge function is enabled. While A10 = low, auto-precharge function is disabled.  
BA0 and BA1 (input pins)  
BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See  
Bank Select Signal Table)  
[Bank Select Signal Table]  
BA0  
L
BA1  
L
Bank 0  
Bank 1  
H
L
Bank 2  
L
H
Bank 3  
H
H
Remark: H: VIH. L: VIL.  
CKE (input pin)  
CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the  
CKE is driven low and exited when it resumes to high.  
The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge  
and the VREF level with proper setup time tIS, at the next CK rising edge CKE level must be kept with proper hold  
time tIH.  
DQ (input and output pins)  
Data are input to and output from these pins.  
DQS and /DQS (input and output pin)  
DQS and /DQS provide the read data strobes (as output) and the write data strobes (as input).  
Preliminary Data Sheet E1028E10 (Ver. 1.0)  
24  
EBE11UD8AHWA  
DM (input pins)  
DM is the reference signal of the data input mask function. DMs are sampled at the cross point of DQS and /DQS.  
VDD (power supply pins)  
1.8V is applied. (VDD is for the internal circuit.)  
VDDSPD (power supply pin)  
1.8V is applied (For serial EEPROM).  
VSS (power supply pin)  
Ground is connected.  
Detailed Operation Part and Timing Waveforms  
Refer to the EDE5108AHBG, EDE5116AHBG datasheet (E0933E).  
Preliminary Data Sheet E1028E10 (Ver. 1.0)  
25  
EBE11UD8AHWA  
Physical Outline  
Unit: mm  
4.00 max  
0.5 min  
(DATUM -A-)  
Component area  
(Front)  
1
120  
B
A
1.27 ± 0.10  
63.00  
55.00  
133.35  
121  
240  
Component area  
(Back)  
FULL R  
3.00  
Detail A  
Detail B  
1.00  
(DATUM -A-)  
FULL R  
4.00  
2.50  
5.00  
1.50 ± 0.10  
0.80 ± 0.05  
ECA-TS2-0093-01  
Preliminary Data Sheet E1028E10 (Ver. 1.0)  
26  
EBE11UD8AHWA  
CAUTION FOR HANDLING MEMORY MODULES  
When handling or inserting memory modules, be sure not to touch any components on the modules, such as  
the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on  
these components to prevent damaging them.  
In particular, do not push module cover or drop the modules in order to protect from mechanical defects,  
which would be electrical defects.  
When re-packing memory modules, be sure the modules are not touching each other.  
Modules in contact with other modules may cause excessive mechanical stress, which may damage the  
modules.  
MDE0202  
NOTES FOR CMOS DEVICES  
PRECAUTION AGAINST ESD FOR MOS DEVICES  
1
Exposing the MOS devices to a strong electric field can cause destruction of the gate  
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop  
generation of static electricity as much as possible, and quickly dissipate it, when once  
it has occurred. Environmental control must be adequate. When it is dry, humidifier  
should be used. It is recommended to avoid using insulators that easily build static  
electricity. MOS devices must be stored and transported in an anti-static container,  
static shielding bag or conductive material. All test and measurement tools including  
work bench and floor should be grounded. The operator should be grounded using  
wrist strap. MOS devices must not be touched with bare hands. Similar precautions  
need to be taken for PW boards with semiconductor MOS devices on it.  
2
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES  
No connection for CMOS devices input pins can be a cause of malfunction. If no  
connection is provided to the input pins, it is possible that an internal input level may be  
generated due to noise, etc., hence causing malfunction. CMOS devices behave  
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed  
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected  
to VDD or GND with a resistor, if it is considered to have a possibility of being an output  
pin. The unused pins must be handled in accordance with the related specifications.  
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES  
Power-on does not necessarily define initial status of MOS devices. Production process  
of MOS does not define the initial operation status of the device. Immediately after the  
power source is turned ON, the MOS devices with reset function have not yet been  
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or  
contents of registers. MOS devices are not initialized until the reset signal is received.  
Reset operation must be executed immediately after power-on for MOS devices having  
reset function.  
CME0107  
Preliminary Data Sheet E1028E10 (Ver. 1.0)  
27  
EBE11UD8AHWA  
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.  
No part of this document may be copied or reproduced in any form or by any means without the prior  
written consent of Elpida Memory, Inc.  
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights  
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or  
third parties by or arising from the use of the products or information listed in this document. No license,  
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property  
rights of Elpida Memory, Inc. or others.  
Descriptions of circuits, software and other related information in this document are provided for  
illustrative purposes in semiconductor product operation and application examples. The incorporation of  
these circuits, software and information in the design of the customer's equipment shall be done under  
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses  
incurred by customers or third parties arising from the use of these circuits, software and information.  
[Product applications]  
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.  
However, users are instructed to contact Elpida Memory's sales office before using the product in  
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,  
medical equipment for life support, or other such application in which especially high quality and  
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk  
of bodily injury.  
[Product usage]  
Design your application so that the product is used within the ranges and conditions guaranteed by  
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation  
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no  
responsibility for failure or damage when the product is used beyond the guaranteed ranges and  
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure  
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so  
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other  
consequential damage due to the operation of the Elpida Memory, Inc. product.  
[Usage environment]  
This product is not designed to be resistant to electromagnetic waves or radiation. This product must be  
used in a non-condensing environment.  
If you export the products or technology described in this document that are controlled by the Foreign  
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance  
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by  
U.S. export control regulations, or another country's export control laws or regulations, you must follow  
the necessary procedures in accordance with such laws or regulations.  
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted  
license to use these products, that third party must be made aware that they are responsible for  
compliance with the relevant laws and regulations.  
M01E0107  
Preliminary Data Sheet E1028E10 (Ver. 1.0)  
28  

相关型号：

SI9130DB

 5- and 3.3-V Step-Down Synchronous Converters

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135LG-T1

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135LG-T1-E3

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135_11

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9136_11

 Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130CG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130LG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130_11

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137LG

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9122E

 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明