EDD1216AASE-7A-E_技术文档

PRELIMINARY DATA SHEET

128M bits DDR SDRAM

EDD1216AASE (8M words × 16 bits)

Description

Pin Configurations

The EDD1216AASE is a 128M bits Double Data Rate

(DDR) SDRAM organized as 2,097,154 words × 16 bits

× 4 banks. Read and write operations are performed at

the cross points of the CK and the /CK. This high-

speed data transfer is realized by the 2 bits prefetch-

pipelined architecture. Data strobe (DQS) both for

read and write are available for high speed and reliable

data bus design. By setting extended mode register,

the on-chip Delay Locked Loop (DLL) can be set

enable or disable. It is packaged in 60-ball FBGA

(µBGA^) package.

/xxx indicates active low signal.

60-ball FBGA ( BGA)

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

VSSQ DQ15 VSS

DQ14 VDDQ DQ13

DQ12 VSSQ DQ11

DQ10 VDDQ DQ9

DQ8 VSSQ UDQS

VREF VSS UDM

VDD DQ0 VDDQ

DQ2 VSSQ DQ1

DQ4 VDDQ DQ3

DQ6 VSSQ DQ5

LDQS VDDQ DQ7

Features

• Power supply : VDDQ = 2.5V ± 0.2V

: VDD = 2.5V ± 0.2V

• Data rate: 333Mbps/266Mbps (max.)

LDM VDD

/WE /CAS

/RAS /CS

BA1 BA0

NC

G

H

J

CK

NC

A11

A8

/CK

CKE

A9

• Double Data Rate architecture; two data transfers per

clock cycle

• Bi-directional, data strobe (DQS) is transmitted

/received with data, to be used in capturing data at

the receiver

K

L

A7

A0

A2

A10

(AP)

• Data inputs, outputs, and DM are synchronized with

DQS

A6

A5

A1

A3

• 4 internal banks for concurrent operation

M

• DQS is edge aligned with data for READs; center

A4

VSS

VDD

aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

(Top view)

Address inputs

• DLL aligns DQ and DQS transitions with CK

A0 to A11

transitions

BA0, BA1

DQ0 to DQ15

UQQS/LDQS

/CS

/RAS

/CAS

/WE

UDM/LDM

CK

/CK

CKE

VREF

VDD

VSS

VDDQ

VSSQ

NC

Bank select address

Data-input/output

Input and output data strobe

Chip select

Row address strobe

Column address strobe

Write enable

Input mask

Clock input

Differential clock input

Clock enable

Input reference voltage

Power for internal circuit

Ground for internal circuit

Power for DQ circuit

Ground for DQ circuit

No connection

• Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

• Data mask (DM) for write data

• Auto precharge option for each burst access

• SSTL_2 compatible I/O

• Programmable burst length (BL): 2, 4, 8

• Programmable /CAS latency (CL): 2, 2.5

• Programmable output driver strength: normal/weak

• Refresh cycles: 4096 refresh cycles/64ms

15.6µs maximum average periodic refresh interval

• 2 variations of refresh

Auto refresh

Self refresh

• FBGA (µBGA) package with lead free solder

(Sn-Ag-Cu)

Document No. E0614E20 (Ver. 2.0)

Date Published March 2005 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2004-2005

EDD1216AASE

Ordering Information

Mask

version

Organization

(words × bits)

Internal

banks

Data rate

Mbps (max.)

JEDEC speed bin

(CL-tRCD-tRP)

Part number

Package

EDD1216AASE-6B-E

EDD1216AASE-7A-E

333

266

DDR-333B (2.5-3-3)

DDR-266A (2-3-3)

60-ball FBGA

(µBGA)

A

8M × 16

4

Part Number

E D D 12 16 A A SE - 6B - E

Elpida Memory

Type

D: Monolithic Device

Product Code

D: DDR SDRAM

Environment Code

E: Lead Free

Density / Bank

12: 128M / 4-bank

Speed

6B: DDR333B (2.5-3-3)

7A: DDR266A (2-3-3)

Bit Organization

16: x16

Voltage, Interface

A: 2.5V, SSTL_2

Package

SE: FBGA (µBGA with back cover)

Die Rev.

Preliminary Data Sheet E0614E20 (Ver. 2.0)

2

EDD1216AASE

CONTENTS

Description.....................................................................................................................................................1

Features.........................................................................................................................................................1

Pin Configurations .........................................................................................................................................1

Ordering Information......................................................................................................................................2

Part Number ..................................................................................................................................................2

Electrical Specifications.................................................................................................................................4

Block Diagram .............................................................................................................................................10

Pin Function.................................................................................................................................................11

Command Operation ...................................................................................................................................13

Simplified State Diagram.............................................................................................................................20

Operation of the DDR SDRAM....................................................................................................................21

Timing Waveforms.......................................................................................................................................40

Package Drawing ........................................................................................................................................46

Recommended Soldering Conditions..........................................................................................................47

Preliminary Data Sheet E0614E20 (Ver. 2.0)

3

EDD1216AASE

Electrical Specifications

• All voltages are referenced to VSS (GND).

• After power up, wait more than 200 µs and then, execute power on sequence and CBR (Auto) refresh before

proper device operation is achieved.

Absolute Maximum Ratings

Parameter

Symbol

VT

Rating

Unit

V

Note

Voltage on any pin relative to VSS

Supply voltage relative to VSS

Short circuit output current

Power dissipation

–1.0 to +3.6

50

VDD

IOS

PD

V

mA

W

1.0

Operating ambient temperature

Storage temperature

TA

0 to +70

–55 to +125

°C

Tstg

Caution

Exposing the device to stress above those listed in Absolute Maximum Ratings could cause

permanent damage. The device is not meant to be operated under conditions outside the limits

described in the operational section of this specification. Exposure to Absolute Maximum Rating

conditions for extended periods may affect device reliability.

Recommended Operating Conditions (TA = 0 to +70°C)

Parameter

Symbol

min.

2.3

typ.

2.5

max.

2.7

Unit

V

Notes

1

VDD,

VDDQ

Supply voltage

VSS,

VSSQ

0

V

Input reference voltage

Termination voltage

Input high voltage

Input low voltage

VREF

0.49 × VDDQ

VREF – 0.04

VREF + 0.15

–0.3

0.50 × VDDQ 0.51 × VDDQ

V

VTT

VREF

—

VREF + 0.04

VDDQ + 0.3

VREF – 0.15

VIH (DC)

VIL (DC)

2

3

—

Input voltage level,

VIN (DC)

VIX (DC)

VID (DC)

–0.3

—

VDDQ + 0.3

V

4

CK and /CK inputs

Input differential cross point

voltage, CK and /CK inputs

Input differential voltage,

CK and /CK inputs

0.5 × VDDQ − 0.2V 0.5 × VDDQ

0.36

0.5 × VDDQ + 0.2V

VDDQ + 0.6

—

5, 6

Notes: 1. VDDQ must be lower than or equal to VDD.

2. VIH is allowed to exceed VDD up to 3.6V for the period shorter than or equal to 5ns.

3. VIL is allowed to outreach below VSS down to –1.0V for the period shorter than or equal to 5ns.

4. VIN (DC) specifies the allowable DC execution of each differential input.

5. VID (DC) specifies the input differential voltage required for switching.

6. VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF – 0.18V if measurement.

Preliminary Data Sheet E0614E20 (Ver. 2.0)

4

EDD1216AASE

DC Characteristics 1 (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)

Parameter

Symbol

Grade

max.

110

Unit

mA

Test condition

Notes

1, 2, 9

CKE ≥ VIH,

tRC = tRC (min.)

Operating current (ACT-PRE) IDD0

CKE ≥ VIH, BL = 4,

Operating current

IDD1

140

mA

CL = 2.5,

1, 2, 5

(ACT-READ-PRE)

tRC = tRC (min.)

Idle power down standby

IDD2P

current

3

mA

CKE ≤ VIL

4

CKE ≥ VIH, /CS ≥ VIH

DQ, DQS, DM = VREF

CKE ≥ VIH, /CS ≥ VIH

DQ, DQS, DM = VREF

Floating idle standby current

IDD2F

IDD2Q

IDD3P

IDD3N

IDD4R

IDD4W

IDD5

35

4, 5

Quiet idle standby current

30

4, 10

3

Active power down standby

current

20

CKE ≤ VIL

CKE ≥ VIH, /CS ≥ VIH

tRAS = tRAS (max.)

CKE ≥ VIH, BL = 2,

CL = 2.5

CKE ≥ VIH, BL = 2,

CL = 2.5

tRFC = tRFC (min.),

Input ≤ VIL or ≥ VIH

Active standby current

55

3, 5, 6

1, 2, 5, 6

Operating current

(Burst read operation)

Operating current

(Burst write operation)

205

200

3

Auto Refresh current

Input ≥ VDD – 0.2 V

Input ≤ 0.2 V

Self refresh current

IDD6

Operating current

(4 banks interleaving)

IDD7A

350

BL = 4

1, 5, 6, 7

Notes: 1. These IDD data are measured under condition that DQ pins are not connected.

2. One bank operation.

3. One bank active.

4. All banks idle.

5. Command/Address transition once per one clock cycle.

6. DQ, DM and DQS transition twice per one clock cycle.

7. 4 banks active. Only one bank is running at tRC = tRC (min.)

8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.

9. Command/Address transition once every two clock cycle.

10. Command/Address stable at ≥ VIH or ≤ VIL.

DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)

Parameter

Symbol

ILI

min.

–2

max.

2

Unit

µA

Test condition

Note

Input leakage current

Output leakage current

Output high current

Output low current

VDD ≥ VIN ≥ VSS

VDDQ ≥ VOUT ≥ VSS

VOUT = 1.95V

ILO

–5

5

µA

IOH

IOL

–15.2

15.2

—

mA

VOUT = 0.35V

Preliminary Data Sheet E0614E20 (Ver. 2.0)

5

EDD1216AASE

Pin Capacitance (TA = +25°C, VDD, VDDQ = 2.5V ± 0.2V)

Parameter

Symbol

CI1

Pins

min.

1.5

—

typ.

—

max.

3.0

Unit

pF

Notes

Input capacitance

CK, /CK

1

CI2

All other input pins

CK, /CK

3.0

1

Delta input capacitance

Cdi1

Cdi2

CI/O

Cdio

0.25

0.5

1

All other input-only pins

DQ, DM, DQS

—

1

Data input/output capacitance

Delta input/output capacitance

3.0

—

4.8

1, 2,

1

0.6

Notes: 1. These parameters are measured on conditions: f = 100MHz, VOUT = VDDQ/2, ∆VOUT = 0.2V,

TA = +25°C.

2. DOUT circuits are disabled.

AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)

-6B

-7A

Parameter

Clock cycle time

(CL = 2)

Symbol

tCK

min.

max.

12

min.

max.

12

Unit

ns

Notes

10

7.5

(CL = 2.5)

tCK

tCH

tCL

6

12

7.5

12

ns

CK high-level width

CK low-level width

0.45

0.55

0.45

0.55

tCK

min

CK half period

tHP

tAC

—

tCK

ns

(tCH, tCL)

DQ output access time from

CK, /CK

–0.7

0.7

–0.75

0.75

2, 11

DQS output access time from CK, /CK

tDQSCK –0.6

0.6

–0.75

—

0.75

0.5

ns

2, 11

3

DQS to DQ skew

tDQSQ

tQH

—

0.45

DQ/DQS output hold time from DQS

Data hold skew factor

tHP – tQHS —

tQHS

—

0.55

—

0.75

Data-out high-impedance time from CK,

/CK

Data-out low-impedance time from CK, /CK tLZ

tHZ

–0.7

0.7

–0.75

0.75

ns

5, 11

6, 11

–0.7

0.9

0.7

1.1

0.6

—

–0.75

0.9

0.75

1.1

0.6

—

ns

Read preamble

tRPRE

tCK

ns

Read postamble

tRPST

tDS

0.4

DQ and DM input setup time

DQ and DM input hold time

DQ and DM input pulse width

Write preamble setup time

Write preamble

0.45

1.75

0

0.5

8

7

tDH

—

0.5

—

ns

tDIPW

tWPRES

tWPRE

tWPST

—

1.75

0

—

ns

—

ns

0.25

0.4

—

0.25

0.4

—

tCK

Write postamble

0.6

9

Write command to first DQS latching

transition

tDQSS

0.75

1.25

0.75

1.25

tCK

DQS falling edge to CK setup time

DQS falling edge hold time from CK

DQS input high pulse width

tDSS

tDSH

tDQSH

tDQSL

tIS

0.2

—

0.2

—

tCK

ns

0.2

0.35

0.75

0.35

0.9

DQS input low pulse width

Address and control input setup time

Address and control input hold time

8

tIH

0.9

ns

Preliminary Data Sheet E0614E20 (Ver. 2.0)

6

EDD1216AASE

-6B

-7A

Parameter

Symbol

tIPW

min.

2.2

2

max.

—

min.

2.2

2

max.

—

Unit

ns

Notes

7

Address and control input pulse width

Mode register set command cycle time

Active to Precharge command period

tMRD

tRAS

—

tCK

ns

42

120000

45

120000

Active to Active/Auto refresh command

tRC

60

72

—

67.5

75

—

ns

period

Auto refresh to Active/Auto refresh

command period

tRFC

Active to Read/Write delay

Precharge to active command period

Active to Autoprecharge delay

Active to active command period

Write recovery time

tRCD

tRP

18

—

20

—

ns

18

20

tRAP

tRRD

tWR

tRCD min.

12

15

Auto precharge write recovery and

precharge time

(tWR/tCK)+

(tRP/tCK)

(tWR/tCK)+

(tRP/tCK)

tDAL

—

tCK

13

Internal write to Read command delay

tWTR

tREF

1

—

1

—

tCK

µs

Average periodic refresh interval

—

15.6

—

15.6

Notes: 1. On all AC measurements, we assume the test conditions shown in the next page. For timing parameter

definitions, see ‘Timing Waveforms’ section.

2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal

transition is defined to occur when the signal level crossing VTT.

3. The timing reference level is VTT.

4. Output valid window is defined to be the period between two successive transition of data out or DQS

(read) signals. The signal transition is defined to occur when the signal level crossing VTT.

5. tHZ is defined as DOUT transition delay from Low-Z to High-Z at the end of read burst operation. The

timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage

level, but specify when the device output stops driving.

6. tLZ is defined as DOUT transition delay from High-Z to Low-Z at the beginning of read operation. This

parameter is not referred to a specific DOUT voltage level, but specify when the device output begins

driving.

7. Input valid windows is defined to be the period between two successive transition of data input or DQS

(write) signals. The signal transition is defined to occur when the signal level crossing VREF.

8. The timing reference level is VREF.

9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific

reference voltage to judge this transition is not given.

10. tCK (max.) is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not

assured.

11. tCK = tCK (min) when these parameters are measured. Otherwise, absolute minimum values of these

values are 10% of tCK.

12. VDD is assumed to be 2.5V ± 0.2V. VDD power supply variation per cycle expected to be less than

0.4V/400 cycle.

13. tDAL = (tWR/tCK)+(tRP/tCK)

For each of the terms above, if not already an integer, round to the next highest integer.

Example: For –7A Speed at CL = 2.5, tCK = 7.5ns, tWR = 15ns and tRP= 20ns,

tDAL = (15ns/7.5ns) + (20ns/7.5ns) = (2) + (3)

tDAL = 5 clocks

Preliminary Data Sheet E0614E20 (Ver. 2.0)

7

EDD1216AASE

Test Conditions

Parameter

Symbol

VREF

Value

Unit

V

Input reference voltage

Termination voltage

Input high voltage

Input low voltage

VDDQ/2

VREF

VTT

V

VIH (AC)

VIL (AC)

VREF + 0.31

VREF − 0.31

V

Input differential voltage, CK and /CK

inputs

VID (AC)

0.62

V

Input differential cross point voltage,

CK and /CK inputs

Input signal slew rate

VIX (AC)

SLEW

VREF

1

V

V/ns

tCK

VDD

VREF

VSS

CK

VID

/CK

tCL

tCH

VIX

VDD

VIH

VREF

VIL

VSS

∆t

SLEW = (VIH (AC) – VIL (AC))/∆t

VTT

Measurement point

DQ

RT = 50Ω

CL = 30pF

Input Waveforms and Output Load

Preliminary Data Sheet E0614E20 (Ver. 2.0)

8

EDD1216AASE

Timing Parameter Measured in Clock Cycle

Number of clock cycle

6ns

tCK

7.5ns

Parameter

Symbol

tWPD

tRPD

min.

max.

—

min.

max.

—

Unit

tCK

Write to pre-charge command delay (same bank)

Read to pre-charge command delay (same bank)

Write to read command delay (to input all data)

4 + BL/2

BL/2

3 + BL/2

BL/2

—

tWRD

2 + BL/2

—

2 + BL/2

—

Burst stop command to write command delay

(CL = 2)

(CL = 2.5)

Burst stop command to DQ High-Z

(CL = 2)

(CL = 2.5)

tBSTW

tBSTZ

—

3

—

2.5

2

—

2

tCK

3

—

2.5

2

2.5

Read command to write command delay

(to output all data)

(CL = 2)

tRWD

—

2 + BL/2

—

tCK

(CL = 2.5)

Pre-charge command to High-Z

(CL = 2)

tRWD

tHZP

3 + BL/2

—

3 + BL/2

2

—

2

tCK

(CL = 2.5)

tHZP

2.5

1

2.5

1

2.5

1

2.5

1

tCK

Write command to data in latency

Write recovery

tWCD

tWR

3

—

0

2

—

0

DM to data in latency

tDMD

tMRD

tSNR

tSRD

tPDEN

tPDEX

0

Mode register set command cycle time

Self refresh exit to non-read command

Self refresh exit to read command

Power down entry

2

—

1

2

—

1

12

200

1

10

200

1

Power down exit to command input

1

—

1

—

Preliminary Data Sheet E0614E20 (Ver. 2.0)

9

EDD1216AASE

Block Diagram

CK

/CK

CKE

Bank 3

Bank 2

Bank 1

A0 to A11, BA0, BA1

Row

address

buffer

and

Memory cell array

Bank 0

refresh

counter

Mode

register

Sense amp.

Column decoder

Column

address

buffer

and

/CS

/RAS

/CAS

/WE

burst

counter

Data control circuit

Latch circuit

DQS

DM

DLL

Input & Output buffer

CK, /CK

DQ

Preliminary Data Sheet E0614E20 (Ver. 2.0)

10

EDD1216AASE

Pin Function

CK, /CK (input pins)

The CK and the /CK are the master clock inputs. All inputs except DM, DQS and DQs are referred to the cross point

of the CK rising edge and the /CK falling edge. When a read operation, DQS and DQs are referred to the cross point

of the CK and the /CK. When a write operation, DQS and DQs are referred to the cross point of the DQS and the

VREF level. DQS for write operation is referred to the cross point of the CK and the /CK. CK is the master clock

input to this pin. The other input signals are referred at CK rising edge.

/CS (input pin)

When /CS is Low, commands and data can be input. When /CS is High, all inputs are ignored. However, internal

operations (bank active, burst operations, etc.) are held.

/RAS, /CAS, and /WE (input pins)

These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels.

See "Command operation".

A0 toA11 (input pins)

Row address (AX0 to AX11) is determined by the A0 to the A11 level at the cross point of the CK rising edge and the

/CK falling edge in a bank active command cycle. Column address (See “Address Pins Table”) is loaded via the A0

to the A8 at the cross point of the CK rising edge and the /CK falling edge in a read or a write command cycle. This

column address becomes the starting address of a burst operation.

[Address Pins Table]

Address (A0 to A11)

Part number

Row address

AX0 to AX11

Column address

AY0 to AY8

EDD1216AASE

A10 (AP) (input pin)

A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If

A10 = High when a precharge command is issued, all banks are precharged. If A10 = Low when a precharge

command is issued, only the bank that is selected by BA1/BA0 is precharged. If A10 = High when read or write

command, auto-precharge function is enabled. While A10 = Low, auto-precharge function is disabled.

BA0 and BA1 (input pins)

BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See

Bank Select Signal Table)

[Bank Select Signal Table]

BA0

L

BA1

L

Bank 0

Bank 1

H

L

Bank 2

L

H

Bank 3

H

Remark: H: VIH. L: VIL.

Preliminary Data Sheet E0614E20 (Ver. 2.0)

11

EDD1216AASE

CKE (input pin)

This pin determines whether or not the next CK is valid. If CKE is High, the next CK rising edge is valid. If CKE is

Low. CKE controls power down and self-refresh. The power down and the self-refresh commands are entered

when the CKE is driven Low and exited when it resumes to High. CKE must be maintained high throughout read or

write access.

The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge

and the /CK falling edge with proper setup time tIS, by the next CK rising edge CKE level must be kept with proper

hold time tIH.

UDM, LDM (input pin)

DMs are the reference signals of the data input mask function. DMs are sampled at the cross point of DQS and

VREF. DMs provide the byte mask function. In × 16 products, LDM controls the lower byte (DQ0 to DQ7) and UDM

controls the upper byte (DQ8 to DQ15) of write data. When DM = High, the data input at the same timing are

masked while the internal burst counter will be count up.

DQ0 toDQ15 (input/output pins)

Data is input to and output from these pins.

UDQS, LDQS (input and output pin)

DQS provide the read data strobes (as output) and the write data strobes (as input). In ×16 products, LDQS is the

lower byte (DQ0 to DQ7) data strobe signal, UDQS is the upper byte (DQ8 to DQ15) data strobe signal.

VDD, VSS, VDDQ, VSSQ (Power supply)

VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output

buffers.

Preliminary Data Sheet E0614E20 (Ver. 2.0)

12

EDD1216AASE

Command Operation

Command Truth Table

DDR SDRAM recognize the following commands specified by the /CS, /RAS, /CAS, /WE and address pins. All other

combinations than those in the table below are illegal.

CKE

Command

Symbol

DESL

NOP

n – 1

H

n

/CS /RAS /CAS /WE BA1 BA0 AP

Address

Ignore command

H

L

H

L

×

H

L

×

H

L

×

V

×

L

×

V

×

L

×

L

H

L

H

V

L

H

×

L

×

V

×

V

No operation

H

L

Burst stop in read command

Column address and read command

Read with auto-precharge

Column address and write command

Write with auto-precharge

Row address strobe and bank active

Precharge select bank

Precharge all bank

BST

H

READ

READA

WRIT

WRITA

ACT

H

L

H

L

H

L

H

L

H

L

H

L

PRE

H

L

PALL

REF

H

L

Refresh

H

L

H

L

SELF

MRS

H

L

Mode register set

H

L

EMRS

H

L

H

Remark: H: VIH. L: VIL. ×: VIH or VIL V: Valid address input

Note: The CKE level must be kept for 1 CK cycle at least.

Ignore command [DESL]

When /CS is High at the cross point of the CK rising edge and the VREF level, every input are neglected and internal

status is held.

No operation [NOP]

As long as this command is input at the cross point of the CK rising edge and the VREF level, address and data

input are neglected and internal status is held.

Burst stop in read operation [BST]

This command stops a burst read operation, which is not applicable for a burst write operation.

Column address strobe and read command [READ]

This command starts a read operation. The start address of the burst read is determined by the column address

(See “Address Pins Table” in Pin Function) and the bank select address. After the completion of the read operation,

the output buffer becomes High-Z.

Read with auto-precharge [READA]

This command starts a read operation. After completion of the read operation, precharge is automatically executed.

Column address strobe and write command [WRIT]

This command starts a write operation. The start address of the burst write is determined by the column address

(See “Address Pins Table” in Pin Function) and the bank select address.

Write with auto-precharge [WRITA]

This command starts a write operation. After completion of the write operation, precharge is automatically executed.

Preliminary Data Sheet E0614E20 (Ver. 2.0)

13

EDD1216AASE

Row address strobe and bank activate [ACT]

This command activates the bank that is selected by BA0, BA1 and determines the row address (AX0 to AX11).

(See Bank Select Signal Table)

Precharge selected bank [PRE]

This command starts precharge operation for the bank selected by BA0, BA1. (See Bank Select Signal Table)

[Bank Select Signal Table]

BA0

L

BA1

L

Bank 0

Bank 1

H

L

Bank 2

L

H

Bank 3

H

Remark: H: VIH. L: VIL.

Precharge all banks [PALL]

This command starts a precharge operation for all banks.

Refresh [REF/SELF]

This command starts a refresh operation. There are two types of refresh operation, one is auto-refresh, and another

is self-refresh. For details, refer to the CKE truth table section.

Mode register set/Extended mode register set [MRS/EMRS]

The DDR SDRAM has the two mode registers, the mode register and the extended mode register, to defines how it

works. The both mode registers are set through the address pins (the A0 to the A11, BA0 to BA1) in the mode

register set cycle. For details, refer to "Mode register and extended mode register set".

CKE Truth Table

CKE

Current state

Command

n – 1

H

n

/CS

L

/RAS /CAS /WE

Address

Notes

Idle

Auto-refresh command (REF)

Self-refresh entry (SELF)

Power down entry (PDEN)

H

L

H

×

2

H

L

H

L

H

×

H

×

H

L

H

L

Self refresh

Power down

Self refresh exit (SELFX)

Power down exit (PDEX)

L

H

×

H

×

H

×

L

H

L

H

×

H

×

H

×

L

H

Remark: H: VIH. L: VIL. ×: VIH or VIL.

Notes: 1. All the banks must be in IDLE before executing this command.

2. The CKE level must be kept for 1 CK cycle at least.

Preliminary Data Sheet E0614E20 (Ver. 2.0)

14

EDD1216AASE

Function Truth Table

The following tables show the operations that are performed when each command is issued in each state of the

DDR SDRAM.

Current state

Precharging*¹

/CS

H

L

/RAS /CAS /WE Address

Command

DESL

Operation

NOP

Next state

ldle

—

×

H

L

H

L

H

L

×

NOP

L

×

BST

ILLEGAL*¹¹

NOP

L

H

L

BA, CA, A10

BA, RA

BA, A10

×

READ/READA

WRIT/WRITA

ACT

—

L

—

L

H

L

H

L

—

L

PRE, PALL

ldle

—

L

×

ILLEGAL

NOP

Idle*²

H

L

×

DESL

ldle

—

H

L

H

L

H

L

×

NOP

L

×

BST

ILLEGAL*¹¹

Activating

NOP

L

H

L

BA, CA, A10

BA, RA

BA, A10

READ/READA

WRIT/WRITA

ACT

—

L

—

L

H

L

Active

ldle

L

PRE, PALL

Refresh/

ldle/

L

H

L

×

L

×

H

L

×

REF, SELF

MRS

Self refresh*¹²

Self refresh

MODE

Mode register set*¹²

ldle

Refresh

×

DESL

NOP

ldle

(auto-refresh)*³

L

H

L

H

L

H

L

H

L

H

L

×

NOP

BST

NOP

ldle

—

×

ILLEGAL

NOP

×

—

×

—

Activating*⁴

×

DESL

Active

—

H

L

H

L

H

L

×

NOP

×

BST

ILLEGAL*¹¹

ILLEGAL

NOP

H

L

BA, CA, A10

READ/READA

WRIT/WRITA

ACT

—

L

BA, CA, A10

—

H

L

H

L

BA, RA

—

L

BA, A10

PRE, PALL

—

L

×

—

Active*⁵

×

DESL

Active

H

L

H

L

×

NOP

×

BST

ILLEGAL

H

BA, CA, A10

READ/READA

Starting read operation Read/READA

Write

Starting write operation recovering/

precharging

L

H

L

BA, CA, A10

WRIT/WRITA

L

H

L

H

L

BA, RA

BA, A10

×

ACT

ILLEGAL*¹¹

Pre-charge

ILLEGAL

—

PRE, PALL

Idle

—

×

Preliminary Data Sheet E0614E20 (Ver. 2.0)

15

EDD1216AASE

Current state

Read*⁶

/CS

H

/RAS /CAS /WE Address

Command

DESL

NOP

Operation

NOP

Next state

Active

×

H

L

×

L

H

NOP

Active

L

BST

Active

Interrupting burst read

operation to

L

H

L

H

BA, CA, A10

READ/READA

Active

start new read

L

H

L

BA, CA, A10

BA, RA

WRIT/WRITA

ACT

ILLEGAL*¹³

ILLEGAL*¹¹

—

H

Interrupting burst

read operation to

start pre-charge

L

H

L

BA, A10

PRE, PALL

Precharging

L

×

ILLEGAL

—

Read with auto-pre-

charge*⁷

H

×

DESL

NOP

Precharging

L

H

L

H

L

H

L

×

NOP

Precharging

×

BST

ILLEGAL

—

H

L

BA, CA, A10

BA, RA

BA, A10

×

READ/READA

WRIT/WRITA

ACT

ILLEGAL*¹⁴

ILLEGAL*^{11, 14}

ILLEGAL

L

H

L

H

L

PRE, PALL

L

×

Write

recovering

Write*⁸

H

×

DESL

NOP

Write

L

H

L

×

NOP

BST

NOP

recovering

ILLEGAL

—

Interrupting burst write

operation to

L

H

L

H

BA, CA, A10

READ/READA

Read/ReadA

start read operation.

Interrupting burst write

operation to

L

H

L

WRIT/WRITA

Write/WriteA

start new write

operation.

L

H

L

BA, RA

ACT

ILLEGAL*¹¹

—

Interrupting write

operation to start pre-

charge.

BA, A10

PRE, PALL

Idle

L

H

L

×

ILLEGAL

—

Write recovering*⁹

×

DESL

NOP

Active

—

H

L

H

L

×

NOP

×

BST

ILLEGAL

H

BA, CA, A10

READ/READA

Starting read operation. Read/ReadA

Starting new write

Write/WriteA

operation.

L

H

L

BA, CA, A10

WRIT/WRITA

L

H

L

H

L

BA, RA

BA, A10

×

ACT

ILLEGAL*¹¹

ILLEGAL

—

PRE/PALL

×

Preliminary Data Sheet E0614E20 (Ver. 2.0)

16

EDD1216AASE

Current state

/CS

H

/RAS /CAS /WE Address

Command

DESL

Operation

NOP

Next state

Write with auto-

×

Precharging

pre-charge*¹⁰

L

H

L

H

L

H

L

×

NOP

Precharging

×

BST

ILLEGAL

—

H

L

BA, CA, A10

BA, RA

BA, A10

×

READ/READA

WRIT/WRIT A

ACT

ILLEGAL*¹⁴

ILLEGAL*^{11, 14}

ILLEGAL

L

H

L

H

L

PRE, PALL

L

×

Remark: H: VIH. L: VIL. ×: VIH or VIL

Notes: 1. The DDR SDRAM is in "Precharging" state for tRP after precharge command is issued.

2. The DDR SDRAM reaches "IDLE" state tRP after precharge command is issued.

3. The DDR SDRAM is in "Refresh" state for tRFC after auto-refresh command is issued.

4. The DDR SDRAM is in "Activating" state for tRCD after ACT command is issued.

5. The DDR SDRAM is in "Active" state after "Activating" is completed.

6. The DDR SDRAM is in "READ" state until burst data have been output and DQ output circuits are turned

off.

7. The DDR SDRAM is in "READ with auto-precharge" from READA command until burst data has been

output and DQ output circuits are turned off.

8. The DDR SDRAM is in "WRITE" state from WRIT command to the last burst data are input.

9. The DDR SDRAM is in "Write recovering" for tWR after the last data are input.

10. The DDR SDRAM is in "Write with auto-precharge" until tWR after the last data has been input.

11. This command may be issued for other banks, depending on the state of the banks.

12. All banks must be in "IDLE".

13. Before executing a write command to stop the preceding burst read operation, BST command must be

issued.

14. The DDR SDRAM supports the concurrent auto-precharge feature, a read with auto-precharge enabled,or

a write with auto-precharge enabled, may be followed by any column command to other banks, as long as

that command does not interrupt the read or write data transfer, and all other related limitations apply.

(E.g. Conflict between READ data and WRITE data must be avoided.)

The minimum delay from a read or write command with auto precharge enabled, to a command to a

different bank, is summarized below.

To command (different bank, non-

interrupting command)

Minimum delay

From command

Read w/AP

(Concurrent AP supported)

Units

tCK

Read or Read w/AP

Write or Write w/AP

Precharge or Activate

Read or Read w/AP

Write or Write w/AP

Precharge or Activate

BL/2

CL(rounded up)+ (BL/2)

1

Write w/AP

1 + (BL/2) + tWTR

BL/2

1

Preliminary Data Sheet E0614E20 (Ver. 2.0)

17

EDD1216AASE

Command Truth Table for CKE

Current State

CKE

n – 1 n

/CS /RAS /CAS /WE Address

Operation

Notes

Self refresh

H

L

×

H

L

×

H

L

H

L

×

H

L

×

H

L

H

L

×

H

L

×

H

L

×

H

L

×

H

×

H

L

×

H

L

×

H

L

×

H

L

×

H

L

×

H

×

H

L

×

H

L

×

H

×

H

L

×

H

L

×

INVALID, CK (n-1) would exit self refresh

Self refresh recovery

ILLEGAL

H

L

ILLEGAL

L

Maintain self refresh

Idle after tRC

Self refresh recovery

H

L

H

L

Idle after tRC

ILLEGAL

L

ILLEGAL

L

ILLEGAL

L

ILLEGAL

Power down

All banks idle

×

INVALID, CK (n – 1) would exit power down

EXIT power down → Idle

H

L

×

L

Maintain power down mode

H

L

H

L

Refer to operations in Function Truth Table

CBR (auto) refresh

×

OPCODE Refer to operations in Function Truth Table

Refer to operations in Function Truth Table

L

×

Self refresh

1

L

OPCODE Refer to operations in Function Truth Table

×

Power down

Row active

H

L

×

Refer to operations in Function Truth Table

Power down

×

Remark: H: VIH. L: VIL. ×: VIH or VIL

Note: Self refresh can be entered only from the all banks idle state. Power down can be entered only from all

banks idle or row active state.

Preliminary Data Sheet E0614E20 (Ver. 2.0)

18

EDD1216AASE

Auto-refresh command [REF]

This command executes auto-refresh. The banks and the ROW addresses to be refreshed are internally determined

by the internal refresh controller. The average refresh cycle is 15.6 µs. The output buffer becomes High-Z after

auto-refresh start. Precharge has been completed automatically after the auto-refresh. The ACT or MRS command

can be issued tRFC after the last auto-refresh command.

Self-refresh entry [SELF]

This command starts self-refresh. The self-refresh operation continues as long as CKE is held Low. During the self-

refresh operation, all ROW addresses are repeated refreshing by the internal refresh controller. A self-refresh is

terminated by a self-refresh exit command.

Power down mode entry [PDEN]

tPDEN (= 1 cycle) after the cycle when [PDEN] is issued. The DDR SDRAM enters into power-down mode. In

power down mode, power consumption is suppressed by deactivating the input initial circuit. Power down mode

continues while CKE is held Low. No internal refresh operation occurs during the power down mode. [PDEN] do not

disable DLL.

Self-refresh exit [SELFX]

This command is executed to exit from self-refresh mode. To issue non-read commands, tSNR has to be satisfied.

((tSNR =)10 cycles for tCK = 7.5 ns or 12 cycles for tCK = 6.0 ns after [SELFX]) To issue read command, tSRD has

to be satisfied to adjust DOUT timing by DLL. (200 cycles after [SELFX]) After the exit, input auto-refresh command

within 15.6 µs.

Power down exit [PDEX]

The DDR SDRAM can exit from power down mode tPDEX (1 cycle min.) after the cycle when [PDEX] is issued.

Preliminary Data Sheet E0614E20 (Ver. 2.0)

19

EDD1216AASE

Simplified State Diagram

SELF

REFRESH

SR ENTRY

SR EXIT

MRS

*1

REFRESH

AUTO

MRS

EMRS

IDLE

REFRESH

CKE

CKE_

IDLE

POWER

DOWN

ACTIVE

POWER

DOWN

CKE_

CKE

ROW

ACTIVE

BST

READ

WRITE

Write

WRITE

WITH

AP

READ

WITH

AP

Read

WRITE

READ

WITH AP

WRITE

WITH AP

READ

WITH AP

PRECHARGE

WRITEA

READA

PRECHARGE PRECHARGE

POWER

APPLIED

POWER

ON

PRECHARGE

Automatic transition after completion of command.

Transition resulting from command input.

Note: 1. After the auto-refresh operation, precharge operation is performed automatically

and enter the IDLE state.

Preliminary Data Sheet E0614E20 (Ver. 2.0)

20

EDD1216AASE

Operation of the DDR SDRAM

Power-up Sequence

(1)Apply power and maintain CKE at an LVCMOS low state (all other inputs are undefined).

Apply VDD before or at the same time as VDDQ.

Apply VDDQ before or at the same time as VTT and VREF.

(2) Start clock and maintain stable condition for a minimum of 200 µs.

(3) After the minimum 200 µs of stable power and clock (CK, /CK), apply NOP and take CKE high.

(4) Issue precharge all command for the device.

(5) Issue EMRS to enable DLL.

(6) Issue a mode register set command (MRS) for "DLL reset" with bit A8 set to high (An additional 200 cycles of

clock input is required to lock the DLL after every DLL reset).

(7) Issue precharge all command for the device.

(8) Issue 2 or more auto-refresh commands.

(9) Issue a mode register set command to initialize device operation with bit A8 set to low in order to avoid resetting

the DLL.

(4)

(5)

(6)

(7)

(8)

(9)

/CK

CK

Any

command

Command

PALL

EMRS

MRS

PALL

REF

MRS

t

RFC

2 cycles (min.) 2 cycles (min.) 2 cycles (min.)

DLL enable

DLL reset with A8 = High

2 cycles (min.)

RP

RFC

Disable DLL reset with A8 = Low

200 cycles (min)

Power-up Sequence after CKE Goes High

Mode Register and Extended Mode Register Set

There are two mode registers, the mode register and the extended mode register so as to define the operating

mode. Parameters are set to both through the A0 to the A11 and BA0, BA1 pins by the mode register set command

[MRS] or the extended mode register set command [EMRS]. The mode register and the extended mode register are

set by inputting signal via the A0 to the A11 and BA0, BA1 during mode register set cycles. BA0 and BA1 determine

which one of the mode register or the extended mode register are set. Prior to a read or a write operation, the mode

register must be set.

Remind that no other parameters shown in the table bellow are allowed to input to the registers.

BA0 BA1 A11 A10 A9 A8 A7 A6 A5 A4

DR LMODE

A3

BT

A2 A1

BL

A0

0

MRS

A6 A5 A4 CAS Latency

A8 DLL Reset

A3 Burst Type

Burst Length

BT=0 BT=1

A2 A1 A0

2

0

1

0

1

No

0

1

Sequential

Interleave

2.5

2

4

8

2

4

8

0

1

0

1

Yes

Mode Register Set [MRS] (BA0 = 0, BA1 = 0)

Preliminary Data Sheet E0614E20 (Ver. 2.0)

21

EDD1216AASE

BA0 BA1 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

DS DLL

1

0

EMRS

A0 DLL Control

A1

0

Driver Strength

Normal

0

1

DLL Enable

DLL Disable

1

Weak

Extended Mode Register Set [EMRS] (BA0 = 1, BA1 = 0)

Burst Operation

The burst type (BT) and the first three bits of the column address determine the order of a data out.

Burst length = 2

Burst length = 4

Starting Ad. Addressing(decimal)

A0

0

Sequence Interleave

A1

0

A0 Sequence

Interleave

0, 1,

1, 0,

0, 1,

1, 0,

0

1

0

1

0, 1, 2, 3,

1, 0, 3, 2,

2, 3, 0, 1,

3, 2, 1, 0,

1

0

1, 2, 3, 0,

2, 3, 0, 1,

1

3,

0, 1, 2,

Burst length = 8

Starting Ad.

Addressing(decimal)

A2 A1 A0 Sequence

Interleave

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0, 1, 2, 3, 4, 5, 6, 7,

1, 2, 3, 4, 5, 6, 7, 0,

2, 3, 4, 5, 6, 7, 0, 1,

3, 4, 5, 6, 7, 0, 1, 2,

4, 5, 6, 7, 0, 1, 2, 3,

5, 6, 7, 0, 1, 2, 3, 4,

6, 7, 0, 1, 2, 3, 4, 5,

7, 0, 1, 2, 3, 4, 5, 6,

0, 1, 2, 3, 4, 5, 6, 7,

1, 0, 3, 2, 5, 4, 7, 6,

2, 3, 0, 1, 6, 7, 4, 5,

3, 2, 1, 0, 7, 6, 5, 4,

4, 5, 6, 7, 0, 1, 2, 3,

5, 4, 7, 6, 1, 0, 3, 2,

6, 7, 4, 5, 2, 3, 0, 1,

7, 6, 5, 4, 3, 2, 1, 0,

Preliminary Data Sheet E0614E20 (Ver. 2.0)

22

EDD1216AASE

Read/Write Operations

Bank active

A read or a write operation begins with the bank active command [ACT]. The bank active command determines a

bank address and a row address. For the bank and the row, a read or a write command can be issued tRCD after

the ACT is issued.

Read operation

The burst length (BL), the /CAS latency (CL) and the burst type (BT) of the mode register are referred when a read

command is issued. The burst length (BL) determines the length of a sequential output data by the read command

that can be set to 2, 4, or 8. The starting address of the burst read is defined by the column address, the bank select

address which are loaded via the A0 to A11 and BA0, BA1 pins in the cycle when the read command is issued. The

data output timing are characterized by CL and tAC. The read burst start CL • tCK + tAC (ns) after the clock rising

edge where the read command are latched. The DDR SDRAM output the data strobe through DQS simultaneously

with data. tRPRE prior to the first rising edge of the data strobe, the DQS are driven Low from VTT level. This low

period of DQS is referred as read preamble. The burst data are output coincidentally at both the rising and falling

edge of the data strobe. The DQ pins become High-Z in the next cycle after the burst read operation completed.

tRPST from the last falling edge of the data strobe, the DQS pins become High-Z. This low period of DQS is

referred as read postamble.

t0

t1

t4

t5

t6

t7

t8

t9

CK

/CK

tRCD

NOP

Command

Address

NOP

ACT

Row

READ

NOP

Column

tRPRE

out0 out1

BL = 2

tRPST

DQS

DQ

out0 out1 out2 out3

BL = 4

BL = 8

out0 out1 out2 out3 out4 out5 out6 out7

CL = 2

BL: Burst length

Read Operation (Burst Length)

Preliminary Data Sheet E0614E20 (Ver. 2.0)

23

EDD1216AASE

t0

t0.5

t1

t1.5

t2

t2.5

t3

t3.5

t4

t4.5

t5

t5.5

CK

/CK

READ

NOP

Command

DQS

tRPRE

tRPST

VTT

CL = 2

tAC,tDQSCK

tRPRE

VTT

out0 out1 out2 out3

DQ

tRPST

DQS

CL = 2.5

tAC,tDQSCK

VTT

out0 out1 out2 out3

DQ

Read Operation (/CAS Latency)

Write operation

The burst length (BL) and the burst type (BT) of the mode register are referred when a write command is issued.

The burst length (BL) determines the length of a sequential data input by the write command that can be set to 2, 4,

or 8. The latency from write command to data input is fixed to 1. The starting address of the burst read is defined by

the column address, the bank select address which are loaded via the A0 to A11, BA0 to BA1 pins in the cycle when

the write command is issued. DQS should be input as the strobe for the input-data and DM as well during burst

operation. tWPRE prior to the first rising edge of the DQS should be set to Low and tWPST after the last falling edge

of the data strobe can be set to High-Z. The leading low period of DQS is referred as write preamble. The last low

period of DQS is referred as write postamble.

t0

t1

tn tn+0.5 tn+1

tn+2

tn+3

tn+4

tn+5

CK

/CK

tRCD

NOP

Command

Address

NOP

ACT

Row

WRITE

NOP

Column

tWPRE

tWPRES

in0 in1

BL = 2

tWPST

DQS

DQ

in0 in1 in2 in3

BL = 4

BL = 8

in0 in1 in2 in3 in4 in5 in6 in7

BL: Burst length

Write Operation

Preliminary Data Sheet E0614E20 (Ver. 2.0)

24

EDD1216AASE

Burst Stop

Burst stop command during burst read

The burst stop (BST) command is used to stop data output during a burst read. The BST command stops the burst

read and sets the output buffer to High-Z. tBSTZ (= CL) cycles after a BST command issued, the DQ pins become

High-Z. The BST command is not supported for the burst write operation. Note that bank address is not referred

when this command is executed.

t0

t0.5

t1

t1.5

t2

t2.5

t3

t3.5

t4

t4.5

t5

t5.5

CK

/CK

READ

Command

BST

NOP

tBSTZ

2 cycles

DQS

CL = 2

out0 out1

tBSTZ

DQ

2.5 cycles

DQS

DQ

CL = 2.5

out0 out1

CL: /CAS latency

Burst Stop during a Read Operation

Preliminary Data Sheet E0614E20 (Ver. 2.0)

25

EDD1216AASE

Auto Precharge

Read with auto-precharge

The precharge is automatically performed after completing a read operation. The precharge starts tRPD (BL/2)

cycle after READA command input. tRAP specification for READA allows a read command with auto precharge to be

issued to a bank that has been activated (opened) but has not yet satisfied the tRAS (min) specification. A column

command to the other active bank can be issued the next cycle after the last data output. Read with auto-precharge

command does not limit row commands execution for other bank. Refer to ‘Function truth table and related

note(Notes.*14).

CK

/CK

tRP (min)

tRAP (min) = tRCD (min)

tRPD

2 cycles (= BL/2)

ACT

READA

NOP

ACT

Command

DQS

tAC,tDQSCK

DQ

out0 out1 out2 out3

Note: Internal auto-precharge starts at the timing indicated by " ".

Read with auto-precharge

Write with auto-precharge

The precharge is automatically performed after completing a burst write operation. The precharge operation is

started (BL/ 2 + 3) cycles after WRITA command issued. A column command to the other banks can be issued the

next cycle after the internal precharge command issued. Write with auto-precharge command does not limit row

commands execution for other bank. Refer to the ‘Read with Auto-Precharge Enabled, Write with Auto-Precharge

Enabled’ section. Refer to ‘Function truth table and related note(Notes.*14)‘.

CK

/CK

tRAS (min)

tRP

tRCD (min)

ACT

NOP

WRITA

NOP

ACT

Command

BL/2 + 3 cycles

DM

DQS

DQ

in1 in2 in3 in4

BL = 4

Note: Internal auto-precharge starts at the timing indicated by " ".

Burst Write (BL = 4)

Preliminary Data Sheet E0614E20 (Ver. 2.0)

26

EDD1216AASE

Command Intervals

A Read command to the consecutive Read command Interval

Destination row of the

consecutive read command

Bank

address

Row address State

Operation

The consecutive read can be performed after an interval of no less than 1 cycle to

interrupt the preceding read operation.

Precharge the bank to interrupt the preceding read operation. tRP after the

precharge command, issue the ACT command. tRCD after the ACT command, the

consecutive read command can be issued. See ‘A read command to the

consecutive precharge interval’ section.

The consecutive read can be performed after an interval of no less than 1 cycle to

interrupt the preceding read operation.

Precharge the bank without interrupting the preceding read operation. tRP after

the precharge command, issue the ACT command. tRCD after the ACT command,

the consecutive read command can be issued.

1. Same

Same

Different

Any

ACTIVE

2. Same

—

3. Different

ACTIVE

IDLE

t0

t3

t4

t5

t6

t7

t8

t9

CK

/CK

Command

NOP

ACT

Row

NOP

READ

Column A Column B

Address

BA

out out out out out out

A0 A1 B0 B1 B2 B3

DQ

Column = A Column = B

Read

Column = A

Dout

Column = B

Dout

DQS

CL = 2

BL = 4

Bank0

Active

READ to READ Command Interval (same ROW address in the same bank)

Preliminary Data Sheet E0614E20 (Ver. 2.0)

27

EDD1216AASE

t0

t1

t2

t3

t4

t5

t6

t7

t8

t9

CK

/CK

Command

READ

NOP

ACT

NOP

ACT

NOP

Row0

Row1

Column A Column B

Address

BA

out out out out out out

A0 A1 B0 B1 B2 B3

DQ

Column = A Column = B

Read

Bank0

Dout

Bank3

Dout

DQS

CL = 2

BL = 4

Bank0

Active

Bank3

Active

Bank0

Read

Bank3

Read

READ to READ Command Interval (different bank)

Preliminary Data Sheet E0614E20 (Ver. 2.0)

28

EDD1216AASE

A Write command to the consecutive Write command Interval

Destination row of the consecutive write

command

Bank

address

Row address State

Operation

The consecutive write can be performed after an interval of no less than 1 cycle to

interrupt the preceding write operation.

Precharge the bank to interrupt the preceding write operation. tRP after the

precharge command, issue the ACT command. tRCD after the ACT command, the

consecutive write command can be issued. See ‘A write command to the

consecutive precharge interval’ section.

The consecutive write can be performed after an interval of no less than 1 cycle to

interrupt the preceding write operation.

Precharge the bank without interrupting the preceding write operation. tRP after

the precharge command, issue the ACT command. tRCD after the ACT command,

the consecutive write command can be issued.

1. Same

Same

Different

Any

ACTIVE

2. Same

—

3. Different

ACTIVE

IDLE

t0

tn

tn+1

tn+2

tn+3

tn+4

tn+5

tn+6

CK

/CK

Command

NOP

ACT

Row

NOP

WRIT

Column A Column B

Address

BA

DQ

inA0 inA1 inB0 inB1 inB2 inB3

Column = A

Write

Column = B

Write

DQS

Bank0

Active

BL = 4

Bank0

WRITE to WRITE Command Interval (same ROW address in the same bank)

Preliminary Data Sheet E0614E20 (Ver. 2.0)

29

EDD1216AASE

t0

t1

t2

tn

tn+1

tn+2

tn+3

tn+4

tn+5

CK

/CK

Command

NOP

ACT

NOP

ACT

NOP

WRIT

Row0

Row1

Column A Column B

Address

BA

DQ

inA0 inA1 inB0 inB1 inB2 inB3

Bank0

Write

Bank3

Write

DQS

Bank0

Active

Bank3

Active

BL = 4

Bank0, 3

WRITE to WRITE Command Interval (different bank)

Preliminary Data Sheet E0614E20 (Ver. 2.0)

30

EDD1216AASE

A Read command to the consecutive Write command interval with the BST command

Destination row of the consecutive write

command

Bank

address

Row address State

Operation

Issue the BST command. tBSTW (≥ tBSTZ) after the BST command, the

1. Same

Same

Different

Any

ACTIVE

consecutive write command can be issued.

Precharge the bank to interrupt the preceding read operation. tRP after the

precharge command, issue the ACT command. tRCD after the ACT command, the

consecutive write command can be issued. See ‘A read command to the

consecutive precharge interval’ section.

Issue the BST command. tBSTW (≥ tBSTZ) after the BST command, the

consecutive write command can be issued.

Precharge the bank independently of the preceding read operation. tRP after the

precharge command, issue the ACT command. tRCD after the ACT command, the

consecutive write command can be issued.

2. Same

—

3. Different

ACTIVE

IDLE

t0

t1

t2

t3

t4

t5

t6

t7

t8

CK

/CK

Command

READ

WRIT

BST

NOP

tBSTW (≥ tBSTZ)

DM

tBSTZ (= CL)

DQ

out0 out1

in0 in1 in2 in3

High-Z

DQS

OUTPUT

INPUT

BL = 4

CL = 2

READ to WRITE Command Interval

Preliminary Data Sheet E0614E20 (Ver. 2.0)

31

EDD1216AASE

A Write command to the consecutive Read command interval: To complete the burst operation

Destination row of the consecutive read

command

Bank

Row address State

address

Operation

To complete the burst operation, the consecutive read command should be

performed tWRD (= BL/ 2 + 2) after the write command.

Precharge the bank tWPD after the preceding write command. tRP after the

precharge command, issue the ACT command. tRCD after the ACT command, the

consecutive read command can be issued. See ‘A read command to the

consecutive precharge interval’ section.

To complete a burst operation, the consecutive read command should be

performed tWRD (= BL/ 2 + 2) after the write command.

Precharge the bank independently of the preceding write operation. tRP after the

precharge command, issue the ACT command. tRCD after the ACT command, the

consecutive read command can be issued.

1. Same

2. Same

3. Different

Same

Different

Any

ACTIVE

—

ACTIVE

IDLE

t0

t1

t2

t3

t4

t5

t6

CK

/CK

Command

WRIT

NOP

READ

NOP

tWRD (min)

tWTR*

BL/2 + 2 cycle

DM

out2

DQ

out0 out1

in0

in1

in2

in3

DQS

INPUT

OUTPUT

BL = 4

CL = 2

Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR.

WRITE to READ Command Interval

Preliminary Data Sheet E0614E20 (Ver. 2.0)

32

EDD1216AASE

A Write command to the consecutive Read command interval: To interrupt the write operation

Destination row of the consecutive read

command

Bank

Row address State

address

Operation

DM must be input 1 cycle prior to the read command input to prevent from being

written invalid data. In case, the read command is input in the next cycle of the

write command, DM is not necessary.

1. Same

2. Same

3. Different

Same

Different

Any

ACTIVE

—

—*¹

DM must be input 1 cycle prior to the read command input to prevent from being

written invalid data. In case, the read command is input in the next cycle of the

write command, DM is not necessary.

ACTIVE

IDLE

—*¹

Note: 1. Precharge must be preceded to read command. Therefore read command can not interrupt the write

operation in this case.

WRITE to READ Command Interval (Same bank, same ROW address)

t0

t1

t2

t3

t4

t5

t6

t7

t8

CK

/CK

Command

WRIT

READ

NOP

1 cycle

CL=2

DM

High-Z

DQ

out0 out1 out2 out3

in0 in1

in2

DQS

BL = 4

CL= 2

Data masked

[WRITE to READ delay = 1 clock cycle]

Preliminary Data Sheet E0614E20 (Ver. 2.0)

33

EDD1216AASE

t0

t1

t2

t3

t4

t5

t6

t7

t8

CK

/CK

Command

WRIT

NOP

READ

NOP

2 cycle

CL=2

DM

High-Z

DQ

in0 in1

in2

in3

out0 out1 out2 out3

High-Z

DQS

Data masked

BL = 4

CL= 2

[WRITE to READ delay = 2 clock cycle]

t0

t1

t2

t3

t4

t5

t6

t7

t8

CK

/CK

Command

WRIT

NOP

3 cycle

READ

NOP

CL=2

tWTR*

DM

out0 out1 out2 out3

DQ

in0 in1

in2

in3

DQS

BL = 4

CL= 2

Data masked

Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR.

[WRITE to READ delay = 3 clock cycle]

Preliminary Data Sheet E0614E20 (Ver. 2.0)

34

EDD1216AASE

A Read command to the consecutive Precharge command interval (same bank): To output all data

To complete a burst read operation and get a burst length of data, the consecutive precharge command must be

issued tRPD (= BL/ 2 cycles) after the read command is issued.

t0

t1

t2

t3

t4

t5

t6

t7

t8

CK

/CK

Command

PRE/

PALL

NOP

READ

DQ

out0 out1 out2 out3

DQS

tRPD = BL/2

READ to PRECHARGE Command Interval (same bank): To output all data (CL = 2, BL = 4)

t0

t1

t2

t3

t4

t5

t6

t7

t8

CK

/CK

PRE/

PALL

Command

DQ

NOP

READ

out0 out1 out2 out3

DQS

tRPD = BL/2

READ to PRECHARGE Command Interval (same bank): To output all data (CL = 2.5, BL = 4)

Preliminary Data Sheet E0614E20 (Ver. 2.0)

35

EDD1216AASE

READ to PRECHARGE Command Interval (same bank): To stop output data

A burst data output can be interrupted with a precharge command. All DQ pins and DQS pins become High-Z tHZP

(= CL) after the precharge command.

t0

t1

t2

t3

t4

t5

t6

t7

t8

CK

/CK

Command

DQ

NOP

PRE/PALL

READ

High-Z

out0 out1

DQS

tHZP

READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 2, BL = 2, 4, 8)

t0

t1

t2

t3

t4

t5

t6

t7

t8

CK

/CK

PRE/PALL

CL = 2.5

Command

DQ

NOP

READ

High-Z

out0 out1

DQS

tHZP

READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 2.5, BL = 2, 4, 8)

Preliminary Data Sheet E0614E20 (Ver. 2.0)

36

EDD1216AASE

A Write command to the consecutive Precharge command interval (same bank)

The minimum interval tWPD is necessary between the write command and the precharge command.

t0

t1

t2

t3

t4

t5

t6

t7

CK

/CK

Command

PRE/PALL

WRIT

NOP

tWPD

NOP

tWR

DM

DQS

DQ

in0

in1

in2

in3

Last data input

WRITE to PRECHARGE Command Interval (same bank) (BL = 4)

Precharge Termination in Write Cycles

During a burst write cycle without auto precharge, the burst write operation is terminated by a precharge command

of the same bank. In order to write the last input data, tWR (min) must be satisfied. When the precharge command

is issued, the invalid data must be masked by DM.

t0

t1

t2

t3

t4

t5

t6

t7

CK

/CK

Command

PRE/PALL

WRIT

NOP

tWR

DM

DQS

DQ

in0

in1

in2

in3

Data masked

Precharge Termination in Write Cycles (same bank) (BL = 4)

Preliminary Data Sheet E0614E20 (Ver. 2.0)

37

EDD1216AASE

Bank active command interval

Destination row of the consecutive ACT

command

Bank

address

Row address

State

Operation

Two successive ACT commands can be issued at tRC interval. In between two

1. Same

2. Different

Any

ACTIVE

successive ACT operations, precharge command should be executed.

Precharge the bank. tRP after the precharge command, the consecutive ACT

command can be issued.

tRRD after an ACT command, the next ACT command can be issued.

ACTIVE

IDLE

CK

/CK

Command

A

C

T

V

ACT

NOP

PRE

NOP

ACT

NOP

Address

BA

ROW: 0

ROW: 1

ROW: 0

Bank0

Active

Bank3

Active

Bank0

Precharge

Bank0

Active

tRRD

tRC

Bank Active to Bank Active

Mode register set to Bank-active command interval

The interval between setting the mode register and executing a bank-active command must be no less than tMRD.

CK

/CK

Command

MRS

NOP

ACT

NOP

Address

CODE

BS and ROW

Mode Register Set

Bank3

Active

tMRD

Preliminary Data Sheet E0614E20 (Ver. 2.0)

38

EDD1216AASE

DM Control

DM can mask input data. In ×16 products, UDM and LDM can mask the upper and lower byte of input data,

respectively. By setting DM to Low, data can be written. When DM is set to High, the corresponding data is not

written, and the previous data is held. The latency between DM input and enabling/disabling mask function is 0.

t1

t2

t3

t4

t5

t6

DQS

DQ

Mask

DM

Write mask latency = 0

DM Control

Preliminary Data Sheet E0614E20 (Ver. 2.0)

39

EDD1216AASE

Timing Waveforms

Command and Addresses Input Timing Definition

CK

/CK

tIS

tIH

Command

(/RAS, /CAS,

/WE, /CS)

VREF

Address

Read Timing Definition

tCK

/CK

CK

tCL

tRPRE

tCH

tDQSCK

tDQSCK tRPST

DQS

tDQSQ

tQH

tHZ

tQH

tAC

tLZ

tAC

DQ

(Dout)

tDQSQ

tQH

Write Timing Definition

tCK

/CK

CK

tDQSS

tDSS

tDSH

tDSS

VREF

DQS

tWPRES

tDQSL

tDQSH

tWPST

tWPRE

DQ

(Din)

tDIPW

tDS

tDH

DM

tDIPW

Preliminary Data Sheet E0614E20 (Ver. 2.0)

40

EDD1216AASE

Read Cycle

tCK

tCH tCL

CK

/CK

tRC

VIH

CKE

tRAS

tRP

tRCD

tIS tIH

/CS

tIS tIH

/RAS

tIS tIH

/CAS

tIS tIH

/WE

BA

tIS tIH

A10

tIS tIH

Address

DM

tRPST

tRPRE

High-Z

DQS

High-Z

DQ (output)

Bankk 00

Actiivvee

B

ank

0

Bank 0

Precharge

CL = 2

BL = 4

Bank0 Access

= VIH or VIL

Preliminary Data Sheet E0614E20 (Ver. 2.0)

41

EDD1216AASE

Write Cycle

tCK

tCH

tCL

CK

/CK

tRC

VIH

CKE

/CS

tRAS

tRP

tRCD

tIS tIH

/RAS

/CAS

/WE

tIS tIH

tIS

tIH

tIS tIH

BA

tIS tIH

A10

tIS tIH

Address

tDQSS

tDQSL

tWPST

tDH

DQS

(input)

tDQSH

tDS

DM

tDS

tDH

DQ (input)

tWR

tDH

CL = 2

BL = 4

Bank0 Access

= VIH or VIL

Bank 0

Active

Bank 0

Write

Bank 0

Precharge

Preliminary Data Sheet E0614E20 (Ver. 2.0)

42

EDD1216AASE

Mode Register Set Cycle

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

/CK

CK

VIH

CKE

/CS

/RAS

/CAS

/WE

BA

Address

DM

code

C: b

R: b

valid

High-Z

DQS

b

DQ (output)

tMRD

tRP

Bank 3

Read

Bank 3

Precharge

Mode

register

set

Bank 3

Active

CL = 2

BL = 4

Precharge

If needed

= VIH or VIL

Read/Write Cycle

/CK

CK

VIH

CKE

/CS

/RAS

/CAS

/WE

BA

Address

R:a

C:b''

C:a R:b

C:b

DM

DQS

a

b’’

DQ (output)

DQ (input)

High-Z

b

tRWD

tWRD

Bank 0

Active

Bank 0 Bank 3

Read Active

Bank 3

Write

Bank 3

Read

Read cycle

CL = 2

BL = 4

=VIH or VIL

Preliminary Data Sheet E0614E20 (Ver. 2.0)

43

EDD1216AASE

Auto Refresh Cycle

/CK

CK

VIH

CKE

/CS

/RAS

/CAS

/WE

BA

Address

A10=1

R: b

C: b

DM

DQS

b

DQ (output)

DQ (input)

High-Z

tRP

tRFC

Precharge

If needed

Auto

Refresh

Bank 0

Active

Bank 0

Read

CL = 2

BL = 4

= VIH or VIL

Preliminary Data Sheet E0614E20 (Ver. 2.0)

44

EDD1216AASE

Self Refresh Cycle

/CK

CK

tIS

tIH

CKE = low

CKE

/CS

/RAS

/CAS

/WE

BA

Address

A10=1

R: b

C: b

DM

DQS

DQ (output)

DQ (input)

High-Z

tSNR

tSRD

tRP

Precharge

If needed

Self

refresh

entry

Self refresh

exit

Bank 0

Active

Bank 0

Read

CL = 2.5

BL = 4

= VIH or VIL

Preliminary Data Sheet E0614E20 (Ver. 2.0)

45

EDD1216AASE

Package Drawing

60-ball FBGA (µBGA)

Solder ball: Lead free (Sn-Ag-Cu)

Unit: mm

8.0 ± 0.1

S

B

0.2

INDEX MARK

S

A

0.2

S

0.1

1.14 max.

S

0.1

0.35 ± 0.05

B

M

φ0.10

S A B

60-φ0.45 ± 0.05

A

INDEX MARK

1.6

6.4

0.8

ECA-TS2-0140-01

Preliminary Data Sheet E0614E20 (Ver. 2.0)

46

EDD1216AASE

Recommended Soldering Conditions

Please consult with our sales offices for soldering conditions of the EDD1216AASE.

Type of Surface Mount Device

EDD1216AASE: 60-ball FBGA (µBGA) < Lead free (Sn-Ag-Cu) >

Preliminary Data Sheet E0614E20 (Ver. 2.0)

47

EDD1216AASE

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR MOS DEVICES

1

Exposing the MOS devices to a strong electric field can cause destruction of the gate

oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop

generation of static electricity as much as possible, and quickly dissipate it, when once

it has occurred. Environmental control must be adequate. When it is dry, humidifier

should be used. It is recommended to avoid using insulators that easily build static

electricity. MOS devices must be stored and transported in an anti-static container,

static shielding bag or conductive material. All test and measurement tools including

work bench and floor should be grounded. The operator should be grounded using

wrist strap. MOS devices must not be touched with bare hands. Similar precautions

need to be taken for PW boards with semiconductor MOS devices on it.

2

HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES

No connection for CMOS devices input pins can be a cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input level may be

generated due to noise, etc., hence causing malfunction. CMOS devices behave

differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected

to V^DDor GND with a resistor, if it is considered to have a possibility of being an output

pin. The unused pins must be handled in accordance with the related specifications.

3

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Power-on does not necessarily define initial status of MOS devices. Production process

of MOS does not define the initial operation status of the device. Immediately after the

power source is turned ON, the MOS devices with reset function have not yet been

initialized. Hence, power-on does not guarantee output pin levels, I/O settings or

contents of registers. MOS devices are not initialized until the reset signal is received.

Reset operation must be executed immediately after power-on for MOS devices having

reset function.

CME0107

Preliminary Data Sheet E0614E20 (Ver. 2.0)

48

EDD1216AASE

µBGA is a registered trademark of Tessera, Inc.

All other trademarks are the intellectual property of their respective owners.

The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.

No part of this document may be copied or reproduced in any form or by any means without the prior

written consent of Elpida Memory, Inc.

Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights

(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or

third parties by or arising from the use of the products or information listed in this document. No license,

express, implied or otherwise, is granted under any patents, copyrights or other intellectual property

rights of Elpida Memory, Inc. or others.

Descriptions of circuits, software and other related information in this document are provided for

illustrative purposes in semiconductor product operation and application examples. The incorporation of

these circuits, software and information in the design of the customer's equipment shall be done under

the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses

incurred by customers or third parties arising from the use of these circuits, software and information.

[Product applications]

Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.

However, users are instructed to contact Elpida Memory's sales office before using the product in

aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,

medical equipment for life support, or other such application in which especially high quality and

reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk

of bodily injury.

[Product usage]

Design your application so that the product is used within the ranges and conditions guaranteed by

Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation

characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no

responsibility for failure or damage when the product is used beyond the guaranteed ranges and

conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure

rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so

that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other

consequential damage due to the operation of the Elpida Memory, Inc. product.

[Usage environment]

This product is not designed to be resistant to electromagnetic waves or radiation. This product must be

used in a non-condensing environment.

If you export the products or technology described in this document that are controlled by the Foreign

Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance

with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by

U.S. export control regulations, or another country's export control laws or regulations, you must follow

the necessary procedures in accordance with such laws or regulations.

If these products/technology are sold, leased, or transferred to a third party, or a third party is granted

license to use these products, that third party must be made aware that they are responsible for

compliance with the relevant laws and regulations.

M01E0107

Preliminary Data Sheet E0614E20 (Ver. 2.0)

49


型号：	EDD1216AASE-7A-E
厂家：	ELPIDA MEMORY
描述：	128M bits DDR SDRAM (8M words x 16 bits) 128M位的DDR SDRAM （8M字×16位）动态存储器双倍数据速率
文件：	总49页 (文件大小：564K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EDD1216AASE-7A-E [ELPIDA]

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