EDE5108GASA-4A-E_技术文档

PRELIMINARY DATA SHEET

512M bits DDR-II SDRAM

EDE5104GASA (128M words × 4 bits)

EDE5108GASA (64M words × 8 bits)

Pin Configurations

Description

The EDE5104GA is a 512M bits DDR-II SDRAM

/xxx indicates active low signal.

60-ball FBGA

organized as 33,554,432 words × 4 bits × 4 banks.

1

2

3

7

8

9

The EDE5108GA is a 512M bits DDR-II SDRAM

organized as 16,777,216 words × 8 bits × 4 banks.

A

B

C

D

E

F

G

H

J

NU/ /RDQS

(NC)*

VDD

VSS

VSSQ /DQS VDDQ

It is packaged in 60-ball FBGA package.

DQ6

(NC)*

DQ7

DQS VSSQ

(NC)*

DM/RDQS

(DM)*

Features

VSSQ

• 1.8V power supply

VDDQ

DQ1 VDDQ

VSSQ DQ3

VREF VSS

CKE /WE

VDDQ DQ0 VDDQ

• Double-data-rate architecture: two data transfers per

clock cycle

DQ4

(NC)*

DQ5

DQ2 VSSQ

(NC)*

• Bi-directional, differential data strobe (DQS and

/DQS) is transmitted/received with data, to be used in

capturing data at the receiver

VDDL

VSSDL CK

VDD

NC

/RAS

/CAS

A2

/CK

/CS

A0

• DQS is edge aligned with data for READs: center-

aligned with data for WRITEs

BA0

A10

A3

BA1

A1

NC

• Differential clock inputs (CK and /CK)

VDD

VSS

• DLL aligns DQ and DQS transitions with CK

transitions

A5

A6

A4

VSS

VDD

• Commands entered on each positive CK edge: data

and data mask referenced to both edges of DQS

K

L

A7

A9

A11

NC

A8

• Four internal banks for concurrent operation

• Data mask (DM) for write data

A12

NC

• Burst lengths: 4 only

(Top view)

Note: ( )* marked pins are for EDE5104GA.

• /CAS Latency (CL): 3, 4

• Auto precharge operation for each burst access

• Auto refresh and self refresh modes

• 7.8µs maximum average periodic refresh interval

• 1.8V (SSTL_18 compatible) I/O

A0 to A12

BA0, BA1

DQ0 to DQ7

DQS, /DQS

RDQS, /RDQS

/CS

/RAS, /CAS, /WE

CKE

CK, /CK

DM

VDD

VSS

VDDQ

VSSQ

VREF

VDDL

VSSDL

NC*¹

NU*²

Address input

Bank select address

Data-input/output

Differential data strobe

Differential data strobe for read

Chip select

Command input

Clock enable

Differential Clock input

Output mask

Power for internal circuit

Ground for internal circuit

Power for DQ circuit

Ground for DQ circuit

Reference supply voltage

Power for DLL circuit

Ground for DLL circuit

No connection

• Off-Chip-Driver Impedance Adjustment for better

signal quality.

• Programmable RDQS, /RDQS output for the

compatibility to × 4 organization

• /DQS, (/RDQS) can be disabled for single-ended

Data Strobe operation.

• FBGA package is lead free solder (Sn-Ag-Cu)

Not usable

Notes: 1. Not internally connected with die.

2. Don't connect. Internally connected with die.

Document No. E0203E41 (Ver. 4.1)

Date Published February 2006 (K) Japan

URL: http://www.elpida.com

This product became EOL in March, 2004.

Elpida Memory, Inc. 2001-2006

EDE5104GASA, EDE5108GASA

Ordering Information

Mask

version

Organization

(words × bits)

Internal

Banks

Data rate

(Mbps)

Part number

/CAS latency Package

4

3, 4

EDE5104GASA-5A-E

EDE5104GASA-4A-E

533

400

A

128M × 4

64M × 8

4

60-ball FBGA

EDE5108GASA-5A-E

EDE5108GASA-4A-E

533

400

4

3, 4

Part Number

E D E 51 04 G A SA - 4A - E

Elpida Memory

Type

D: Monolithic Device

Lead Free

Product Code

E: DDR-II

Speed

Density / Bank

5A: 533Mbps

4A: 400Mbps

51: 512M /4-bank

Bit Organization

04: x4

08: x8

Package

SA: FBGA

Die Rev.

Voltage, Interface

G: 1.8V, SSTL_18

Preliminary Data Sheet E0203E41 (Ver. 4.1)

2

EDE5104GASA, EDE5108GASA

CONTENTS

Description.....................................................................................................................................................1

Features.........................................................................................................................................................1

Pin Configurations .........................................................................................................................................1

Ordering Information......................................................................................................................................2

Part Number ..................................................................................................................................................2

Electrical Specifications.................................................................................................................................4

Block Diagram ...............................................................................................................................................9

Pin Function.................................................................................................................................................10

Command Operation ...................................................................................................................................12

Simplified State Diagram.............................................................................................................................19

Operation of DDR-II SDRAM.......................................................................................................................20

Package Drawing ........................................................................................................................................42

Recommended Soldering Conditions..........................................................................................................43

Preliminary Data Sheet E0203E41 (Ver. 4.1)

3

EDE5104GASA, EDE5108GASA

Electrical Specifications

• All voltages are referenced to VSS (GND)

• After power up, wait more than 200µs and then execute power on sequence and CBR (Auto) refresh before proper

device operation is achieved.

Absolute Maximum Ratings

Parameter

Symbol

VDD

VDDQ

VIN

Rating

Unit

V

Note

Power supply voltage

Power supply voltage for output

Input voltage

–0.5 to +2.3

0 to +70

–55 to +150

1.0

1

V

Output voltage

VOUT

TA

V

Operating temperature (ambient)

Storage temperature

Power dissipation

°C

W

mA

TSTG

PD

Short circuit output current

IOUT

50

Note: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional operation of the device at these or any other

conditions above those indicated in the operational sections of this specification is not implied. Exposure

to absolute maximum rating conditions for extended periods may affect reliability.

Caution

Exposing the device to stress above those listed in Absolute Maximum Ratings could cause

permanent damage. The device is not meant to be operated under conditions outside the limits

described in the operational section of this specification. Exposure to Absolute Maximum Rating

conditions for extended periods may affect device reliability.

Recommended DC Operating Conditions (SSTL_18)

• There is no specific device VDD supply voltage requirement for SSTL_18 compliance. However under all

conditions VDDQ must be less than or equal to VDD.

Parameter

Symbol

min.

Typ.

1.8

max.

1.9

Unit

V

Notes

Supply voltage

VDD

1.7

4

Supply voltage for output

Input reference voltage

Termination voltage

DC input logic high

DC input low

VDDQ

VREF

1.7

1.8

1.9

V

4

0.49 × VDDQ

VREF – 0.04

VREF + 0.125

–0.3

0.50 × VDDQ 0.51 × VDDQ

V

1, 2

3

VTT

VREF

VREF + 0.04

VDDQ + 0.3V

VREF – 0.125

V

VIH (dc)

VIL (dc)

VIH (ac)

VIL (ac)

V

AC input logic high

AC input low

VREF + 0.250

V

VREF – 0.250

V

Notes: 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically

the value of VREF is expected to be about 0.5 × VDDQ of the transmitting device and VREF are expected

to track variations in VDDQ.

2. Peak to peak AC noise on VREF may not exceed ±2% VREF (dc).

3. VTT of transmitting device must track VREF of receiving device.

4. VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and

VDDL tied together.

Preliminary Data Sheet E0203E41 (Ver. 4.1)

4

EDE5104GASA, EDE5108GASA

DC Characteristics 1 (TA = 0 to +70°C, VDD, VDDQ = 1.8V ± 0.1V)

Parameter

Symbol

Grade

max.

Unit

Test condition

one bank; tRC = tRC (min.) ; tCK = tCK (min.) ; DQ,

DM, and DQS inputs changing twice per clock cycle;

address and control inputs changing once per clock

cycle

Operating current

(ACT-PRE)

-5A

-4A

110

100

IDD0

mA

one bank; Burst = 4; tRC = tRC (min.) ;

CL = 4; tCK = tCK (min.) ; IOUT = 0mA;

address and control inputs changing once per clock

cycle

Operating current

(ACT-READ-PRE)

-5A

-4A

160

140

IDD1

mA

Precharge power-down

standby current

all banks idle; power-down mode; CKE = VIL (max.);

tCK = tCK (min.)

IDD2P

IDD2N

IDD3P

25

mA

/CS = VIH (min.); all banks idle; CKE = VIH (min.);

tCK = tCK (min.) ; address and control inputs changing

once per clock cycle

-5A

-4A

55

45

Idle standby current

Active power-down

standby current

one bank active; power-down mode; CKE = VIL (max.);

tCK = tCK (min.)

30

one bank; active / precharge;/CS = VIH (min.);

CKE = VIH (min.); tRC = tRAS max; tCK = tCK (min.);

DQ, DM, and DQS inputs changing twice per clock

cycle; address and control inputs changing once per

clock cycle

-5A

-4A

65

55

Active standby current

IDD3N

mA

one bank; Burst = 4; burst; address and control inputs

changing once per clock cycle; DQ and DQS outputs

changing twice per clock cycle; CL = 4; tCK = tCK

(min.) ; IOUT = 0mA

Operating current

-5A

-4A

225

175

IDD4R

IDD4W

mA

(Burst read operating)

one bank; Burst = 4; writes; continuous burst; address

and control inputs changing once per clock cycle; DQ

and DQS inputs changing twice per clock cycle; CL = 4;

tCK = tCK (min.)

Operating current

-5A

-4A

225

175

(Burst write operating)

-5A

-4A

270

250

Auto-refresh current

Self-refresh current

IDD5

IDD6

mA

tRC = tRFC (min.)

4

CKE = 0.2V

Four bank interleaving READs (BL4) with auto

precharge, tRC = tRC (min.); Address and control

inputs change during Active, READ, or WRITE

commands.

Operating current

(Bank interleaving)

-5A

-4A

440

380

IDD7

mA

DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 1.8V ± 0.1V)

Parameter

Symbol

VOH

Unit

V

Notes

Minimum required output pull-up under AC

test load

VTT + 0.603

VTT – 0.603

Maximum required output pull-down under

AC test load

VOL

V

Output timing measurement reference level VOTR

0.5 × VDDQ

+13.4

V

1

Output minimum sink DC current

Output minimum source DC current

IOL

mA

3, 4,

2, 4

IOH

–13.4

Note: 1. The VDDQ of the device under test is referenced.

2. VDDQ = 1.7V; VOUT = 1.42V.

3. VDDQ = 1.9V; VOUT = 0.28V.

4. The DC value of VREF applied to the receiving device is expected to be set to VTT.

Preliminary Data Sheet E0203E41 (Ver. 4.1)

5

EDE5104GASA, EDE5108GASA

Pin Capacitance (TA = 25°C, VDD, VDDQ = 1.8V ± 0.1V)

Notes

Parameter

Symbol

CCK

CIN

Pins

CK

min.

1.5

3.0

Typ

2.0

3.5

max.

2.5

Unit

pF

1

2

CLK input pin capacitance

Input pin capacitance

Input/output pin capacitance

2.5

pF

CI/O

DQ

4.0

pF

Notes: 1. Matching within 0.25pF.

2. Matching within 0.50pF.

AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 1.8V ± 0.1V, VSS, VSSQ = 0V)

-5A

-4A

Frequency (Mbps)

533

400

Parameter

Symbol

tAC

min.

–500

max.

+500

+450

0.55

min.

–600

–500

0.45

max.

+600

+500

0.55

Unit

ps

Notes

DQ output access time from CK, /CK

DQS output access time from CK, /CK tDQSCK –450

ps

CK high-level width

CK low-level width

tCH

tCL

0.45

tCK

min.

(tCL, tCH)

min.

(tCL, tCH)

CK half period

tHP

ps

Clock cycle time

tCK

tDH

tDS

3750

350

8000

5000

400

8000

ps

DQ and DM input hold time

DQ and DM input setup time

350

400

Control and Address input pulse width

for each input

tIPW

tDIPW

tHZ

0.6

tCK

ps

DQ and DM input pulse width for each

input

0.35

Data-out high-impedance time from

CK,/CK

tAC max.

Data-out low-impedance time from

CK,/CK

tLZ

tAC min.

ps

DQS-DQ skew for DQS and associated

DQ signals

tDQSQ

300

400

350

450

ps

DQ hold skew factor

tQHS

tQH

ps

DQ/DQS output hold time from DQS

tHP – tQHS

WL – 0.25

tHP – tQHS

WL – 0.25

Write command to first DQS latching

transition

tDQSS

WL + 0.25

tCK

DQS input high pulse width

tDQSH

tDQSL

tDSS

0.35

0.2

2

0.35

0.2

2

tCK

ps

DQS input low pulse width

DQS falling edge to CK setup time

DQS falling edge hold time from CK

tDSH

Mode register set command cycle time tMRD

Write preamble setup time

Write postamble

tWPRES

0

tWPST

tWPRE

tIH

0.4

0.25

500

0.9

0.4

0.6

0.4

0.25

600

0.9

0.4

0.6

Write preamble

Address and control input hold time

Address and control input setup time

Read preamble

tIS

ps

tRPRE

tRPST

1.1

0.6

1.1

0.6

tCK

Read postamble

Preliminary Data Sheet E0203E41 (Ver. 4.1)

6

EDE5104GASA, EDE5108GASA

-5A

533

min.

45

-4A

400

Frequency (Mbps)

Parameter

Symbol

tRAS

max.

min.

45

max.

Unit

ns

Notes

Active to precharge command

Active to active/auto refresh command

time

tRC

60

65

ns

Active to read or write command delay tRCD

15

20

ns

Precharge command period

Active to auto-precharge delay

tRP

15

20

tRAP

tRCD min.

Active bank A to active bank B

command period

tRRD

tWR

7.5

10

ns

Write recovery time

15

ns

Auto precharge write recovery +

precharge time

(tWR/tCK)+

(tRP/tCK)

(tWR/tCK)+

(tRP/tCK)

tDAL

tCK

1

2

Internal write to read command delay

Exit self refresh to any command

tWTR

tXSC

7.5

10

ns

200

tCK

Exit power down to any non-read

command

tXPNR

tXPRD

2

tCK

Exit precharge power down to read

command

6 – AL

Exit active power down to read

command

tXARD

tOIT

2

tCK

ns

Output impedance test driver delay

0

32

0

32

Auto refresh to active/auto refresh

command time

tRFC

tREFI

120

ns

Average periodic refresh interval

7.8

µs

Note: 1. For each of the terms above, if not already an integer, round to the next highest integer.

2. AL: Additive Latency.

Preliminary Data Sheet E0203E41 (Ver. 4.1)

7

EDE5104GASA, EDE5108GASA

Test Conditions

tCK

VDD

CLK

VREF

VX

VSWING

/CLK

VSS

tCL

tCH

VDD

VIH

VREF

VIL

VSS

∆t

SLEW = (VIH (ac) – VIL (ac))/∆t

Measurement point

DQ

VTT

RT =25 Ω

Preliminary Data Sheet E0203E41 (Ver. 4.1)

8

EDE5104GASA, EDE5108GASA

Block Diagram

CK

/CK

CKE

Bank 3

Bank 2

Bank 1

A0 to A12, BA0, BA1

Row

address

buffer

and

Memory cell array

Bank 0

refresh

counter

Mode

register

Sense amp.

Column decoder

Column

address

buffer

and

/CS

/RAS

/CAS

/WE

burst

counter

Data control circuit

Latch circuit

DQS, /DQS

RDQS, /RDQS

DM

CK, /CK

DLL

Input & Output buffer

DQ

Preliminary Data Sheet E0203E41 (Ver. 4.1)

9

EDE5104GASA, EDE5108GASA

Pin Function

CK, /CK (input pins)

CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the

positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK

(both directions of crossing).

/CS (input pin)

All commands are masked when /CS is registered High. /CS provides for external bank selection on systems with

multiple banks. /CS is considered part of the command code.

/RAS, /CAS, /WE (input pins)

/RAS, /CAS and /WE (along with /CS) define the command being entered.

A0 to A12 (input pins)

Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write

commands to select one location out of the memory array in the respective bank.

[Address Pins Table]

Address (A0 to A12)

Part number

EDE5104GA

EDE5108GA

Row address

AX0 to AX12

Column address

AY0 to AY9, AY11, AY12

AY0 to AY9, AY11

A10 (AP) (input pin)

A10 is sampled during a precharge command to determine whether the precharge applies to one bank (A10 = Low)

or all banks (A10 = High). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address

inputs also provide the op-code during mode register set commands.

BA0, BA1 (input pins)

BA0 and BA1 define to which bank an active, read, write or precharge command is being applied. BA0 also

determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle.

[Bank Select Signal Table]

BA0

L

BA1

L

Bank 0

Bank 1

H

L

Bank 2

L

H

Bank 3

H

Remark: H: VIH. L: VIL.

CKE (input pin)

CKE High activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers.

Taking CKE Low provides precharge power-down and Self Refresh operation (all banks idle), or active power-down

(row active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is

asynchronous for self refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers,

excluding CK, /CK and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self

refresh.

Preliminary Data Sheet E0203E41 (Ver. 4.1)

10

EDE5104GASA, EDE5108GASA

DM (input pin)

DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with that input

data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM

loading matches the DQ and DQS loading. For ×8 configuration, DM function will be disabled when RDQS function

is enabled by EMRS.

DQ (input/output pins)

Bi-directional data bus.

DQS, /DQS (input/output pins)

Output with read data, input with write data for source synchronous operation. Edge-aligned with read data,

centered in write data. Used to capture write data. /DQS can be disabled by EMRS.

RDQS, /RDQS (output pins)

Differential Data Strobe for READ operation only. DM and RDQS functions are switchable by EMRS. These pins

exist only in ×8 configuration. /RDQS output will be disabled when /DQS is disabled by EMRS.

VDD, VSS, VDDQ, VSSQ (power supply)

VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output

buffers.

VDDL and VSSDL (power supply)

VDDL and VSSDL are power supply pins for DLL circuits.

VREF (Power supply)

SSTL_18 reference voltage: (0.50 ± 0.01) × VDDQ

Preliminary Data Sheet E0203E41 (Ver. 4.1)

11

EDE5104GASA, EDE5108GASA

Command Operation

Command Truth Table

The DDR-II SDRAM recognizes the following commands specified by the /CS, /RAS, /CAS, /WE and address pins.

CKE

Previous Current

BA1,

A12 to

A11

A0 to

A10 A9

Function

Symbol cycle

cycle

/CS /RAS /CAS /WE BA0

Notes

Mode register set

Extended mode register set

Auto (CBR) refresh

Entry self refresh

Exit self refresh

MRS

H

L

×

L

H

L

H

×

L

×

L

H

×

L

×

H

L

H

×

L

BA0 = 0 and MRS OP Code

BA0 = 1 and EMRS OP Code

1

EMRS

REF

×

L

1

H

L

H

×

L

H

×

1

SELF

SELFX

PRE

×

1

H

×

1

Single bank precharge

Precharge all banks

Bank activate

H

×

L

BA

×

1, 2

1

PALL

ACT

×

L

×

H

L

BA

×

Row Address

Column L

Column H

Column L

Column H

1, 2

Write

WRIT

WRITA

READ

READA

NOP

×

Column 1, 2, 3

Write with auto precharge

Read

×

L

×

H

×

Read with auto precharge

No operation

×

1

Device deselect

DESL

PDEN

PDEX

×

1

Power down mode entry

Power down mode exit

L

×

1, 4, 5

×

H

×

Remark: H = VIH. L = VIL. × = VIH or VIL

Notes: 1. All of the DDR-II SDRAM operations are defined by states of /CS, /WE, /RAS, and /CAS at the positive

rising edge of the clock.

2. Bank Select (BA0, BA1), determine which bank is to be operated upon.

3. Burst read or write cycle may not be terminated.

4. The Power Down Mode does not perform any refresh operations; therefore the device can’t remain in this

mode longer than the Refresh period (tREF) of the device. One clock delay is required for mode entry and

exit.

5. If /CS is low, then when CKE returns high, no command is registered into the chip for one clock cycle.

Preliminary Data Sheet E0203E41 (Ver. 4.1)

12

EDE5104GASA, EDE5108GASA

CKE Truth Table

CKE

Command

Current

Cycle

BA1,BA0,

Current state

Self refresh

Function

/CS /RAS /CAS /WE A12 to A0 Notes

INVALID

H

L

×

1

2

Exit self refresh with device

deselect

H

Exit self refresh with no

operation

L

H

L

H

×

2

Illegal

L

H

L

H

L

×

H

Command

Address

Maintain self refresh

INVALID

×

Power down

All banks idle

×

1

2

Power down mode exit

H

Command

except NOP

ILLEGAL

L

H

L

Address

2

Maintain power down mode

Device deselect

L

×

H

3

Refer to the current state truth

table

H

L

H

L

×

Command

Address

Power down

×

Register command begin power

down next cycle

L

Command

Address

3

4

Entry self refresh

L

H

×

Refer to operations in the

current state truth table

Any state other

than listed

above

H

×

Power down entry

ILLEGAL

H

L

×

5

×

Remark: H = VIH. L = VIL. × = VIH or VIL

Notes: 1. For the given Current State CKE must be low in the previous cycle.

2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The

minimum setup time for CKE (tCES) must be satisfied before any command other than self refresh exit.

3. The inputs (BA1, BA0, A12 to A0) depend on the command that is issued. See the Command Truth Table

for more information.

4. The Auto Refresh, Self Refresh mode, and the Mode Register Set modes can only be entered from the all

banks idle state.

5. Must be a legal command as defined in the Command Truth Table.

Preliminary Data Sheet E0203E41 (Ver. 4.1)

13

EDE5104GASA, EDE5108GASA

Function Truth Table

The following tables show the operations that are performed when each command is issued in each state of the

DDR SDRAM.

Current state

/CS /RAS /CAS /WE Address

Command Operation

Notes

Idle

H

L

H

L

H

L

×

H

L

×

H

L

H

L

×

H

L

H

L

×

H

L

H

L

×

DESL

NOP

Nop or Power down

H

L

×

Nop or Power down

ILLEGAL

BA, CA, A10 (AP)

BA, RA

READ

READA

WRIT

WRITA

ACT

1

ILLEGAL

L

ILLEGAL

H

L

Row activating

Precharge

L

BA, A10 (AP)

A10 (AP)

PRE

L

PALL

REF

Precharge all banks

Auto refresh

Self refresh

L

H

L

×

2

L

×

SELF

MRS

L

BA, MRS-OPCODE

Mode register accessing

Extended mode register accessing

Nop

L

BA, EMRS-OPCODE EMRS

Bank(s) active

×

DESL

NOP

H

L

H

L

×

Nop

BA, CA, A10 (AP)

BA, RA

READ

READA

WRIT

WRITA

ACT

Begin Read

Begin Write

L

Begin Write

H

L

ILLEGAL

1

L

BA, A10 (AP)

A10 (AP)

PRE

Precharge

L

PALL

REF

Precharge all banks

ILLEGAL

L

H

L

×

L

×

SELF

MRS

ILLEGAL

L

BA, MRS-OPCODE

ILLEGAL

L

BA, EMRS-OPCODE EMRS

ILLEGAL

Read

×

DESL

NOP

Continue burst to end -> Row active

ILLEGAL

H

L

H

L

×

BA, CA, A10 (AP)

BA, RA

READ

READA

WRIT

WRITA

ACT

1

ILLEGAL

L

ILLEGAL

H

L

ILLEGAL

L

BA, A10 (AP)

A10 (AP)

PRE

ILLEGAL

L

PALL

REF

ILLEGAL

L

H

L

×

ILLEGAL

L

×

SELF

MRS

ILLEGAL

L

BA, MRS-OPCODE

ILLEGAL

L

BA, EMRS-OPCODE EMRS

ILLEGAL

Preliminary Data Sheet E0203E41 (Ver. 4.1)

14

EDE5104GASA, EDE5108GASA

Current state

Write

/CS /RAS /CAS /WE Address

Command

DESL

Operation

Note

Continue burst to end

-> Write recovering

H

L

×

Continue burst to end

-> Write recovering

H

NOP

L

H

L

H

L

H

L

×

H

L

H

L

H

L

BA, CA, A10 (AP)

BA, RA

READ

READA

WRIT

WRITA

ACT

ILLEGAL

1

ILLEGAL

L

ILLEGAL

H

L

ILLEGAL

L

BA, A10 (AP)

A10 (AP)

PRE

ILLEGAL

L

PALL

REF

ILLEGAL

L

H

L

×

ILLEGAL

L

×

SELF

MRS

ILLEGAL

L

BA, MRS-OPCODE

ILLEGAL

L

BA, EMRS-OPCODE EMRS

ILLEGAL

Read with

×

H

L

×

DESL

NOP

Continue burst to end -> Precharging

auto precharge

H

L

×

Continue burst to end -> Precharging

BA, CA, A10 (AP)

BA, RA

READ

READA

WRIT

WRITA

ACT

ILLEGAL

1

L

H

L

BA, A10 (AP)

A10 (AP)

PRE

L

PALL

REF

L

H

L

×

L

×

SELF

MRS

L

BA, MRS-OPCODE

L

BA, EMRS-OPCODE EMRS

Write with auto

Precharge

Continue burst to end

->Write recovering with auto precharge

H

L

×

DESL

NOP

Continue burst to end

->Write recovering with auto precharge

H

L

H

L

H

L

H

L

BA, CA, A10 (AP)

BA, RA

READ

READA

WRIT

WRITA

ACT

ILLEGAL

1

L

H

L

BA, A10 (AP)

A10 (AP)

PRE

L

PALL

REF

L

H

L

×

L

×

SELF

MRS

L

BA, MRS-OPCODE

L

BA, EMRS-OPCODE EMRS

Preliminary Data Sheet E0203E41 (Ver. 4.1)

15

EDE5104GASA, EDE5108GASA

Current state

Precharging

/CS /RAS /CAS /WE Address

Command

DESL

NOP

Operation

Note

H

L

H

L

H

L

×

H

L

×

H

L

H

L

×

H

L

H

L

×

H

L

H

L

×

Nop -> Enter idle after tRP

H

L

×

Nop -> Enter idle after tRP

BA, CA, A10 (AP)

BA, RA

READ

READA

WRIT

WRITA

ACT

ILLEGAL

1

ILLEGAL

L

ILLEGAL

H

L

ILLEGAL

L

BA, A10 (AP)

A10 (AP)

PRE

Nop -> Enter idle after tRP

L

PALL

REF

Nop -> Enter idle after tRP

L

H

L

×

ILLEGAL

L

×

SELF

MRS

ILLEGAL

L

BA, MRS-OPCODE

BA, EMRS-OPCODE

×

ILLEGAL

L

EMRS

DESL

NOP

ILLEGAL

Row activating

×

Nop -> Enter bank active after tRCD

H

L

H

L

×

Nop -> Enter bank active after tRCD

BA, CA, A10 (AP)

BA, RA

READ

READA

WRIT

WRITA

ACT

ILLEGAL

1

ILLEGAL

L

ILLEGAL

H

L

ILLEGAL

L

BA, A10 (AP)

A10 (AP)

PRE

ILLEGAL

L

PALL

REF

ILLEGAL

L

H

L

×

ILLEGAL

L

×

SELF

MRS

ILLEGAL

L

BA, MRS-OPCODE

BA, EMRS-OPCODE

×

ILLEGAL

L

EMRS

DESL

NOP

ILLEGAL

Write recovering

×

Nop -> Enter bank active after tWR

ILLEGAL

H

L

H

L

×

BA, CA, A10 (AP)

BA, RA

READ

READA

WRIT

WRITA

ACT

1

ILLEGAL

New write

L

New write

H

L

ILLEGAL

1

L

BA, A10 (AP)

A10 (AP)

PRE

ILLEGAL

L

PALL

REF

ILLEGAL

L

H

L

×

ILLEGAL

L

×

SELF

MRS

ILLEGAL

L

BA, MRS-OPCODE

BA, EMRS-OPCODE

ILLEGAL

L

EMRS

ILLEGAL

Preliminary Data Sheet E0203E41 (Ver. 4.1)

16

EDE5104GASA, EDE5108GASA

Current state

/CS /RAS /CAS /WE Address

Command

DESL

Operation

Note

Write recovering

with

H

×

Nop -> Enter bank active after tWR

auto precharge

L

H

L

H

L

H

L

H

L

×

H

L

H

L

H

L

×

NOP

Nop -> Enter bank active after tWR

ILLEGAL

BA, CA, A10 (AP)

BA, RA

READ

READA

WRIT

WRITA

ACT

1

ILLEGAL

L

ILLEGAL

H

L

ILLEGAL

L

BA, A10 (AP)

A10 (AP)

PRE

ILLEGAL

L

PALL

REF

ILLEGAL

L

H

L

×

ILLEGAL

L

×

SELF

MRS

ILLEGAL

L

BA, MRS-OPCODE

BA, EMRS-OPCODE

×

ILLEGAL

L

EMRS

DESL

NOP

ILLEGAL

Refresh

×

Nop -> Enter idle after tRFC

ILLEGAL

H

L

H

L

×

BA, CA, A10 (AP)

BA, RA

READ

READA

WRIT

WRITA

ACT

ILLEGAL

L

ILLEGAL

H

L

ILLEGAL

L

BA, A10 (AP)

A10 (AP)

PRE

ILLEGAL

L

PALL

REF

ILLEGAL

L

H

L

×

ILLEGAL

L

×

SELF

MRS

ILLEGAL

L

BA, MRS-OPCODE

BA, EMRS-OPCODE

ILLEGAL

L

EMRS

ILLEGAL

Mode register

accessing

H

×

DESL

Nop -> Enter idle after tMRD

L

H

L

H

L

H

L

H

L

×

NOP

Nop -> Enter idle after tMRD

ILLEGAL

BA, CA, A10 (AP)

BA, RA

READ

READA

WRIT

WRITA

ACT

ILLEGAL

L

ILLEGAL

H

L

ILLEGAL

L

BA, A10 (AP)

A10 (AP)

PRE

ILLEGAL

L

PALL

REF

ILLEGAL

L

H

L

×

ILLEGAL

L

×

SELF

MRS

ILLEGAL

L

BA, MRS-OPCODE

BA, EMRS-OPCODE

ILLEGAL

L

EMRS

ILLEGAL

Preliminary Data Sheet E0203E41 (Ver. 4.1)

17

EDE5104GASA, EDE5108GASA

Current state

/CS

H

L

/RAS /CAS /WE Address

Command

DESL

NOP

Operation

Note

Extended Mode

register accessing

×

H

L

×

H

L

H

L

×

Nop -> Enter idle after tMRD

ILLEGAL

H

L

×

L

BA, CA, A10 (AP)

BA, RA

READ

READA

WRIT

WRITA

ACT

L

ILLEGAL

L

ILLEGAL

L

ILLEGAL

L

H

L

ILLEGAL

L

BA, A10 (AP)

A10 (AP)

PRE

ILLEGAL

L

PALL

REF

ILLEGAL

L

H

L

×

ILLEGAL

L

×

SELF

MRS

ILLEGAL

L

BA, MRS-OPCODE

BA, EMRS-OPCODE

ILLEGAL

L

EMRS

ILLEGAL

Remark: H = VIH. L = VIL. × = VIH or VIL

Notes: 1. This command may be issued for other banks, depending on the state of the banks.

2. All banks must be in "IDLE".

3. All AC timing specs must be met.

Preliminary Data Sheet E0203E41 (Ver. 4.1)

18

EDE5104GASA, EDE5108GASA

Simplified State Diagram

Power

Applied

POWER

ON

PRECHARGE

PREALL

SELF

REFRESH

REFS

REFSX

MRS

REFA

MRS

EMRS

AUTO

REFRESH

IDLE

*NOTE

CKEL

CKEH

ACT

ACTIVE

POWER

DOWN

PRECHARGE

POWER

DOWN

CKEH

CKEL

ROW

ACTIVE

WRITE

READ

WRITA

READA

WRITE

READ

WRITA

READA

PRECHARGE

PRECHARGE PRECHARGE

WRITA

READA

PRECHARGE

PREALL

PRECHARGE

Automatic sequence

Command sequence

*Note : Except drive mode activated by EMRS, drive mode should be deactivated by

EMRS to move to an idle state.

Simplified State Diagram

Preliminary Data Sheet E0203E41 (Ver. 4.1)

19

EDE5104GASA, EDE5108GASA

Operation of DDR-II SDRAM

Read and write accesses to the DDR-II SDRAM are burst oriented; accesses start at a selected location and

continue for the fixed burst length of four in a programmed sequence. Accesses begin with the registration of an

Active command, which is then followed by a Read or Write command. The address bits registered coincident with

the active command is used to select the bank and row to be accessed (BA0, BA1 select the bank; A0 to A12 select

the row). The address bits registered coincident with the Read or Write command are used to select the starting

column location for the burst access and to determine if the auto precharge command is to be issued. Prior to

normal operation, the DDR-II SDRAM must be initialized. The following sections provide detailed information

covering device initialization; register definition, command descriptions and device operation.

Power On and Initialization

DDR-II SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than

those specified may result in undefined operation. Power must first be applied to VDD, then to VDDQ, and finally to

VREF (and to the system VTT). VTT must be applied after VDDQ to avoid device latch-up, which may cause

permanent damage to the device. VREF can be applied any time after VDDQ, but is expected to be nominally

coincident with VTT. The DQ and DQS outputs are in the High-Z state, where they remain until driven active in

normal operation (by a read access). After all power supply, reference voltages, and the clocks are stable, the DDR-

II SDRAM requires a 200µs delay prior to applying an executable command.

Once the 200µs delay has been satisfied, a Deselect or NOP command should be applied, and CKE must be

brought High. Following the NOP command, a Precharge ALL command must be applied. Next a mode register set

command must be issued for the extended mode register, to enable the DLL. Then a mode register set command

must be issued for the mode register, to reset the DLL and to program the operating parameters. 200 clock cycles

are required between the DLL reset and any read command. A Precharge ALL command should be applied, placing

the device in the “all banks idle” state.

Once in the idle state, two Auto Refresh cycles must be performed. Additionally, a mode register set command for

the mode register, with the reset DLL bit deactivated (i.e. to program operating parameters without resetting the DLL)

must be performed. Following these cycles, the DDR-II SDRAM is ready for normal operation. Failure to follow

these steps may lead to unpredictable start-up modes.

Power-Up and Initialization Sequence

The following sequence is required for power-up and Initialization.

1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.)

Apply VDD before or at the same time as VDDQ.

Apply VDDQ before or at the same time as VTT and VREF.

2. Start clock and maintain stable condition for a minimum of 200µs.

3. The minimum of 200µs after stable power and clock (CK, /CK), apply NOP and take CKE High.

4. Wait tRFC.

5. Issue precharge commands for all banks of the device.

6. Issue EMRS to enable DLL. (To issue DLL Enable command, provide Low to A0, High to BA0 and Low to all of

the rest address pins, A1 to A11 and BA1)

7. Issue a mode register set command for DLL reset. The additional 200 cycles of clock input is required to lock the

DLL. (To issue DLL reset command, provide High to A8 and Low to BA0)

8. Issue precharge commands for all banks of the device.

9. Issue 2 or more auto-refresh commands.

10.Issue a mode register set command with Low to A8 to initialize device operation.

11.Carry out OCD impedance adjustment (Follow “OCD Flow Chart” in the chapter of Off-Chip Driver (OCD)

Impedance Adjustment). Whenever issue extended mode register set command for OCD, keep previous setting

of A0 to A6, A0 to A12 and BA1

/CK

CK

Any

command

Command

PALL

2 cycles (min.) 2 cycles (min.) 2 cycles (min.)

DLL reset

EMRS

MRS

PALL

REF

MRS

EMRS

REF

tRP

tRFC

tMRD

2 cycles (min.)

Follow OCD

Flowchart

DLL enable

OCD mode set

OCD calibration

exit

200 cycles (min)

Power up and Initialization Sequence

Preliminary Data Sheet E0203E41 (Ver. 4.1)

20

EDE5104GASA, EDE5108GASA

Programming the Mode Register

For application flexibility, burst type, /CAS latency, DLL reset function are user defined variables and must be

programmed with a Mode Register Set (MRS) command. Additionally, DLL disable function, additive /CAS latency,

and variable data-output impedance adjustment are also user defined variables and must be programmed with an

Extended Mode Register Set (EMRS) command. Re-executing the MRS and EMRS Commands can alter contents

of the MRS and EMRS. If the user chooses to modify only a subset of the MRS or EMRS variables, all variables

must be redefined when the MRS or EMRS commands are issued.

After initial power up, the both MRS and EMRS Commands must be issued before read or write cycles may begin.

All four banks must be in a precharged state and CKE must be high at least one cycle before the Mode Register Set

Command can be issued. Either MRS or EMRS Commands are activated by the low signals of /CS, /RAS, /CAS and

/WE at the positive edge of the clock. When the bank address 0 (BA0) is low, the DDR-II SDRAM enables the MRS

command. When the bank address 0 (BA0) is high, the DDR-II SDRAM enables the EMRS command. The address

input data during this cycle defines the parameters to be set as shown in the MRS and EMRS table. A new

command may be issued after the mode register set command cycle time (tMRD). MRS, EMRS and Reset DLL do

not affect array contents, which means reinitialization including those can be executed any time after power-up

without affecting array contents.

DDR-II SDRAM Mode Register Set [MRS]

The mode register stores the data for controlling the various operating modes of DDR-II SDRAM. It controls /CAS

latency, burst sequence, test mode, DLL reset and various vendor specific options to make DDR-II SDRAM useful

for various applications. The default value of the mode register is not defined, therefore the mode register must be

written after power-up for proper operation. The mode register is written by asserting low on /CS, /RAS, /CAS, /WE

and BA0, while controlling the state of address pins A0 to A12. The DDR-II SDRAM should be in all bank precharge

with CKE already high prior to writing into the mode register. The mode register set command cycle time (tMRD) is

required to complete the write operation to the mode register. The mode register contents can be changed using the

same command and clock cycle requirements during normal operation as long as all banks are in the precharge

state. The mode register is divided into various fields depending on functionality. Burst address sequence type is

defined by A3, and, /CAS latency is defined by A4 to A6. The DDR-II doesn’t support half clock latency mode. A7 is

used for test mode. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Refer to the table for

specific codes.

BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Address field

0*

0

0*

tWR

DLL TM /CAS latency BT Burst length*²

Mode register

Burst length

A8

0

DLL reset

No

A7

0

Mode

Normal

Test

A3

0

Burst type

Sequential

Interleave

A2

0

A1

1

A0

0

BL

4

1

Yes

1

tWR

A11 A10 A9

/CAS latency

BA0

0

MRS mode

MRS

tWR

Reserved

2

A6

0

A5

0

A4

0

Latency

Reserved

0

1

0

1

0

1

0

1

0

1

0

1

0

1

EMRS

0

1

Reserved

3

0

1

0

4

0

1

Reserved

1

0

4

1

0

1

Reserved

1

0

1

*BA1 and A12 are reserved for future use and must be programmed to 0 when setting the mode register.

Mode Register Set (MRS)

Preliminary Data Sheet E0203E41 (Ver. 4.1)

21

EDE5104GASA, EDE5108GASA

DDR-II SDRAM Extended Mode Register Set [EMRS]

The extended mode register stores the data for enabling or disabling the DLL, output driver strength and additive

latency. The default value of the extended mode register is not defined, therefore the extended mode register must

be written after power-up for proper operation. The extended mode register is written by asserting low on /CS, /RAS,

/CAS, /WE and High on BA0, while controlling the states of address pins A0 to A12. The DDR-II SDRAM should be

in all bank precharge with CKE already high prior to writing into the extended mode register. The mode register set

command cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register. Mode

register contents can be changed using the same command and clock cycle requirements during normal operation

as long as all banks are in the precharge state. A0 is used for DLL enable or disable. A1 is used for enabling a half

strength data-output driver. A3 to A5 determines the additive latency, A7 to A9 are used for OCD control, A10 is

used for DQS disable and A11 is used for RDQS enable.

DLL Enable/Disable

The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon

returning to normal operation after having the DLL disabled. The DLL is automatically disabled when entering self

refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled

(and subsequently reset), 200 clock cycles must occur before a Read command can be issued to allow time for the

internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a

violation of the tAC or tDQSCK parameters.

BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Address field

0*¹

1

0*¹RDQS /DQS OCD program RFU Additive latency RFU D.I.C DLL

Extended mode register

A10 /DQS disable

0

1

Enable

Disable

A11 RDQS enable

A0

0

DLL enable

Enable

0

1

Disable

Enable

1

Disable

Additive latency

BA0

0

MRS mode

MRS

A5

0

A4

0

A3

0

Latency

0

1

EMRS

0

1

Driver impedance adjustment

0

1

0

2

Operation

OCD calibration mode exit

Driver(1) DQ High

Driver(0) DQ Low

Adjust mode

A9

0

A8

0

A7

0

1

3

1

0

Reserved

0

1

0

1

0

1

0

1

0

1

0

1

Reserved

*Refer to the chapter "Off-chip Driver (OCD) impedance Adjustment"

for detailed information

Driver strength control

Output Driver

Driver

Size

A1

0

Impedance Control

Normal

100%

1

Weak

Reserved

*BA1 and A12 to A15 are reserved for future use, and must be programmed to 0 when setting the extended mode register.

Extended Mode Register Set (EMRS)

Preliminary Data Sheet E0203E41 (Ver. 4.1)

22

EDE5104GASA, EDE5108GASA

Off-Chip Driver (OCD) Impedance Adjustment

DDR-II SDRAM supports driver calibration feature and the “OCD Flow Chart ” is an example of sequence. Every

calibration mode command should be followed by “OCD calibration mode exit” before any other command being

issued. MRS should be set before entering OCD impedance adjustment.

Start

EMRS: OCD calibration mode exit

EMRS: Drive(1)

DQ ; High

EMRS: Drive(0)

DQ ; Low

ALL OK

Test

Need calibration

EMRS: OCD calibration mode exit

EMRS :

Enter Adjust Mode

BL=4 code input to all DQs

Inc, Dec, or NOP

BL=4 code input to all DQs

Inc, Dec, or NOP

EMRS: OCD calibration mode exit

End

OCD Flow Chart

Preliminary Data Sheet E0203E41 (Ver. 4.1)

23

EDE5104GASA, EDE5108GASA

Extended Mode Register Set for OCD Impedance Adjustment

OCD impedance adjustment can be done using the following EMRS mode. In drive mode, all outputs are driven out

by DDR-II SDRAM. In drive (1) mode, all DQ signals are driven high. In drive (0) mode, all DQ signals are driven

low.

In adjust mode, BL = 4 of operation code data must be used.

OCD must used to control driver impedance within 18Ω ± 3Ω range.

[OCD Mode Set Program]

A9

0

A8

0

A7

0

Operation

OCD calibration mode exit

Drive (1) DQ High

Drive (0) DQ Low

Adjust mode

0

1

0

1

0

1

0

1

Reserved

OCD Impedance Adjustment

OCD impedance adjustment can be done using “EMRS Adjust mode” and input operation code patterns as the table

of “OCD Adjustment Program”. To adjust output driver impedance, controllers must issue “Adjust mode” command

using an EMRS command first, after that drive 4 bits of burst code information to DDR-II SDRAM. For this operation,

controllers must drive all DQs to each device. Driver impedance in each DDR-II SDRAM device is adjusted for all

DQs simultaneously. The maximum step count for adjustment is 16 and when the limit is reached, further increment

or decrement has no effect. Default setting can be any step within the 16 steps range.

[OCD Adjustment Program]

4bits burst data inputs to all DQs

Operation

DT0

0

DT1

0

DT2

0

DT3

0

Pull-up driver strength

NOP

Pull-down driver strength

NOP

0

1

Increase by 1 step

Decrease by 1 step

NOP

0

1

0

NOP

0

1

0

Increase by 1 step

Decrease by 1 step

Reserved

1

0

NOP

0

1

0

1

Reserved

0

1

0

Reserved

1

0

1

Reserved

1

0

1

0

Reserved

Other combinations

Reserved

Preliminary Data Sheet E0203E41 (Ver. 4.1)

24

EDE5104GASA, EDE5108GASA

For proper operation of adjust mode, WL = RL − 1 = AL + CL − 1 clocks and tDS/tDH should be met as the “Output

Impedance Control Register Set Cycle”. For input data pattern for adjustment, DT0 to DT3 is a fixed order and not

affected by MRS addressing mode (i.e. sequential or interleave).

/CK

CK

Command

EMRS

NOP

WL

NOP

tWR

EMRS

NOP

DQS, /DQS

tDS tDH

DT0

DQ_in

DT1

DT2

DT3

OCD adjust mode

OCD calibration mode exit

Output Impedance Control Register Set Cycle

Drive Mode

Drive mode, both drive (1) and drive (0), is used for controllers to measure DDR-II SDRAM Driver impedance before

OCD impedance adjustment. In this mode, all outputs are driven out tOIT after “Enter drive mode” command and all

output drivers are turned-off tOIT after “OCD calibration mode exit” command as the ”Output Impedance

Measurement/Verify Cycle”.

/CK

CK

Command

EMRS

NOP

EMRS

High-Z

DQS, /DQS

DQs High for drive (1)

DQs Low for drive (0)

DQ

tOIT

(0 to 32ns)

tOIT

(0 to 32ns)

Enter drivemode

OCD Calibration mode exit

Output Impedance Measurement/Verify Cycle

Preliminary Data Sheet E0203E41 (Ver. 4.1)

25

EDE5104GASA, EDE5108GASA

Bank Activate Command [ACT]

The bank activate command is issued by holding /CAS and /WE High with /CS and /RAS Low at the rising edge of

the clock. The bank addresses BA0 and BA1, are used to select the desired bank. The row address A0 through

A12 is used to determine which row to activate in the selected bank. The Bank activate command must be applied

before any read or write operation can be executed. Immediately after the bank active command, the DDR-II

SDRAM can accept a read or write command on the following clock cycle. If a R/W command is issued to a bank

that has not satisfied the tRCD (min.) specification, then additive latency must be programmed into the device to

delay when the R/W command is internally issued to the device. The additive latency value must be chosen to

assure tRCD (min.) is satisfied. Additive latencies of 0, 1 and 2 are supported. Once a bank has been activated it

must be precharged before another bank activate command can be applied to the same bank. The bank active and

precharge times are defined as tRAS and tRP, respectively. The minimum time interval between successive bank

activate commands to the same bank is determined by the /RAS cycle time of the device (tRC), which is equal to

tRAS + tRP. The minimum time interval between successive bank activate commands to the different bank is

determined by (tRRD).

T0

T1

T2

T3

Tn

Tn+1

Tn+2

PRE

Tn+3

/CK

CK

Posted

READ

Posted

READ

Command

ACT

PRE

ACT

tRCD(min.)

Address

ROW: 0

COL: 0

ROW: 1

tCCD

COL: 1

ROW: 0

Bank0 Read begins

Additive latency (AL)

tRCD =1

tRRD

tRAS

tRP

tRC

Bank0

Active

Bank1

Active

Bank0

Precharge

Bank1

Precharge Active

Bank0

Bank Activate Command Cycle (tRCD = 3, AL = 2, tRP = 3, tRRD = 2, tCCD = 2)

Preliminary Data Sheet E0203E41 (Ver. 4.1)

26

EDE5104GASA, EDE5108GASA

Read and Write Access Modes

After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting /RAS High,

/CS and /CAS Low at the clock’s rising edge. /WE must also be defined at this time to determine whether the access

cycle is a read operation (/WE high) or a write operation (/WE low).

The DDR-II SDRAM provides a fast column access operation. A single read or write Command will initiate a serial

read or write operation on successive clock cycles. The boundary of the burst cycle is strictly restricted to specific

segments of the page length. For example, the 8M bits × 4 I/O × 4 Banks chip has a page length of 2048 bits

(defined by CA0 to CA9, CA11). The page length of 2048 is divided into 512 uniquely addressable boundary

segments (4 bits each). A 4 bits burst operation will occur entirely within one of the 512 groups beginning with the

column address supplied to the device during the read or write Command (CA0 to CA9, CA11). The second, third

and fourth access will also occur within this group segment, however, the burst order is a function of the starting

address, and the burst sequence.

A new burst access must not interrupt the previous 4-bit burst operation. The minimum /CAS to /CAS delay is

defined by tCCD, and is a minimum of 2 clocks for read or write cycles.

Posted /CAS

Posted /CAS operation is supported to make command and data bus efficient for sustainable bandwidths in DDR-II

SDRAM. In this operation, the DDR-II SDRAM allows a /CAS read or write command to be issued immediately after

the /RAS bank activate command (or any time during the /RAS-/CAS-delay time, tRCD, period). The command is

held for the time of the additive latency (AL) before it is issued inside the device. The Read Latency (RL) is

controlled by the sum of AL and the /CAS latency (CL). Therefore if a user chooses to issue a R/W command before

the tRCD (min), then AL (greater than 0) must be written into the EMRS. The Write Latency (WL) is always defined

as RL − 1 (read latency −1) where read latency is defined as the sum of additive latency plus /CAS latency

(RL=AL+CL).

-1

0

1

2

3

4

5

6

7

8

9

10

11

12

/CK

CK

Command

DQS, /DQS

DQ

READ

ACT

WRIT

WL = RL n–1 = 4

AL = 2

CL = 3

> tRCD

=

RL = AL + CL = 5

out0 out1 out2 out3

in0 in1 in2 in3

> tRAC

=

Read followed by a write to the same bank

[AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4]

-1

0

1

2

3

4

5

6

7

8

9

10

11

12

/CK

CK

AL = 0

READ

Command

DQS, /DQS

DQ

ACT

WRIT

CL = 3

WL = RL n–1 = 2

> tRCD

=

RL = AL + CL = 3

out0 out1 out2 out3

in0 in1 in2 in3

> tRAC

=

Read followed by a write to the same bank

[AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2]

Preliminary Data Sheet E0203E41 (Ver. 4.1)

27

EDE5104GASA, EDE5108GASA

Fixed 4 bits Burst Mode Operation

Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory

locations (read cycle). The parameters that define how the burst mode will operate are burst sequence and burst

length. Unlike the DDR-I SDRAM, DDR-II SDRAM supports 4 bits burst mode only. The burst type, either

sequential or interleaved, is programmable and defined by the address bit 3 (A3) of the MRS, which is similar to the

DDR-I SDRAM operation. Seamless burst read or write operations are supported.

Unlike DDR-I devices, interruption of a burst read or write operation is prohibited. Therefore the burst stop command

is not supported on DDR-II SDRAM devices.

[Burst Length and Sequence]

Burst length

Starting address (a1, a0)

Sequential addressing (decimal)

Interleave addressing (decimal)

00

01

10

11

0, 1, 2, 3

1, 2, 3, 0

2, 3, 0, 1

3, 0, 1, 2

0, 1, 2, 3

1, 0, 3, 2

2, 3, 0, 1

3, 2, 1, 0

4

Note: Page length is a function of I/O organization and column addressing

32M bits × 4 organization (CA0 to CA9, CA11, CA12); Page Length = 2048 bits

16M bits × 8 organization (CA0 to CA9, CA11); Page Length = 1024 bits

Preliminary Data Sheet E0203E41 (Ver. 4.1)

28

EDE5104GASA, EDE5108GASA

Burst Read Command [READ]

The Burst Read command is initiated by having /CS and /CAS low while holding /RAS and /WE high at the rising

edge of the clock. The address inputs determine the starting column address for the burst. The delay from the start

of the command to when the data from the first cell appears on the outputs is equal to the value of the read latency

(RL). The data strobe output (DQS) is driven low 1 clock cycle before valid data (DQ) is driven onto the data bus.

The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out

appears on the DQ pin in phase with the DQS signal in a source synchronous manner.

The RL is equal to an additive latency (AL) plus /CAS latency (CL). The CL is defined by the mode register set

(MRS), similar to the existing SDR and DDR-I SDRAMs. The AL is defined by the extended mode register set

(EMRS).

T0

T1

T2

T3

T4

T5

T6

T7

T8

/CK

CK

Posted

READ

NOP

<tDQSCK

NOP

Command

=

DQS, /DQS

AL = 2

CL = 3

RL = 5

out0 out1 out2 out3

DQ

Burst Read Operation (RL = 5 (AL = 2, CL = 3))

T0

T1

T2

T3

T4

T5

T6

T7

T8

/CK

CK

READ

NOP

Command

<tDQSCK

=

DQS, /DQS

DQ

CL = 3

RL = 3

Out0 Out1 Out2 Out3

Burst Read Operation (RL = 3 (AL = 0 and CL = 3))

Preliminary Data Sheet E0203E41 (Ver. 4.1)

29

EDE5104GASA, EDE5108GASA

T0

T1

T3

T4

T5

T6

T7

T8

T9

/CK

CK

Posted

READ

Posted

WRIT

NOP

Command

tRTW (Read to Write = 4 clocks)

DQS, /DQS

RL = 5

WL = RL - 1 = 4

out0 out1 out2 out3

in0

in1

in2

in3

DQ

Burst Read followed by Burst Write (RL = 5, WL = RL-1 = 4)

The minimum time from the burst read command to the burst write command is defined by a read-to-write-turn-

around-time, which is 4 clocks.

T0

T1

T2

T3

T4

T5

T6

T7

T8

/CK

CK

Posted

READ

Posted

READ

NOP

Command

DQS, /DQS

AL = 2

CL = 3

RL = 5

Out0 Out1 Out2 Out3 Out4 Out5 Out6

DQ

Seamless Burst Read Operation (RL = 5, AL = 2, and CL = 3)

Enabling a read command at every other clock supports the seamless burst read operation. This operation is

allowed regardless of same or different banks as long as the banks are activated.

Preliminary Data Sheet E0203E41 (Ver. 4.1)

30

EDE5104GASA, EDE5108GASA

Burst Write Command [WRIT]

The Burst Write command is initiated by having /CS, /CAS and /WE low while holding /RAS high at the rising edge of

the clock. The address inputs determine the starting column address. Write latency (WL) is defined by a read

latency (RL) minus one and is equal to (AL + CL −1). A data strobe signal (DQS) should be driven low (preamble)

one clock prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge

of the DQS following the preamble. The tDQSS specification must be satisfied for write cycles. The subsequent

burst bit data are issued on successive edges of the DQS until the burst length of 4 is completed. When the burst

has finished, any additional data supplied to the DQ pins will be ignored. The DQ Signal is ignored after the burst

write operation is complete. The time from the completion of the burst write to bank precharge is the write recovery

time (tWR).

T0

T1

T2

T3

T4

T5

T6

T7

T9

/CK

CK

Posted

WRIT

NOP

<tDQSS

NOP

PRE

Command

Completion of

the Burst Write

=

DQS, /DQS

DQ

>tWR

WL = RL −1 = 4

=

in0

in1

in2

in3

Burst Write Operation (RL = 5, WL = 4, tWR = 3 (AL=2, CL=3))

T0

T1

T2

T3

T4

T5

T6

T7

T9

/CK

CK

WRIT

NOP

<tDQSS

NOP

PRE

NOP

Command

ACT

Completion of

the Burst Write

=

DQS, /DQS

DQ

>tWR

>tRP

WL = RL –1 = 2

=

in0

in1

in2

in3

Burst Write Operation (RL = 3, WL = 2, tWR = 2 (AL=0, CL=3))

Preliminary Data Sheet E0203E41 (Ver. 4.1)

31

EDE5104GASA, EDE5108GASA

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

/CK

CK

Write to Read = CL + 1 + tWTR (2) = 6

NOP NOP

NOP

Posted

READ

NOP

Command

DQS, /DQS

DQ

AL = 2

CL = 3

WL = RL –1 = 4

RL = 5

>tWTR

=

out0 out1 out2 out3

Burst Write followed by Burst Read (RL = 5 (AL=2, CL=3), WL = 4, tWTR = 2)

The minimum number of clock from the burst write command to the burst read command is CL + 1 + a write to-read-

turn-around-time (tWTR). This tWTR is not a write recovery time (tWR) but the time required to transfer the 4bit

write data from the input buffer into sense amplifiers in the array.

T0

T1

T2

T3

T4

T5

T6

T7

T8

/CK

CK

Posted

WRIT

Posted

WRIT

Command

NOP

DQS, /DQS

WL = RL − 1 = 4

in 0 in 1 in 2 in 3 in 4 in 5 in 6 in 7

DQ

Seamless Burst Write Operation (RL = 5, WL = 4)

Enabling a write command every other clock supports the seamless burst write operation. This operation is allowed

regardless of same or different banks as long as the banks are activated.

Preliminary Data Sheet E0203E41 (Ver. 4.1)

32

EDE5104GASA, EDE5108GASA

Write data mask

One write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR-II SDRAMs, Consistent with the

implementation on DDR-I SDRAMs. It has identical timings on write operations as the data bits, and though used in

a uni-directional manner, is internally loaded identically to data bits to insure matched system timing. DM is not used

during read cycles.

T1

in

T2

T3

in

T4

in

T5

T6

DQS

/DQS

DQ

DM

in

Write mask latency = 0

Data Mask Timing

[tDQSS(min.)]

/CK

CK

tWR

WRIT

NOP

Command

NOP

tDQSS

DQS, /DQS

DQ

in0

in2 in3

DM

tDQSS

[tDQSS(max.)]

DQS, /DQS

DQ

in0

in2 in3

DM

Data Mask Function, WL = 3, AL = 0 shown

Preliminary Data Sheet E0203E41 (Ver. 4.1)

33

EDE5104GASA, EDE5108GASA

Precharge Command [PRE]

The precharge command is used to precharge or close a bank that has been activated. The precharge command is

triggered when /CS, /RAS and /WE are low and /CAS is high at the rising edge of the clock. The precharge

command can be used to precharge each bank independently or all banks simultaneously. Three address bits A10,

BA0 and BA1 are used to define which bank to precharge when the command is issued.

[Bank Selection for Precharge by Address Bits]

A10

L

BA0

L

BA1

L

Precharged Bank(s)

Bank 0 only

L

H

L

Bank 1 only

L

H

Bank 2 only

L

H

Bank 3 only

H

×

All banks 0 to 3

Remark: H: VIH, L: VIL, ×: VIH or VIL

Burst Read Operation Followed by Precharge

Minimum read to precharge command spacing to the same bank = AL + 2 clocks

For the earliest possible precharge, the precharge command may be issued on the rising edge that is

“Additive latency (AL) + 2 clocks” after a Read command. A new bank active (command) may be issued to the same

bank after the RAS precharge time (tRP). A precharge command cannot be issued until tRAS is satisfied.

T0

T1

T2

T3

T4

T5

T6

T7

T8

/CK

CK

Posted

READ

NOP

AL + 2 clocks

NOP

PRE

NOP

ACT

NOP

Command

DQS, /DQS

> t

RP

=

AL = 1

CL = 3

RL = 4

out0 out1 out2 out3

CL = 3

DQ

> t

RAS

=

Burst Read Operation Followed by Precharge (RL = 4 (AL=1, CL=3))

T0

T1

T2

T3

T4

T5

T6

T7

T8

/CK

CK

Posted

READ

ACT

NOP

AL + 2 clocks

NOP

PRE

NOP

Command

DQS, /DQS

> t

RP

=

AL = 2

CL = 3

RL = 5

out0 out1 out2 out3

CL = 3

DQ

> t

RAS

=

Burst Read Operation Followed by Precharge (RL = 5 (AL=2, CL=3))

Preliminary Data Sheet E0203E41 (Ver. 4.1)

34

EDE5104GASA, EDE5108GASA

T0

T1

T2

T3

T4

T5

T6

T7

T8

/CK

CK

Posted

READ

NOP

AL + 2 Clocks

NOP

PRE

NOP

ACT

Command

DQS, /DQS

DQ

> t

RP

=

AL = 2

CL = 4

RL = 6

out0 out1 out2 out3

> t

RAS

CL = 4

=

Burst Read Operation Followed by Precharge (RL = 6 (AL=2, CL=4))

Preliminary Data Sheet E0203E41 (Ver. 4.1)

35

EDE5104GASA, EDE5108GASA

Burst Write followed by Precharge

Minimum Write to Precharge Command spacing to the same bank = WL + 2 clocks + tWR

For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the precharge

command can be issued. This delay is known as a write recovery time (tWR) referenced from the completion of the

burst write to the precharge command. No precharge command should be issued prior to the tWR delay, as DDR-II

SDRAM does not support any burst interrupt operation.

T0

T1

T2

T3

T4

T5

T6

T7

T8

/CK

CK

Posted

WRIT

NOP

PRE

Command

> tWR

=

DQS, /DQS

WL = 3

in0

in1

in2

in3

DQ

Completion of

the Burst Write

Burst Write followed by Precharge (WL = (RL-1) =3)

T0

T1

T2

T3

T4

T5

T6

T7

T9

/CK

CK

Posted

WRIT

NOP

PRE

Command

> tWR

=

DQS, /DQS

DQ

WL = 4

in0

in1

in2

in3

Completion of

the Burst Write

Burst Write followed by Precharge (WL = (RL-1) = 4)

Preliminary Data Sheet E0203E41 (Ver. 4.1)

36

EDE5104GASA, EDE5108GASA

Auto-Precharge Operation

Before a new row in an active bank can be opened, the active bank must be precharged using either the precharge

command or the auto-precharge function. When a read or a write command is given to the DDR-II SDRAM, the

/CAS timing accepts one extra address, column address A10, to allow the active bank to automatically begin

precharge at the earliest possible moment during the burst read or write cycle. If A10 is low when the read or write

Command is issued, then normal read or write burst operation is executed and the bank remains active at the

completion of the burst sequence. If A10 is high when the Read or Write Command is issued, then the auto-

precharge function is engaged. During auto-precharge, a read Command will execute as normal with the exception

that the active bank will begin to precharge on the rising edge which is /CAS latency (CL) clock cycles before the end

of the read burst.

Auto-precharge can also be implemented during Write commands. The precharge operation engaged by the Auto

precharge command will not begin until the last data of the burst write sequence is properly stored in the memory

array.

This feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent

upon /CAS latency) thus improving system performance for random data access. The /RAS lockout circuit internally

delays the Precharge operation until the array restore operation has been completed so that the auto precharge

command may be issued with any read or write command.

Burst Read with Auto Precharge [READA]

If A10 is high when a Read Command is issued, the Read with Auto-Precharge function is engaged. The DDR-II

SDRAM starts an auto Precharge operation on the rising edge which is (AL + 2) cycles later from the read with AP

command when the condition that. When tRAS (min) is satisfied. If tRAS (min.) is not satisfied at the edge, the start

point so auto-precharge operation will be delayed until tRAS (min.) is satisfied. A new bank active (command) may

be issued to the same bank if the following two conditions are satisfied simultaneously.

(1) The /RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins.

(2) The /RAS cycle time (tRC) from the previous bank activation has been satisfied.

T0

T1

T2

T3

T4

T5

T6

T7

T8

/CK

CK

A10 = 1

Posted

READ

NOP

Command

ACT

> tRAS(min.)

=

DQS, /DQS

> tRP

=

AL = 2

CL = 3

RL = 5

out0 out1 out2 out3

CL = 3

DQ

> tRC

=

Auto precharge begins

Burst Read with Auto Precharge Followed by an Activation to the Same Bank (tRC limit)

(RL = 5 (AL = 2, CL = 3, internal tRCD = 3))

Preliminary Data Sheet E0203E41 (Ver. 4.1)

37

EDE5104GASA, EDE5108GASA

T0

T1

T2

T3

T4

T5

T6

T7

T8

/CK

CK

A10 = 1

Posted

READ

ACT

NOP

Command

> tRAS(min.)

=

DQS, /DQS

> tRP

=

AL = 2

CL = 3

RL = 5

out0 out1 out2 out3

CL = 3

DQ

> tRC

=

Auto precharge begins

Burst Read with Auto Precharge Followed by an Activation to the Same Bank (tRP limit)

RL = 5 (AL = 2, CL = 3, internal tRCD = 3)

Preliminary Data Sheet E0203E41 (Ver. 4.1)

38

EDE5104GASA, EDE5108GASA

Burst Write with Auto-Precharge [WRITA]

If A10 is high when a write command is issued, the Write with auto-precharge function is engaged. The DDR-II

SDRAM automatically begins precharge operation after the completion of the burst write plus write recovery time

(tWR). The bank undergoing auto-precharge from the completion of the write burst may be reactivated if the

following two conditions are satisfied.

(1) The data-in to bank activate delay time (tWR + tRP) has been satisfied.

(2) The /RAS cycle time (tRC) from the previous bank activation has been satisfied.

T0

T1

T2

T3

T4

T5

T6

T7

T12

/CK

CK

A10 = 1

Posted

WRIT

NOP

Command

ACT

DQS, /DQS

> tWR

> tRP

WL = RL –1 = 2

=

in0

in1

in2

in3

DQ

> tRC

=

Auto Precharge Begins

Completion of the Burst Write

Burst Write with Auto-Precharge (tRC Limit) (WL = 2, tWR =2, tRP=3)

T0

T3

T4

T5

T6

T7

T8

T9

T12

/CK

CK

A10 = 1

Posted

WRIT

NOP

Command

ACT

DQS, /DQS

> tWR

=

WL = RL –1 = 4

> tRP

=

in0

in1

in2

in3

DQ

> tRC

=

Auto Precharge Begins

Completion of the Burst Write

Burst Write with Auto-Precharge (tWR + tRP) (WL = 4, tWR =2, tRP=3)

Preliminary Data Sheet E0203E41 (Ver. 4.1)

39

EDE5104GASA, EDE5108GASA

Automatic Refresh Command (/CAS Before /RAS Refresh) [REF]

When /CS, /RAS and /CAS are held low and /WE high at the rising edge of the clock, the chip enters the Automatic

Refresh mode (CBR). All banks of the DDR-II SDRAM must be precharged and idle for a minimum of the Precharge

time (tRP) before the Auto Refresh Command (CBR) can be applied. An address counter, internal to the device,

supplies the bank address during the refresh cycle. No control of the external address bus is required once this

cycle has started.

When the refresh cycle has completed, all banks of the DDR-II SDRAM will be in the precharged (idle) state. A

delay between the Auto Refresh Command (CBR) and the next Activate Command or subsequent Auto Refresh

Command must be greater than or equal to the Auto Refresh cycle time (tRFC).

T0

T1

T2

T3

T15

T7

T8

/CK

CK

High

> tRP

> tRFC

=

CKE

=

Any

Command

PRE

NOP

CBR

NOP

Command

Automatic Refresh Command

Self Refresh Command [SELF]

The DDR-II SDRAM device has a built-in timer to accommodate Self Refresh operation. The self refresh command

is defined by having /CS, /RAS, /CAS and CKE held low with /WE high at the rising edge of the clock. Once the

Command is registered, CKE must be held low to keep the device in self refresh mode. When the SDRAM has

entered self refresh mode all of the external control signals, except CKE, are disabled. The clock is internally

disabled during self refresh operation to save power. The user may halt the external clock while the device is in Self

Refresh mode, however, the clock must be restarted before the device can exit self refresh operation. Once the

clock is cycling, the exit command will be registered asynchronously by bringing CKE high. After CKE is brought

high, an internal timer is started to insure CKE is held high for approximately 10ns before registering the self refresh

exit command. The purpose of this circuit is to filter out noise glitches on the CKE input that may cause the DDR-II

SDRAM to erroneously exit self refresh operation. Once the self refresh command is registered, a delay equal or

longer than the tXSC must be satisfied before any command can be issued to the device. CKE must remain high

for the entire Self Refresh exit period (tXSC) and commands must be gated off with /CS held High. Alternatively,

NOP commands may be registered on each positive clock edge during the self refresh exit interval. (Self Refresh

Command)

T0

T1

T2

T3

Tm

Tn

Tn+1

/CK

CK

> tXSC

=

CKE

Any

Command

SELF

NOP

: VIH or VIL

Self Refresh Command

Preliminary Data Sheet E0203E41 (Ver. 4.1)

40

EDE5104GASA, EDE5108GASA

Power-Down [PDEN]

Power-down is entered when CKE is registered (no accesses can be in progress). If power-down occurs when all

banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active

in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output

buffers, excluding CK, /CK and CKE. In power down mode, CKE Low and a stable clock signal must be maintained

at the inputs of the DDR-II SDRAM, and all other input signals are “VIH or VIL”. Power-down duration is limited by

the refresh requirements of the device.

The power-down state is synchronously exited when CKE is registered High (along with a NOP or DESL). A valid,

executable command may be applied after satisfied tXPRD or tXARD for read command exiting form precharge

power-down or active power-down respectively ,and after satisfied tXPNR for non-read command.

/CK

CK

tIS

CKE

VALID

NOP

VALID

Command

tXPRD, tXPNR

tXARD

No column

Exit

access in progress

power down

mode

Enter power down mode

(Burst read or write operation

must not be in progress)

: VIH or VIL

Power Down

Burst Interruption

Interruption of a burst read or write cycle is prohibited.

No Operation Command [NOP]

The no operation command should be used in cases when the DDR-II SDRAM is in an idle or a wait state. The

purpose of the no operation command is to prevent the DDR-II SDRAM from registering any unwanted commands

between operations. A no operation command is registered when /CS is low with /RAS, /CAS, and /WE held high at

the rising edge of the clock. A no operation command will not terminate a previous operation that is still executing,

such as a burst read or write cycle.

Deselect Command [DESL]

The deselect command performs the same function as a no operation command. Deselect Command occurs when

/CS is brought high at the rising edge of the clock, the /RAS, /CAS, and /WE signals become don’t cares.

Preliminary Data Sheet E0203E41 (Ver. 4.1)

41

EDE5104GASA, EDE5108GASA

Package Drawing

60-ball FBGA

Solder ball: Lead free (Sn-Ag-Cu)

0.2

S A

Unit: mm

11.3±0.1

0.2

S B

INDEX AREA

⁄⁄ 0.2

S

0.1

S

B

1

2 3

8 9

7

A

0.8

1.6

0.8

A

2.45

2.2

INDEX MARK

60-φ0.45±0.05

φ0.08

M

S

B

ECA-TS2-0075-01

Preliminary Data Sheet E0203E41 (Ver. 4.1)

42

EDE5104GASA, EDE5108GASA

Recommended Soldering Conditions

Please consult with our sales offices for soldering conditions of the EDE51XXGASA.

Type of Surface Mount Device

EDE51XXGASA: 60-ball FBGA < Lead free (Sn-Ag-Cu) >

Preliminary Data Sheet E0203E41 (Ver. 4.1)

43

EDE5104GASA, EDE5108GASA

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR MOS DEVICES

1

Exposing the MOS devices to a strong electric field can cause destruction of the gate

oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop

generation of static electricity as much as possible, and quickly dissipate it, when once

it has occurred. Environmental control must be adequate. When it is dry, humidifier

should be used. It is recommended to avoid using insulators that easily build static

electricity. MOS devices must be stored and transported in an anti-static container,

static shielding bag or conductive material. All test and measurement tools including

work bench and floor should be grounded. The operator should be grounded using

wrist strap. MOS devices must not be touched with bare hands. Similar precautions

need to be taken for PW boards with semiconductor MOS devices on it.

2

HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES

No connection for CMOS devices input pins can be a cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input level may be

generated due to noise, etc., hence causing malfunction. CMOS devices behave

differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected

to V^DDor GND with a resistor, if it is considered to have a possibility of being an output

pin. The unused pins must be handled in accordance with the related specifications.

3

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Power-on does not necessarily define initial status of MOS devices. Production process

of MOS does not define the initial operation status of the device. Immediately after the

power source is turned ON, the MOS devices with reset function have not yet been

initialized. Hence, power-on does not guarantee output pin levels, I/O settings or

contents of registers. MOS devices are not initialized until the reset signal is received.

Reset operation must be executed immediately after power-on for MOS devices having

reset function.

CME0107

Preliminary Data Sheet E0203E41 (Ver. 4.1)

44

EDE5104GASA, EDE5108GASA

The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.

No part of this document may be copied or reproduced in any form or by any means without the prior

written consent of Elpida Memory, Inc.

Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights

(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or

third parties by or arising from the use of the products or information listed in this document. No license,

express, implied or otherwise, is granted under any patents, copyrights or other intellectual property

rights of Elpida Memory, Inc. or others.

Descriptions of circuits, software and other related information in this document are provided for

illustrative purposes in semiconductor product operation and application examples. The incorporation of

these circuits, software and information in the design of the customer's equipment shall be done under

the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses

incurred by customers or third parties arising from the use of these circuits, software and information.

[Product applications]

Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.

However, users are instructed to contact Elpida Memory's sales office before using the product in

aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,

medical equipment for life support, or other such application in which especially high quality and

reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk

of bodily injury.

[Product usage]

Design your application so that the product is used within the ranges and conditions guaranteed by

Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation

characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no

responsibility for failure or damage when the product is used beyond the guaranteed ranges and

conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure

rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so

that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other

consequential damage due to the operation of the Elpida Memory, Inc. product.

[Usage environment]

This product is not designed to be resistant to electromagnetic waves or radiation. This product must be

used in a non-condensing environment.

If you export the products or technology described in this document that are controlled by the Foreign

Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance

with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by

U.S. export control regulations, or another country's export control laws or regulations, you must follow

the necessary procedures in accordance with such laws or regulations.

If these products/technology are sold, leased, or transferred to a third party, or a third party is granted

license to use these products, that third party must be made aware that they are responsible for

compliance with the relevant laws and regulations.

M01E0107

Preliminary Data Sheet E0203E41 (Ver. 4.1)

45


型号：	EDE5108GASA-4A-E
厂家：	ELPIDA MEMORY
描述：	512M bits DDR-II SDRAM 位512M DDR- II SDRAM 存储内存集成电路动态存储器双倍数据速率
文件：	总45页 (文件大小：467K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EDE5108GASA-4A-E [ELPIDA]

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