EDL1216AASA [ELPIDA]
128M bits Mobile RAM; 128M位的移动RAM
| 型号： | EDL1216AASA |
| 厂家： | 
ELPIDA MEMORY |
| 描述： | 128M bits Mobile RAM |
| 文件： | 总59页 (文件大小：470K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
128M bits Mobile RAM
EDL1216AASA (8M words × 16 bits)
Description
Pin Configurations
The EDL1216AA is a 128M bits Mobile RAM organized
as 2,097,152 words × 16 bits × 4 banks. The Mobile
RAM achieved low power consumption and high-speed
data transfer using the pipeline architecture. All inputs
and outputs are synchronized with the positive edge of
the clock.
/xxx indicates active low signal.
54-ball FBGA ( BGA)
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
VSS DQ15 VSSQ
DQ14 DQ13 VDDQ
DQ12 DQ11 VSSQ
DQ10 DQ9 VDDQ
VDDQ DQ0
VSSQ DQ2
VDDQ DQ4
VSSQ DQ6
VDD
DQ1
DQ3
DQ5
This product is packaged in 54-ball FBGA (µBGA ).
Features
• Low voltage power supply
VDD:
2.5V ± 0.2V
VDDQ: 1.8V ± 0.15V
• Wide temperature range (−25°C to 85°C)
• Programmable partial self refresh
• Programmable driver strength
DQ8
NC
VSS
CKE
A9
VDD LDQM DQ7
/CAS /RAS /WE
UDQM CLK
• Programmable temperature compensated self refresh
(Option)
G
H
J
NC
A8
A11
A7
BA0
A0
BA1
A1
/CS
A10
VDD
• Deep power down mode
• Small package (54-ball FBGA (µBGA))
A6
• Fully Synchronous Dynamic RAM, with all signals
referenced to a positive clock edge
VSS
A5
A4
A3
A2
• Pulsed interface
(Top view)
• Possible to assert random column address in every
cycle
A0 to A11
BA0, BA1
Address inputs
Bank select
• Quad internal banks controlled by BA0 and BA1
• Byte control by LDQM and UDQM
• Wrap sequence = Sequential/ Interleave
• /CAS latency (CL) = 2, 3
DQ0 to DQ15
CLK
Data inputs/ outputs
Clock input
CKE
Clock enable
/CS
Chip select
• Automatic precharge and controlled precharge
• Auto refresh and self refresh
/RAS
/CAS
/WE
Row address strobe
Column address strobe
Write enable
• ×16 organization
• 4,096 refresh cycles/64ms
UDQM
LDQM
VDD
Upper DQ mask enable
Lower DQ mask enable
Power supply
• Burst termination by Burst stop command and
Precharge command
• FBGA(µBGA) package is lead free solder (Sn-Ag-Cu)
VSS
Ground
Applications
VDDQ
VSSQ
NC
Power supply for DQ
Ground for DQ
No connection
Mobile cellular handsets, PDAs, wireless PDAs,
handheld PCs, home electronic appliances, and
information appliances, etc.
Document No. E0196E30 (Ver. 3.0)
Date Published June 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2001-2002
EDL1216AASA
Ordering Information
Organization
(words × bits)
Clock frequency
MHz (max.)
Part number
Internal Banks
4
/CAS latency
3
Package
EDL1216AASA-75-E
8M × 16
133
54-ball FBGA (µBGA)
Part Number
E D L 12 16 A A SA - 75 - E
Elpida Memory
Type
D: Monolithic Device
Product Code
L: Mobile RAM
Lead Free
Density / Bank
12: 128M / 4 banks
Speed
75: 133MHz
Bit Organization
16: x16
Package
SA: µBGA
Voltage, Interface
Die Rev.
A: VDD = 2.5V, VDDQ = 1.8V, LVCMOS
Data Sheet E0196E30 (Ver. 3.0)
2
EDL1216AASA
CONTENTS
Description ....................................................................................................................................................1
Features ........................................................................................................................................................1
Applications...................................................................................................................................................1
Pin Configurations.........................................................................................................................................1
Ordering Information .....................................................................................................................................2
Electrical Specifications.................................................................................................................................4
Pin Function ..................................................................................................................................................9
Command Operation...................................................................................................................................10
Truth Table..................................................................................................................................................14
Simplified State Diagram.............................................................................................................................19
Initialization..................................................................................................................................................20
Programming Mode Registers ....................................................................................................................20
Address Bits of Bank-Select and Precharge...............................................................................................24
Operation of the Mobile RAM......................................................................................................................25
Timing Waveforms ......................................................................................................................................33
Package Drawing ........................................................................................................................................56
Recommended Soldering Conditions..........................................................................................................57
Revision History ..........................................................................................................................................60
Data Sheet E0196E30 (Ver. 3.0)
3
EDL1216AASA
Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, wait more than 200 µs and then, execute Power on sequence and two Auto Refresh before proper
device operation is achieved.
Absolute Maximum Ratings
Parameter
Symbol
VT
Rating
Unit
V
Note
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
–0.5 to +3.6
–0.5 to +3.6
50
VDD, VDDQ
IOS
V
mA
W
PD
1.0
Operating ambient temperature
Storage temperature
TA
–25 to +85
–55 to +125
°C
°C
Tstg
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions (TA = –25 to +85°C)
Parameter
Symbol
VDD
VSS
min.
typ.
2.5
0
max.
Unit
V
Notes
Supply voltage
2.3
2.7
0
0
V
DQ Supply voltage
Input high voltage
Input low voltage
VDDQ
VIH
1.65
1.8
1.95
VDDQ + 0.3*1
V
0.8 × VDDQ
–0.3*2
V
VIL
0.3
V
Notes: 1. VIH (max.) = VDDQ + 1.5V (pulse width ≤ 5ns).
2. VIL (min.) = –1.5V (pulse width ≤ 5ns).
Data Sheet E0196E30 (Ver. 3.0)
4
EDL1216AASA
DC Characteristics (TA = –25 to +85°C, VDD = 2.5V 0.2V, VDDQ = 1.8V 0.15V, VSS, VSSQ = 0V)
Parameter
/CAS latency
Symbol
IDD1
Grade
max.
65
Unit
mA
Test condition
Notes
1
Operating current
(CL = 2)
Burst length = 1
tRC ≥ tRC min., IO = 0mA,
One bank active
(CL = 3)
IDD1
65
1
mA
mA
Standby current in power down IDD2P
CKE ≤ VIL max., tCK = 15ns
CKE ≤ VIL max., tCK = ∞
Standby current in power down
IDD2PS
0.6
mA
(input signal stable)
CKE ≥ VIH min., tCK = 15ns,
/CS ≥ VIH min.,
Input signals are changed one
time during 30ns.
Standby current in non power
down
IDD2N
5.5
mA
CKE ≥ VIH min., tCK = ∞,
Input signals are stable.
CKE ≤ VIL max., tCK = 15ns
Standby current in non power
IDD2NS
2
mA
mA
mA
down (input signal stable)
Active standby current in power
down
IDD3P
1.5
1
Active standby current in power
down (input signal stable)
CKE ≤ VIL max., tCK = ∞
IDD3PS
CKE ≥ VIH min., tCK = 15 ns,
/CS ≥ VIH min.,
Input signals are changed one
time during 30ns.
Active standby current in non
IDD3N
17
12
mA
mA
power down
CKE ≥ VIH min., tCK = ∞,
Input signals are stable.
Active standby current in non
IDD3NS
power down (input signal stable)
Burst operating current
IDD4
tCK ≥ tCK min.,
IOUT = 0mA, All banks active
60
mA
mA
mA
mA
mA
2
3
(CL = 2)
(CL = 3)
IDD4
IDD5
IDD5
IDD6
80
Refresh current
(CL = 2)
155
155
0.35
tRC ≥ tRC min.
(CL = 3)
Self refresh current
PASR="000" (Full)
TCSR="00" (Ts*4 ≤ 70°C)
CKE ≤ 0.2V
PASR="001" (2BK)
PASR="010" (1BK)
PASR="101" (1/2 BK)
PASR="110" (1/4 BK)
PASR="000" (Full)
PASR="001" (2BK)
PASR="010" (1BK)
PASR="101" (1/2 BK)
PASR="110" (1/4 BK)
PASR="000" (Full)
PASR="001" (2BK)
PASR="010" (1BK)
PASR="101" (1/2 BK)
PASR="110" (1/4 BK)
0.25
0.18
0.12
0.09
0.20
0.15
0.10
0.08
0.07
0.60
0.50
0.43
0.37
0.34
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD6
IDD6
TCSR="01" (Ts*4 ≤ 45°C)
CKE ≤ 0.2V
TCSR="11" (Ts*4 ≤ 85°C)
CKE ≤ 0.2V
Standby current in deep power
down mode
IDD7
10
µA
CKE ≤ 0.2V
Data Sheet E0196E30 (Ver. 3.0)
5
EDL1216AASA
Notes: 1. IDD1 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, IDD1 is measured condition that addresses are changed only one time during tCK (min.).
2. IDD4 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, IDD4 is measured condition that addresses are changed only one time during tCK (min.).
3. IDD5 is measured on condition that addresses are changed only one time during tCK (min.).
4. Ts is surface temperature.
DC Characteristics 2 (TA = –25 to +85°C, VDD = 2.5V 0.2V, VDDQ = 1.8V 0.15V, VSS, VSSQ = 0V)
Parameter
Symbol
ILI
min.
max.
1.0
1.5
—
Unit
µA
µA
V
Test condition
Notes
Input leakage current
Output leakage current
Output high voltage
Output low voltage
–1.0
0 ≤ VIN ≤ VDDQ
ILO
–1.5
0 ≤ VOUT ≤ VDDQ, DQ = disable
IOH = –0.1 mA
VOH
VOL
VDDQ – 0.2
—
0.2
V
IOL = 0.1 mA
Pin Capacitance (TA = 25°C, f = 1MHz)
Notes
Parameter
Symbol
CI1
Pins
CLK
min.
Typ
—
max.
3.5
Unit
pF
Input capacitance
2.0
2.0
4
Address, CKE, /CS, /RAS,
/CAS, /WE, UDQM, LDQM
CI2
—
—
3.8
6.5
pF
pF
Data input/output capacitance
CI/O
DQ
Data Sheet E0196E30 (Ver. 3.0)
6
EDL1216AASA
AC Characteristics (TA = –25 to +85°C, VDD = 2.5V 0.2V, VDDQ = 1.8V 0.15V, VSS, VSSQ = 0V)
Test Conditions
• AC high level input voltage / low level input voltage: 1.6 / 0.2V
• Input timing measurement reference level: 0.9V
• Transition time (Input rise and fall time): 1ns
• Output timing measurement reference level: 0.9V
t
CK
t
CH
t
CL
1.6 V
CLK
0.9 V
0.2 V
t
SETUP
t
HOLD
1.6 V
0.9 V
0.2 V
Input
t
AC
t
OH
Output
Data Sheet E0196E30 (Ver. 3.0)
7
EDL1216AASA
Synchronous Characteristics
Parameter
Symbol
tCK2
min.
10
max.
—
Unit
ns
Note
Clock cycle time
(CL= 2)
(CL= 3)
tCK3
7.5
—
—
ns
Access time from CLK
(CL= 2)
tAC2
6
ns
1
1
(CL= 3)
tAC3
tCH
tCL
—
5.4
—
—
—
—
ns
ns
ns
ns
ns
CLK high level width
CLK low level width
Data-out hold time
Data-out low-impedance time
2.5
2.5
2.5
0
tOH
tLZ
1
Data-out high-impedance time
(CL= 2)
tHZ2
2.5
6
ns
(CL= 3)
tHZ3
tDS
2.5
1.5
0.8
1.5
0.8
1.5
0.8
1.5
5.4
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
Data-in setup time
Data-in hold time
Address setup time
Address hold time
CKE setup time
tDH
tAS
tAH
tCKS
tCKH
tCKSP
CKE hold time
CKE setup time (Power down exit)
Command (/CS, /RAS, /CAS, /WE,
UDQM, LDQM) setup time
Command (/CS, /RAS, /CAS, /WE,
UDQM, LDQM) hold time
tCMS
tCMH
1.5
0.8
—
—
ns
ns
Note: 1. Output load.
Z = 50Ω
Output
30 pF
Output load
Asynchronous Characteristics
Parameter
Symbol
min.
67.5
67.5
45
max.
Unit
Notes
ACT to REF/ACT command period (operation) tRC
ns
ns
ns
ns
ns
ns
ns
ACT to REF/ACT command period (refresh)
ACT to PRE command period
tRC1
tRAS
tRP
120000
PRE to ACT command period
20
Delay time ACT to READ/WRITE command
ACT (one) to ACT (another) command period
Data-in to PRE command period
tRCD
tRRD
tDPL
20
15
15
Data-in to ACT (REF) command period
(Auto precharge)
TDAL2
2CLK + 20
ns
(CL = 2)
(CL = 3)
TDAL3
tRSC
tT
2CLK + 20
ns
Mode register set cycle time
Transition time
2
CLK
ns
0.5
64
30
Refresh time (4,096 refresh cycles)
tREF
ms
Data Sheet E0196E30 (Ver. 3.0)
8
EDL1216AASA
Pin Function
CLK (input pin)
CLK is the master clock input. Other inputs signals are referenced to the CLK rising edge.
CKE (input pins)
CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising edge is valid; otherwise it is
invalid. If the CLK rising edge is invalid, the internal clock is not issued and the Mobile RAM suspends operation.
When the Mobile RAM is not in burst mode and CKE is negated, the device enters power down mode. During power
down mode, CKE must remain low.
/CS (input pins)
/CS low starts the command input cycle. When /CS is high, commands are ignored but operations continue.
/RAS, /CAS, and /WE (input pins)
/RAS, /CAS and /WE have the same symbols on conventional DRAM but different functions. For details, refer to the
command table.
A0 to A11 (input pins)
Row Address is determined by A0 to A11 at the CLK (clock) rising edge in the active command cycle. It does not
depend on the bit organization.
Column Address is determined by A0 to 8 at the CLK rising edge in the read or write command cycle.
A10 defines the precharge mode. When A10 is high in the precharge command cycle, all banks are precharged;
when A10 is low, only the bank selected by BA0 and BA1 is precharged.
When A10 is high in read or write command cycle, the precharge starts automatically after the burst access.
BA0 and BA1 (input pin)
BA0 and BA1 are bank select signal. (See Bank Select Signal Table)
[Bank Select Signal Table]
BA0
BA1
Bank A
Bank B
Bank C
Bank D
L
L
H
L
L
H
H
H
Remark: H: VIH. L: VIL. ×: VIH or VIL
UDQM and LDQM (input pins)
UDQM and LDQM control upper byte and lower byte I/O buffers, respectively. In read mode, DQM controls the
output buffers like a conventional /OE pin. DQM high and DQM low turn the output buffers off and on, respectively.
The DQM latency for the read is two clocks. In write mode, DQM controls the word mask. Input data is written to the
memory cell if DQM is low but not if DQM is high. The DQM latency for the write is zero.
DQ0 to DQ15 (input/output pins)
DQ pins have the same function as I/O pins on a conventional DRAM.
VDD, VSS, VDDQ, VSSQ (Power supply)
VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output
buffers.
Data Sheet E0196E30 (Ver. 3.0)
9
EDL1216AASA
Command Operation
Extended Mode register set command (/CS, /RAS, /CAS, /WE, BA0 = Low, BA1 = High)
The Mobile RAM has an extended mode register that defines low power functions. In this command, A0 through A11
are the data input pins.
After power on, the extended mode register set command must be executed to fix low power functions.
The extended mode register can be set only when all banks are in idle state.
During tRSC following this command, the Mobile RAM can not accept any other commands.
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
Add
Extended Mode register set command
Mode register set command (/CS, /RAS, /CAS, /WE, BA0, BA1 = Low)
The Mobile RAM has a mode register that defines how the device operates. In this command, A0 through A11 are
the data input pins. After power on, the mode register set command must be executed to initialize the device. The
mode register can be set only when all banks are in idle state. During tRSC following this command, the Mobile
RAM cannot accept any other commands.
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
Add
Mode register set command
Activate command (/CS, /RAS = Low, /CAS, /WE = High)
The Mobile RAM has four banks, each with 4,096 rows. This command activates the bank selected by BA0 and BA1
and a row address selected by A0 through A11. This command corresponds to a conventional DRAM's /RAS falling.
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0, BA1
A10
Row
Row
Add
Activate command
Data Sheet E0196E30 (Ver. 3.0)
10
EDL1216AASA
Precharge command (/CS, /RAS, /WE = Low, /CAS = High)
This command begins precharge operation of the bank selected by BA0 and BA1. When A10 is High, all banks are
precharged, regardless of BA0 and BA1. When A10 is Low, only the bank selected by BA0 and BA1 is precharged.
After this command, the Mobile RAM can’t accept the activate command to the precharging bank during tRP
(precharge to activate command period). This command corresponds to a conventional DRAM’s /RAS rising.
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0, BA1
A10
(Precharge select)
Add
Precharge command
Write command (/CS, /CAS, /WE = Low, /RAS = High)
This command sets the burst start address given by the column address to begin the burst write operation. The first
write data in burst mode can input with this command with subsequent data on following clocks.
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0, BA1
A10
Add
Col.
Write command
Read command (/CS, /CAS = Low, /RAS, /WE = High)
Read data is available after /CAS latency requirements have been met. This command sets the burst start address
given by the column address.
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0, BA1
A10
Add
Col.
Read command
Data Sheet E0196E30 (Ver. 3.0)
11
EDL1216AASA
Auto refresh command (/CS, /RAS, /CAS = Low, /WE, CKE = High)
This command is a request to begin the Auto refresh operation. The refresh address is generated internally.
Before executing Auto refresh, all banks must be precharged. After this cycle, all banks will be in the idle
(precharged) state and ready for a row activate command. During tRC1 period (from refresh command to refresh or
activate command), the Mobile RAM cannot accept any other command
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0, BA1
A10
Add
Auto refresh command
Self refresh entry command (/CS, /RAS, /CAS, CKE = Low, /WE = High)
After the command execution, self refresh operation continues while CKE remains low. When CKE goes high, the
Mobile RAM exits the self refresh mode. During self refresh mode, refresh interval and refresh operation are
performed internally, so there is no need for external control. Before executing self refresh, all banks must be
precharged.
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0, BA1
A10
Add
Self refresh entry command
Power down entry command (/CS, CKE = Low, /RAS, /CAS, /WE = High)
After the command execution, power down mode continues while CKE remains low. When CKE goes high, the
Mobile RAM exits the power down mode. Before executing power down, all banks must be precharged.
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0, BA1
A10
Add
Power down entry command
Data Sheet E0196E30 (Ver. 3.0)
12
EDL1216AASA
Deep power down entry command( /CS, CKE, /WE = Low, /RAS, /CAS = High)
After the command execution, deep power down mode continues while CKE remains low. When CKE goes high, the
Mobile RAM exits the deep power down mode. Before executing deep power down, all banks must be precharged.
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0, BA1
A10
Add
Deep power down entry command
Burst stop command (/CS = /WE = Low, /RAS, /CAS = High)
This command can stop the current burst operation.
CLK
CKE
H
/CS
/RAS
/CAS
/WE
BA0, BA1
A10
Add
Burst stop command
No operation (/CS = Low, /RAS, /CAS, /WE = High)
This command is not an execution command. No operations begin or terminate by this command.
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0, BA1
A10
Add
No operation
Data Sheet E0196E30 (Ver. 3.0)
13
EDL1216AASA
Truth Table
Command Truth Table
CK
E A11,
n – 1
Function
Symbol
DESL
NOP
n
×
×
H
×
×
×
×
×
×
×
×
×
/CS
H
L
/RAS /CAS /WE
BA1
×
BA0
×
A10
×
A9 - A0
Device deselect
No operation
H
H
H
H
H
H
H
H
H
H
H
H
×
×
×
H
L
×
H
H
H
H
H
H
L
H
H
L
×
×
×
×
Burst stop
BST
L
×
×
×
×
Read
READ
READA
WRIT
WRITA
ACT
L
H
H
L
V
V
V
V
V
V
×
V
V
V
V
V
V
×
L
V
V
V
V
V
×
Read with auto precharge
Write
L
L
H
L
L
L
Write with auto precharge
Bank activate
L
L
L
H
V
L
L
H
H
H
L
H
L
Precharge select bank
Precharge all banks
Mode register set
Extended mode register set
PRE
L
L
PALL
MRS
L
L
L
H
L
×
L
L
L
L
L
V
V
EMRS
L
L
L
L
H
L
L
Remark: H: VIH. L: VIL. ×: VIH or VIL, V = Valid data
DQM Truth Table
CKE
DQM
Function
Symbol
ENB
n – 1
H
n
×
×
×
×
×
×
U
L
L
L
H
×
L
×
H
Data write / output enable
Data mask / output disable
MASK
ENBU
ENBL
H
H
L
Upper byte write enable / output enable
Lower byte write enable / output enable
Upper byte write inhibit / output disable
Lower byte write inhibit / output disable
H
H
×
MASKU
MASKL
H
H
×
H
Remark: H: VIH. L: VIL. ×: VIH or VIL
CKE Truth Table
CK
E
Current state
Activating
Any
Function
Symbol
n – 1
n
L
L
/CS
×
/RAS
×
/CAS
/WE
Address
Clock suspend mode entry
Clock suspend mode
Clock suspend mode exit
Auto refresh command
Self refresh entry
H
L
×
×
×
L
×
×
×
×
×
×
×
×
×
Clock suspend
Idle
L
H
H
L
×
×
×
REF
SELF
PD
H
H
H
H
H
L
L
L
H
H
H
×
Idle
L
L
L
Idle
Power down entry
L
L
H
×
H
×
H
H
×
H
×
×
×
×
×
×
×
×
×
×
L
H
L
Idle
Deep power down entry
Self refresh exit
DPD
L
H
H
×
L
Self refresh
H
H
H
H
H
L
H
×
L
H
L
Power down
Power down exit
L
H
×
H
×
L
H
×
Deep power down
Deep power down exit
L
×
×
Remark: H: VIH. L: VIL. ×: VIH or VIL
Data Sheet E0196E30 (Ver. 3.0)
14
EDL1216AASA
Function Truth Table
Current state
Idle
/CS /RAS /CAS /WE Address
Command
Action
Notes
H
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
×
×
×
×
DESL
NOP
Nop
H
H
H
H
L
H
H
L
H
L
×
Nop
×
BST
Nop
READ/READA
H
L
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
×
ILLEGAL
ILLEGAL
→ Row activating
Nop
2
2
WRIT/ WRITA
L
H
H
L
H
L
ACT
L
PRE/PALL
REF
L
H
L
Auto refresh
Mode register set
L
L
OC, BA1= L
MRS
L
L
L
OC, BA1= H EMRS
Extended mode register set
Row active
×
×
×
×
DESL
NOP
Nop
H
H
H
H
L
H
H
L
H
L
×
Nop
×
BST
Nop
READ/READA
H
L
BA, CA, A10
Begin read
3
3
2
4
WRIT/ WRITA
L
BA, CA, A10
Begin write
H
H
L
H
L
BA, RA
ACT
ILLEGAL
L
BA, A10
PRE/PALL
REF
Precharge/Precharge all banks
ILLEGAL
L
H
L
×
L
L
OC, BA
MRS/EMRS
DESL
ILLEGAL
Read
×
×
×
×
×
×
Continue burst to end → Row active
Continue burst to end → Row active
Burst stop → Row active
H
H
H
H
L
H
H
L
H
L
NOP
BST
H
L
BA, CA, A10 READ/READA Terminate burst, begin new read
5
L
BA, CA, A10 WRIT/WRITA
Terminate burst, begin write
ILLEGAL
5, 6
2
H
H
L
H
L
BA, RA
ACT
L
BA, A10
PRE/PALL
REF
Terminate burst → Precharging
ILLEGAL
L
H
L
×
L
L
OC, BA
MRS/EMRS
DESL
ILLEGAL
Write
×
×
×
×
×
×
Continue burst to end → Write recovering
Continue burst to end → Write recovering
Burst stop → Row active
H
H
H
H
L
H
H
L
H
L
NOP
BST
H
L
BA, CA, A10 READ/READA Terminate burst, start read : Determine AP 5, 6
L
BA, CA, A10 WRIT/WRITA
Terminate burst, new write : Determine AP
5
2
7
H
H
L
H
L
BA, RA
BA, A10
×
ACT
ILLEGAL
L
PRE/PALL
REF
Terminate burst → Precharging
ILLEGAL
L
H
L
L
L
OC, BA
MRS/EMRS
ILLEGAL
Data Sheet E0196E30 (Ver. 3.0)
15
EDL1216AASA
Current state
Read with auto
precharge
/CS /RAS /CAS /WE Address
Command
Action
Notes
H
L
L
L
L
L
L
L
L
×
×
×
×
DESL
NOP
Continue burst to end → Precharging
H
H
H
H
L
H
H
L
H
L
×
Continue burst to end → Precharging
×
BST
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
READ/READA
H
L
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
×
2
2
2
2
WRIT/ WRITA
L
H
H
L
H
L
ACT
L
PRE/PALL
REF
L
H
L
L
L
OC, BA
MRS/EMRS
Write with auto
precharge
Continue burst to end → Write recovering
with auto precharge
H
L
×
×
×
×
×
DESL
NOP
Continue burst to end → Write recovering
with auto precharge
H
H
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
H
H
L
H
L
L
×
BST
ILLEGAL
READ/READA
H
L
BA, CA, A10
ILLEGAL
2
2
2
2
WRIT/ WRITA
L
BA, CA, A10
ILLEGAL
H
H
L
H
L
BA, RA
ACT
ILLEGAL
L
BA, A10
PRE/PALL
REF
ILLEGAL
L
H
L
×
ILLEGAL
L
L
OC, BA
MRS/EMRS
DESL
ILLEGAL
Precharging
×
×
×
×
×
×
Nop → Enter idle after tRP
Nop → Enter idle after tRP
ILLEGAL
H
H
H
H
L
H
H
L
H
L
NOP
BST
H
L
BA, CA, A10 READ/READA ILLEGAL
2
2
2
L
BA, CA, A10 WRIT/WRITA
ILLEGAL
H
H
L
H
L
BA, RA
ACT
ILLEGAL
L
BA, A10
PRE/PALL
REF
Nop → Enter idle after tRP
ILLEGAL
L
H
L
×
L
L
OC, BA
MRS/EMRS
DESL
ILLEGAL
Row activating
×
×
×
×
×
×
Nop → Enter bank active after tRCD
Nop → Enter bank active after tRCD
ILLEGAL
H
H
H
H
L
H
H
L
H
L
NOP
BST
H
L
BA, CA, A10 READ/READA ILLEGAL
2
L
BA, CA, A10 WRIT/WRITA
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
2
H
H
L
H
L
BA, RA
BA, A10
×
ACT
2, 8
2
L
PRE/PALL
REF
L
H
L
L
L
OC, BA
MRS/EMRS
Data Sheet E0196E30 (Ver. 3.0)
16
EDL1216AASA
Current state
/CS /RAS /CAS /WE Address
Command
Action
Notes
Write recovering
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
×
×
×
×
DESL
NOP
Nop → Enter row active after tDPL
Nop → Enter row active after tDPL
Nop → Enter row active after tDPL
Begin read
H
H
H
H
L
H
H
L
H
L
×
×
BST
READ/READA
H
L
BA, CA, A10
6
WRIT/ WRITA
L
BA, CA, A10
Begin new write
H
H
L
H
L
BA, RA
ACT
ILLEGAL
2
2
L
BA, A10
PRE/PALL
REF
ILLEGAL
L
H
L
×
ILLEGAL
L
L
OC, BA
MRS/EMRS
DESL
ILLEGAL
Write recovering
×
×
×
×
×
×
Nop → Enter precharge after tDPL
Nop → Enter precharge after tDPL
Nop → Enter row active after tDPL
with auto
H
H
H
H
L
H
H
L
H
L
NOP
precharge
BST
H
L
BA, CA, A10 READ/READA ILLEGAL
L
BA, CA, A10 WRIT/WRITA
ILLEGAL
2, 6
2
H
H
L
H
L
BA, RA
ACT
ILLEGAL
L
BA, A10
PRE/PALL
REF
ILLEGAL
2
L
H
L
×
ILLEGAL
L
L
OC, BA
MRS/EMRS
DESL
ILLEGAL
Refresh
×
×
×
×
×
×
Nop → Enter idle after tRC1
Nop → Enter idle after tRC1
Nop → Enter idle after tRC1
H
H
H
H
L
H
H
L
H
L
NOP
BST
H
L
BA, CA, A10 READ/READA ILLEGAL
L
BA, CA, A10 WRIT/WRITA
ILLEGAL
H
H
L
H
L
BA, RA
ACT
ILLEGAL
L
BA, A10
PRE/PALL
REF
ILLEGAL
L
H
L
×
ILLEGAL
L
L
OC, BA
MRS/EMRS
DESL
ILLEGAL
Mode register
accessing
×
×
×
×
×
×
Nop → Enter idle after tRSC
Nop → Enter idle after tRSC
Nop → Enter idle after tRSC
H
H
H
H
L
H
H
L
H
L
NOP
BST
H
L
BA, CA, A10 READ/READA ILLEGAL
L
BA, CA, A10 WRIT/WRITA
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
H
H
L
H
L
BA, RA
BA, A10
×
ACT
L
PRE/PALL
REF
L
H
L
L
L
OC, BA
MRS/EMRS
Data Sheet E0196E30 (Ver. 3.0)
17
EDL1216AASA
Current state
Extended mode
register
/CS /RAS /CAS /WE Address
Command
Action
Notes
H
L
L
L
L
L
L
L
L
×
×
×
×
×
×
DESL
NOP
BST
Nop → Enter idle after tRSC
Nop → Enter idle after tRSC
Nop → Enter idle after tRSC
H
H
H
H
L
H
H
L
H
L
accessing
H
L
BA, CA, A10 READ/READA ILLEGAL
L
BA, CA, A10 WRIT/WRITA
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
H
H
L
H
L
BA, RA
BA, A10
×
ACT
L
PRE/PALL
REF
L
H
L
L
L
OC, BA0,BA1 MRS/EMRS
Remark: H: VIH. L: VIL. ×: VIH or VIL, V = Valid data
BA: Bank Address, CA: Column Address, RA: Row Address, OC: Op-Code
Notes: 1. All entries assume that CKE is active (CKEn-1=CKEn=H).
2. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA),
depending on the state of that bank.
3. Illegal if tRCD is not satisfied.
4. Illegal if tRAS is not satisfied.
5. Must satisfy burst interrupt condition.
6. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
7. Must mask preceding data which don't satisfy tDPL.
8. Illegal if tRRD is not satisfied.
Data Sheet E0196E30 (Ver. 3.0)
18
EDL1216AASA
Simplified State Diagram
Extended
Mode
Register
Set
Self
Refresh
MRS
Mode
Register
Set
REF
CBR (Auto)
Refresh
IDLE
Power
Down
Deep
Power
Down
CKE
CKE
Active
Power
Down
ROW
ACTIVE
Write
Read
CKE
CKE
Read
CKE
WRITE
SUSPEND
READ
SUSPEND
WRITE
READ
Write
CKE
CKE
CKE
CKE
CKE
READA
SUSPEND
WRITEA
SUSPEND
WRITEA
READA
Precharge
POWER
ON
Precharge
Automatic sequence
Manual input
Data Sheet E0196E30 (Ver. 3.0)
19
EDL1216AASA
Initialization
The synchronous DRAM is initialized in the power-on sequence according to the following.
(1) To stabilize internal circuits, when power is applied, a 200 µs or longer pause must precede any signal toggling.
(2) After the pause, all banks must be precharged using the Precharge command (The Precharge all banks
command is convenient).
(3) Once the precharge is completed and the minimum tRP is satisfied, two or more Auto refresh must be performed.
(4) Both the mode register and the extended mode register must be programmed. After the mode register set cycle
or the extended mode register set cycle, tRSC (2 CLK minimum) pause must be satisfied.
Remarks:
1
The sequence of Auto refresh, mode register programming and extended mode register programming above may
be transposed.
2
CKE and DQM must be held high until the Precharge command is issued to ensure data-bus High-Z.
Programming Mode Registers
The mode register and extended mode register are programmed by the Mode register set command and Extended
mode register command, respectively using address bits A11 through A0, BA0 and BA1 as data inputs. The
registers retain data until they are re-programmed, or the device enters into the deep power down or the device
loses power.
Mode register
The mode register has three fields;
Options
:
:
:
:
A11 through A7
A6 through A4
A3
/CAS latency
Wrap type
Burst length
A2 through A0
Following mode register programming, no command can be issued before at least 2 CLK have elapsed.
/CAS Latency
/CAS latency is the most critical of the parameters being set. It tells the device how many clocks must elapse before
the data will be available. The value is determined by the frequency of the clock and the speed grade of the device.
Burst Length
Burst Length is the number of words that will be output or input in a read or write cycle. After a read burst is
completed, the output bus will become High-Z. The burst length is programmable as 1, 2, 4, 8 or full page.
Wrap Type (Burst Sequence)
The wrap type specifies the order in which the burst data will be addressed. This order is programmable as either
“Sequential” or “Interleave”. The method chosen will depend on the type of CPU in the system.
Some microprocessor cache systems are optimized for sequential addressing and others for interleaved addressing.
“Burst Length Sequence” shows the addressing sequence for each burst length using them. Both sequences
support bursts of 1, 2, 4 and 8. Additionally, sequence supports the full page length.
Data Sheet E0196E30 (Ver. 3.0)
20
EDL1216AASA
Extended Mode Register
The extended mode register has four fields;
Options
:
A11 through A7
Drive Strength : A6 through A5
Temperature Compensated Self Refresh
:
A4 through A3
Partial Array Self Refresh
A2 through A0
:
Following extended mode register programming, no command can be issued before at least 2 CLK have elapsed.
Drive Strength
Driving capability of data output drivers.
Temperature Compensated Self Refresh
Programmable refresh rate for self refresh mode to allow the system to control power as a function of temperature.
Partial Array Self Refresh
Memory array size to be refreshed during self refresh operation is programmable in order to reduce power. Data
outside the defined area will not be retained during self refresh.
Data Sheet E0196E30 (Ver. 3.0)
21
EDL1216AASA
Mode Register Definition
BA0 BA1
A11 A10 A9
A8
0
A7
0
A6
A5
A4
A3
A2
A1
BL
A0
0
0
0
0
0
LTMODE
WT
Mode Register Set
Bits2-0
000
WT = 0
WT = 1
1
1
2
001
2
Bits6-4
/CAS latency
010
4
4
000
001
010
011
100
101
110
111
R
R
2
Burst length
011
100
101
110
111
8
8
R
R
R
R
R
R
R
3
Latency
mode
R
R
R
R
Full page
0
1
Sequential
Interleave
Wrap type
BA0 BA1
A11 A10 A9
A8
A7
0
A6
A5
A4
A3
A2
A1
A0
0
1
0
0
0
0
DS
TCSR
PASR
Extended Mode Register Set
Bits2-0 Refresh Array
000
001
010
011
100
101
110
111
All banks
Bank A & Bank B (BA1=0)
Bank A (BA0=BA1=0)
Partial Array
Self Refresh
R
R
1/2 of Bank A (RA11=0)
1/4 of Bank A (RA11=RA10=0)
R
Bits6-5 Strength
Bits4-3 Max Temperature
Temprature
Compensated
Self Refresh
00
01
10
11
Normal
00
01
10
11
70°
45°
15°
85°
C
C
C
C
Drive Strength
1/2 strength
1/4 strength
R
Remark R : Reserved
Data Sheet E0196E30 (Ver. 3.0)
22
EDL1216AASA
Burst Length and Sequence
[Burst of Two]
Starting address
(column address A0, binary)
Sequential addressing sequence
(decimal)
Interleave addressing sequence
(decimal)
0
1
0, 1
1, 0
0, 1
1, 0
[Burst of Four]
Starting address
(column address A1−A0, binary)
Sequential addressing sequence
(decimal)
Interleave addressing sequence
(decimal)
00
01
10
11
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
[Burst of Eight]
Starting address
(column address A2−A0, binary)
Sequential addressing sequence
(decimal)
Interleave addressing sequence
(decimal)
000
001
010
011
100
101
110
111
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
Full page burst is an extension of the above tables of sequential addressing, with the length being 512.
Data Sheet E0196E30 (Ver. 3.0)
23
EDL1216AASA
Address Bits of Bank-Select and Precharge
BA1
0
BA0
0
Result
Row
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9 A10 A11 BA1 BA0
Select Bank A
“Activate” command
(Activate command)
Select Bank B
“Activate” command
0
1
1
1
0
1
Select Bank C
“Activate” command
Select Bank D
“Activate” command
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9 A10 A11 BA1 BA0
BA1
0
BA0
0
A10
0
Result
(Precharge command)
Precharge Bank A
Precharge Bank B
Precharge Bank C
Precharge Bank D
Precharge All Banks
0
0
1
0
1
0
0
1
1
1
x
x
x : Don’t care
disables Auto-Precharge
(End of Burst)
0
1
enables Auto-Precharge
(End of Burst)
Col.
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9 A10 A11 BA1 BA0
(/CAS strobes)
BA1
0
BA0
0
Result
enables Read/Write
commands for Bank A
enables Read/Write
commands for Bank B
0
1
1
1
0
1
enables Read/Write
commands for Bank C
enables Read/Write
commands for Bank D
Data Sheet E0196E30 (Ver. 3.0)
24
EDL1216AASA
Operation of the Mobile RAM
Precharge
The precharge command can be issued anytime after tRAS min. is satisfied. Soon after the precharge command is
issued, precharge operation performed and the synchronous DRAM enters the idle state after tRP is satisfied. The
parameter tRP is the time required to perform the precharge. The earliest timing in a read cycle that a precharge
command can be issued without losing any data in the burst is as follows.
Burst length=4
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
/CAS latency = 2
PRE
Q3
READ
Command
Hi-Z
DQ
Q1
Q2
Q4
Q3
/CAS latency = 3
Command
READ
PRE
Q2
Hi-Z
DQ
Q1
Q4
(tRAS must be satisfied)
Precharge
In order to write all data to the memory cell correctly, the asynchronous parameter tDPL must be satisfied. The tDPL
(min.) specification defines the earliest time that a precharge command can be issued. Minimum number of clocks is
calculated by dividing tDPL (min.) with clock cycle time. In summary, the precharge command can be issued relative
to reference clock that indicates the last data word is valid. In the following table, minus means clocks before the
reference; plus means time after the reference.
/CAS latency
Read
-1
Write
2
3
+tDPL(min.)
+tDPL(min.)
-2
Data Sheet E0196E30 (Ver. 3.0)
25
EDL1216AASA
Auto Precharge
During a read or write command cycle, A10 controls whether auto precharge is selected. A10 high in the Read or
Write command (Read with Auto precharge command or Write with Auto precharge command), auto precharge is
selected and begins automatically. The tRAS must be satisfied with a read with auto precharge or a write with auto
precharge operation. In addition, the next activate command to the bank being precharged cannot be executed until
the precharge cycle ends.
In read cycle, once auto precharge has started, an activate command to the bank can be issued after tRP has been
satisfied.
In write cycle, the tDAL must be satisfied to issue the next activate command to the bank being precharged.
The timing that begins the auto precharge cycle depends on whether read or write cycle.
Read with Auto Precharge
During a read cycle, the auto precharge begins one clock earlier (/CAS latency of 2) or two clocks earlier (/CAS
latency of 3) the last data word output.
Burst length = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CLK
/CAS latency = 2
Auto precharge starts
Command
READA B
Hi-Z
DQ
QB1
QB2
QB3
QB4
/CAS latency = 3
Auto precharge starts
Command
READA B
Hi-Z
DQ
QB1
QB2
QB3
QB4
(tRAS must be satisfied)
Read with Auto Precharge
Remark: READA means Read with Auto precharge
Write with Auto Precharge
During a write cycle, the auto precharge starts at the timing that is equal to the value of the tDPL (min.) after the
last data word input to the device.
Burst length = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Auto precharge starts
Command
WRITA B
DB1
Hi-Z
DQ
DB2
DB3
DB4
t
DPL(MIN.)
(tRAS must be satisfied)
Write with Auto Precharge
Remark: WRITA means Write with Auto Precharge
Data Sheet E0196E30 (Ver. 3.0)
26
EDL1216AASA
Read / Write Command Interval
Read to Read Command Interval
During a read cycle, when new Read command is issued, it will be effective after /CAS latency, even if the previous
read operation does not completed. READ will be interrupted by another READ. The interval between the
commands is 1 cycle minimum. Each Read command can be issued in every clock without any restriction.
Burst length = 4, /CAS latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CLK
Command
READ A
READ B
Hi-Z
DQ
QA1
QB1
QB2
QB3
QB4
1cycle
Read to Read Command Interval
Write to Write Command Interval
During a write cycle, when a new Write command is issued, the previous burst will terminate and the new burst will
begin with a new Write command. WRITE will be interrupted by another WRITE. The interval between the
commands is minimum 1 cycle. Each Write command can be issued in every clock without any restriction.
Burst length = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command
DQ
WRITE A WRITE B
Hi-Z
DA1
DB1
DB2
DB3
DB4
1cycle
Write to Write Command Interval
Data Sheet E0196E30 (Ver. 3.0)
27
EDL1216AASA
Write to Read Command Interval
Write command and Read command interval is also 1 cycle. Only the write data before Read command will be
written. The data bus must be High-Z at least one cycle prior to the first DOUT.
Burst length = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
/CAS latency = 2
Command
WRITE A
DA1
READ B
Hi-Z
DQ
QB1
QB2
QB3
QB4
/CAS latency = 3
Command
WRITE A
DA1
READ B
Hi-Z
DQ
QB1
QB2
QB3
QB4
Write to Read Command Interval
Data Sheet E0196E30 (Ver. 3.0)
28
EDL1216AASA
Read to Write Command Interval
During a read cycle, READ can be interrupted by WRITE. The Read and Write command interval is 1 cycle
minimum. There is a restriction to avoid data conflict. The Data bus must be High-Z using DQM before WRITE.
Burst length = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command
DQM
READ WRITE
Hi-Z
DQ
D1
D2
D3
D4
1cycle
Read to Write Command Interval 1
READ can be interrupted by WRITE. DQM must be High at least 3 clocks prior to the Write command.
Burst length = 8
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CLK
/CAS latency = 2
Command
READ
WRITE
DQM
DQ
Q1
Q2
Q3
D1
WRITE
D1
D2
D3
Hi-Z is
necessary
/CAS latency = 3
Command
READ
DQM
DQ
Q1
Q2
D2
D3
Hi-Z is
necessary
Read to Write Command Interval 2
Data Sheet E0196E30 (Ver. 3.0)
29
EDL1216AASA
Burst Termination
There are two methods to terminate a burst operation other than using a Read or a Write command. One is the
burst stop command and the other is the precharge command.
Burst Termination in READ Cycle
During a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus
goes to High-Z after the /CAS latency from the burst stop command.
Burst length = X
T0
T1
T2
T3
T4
T5
T6
T7
CLK
Command
READ
BST
/CAS latency = 2
Hi-Z
DQ
Q1
Q2
Q1
Q3
/CAS latency = 3
Hi-Z
DQ
Q2
Q3
Burst Termination in READ Cycle
Remark: BST: Burst stop command
Burst Termination in WRITE Cycle
During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes
to High-Z at the same clock with the burst stop command.
Burst length = X
T0
T1
T2
T3
T4
T5
T6
T7
CLK
Command
WRITE
BST
Hi-Z
DQ
D1
D2
D3
D4
Burst Termination in WRITE Cycle
Remark: BST: Burst stop command
Data Sheet E0196E30 (Ver. 3.0)
30
EDL1216AASA
Precharge Termination in READ Cycle
During a read cycle, the burst read operation is terminated by a precharge command. When the precharge
command is issued, the burst read operation is terminated and precharge starts. The same bank can be activated
again after tRP from the precharge command. To issue a precharge command, tRAS must be satisfied.
When /CAS latency is 2, the read data will remain valid until one clock after the precharge command.
Burst length = X, /CAS latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
Command
READ
PRE
ACT
Hi-Z
DQ
Q1
Q2
Q3
Q4
t
RP
(tRAS must be satisfied)
Precharge Termination in READ Cycle (CL = 2)
When /CAS latency is 3, the read data will remain valid until two clocks after the precharge command.
Burst length = X, /CAS latency = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command
READ
PRE
ACT
Hi-Z
DQ
Q1
Q2
Q3
Q4
t
RP
(tRAS must be satisfied)
Precharge Termination in READ Cycle (CL = 3)
Data Sheet E0196E30 (Ver. 3.0)
31
EDL1216AASA
Precharge Termination in WRITE Cycle
During a write cycle, the burst write operation is terminated by a precharge command. When the precharge
command is issued, the burst write operation is terminated and precharge starts. The same bank can be activated
again after tRP from the precharge command. To issue a precharge command, tRAS must be satisfied.
The write data written prior to the precharge command will be correctly stored. However, invalid data may be written
at the same clock as the precharge command. To prevent this from happening, DQM must be high at the same
clock as the precharge command. This will mask the invalid data.
Burst length = X, /CAS latency = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command
WRITE
PRE
ACT
DQM
DQ
Hi-Z
D1
D2
D3
D4
D5
t
RP
(tRAS must be satisfied)
Precharge Termination in WRITE Cycle
Data Sheet E0196E30 (Ver. 3.0)
32
EDL1216AASA
Timing Waveforms
AC Parameters for Read Timing with Manual Precharge
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
t
CK
CLK
t
CH
tCL
CKE
/CS
t
CKH
t
CKS
t
CMS tCMH
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
t
AS tAH
L
tAC
tAC
tAC
tAC
tHZ
Hi-Z
tLZ
tOH
tOH
tOH
tRP
tOH
t
RCD
tRAS
tRC
Activate
Command
for Bank A
Read
Command
for Bank A
Precharge
Command
for Bank A
Activate
Command
for Bank A
[Burst Length = 4, /CAS Latency = 3]
Data Sheet E0196E30 (Ver. 3.0)
33
EDL1216AASA
AC Parameters for Read Timing with Auto Precharge
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
t
CK
CLK
t
CH
tCL
CKE
/CS
Auto Precharge
Start for Bank C
t
CKH
t
CKS
t
CMS tCMH
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
t
AS tAH
L
t
AC
t
AC
t
AC
t
AC
t
HZ
Hi-Z
t
RCD
t
LZ
t
OH
t
OH
t
OH
tOH
t
RAS
t
RRD
t
RC
Activate
Command
for Bank C
Read with
Auto Precharge
Command
Activate
Command
for Bank D
Activate
Command
for Bank C
for Bank C
[Burst Length = 4, /CAS Latency = 3]
Data Sheet E0196E30 (Ver. 3.0)
34
EDL1216AASA
AC Parameters for Write Timing
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
Auto Precharge
Start for Bank C
t
CKH
t
CKS
t
CMS tCMH
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
t
AS tAH
L
t
DS tDH
Hi-Z
t
RCD
t
DAL
t
RC
t
RRD
t
RCD
t
DPL
tRP
t
RAS
t
RC
Write with
Auto Precharge
Command
Activate
Command
for Bank C
Activate
Command
for Bank B
Write
Command
for Bank B
Activate Precharge
Command Command
for Bank C for Bank B
Activate
Command
for Bank B
for Bank C
[Burst Length = 4]
Data Sheet E0196E30 (Ver. 3.0)
35
EDL1216AASA
Mode Register Set
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
H
t
RSC
2 CLK (MIN.)
/CS
/RAS
/CAS
/WE
BA0
BA1
A10
ADDRESS KEY
ADD
DQM
DQ
Hi-Z
Precharge
All Banks
Command
Mode
Register Set
Command
Activate
Command
is valid
t
RP
Data Sheet E0196E30 (Ver. 3.0)
36
EDL1216AASA
Extended Mode Register Set
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
H
t
RSC
2 CLK (MIN.)
/CS
/RAS
/CAS
/WE
BA0
BA1
A10
ADDRESS KEY
ADD
DQM
DQ
Hi-Z
Precharge
All Banks
Command
Extended
Mode
Register Set
Command
Activate
Command
is valid
t
RP
Power On Sequence
CLK
Clock cycle is necessary
High level is necessary
CKE
t
RSC
tRSC
2 refresh cycles are necessary
/CS
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
ADDRESS KEY ADDRESS KEY
High level is necessary
Hi-Z
Precharge
All Banks
Command
is necessary
Mode
Extended
Mode
Register Set
Command
is necessary
CBR (Auto)
Refresh
Command
is necessary
CBR (Auto)
Refresh
Command
is necessary
Activate
Command
Register Set
Command
is necessary
t
RP
t
RC1
tRC1
Data Sheet E0196E30 (Ver. 3.0)
37
EDL1216AASA
/CS Function
Only /CS signal needs to be issued at minimum rate
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
L
L
BA1
A10
ADD
DQM
DQ
RAa
RAa
CAa
CAb
L
Hi-Z
QAa1 QAa2 QAa3 QAa4
DAb1 DAb2 DAb3 DAb4
Activate
Command
for Bank A
Read
Command
for Bank A
Write
Command
for Bank A
Precharge
Command
for Bank A
[Burst Length = 4, /CAS Latency = 3]
Data Sheet E0196E30 (Ver. 3.0)
38
EDL1216AASA
Clock Suspension during Burst Read
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
RAa
RAa
CAa
L
Hi-Z
QAa1 QAa2
QAa3
QAa4
Activate
Read
1-CLOCK
2-CLOCK
3-CLOCK
Hi-Z (turn off)
Command
for Bank A
Command
for Bank A
SUSPENDED
SUSPENDED
SUSPENDED
at the end of burst
[Burst Length = 4, /CAS Latency = 3]
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
RAa
RAa
CAa
L
Hi-Z
QAa1 QAa2
QAa3
QAa4
Activate
Command
for Bank A
Read
Command
for Bank A
1-CLOCK
SUSPENDED
2-CLOCK
SUSPENDED
3-CLOCK
SUSPENDED
at the end of burst
Hi-Z (turn off)
[Burst Length = 4, /CAS Latency = 2]
Data Sheet E0196E30 (Ver. 3.0)
39
EDL1216AASA
Clock Suspension during Burst Write
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
RAa
RAa
CAa
L
Hi-Z
DAa1
DAa2
DAa3
DAa4
Activate
Command
for Bank A
Write
1-CLOCK
2-CLOCK
SUSPENDED
3-CLOCK
SUSPENDED
Command SUSPENDED
for Bank A
Data Sheet E0196E30 (Ver. 3.0)
40
EDL1216AASA
Power Down Mode and Clock Mask
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
t
CKSP
tCKSP
CKE
/CS
VALID
/RAS
/CAS
/WE
BA0
BA1
A10
RAa
RAa
ADD
DQM
CAa
L
Hi-Z
QAa1 QAa2 QAa3
QAa4
DQ
Activate
Command
for Bank A
Read
Command
for Bank A
Precharge
Command
for Bank A
Power Down
Mode Entry
Power Down
Mode Exit
Clock Mask Clock Mask
Start End
Power Down
Mode Entry
Power Down
Mode Exit
ACTIVE STANDBY
PRECHARGE STANDBY
[Burst Length = 4, /CAS Latency = 3]
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
t
CKSP
tCKSP
CKE
/CS
VALID
/RAS
/CAS
/WE
BA0
BA1
A10
RAa
RAa
ADD
DQM
CAa
L
Hi-Z
QAa1 QAa2 QAa3
QAa4
DQ
Activate
Command
for Bank A
Read
Command
for Bank A
Precharge
Command
for Bank A
Power Down
Mode Entry
Power Down
Mode Exit
Clock Mask
Start
Clock Mask
End
Power Down
Mode Entry
Power Down
Mode Exit
ACTIVE STANDBY
PRECHARGE STANDBY
[Burst Length = 4, /CAS Latency = 2]
Data Sheet E0196E30 (Ver. 3.0)
41
EDL1216AASA
Auto Refresh
T0
T1
T2
T3
T4
T5
T6
Tn
Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6
Tm Tm + 1 Tm + 2 Tm + 3 Tm + 4 Tm + 5 Tm + 6 Tm + 7
CLK
CKE
H
/CS
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
L
Hi-Z
Q1
Precharge CBR (Auto) Refresh
Command
CBR (Auto) Refresh
Activate
Command
Read
Command
(if necessary)
t
RP
t
RC1
tRC1
Data Sheet E0196E30 (Ver. 3.0)
42
EDL1216AASA
Self Refresh (Entry and Exit)
T0
T1
T2
T3
T4
Tn
Tn + 1 Tn + 2
Tm Tm + 1
Tk
Tk + 1 Tk + 2 Tk + 3 Tk + 4
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
L
Hi-Z
Precharge
Command
Self Refresh
Entry
Self Refresh
Exit
Self Refresh Self Refresh
Activate
Command
Entry
Exit
(if necessary)
(or Activate Command)
Next Clock
Enable
Next Clock
Enable
t
RP
t
RC1
tRC1
Data Sheet E0196E30 (Ver. 3.0)
43
EDL1216AASA
Deep Power Down Entry
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
L
Hi-Z
Precharge
All Banks
Command
Deep
Power Down
Entry
t
RP
Deep Power Down Exit
CLK
Clock cycle is necessary
CKE
t
RSC
tRSC
High level is necessary
2 refresh cycles are necessary
/CS
/RAS
/CAS
/WE
BA0
BA1
A10
ADDRESS KEY ADDRESS KEY
ADD
DQM
DQ
High level is necessary
Hi-Z
Deep
Power Down
Exit
Precharge
All Banks
Command
is necessary
Mode
Extended
Mode
Register Set
Command
is necessary
CBR (Auto)
Refresh
Command
is necessary
CBR (Auto)
Refresh
Command
is necessary
Activate
Command
Register Set
Command
is necessary
Command
200µs
t
RP
t
RC1
tRC1
Data Sheet E0196E30 (Ver. 3.0)
44
EDL1216AASA
Random Column Read
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
RAa
RAa
RAa
CAa
CAb
CAc
RAa
CAa
L
Hi-Z
QAa1 QAa2 QAa3 QAa4 QAb1 QAb2 QAc1 QAc2 QAc3 QAc4
Read
Command
for Bank A
Activate
Command
for Bank A
Read
Command
for Bank A
Read
Command
for Bank A
Precharge
Command
for Bank A
Activate
Command
for Bank A
Read
Command
for Bank A
[Burst Length = 4, /CAS Latency = 3]
T0
H
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
RAd
RAa
RAa
CAa
CAb
CAc
RAd
CAd
L
Hi-Z
QAa1 QAa2 QAa3 QAa4 QAb1 QAb2 QAc1 QAc2 QAc3 QAc4
QAd1 QAd2 QAd3
Activate
Command
for Bank A
Read
Command
for Bank A
Read
Command
for Bank A
Read
Command
for Bank A
Precharge
Command
for Bank A
Activate
Command
for Bank A
Read
Command
for Bank A
[Burst Length = 4, /CAS Latency = 2]
Data Sheet E0196E30 (Ver. 3.0)
45
EDL1216AASA
Random Column Write
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
RDd
RDa
RDa
CDa
CDb
CDc
RDd
CDd
L
Hi-Z
DDa1 DDa2 DDa3 DDa4 DDb1 DDb2 DDc1 DDc2 DDc3 DDc4
DDd1 DDd2
Activate
Command
for Bank D
Write
Command
for Bank D
Write
Command
for Bank D
Write
Command
for Bank D
Precharge
Command
for Bank D
Activate
Command
for Bank D
Write
Command
for Bank D
[Burst Length = 4]
Data Sheet E0196E30 (Ver. 3.0)
46
EDL1216AASA
Random Row Read
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
RBa
RBa
RAa
RAa
RBb
CBa
CAa
RBb
CBb
L
Hi-Z
QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QBa8 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7
Activate
Command
for Bank B
Read
Command
for Bank B
Activate
Command
for Bank A
Read
Command
for Bank A
Precharge
Command
for Bank B
Activate
Command
for Bank B
Read
Command
for Bank B
Precharge
Command
for Bank A
[Burst Length = 8, /CAS Latency = 3]
T0
H
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
RDa
RDa
RBa
RBa
RDb
CDa
CBa
RDb
CDb
L
Hi-Z
QDa1 QDa2 QDa3 QDa4 QDa5 QDa6 QDa7 QDa8 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QBa8
Activate
Command
for Bank D
Read
Command
for Bank D
Activate
Command
for Bank B
Read
Command
for Bank B
Activate
Command
for Bank D
Read
Command
for Bank D
Precharge
Command
for Bank D
[Burst Length = 8, /CAS Latency = 2]
Data Sheet E0196E30 (Ver. 3.0)
47
EDL1216AASA
Random Row Write
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
RDa
RDa
RAb
RAa
RAa
ADD
CAa
CDa
RAb
CAb
L
DQM
Hi-Z
DAa1 DAa2 DAa3 DAa4 DAa5 DAa6 DAa7 DAa8 DDa1 DDa2 DDa3 DDa4 DDa5 DDa6 DDa7 DDa8 DAb1 DAb2
DQ
Activate
Command
for Bank A
Write
Command
for Bank A
Activate
Command
for Bank D
Write
Command
for Bank D
Precharge
Command
for Bank A
Activate
Command
for Bank A
Write
Command
for Bank A
Precharge
Command
for Bank D
[Burst Length = 8]
Data Sheet E0196E30 (Ver. 3.0)
48
EDL1216AASA
Read and Write
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
RAa
RAa
ADD
CAa
CAb
Write Latency = 0
CAc
DQM
DQ
L
Word Masking
Hi-Z
QAa1 QAa2 QAa3 QAa4
DAb1 DAb2
DAb4
QAc1 QAc2
Activate
Read
Write
Read
Command
for Bank A
Command
for Bank A
Command
for Bank A
Command
for Bank A
Hi-Z at the end of wrap function
0-Clock Latency
2-Clock Latency
[Burst Length = 4, /CAS Latency = 3]
T0
H
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
BA1
A10
RAa
RAa
ADD
CAa
CAb
CAc
Write Latency = 0
DQM
DQ
L
Word Masking
Hi-Z
QAa1 QAa2 QAa3 QAa4
DAb1 DAb2
DAb4
QAc1 QAc2
QAc4
Activate
Command
for Bank A
Read
Command
for Bank A
Write
Command
for Bank A
Read
Command
for Bank A
Hi-Z at the end of wrap function
0-Clock Latency
2-Clock Latency
[Burst Length = 4, /CAS Latency = 2]
Data Sheet E0196E30 (Ver. 3.0)
49
EDL1216AASA
Interleaved Column Read Cycle
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
RAa
RAa
RDa
RDa
ADD
CAa
CDa
CDb
CAb
CDc
DQM
DQ
L
Hi-Z
Aa1
Aa2
Aa3
Aa4
Da1
Da2
Db1
Db2
Dc1
Dc2
Ab1
Ab2
Ab3
Ab4
Activate
Command
for Bank A
Read
Command
for Bank A
Read
Command
for Bank D
Read
Command
for Bank D
Read
Command
for Bank D
Read
Command
for Bank A
Precharge
Command
for Bank D
Precharge
Command
for Bank A
Activate
Command
for Bank D
[Burst Length = 4, /CAS Latency = 3]
T0
H
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
BA1
A10
RAa
RDa
RDa
ADD
RAa
CAa
CDa
CDb
CDc
CAb
CDd
DQM
DQ
L
Hi-Z
Aa1
Aa2
Aa3
Aa4
Da1
Da2
Db1
Db2
Dc1
Dc2
Ab1
Ab2
Dd1
Dd2
Dd3
Dd4
Activate
Command
for Bank A
Read
Command
for Bank A
Read
Command
for Bank D
Read
Command
for Bank D
Read
Command
for Bank D
Read
Command
for Bank A
Read
Command
for Bank D
Activate
Command
for bank D
Precharge
Command
for Bank A
Precharge
Command
for Bank D
[Burst Length = 4, /CAS Latency = 2]
Data Sheet E0196E30 (Ver. 3.0)
50
EDL1216AASA
Interleaved Column Write Cycle
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
RAa
RAa
RBa
RBa
CAa
Aa1
CBa
Ba1
CBb
Bb1
CAb
CBd
CBc
DQM
DQ
L
Hi-Z
Aa2
Aa3
Aa4
Ba2
Bb2
Bc1
Bc2
Ab1
Ab2
Bd1
Bd2
Bd3
Bd4
Activate
Write
Write
Write
Write
Write
Write
Command
for Bank A
Command
for Bank A
Command
for Bank B
Command
for Bank B
Command
for Bank B
Command
for Bank A
Command
for Bank B
Activate
Command
for Bank B
Precharge
Command
for Bank A
Precharge
Command
for Bank B
[Burst Length = 4]
Data Sheet E0196E30 (Ver. 3.0)
51
EDL1216AASA
Auto Precharge after Read Burst
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
RAa
RAa
RDa
RDb
CAa RDa
CDa
CAb
RDb
CDb
L
Hi-Z
Activate
Command
for Bank A
Activate
Command
for Bank D
Read with
Auto Precharge
Command
Activate
Command
for Bank D
Read with
Auto Precharge
Command
Read
Command
for Bank A
Read with
Auto Precharge
Command
for Bank A
for Bank D
Auto Precharge
Start for Bank D
Auto Precharge
Start for Bank A
for Bank D
[Burst Length = 4, /CAS Latency = 3]
T0
H
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
BA1
A10
RAa
RAa
RDa
RDa
RDb
RAc
ADD
CAa
CDa
CAb
RDb
CDb
RAc
CAc
DQM
DQ
L
Hi-Z
Activate
Command
for Bank A
Activate
Command
for Bank A
Activate
Command
for Bank D
Activate
Command
for Bank D
Read
Command
for Bank A
Read with
Auto Precharge
Command
Read with
Auto Precharge
Command
Read with
Auto Precharge
Command
Read with
Auto Precharge
Command
for Bank D
for Bank A
for Bank D
for Bank A
Auto Precharge
Start for Bank A
Auto Precharge
Start for Bank D
Auto Precharge
Start for Bank D
[Burst Length = 4, /CAS Latency = 2]
Data Sheet E0196E30 (Ver. 3.0)
52
EDL1216AASA
Auto Precharge after Write Burst
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
RAa
RAa
RDa
RDb
CAa RDa
CDa
CAb
RDb
CDb
L
Hi-Z
Activate
Command
for Bank A
Activate
Command
for Bank D
Write with
Auto Precharge
Command
Activate
Command
for bank D
Write with
Auto Precharge
Command
for Bank A
Write
Command
for Bank A
Write with
Auto Precharge
Command
for Bank D
Auto Precharge
Start for Bank D
Auto Precharge
Start for Bank A
for Bank D
[Burst Length = 4]
Data Sheet E0196E30 (Ver. 3.0)
53
EDL1216AASA
Burst Write Operation
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
LDQM
UDQM
DQ
(lower)
DQ
(upper)
Activate
Command
for Bank D
Read
Command
for Bank D
Upper
Byte
not Read
Lower
Byte
not Read
Lower
Byte
not Write
Upper
Byte
not Write
Lower
Byte
not Write
Read
Command
for Bank D
Lower
Byte
not Read
Lower
Byte
not Read
[Burst Length = 4]
Data Sheet E0196E30 (Ver. 3.0)
54
EDL1216AASA
Precharge Termination
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
RAa
RAa
RAb
RAc
CAa
RAb
CAb
RAc
L
Write
Masking
Hi-Z
Hi-Z
DAa1 DAa2 DAa3 DAa4 DAa5
QAb1 QAb2 QAb3 QAb4
Write
Command
for Bank A
Read
Command
for Bank A
Activate
Command
for Bank A
Activate
Command
for Bank A
Precharge
Command
PRE Termination
for Bank A
Activate
Command
for Bank A
Precharge
Command
for Bank A
PRE Termination
of Burst
of Burst
t
RCD
t
DPL
t
RP
tRAS
t
RAS
[Burst Length = 8, /CAS Latency = 3]
T0
H
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
RAa
RAa
RAb
RAb
RAc
RAc
CAa
CAb
Write
Masking
L
Hi-Z
Hi-Z
DAa1 DAa2 DAa3 DAa4 DAa5
QAb1 QAb2 QAb3 QAb4 QAb5
Activate
Write
Read
Activate
Command
for Bank A
Command
for Bank A
Command
for Bank A
Command
for Bank A
Precharge
Command
for Bank A
Activate
Command
for Bank A
Precharge
Command
for Bank A
PRE Termination
of Burst
PRE Termination
of Burst
t
RCD
t
DPL
t
RP
tRAS
t
RAS
[Burst Length = 8, /CAS Latency = 2]
Data Sheet E0196E30 (Ver. 3.0)
55
EDL1216AASA
Package Drawing
54-ball FBGA (µBGA)
Solder ball: Lead free (Sn-Ag-Cu)
Unit: mm
0.2
S A
8.0±0.1
0.2
S B
INDEX AREA
1.0 max
⁄⁄ 0.2
S
S
0.1
S
0.35±0.05
7
8
9
1
2
3
A
0.8
0.8
0.8
0.8
1.6
54-φ0.45±0.05
φ0.08
M
S
A
B
ECA-TS2-0017-04
Data Sheet E0196E30 (Ver. 3.0)
56
EDL1216AASA
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the EDL1216AASA.
Type of Surface Mount Device
EDL1216AASA: 54-ball FBGA (µBGA) < Lead free (Sn-Ag-Cu) >
Data Sheet E0196E30 (Ver. 3.0)
57
EDL1216AASA
NOTES FOR CMOS DEVICES
PRECAUTION AGAINST ESD FOR MOS DEVICES
1
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to VDD or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
CME0107
Data Sheet E0196E30 (Ver. 3.0)
58
EDL1216AASA
µBGA is a registered trademark of Tessera, Inc.
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
[Product applications]
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
[Usage environment]
This product is not designed to be resistant to electromagnetic waves or radiation. This product must be
used in a non-condensing environment.
If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.
M01E0107
Data Sheet E0196E30 (Ver. 3.0)
59
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