EDS1232CABB-10L [ELPIDA]
Synchronous DRAM, 4MX32, 6ns, CMOS, PBGA90, FBGA-90;
| 型号： | EDS1232CABB-10L |
| 厂家： | 
ELPIDA MEMORY |
| 描述： | Synchronous DRAM, 4MX32, 6ns, CMOS, PBGA90, FBGA-90 时钟 动态存储器 内存集成电路 |
| 文件： | 总55页 (文件大小：571K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
128M bits SDRAM
EDS1232CABB, EDS1232CATA (4M words × 32 bits)
Description
Features
The EDS1232CA is a 128M bits SDRAM organized as
1,048,576 words × 32 bits × 4 banks. All inputs and
outputs are synchronized with the positive edge of the
clock.
• 2.5V power supply
• Clock frequency: 133MHz (max.)
• Single pulsed /RAS
• ×32 organization
They are packaged in 90-ball FBGA, 86-pin plastic
TSOP (II).
• 4 banks can operate simultaneously and
independently
• Burst read/write operation and burst read/single write
operation capability
• Programmable burst length (BL): 1, 2, 4, 8 and full
page
• 2 variations of burst sequence
Sequential (BL = 1, 2, 4, 8)
Interleave (BL = 1, 2, 4, 8)
• Programmable /CAS latency (CL): 2, 3
• Byte control by DQM
• Refresh cycles: 4096 refresh cycles/64ms
• 2 variations of refresh
Auto refresh
Self refresh
Document No. E0247E20 (Ver. 2.0)
Date Published April 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2002
EDS1232CABB, EDS1232CATA
Ordering Information
Supply
Organization
Clock frequency
Part number
voltage
(words × bits) Internal Banks
MHz (max.)
/CAS latency
Package
133
100
3
2
EDS1232CABB-75
EDS1232CABB-10
EDS1232CABB-75L
EDS1232CABB-10L
EDS1232CATA-75
EDS1232CATA-10
EDS1232CATA-75L
EDS1232CATA-10L
2.5V
4M × 32
4
90-ball FBGA
100
3
133
100
3
2
100
3
133
100
3
2
86-pin plastic
TSOP (II)
2.5V
4M × 32
4
100
3
133
100
3
2
100
3
Part Number
E D S 12 32 C A TA - 75 L
Elpida Memory
Material Type
D: Monolithic Device
Function
S: SDRAM
Density & Bank
12: 128M/4 Banks
Bit Organization
32: x32
Interface
C: 2.5V, LVTTL
Mask Revision
Package
TA: TSOP (II)
BB: FBGA
Speed
75: 133MHz/CL3
100MHz/CL2
10: 100MHz/CL3
Power Consumption
Blank: Normal
L: Low Power
Data Sheet E0247E20 (Ver. 2.0)
2
EDS1232CABB, EDS1232CATA
Pin Configurations
/xxx indicate active low signal.
90-ball FBGA
86-pin TSOP
1
2
3
4
5
6
7
8
9
VDD
DQ0
V
SS
1
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
2
A
B
C
D
E
F
VDDQ
DQ1
3
DQ26 DQ24 VSS
DQ28 VDDQ VSSQ
VSSQ DQ27 DQ25
VSSQ DQ29 DQ30
VDDQ DQ31 NC
VSS DQM3 A3
VDD DQ23 DQ21
VDDQ VSSQ DQ19
DQ22 DQ20 VDDQ
DQ17 DQ18 VDDQ
NC DQ16 VSSQ
A2 DQM2 VDD
4
DQ2
5
VSSQ
DQ3
6
7
DQ4
8
VDDQ
DQ5
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
DQ6
VSSQ
DQ7
NC
VDD
VSS
DQM0
/WE
DQM1
NC
/CAS
/RAS
/CS
NC
CLK
G
H
J
CKE
A9
A4
A7
A5
A8
A6
NC
A9
A10
NC
A0
A1
A11
BA0
A8
BA1
A7
BA1 A11
A10(AP)
A0
A6
A5
CLK CKE
DQM1 NC
BA0 /CS /RAS
/CAS /WE DQM0
VDD DQ7 VSSQ
DQ6 DQ5 VDDQ
DQ1 DQ3 VDDQ
VDDQ VSSQ DQ4
VDD DQ0 DQ2
A1
A2
A4
A3
K
L
DQM2
VDD
DQM3
VSS
NC
NC
NC
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS
VDDQ DQ8 VSS
VSSQ DQ10 DQ9
VSSQ DQ12 DQ14
DQ11 VDDQ VSSQ
DQ13 DQ15 VSS
M
N
P
R
(Top view)
(Top view)
Pin name
A0 to A11
BA0, BA1
Function
Address inputs
Bank select
DQ0 to DQ31
CLK
Data input/output
Clock input
CKE
Clock enable
Chip select
/CS
/RAS
Row address strobe
/CAS
Column address strobe
Write enable
/WE
DQM0 to DQM3
VDD
DQ mask enable
Supply voltage
Ground
VSS
VDDQ
VSSQ
Supply voltage for DQ
Ground for DQ
No connection
NC
Data Sheet E0247E20 (Ver. 2.0)
3
EDS1232CABB, EDS1232CATA
CONTENTS
Description ....................................................................................................................................................1
Features ........................................................................................................................................................1
Ordering Information .....................................................................................................................................2
Part Number..................................................................................................................................................2
Pin Configurations.........................................................................................................................................3
Electrical Specifications.................................................................................................................................5
Block Diagram.............................................................................................................................................10
Pin Function ................................................................................................................................................11
Command Operation...................................................................................................................................12
Truth Table..................................................................................................................................................16
Simplified State Diagram.............................................................................................................................22
Programming Mode Registers ....................................................................................................................23
Mode Register.............................................................................................................................................24
Power-up sequence ....................................................................................................................................27
Operation of the SDRAM ............................................................................................................................28
Timing Waveforms ......................................................................................................................................44
Package Drawing ........................................................................................................................................51
Recommended Soldering Conditions..........................................................................................................53
Revision History ..........................................................................................................................................56
Data Sheet E0247E20 (Ver. 2.0)
4
EDS1232CABB, EDS1232CATA
Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, wait more than 100 µs and then, execute Power on sequence and CBR (auto) Refresh before
proper device operation is achieved.
Absolute Maximum Ratings
Parameter
Symbol
VT
Rating
Unit
V
Note
–0.5 to +3.6
–0.5 to +3.6
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
VDD, VDDQ
IOS
V
50
mA
W
PD
1.0
Operating ambient temperature
Storage temperature
TA
0 to +70
–55 to +125
°C
°C
Tstg
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions (TA = 0 to +70°C)
Parameter
Symbol
min.
typ.
2.5
0
max.
Unit
V
Notes
Supply voltage
VDD, VDDQ 2.3
2.7
VSS
VIH
VIL
0
0
V
Input high voltage
Input low voltage
1.7
–0.3
VDD + 0.3*1
V
0.7
V
Notes: 1. VIH (max.) = VDDQ + 1.5V (pulse width ≤ 5ns).
2. VIL (min.) = –1.5V (pulse width ≤ 5ns).
Data Sheet E0247E20 (Ver. 2.0)
5
EDS1232CABB, EDS1232CATA
DC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 2.5V±0.2V, VSS, VSSQ = 0V)
Parameter
/CAS latency
Symbol
IDD1
Grade
max.
120
Unit
mA
Test condition
Notes
1
Operating current
(CL = 2)
Burst length = 1
tRC ≥ tRC (min.)
IO = 0mA
(CL = 3)
IDD1
120
1
mA
mA
mA
One bank active
Standby current in power down
IDD2P
IDD2PS
CKE ≤ VIL (max.) tCK = 15ns
CKE ≤ VIL (max.) tCK = ∞
Standby current in power down
(input signal stable)
1
CKE ≥ VIH (min.) tCK = 15ns
CS ≥ VIH (min.)
Input signals are changed one
time during 30ns
Standby current in non power
down
IDD2N
20
8
mA
mA
Standby current in non power
down
IDD2NS
CKE ≥ VIH (min.) tCK = ∞
(input signal stable)
Active standby current in power
down
IDD3P
5
4
mA
mA
CKE ≤ VIL (max.) tCK = 15ns
CKE ≤ VIL (max.), tCK = ∞
Active standby current in power
down (input signal stable)
IDD3PS
CKE ≥ VIH (min.), tCK = 15 ns,
/CS ≥ VIH (min.),
Input signals are changed one
time during 30ns.
Active standby current in non
power down
IDD3N
40
mA
mA
Active standby current in non
power down
IDD3NS
25
CKE ≥ VIH (min.), tCK = ∞,
(input signal stable)
-75
-10
150
130
tCK ≥ tCK (min.),
IO = 0mA, All banks active
Burst operating current
Refresh current
IDD4
IDD5
IDD6
mA
mA
mA
2
3
250
tRC ≥ tRC (min.)
VIH ≥ VDD − 0.2V,
VIL ≤ GND + 0.2V
Self refresh current
2.0
Self refresh current
(L-version)
IDD6
-xxL
0.6
mA
Notes: 1. IDD1 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, IDD1 is measured condition that addresses are changed only one time during tCK (min.).
2. IDD4 depends on output loading and cycle rates. Specified values are obtained with the output open.
In addition to this, IDD4 is measured condition that addresses are changed only one time during tCK
(min.).
3. IDD5 is measured on condition that addresses are changed only one time during tCK (min.).
DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 2.5V±0.2V, VSS, VSSQ = 0V)
Parameter
Symbol
ILI
min.
–1.0
max.
1.0
Unit
µA
Test condition
Notes
0 = VIN = VDDQ, VDDQ = VDD,
All other pins not under test = 0V
Input leakage current
Output leakage current
Output high voltage
Output low voltage
ILO
–1.5
2.0
—
1.5
—
µA
V
0 = VIN = VDDQ DOUT is disabled
IOH = –1mA
VOH
VOL
0.4
V
IOL = 1mA
Data Sheet E0247E20 (Ver. 2.0)
6
EDS1232CABB, EDS1232CATA
Pin Capacitance (TA = 25°C, f = 1MHz)
90-ball FBGA
86-pin TSOP (II)
Notes
Parameter
Symbol Pins
min.
1.5
Typ
—
max.
3.0
min.
2.5
Typ
—
max.
4.0
Unit
pF
Input capacitance
CI1
CI2
Address
CLK, CKE, /CS, /RAS,
/CAS, /WE, DQM
1.5
3.0
—
—
3.0
5.5
2.5
4.0
—
—
4.0
6.5
pF
pF
Data input/output
capacitance
CI/O
DQ
AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 2.5V±0.2V, VSS, VSSQ = 0V)
-75
-10
Parameter
Symbol
tCK
min.
max.
—
min.
max.
—
Unit
Notes
System clock cycle time
(CL = 2)
10
13
ns
(CL = 3)
tCK
tCH
tCL
tAC
tOH
tLZ
7.5
2.5
2.5
—
—
—
—
5.4
—
—
5.4
—
—
—
10
3
—
—
—
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK high pulse width
CLK low pulse width
Access time from CLK
Data-out hold time
3
—
2
2
—
—
6
CLK to Data-out low impedance
CLK to Data-out high impedance
Input setup time
0
0
tHZ
tSI
2
2
1.5
0.8
1.5
2
—
—
—
Input hold time
tHI
1
CKE setup time (Power down exit)
tCKSP
2
ACT to REF/ACT command period
(operation)
tRC
67.5
70
ns
(refresh)
tRC
67.5
45
70
50
ns
ns
Active to Precharge command period
tRAS
120000
120000
Active command to column command
(same bank)
tRCD
tRP
20
20
15
20
20
20
ns
ns
ns
Precharge to active command period
Write recovery or data-in to precharge
lead time
tDPL
2CLK +
20ns
2CLK +
20ns
Last data into active latency
tDAL
—
—
Active (a) to Active (b) command period tRRD
15
2
20
2
ns
Mode register set cycle time
Transition time (rise and fall)
tRSC
tT
CLK
ns
0.5
30
64
0.5
30
64
Refresh period
(4096 refresh cycles)
tREF
—
—
ms
Data Sheet E0247E20 (Ver. 2.0)
7
EDS1232CABB, EDS1232CATA
Test Conditions
• AC high level input voltage / low level input voltage: 2.4V / 0.4V
• Input timing measurement reference level: 1.4V
• Transition time (Input rise and fall time): 1ns
• Output timing measurement reference level: 1.4V
• Termination voltage (Vtt): 1.2V
tCK
tCL
tCH
2.4V
CLK
1.4V
0.4V
tSETUP tHOLD
2.4V
1.4V
0.4V
Input
tAC
tOH
Output
Vtt
50Ω
Z = 50Ω
Output
30pF
Input Waveforms and Output Load
Data Sheet E0247E20 (Ver. 2.0)
8
EDS1232CABB, EDS1232CATA
Relationship Between Frequency and Minimum Latency
Parameter
-75
133
7.5
-10
Frequency (MHz)
tCK (ns)
100
10
100
10
77
13
Symbol
lRCD
Notes
1
Active command to column command
(same bank)
Active command to active command
(same bank)
3
9
6
3
2
2
7
5
2
2
2
7
5
2
2
2
6
4
2
2
lRC
1
1
1
1
Active command to precharge command
(same bank)
lRAS
lRP
Precharge command to active command
(same bank)
Write recovery or data-in to precharge
command (same bank)
lDPL
Active command to active command
(different bank)
lRRD
lSREX
lDAL
2
1
5
2
1
4
2
1
4
2
1
4
1
Self refresh exit time
2
Last data in to active command
(Auto precharge, same bank)
= [lDPL + lRP]
= [lRC]
3
Self refresh exit to command input
lSEC
9
7
7
6
Precharge command to high impedance
(CL = 2)
lHZP
lHZP
lAPR
2
3
1
2
3
1
(CL = 3)
3
1
3
1
Last data out to active command
(auto precharge) (same bank)
Last data out to precharge
(early precharge)
(CL = 2)
lEP
–1
–1
(CL = 3)
lEP
–2
1
–2
1
–2
1
–2
1
Column command to column command
Write command to data in latency
DQM to data in
lCCD
lWCD
lDID
0
0
0
0
0
0
0
0
DQM to data out
lDOD
lCLE
lMRD
lCDD
lPEC
2
2
2
2
CKE to CLK disable
1
1
1
1
Register set to active command
/CS to command disable
Power down exit to command input
2
2
2
2
0
0
0
0
1
1
1
1
Notes: 1. IRCD to IRRD are recommended value.
2. Be valid [DESL] or [NOP] at next command of self refresh exit.
3. Except [DESL] and [NOP]
Data Sheet E0247E20 (Ver. 2.0)
9
EDS1232CABB, EDS1232CATA
Block Diagram
CLK
Clock
Generator
CKE
Bank 3
Bank 2
Bank 1
Row
Address
Address
Buffer
&
Refresh
Counter
Mode
Register
Bank 0
Sense Amplifier
DQM
/CS
Column Decoder &
Latch Circuit
Column
Address
Buffer
&
Burst
Counter
/RAS
/CAS
/WE
Data Control Circuit
DQ
Data Sheet E0247E20 (Ver. 2.0)
10
EDS1232CABB, EDS1232CATA
Pin Function
CLK (input pin)
CLK is the master clock input. Other inputs signals are referenced to the CLK rising edge.
CKE (input pins)
CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising edge is valid; otherwise it is
invalid. If the CLK rising edge is invalid, the internal clock is not issued and the Synchronous DRAM suspends
operation.
When the Synchronous DRAM is not in burst mode and CKE is negated, the device enters power down mode.
During power down mode, CKE must remain low.
/CS (input pins)
/CS low starts the command input cycle. When /CS is high, commands are ignored but operations continue.
/RAS, /CAS, and /WE (input pins)
/RAS, /CAS and /WE have the same symbols on conventional DRAM but different functions. For details, refer to the
command table.
A0 to A11 (input pins)
Row Address is determined by A0 to A11 at the CLK (clock) rising edge in the active command cycle.
Column Address is determined by A0 to 7 at the CLK rising edge in the read or write command cycle.
A10 defines the precharge mode. When A10 is high in the precharge command cycle, all banks are precharged;
when A10 is low, only the bank selected by BA0 and BA1 is precharged.
When A10 is high in read or write command cycle, the precharge starts automatically after the burst access.
BA0 and BA1 (input pin)
BA0 and BA1 are bank select signal. (See Bank Select Signal Table)
[Bank Select Signal Table]
BA0
L
BA1
L
Bank 0
Bank 1
Bank 2
Bank 3
H
L
L
H
H
H
Remark: H: VIH. L: VIL. ×: VIH or VIL
DQM (input pins)
DQM controls I/O buffers. DQM0 controls DQ0 to 7, DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to DQ23,
DQM3 controls DQ24 to DQ31. In read mode, DQM controls the output buffers like a conventional /OE pin. DQM
high and DQM low turn the output buffers off and on, respectively. The DQM latency for the read is two clocks. In
write mode, DQM controls the word mask. Input data is written to the memory cell if DQM is low but not if DQM is
high. The DQM latency for the write is zero.
DQ0 to DQ31 (input/output pins)
DQ pins have the same function as I/O pins on a conventional DRAM.
VDD, VSS, VDDQ, VSSQ (Power supply)
VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output
buffers.
Data Sheet E0247E20 (Ver. 2.0)
11
EDS1232CABB, EDS1232CATA
Command Operation
Mode register set command (/CS, /RAS, /CAS, /WE)
The Synchronous DRAM has a mode register that defines how the device operates. In this command, A0 through
A11 are the data input pins. After power on, the mode register set command must be executed to initialize the
device. The mode register can be set only when all banks are in idle state. During 2CLK (tRSC) following this
command, the Synchronous DRAM cannot accept any other commands.
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0, BA1
(Bank select)
A10
Add
Mode Register Set Command
Activate command (/CS, /RAS = Low, /CAS, /WE = High)
The Synchronous DRAM has four banks, each with 8,192 rows. This command activates the bank selected by BA0
and BA1 and a row address selected by A0 through A11. This command corresponds to a conventional DRAM's
/RAS falling.
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0, BA1
(Bank select)
A10
Add
Row
Row
Row Address Strobe and Bank Activate Command
Data Sheet E0247E20 (Ver. 2.0)
12
EDS1232CABB, EDS1232CATA
Precharge command (/CS, /RAS, /WE = Low, /CAS = High)
This command begins precharge operation of the bank selected by BA0 and BA1. When A10 is High, all banks are
precharged, regardless of BA0 and BA1. When A10 is Low, only the bank selected by BA0 and BA1 is precharged.
After this command, the Synchronous DRAM can’t accept the activate command to the precharging bank during tRP
(precharge to activate command period). This command corresponds to a conventional DRAM’s /RAS rising.
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0, BA1
(Bank select)
A10
(Precharge select)
Add
Precharge Command
Write command (/CS, /CAS, /WE = Low, /RAS = High)
If the mode register is in the burst write mode, this command sets the burst start address given by the column
address to begin the burst write operation. The first write data in burst mode can input with this command with
subsequent data on following clocks.
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0, BA1
(Bank select)
A10
Add
Col.
Column Address and Write Command
Data Sheet E0247E20 (Ver. 2.0)
13
EDS1232CABB, EDS1232CATA
Read command (/CS, /CAS = Low, /RAS, /WE = High)
Read data is available after /CAS latency requirements have been met. This command sets the burst start address
given by the column address.
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0, BA1
(Bank select)
A10
Add
Col.
Column Address and and Read Command
CBR (auto) refresh command (/CS, /RAS, /CAS = Low, /WE, CKE = High)
This command is a request to begin the CBR (auto) refresh operation. The refresh address is generated internally.
Before executing CBR (auto) refresh, all banks must be precharged. After this cycle, all banks will be in the idle
(precharged) state and ready for a row activate command. During tRC period (from refresh command to refresh or
activate command), the Synchronous DRAM cannot accept any other command
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0, BA1
(Bank select)
A10
Add
CBR (auto) Refresh Command
Data Sheet E0247E20 (Ver. 2.0)
14
EDS1232CABB, EDS1232CATA
Self refresh entry command (/CS, /RAS, /CAS, CKE = Low, /WE = High)
After the command execution, self refresh operation continues while CKE remains low. When CKE goes high, the
Synchronous DRAM exits the self refresh mode. During self refresh mode, refresh interval and refresh operation are
performed internally, so there is no need for external control. Before executing self refresh, all banks must be
precharged.
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0, BA1
(Bank select)
A10
Add
Self Refresh Entry Command
Burst stop command (/CS = /WE = Low, /RAS, /CAS = High)
This command can stop the current burst operation.
CLK
CKE
H
/CS
/RAS
/CAS
/WE
BA0, BA1
(Bank select)
A10
Add
Burst Stop Command in Full Page Mode
No operation (/CS = Low, /RAS, /CAS, /WE = High)
This command is not an execution command. No operations begin or terminate by this command.
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0, BA1
(Bank select)
A10
Add
No Operation
Data Sheet E0247E20 (Ver. 2.0)
15
EDS1232CABB, EDS1232CATA
Truth Table
Command Truth Table
CKE
n – 1
H
BA0,
BA1
×
A9 - A0,
Function
Symbol
DESL
NOP
n
×
×
×
×
×
×
×
×
×
×
×
/CS
H
L
/RAS
×
/CAS
×
/WE
×
A10
×
A11
×
Device deselect
No operation
H
H
H
H
H
H
H
L
H
H
L
H
L
×
×
×
Burst stop
BST
H
L
×
×
×
Read
READ
READA
WRIT
WRITA
ACT
H
L
H
H
L
V
L
V
V
V
V
V
×
Read with auto precharge
Write
H
L
L
V
H
L
H
L
L
V
Write with auto precharge
Bank activate
H
L
L
L
V
H
V
L
H
L
H
H
H
L
H
L
V
Precharge select bank
Precharge all banks
Mode register set
PRE
H
L
L
V
PALL
MRS
H
L
L
L
×
H
L
×
H
L
L
L
L
V
Remark: H: VIH. L: VIL. ×: VIH or VIL, V = Valid data
DQM Truth Table
CKE
DQM
0
1
2
3
Function
Symbol
ENB
n – 1
H
n
Data write / output enable
×
×
×
×
×
×
×
×
×
×
L
H
L
×
×
×
H
×
×
×
L
H
×
L
×
×
×
H
×
×
L
H
×
×
L
×
×
×
H
×
L
H
×
×
×
L
×
×
×
H
Data mask / output disable
MASK
ENB0
H
DQ0 to DQ7 write enable/output enable
DQ8 to DQ15 write enable/output enable
DQ16 to DQ23 write enable/output enable
DQ24 to DQ31 write enable/output enable
DQ0 to DQ7 write inhibit/output disable
DQ8 to DQ15 write inhibit/output disable
DQ16 to DQ23 write inhibit/output disable
DQ24 to DQ31 write inhibit/output disable
H
ENB1
H
ENB2
H
ENB3
H
MASK0
MASK 1
MASK 2
MASK 3
H
H
H
H
Remark: H: VIH. L: VIL. ×: VIH or VIL
Data Sheet E0247E20 (Ver. 2.0)
16
EDS1232CABB, EDS1232CATA
CKE Truth Table
CKE
Current state
Activating
Any
Function
Symbol
n – 1
H
L
n
/CS
×
/RAS
×
/CAS
×
/WE
×
Address
Clock suspend mode entry
Clock suspend mode
Clock suspend mode exit
CBR (auto) refresh command
Self refresh entry
L
×
×
×
×
×
L
×
×
×
×
Clock suspend
Idle
L
H
H
L
×
×
×
×
REF
H
H
L
L
L
L
H
H
H
×
Idle
SELF
L
L
L
Self refresh
Self refresh exit
H
H
L
L
H
×
H
×
×
×
×
×
×
×
L
H
L
Idle
Power down entry
Power down exit
H
H
L
H
×
H
×
H
×
L
H
H
L
Power down
H
H
×
×
×
L
H
H
H
Remark: H: VIH. L: VIL. ×: VIH or VIL
Data Sheet E0247E20 (Ver. 2.0)
17
EDS1232CABB, EDS1232CATA
Function Truth Table*1
Current state
Idle
/CS /RAS /CAS /WE Address
Command
Operation
Notes
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
×
×
×
×
DESL
Nop or power down
Nop or power down
ILLEGAL
2
2
3
3
H
H
H
L
H
L
×
×
NOP or BST
READ/READA
H
L
BA, CA, A10
WRIT/ WRITA
L
BA, CA, A10
ILLEGAL
H
H
L
H
L
BA, RA
ACT
Row activating
L
BA, A10
PRE/PALL
REF/SELF
MRS
Nop
L
H
L
×
CBR (auto) refresh or self refresh
Mode register accessing
Nop
4
L
L
OPCODE
Row active
×
×
×
×
DESL
H
H
H
L
H
L
×
×
NOP or BST
Nop
READ/READA
H
L
BA, CA, A10
Begin read: Determine AP
Begin write: Determine AP
ILLEGAL
5
5
3
6
WRIT/ WRITA
L
BA, CA, A10
H
H
L
H
L
BA, RA
ACT
L
BA, A10
PRE/PALL
REF/SELF
MRS
Precharge
L
H
L
×
ILLEGAL
L
L
OPCODE
ILLEGAL
Read
×
×
×
×
×
×
DESL
Continue burst to end → Row active
Continue burst to end → Row active
Burst stop → Row active
H
H
H
H
L
H
H
L
H
L
NOP
BST
H
L
BA, CA, A10 READ/READA Terminate burst, new read: Determine AP
BA, CA, A10 WRIT/WRITA
7
L
Terminate burst, begin write: Determine AP 7, 8
H
H
L
H
L
BA, RA
ACT
ILLEGAL
3
L
BA, A10
PRE/PALL
REF/SELF
MRS
Terminate burst, Precharging
ILLEGAL
L
H
L
×
L
L
OPCODE
ILLEGAL
Write
×
×
×
×
×
×
DESL
Continue burst to end → Write recovering
Continue burst to end → Write recovering
Burst stop → Row active
H
H
H
H
L
H
H
L
H
L
NOP
BST
H
L
BA, CA, A10 READ/READA Terminate burst, start read : Determine AP 7, 8
L
BA, CA, A10 WRIT/WRITA
Terminate burst, new write : Determine AP
7
3
9
H
H
L
H
L
BA, RA
BA, A10
×
ACT
ILLEGAL
L
PRE/PALL
REF/SELF
MRS
Terminate burst, Precharging
ILLEGAL
L
H
L
L
L
OPCODE
ILLEGAL
Data Sheet E0247E20 (Ver. 2.0)
18
EDS1232CABB, EDS1232CATA
Current state
Read with auto
precharge
/CS /RAS /CAS /WE Address
Command
Operation
Notes
H
L
L
L
L
L
L
L
L
×
×
×
×
DESL
NOP
Continue burst to end → Precharging
H
H
H
H
L
H
H
L
H
L
×
Continue burst to end → Precharging
×
BST
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
READ/READA
H
L
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
×
3
3
3
3
WRIT/ WRITA
L
H
H
L
H
L
ACT
L
PRE/PALL
REF/SELF
MRS
L
H
L
L
L
OPCODE
Continue burst to end → Write
recovering with auto precharge
Write with auto
precharge
H
L
×
×
×
×
×
DESL
NOP
Continue burst to end → Write
recovering with auto precharge
H
H
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
H
H
L
H
L
L
×
BST
ILLEGAL
READ/READA
H
L
BA, CA, A10
ILLEGAL
3
3
3
3
WRIT/ WRITA
L
BA, CA, A10
ILLEGAL
H
H
L
H
L
BA, RA
ACT
ILLEGAL
L
BA, A10
PRE/PALL
REF/SELF
MRS
ILLEGAL
L
H
L
×
ILLEGAL
L
L
OPCODE
ILLEGAL
Precharging
×
×
×
×
×
×
DESL
Nop → Enter idle after tRP
Nop → Enter idle after tRP
ILLEGAL
H
H
H
H
L
H
H
L
H
L
NOP
BST
H
L
BA, CA, A10 READ/READA ILLEGAL
3
3
3
L
BA, CA, A10 WRIT/WRITA
ILLEGAL
H
H
L
H
L
BA, RA
ACT
ILLEGAL
L
BA, A10
PRE/PALL
REF/SELF
MRS
Nop → Enter idle after tRP
ILLEGAL
L
H
L
×
L
L
OPCODE
ILLEGAL
Row activating
×
×
×
×
×
×
DESL
Nop → Enter bank active after tRCD
Nop → Enter bank active after tRCD
ILLEGAL
H
H
H
H
L
H
H
L
H
L
NOP
BST
H
L
BA, CA, A10 READ/READA ILLEGAL
3
L
BA, CA, A10 WRIT/WRITA
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
3
H
H
L
H
L
BA, RA
BA, A10
×
ACT
3, 10
3
L
PRE/PALL
REF/SELF
MRS
L
H
L
L
L
OPCODE
Data Sheet E0247E20 (Ver. 2.0)
19
EDS1232CABB, EDS1232CATA
Current state
/CS /RAS /CAS /WE Address
Command
Operation
Notes
Write recovering
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
×
×
×
×
DESL
NOP
Nop → Enter row active after tDPL
Nop → Enter row active after tDPL
Nop → Enter row active after tDPL
Start read, Determine AP
New write, Determine AP
ILLEGAL
H
H
H
H
L
H
H
L
H
L
×
×
BST
READ/READA
H
L
BA, CA, A10
8
WRIT/ WRITA
L
BA, CA, A10
H
H
L
H
L
BA, RA
ACT
3
3
L
BA, A10
PRE/PALL
REF/SELF
MRS
ILLEGAL
L
H
L
×
ILLEGAL
L
L
OPCODE
ILLEGAL
Write recovering
×
×
×
×
×
×
DESL
Nop → Enter precharge after tDPL
Nop → Enter precharge after tDPL
Nop → Enter row active after tDPL
with auto
H
H
H
H
L
H
H
L
H
L
NOP
precharge
BST
H
L
BA, CA, A10 READ/READA ILLEGAL
L
BA, CA, A10 WRIT/WRITA
ILLEGAL
3, 8
3
H
H
L
H
L
BA, RA
ACT
ILLEGAL
L
BA, A10
PRE/PALL
REF/SELF
MRS
ILLEGAL
3
L
H
L
×
ILLEGAL
L
L
OPCODE
ILLEGAL
Refresh
×
×
×
×
×
×
×
×
×
×
×
×
DESL
Nop → Enter idle after tRC
Nop → Enter idle after tRC
H
H
H
H
×
H
H
L
H
L
NOP/BST
READ/READA ILLEGAL
ACT/PRE/PALL ILLEGAL
REF/SELF/MRS ILLEGAL
H
L
L
Mode register
accessing
×
×
DESL
NOP
BST
Nop → Enter idle after tRSC
H
H
H
H
H
L
H
L
Nop → Enter idle after tRSC
ILLEGAL
H
READ/READA ILLEGAL
ACT/PRE/PLL/
ILLEGAL
L
L
L
L
×
REF/SELF/MRS
Remark: H: VIH. L: VIL. ×: VIH or VIL, V = Valid data
BA: Bank Address, CA: Column Address, RA: Row Address
Notes: 1. All entries assume that CKE was active (High level) during the preceding clock cycle.
2. If all banks are idle, and CKE is inactive (Low level), the Synchronous DRAM will enter Power down
mode.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA),
depending on the state of that bank.
4. If all banks are idle, and CKE is inactive (Low level), the Synchronous DRAM will enter Self refresh mode.
All input buffers except CKE will be disabled.
5. Illegal if tRCD is not satisfied.
6. Illegal if tRAS is not satisfied.
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus trun around, and/or write recovery requirements.
9. Must mask preceding data which don’t satisfy tDPL.
10. Illegal if tRRD is not satisfied.
Data Sheet E0247E20 (Ver. 2.0)
20
EDS1232CABB, EDS1232CATA
Command Truth Table for CKE
CKE
Current State
Self refresh
n – 1 n
/CS /RAS /CAS /WE Address
Operation
Notes
H
L
×
×
H
L
L
L
×
H
L
L
L
H
L
L
L
×
H
L
×
H
L
L
L
L
H
L
L
L
L
×
×
×
×
×
×
×
×
×
×
H
H
L
×
×
H
H
L
×
H
H
L
×
×
H
×
×
H
L
L
L
×
H
L
L
L
×
×
×
×
×
×
×
×
×
×
H
L
×
×
×
H
L
×
×
H
L
×
×
×
H
×
×
×
H
L
L
×
×
H
L
L
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
H
×
×
×
×
H
L
×
×
×
H
L
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
INVALID, CLK (n – 1) would exit self refresh
Self refresh recovery
Self refresh recovery
ILLEGAL
H
H
H
H
L
L
L
L
ILLEGAL
L
Continue self refresh
Idle after tRC
Self refresh recovery
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
Idle after tRC
ILLEGAL
ILLEGAL
ILLEGAL
L
ILLEGAL
L
ILLEGAL
L
ILLEGAL
Power down
All banks idle
×
INVALID, CLK (n – 1) would exit power down
EXIT power down
H
H
L
×
×
×
L
EXIT power down
L
Continue power down mode
Refer to operations in Function Truth Table
Refer to operations in Function Truth Table
Refer to operations in Function Truth Table
CBR (auto) Refresh
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
×
OPCODE Refer to operations in Function Truth Table
Begin power down next cycle
L
Refer to operations in Function Truth Table
Refer to operations in Function Truth Table
L
L
×
Self refresh
1
L
OPCODE Refer to operations in Function Truth Table
H
L
×
×
×
×
Exit power down next cycle
Power down
L
1
1
2
Row active
H
L
×
Refer to operations in Function Truth Table
Clock suspend
×
Any state other than
listed above
H
H
L
H
L
Refer to operations in Function Truth Table
Begin clock suspend next cycle
Exit clock suspend next cycle
Maintain clock suspend
×
×
×
H
L
L
Remark: H = VIH, L = VIL, × = VIH or VIL
Notes: 1. Self refresh can be entered only from the all banks idle state. Power down can be entered only from all
banks idle or row active state.
2. Must be legal command as defined in Function Truth Table.
Data Sheet E0247E20 (Ver. 2.0)
21
EDS1232CABB, EDS1232CATA
Simplified State Diagram
Self
Refresh
MRS
Mode
Register
Set
REF
CBR(auto)
Refresh
IDLE
CKE
CKE
Power
Down
CKE
Active
Power
Down
ROW
ACTIVE
CKE
Write
Read
CKE
Read
CKE
WRITE
SUSPEND
READ
SUSPEND
WRITE
READ
Write
CKE
CKE
CKE
CKE
CKE
READA
SUSPEND
WRITEA
SUSPEND
WRITEA
READA
CKE
PRE (Precharge termination)
Precharge
POWER
ON
Precharge
Automatic sequence
Manual input
Data Sheet E0247E20 (Ver. 2.0)
22
EDS1232CABB, EDS1232CATA
Programming Mode Registers
The mode register is programmed by the Mode register set command using address bits A11 through A0, BA0 and
BA1 as data inputs. The registers retain data until it is re-programmed, or the device loses power.
The mode register has three fields;
Options
:
:
:
:
A11 through A7, BA0, BA1
A6 through A4
A3
/CAS latency
Wrap type
Burst length
A2 through A0
Following mode register programming, no command can be issued before at least 2 CLK have elapsed.
/CAS Latency
/CAS latency is the most critical of the parameters being set. It tells the device how many clocks must elapse before
the data will be available. The value is determined by the frequency of the clock and the speed grade of the device.
”Relationship between Frequency and Latency” shows the relationship of /CAS latency to the clock period and the
speed grade of the device.
Burst Length
Burst Length is the number of words that will be output or input in a read or write cycle. After a read burst is
completed, the output bus will become High-Z. The burst length is programmable as 1, 2, 4, 8 or full page.
Wrap Type (Burst Sequence)
The wrap type specifies the order in which the burst data will be addressed. This order is programmable as either
“Sequential” or “Interleave”. The method chosen will depend on the type of CPU in the system.
Some microprocessor cache systems are optimized for sequential addressing and others for interleaved addressing.
“Burst Length Sequence” shows the addressing sequence for each burst length using them. Both sequences
support bursts of 1, 2, 4 and 8. Additionally, sequence supports the full page length.
Data Sheet E0247E20 (Ver. 2.0)
23
EDS1232CABB, EDS1232CATA
Mode Register
BA0 BA1 A11 A10 A9
A8
0
A7
1
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
0
JEDEC Standard Test Set (refresh counter test)
BA0 BA1 A11 A10 A9
A8
0
A7
0
A6
A6
A5
A4
A4
A3
A2
A2
A1
BL
A0
x
x
x
x
1
LTMODE
WT
Burst Read and Single Write
(for Write Through Cache)
BA0 BA1 A11 A10 A9
A8
1
A7
0
A5
A3
A1
A0
Use in future
BA0 BA1 A11 A10 A9
A8
1
A7
1
A6
V
A5
V
A4
V
A3
V
A2
V
A1
V
A0
x
x
x
x
x
V
Vender Specific
V = Valid
x = Don’t care
BA0 BA1 A11 A10 A9
A8
0
A7
0
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
0
LTMODE
WT
BL
Mode Register Set
Bits2-0
000
WT = 0
WT = 1
1
1
2
001
2
010
4
4
Burst length
011
100
101
110
111
8
8
R
R
R
R
R
R
R
Full page
0
1
Sequential
Wrap type
Interleave
Bits6-4
000
001
010
011
100
101
110
111
/CAS latency
R
R
2
3
Latency
mode
R
R
R
R
Remark R : Reserved
Mode Register Set Timing
CLK
CKE
/CS
/RAS
/CAS
/WE
A0 - A11,
BA0(13), BA1(A12)
Mode Register Set
Data Sheet E0247E20 (Ver. 2.0)
24
EDS1232CABB, EDS1232CATA
Burst Length and Sequence
[Burst of Two]
Starting address
(column address A0, binary)
Sequential addressing sequence
(decimal)
Interleave addressing sequence
(decimal)
0
1
0, 1
1, 0
0, 1
1, 0
[Burst of Four]
Starting address
(column address A1 to A0, binary)
Sequential addressing sequence
(decimal)
Interleave addressing sequence
(decimal)
00
01
10
11
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
[Burst of Eight]
Starting address
(column address A2 to A0, binary)
Sequential addressing sequence
(decimal)
Interleave addressing sequence
(decimal)
000
001
010
011
100
101
110
111
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
Full page burst is an extension of the above tables of sequential addressing, with the length being 256.
Data Sheet E0247E20 (Ver. 2.0)
25
EDS1232CABB, EDS1232CATA
Address Bits of Bank-Select and Precharge
BA1(A12) BA0(A13)
Result
Row
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9 A10 A11 BA1 BA0
Select Bank A
“Activate” command
0
0
1
1
0
1
0
1
(Activate command)
Select Bank B
“Activate” command
Select Bank C
“Activate” command
Select Bank D
“Activate” command
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9 A10 A11 BA1 BA0
BA1(A12) BA0(A13)
A10
0
Result
(Precharge command)
0
0
1
1
x
0
1
0
1
x
Precharge Bank A
Precharge Bank B
Precharge Bank C
Precharge Bank D
Precharge All Banks
0
0
0
1
x : Don’t care
disables Auto-Precharge
(End of Burst)
0
1
enables Auto-Precharge
(End of Burst)
Col.
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9 A10
x
BA1 BA0
(/CAS strobes)
BA1(A12) BA0(A13)
Result
enables Read/Write
commands for Bank A
0
0
1
1
0
1
0
1
enables Read/Write
commands for Bank B
enables Read/Write
commands for Bank C
enables Read/Write
commands for Bank D
Data Sheet E0247E20 (Ver. 2.0)
26
EDS1232CABB, EDS1232CATA
Power-up sequence
Power-up sequence
The SDRAM should be goes on the following sequence with power up.
The CLK, CKE, /CS, DQM and DQ pins keep low till power stabilizes.
The CLK pin is stabilized within 100 µs after power stabilizes before the following initialization sequence.
The CKE and DQM is driven to high between power stabilizes and the initialization sequence.
This SDRAM has VDD clamp diodes for CLK, CKE, /CS DQM and DQ pins. If these pins go high before power up,
the large current flows from these pins to VDD through the diodes.
Initialization sequence
When 200 µs or more has past after the above power-up sequence, all banks must be precharged using the
precharge command (PALL). After tRP delay, set 8 or more auto refresh commands (REF). Set the mode register
set command (MRS) to initialize the mode register. We recommend that by keeping DQM and CKE to High, the
output buffer becomes High-Z during Initialization sequence, to avoid DQ bus contention on memory system formed
with a number of device.
Initialization sequence
Power up sequence
100 µs
200 µs
VDD, VDDQ 0 V
Low
Low
Low
CKE, DQM
CLK
/CS, DQ
Power stabilize
Power-up sequence and Initialization sequence
Data Sheet E0247E20 (Ver. 2.0)
27
EDS1232CABB, EDS1232CATA
Operation of the SDRAM
Read/Write Operations
Bank active
Before executing a read or write operation, the corresponding bank and the row address must be activated by the
bank active (ACT) command. An interval of tRCD is required between the bank active command input and the
following read/write command input.
Read operation
A read operation starts when a read command is input. Output buffer becomes Low-Z in the (/CAS Latency - 1)
cycle after read command set. The SDRAM can perform a burst read operation.
The burst length can be set to 1, 2, 4 and 8. The start address for a burst read is specified by the column address
and the bank select address at the read command set cycle. In a read operation, data output starts after the number
of clocks specified by the /CAS Latency. The /CAS Latency can be set to 2 or 3.
When the burst length is 1, 2, 4 and 8 the DOUT buffer automatically becomes High-Z at the next clock after the
successive burst-length data has been output.
The /CAS latency and burst length must be specified at the mode register.
CLK
tRCD
Command
Address
READ
ACT
Row
Column
out 3
out 1 out 2
out 0
out 1 out 2
CL = 2
CL = 3
DQ
out 3
out 0
CL = /CAS latency
Burst Length = 4
/CAS Latency
CLK
Command
Address
tRCD
ACT
Row
READ
Column
out 0
BL = 1
out 0 out 1
BL = 2
BL = 4
BL = 8
DQ
out 3
out 0 out 1 out 2
out 0 out 1 out 2
out 3
out 5 out 6 out 7
out 4
BL : Burst Length
/CAS Latency = 2
Burst Length
Data Sheet E0247E20 (Ver. 2.0)
28
EDS1232CABB, EDS1232CATA
Write operation
Burst write or single write mode is selected by the OPCODE of the mode register.
1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write starts in the
same clock as a write command set. (The latency of data input is 0 clock.) The burst length can be set to 1, 2, 4
and 8, like burst read operations. The write start address is specified by the column address and the bank select
address at the write command set cycle.
CLK
tRCD
Command
Address
ACT
Row
WRIT
Column
in 0
in 0
BL = 1
in 1
in 1
in 1
BL = 2
BL = 4
BL = 8
DQ
in 3
in 0
in 0
in 2
in 2
in 5
in 6 in 7
in 3 in 4
CL = 2, 3
Burst write
2. Single write: A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0). In a single write
operation, data is only written to the column address and the bank select address specified by the write
command set cycle without regard to the burst length setting. (The latency of data input is 0 clock).
CLK
tRCD
Command
WRIT
ACT
Row
Column
Address
DQ
in 0
Single write
Data Sheet E0247E20 (Ver. 2.0)
29
EDS1232CABB, EDS1232CATA
Auto Precharge
Read with auto-precharge
In this operation, since precharge is automatically performed after completing a read operation, a precharge
command need not be executed after each read operation. The command executed for the same bank after the
execution of this command must be the bank active (ACT) command. In addition, an interval defined by lAPR is
required before execution of the next command.
[Clock cycle time]
/CAS latency
Precharge start cycle
3
2
2 cycle before the final data is output
1 cycle before the final data is output
CLK
ACT
READA
ACT
CL=2 Command
lRAS
DQ
out0
out1
out2
out3
lAPR
CL=3 Command
DQ
ACT
READA
ACT
lRAS
out0
out1
out2
out3
lAPR
Note: Internal auto-precharge starts at the timing indicated by " ".
And an interval of tRAS (lRAS) is required between previous active (ACT) command and internal precharge
"
".
Burst Read (BL = 4)
Write with auto-precharge
In this operation, since precharge is automatically performed after completing a burst write or single write operation,
a precharge command need not be executed after each write operation. The command executed for the same bank
after the execution of this command must be the bank active (ACT) command. In addition, an interval of lDAL is
required between the final valid data input and input of next command.
CLK
WRITA
ACT
ACT
Command
DQ
IRAS
in0 in1 in2 in3
lDAL
Note: Internal auto-precharge starts at the timing indicated by " ".
and an interval of tRAS (lRAS) is required between previous active (ACT) command
and internal precharge " ".
Burst Write (BL = 4)
Data Sheet E0247E20 (Ver. 2.0)
30
EDS1232CABB, EDS1232CATA
CLK
WRITA
ACT
ACT
Command
IRAS
DQ
in
lDAL
Note: Internal auto-precharge starts at the timing indicated by " ".
and an interval of tRAS (lRAS) is required between previous active (ACT) command
and internal precharge " ".
Single Write
Data Sheet E0247E20 (Ver. 2.0)
31
EDS1232CABB, EDS1232CATA
Burst Stop Command
During a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus
goes to High-Z after the /CAS latency from the burst stop command.
CLK
READ
BST
Command
High-Z
High-Z
DQ
out
out
out
out
out
(CL = 2)
DQ
(CL = 3)
out
Burst Stop at Read
During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes
to High-Z at the same clock with the burst stop command.
CLK
WRITE
in
BST
Command
DQ
High-Z
in
in
in
Burst Stop at Write
Data Sheet E0247E20 (Ver. 2.0)
32
EDS1232CABB, EDS1232CATA
Command Intervals
Read command to Read command interval
1. Same bank, same ROW address: When another read command is executed at the same ROW address of the
same bank as the preceding read command execution, the second read can be performed after an interval of no
less than 1 clock. Even when the first command is a burst read that is not yet finished, the data read by the
second command will be valid.
CLK
Command
ACT
Row
READ
READ
Column A Column B
Address
BS
DQ
out A0
out B2 out B3
out B0 out B1
CL = 3
BL = 4
Bank 0
Column =B
Dout
Bank0
Active
Column =A Column =B Column =A
Read Read Dout
READ to READ Command Interval (same ROW address in same bank)
2. Same bank, different ROW address: When the ROW address changes on same bank, consecutive read
commands cannot be executed; it is necessary to separate the two read commands with a precharge command
and a bank active command.
3. Different bank: When the bank changes, the second read can be performed after an interval of no less than 1
clock, provided that the other bank is in the bank active state. Even when the first command is a burst read that
is not yet finished, the data read by the second command will be valid.
CLK
Command
READ READ
ACT
ACT
Column A
Row 1
Column B
Address
BS
Row 0
DQ
out A0
out B2 out B3
out B0 out B1
Bank3
Dout
Bank0
Dout
CL = 3
BL = 4
Bank0
Active
Bank3 Bank0 Bank3
Active Read Read
READ to READ Command Interval (different bank)
Data Sheet E0247E20 (Ver. 2.0)
33
EDS1232CABB, EDS1232CATA
Write command to Write command interval
1. Same bank, same ROW address: When another write command is executed at the same ROW address of the
same bank as the preceding write command, the second write can be performed after an interval of no less than
1 clock. In the case of burst writes, the second write command has priority.
CLK
Command
Address
WRIT
ACT
Row
WRIT
Column B
Column A
BS
DQ
in A0
in B2 in B3
in B0 in B1
Bank0
Active
Column =A Column =B
Write Write
Burst Write Mode
BL = 4
Bank 0
WRITE to WRITE Command Interval (same ROW address in same bank)
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be
executed; it is necessary to separate the two write commands with a precharge command and a bank active
command.
3. Different bank: When the bank changes, the second write can be performed after an interval of no less than 1
clock, provided that the other bank is in the bank active state. In the case of burst write, the second write
command has priority.
CLK
Command
Address
ACT
WRIT WRIT
ACT
Column A
Column B
Row 1
Row 0
BS
DQ
in A0
in B2 in B3
in B0 in B1
Burst Write Mode
BL = 4
Bank0
Active
Bank3 Bank0 Bank3
Active Write Write
WRITE to WRITE Command Interval (different bank)
Data Sheet E0247E20 (Ver. 2.0)
34
EDS1232CABB, EDS1232CATA
Read command to Write command interval
1. Same bank, same ROW address: When the write command is executed at the same ROW address of the same
bank as the preceding read command, the write command can be performed after an interval of no less than 1
clock. However, DQM must be set High so that the output buffer becomes High-Z before data input.
CLK
Command
READ WRIT
CL=2
DQM
CL=3
DQ (input)
DQ (output)
in B0
in B3
in B1 in B2
BL = 4
Burst write
High-Z
READ to WRITE Command Interval (1)
CLK
Command
DQM
READ
WRIT
2 clock
CL=2
out
out
out
out
out
in
in
in
in
in
in
in
in
DQ
CL=3
READ to WRITE Command Interval (2)
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be
executed; it is necessary to separate the two commands with a precharge command and a bank active
command.
3. Different bank: When the bank changes, the write command can be performed after an interval of no less than 1
cycle, provided that the other bank is in the bank active state. However, DQM must be set High so that the
output buffer becomes High-Z before data input.
Data Sheet E0247E20 (Ver. 2.0)
35
EDS1232CABB, EDS1232CATA
Write command to Read command interval:
1. Same bank, same ROW address: When the read command is executed at the same ROW address of the same
bank as the preceding write command, the read command can be performed after an interval of no less than 1
clock. However, in the case of a burst write, data will continue to be written until one clock before the read
command is executed.
CLK
Command
DQM
WRIT
in A0
READ
DQ (input)
DQ (output)
out B0
out B1
out B2
out B3
Burst Write Mode
CL = 2
Column = A
Write
/CAS Latency
Column = B
Read
Column = B
Dout
BL = 4
Bank 0
WRITE to READ Command Interval (1)
CLK
WRIT
in A0
READ
Command
DQM
DQ (input)
in A1
DQ (output)
out B0
out B1
out B2
out B3
Burst Write Mode
CL = 2
Column = A
Write
/CAS Latency
Column = B
Read
Column = B
Dout
BL = 4
Bank 0
WRITE to READ Command Interval (2)
2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be
executed; it is necessary to separate the two commands with a precharge command and a bank active
command.
3. Different bank: When the bank changes, the read command can be performed after an interval of no less than 1
clock, provided that the other bank is in the bank active state. However, in the case of a burst write, data will
continue to be written until one clock before the read command is executed (as in the case of the same bank and
the same address).
Data Sheet E0247E20 (Ver. 2.0)
36
EDS1232CABB, EDS1232CATA
Read with auto precharge to Read command interval
1. Different bank: When some banks are in the active state, the second read command (another bank) is executed.
Even when the first read with auto-precharge is a burst read that is not yet finished, the data read by the second
command is valid. The internal auto-precharge of one bank starts at the next clock of the second command.
CLK
Command
BS
READA
READ
DQ
out A0
out A1
out B0
out B1
bank0
Read A
bank3
Read
CL= 3
BL = 4
Note: Internal auto-precharge starts at the timing indicated by "
Read with Auto Precharge to Read Command Interval (Different bank)
2. Same bank: The consecutive read command (the same bank) is illegal.
Write with auto precharge to Write command interval
".
1. Different bank: When some banks are in the active state, the second write command (another bank) is executed.
In the case of burst writes, the second write command has priority. The internal auto-precharge of one bank
starts 2 clocks later from the second command.
CLK
Command
BS
WRITA
in A0
WRIT
in B0
DQ
in A1
in B1
in B2
".
in B3
bank0
Write A
bank3
Write
BL= 4
Note: Internal auto-precharge starts at the timing indicated by "
Write with Auto Precharge to Write Command Interval (Different bank)
2. Same bank: The consecutive write command (the same bank) is illegal.
Data Sheet E0247E20 (Ver. 2.0)
37
EDS1232CABB, EDS1232CATA
Read with auto precharge to Write command interval
1. Different bank: When some banks are in the active state, the second write command (another bank) is executed.
However, DQM must be set High so that the output buffer becomes High-Z before data input. The internal auto-
precharge of one bank starts at the next clock of the second command.
CLK
Command
BS
READA
WRIT
in B0
CL = 2
DQM
CL = 3
DQ (input)
in B1
in B2
in B3
DQ (output)
High-Z
BL = 4
bank0
ReadA
bank3
Write
Note: Internal auto-precharge starts at the timing indicated by "
".
Read with Auto Precharge to Write Command Interval (Different bank)
2. Same bank: The consecutive write command from read with auto precharge (the same bank) is illegal. It is
necessary to separate the two commands with a bank active command.
Write with auto precharge to Read command interval
1. Different bank: When some banks are in the active state, the second read command (another bank) is executed.
However, in case of a burst write, data will continue to be written until one clock before the read command is
executed. The internal auto-precharge of one bank starts at 2 clocks later from the second command.
CLK
Command
BS
WRITA
in A0
READ
DQM
DQ (input)
DQ (output)
out B0
out B1
out B2 out B3
CL = 3
BL = 4
bank0
WriteA
bank3
Read
Note: Internal auto-precharge starts at the timing indicated by "
".
Write with Auto Precharge to Read Command Interval (Different bank)
2. Same bank: The consecutive read command from write with auto precharge (the same bank) is illegal. It is
necessary to separate the two commands with a bank active command.
Data Sheet E0247E20 (Ver. 2.0)
38
EDS1232CABB, EDS1232CATA
Read command to Precharge command interval (same bank)
When the precharge command is executed for the same bank as the read command that preceded it, the minimum
interval between the two commands is one clock. However, since the output buffer then becomes High-Z after the
clocks defined by lHZP, there is a case of interruption to burst read data output will be interrupted, if the precharge
command is input during burst read. To read all data by burst read, the clocks defined by lEP must be assured as
an interval from the final data output to precharge command execution.
CLK
PRE/PALL
out A2
READ
Command
DQ
out A0
out A1
out A3
CL=2
lEP = -1 cycle
READ to PRECHARGE Command Interval (same bank): To output all data (CL = 2, BL = 4)
CLK
PRE/PALL
out A1
READ
Command
DQ
out A0
out A2
out A3
CL=3
lEP = -2 cycle
READ to PRECHARGE Command Interval (same bank): To output all data (CL = 3, BL = 4)
CLK
PRE/PALL
READ
Command
High-Z
DQ
out A0
lHZP = 2
READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 2, BL = 1, 2, 4, 8)
CLK
PRE/PALL
READ
Command
DQ
High-Z
out A0
lHZP =3
READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 3, BL = 1, 2, 4, 8)
Data Sheet E0247E20 (Ver. 2.0)
39
EDS1232CABB, EDS1232CATA
Write command to Precharge command interval (same bank)
When the precharge command is executed for the same bank as the write command that preceded it, the minimum
interval between the two commands is 1 clock. However, if the burst write operation is unfinished, the input data
must be masked by means of DQM for assurance of the clock defined by tDPL.
CLK
PRE/PALL
Command
DQM
WRIT
DQ
tDPL
WRIT
CLK
Command
DQM
PRE/PALL
DQ
in A0
in A1
tDPL
WRITE to PRECHARGE Command Interval (same bank) (BL = 4 (To stop write operation))
CLK
PRE/PALL
Command
DQM
WRIT
in A0
DQ
in A1
in A2
in A3
tDPL
WRITE to PRECHARGE Command Interval (same bank) (BL = 4 (To write all data))
Data Sheet E0247E20 (Ver. 2.0)
40
EDS1232CABB, EDS1232CATA
Bank active command interval
1. Same bank: The interval between the two bank active commands must be no less than tRC.
2. In the case of different bank active commands: The interval between the two bank active commands must be no
less than tRRD.
CLK
Command
Address
BS
ACT
ACT
ROW
ROW
tRC
Bank 0
Active
Bank 0
Active
Bank Active to Bank Active for Same Bank
CLK
Command
Address
ACT
ACT
ROW:0
ROW:1
BS
tRRD
Bank 0
Active
Bank 3
Active
Bank Active to Bank Active for Different Bank
Mode register set to Bank active command interval
The interval between setting the mode register and executing a bank active command must be no less than lMRD.
CLK
Command
Address
MRS
ACT
OPCODE
BS & ROW
IMRD
Mode
Register Set
Bank
Active
Mode register set to Bank active command interval
Data Sheet E0247E20 (Ver. 2.0)
41
EDS1232CABB, EDS1232CATA
DQM Control
The DQM mask the DQ data. The UDQM and LDQM mask the upper and lower bytes of the DQ data, respectively.
The timing of UDQM/LDQM is different during reading and writing.
Reading
When data is read, the output buffer can be controlled by DQM. By setting DQM to Low, the output buffer becomes
Low-Z, enabling data output. By setting DQM to High, the output buffer becomes High-Z, and the corresponding
data is not output. However, internal reading operations continue. The latency of DQM during reading is 2 clocks.
Writing
Input data can be masked by DQM. By setting DQM to Low, data can be written. In addition, when DQM is set to
High, the corresponding data is not written, and the previous data is held. The latency of DQM during writing is 0
clock.
CLK
DQM
High-Z
DQ
out 0
out 1
out 3
lDOD = 2 Latency
Reading
CLK
DQM
DQ
in 3
in 0
in 1
lDID = 0 Latency
Writing
Data Sheet E0247E20 (Ver. 2.0)
42
EDS1232CABB, EDS1232CATA
Refresh
Auto-refresh
All the banks must be precharged before executing an auto-refresh command. Since the auto-refresh command
updates the internal counter every time it is executed and determines the banks and the ROW addresses to be
refreshed, external address specification is not required. The refresh cycles are required to refresh all the ROW
addresses within tREF (max.). The output buffer becomes High-Z after auto-refresh start. In addition, since a
precharge has been completed by an internal operation after the auto-refresh, an additional precharge operation by
the precharge command is not required.
Self-refresh
After executing a self-refresh command, the self-refresh operation continues while CKE is held Low. During self-
refresh operation, all ROW addresses are refreshed by the internal refresh timer. A self-refresh is terminated by a
self-refresh exit command. Before and after self-refresh mode, execute auto-refresh to all refresh addresses in or
within tREF (max.) period on the condition 1 and 2 below.
1. Enter self-refresh mode within time as below* after either burst refresh or distributed refresh at equal interval to
all refresh addresses are completed.
2. Start burst refresh or distributed refresh at equal interval to all refresh addresses within time as below*after
exiting from self-refresh mode.
Note: tREF (max.) / refresh cycles.
Others
Power-down mode
The SDRAM enters power-down mode when CKE goes Low in the IDLE state. In power down mode, power
consumption is suppressed by deactivating the input initial circuit. Power down mode continues while CKE is held
Low. In addition, by setting CKE to High, the SDRAM exits from the power down mode, and command input is
enabled from the next clock. In this mode, internal refresh is not performed.
Clock suspend mode
By driving CKE to Low during a bank active or read/write operation, the SDRAM enters clock suspend mode. During
clock suspend mode, external input signals are ignored and the internal state is maintained. When CKE is driven
High, the SDRAM terminates clock suspend mode, and command input is enabled from the next clock. For details,
refer to the "CKE Truth Table".
Data Sheet E0247E20 (Ver. 2.0)
43
EDS1232CABB, EDS1232CATA
Timing Waveforms
Read Cycle
tCK
tCH tCL
CLK
tRC
VIH
CKE
t
tRAS
RP
tRCD
tHI
tSI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
/CS
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
/RAS
tSI tHI
tSI tHI
/CAS
tSI tHI
tSI tHI
tSI tHI
tSI tHI
/WE
BS
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
A10
Address
DQM
tSI tHI
tSI tHI
tSI
tHI
DQ (input)
t
t
t
t
HZ
AC
AC
AC
DQ (output)
t
AC
t
t
OH
t
OH
OH
t
OH
/CAS latency = 2
Burst length = 4
Bank 0 access
= VIH or VIL
Bank 0
Read
tLZ
Bank 0
Active
Bank 0
Precharge
Data Sheet E0247E20 (Ver. 2.0)
44
EDS1232CABB, EDS1232CATA
Write Cycle
tCK
tCH tCL
CLK
tRC
VIH
CKE
tRP
tRAS
tRCD
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
/CS
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
/RAS
tSI tHI
/CAS
/WE
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
BS
tSI tHI
tSI tHI
tSI tHI
A10
tSI tHI
tSI tHI
Address
DQM
tSI
tHI
tSI tHI tSI tHI tSI tHI tSI tHI
DQ (input)
tDPL
DQ (output)
Bank 0
Precharge
Bank 0
Write
CL = 2
BL = 4
Bank 0
Active
Bank 0 access
= VIH or VIL
Mode Register Set Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
VIL
CKE
/CS
/RAS
/CAS
/WE
BS
code
C: b’
Address
DQM
valid
C: b
R: b
b
b+3
b’ b’+1 b’+2 b’+3
DQ (output)
DQ (input)
High-Z
lMRD
lRP
lRCD
Output mask
l
RCD = 3
Precharge
If needed
Mode
register
Set
Bank 3
Active
Bank 3
Read
/CAS latency = 3
Burst length = 4
= VIH or VIL
Data Sheet E0247E20 (Ver. 2.0)
45
EDS1232CABB, EDS1232CATA
Read Cycle/Write Cycle
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
CLK
CKE
VIH
Read cycle
/RAS-/CAS delay = 3
/CAS latency = 3
Burst length = 4
/CS
/RAS
=
VIH or VIL
/CAS
/WE
BS
Address
DQM
R:a
C:a
R:b
C:b
C:b'
C:b"
DQ (output)
DQ (input)
a
a+1 a+2 a+3
b
b+1 b+2 b+3 b' b'+1 b" b"+1 b"+2 b"+3
High-Z
Bank 0
Active
Bank 0
Read
Bank 3
Active
Bank 3 Bank 0
Bank 3
Read
Bank 3
Read
Bank 3
Precharge
Read
Precharge
VIH
CKE
Write cycle
/RAS-/CAS delay = 3
/CAS latency = 3
Burst length = 4
= VIH or VIL
/CS
/RAS
/CAS
/WE
BS
Address
DQM
R:a
C:a
a
R:b
C:b
C:b'
C:b"
High-Z
DQ (output)
DQ (input)
a+1 a+2 a+3
b
b+1 b+2 b+3 b'
b'+1 b" b"+1b"+2 b"+3
Bank 0
Active
Bank 0
Write
Bank 3
Active
Bank 3
Write
Bank 0
Precharge
Bank 3
Write
Bank 3
Write
Bank 3
Precharge
Data Sheet E0247E20 (Ver. 2.0)
46
EDS1232CABB, EDS1232CATA
Read/Single Write Cycle
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
CLK
V
IH
CKE
/CS
/RAS
/CAS
/WE
BS
R:a
C:a
R:b
C:a' C:a
a
Address
DQM
DQ (input)
DQ (output)
a
a+1 a+2 a+3
a
a+1 a+2 a+3
Bank 0
Active
Bank 0
Read
Bank 3
Active
Bank 0 Bank 0
Write Read
Bank 0
Precharge
Bank 3
Precharge
V
IH
CKE
/CS
/RAS
/CAS
/WE
BS
R:a
C:a
R:b
C:a
C:b C:c
Address
DQM
a
b
c
DQ (input)
DQ (output)
a
a+1
a+3
Bank 0
Active
Bank 0
Read
Bank 0
Write
Bank 0 Bank 0
Write Write
Bank 0
Precharge
Bank 3
Active
Read/Single write
/RAS-/CAS delay = 3
/CAS latency = 3
Burst length = 4
=
VIH or VIL
Data Sheet E0247E20 (Ver. 2.0)
47
EDS1232CABB, EDS1232CATA
Read/Burst Write Cycle
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
CLK
CKE
/CS
/RAS
/CAS
/WE
BS
Address
DQM
R:a
C:a
R:b
C:a'
a
a+1 a+2 a+3
DQ (input)
DQ (output)
a
a+1 a+2 a+3
Bank 0
Active
Bank 0
Read
Bank 3
Active
Clock
suspend
Bank 0
Precharge
Bank 3
Precharge
Bank 0
Write
VIH
CKE
/CS
/RAS
/CAS
/WE
BS
R:a
C:a
R:b
C:a
a
Address
DQM
DQ (input)
DQ (output)
a+1 a+2 a+3
a
a+1
a+3
Bank 0
Active
Bank 0
Read
Bank 0
Write
Bank 0
Precharge
Bank 3
Active
Read/Burst write
/RAS-/CAS delay = 3
/CAS latency = 3
Burst length = 4
=
VIH or VIL
Auto Refresh Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CLK
CKE
/CS
VIH
/RAS
/CAS
/WE
BS
Address
C:a
A10=1
R:a
DQM
DQ (input)
a
a+1
High-Z
DQ (output)
t
t
t
RC
RP
RC
Refresh cycle and
Read cycle
Active
Bank 0
Read
Bank 0
Auto Refresh
Precharge
If needed
Auto Refresh
/RAS-/CAS delay = 2
/CAS latency = 2
Burst length = 4
= VIH or VIL
Data Sheet E0247E20 (Ver. 2.0)
48
EDS1232CABB, EDS1232CATA
Self Refresh Cycle
CLK
CKE
/CS
lSREX
CKE Low
/RAS
/CAS
/WE
BS
Address
DQM
A10=1
DQ (input)
High-Z
DQ (output)
t
RC
t
t
RC
RP
Self refresh cycle
/RAS-/CAS delay = 3
CL = 3
Auto
refresh
Self refresh entry
command
Precharge command
If needed
Next
Self refresh exit
ignore command
or No operation
Next
clock
enable
Self refresh entry
command
clock
enable
BL = 4
=
VIH or VIL
Clock Suspend Mode
tSI
tSI
10 11 12 13 14 15 16 17 18 19 20
tHI
8
0
1
2
3
4
5
6
7
9
CLK
CKE
Read cycle
/RAS-/CAS delay = 2
/CAS latency = 2
Burst length = 4
= VIH or VIL
/CS
/RAS
/CAS
/WE
BS
Address
R:a
C:a
R:b
C:b
DQM
DQ (output)
DQ (input)
a
a+1 a+2
a+3
b
b+1 b+2 b+3
High-Z
Bank0 Active clock
Active suspend start
Active clock Bank0
suspend end Read
Bank3 Read suspend Read suspend
Bank0
Earliest Bank3
Precharge
Bank3
Active
start
end Read Precharge
CKE
Write cycle
/RAS-/CAS delay = 2
/CAS latency = 2
Burst length = 4
= VIH or VIL
/CS
/RAS
/CAS
/WE
BS
R:b
a+1
Address
DQM
R:a
C:a
a
C:b
High-Z
DQ (output)
DQ (input)
a+2
a+3
b
b+1 b+2 b+3
Bank0
Active clock Bank0 Bank3 Write suspend Write suspend Bank3
Earliest Bank3
Precharge
Bank0 Active clock
Active suspend start
Precharge
end Write
supend end Write Active
start
Data Sheet E0247E20 (Ver. 2.0)
49
EDS1232CABB, EDS1232CATA
Power Down Mode
CLK
CKE
/CS
CKE Low
/RAS
/CAS
/WE
BS
Address
DQM
A10=1
R: a
DQ (input)
High-Z
DQ (output)
tRP
Power down cycle
Power down
Power down entry
Precharge command
If needed
/RAS-/CAS delay = 3
mode exit
Active Bank 0
/CAS latency = 3
Burst length = 4
= VIH or VIL
Initialization Sequence
53
0
1
2
3
4
5
6
7
8
9
10
48
49
50
51
52
54
55
CLK
CKE
/CS
VIH
/RAS
/CAS
/WE
code
valid
Address
Valid
V
IH
DQM
DQ
High-Z
t
t
RC
tRP
RC
l
MRD
Bank active
If needed
All banks
Precharge
Mode register
Set
Auto Refresh
Auto Refresh
Data Sheet E0247E20 (Ver. 2.0)
50
EDS1232CABB, EDS1232CATA
Package Drawing
90-ball FBGA
Unit: mm
S
A
0.2
8.0 ± 0.1
S
B
0.2
13.0 ± 0.1
INDEX AREA
S
0.2
1.07 max.
S
0.27 ± 0.05
S
0.1
B
A
0.8
INDEX MARK
0.8
0.8
0.9
B
1.6
90-φ0.45 ± 0.05
M S A
φ0.08
ECA-TS2-0061-01
Data Sheet E0247E20 (Ver. 2.0)
51
EDS1232CABB, EDS1232CATA
86-pin TSOP (II)
Unit: mm
*1
22.22 ± 0.10
A
86
44
PIN#1 ID
1
43
A
B
0.50
0.10
0.15 to 0.30
0.81 max.
M S
B
0.80
Nom
0.25
0 to 8°
S
S
0.10
0.60 ± 0.15
Note: 1. This dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or
gate burrs shall not exceed 0.20mm per side.
ECA-TS2-0030-01
Data Sheet E0247E20 (Ver. 2.0)
52
EDS1232CABB, EDS1232CATA
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the EDS1232CA.
Type of Surface Mount Device
EDS1232CABB: 90-ball FBGA
EDS1232CATA: 86-pin TSOP (II)
Data Sheet E0247E20 (Ver. 2.0)
53
EDS1232CABB, EDS1232CATA
NOTES FOR CMOS DEVICES
PRECAUTION AGAINST ESD FOR MOS DEVICES
1
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to VDD or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
CME0107
Data Sheet E0247E20 (Ver. 2.0)
54
EDS1232CABB, EDS1232CATA
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
[Product applications]
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
[Usage environment]
This product is not designed to be resistant to electromagnetic waves or radiation. This product must be
used in a non-condensing environment.
If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.
M01E0107
Data Sheet E0247E20 (Ver. 2.0)
55
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明