EDS5116ABTA_技术文档

PRELIMINARY DATA SHEET

512M bits SDRAM

EDS5104ABTA (128M words × 4 bits)

EDS5108ABTA (64M words × 8 bits)

EDS5116ABTA (32M words × 16 bits)

Pin Configurations

Description

The EDS5104AB is a 512M bits SDRAM organized as

33,554,432 words × 4 bits × 4 banks. The EDS5108AB

is a 512M bits SDRAM organized as 16,777,216 words

× 8 bits × 4 banks. The EDS5116AB is a 512M bits

SDRAM organized as 8,388,608 words × 16 bits × 4

banks. All inputs and outputs are referred to the rising

edge of the clock input. It is packaged in standard 54-

pin plastic TSOP (II).

/xxx indicates active low signal.

54-pin TSOP

VDD VDD VDD

NC DQ0 DQ0

VDDQ VDDQ VDDQ

VSS VSS VSS

DQ15 DQ7 NC

VSSQ VSSQ VSSQ

DQ14 NC NC

DQ13 DQ6 DQ3

VDDQ VDDQ VDDQ

DQ12 NC NC

DQ11 DQ5 NC

VSSQ VSSQ VSSQ

DQ10 NC NC

DQ9 DQ4 DQ2

VDDQ VDDQ VDDQ

DQ8 NC NC

VSS VSS VSS

1

2

3

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

NC

NC DQ1

4

DQ0 DQ1 DQ2

VSSQ VSSQ VSSQ

5

6

NC

NC DQ3

7

NC DQ2 DQ4

8

VDDQ VDDQ VDDQ

9

Features

NC

NC DQ5

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

DQ1 DQ3 DQ6

VSSQ VSSQ VSSQ

NC

VDD VDD VDD

NC NC LDQM

/WE /WE /WE

/CAS /CAS /CAS

/RAS /RAS /RAS

• 3.3V power supply

• Clock frequency: 166MHz/133MHz (max.)

• LVTTL interface

NC DQ7

NC

NC NC

UDQM DQM DQM

CLK CLK CLK

CKE CKE CKE

A12 A12 A12

A11 A11 A11

• Single pulsed /RAS

• 4 banks can operate simultaneously and

independently

/CS /CS

/CS

BA0 BA0 BA0

BA1 BA1 BA1

A10 A10 A10

A0

A1

A2

A3

• Burst read/write operation and burst read/single write

operation capability

A9

A8

A7

A6

A5

A4

A9

A8

A7

A6

A5

A4

A9

A8

A7

A6

A5

A4

A0

A1

A2

A3

A0

A1

A2

A3

• Programmable burst length (BL): 1, 2, 4, 8, full page

• 2 variations of burst sequence

Sequential (BL = 1, 2, 4, 8, full page)

Interleave (BL = 1, 2, 4, 8)

VDD VDD VDD

VSS VSS VSS

X 16

X 8

• Programmable /CAS latency (CL): 2, 3

• Byte control by DQM

: DQM (EDS5104AB, EDS5108AB)

: UDQM, LDQM (EDS5116AB)

X 4

(Top view)

• Refresh cycles: 8192 refresh cycles/64ms

• 2 variations of refresh

Auto refresh

A0 to A12, Address input

BA0, BA1 Bank select address

DQ0 to DQ15 Data-input/output

DQM Input/output mask

CKE Clock enable

CLK Clock input

VDD Power for internal circuit

VSS Ground for internal circuit

/CS

Chip select

Self refresh

/RAS

/CAS

/WE

Row address strobe

Column address strobe VDDQ Power for DQ circuit

Write enable VSSQ Ground for DQ circuit

NC

No connection

Document No. E0250E10 (Ver. 1.0)

Date Published March 2002 (K) Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2002

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Ordering Information

Mask

Organization

(words × bits)

Clock frequency

MHz (max.)

Part number

Version

B

Internal Banks

4

/CAS latency Package

3

EDS5104ABTA-6B

EDS5104ABTA-7A

EDS5104ABTA-75*

166

133

54-pin Plastic

128M × 4

2, 3

3

TSOP (II)

EDS5108ABTA-6B

EDS5108ABTA-7A

EDS5108ABTA-75*

166

133

3

2, 3

3

64M × 8

EDS5116ABTA-6B

EDS5116ABTA-7A

EDS5116ABTA-75*

166

133

3

2, 3

3

32M × 16

Note: 100MHz operation at /CAS latency = 2.

Part Number

E D S 51 04 A B TA - 6B

Elpida Memory

Material Type

D: Mono

Function

S: SDRAM

Density & Bank

51: 512M/4 Banks

Bit Organization

04: x4

08: x8

16: x16

Interface

A: 3.3V, LVTTL

Mask Revision

Package

TA: TSOP (II)

Speed

6B: 166MHz/CL3

7A: 133MHz/CL2, 3

75: 133MHz/CL3

100MHz/CL2

Preliminary Data Sheet E0250E10 (Ver. 1.0)

2

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

CONTENTS

Description ....................................................................................................................................................1

Features ........................................................................................................................................................1

Pin Configurations.........................................................................................................................................1

Ordering Information .....................................................................................................................................2

Part Number..................................................................................................................................................2

Electrical Specifications.................................................................................................................................4

Block Diagram...............................................................................................................................................8

Pin Function ................................................................................................................................................13

Command Operation...................................................................................................................................15

Simplified State Diagram.............................................................................................................................23

Mode Register Configuration ......................................................................................................................24

Power-up Sequence....................................................................................................................................25

Operation of the SDRAM ............................................................................................................................27

Timing Waveforms ......................................................................................................................................43

Package Drawing ........................................................................................................................................49

Recommended Soldering Conditions..........................................................................................................50

Revision History ..........................................................................................................................................53

Preliminary Data Sheet E0250E10 (Ver. 1.0)

3

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Electrical Specifications

• All voltages are referenced to VSS (GND).

• After power up (refer to the Power-up Sequence).

Absolute Maximum Ratings

Parameter

Symbol

VT

Rating

Unit

V

Note

Voltage on any pin relative to VSS

Supply voltage relative to VSS

Short circuit output current

Power dissipation

–0.5 to VDD + 0.5 (≤ 4.6 (max.))

VDD

IOS

PD

–0.5 to +4.6

V

50

mA

W

1.0

Operating temperature

Storage temperature

TA

0 to +70

–55 to +125

°C

Tstg

Caution

Exposing the device to stress above those listed in Absolute Maximum Ratings could cause

permanent damage. The device is not meant to be operated under conditions outside the limits

described in the operational section of this specification. Exposure to Absolute Maximum Rating

conditions for extended periods may affect device reliability.

Recommended Operating Conditions (TA = 0 to 70°C)

Parameter

Symbol

VDD, VDDQ

VSS, VSSQ

VIH

min.

3.0

0

max.

Unit

V

Notes

Supply voltage

3.6

1

2

3

4

0

V

Input high voltage

Input low voltage

2.0

–0.3

VDD + 0.3

0.8

V

VIL

V

Notes: 1. The supply voltage with all VDDand VDDQ pins must be on the same level.

2. The supply voltage with all VSS and VSSQ pins must be on the same level.

3. VIH (max.) = VDD + 2.0 V for pulse width ≤ 3ns at VDD.

4. VIL (min.) = VSS – 2.0 V for pulse width ≤ 3ns at VSS.

Preliminary Data Sheet E0250E10 (Ver. 1.0)

4

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

DC Characteristics 1 (TA = 0 to +70°C, VDD, VDDQ = 3.3V 0.3V, VSS, VSSQ = 0V)

Parameter

max.

/CAS latency

Symbol

ICC1

Grade

× 4

× 8

× 16

Unit

mA

Test condition

Notes

1, 2, 3

-6B,-7A 160

-75

165

145

175

155

Burst length = 1

tRC = tRC (min.)

Operating current

140

Standby current in power

down

CKE = VIL,

tCK = tCK (min.)

ICC2P

ICC2PS

ICC2N

3

2

3

2

mA

6

7

4

Standby current in power

down (input signal stable)

2

CKE = VIL, tCK = ∞

Standby current in non

power down

-6B

30

25

30

25

CKE, /CS = VIH,

tCK = tCK (min.)

-7A, -75 25

Standby current in non

power down (input signal ICC2NS

stable)

Active standby current in

power down

CKE = VIH, tCK = ∞,

/CS = VIH

9

4

3

9

4

3

mA

8

CKE = VIL,

tCK = tCK (min.)

ICC3P

4

3

1, 2, 6

2, 7

Active standby current in

power down (input signal ICC3PS

stable)

CKE = VIL, tCK = ∞

Active standby current in

non power down

-6B

45

40

45

40

CKE, /CS = VIH,

tCK = tCK (min.)

ICC3N

1, 2, 4

2, 8

-7A, -75 40

Active standby current in

non power down (input

signal stable)

CKE = VIH, tCK = ∞,

/CS = VIH

ICC3NS

20

-6B

-7A, -75 130

160

170

140

190

160

Burst operating current

Refresh current

ICC4

ICC5

ICC6

mA

tCK = tCK (min.), BL = 4 1, 2, 5

-6B,-7A 320

-75

320

280

320

280

tRC = tRC (min.)

3

280

VIH ≥ VDD – 0.2V

VIL ≤ 0.2V

Self refresh current

4

Notes: 1. ICC depends on output load condition when the device is selected. ICC (max.) is specified at the output

open condition.

2. One bank operation.

3. Input signals are changed once per one clock.

4. Input signals are changed once per two clocks.

5. Input signals are changed once per four clocks.

6. After power down mode, CLK operating current.

7. After power down mode, no CLK operating current.

8. Input signals are VIH or VIL fixed.

DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 3.3V 0.3V, VSS, VSSQ = 0V)

Parameter

Symbol

ILI

min.

–1

max.

1

Unit

µA

V

Test condition

Notes

Input leakage current

Output leakage current

Output high voltage

Output low voltage

0 ≤ VIN ≤ VDD

ILO

–1.5

2.4

—

1.5

—

0 ≤ VOUT ≤ VDD, DQ = disable

IOH = –4 mA

VOH

VOL

0.4

V

IOL = 4 mA

Preliminary Data Sheet E0250E10 (Ver. 1.0)

5

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Pin Capacitance (TA = 25°C, VDD, VDDQ = 3.3V 0.3V)

Notes

1, 2, 4

Parameter

Symbol

CI1

Pins

CLK

min.

2.5

Typ

—

max.

3.5

Unit

pF

Input capacitance

Address, CKE, /CS, /RAS,

/CAS, /WE, DQM,

CI2

2.5

4

—

3.8

6.5

pF

1, 2, 3, 4

Data input/output capacitance

CI/O

DQ

Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.

2. Measurement condition: f = 1MHz, 1.4V bias, 200mV swing.

3. DQM = VIH to disable DOUT.

4. This parameter is sampled and not 100% tested.

AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 3.3V 0.3V, VSS, VSSQ = 0V)

-6B

-7A

min.

7.5

2.5

—

-75

min.

7.5

2.5

—

Parameter

Symbol min.

max.

—

max.

—

max.

—

Unit Notes

System clock cycle time

CLK high pulse width

CLK low pulse width

Access time from CLK

Data-out hold time

tCK

tCH

tCL

tAC

tOH

tLZ

tHZ

tSI

6.0

2.5

—

ns

1

—

1

—

ns

1

5.0

—

5.4

—

5.4

—

1, 2

1, 2, 3

1, 4

1

2.5

1

3.0

1

3.0

1

CLK to Data-out low impedance

CLK to Data-out high impedance

Input setup time

—

5.4

—

5.4

—

5.4

—

1.5

0.8

1.5

0.8

1.5

0.8

Input hold time

tHI

—

1

Ref/Active to Ref/Active command

period

tRC

60

42

18

12

—

60

45

15

—

67.5

45

—

ns

1

Active to Precharge command

period

tRAS

tRCD

tRP

120000

—

120000

—

120000

—

Active command to column

command (same bank)

20

Precharge to active command

period

—

20

—

Write recovery or data-in to

precharge lead time

tDPL

tDAL

—

15

—

2CLK +

18ns

2CLK +

15ns

2CLK +

20ns

Last data into active latency

—

Active (a) to Active (b) command

period

tRRD

tT

12

0.5

—

5

15

0.5

—

5

15

0.5

—

5

ns

ms

1

Transition time (rise and fall)

Refresh period

(8192 refresh cycles)

tREF

64

Notes: 1. AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.4V.

2. Access time is measured at 1.4V. Load condition is CL = 50pF.

3. tLZ (min.) defines the time at which the outputs achieves the low impedance state.

4. tHZ (max.) defines the time at which the outputs achieves the high impedance state.

Preliminary Data Sheet E0250E10 (Ver. 1.0)

6

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Test Conditions

• Input and output timing reference levels: 1.4V

• Input waveform and output load: See following figures

2.4 V

I/O

2.0 V

input

0.8 V

0.4 V

CL

t

T

tT

Output load

Relationship Between Frequency and Minimum Latency

Parameter

-6B

166

6.0

-7A

133

7.5

-75

Frequency (MHz)

tCK (ns)

Symbol

lRCD

7.5

3

Notes

1

Active command to column command

(same bank)

Active command to active command

(same bank)

3

2

8

6

2

lRC

10

7

9

6

3

2

1

Active command to precharge command

(same bank)

lRAS

lRP

Precharge command to active command

(same bank)

Write recovery or data-in to precharge

command (same bank)

3

lDPL

2

Active command to active command

(different bank)

lRRD

lSREX

lDAL

2

1

5

2

1

4

2

1

5

1

Self refresh exit time

2

Last data in to active command

(Auto precharge, same bank)

= [lDPL + lRP]

= [lRC]

3

Self refresh exit to command input

lSEC

10

8

9

Precharge command to high impedance

(CL = 2)

lHZP

—

3

2

3

2

3

(CL = 3)

Last data out to active command

(Auto precharge, same bank)

lAPR

1

Last data out to precharge (early precharge)

(CL = 2)

lEP

—

–1

–2

–1

–2

(CL = 3)

–2

Column command to column command

Write command to data in latency

DQM to data in

lCCD

lWCD

lDID

1

0

2

1

2

0

1

0

2

1

2

0

1

0

2

1

2

0

1

DQM to data out

lDOD

lCLE

lMRD

lCDD

lPEC

CKE to CLK disable

Register set to active command

/CS to command disable

Power down exit to command input

Notes: 1. IRCD to IRRD are recommended value.

2. Be valid [DESL] or [NOP] at next command of self refresh exit.

3. Except [DESL] and [NOP]

Preliminary Data Sheet E0250E10 (Ver. 1.0)

7

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

VIL/VIH Clamp

This SDRAM component has VIL and VIH clamp for CLK, CKE, /CS, DQM and DQ pins.

[Minimum VIL Clamp Current]

VIL (V)

I (mA)

–32

–25

–19

–13

–8

–2

–1.8

–1.6

–1.4

–1.2

–1

–4

–0.9

–0.8

–0.6

–0.4

–0.2

0

–2

–0.6

0

–2

–1.5

–1

–0.5

0

–5

–10

–15

–20

–25

–30

–35

VIL (V)

Minimum VIL Clamp Current

Preliminary Data Sheet E0250E10 (Ver. 1.0)

8

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

[Minimum VIH Clamp Current]

VIH (V)

I (mA)

10

8

VDD + 2

VDD + 1.8

VDD + 1.6

VDD + 1.4

VDD + 1.2

VDD + 1

5.5

3.5

1.5

0.3

0

VDD + 0.8

VDD + 0.6

VDD + 0.4

VDD + 0.2

VDD + 0

0

10

8

6

4

2

0

VDD + 0

VDD + 0.5

VDD + 1

VIH (V)

VDD + 1.5

VDD + 2

Minimum VIH Clamp Current

Preliminary Data Sheet E0250E10 (Ver. 1.0)

9

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

IOL/IOH Characteristics

[Output Low Current (IOL)]

IOL

VOUT (V)

0

min. (mA)

0

max. (mA)

0

0.4

27.5

41.8

51.6

58.0

70.7

72.9

75.4

77.0

77.6

80.3

81.4

70.2

0.65

0.85

1

107.5

133.8

151.2

187.7

194.4

202.5

208.6

212.0

219.6

222.6

1.4

1.5

1.65

1.8

1.95

3

3.45

250

200

150

100

min.

max.

50

0

0.5

1

1.5

2

2.5

3

3.5

VOUT (V)

Output Low Current (IOL)

Preliminary Data Sheet E0250E10 (Ver. 1.0)

10

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

[Output High Current (IOH)]

IOH

VOUT (V)

min. (mA)

max. (mA)

3.45

3.3

3

—

0

−2.4

−27.3

−74.1

2.6

2.4

2

−21.1

−34.1

−58.7

−67.3

−73.0

−77.9

−80.8

−88.6

−93.0

−129.2

−153.3

−197.0

−226.2

−248.0

−269.7

−284.3

−344.5

−502.4

1.8

1.65

1.5

1.4

1

0

0.5

1

1.5

2

2.5

3

3.5

–100

–200

–300

min.

max.

–400

–500

–600

VOUT(V)

Output High Current (IOH)

Preliminary Data Sheet E0250E10 (Ver. 1.0)

11

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Block Diagram

CLK

Clock

Generator

CKE

Bank 3

Bank 2

Bank 1

Row

Address

Buffer

&

Refresh

Counter

Mode

Register

Bank 0

Sense Amplifier

DQM

/CS

Column Decoder &

Latch Circuit

Column

Address

Buffer

&

Burst

/RAS

/CAS

/WE

Data Control Circuit

DQ

Counter

Preliminary Data Sheet E0250E10 (Ver. 1.0)

12

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Pin Function

CLK (input pin)

CLK is the master clock input to this pin. The other input signals are referred at CLK rising edge.

/CS (input pin)

When /CS is Low, the command input cycle becomes valid. When /CS is High, all inputs are ignored. However,

internal operations (bank active, burst operations, etc.) are held.

/RAS, /CAS, and /WE (input pins)

Although these pin names are the same as those of conventional DRAMs, they function in a different way. These

pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details,

refer to the command operation section.

A0 toA12 (input pins)

Row address (AX0 to AX12) is determined by A0 to A12 at the bank active command cycle CLK rising edge.

Column address is determined by A0 to A9, A11 or A12 (see Address Pins Table) at the read or write command

cycle CLK rising edge. And this column address becomes burst access start address.

[Address Pins Table]

Address (A0 to A12)

Part number

EDS5104AB

EDS5108AB

EDS5116AB

Row address

AX0 to AX12

Column address

AY0 to AY9, AY11, AY12

AY0 to AY9, AY11

AY0 to AY9

A10 defines the precharge mode. When A10 = High at the precharge command cycle, all banks are precharged.

But when A10 = Low at the precharge command cycle, only the bank that is selected by BA0 and BA1 (BS) is

precharged. For details refer to the command operation section.

BA0 and BA1 (input pin)

BA0 and BA1 are bank select signal (BS). (See Bank Select Signal Table)

[Bank Select Signal Table]

BA0

BA1

L

Bank 0

L

Bank 1

H

L

Bank 2

L

H

Bank 3

H

Remark: H: VIH. L: VIL.

CKE (input pin)

This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK rising edge is valid. If CKE is

Low, the next CLK rising edge is invalid. This pin is used for power-down mode, clock suspend mode and self

refresh mode.

Preliminary Data Sheet E0250E10 (Ver. 1.0)

13

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

DQM, UDQM and LDQM (input pins)

DQM controls input/output buffers. In 32M × 16 products, UDQM and LDQM control upper byte (DQ8 to DQ15) and

lower byte (DQ0 to DQ7).

Read operation: If DQM is High, the output buffer becomes High-Z. If the DQM is Low, the output buffer becomes

Low-Z. (The latency of DQM during reading is 2 clocks.)

Write operation: If DQM is High, the previous data is held (the new data is not written). If DQM is Low, the data is

written. (The latency of DQM during writing is 0 clock.)

DQ0 toDQ15 (input/output pins)

Data is input to and output from these pins (DQ0 to DQ3; EDS5104AB , DQ0 to DQ7; EDS5108AB, DQ0 to DQ15;

EDS5116AB).

VDD, VSS, VDDQ, VSSQ (Power supply)

VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output

buffers.

Preliminary Data Sheet E0250E10 (Ver. 1.0)

14

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Command Operation

Command Truth Table

The SDRAM recognizes the following commands specified by the /CS, /RAS, /CAS, /WE and address pins.

CKE

Function

Symbol

DESL

NOP

n – 1

H

n

×

/CS

H

L

/RAS

×

/CAS

×

/WE

×

BA1,BA0 A10

A0 to A12

Device deselect

No operation

×

V

×

L

×

L

×

V

×

V

H

L

H

L

H

L

Burst stop

BST

H

L

Read

READ

READA

WRIT

WRITA

ACT

H

L

H

L

Read with auto precharge

Write

H

L

H

L

H

L

Write with auto precharge

Bank activate

H

L

H

V

L

H

L

H

L

H

L

Precharge select bank

Precharge all banks

Mode register set

PRE

H

L

PALL

MRS

H

L

H

L

H

L

Remark: H: VIH. L: VIL. ×: VIH or VIL. V: Valid address input.

Device deselect command [DESL]

When this command is set (/CS is High), the SDRAM ignore command input at the clock. However, the internal

status is held.

No operation [NOP]

This command is not an execution command. However, the internal operations continue.

Burst stop command [BST]

This command can stop the current burst operation.

Column address strobe and read command [READ]

This command starts a read operation. In addition, the start address of burst read is determined by the column

address (see Address Pins Table in Pin Function) and the bank select address (BA0, BA1). After the read operation,

the output buffer becomes High-Z.

Read with auto-precharge [READA]

This command automatically performs a precharge operation after a burst read with a burst length of 1, 2, 4 or 8.

Column address strobe and write command [WRIT]

This command starts a write operation. When the burst write mode is selected, the column address (see Address

Pins Table in Pin Function) and the bank select address (BA0, BA1) become the burst write start address. When the

single write mode is selected, data is only written to the location specified by the column address (see Address Pins

Table in Pin Function) and the bank select address (BA0, BA1).

Write with auto-precharge [WRITA]

This command automatically performs a precharge operation after a burst write with a length of 1, 2, 4 or 8, or after a

single write operation.

Preliminary Data Sheet E0250E10 (Ver. 1.0)

15

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Row address strobe and bank activate [ACT]

This command activates the bank that is selected by BA0, BA1 and determines the row address (AX0 to AX12).

(See Bank Select Signal Table)

Precharge selected bank [PRE]

This command starts precharge operation for the bank selected by BA0, BA1. (See Bank Select Signal Table)

[Bank Select Signal Table]

BA0

L

BA1

L

Bank 0

Bank 1

H

L

Bank 2

L

H

Bank 3

H

Remark: H: VIH. L: VIL.

Precharge all banks [PALL]

This command starts a precharge operation for all banks.

Refresh [REF/SELF]

This command starts the refresh operation. There are two types of refresh operation, the one is auto-refresh, and

the other is self-refresh. For details, refer to the CKE truth table section.

Mode register set [MRS]

The SDRAM has a mode register that defines how it operates. The mode register is specified by the address pins

(A0 to A12, BA0 and BA1) at the mode register set cycle. For details, refer to the mode register configuration. After

power on, the contents of the mode register are undefined, execute the mode register set command to set up the

mode register.

Preliminary Data Sheet E0250E10 (Ver. 1.0)

16

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

DQM Truth Table

CKE

DQM

Commands

Symbol

ENB

n – 1

H

n

×

UDQM

LDQM

Write enable/output enable

L

Write inhibit/output disable

MASK

ENBU

ENBL

H

L

Upper byte write enable/output enable

Lower byte write enable/output enable

Upper byte write inhibit/output disable

Lower byte write inhibit/output disable

H

×

L

×

H

×

H

×

MASKU

MASKL

H

Remark: H: VIH. L: VIL. ×: VIH or VIL

Write: IDID is needed.

Read: IDOD is needed.

CKE Truth Table

CKE

Current state

Activating

Any

Function

Symbol

n – 1

H

L

n

/CS

×

/RAS

×

/CAS

×

/WE

Address

Clock suspend mode entry

Clock suspend mode

Clock suspend mode exit

CBR (auto) refresh command

Self refresh entry

L

×

L

×

Clock suspend

Idle

L

H

L

×

REF

H

L

H

×

Idle

SELF

L

Self refresh

Self refresh exit

H

L

H

×

H

×

L

H

L

Idle

Power down entry

Power down exit

H

L

H

×

H

×

H

×

L

H

L

Power down

H

×

L

H

Remark: H: VIH. L: VIL. ×: VIH or VIL

Preliminary Data Sheet E0250E10 (Ver. 1.0)

17

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Function Truth Table

The following table shows the operations that are performed when each command is issued in each mode of the

SDRAM.

The following table assumes that CKE is high.

Current state

/CS

/RAS /CAS /WE

Address

Command

Operation

Precharge

H

L

H

L

H

L

×

DESL

Enter IDLE after tRP

ILLEGAL

ILLEGAL*³

NOP*⁵

H

L

H

L

H

L

×

NOP

×

BST

H

L

BA, CA, A10

READ/READA

WRIT/WRITA

ACT

L

BA, CA, A10

H

L

H

L

BA, RA

L

BA, A10

PRE, PALL

REF, SELF

MRS

L

H

L

×

ILLEGAL

L

MODE

ILLEGAL

Idle

×

DESL

NOP

H

L

H

L

H

L

×

NOP

×

BST

ILLEGAL

H

L

BA, CA, A10

READ/READA

WRIT/WRITA

ACT

ILLEGAL*⁴

Bank and row active

NOP

L

BA, CA, A10

H

L

H

L

BA, RA

L

BA, A10

PRE, PALL

REF, SELF

MRS

L

H

L

×

Refresh

Mode register set*⁸

L

MODE

Row active

×

DESL

NOP

H

L

H

L

×

NOP

×

BST

ILLEGAL

H

L

BA, CA, A10

READ/READA

WRIT/WRITA

Begin read*⁶

Begin write*⁶

L

Other bank active

L

H

BA, RA

ACT

ILLEGAL on same bank*²

L

H

L

H

L

BA, A10

PRE, PALL

REF, SELF

MRS

Precharge*⁷

L

H

L

×

ILLEGAL

L

MODE

ILLEGAL

Read

×

H

×

H

L

×

DESL

Continue burst to end

Burst stop

H

NOP

BST

Continue burst read to /CAS

latency and New read

L

H

L

H

L

BA, CA, A10

BA, RA

READ/READA

WRIT/WRITA

ACT

Term burst read/start write

Other bank active

H

ILLEGAL on same bank*²

L

H

L

H

L

BA, A10

×

PRE, PALL

REF, SELF

MRS

Term burst read and Precharge

ILLEGAL

MODE

ILLEGAL

Preliminary Data Sheet E0250E10 (Ver. 1.0)

18

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Current state

/CS

H

/RAS /CAS /WE

Address

Command

DESL

Operation

Read with auto-

precharge

Continue burst to end and

precharge

×

Continue burst to end and

precharge

L

H

×

NOP

L

H

L

H

L

×

BST

ILLEGAL

BA, CA, A10

READ/READA

WRIT/WRITA

ILLEGAL*³

L

Other bank active

L

H

BA, RA

ACT

ILLEGAL on same bank*²

L

H

L

H

L

BA, A10

PRE, PALL

REF, SELF

MRS

ILLEGAL*³

L

H

L

×

ILLEGAL

L

MODE

ILLEGAL

Write

×

H

L

×

H

L

×

DESL

Continue burst to end

Burst stop

H

×

NOP

×

BST

H

L

BA, CA, A10

READ/READA

WRIT/WRITA

Term burst and New read

Term burst and New write

L

Other bank active

L

H

BA, RA

ACT

ILLEGAL on same bank*³

L

H

L

H

L

BA, A10

×

PRE, PALL

REF, SELF

MRS

Term burst write and Precharge*¹

ILLEGAL

MODE

Write with auto-

precharge

Continue burst to end and

precharge

H

L

×

DESL

NOP

Continue burst to end and

precharge

H

L

H

L

H

L

×

BST

ILLEGAL

BA, CA, A10

READ/READA

WRIT/WRITA

ILLEGAL*³

L

Other bank active

L

H

BA, RA

ACT

ILLEGAL on same bank*³

L

H

L

H

L

BA, A10

PRE, PALL

REF, SELF

MRS

ILLEGAL*³

L

H

L

×

ILLEGAL

L

MODE

ILLEGAL

Refresh (auto-refresh)

×

H

L

×

DESL

Enter IDLE after tRC

ILLEGAL

ILLEGAL*⁴

ILLEGAL

H

L

H

L

×

NOP

×

BST

H

L

BA, CA, A10

BA, RA

BA, A10

×

READ/READA

WRIT/WRITA

ACT

L

H

L

H

L

PRE, PALL

REF, SELF

MRS

L

H

L

MODE

ILLEGAL

Preliminary Data Sheet E0250E10 (Ver. 1.0)

19

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Current state

/CS

H

L

/RAS /CAS /WE

Address

Command

DESL

Operation

NOP

Mode register set

×

H

L

H

L

H

L

×

NOP

L

×

BST

ILLEGAL

L

H

L

BA, CA, A10

BA, RA

BA, A10

×

READ/READA

WRIT/WRITA

ACT

ILLEGAL*⁴

Bank and row active*⁹

NOP

Refresh*⁹

Mode register set*⁸

L

H

L

H

L

PRE, PALL

REF, SELF

MRS

L

H

L

MODE

Remark: H: VIH. L: VIL. ×: VIH or VIL

Notes: 1.An interval of tDPL is required between the final valid data input and the precharge command.

2. If tRRD is not satisfied, this operation is illegal.

3. Illegal for same bank, except for another bank.

4. Illegal for all banks.

5. NOP for same bank, except for another bank.

6. Illegal if tRCD is not satisfied.

7. Illegal if tRAS is not satisfied.

8. MRS command must be issued after DOUT finished, in case of DOUT remaining.

9. Illegal if lMRD is not satisfied.

Preliminary Data Sheet E0250E10 (Ver. 1.0)

20

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Command Truth Table for CKE

CKE

Current State

Self refresh

n – 1 n

/CS /RAS /CAS /WE Address

Operation

Notes

H

L

×

H

L

×

H

L

H

L

×

H

L

×

H

L

H

L

×

H

L

×

H

L

×

H

L

×

H

×

H

L

×

H

L

×

H

L

×

H

L

×

H

L

×

H

×

H

L

×

H

L

×

H

×

H

L

×

H

L

×

INVALID, CLK (n – 1) would exit self refresh

Self refresh recovery

ILLEGAL

H

L

ILLEGAL

L

Continue self refresh

Idle after t^RC

Self refresh recovery

H

L

H

L

Idle after t^RC

ILLEGAL

L

ILLEGAL

L

ILLEGAL

L

ILLEGAL

Power down

All banks idle

×

INVALID, CLK (n – 1) would exit power down

EXIT power down

H

L

×

L

EXIT power down

L

Continue power down mode

Refer to operations in Function Truth Table

CBR (auto) Refresh

H

L

H

L

×

OPCODE Refer to operations in Function Truth Table

Begin power down next cycle

L

Refer to operations in Function Truth Table

L

×

Self refresh

1

L

OPCODE Refer to operations in Function Truth Table

H

L

×

Exit power down next cycle

Power down

L

1

2

Row active

H

L

×

Refer to operations in Function Truth Table

Clock suspend

×

Any state other than

listed above

H

L

H

L

Refer to operations in Function Truth Table

Begin clock suspend next cycle

Exit clock suspend next cycle

Maintain clock suspend

×

H

L

Remark: H: VIH. L: VIL. ×: VIH or VIL

Notes: 1. Self refresh can be entered only from the all banks idle state. Power down can be entered only from all

banks idle. Clock suspend can be entered only from following states, row active, read, read with auto-

precharge, write and write with auto precharge.

2. Must be legal command as defined in Function Truth Table.

Preliminary Data Sheet E0250E10 (Ver. 1.0)

21

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Clock suspend mode entry

The SDRAM enters clock suspend mode from active mode by setting CKE to Low. If command is input in the clock

suspend mode entry cycle, the command is valid. The clock suspend mode changes depending on the current

status (1 clock before) as shown below.

ACTIVE clock suspend

This suspend mode ignores inputs after the next clock by internally maintaining the bank active status.

READ suspend and READ with Auto-precharge suspend

The data being output is held (and continues to be output).

WRITE suspend and WRIT with Auto-precharge suspend

In this mode, external signals are not accepted. However, the internal state is held.

Clock suspend

During clock suspend mode, keep the CKE to Low.

Clock suspend mode exit

The SDRAM exits from clock suspend mode by setting CKE to High during the clock suspend state.

IDLE

In this state, all banks are not selected, and completed precharge operation.

Auto-refresh command [REF]

When this command is input from the IDLE state, the SDRAM starts auto-refresh operation. (The auto-refresh is the

same as the CBR refresh of conventional DRAMs.) During the auto-refresh operation, refresh address and bank

select address are generated inside the SDRAM. For every auto-refresh cycle, the internal address counter is

updated. Accordingly, 8192 times are required to refresh the entire memory. Before executing the auto-refresh

command, all the banks must be in the IDLE state. In addition, since the precharge for all banks is automatically

performed after auto-refresh, no precharge command is required after auto-refresh.

Self-refresh entry [SELF]

When this command is input during the IDLE state, the SDRAM starts self-refresh operation. After the execution of

this command, self-refresh continues while CKE is Low. Since self-refresh is performed internally and automatically,

external refresh operations are unnecessary.

Power down mode entry

When this command is executed during the IDLE state, the SDRAM enters power down mode. In power down

mode, power consumption is suppressed by cutting off the initial input circuit.

Self-refresh exit

When this command is executed during self-refresh mode, the SDRAM can exit from self-refresh mode. After exiting

from self-refresh mode, the SDRAM enters the IDLE state.

Power down exit

When this command is executed at the power down mode, the SDRAM can exit from power down mode. After

exiting from power down mode, the SDRAM enters the IDLE state.

Preliminary Data Sheet E0250E10 (Ver. 1.0)

22

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Simplified State Diagram

SELF

REFRESH

SR ENTRY

SR EXIT

*1

MRS

REFRESH

MODE

REGISTER

SET

AUTO

REFRESH

IDLE

CKE

CKE_

IDLE

POWER

DOWN

ACTIVE

CLOCK

SUSPEND

CKE_

CKE

ROW

ACTIVE

BST

WRITE

READ

Write

WRITE

WITH

AP

READ

WITH

AP

Read

CKE_

CKE

WRITE

SUSPEND

READ

SUSPEND

WRITE

READ

WRITE

CKE

READ

WITH AP

WRITE

WITH AP

WRITE

WITH AP

READ

WITH AP

PRECHARGE

CKE_

WRITEA

SUSPEND

READA

SUSPEND

WRITEA

READA

CKE

PRECHARGE PRECHARGE

POWER

APPLIED

POWER

ON

PRECHARGE

Automatic transition after completion of command.

Transition resulting from command input.

Note: 1. After the auto-refresh operation, precharge operation is performed automatically and

enter the IDLE state.

Preliminary Data Sheet E0250E10 (Ver. 1.0)

23

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Mode Register Configuration

The mode register is set by the input to the address pins (A0 to A12, BA0 and BA1) during mode register set cycles.

The mode register consists of five sections, each of which is assigned to address pins.

BA1, BA0, A8, A9, A10, A11, A12: (OPCODE): The SDRAM has two types of write modes. One is the burst write

mode, and the other is the single write mode. These bits specify write mode.

Burst read and burst write: Burst write is performed for the specified burst length starting from the column address

specified in the write cycle.

Burst read and single write: Data is only written to the column address specified during the write cycle, regardless of

the burst length.

A7: Keep this bit Low at the mode register set cycle. If this pin is high, the vender test mode is set.

A6, A5, A4: (LMODE): These pins specify the /CAS latency.

A3: (BT): A burst type is specified.

A2, A1, A0: (BL): These pins specify the burst length.

A12

A11

OPCODE

BA1 BA0

A10

A9

A8

A7

0

A6

A5

A4

A3

BT

A2

A1

BL

A0

LMODE

A6 A5 A4 CAS latency

A3 Burst type

Burst length

BT=0 BT=1

A2 A1 A0

R

2

0

1

0

1

X

0

1

0

1

X

0

1

Sequential

Interleave

1

2

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

R

8

R

A9 A8

Write mode

A10

BA1

0

BA0 A12

A11

R

0

1

0

1

0

1

Burst read and burst write

0

X

0

X

0

X

0

X

F.P.

R

X

Burst read and single write

R

F.P.: Full Page

R is Reserved (inhibit)

X: 0 or 1

X

Mode Register Set Timing

Preliminary Data Sheet E0250E10 (Ver. 1.0)

24

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Burst length = 2

Starting Ad. Addressing(decimal)

Burst length = 4

Starting Ad. Addressing(decimal)

A0

0

Sequential Interleave

A1

0

A0 Sequential

Interleave

0, 1,

1, 0,

0, 1,

1, 0,

0

1

0

1

0, 1, 2, 3,

1, 2, 3, 0,

2, 3, 0, 1,

0, 1, 2, 3,

1, 0, 3, 2,

2, 3, 0, 1,

3, 2, 1, 0,

1

0

1

3,

0, 1, 2,

Burst length = 8

Starting Ad.

Addressing(decimal)

A2 A1 A0 Sequential

Interleave

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0, 1, 2, 3, 4, 5, 6, 7,

1, 2, 3, 4, 5, 6, 7, 0,

2, 3, 4, 5, 6, 7, 0, 1,

3, 4, 5, 6, 7, 0, 1, 2,

4, 5, 6, 7, 0, 1, 2, 3,

5, 6, 7, 0, 1, 2, 3, 4,

6, 7, 0, 1, 2, 3, 4, 5,

7, 0, 1, 2, 3, 4, 5, 6,

0, 1, 2, 3, 4, 5, 6, 7,

1, 0, 3, 2, 5, 4, 7, 6,

2, 3, 0, 1, 6, 7, 4, 5,

3, 2, 1, 0, 7, 6, 5, 4,

4, 5, 6, 7, 0, 1, 2, 3,

5, 4, 7, 6, 1, 0, 3, 2,

6, 7, 4, 5, 2, 3, 0, 1,

7, 6, 5, 4, 3, 2, 1, 0,

Burst Sequence

Full page burst is available only for sequential addressing. The addressing sequence is started from the column

address that is asserted by read/write command. And the address is increased one by one.

It is back to the address 0 when the address reaches at the end of address 4,095 (for 128M ×4 device), 2,047 (for

64M × 8 device) and 1,023 (for 32M × 16 device). “Full page” never stops the burst read/write.

Preliminary Data Sheet E0250E10 (Ver. 1.0)

25

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Power-up Sequence

The SDRAM should be goes on the following sequence with power up.

The CLK, CKE, /CS, DQM and DQ pins keep low till power stabilizes.

The CLK pin is stabilized within 100 µs after power stabilizes before the following initialization sequence.

The CKE and DQM is driven to high between power stabilizes and the initialization sequence.

This SDRAM has VDD clamp diodes for CLK, CKE, /CS DQM and DQ pins. If these pins go high before power up,

the large current flows from these pins to VDD through the diodes.

Initialization Sequence

When 200 µs or more has past after the above power-up sequence, all banks must be precharged using the

precharge command (PALL). After tRP delay, set 8 or more auto refresh commands (REF). Set the mode register

set command (MRS) to initialize the mode register. We recommend that by keeping DQM and CKE to High, the

output buffer becomes High-Z during Initialization sequence, to avoid DQ bus contention on memory system formed

with a number of device.

Initialization sequence

Power up sequence

100 µs

200 µs

VDD, VDDQ 0 V

Low

CKE, DQM

CLK

/CS, DQ

Power stabilize

Power-up sequence and Initialization sequence

Preliminary Data Sheet E0250E10 (Ver. 1.0)

26

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Operation of the SDRAM

Read/Write Operations

Bank active

Before executing a read or write operation, the corresponding bank and the row address must be activated by the

bank active (ACT) command. An interval of tRCD is required between the bank active command input and the

following read/write command input.

Read operation

A read operation starts when a read command is input. Output buffer becomes Low-Z in the (/CAS Latency - 1)

cycle after read command set. The SDRAM can perform a burst read operation.

The burst length can be set to 1, 2, 4 and 8. The start address for a burst read is specified by the column address

and the bank select address at the read command set cycle. In a read operation, data output starts after the number

of clocks specified by the /CAS Latency. The /CAS Latency can be set to 2 or 3.

When the burst length is 1, 2, 4 and 8 the DOUT buffer automatically becomes High-Z at the next clock after the

successive burst-length data has been output.

The /CAS latency and burst length must be specified at the mode register.

CLK

tRCD

Command

Address

READ

ACT

Row

Column

out 3

out 1 out 2

out 0

out 1 out 2

CL = 2

CL = 3

DQ

out 3

out 0

CL = /CAS latency

Burst Length = 4

/CAS Latency

CLK

Command

Address

tRCD

ACT

Row

READ

Column

out 0

BL = 1

out 0 out 1

BL = 2

BL = 4

BL = 8

DQ

out 3

out 0 out 1 out 2

out 3

out 5 out 6 out 7

out 4

BL : Burst Length

/CAS Latency = 2

Burst Length

Preliminary Data Sheet E0250E10 (Ver. 1.0)

27

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Write operation

Burst write or single write mode is selected by the OPCODE of the mode register.

1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write starts in the

same clock as a write command set. (The latency of data input is 0 clock.) The burst length can be set to 1, 2, 4

and 8, like burst read operations. The write start address is specified by the column address and the bank select

address at the write command set cycle.

CLK

tRCD

Command

Address

ACT

Row

WRIT

Column

in 0

BL = 1

in 1

BL = 2

BL = 4

BL = 8

DQ

in 3

in 0

in 2

in 5

in 6 in 7

in 3 in 4

CL = 2, 3

Burst write

2. Single write: A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0). In a single write

operation, data is only written to the column address and the bank select address specified by the write

command set cycle without regard to the burst length setting. (The latency of data input is 0 clock).

CLK

tRCD

Command

WRIT

ACT

Row

Column

Address

DQ

in 0

Single write

Preliminary Data Sheet E0250E10 (Ver. 1.0)

28

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Auto Precharge

Read with auto-precharge

In this operation, since precharge is automatically performed after completing a read operation, a precharge

command need not be executed after each read operation. The command executed for the same bank after the

execution of this command must be the bank active (ACT) command. In addition, an interval defined by lAPR is

required before execution of the next command.

[Clock cycle time]

/CAS latency

Precharge start cycle

3

2

2 cycle before the final data is output

1 cycle before the final data is output

CLK

ACT

READA

ACT

CL=2 Command

lRAS

DQ

out0

out1

out2

out3

lAPR

CL=3 Command

DQ

ACT

READA

ACT

lRAS

out0

out1

out2

out3

lAPR

Note: Internal auto-precharge starts at the timing indicated by " ".

And an interval of tRAS (lRAS) is required between previous active (ACT) command and internal precharge

"

".

Burst Read (BL = 4)

Write with auto-precharge

In this operation, since precharge is automatically performed after completing a burst write or single write operation,

a precharge command need not be executed after each write operation. The command executed for the same bank

after the execution of this command must be the bank active (ACT) command. In addition, an interval of lDAL is

required between the final valid data input and input of next command.

CLK

WRITA

ACT

Command

DQ

I_RAS

in0 in1 in2 in3

lDAL

Note: Internal auto-precharge starts at the timing indicated by " ".

and an interval of tRAS (lRAS) is required between previous active (ACT) command

and internal precharge " ".

Burst Write (BL = 4)

Preliminary Data Sheet E0250E10 (Ver. 1.0)

29

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

CLK

WRITA

ACT

Command

IRAS

DQ

in

lDAL

Note: Internal auto-precharge starts at the timing indicated by " ".

and an interval of tRAS (lRAS) is required between previous active (ACT) command

and internal precharge " ".

Single Write

Preliminary Data Sheet E0250E10 (Ver. 1.0)

30

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Burst Stop Command

During a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus

goes to High-Z after the /CAS latency from the burst stop command.

CLK

READ

BST

Command

High-Z

DQ

out

(CL = 2)

DQ

(CL = 3)

out

Burst Stop at Read

During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes

to High-Z at the same clock with the burst stop command.

CLK

WRITE

in

BST

Command

DQ

High-Z

in

Burst Stop at Write

Preliminary Data Sheet E0250E10 (Ver. 1.0)

31

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Command Intervals

Read command to Read command interval

1. Same bank, same ROW address: When another read command is executed at the same ROW address of the

same bank as the preceding read command execution, the second read can be performed after an interval of no

less than 1 clock. Even when the first command is a burst read that is not yet finished, the data read by the

second command will be valid.

CLK

Command

ACT

Row

READ

Column A Column B

Address

BS

DQ

out A0

out B2 out B3

out B0 out B1

CL = 3

BL = 4

Bank 0

Column =B

Dout

Bank0

Active

Column =A Column =B Column =A

Read Read Dout

READ to READ Command Interval (same ROW address in same bank)

2. Same bank, different ROW address: When the ROW address changes on same bank, consecutive read

commands cannot be executed; it is necessary to separate the two read commands with a precharge command

and a bank active command.

3. Different bank: When the bank changes, the second read can be performed after an interval of no less than 1

clock, provided that the other bank is in the bank active state. Even when the first command is a burst read that

is not yet finished, the data read by the second command will be valid.

CLK

Command

READ READ

ACT

Column A

Row 1

Column B

Address

BS

Row 0

DQ

out A0

out B2 out B3

out B0 out B1

Bank3

Dout

Bank0

Dout

CL = 3

BL = 4

Bank0

Active

Bank3 Bank0 Bank3

Active Read Read

READ to READ Command Interval (different bank)

Preliminary Data Sheet E0250E10 (Ver. 1.0)

32

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Write command to Write command interval

1. Same bank, same ROW address: When another write command is executed at the same ROW address of the

same bank as the preceding write command, the second write can be performed after an interval of no less than

1 clock. In the case of burst writes, the second write command has priority.

CLK

Command

Address

WRIT

ACT

Row

WRIT

Column B

Column A

BS

DQ

in A0

in B2 in B3

in B0 in B1

Bank0

Active

Column =A Column =B

Write Write

Burst Write Mode

BL = 4

Bank 0

WRITE to WRITE Command Interval (same ROW address in same bank)

2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be

executed; it is necessary to separate the two write commands with a precharge command and a bank active

command.

3. Different bank: When the bank changes, the second write can be performed after an interval of no less than 1

clock, provided that the other bank is in the bank active state. In the case of burst write, the second write

command has priority.

CLK

Command

Address

ACT

WRIT WRIT

ACT

Column A

Column B

Row 1

Row 0

BS

DQ

in A0

in B2 in B3

in B0 in B1

Burst Write Mode

BL = 4

Bank0

Active

Bank3 Bank0 Bank3

Active Write Write

WRITE to WRITE Command Interval (different bank)

Preliminary Data Sheet E0250E10 (Ver. 1.0)

33

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Read command to Write command interval

1. Same bank, same ROW address: When the write command is executed at the same ROW address of the same

bank as the preceding read command, the write command can be performed after an interval of no less than 1

clock. However, DQM must be set High so that the output buffer becomes High-Z before data input.

CLK

Command

READ WRIT

CL=2

DQM

CL=3

DQ (input)

DQ (output)

in B0

in B3

in B1 in B2

BL = 4

Burst write

High-Z

READ to WRITE Command Interval (1)

CLK

Command

DQM

READ

WRIT

2 clock

CL=2

out

in

DQ

CL=3

READ to WRITE Command Interval (2)

2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be

executed; it is necessary to separate the two commands with a precharge command and a bank active

command.

3. Different bank: When the bank changes, the write command can be performed after an interval of no less than 1

cycle, provided that the other bank is in the bank active state. However, DQM must be set High so that the

output buffer becomes High-Z before data input.

Preliminary Data Sheet E0250E10 (Ver. 1.0)

34

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Write command to Read command interval:

1. Same bank, same ROW address: When the read command is executed at the same ROW address of the same

bank as the preceding write command, the read command can be performed after an interval of no less than 1

clock. However, in the case of a burst write, data will continue to be written until one clock before the read

command is executed.

CLK

Command

DQM

WRIT

in A0

READ

DQ (input)

DQ (output)

out B0

out B1

out B2

out B3

Burst Write Mode

CL = 2

Column = A

Write

/CAS Latency

Column = B

Read

Column = B

Dout

BL = 4

Bank 0

WRITE to READ Command Interval (1)

CLK

WRIT

in A0

READ

Command

DQM

DQ (input)

in A1

DQ (output)

out B0

out B1

out B2

out B3

Burst Write Mode

CL = 2

Column = A

Write

/CAS Latency

Column = B

Read

Column = B

Dout

BL = 4

Bank 0

WRITE to READ Command Interval (2)

2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be

executed; it is necessary to separate the two commands with a precharge command and a bank active

command.

3. Different bank: When the bank changes, the read command can be performed after an interval of no less than 1

clock, provided that the other bank is in the bank active state. However, in the case of a burst write, data will

continue to be written until one clock before the read command is executed (as in the case of the same bank and

the same address).

Preliminary Data Sheet E0250E10 (Ver. 1.0)

35

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Read with auto precharge to Read command interval

1. Different bank: When some banks are in the active state, the second read command (another bank) is executed.

Even when the first read with auto-precharge is a burst read that is not yet finished, the data read by the second

command is valid. The internal auto-precharge of one bank starts at the next clock of the second command.

CLK

Command

BS

READA

READ

DQ

out A0

out A1

out B0

out B1

bank0

Read A

bank3

Read

CL= 3

BL = 4

Note: Internal auto-precharge starts at the timing indicated by "

Read with Auto Precharge to Read Command Interval (Different bank)

2. Same bank: The consecutive read command (the same bank) is illegal.

Write with auto precharge to Write command interval

".

1. Different bank: When some banks are in the active state, the second write command (another bank) is executed.

In the case of burst writes, the second write command has priority. The internal auto-precharge of one bank

starts 2 clocks later from the second command.

CLK

Command

BS

WRITA

in A0

WRIT

in B0

DQ

in A1

in B1

in B2

".

in B3

bank0

Write A

bank3

Write

BL= 4

Note: Internal auto-precharge starts at the timing indicated by "

Write with Auto Precharge to Write Command Interval (Different bank)

2. Same bank: The consecutive write command (the same bank) is illegal.

Preliminary Data Sheet E0250E10 (Ver. 1.0)

36

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Read with auto precharge to Write command interval

1. Different bank: When some banks are in the active state, the second write command (another bank) is executed.

However, DQM must be set High so that the output buffer becomes High-Z before data input. The internal auto-

precharge of one bank starts at the next clock of the second command.

CLK

Command

BS

READA

WRIT

in B0

CL = 2

DQM

CL = 3

DQ (input)

in B1

in B2

in B3

DQ (output)

High-Z

BL = 4

bank0

ReadA

bank3

Write

Note: Internal auto-precharge starts at the timing indicated by "

".

Read with Auto Precharge to Write Command Interval (Different bank)

2. Same bank: The consecutive write command from read with auto precharge (the same bank) is illegal. It is

necessary to separate the two commands with a bank active command.

Write with auto precharge to Read command interval

1. Different bank: When some banks are in the active state, the second read command (another bank) is executed.

However, in case of a burst write, data will continue to be written until one clock before the read command is

executed. The internal auto-precharge of one bank starts at 2 clocks later from the second command.

CLK

Command

BS

WRITA

in A0

READ

DQM

DQ (input)

DQ (output)

out B0

out B1

out B2 out B3

CL = 3

BL = 4

bank0

WriteA

bank3

Read

Note: Internal auto-precharge starts at the timing indicated by "

".

Write with Auto Precharge to Read Command Interval (Different bank)

2. Same bank: The consecutive read command from write with auto precharge (the same bank) is illegal. It is

necessary to separate the two commands with a bank active command.

Preliminary Data Sheet E0250E10 (Ver. 1.0)

37

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Read command to Precharge command interval (same bank)

When the precharge command is executed for the same bank as the read command that preceded it, the minimum

interval between the two commands is one clock. However, since the output buffer then becomes High-Z after the

clocks defined by lHZP, there is a case of interruption to burst read data output will be interrupted, if the precharge

command is input during burst read. To read all data by burst read, the clocks defined by lEP must be assured as

an interval from the final data output to precharge command execution.

CLK

PRE/PALL

out A2

READ

Command

DQ

out A0

out A1

out A3

CL=2

lEP = -1 cycle

READ to PRECHARGE Command Interval (same bank): To output all data (CL = 2, BL = 4)

CLK

PRE/PALL

out A1

READ

Command

DQ

out A0

out A2

out A3

CL=3

lEP = -2 cycle

READ to PRECHARGE Command Interval (same bank): To output all data (CL = 3, BL = 4)

CLK

PRE/PALL

READ

Command

High-Z

DQ

out A0

lHZP = 2

READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 2, BL = 1, 2, 4, 8)

CLK

PRE/PALL

READ

Command

DQ

High-Z

out A0

lHZP =3

READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 3, BL = 1, 2, 4, 8)

Preliminary Data Sheet E0250E10 (Ver. 1.0)

38

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Write command to Precharge command interval (same bank)

When the precharge command is executed for the same bank as the write command that preceded it, the minimum

interval between the two commands is 1 clock. However, if the burst write operation is unfinished, the input data

must be masked by means of DQM for assurance of the clock defined by tDPL.

CLK

PRE/PALL

Command

DQM

WRIT

DQ

tDPL

WRIT

CLK

Command

DQM

PRE/PALL

DQ

in A0

in A1

tDPL

WRITE to PRECHARGE Command Interval (same bank) (BL = 4 (To stop write operation))

CLK

PRE/PALL

Command

DQM

WRIT

in A0

DQ

in A1

in A2

in A3

tDPL

WRITE to PRECHARGE Command Interval (same bank) (BL = 4 (To write all data))

Preliminary Data Sheet E0250E10 (Ver. 1.0)

39

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Bank active command interval

1. Same bank: The interval between the two bank active commands must be no less than tRC.

2. In the case of different bank active commands: The interval between the two bank active commands must be no

less than tRRD.

CLK

Command

Address

BS

ACT

ROW

tRC

Bank 0

Active

Bank 0

Active

Bank Active to Bank Active for Same Bank

CLK

Command

Address

ACT

ROW:0

ROW:1

BS

tRRD

Bank 0

Active

Bank 3

Active

Bank Active to Bank Active for Different Bank

Mode register set to Bank active command interval

The interval between setting the mode register and executing a bank active command must be no less than lMRD.

CLK

Command

Address

MRS

ACT

OPCODE

BS & ROW

IMRD

Mode

Register Set

Bank

Active

Mode register set to Bank active command interval

Preliminary Data Sheet E0250E10 (Ver. 1.0)

40

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

DQM Control

The DQM mask the DQ data. The UDQM and LDQM mask the upper and lower bytes of the DQ data, respectively.

The timing of UDQM/LDQM is different during reading and writing.

Reading

When data is read, the output buffer can be controlled by DQM. By setting DQM to Low, the output buffer becomes

Low-Z, enabling data output. By setting DQM to High, the output buffer becomes High-Z, and the corresponding

data is not output. However, internal reading operations continue. The latency of DQM during reading is 2 clocks.

Writing

Input data can be masked by DQM. By setting DQM to Low, data can be written. In addition, when DQM is set to

High, the corresponding data is not written, and the previous data is held. The latency of DQM during writing is 0

clock.

CLK

DQM

High-Z

DQ

out 0

out 1

out 3

lDOD = 2 Latency

Reading

CLK

DQM

DQ

in 3

in 0

in 1

lDID = 0 Latency

Writing

Preliminary Data Sheet E0250E10 (Ver. 1.0)

41

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Refresh

Auto-refresh

All the banks must be precharged before executing an auto-refresh command. Since the auto-refresh command

updates the internal counter every time it is executed and determines the banks and the ROW addresses to be

refreshed, external address specification is not required. The refresh cycles are required to refresh all the ROW

addresses within tREF (max.). The output buffer becomes High-Z after auto-refresh start. In addition, since a

precharge has been completed by an internal operation after the auto-refresh, an additional precharge operation by

the precharge command is not required.

Self-refresh

After executing a self-refresh command, the self-refresh operation continues while CKE is held Low. During self-

refresh operation, all ROW addresses are refreshed by the internal refresh timer. A self-refresh is terminated by a

self-refresh exit command. Before and after self-refresh mode, execute auto-refresh to all refresh addresses in or

within tREF (max.) period on the condition 1 and 2 below.

1. Enter self-refresh mode within time as below* after either burst refresh or distributed refresh at equal interval to

all refresh addresses are completed.

2. Start burst refresh or distributed refresh at equal interval to all refresh addresses within time as below*after

exiting from self-refresh mode.

Note: tREF (max.) / refresh cycles.

Others

Power-down mode

The SDRAM enters power-down mode when CKE goes Low in the IDLE state. In power down mode, power

consumption is suppressed by deactivating the input initial circuit. Power down mode continues while CKE is held

Low. In addition, by setting CKE to High, the SDRAM exits from the power down mode, and command input is

enabled from the next clock. In this mode, internal refresh is not performed.

Clock suspend mode

By driving CKE to Low during a bank active or read/write operation, the SDRAM enters clock suspend mode. During

clock suspend mode, external input signals are ignored and the internal state is maintained. When CKE is driven

High, the SDRAM terminates clock suspend mode, and command input is enabled from the next clock. For details,

refer to the "CKE Truth Table".

Preliminary Data Sheet E0250E10 (Ver. 1.0)

42

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Timing Waveforms

Read Cycle

tCK

tCH tCL

CLK

tRC

VIH

CKE

t

tRAS

RP

tRCD

tHI

tSI

tSI tHI

/CS

tSI tHI

/RAS

tSI tHI

/CAS

tSI tHI

/WE

BS

tSI tHI

A10

Address

DQM

tSI tHI

tSI

tHI

DQ (input)

t

HZ

AC

DQ (output)

t

AC

t

OH

t

OH

t

OH

/CAS latency = 2

Burst length = 4

Bank 0 access

= VIH or VIL

Bank 0

Read

tLZ

Bank 0

Active

Bank 0

Precharge

Preliminary Data Sheet E0250E10 (Ver. 1.0)

43

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Write Cycle

tCK

tCH tCL

CLK

tRC

VIH

CKE

tRP

tRAS

tRCD

tSI tHI

/CS

tSI tHI

/RAS

tSI tHI

/CAS

/WE

tSI tHI

BS

tSI tHI

A10

tSI tHI

Address

DQM

tSI

tHI

tSI tHI tSI tHI tSI tHI tSI tHI

DQ (input)

tDPL

DQ (output)

Bank 0

Precharge

Bank 0

Write

CL = 2

BL = 4

Bank 0

Active

Bank 0 access

= VIH or VIL

Mode Register Set Cycle

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

CLK

VIL

CKE

/CS

/RAS

/CAS

/WE

BS

code

C: b’

Address

DQM

valid

C: b

R: b

b

b+3

b’ b’+1 b’+2 b’+3

DQ (output)

DQ (input)

High-Z

lMRD

lRP

lRCD

Output mask

l

RCD = 3

Precharge

If needed

Mode

register

Set

Bank 3

Active

Bank 3

Read

/CAS latency = 3

Burst length = 4

= VIH or VIL

Preliminary Data Sheet E0250E10 (Ver. 1.0)

44

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Read Cycle/Write Cycle

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20

CLK

CKE

VIH

Read cycle

/RAS-/CAS delay = 3

/CAS latency = 3

Burst length = 4

/CS

/RAS

=

VIH or VIL

/CAS

/WE

BS

Address

DQM

R:a

C:a

R:b

C:b

C:b'

C:b"

DQ (output)

DQ (input)

a

a+1 a+2 a+3

b

b+1 b+2 b+3 b' b'+1 b" b"+1 b"+2 b"+3

High-Z

Bank 0

Active

Bank 0

Read

Bank 3

Active

Bank 3 Bank 0

Bank 3

Read

Bank 3

Read

Bank 3

Precharge

Read

Precharge

VIH

CKE

Write cycle

/RAS-/CAS delay = 3

/CAS latency = 3

Burst length = 4

= VIH or VIL

/CS

/RAS

/CAS

/WE

BS

Address

DQM

R:a

C:a

a

R:b

C:b

C:b'

C:b"

High-Z

DQ (output)

DQ (input)

a+1 a+2 a+3

b

b+1 b+2 b+3 b'

b'+1 b" b"+1b"+2 b"+3

Bank 0

Active

Bank 0

Write

Bank 3

Active

Bank 3

Write

Bank 0

Precharge

Bank 3

Write

Bank 3

Write

Bank 3

Precharge

Read/Single Write Cycle

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20

CLK

V

IH

CKE

/CS

/RAS

/CAS

/WE

BS

R:a

C:a

R:b

C:a' C:a

a

Address

DQM

DQ (input)

DQ (output)

a

a+1 a+2 a+3

a

a+1 a+2 a+3

Bank 0

Active

Bank 0

Read

Bank 3

Active

Bank 0 Bank 0

Write Read

Bank 0

Precharge

Bank 3

Precharge

V

IH

CKE

/CS

/RAS

/CAS

/WE

BS

R:a

C:a

R:b

C:a

C:b C:c

Address

DQM

a

b

c

DQ (input)

DQ (output)

a

a+1

a+3

Bank 0

Active

Bank 0

Read

Bank 0

Write

Bank 0 Bank 0

Write Write

Bank 0

Precharge

Bank 3

Active

Read/Single write

/RAS-/CAS delay = 3

/CAS latency = 3

Burst length = 4

=

VIH or VIL

Preliminary Data Sheet E0250E10 (Ver. 1.0)

45

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Read/Burst Write Cycle

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20

CLK

CKE

/CS

/RAS

/CAS

/WE

BS

Address

DQM

R:a

C:a

R:b

C:a'

a

a+1 a+2 a+3

DQ (input)

DQ (output)

a

a+1 a+2 a+3

Bank 0

Active

Bank 0

Read

Bank 3

Active

Clock

suspend

Bank 0

Precharge

Bank 3

Precharge

Bank 0

Write

VIH

CKE

/CS

/RAS

/CAS

/WE

BS

R:a

C:a

R:b

C:a

a

Address

DQM

DQ (input)

DQ (output)

a+1 a+2 a+3

a

a+1

a+3

Bank 0

Active

Bank 0

Read

Bank 0

Write

Bank 0

Precharge

Bank 3

Active

Read/Burst write

/RAS-/CAS delay = 3

/CAS latency = 3

Burst length = 4

=

VIH or VIL

Auto Refresh Cycle

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

CLK

CKE

/CS

VIH

/RAS

/CAS

/WE

BS

Address

C:a

A10=1

R:a

DQM

DQ (input)

a

a+1

High-Z

DQ (output)

t

RC

RP

RC

Refresh cycle and

Read cycle

Active

Bank 0

Read

Bank 0

Auto Refresh

Precharge

If needed

Auto Refresh

/RAS-/CAS delay = 2

/CAS latency = 2

Burst length = 4

= VIH or VIL

Preliminary Data Sheet E0250E10 (Ver. 1.0)

46

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Self Refresh Cycle

CLK

CKE

/CS

lSREX

CKE Low

/RAS

/CAS

/WE

BS

Address

DQM

A10=1

DQ (input)

High-Z

DQ (output)

t

RC

t

RC

RP

Self refresh cycle

/RAS-/CAS delay = 3

CL = 3

Auto

refresh

Self refresh entry

command

Precharge command

If needed

ignore command

or No operation

enable

Self refresh entry

command

clock

enable

BL = 4

=

VIH or VIL

Clock Suspend Mode

tSI

10 11 12 13 14 15 16 17 18 19 20

tHI

8

0

1

2

3

4

5

6

7

9

CLK

CKE

Read cycle

/RAS-/CAS delay = 2

/CAS latency = 2

Burst length = 4

= VIH or VIL

/CS

/RAS

/CAS

/WE

BS

Address

R:a

C:a

R:b

C:b

DQM

DQ (output)

DQ (input)

a

a+1 a+2

a+3

b

b+1 b+2 b+3

High-Z

Bank0 Active clock

Active suspend start

Active clock Bank0

suspend end Read

Bank3 Read suspend Read suspend

Bank0

Earliest Bank3

Precharge

Bank3

Active

start

end Read Precharge

CKE

Write cycle

/RAS-/CAS delay = 2

/CAS latency = 2

Burst length = 4

= VIH or VIL

/CS

/RAS

/CAS

/WE

BS

R:b

a+1

Address

DQM

R:a

C:a

a

C:b

High-Z

DQ (output)

DQ (input)

a+2

a+3

b

b+1 b+2 b+3

Bank0

Active clock Bank0 Bank3 Write suspend Write suspend Bank3

Earliest Bank3

Precharge

Bank0 Active clock

Active suspend start

Precharge

end Write

supend end Write Active

start

Preliminary Data Sheet E0250E10 (Ver. 1.0)

47

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Power Down Mode

CLK

CKE

/CS

CKE Low

/RAS

/CAS

/WE

BS

Address

DQM

A10=1

R: a

DQ (input)

High-Z

DQ (output)

tRP

Power down cycle

Power down entry

Power down

mode exit

Precharge command

If needed

/RAS-/CAS delay = 3

/CAS latency = 3

Burst length = 4

= VIH or VIL

Active Bank 0

Initialization Sequence

53

0

1

2

3

4

5

6

7

8

9

10

48

49

50

51

52

54

55

CLK

CKE

/CS

VIH

/RAS

/CAS

/WE

code

valid

Address

Valid

V

IH

DQM

DQ

High-Z

t

RC

tRP

RC

l

MRD

Bank active

If needed

All banks

Precharge

Mode register

Set

Auto Refresh

Preliminary Data Sheet E0250E10 (Ver. 1.0)

48

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Package Drawing

Unit: mm

22.22 ± 0.10

A

54

28

PIN#1 ID

1

27

B

0.80

0.25 to 0.40

M S

A B

0.16

0.80

Nom

0.91 max.

0.25

0 to 8°

S

0.10

S

0.60 ± 0.15

Note: Dimension "A" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or

gate burrs shall not exceed 0.20mm per side.

ECA-TS2-0016-01

Preliminary Data Sheet E0250E10 (Ver. 1.0)

49

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

Recommended Soldering Conditions

Please consult with our sales offices for soldering conditions of the EDS51XXABTA.

Type of Surface Mount Device

EDS51XXABTA: 54-pin Plastic TSOP (II)

Preliminary Data Sheet E0250E10 (Ver. 1.0)

50

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

NOTES FOR CMOS DEVICES

1

PRECAUTION AGAINST ESD FOR MOS DEVICES

Exposing the MOS devices to a strong electric field can cause destruction of the gate

oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop

generation of static electricity as much as possible, and quickly dissipate it, when once

it has occurred. Environmental control must be adequate. When it is dry, humidifier

should be used. It is recommended to avoid using insulators that easily build static

electricity. MOS devices must be stored and transported in an anti-static container,

static shielding bag or conductive material. All test and measurement tools including

work bench and floor should be grounded. The operator should be grounded using

wrist strap. MOS devices must not be touched with bare hands. Similar precautions

need to be taken for PW boards with semiconductor MOS devices on it.

2

HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES

No connection for CMOS devices input pins can be a cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input level may be

generated due to noise, etc., hence causing malfunction. CMOS devices behave

differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected

to V^DDor GND with a resistor, if it is considered to have a possibility of being an output

pin. The unused pins must be handled in accordance with the related specifications.

3

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Power-on does not necessarily define initial status of MOS devices. Production process

of MOS does not define the initial operation status of the device. Immediately after the

power source is turned ON, the MOS devices with reset function have not yet been

initialized. Hence, power-on does not guarantee output pin levels, I/O settings or

contents of registers. MOS devices are not initialized until the reset signal is received.

Reset operation must be executed immediately after power-on for MOS devices having

reset function.

CME0107

Preliminary Data Sheet E0250E10 (Ver. 1.0)

51

EDS5104ABTA, EDS5108ABTA, EDS5116ABTA

The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.

No part of this document may be copied or reproduced in any form or by any means without the prior

written consent of Elpida Memory, Inc.

Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights

(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or

third parties by or arising from the use of the products or information listed in this document. No license,

express, implied or otherwise, is granted under any patents, copyrights or other intellectual property

rights of Elpida Memory, Inc. or others.

Descriptions of circuits, software and other related information in this document are provided for

illustrative purposes in semiconductor product operation and application examples. The incorporation of

these circuits, software and information in the design of the customer's equipment shall be done under

the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses

incurred by customers or third parties arising from the use of these circuits, software and information.

[Product applications]

Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.

However, users are instructed to contact Elpida Memory's sales office before using the product in

aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,

medical equipment for life support, or other such application in which especially high quality and

reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk

of bodily injury.

[Product usage]

Design your application so that the product is used within the ranges and conditions guaranteed by

Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation

characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no

responsibility for failure or damage when the product is used beyond the guaranteed ranges and

conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure

rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so

that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other

consequential damage due to the operation of the Elpida Memory, Inc. product.

[Usage environment]

This product is not designed to be resistant to electromagnetic waves or radiation. This product must be

used in a non-condensing environment.

If you export the products or technology described in this document that are controlled by the Foreign

Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance

with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by

U.S. export control regulations, or another country's export control laws or regulations, you must follow

the necessary procedures in accordance with such laws or regulations.

If these products/technology are sold, leased, or transferred to a third party, or a third party is granted

license to use these products, that third party must be made aware that they are responsible for

compliance with the relevant laws and regulations.

M01E0107

Preliminary Data Sheet E0250E10 (Ver. 1.0)

52


型号：	EDS5116ABTA
厂家：	ELPIDA MEMORY
描述：	512M bits SDRAM 512M位的SDRAM 动态存储器
文件：	总52页 (文件大小：558K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EDS5116ABTA [ELPIDA]

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