EDW1032BBBG-70-F_技术文档

DATA SHEET

1G bits GDDR5 SGRAM

EDW1032BBBG (32M words x 32 bits)

Specifications

Features

• Density: 1G bits

• Organization

• x32/x16 mode configuration set at power-up with

EDC pin

• Single ended interface for data, address and command

• Quarter data-rate differential clock inputs CK, /CK for

address and commands

• Two half data-rate differential clock inputs WCK, /WCK,

each associated with two data bytes (DQ, /DBI, EDC)

• Double Data Rate (DDR) data (WCK)

• Single Data Rate (SDR) command (CK)

• Double Data Rate (DDR) addressing (CK)

• Write data mask function via address bus

(single/double byte mask)

• Data Bus Inversion (DBI) and Address Bus Inversion

(ABI)

— 2Mbit x 32 I/O x 16 banks

— 4Mbit x 16 I/O x 16 banks

• Package

— 170-ball FBGA

— Lead-free (RoHS compliant) and Halogen-free

• Power supply:

— VDD: 1.5V ±3% and 1.35V ± 3%

— VDDQ: 1.5V ±3% and 1.35V ±3%

• Data rate: 7.0Gbps/6.0Gbps/5.0Gbps/4.0Gbps (max.)

• 16 internal banks

• Four bank groups for tCCDL = 3tCK

• 8n prefetch architecture: 256 bit per array Read or

Write access; 128 bit for x16

• Burst length (BL): 8 only

• Programmable CAS latency: 6 to 20

• Programmable Write latency: 3 to 7

• Programmable CRC READ latency: 0 to 3

• Programmable CRC WRITE latency: 8 to 14

• Programmable EDC hold pattern for CDR

• Input/output PLL on/off mode

• Address training: address input monitoring via DQ pins

• WCK2CK clock training: phase information via EDC

pins

• Data read and write training via Read FIFO (FIFO

depth = 6)

• Read FIFO pattern preload by LDFF command

• Direct write data load to Read FIFO by WRTR

command

• Precharge: auto precharge option for each burst

access

• Consecutive read of Read FIFO by RDTR command

• Refresh: auto-refresh, self-refresh

• Refresh cycles: 8192 cycles/32ms

• Interface: Pseudo open drain (POD-15)

• On-die termination (ODT): nom. values of 60Ω or 120Ω

• Pseudo open drain (POD-15) compatible outputs

— 40Ω pulldown

— 60Ω pullup

• ODT and output driver strength auto-calibration with

external resistor ZQ pin (120Ω)

• Programmable termination and driver strength offsets

• Read/Write data transmission integrity secured by

cyclic redundancy check (CRC–8)

• Read/Write EDC on/off mode

• DQ Preamble for Read on/off mode

• Low Power modes

• RDQS mode on EDC pin

• On-chip temperature sensor with read-out

• Automatic temperature sensor controlled self-refresh

rate

• Digital tRAS lockout

• Vendor ID, FIFO depth and Density info fields for

identification

• Selectable external or internal VREF for data inputs;

programmable offsets for internal VREF

• Mirror function with MF pin

• Boundary Scan function with SEN pin

• Separate external VREF for address / command inputs

• Operating case temperature range

— TC = 0°C to +95°C

Document No. E1771E11 (Ver. 1.1)

Date Published September 2011 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2011

EDW1032BBBG

Ordering Information

Organization

(words x bits)

Part number

Max. Data Rate (Gbps/pin)

Package

EDW1032BBBG-40-F

EDW1032BBBG-50-F

EDW1032BBBG-60-F

EDW1032BBBG-70-F

32M x 32

4.0

5.0

6.0

7.0

170-ball FBGA

Part Number

E D W 10 32 B B BG - 60 - F

Elpida Memory

Type

Environment Code

F: Lead Free (RoHS compliant)

and Halogen Free

D: Packaged Device

Product Family

Speed

W: GDDR5 SGRAM

40: 4.0Gbps

50: 5.0Gbps

60: 6.0Gbps

70: 7.0Gbps

Density/Bank

10: 1Gb/16-bank

Package

BG: FBGA

Organization

32: x32

Revision

Power Supply, Interface

B: VDD = 1.5V

Data Sheet E1771E11 (Ver. 1.1)

2

EDW1032BBBG

Pin Configuration

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Data Sheet E1771E11 (Ver. 1.1)

3

EDW1032BBBG

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Signal

Function

Signal

ZQ

Function

CK, /CK

Clock

Impedance Reference

WCK01, /WCK01,

WCK23, /WCK23

Data Clocks

/RESET

Reset

/CKE

Clock Enable

MF

Mirror Function

/CS

Chip Select

SEN

Scan Enable

/RAS, /CAS, /WE

BA0 - BA3

A0 - A11

Command inputs

Bank Address inputs

Address inputs

Data Input/Output

Data bus inversion

VREFC

VREFD

VDDQ

VSSQ

VDD

Reference voltage for command and address

Reference voltage for DQ and /DBI

I/O power

DQ0 - DQ31

/DBI0 - /DBI3

EDC0 - EDC3

/ABI

I/O ground

Power supply

Error Detection Code

Address bus inversion

VSS

Ground

NC

Not connected

Note: 1. /xxx indicates active low signal.

Data Sheet E1771E11 (Ver. 1.1)

4

EDW1032BBBG

1. Configuration

The Elpida GDDR5 SGRAM is a high speed dynamic random-access memory designed for applications requiring

high bandwidth. It contains 1,073,741,824 bits and is internally configured as a 16-bank DRAM.

The GDDR5 SGRAM uses a 8n prefetch architecture and DDR interface to achieve high-speed operation. The

device can be configured to operate in x32 mode or x16 (clamshell) mode. The mode is detected during device

initialization. The GDDR5 interface transfers two 32 bit wide data words per WCK clock cycle to/from the I/O pins.

Corresponding to the 8n prefetch a single write or read access consists of a 256 bit wide, two CK clock cycle data

transfer at the internal memory core and eight corresponding 32 bit wide one-half WCK clock cycle data transfers

at the I/O pins.

The GDDR5 SGRAM operates from a differential clock CK and /CK. Commands are registered at every rising edge

of CK. Addresses are registered at every rising edge of CK and every rising edge of /CK.

GDDR5 replaces the pulsed strobes (WDQS & RDQS) used in previous DRAMs such as GDDR4 with a free running

differential forwarded clock (WCK, /WCK) with both input and output data registered and driven respectively at both

edges of the forwarded WCK.

Read and write accesses to the GDDR5 SGRAM are burst oriented; an access starts at a selected location and

continues for a total of eight data words. Accesses begin with the registration of an ACTIVE command, which is then

followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command and

the next rising /CK edge are used to select the bank and the row to be accessed. The address bits registered

coincident with the READ or WRITE command and the next rising /CK edge are used to select the bank and the

column location for the burst access.

Data Sheet E1771E11 (Ver. 1.1)

5

EDW1032BBBG

1.1 Signal Description

Table 1: Signal Description

Signal

Type

Detailed Function

Clock: CK and /CK are differential clock inputs. Command inputs are latched on the rising

edge of CK. Address inputs are latched on the rising edge of CK and the rising edge of /CK.

All latencies are referenced to CK. CK and /CK are externally terminated.

CK, /CK

Input

Data Clocks: WCK and /WCK are differential clocks used for WRITE data capture and READ

data output. WCK01, /WCK01 is associated with DQ0-DQ15, /DBI0, /DBI1, EDC0 and EDC1.

WCK23, /WCK23 is associated with DQ16-DQ31, /DBI2, /DBI3, EDC2 and EDC3. WCK clocks

operate at nominally twice the CK clock frequency.

WCK01, /WCK01,

WCK23, /WCK23

Input

Clock Enable: /CKE low activates and /CKE high deactivates internal clock, device input

buffers and output drivers. Taking /CKE high provides Precharge Power-Down and Self-

Refresh operations (all banks idle), or Active Power-Down (row active in any bank). /CKE is

synchronous for Power-Down entry and exit and for Self-Refresh entry. /CKE must be

maintained low throughout READ and WRITE accesses.

/CKE

Input buffers excluding CK, /CK, /CKE, WCK01, /WCK01, WCK23, /WCK23 are disabled

during Power-Down. Input buffers excluding /CKE are disabled during Self-Refresh.

The value of /CKE latched at power-up with /RESET going high determines the termination

value of the address and command inputs.

Chip Select: /CS low enables, and /CS high disables the command decoder. All commands

are masked when /CS is registered high, but internal command execution continues. /CS

provides for individual device selection on memory channels with multiple memory devices.

/CS is considered part of the command code.

/CS

/RAS, /CAS, /WE Input

Command inputs: /RAS, /CAS and /WE (along with /CS) define the command to be entered.

Bank Address inputs: BA0-BA3 define to which bank an ACTIVE, READ, WRITE or

PRECHARGE command is being applied. BA0-BA3 also determine which Mode Register is

accessed with a MODE REGISTER SET command. BA0-BA3 are sampled with the rising edge

of CK.

BA0 - BA3

Input

Address inputs: A0-A11 provide the row address for ACTIVE commands. A0-A5(A6) provide

the column address and A8 defines the auto precharge function for READ and WRITE

commands, to select one location out of the memory array in the respective bank. A8 sampled

during a PRECHARGE command determines whether the PRECHARGE applies to one bank

(A8 low, bank selected by BA0-BA3) or all banks (A8 high). The address inputs also provide

the op-code during an MODE REGISTER SET command, and the data bits during LDFF

commands. A8-A11 are sampled with the rising edge of CK and A0-A7 are sampled with the

rising edge of /CK.

A0 - A11

DQ0 - DQ31

/DBI0 - /DBI3

I/O

Data Input/Output: 32 bit data bus

Data bus inversion: /DBI0 is associated with DQ0-DQ7, /DBI1 with DQ8-DQ15, /DBI2 with

DQ16-DQ23, and /DBI3 with DQ24-DQ31.

Error Detection Code: The calculated CRC data is transmitted on these pins. In addition

these pins drive a hold pattern when idle and can be used as an RDQS function. EDC0 is

associated with DQ0-DQ7, EDC1 with DQ8-DQ15, EDC2 with DQ16-DQ23, and EDC3 with

DQ24-DQ31.

EDC0 - EDC3

Output

/ABI

ZQ

Input

-

Address bus inversion

Impedance Reference: external reference pin for auto-calibration

Reset: VDDQ CMOS input. /RESET low asynchronously initiates a full chip reset. With

/RESET low all ODTs are disabled.

/RESET

Input

MF

Input

Mirror Function: VDDQ CMOS input. Must be tied to Power or Ground.

Scan Enable: VDDQ CMOS input. Must be tied to Ground when not in use.

Reference voltage for command and address inputs.

Reference voltage for DQ and /DBI inputs.

Isolated power for the input and output buffers.

Isolated ground for the input and output buffers.

Power supply

SEN

Input

VREFC

VREFD

VDDQ

VSSQ

VDD

Supply

-

VSS

Ground

NC

Not connected

Data Sheet E1771E11 (Ver. 1.1)

6

EDW1032BBBG

1.2 Mirror Function Mode

The GDDR5 SGRAM provides a mirror function (MF) pin to change the physical location of the command, address,

data and WCK pins assisting in routing devices back to back. The MF ball should be tied directly to VSSQ or VDDQ

depending on the control line orientation desired.

The pins affected by this Mirror Function mode are listed in Table 2.

Table 2: Ball Assignment with Mirror Function

Signal

M=1

Signal

M=1

Signal

M=1

Signal

MF=1

Ball

A2

B2

C2

D2

E2

F2

MF=0

DQ1

Ball

A4

B4

D4

E4

F4

MF=0

DQ0

DQ2

Ball

K5

MF=0

Ball

G12

L12

A13

B13

C13

D13

E13

F13

M13

N13

P13

R13

T13

U13

MF=0

/CS

DQ25

DQ27

EDC3

/DBI3

DQ29

DQ31

DQ7

DQ24

DQ26

A11 A6 A9 A1

/WCK23 /WCK01

BA3 A3 BA1 A5

BA1 A5 BA3 A3

/WE

DQ3

P5

/WE

/CS

EDC0

/DBI0

DQ5

WCK01 WCK23

H10

K10

A11

B11

E11

F11

H11

K11

M11

N11

T11

U11

DQ9

DQ17

DQ19

EDC2

/DBI2

DQ21

DQ23

DQ15

DQ13

/DBI1

EDC1

DQ11

DQ9

DQ4

DQ6

DQ28

DQ30

DQ11

EDC1

/DBI1

DQ13

DQ15

DQ23

DQ21

/DBI2

EDC2

DQ19

DQ17

DQ8

DQ16

DQ18

DQ20

DQ22

DQ7

H4

K4

M4

N4

P4

T4

A10 A0 A8 A7

DQ10

DQ12

DQ14

M2

N2

P2

R2

T2

DQ31

DQ29

/DBI3

EDC3

DQ27

DQ25

/RAS

/CAS

A8 A7

DQ30

DQ28

A10 A0

DQ6

DQ5

/DBI0

EDC0

DQ3

DQ4

BA0 A2 BA2 A4

BA2 A4 BA0 A2

WCK23 WCK01

DQ26

DQ24

DQ2

DQ0

DQ22

DQ20

DQ18

DQ16

DQ14

DQ12

DQ10

DQ8

U2

G3

L3

DQ1

U4

D5

H5

/CAS

/RAS

/WCK01 /WCK23

A9 A1 A11 A6

Functions within the GDDR5 SGRAM that refer to external signals are transparent with respect to Mirror Function

mode, meaning that the signal names shown in the respective functional description apply both to mirrored (MF=1)

and non-mirrored (MF=0) modes. The referenced package pin is determined by the Mirror Function mode the

devices is configured to.

1.3 Clamshell Mode Detection

The GDDR5 SGRAM can operate in a x32 mode or a x16 mode to allow a clamshell configuration with a point to

point connection on the high speed data signals. The disabled pins in x16 mode will be in Hi-Z state, non-terminating.

The x16 mode is detected at power-up on the pin at location C-13 which is EDC1 when configured to MF=0 and

EDC2 when configured to MF=1. For x16 mode this pin is tied to VSSQ; the pin is part of the two bytes that are

disabled in this mode and therefore not needed for EDC functionality. For x32 mode this pin is active and always

terminated to VDDQ in the system or by the controller. The configuration is set with /RESET going high. Once the

configuration has been set, it cannot be changed during normal operation. Usually the configuration is fixed in the

system.

Table 3: Clamshell Mode and Mirror Function

Mode

MF

EDC1 (MF=0) or EDC2 (MF=1)

x16 non-mirrored

x32 non-mirrored

x16 mirrored

x32 mirrored

VSSQ

VDDQ

VSSQ

VDDQ (terminated by the system or controller)

VSSQ

VDDQ (terminated by the system or controller)

Data Sheet E1771E11 (Ver. 1.1)

7

EDW1032BBBG

1.4 Clocking

The GDDR5 SGRAM operates from a differential clock CK and /CK. Commands are registered at every rising edge

of CK. Addresses are registered at every rising edge of CK and every rising edge of /CK.

GDDR5 uses a double data rate data interface and an 8n-prefetch architecture. The data interface uses two

differential forwarded clocks (WCK, /WCK). DDR means that the data is registered at every rising edge of WCK and

rising edge of /WCK. WCK and /WCK are continuously running and operate at twice the frequency of the

command/address clock (CK, /CK).

ꢝꢀꢁ

ꢀꢁ

ꢀꢂꢃꢃꢄꢅꢆ

ꢇꢆꢆꢈꢉꢊꢊ

ꢋꢀꢁ

ꢝꢋꢀꢁ

ꢌꢄꢍꢄ

ꢎꢂꢍꢉꢏꢐꢍꢑꢉꢐꢒꢓꢔꢕꢈꢉꢐꢊꢑꢂꢖꢊꢐꢍꢑꢉꢐꢈꢉꢗꢄꢍꢓꢂꢅꢊꢑꢓꢘꢐꢙꢉꢍꢖꢉꢉꢅꢐꢍꢑꢉꢐꢆꢄꢍꢄꢐꢈꢄꢍꢉꢐꢂꢒꢐꢍꢑꢉꢐꢙꢕꢊꢉꢊꢐꢄꢅꢆꢐꢍꢑꢉꢐꢚꢗꢂꢚꢛꢊꢐꢄꢅꢆꢐꢓꢊꢐꢅꢂꢍꢐꢄꢐꢍꢓꢃꢓꢅꢔꢐꢆꢓꢄꢔꢈꢄꢃꢜ

Figure 1: GDDR5 Clocking and Interface Relationship

1.5 Addressing

The GDDR5 SGRAM uses a double data rate address scheme to reduce pins required on the GDDR5 SGRAM as

shown in Table 4. The addresses should be provided to the GDDR5 SGRAM in two parts; the first half is latched on

the rising edge of CK along with the command pins such as /RAS, /CAS and /WE; the second half is latched on the

rising edge of /CK.

The use of DDR addressing allows all address values to be latched in at the same rate as the SDR commands. All

addresses related to command access have been positioned for latching on the initial rising edge for faster

decoding.

Table 4: Address Pairs

Clock Edge

Rising CK

Rising /CK

Address Inputs

BA3

A3

BA2

A4

BA1

A5

BA0

A2

A11

A6

A10

A0

A9

A1

A8

A7

Addressing schemes for x32 mode and x16 mode differ only in the number of valid column addresses, as shown in

Table 5.

Table 5: Addressing Scheme

32M x 32

A0-A11

A0-A5

BA0-BA3

A8

64M x 16

A0-A11

A0-A6

BA0-BA3

A8

Row Address

Column address

Bank address

Autoprecharge

Page size

2 KB

Refresh

8k/32ms

3.9 µs

8k/32ms

3.9 µs

Refresh period

Data Sheet E1771E11 (Ver. 1.1)

8

EDW1032BBBG

1.6 Commands

Table 6: Command Truth Table

/CKE /CKE

BA3-

A6-A7, A0-A5

Operation

Code

n-1

n

/CS /RAS /CAS /WE BA0

A11 A10 A8

A9

(A6) Note

DESELECT

DESEL

L

X

H

X

2,8

NO OPERATION

(NOP)

NOP

MRS

L

X

L

H

X

2,8

MODE REGISTER

SET

L

MRA OPCODE

2,3

ACTIVATE

READ

ACT

RD

L

H

L

H

BA

RA

L

2,4

H

L

X

CA

2,5,9

READ with

Autoprecharge

RDA

L

H

L

H

BA

L

H

2,5

LOAD FIFO

LDFF

L

H

L

H

L

BST

X

H

L

H

L

DATA

2,7

2

READ TRAINING

RDTR

X

WRITE without Mask WR

WRITE without Mask

BA

CA

2,5

WRA

L

H

L

BA

L

H

L

X

CA

2,5

with Autoprecharge

WRITE with Single

Byte Mask

WSM

H

WRITE with

Autoprecharge, Single WSMA

Byte Mask

L

H

L

BA

L

H

L

H

L

X

CA

2,5

WRITE with Double

WDM

H

Byte Mask

WRITE with

Autoprecharge,

WDMA

L

H

Double Byte Mask

WRITE TRAINING

PRECHARGE

PRECHARGE ALL

REFRESH

WRTR

PRE

L

H

L

H

L

H

L

X

H

X

H

X

L

X

2

6

H

L

BA

X

L

PREALL L

L

H

X

REF

L

H

X

H

X

H

X

H

X

H

X

H

X

H

POWER-DOWN-

ENTRY

PDE

L

H

X

POWER-DOWN-

EXIT

PDX

SRE

SRX

H

L

H

L

X

SELF-REFRESH-

ENTRY

L

H

6

H

L

X

H

X

H

X

H

SELF-REFRESH-

EXIT

H

Notes: 1. H = logic high level; L = logic low level; X = Don’t Care. Signal may be H or L, but not floating.

2. Addresses shown are logical addresses; physical addresses are inverted when address bus inversion (ABI) is

activated and /ABI=L.

3. BA0-BA3 provide the Mode Register address (MRA), A0-A11 the opcode to be loaded.

4. BA0-BA3 provide the bank address (BA), A0-A11 provide the row address (RA).

5. BA0-BA3 provide the bank address, A0-A5 (A6) provide the column address (CA); no sub-word addressing within a

burst of 8.

6. This command is REFRESH when /CKE(n) = L, and SELF-REFRESH ENTRY when /CKE(n) is H.

7. BA0-BA3 and CA are used to select burst location (BST) and data, respectively.

8. DESELECT and NO OPERATION are functionally interchangeable.

9. In address training mode READ is decoded from the command pins only with /RAS = H, /CAS = L, /WE= H.

Data Sheet E1771E11 (Ver. 1.1)

9

EDW1032BBBG

2. Electrical Characteristics

Table 7: Absolute Maximum Ratings

Parameter

Symbol

VDD

Min.

-0.5

-55

—

Max.

2.0

Unit

V

Voltage on VDD supply relative to VSS

Voltage on VDDQ supply relative to VSSQ

Voltage on VREF and inputs relative to VSS

Voltage on I/O pins relative to VSS

Storage Temperature

VDDQ

VIN

2.0

V

2.0

V

VOUT

TSTG

TJ

2.0

V

+150

+125

50

°C

mA

Junction Temperature

Short Circuit output current

IOUT

—

Caution: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent

damage of the device. This is a stress rating only, and functional operation of the device at these

or any other conditions above those indicated in the operational sections of these specification

is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

Data Sheet E1771E11 (Ver. 1.1)

10

EDW1032BBBG

2.1 Operating Conditions

Table 8: DC Operating Conditions

POD15

typ.

POD135

typ.

Parameter

Symbol

VDD

min.

1.455

max.

1.545

min.

max. Unit Note

Device supply voltage

I/O Supply voltage

1.5

1.3095

1.35

1.3905

V

2

VDDQ

1.5

0.69 *

VDDQ

0.71 *

VDDQ

0.69 *

VDDQ

0.71 *

VDDQ

Reference voltage for DQ and /DBI pins

VREFD

—

V

3,4

3,4,5

6

0.49 *

VDDQ

0.51 *

VDDQ

0.49 *

VDDQ

0.51 *

VDDQ

VREFD2

VREFC

External reference voltage for address and

command

0.69 *

VDDQ

0.71 *

VDDQ

0.69 *

VDDQ

0.71 *

VDDQ

DC input logic high voltage for address and

command inputs

VREFC

+ 0.15

VREFC

+ 0.135

VIHA(DC)

VILA(DC)

VIHD(DC)

VILD(DC)

VIHD2(DC)

VILD2(DC)

VIHR

—

DC input logic low voltage for address and

command inputs

VREFC

- 0.15

VREFC

- 0.135

—

DC input logic high voltage for DQ, /DBI

inputs with VREFD

VREFD

+ 0.10

VREFD

+ 0.09

—

DC input logic low voltage for DQ, /DBI

inputs with VREFD

VREFD

- 0.10

VREFD

- 0.09

—

DC input logic high voltage for DQ, /DBI

inputs with VREFD2

VREFD2

+ 0.30

VREFD2

+ 0.27

—

DC input logic low voltage for DQ, /DBI

inputs with VREFD2

VREFD2

- 0.30

VREFD2

- 0.27

—

Input logic high voltage for /RESET, SEN,

MF

VDDQ

- 0.5

VDDQ

- 0.5

—

0.3

—

0.3

—

V

Input logic low voltage for /RESET, SEN, MF VILR

—

Input logic high voltage for EDC1/2

VIHX

VDDQ

- 0.3

VDDQ

- 0.3

9

(x16 mode detect)

Input logic low voltage for EDC1/2

VILX

—

-5

—

0.3

+5

—

-5

—

0.3

+5

V

(x16 mode detect)

Input leakage current

(any input 0V ≤ VIN ≤ VDDQ; all other pins IL

not under test = 0V)

μA 10

μA 11

Output leakage current

(DQs are disabled; 0V ≤ VOUT ≤ VDDQ)

IOZ

Output logic low voltage

External resistor value

VOL(DC)

ZQ

—

0.62

125

—

0.56

125

V

115

120

115

120

Ω

Notes: 1. 0°C ≤ TC ≤ 95°C. All voltages are measured at the package pins.

2. GDDR5 SGRAMs are designed to tolerate PCB designs with separate VDDQ and VDD power regulators.

3. AC noise in the system is estimated at 50 mV peak-to-peak for the purpose of DRAM design.

4. Source of reference voltage and control of Reference voltage for DQ and /DBI pins is determined by VREFD, Half

VREFD and VREFD Offset Mode Registers.

5. VREFD Offsets are not supported with VREFD2.

6. External VREFC is to be provided by the controller as there is no alternative supply.

7. DB, /DBI input slew rate must be greater than or equal to 3V/ns for POD15 and 2.7V/ns for POD135. The slew rate is

measured between VREFD crossing and VIHD(AC) or VILD(AC) or VREFD2 crossing and VIHD2(AC) or VILD2(AC).

8. ADR/CMD input slew rate must be greater than or equal to 3V/ns for POD15 and 2.7V/ns for POD135. The slew rate

is measured between VREFC crossing and VIHA(AC) or VILA(AC).

9. VIHX and VILX define the input voltage levels for the receiver that detects x32 mode or x16 mode with /RESET going

high.

^{10. IL is measured with ODT off. Any input 0V}≤ VIN ≤ VDDQ; all other pins not under test = 0V.

^{11. IOZ is measured with DQs disabled; 0V}≤ VOUT ≤ VDDQ.

Data Sheet E1771E11 (Ver. 1.1)

11

EDW1032BBBG

Table 9: AC Operating Conditions

Parameter

POD15

typ.

POD135

typ.

Symbol

min.

max.

min.

max. Unit Note

AC input logic high voltage for address and

command inputs

VREFC

+ 0.20

VREFC

+ 0.18

VIHA(AC)

—

V

AC input logic low voltage for address and

command inputs

VREFC

- 0.20

VREFC

- 0.18

VILA(AC)

VIHD(AC)

VILD(AC)

VIHD2(AC)

VILD2(AC)

—

AC input logic high voltage for DQ, /DBI

inputs with VREFD

VREFD

+ 0.15

VREFD

+ 0.135

—

AC input logic low voltage for DQ, /DBI

inputs with VREFD

VREFD

- 0.15

VREFD

- 0.135

—

AC input logic high voltage for DQ, /DBI

inputs with VREFD2

VREFD2

+ 0.40

VREFD2

+ 0.36

—

AC input logic low voltage for DQ, /DBI

inputs with VREFD2

VREFD2

- 0.40

VREFD2

- 0.36

—

Notes: 1. 0°C ≤ TC ≤ 95°C. All voltages are measured at the package pins.

2. For optimum performance it is recommended that signal swings are larger than shown in the table.

Table 10: Clock Input Operating Conditions

POD15

POD135

Parameter

Symbol

min.

max.

min.

max.

Unit Note

VREFC

- 0.1

VREFC

+ 0.1

VREFC

- 0.1

VREFC

+ 0.1

Clock input mid-point voltage: CK, /CK

VMP(DC)

V

2,7

Clock input differential voltage: CK, /CK

VIDCK(DC)

VIDCK(AC)

0.22

0.40

0.20

0.30

—

0.198

0.36

0.18

0.27

—

V

5,7

3,5,7

6,8

Clock input differential voltage: WCK, /WCK VIDWCK(DC)

Clock input differential voltage: WCK, /WCK VIDWCK(AC)

3,6,8

Clock input voltage level for CK, /CK,

VIN

VDDQ

+ 0.3

VDDQ

+ 0.3

-0.3

V

WCK, /WCK single ended inputs

CK, /CK single ended slew rate

CKslew

3

—

2.7

—

V/ns 10

V/ns 11

WCK, /WCK single ended slew rate

WCKSlew

VREFC

- 0.12

VREFC

+ 0.12

VREFC

- 0.108

VREFC

+ 0.108

Clock input crossing point voltage: CK, /CK VIXCK(AC)

V

3,4,7

Clock input crossing point voltage:

VIXWCK(AC)

VREFD

- 0.10

VREFD

+ 0.10

VREFD

- 0.09

VREFD

+ 0.09

3,4,

8,9

WCK, /WCK

Notes: 1. 0°C ≤ TC ≤ 95°C. All voltages are measured at the package pins.

2. This provides a minimum of 0.9V to a maximum of 1.2V, and is nominally 70% of VDDQ with POD15. If POD135, this

provides a minimum of 0.845V to a maximum of 1.045V, and is nominally 70% of VDDQ. DRAM timings relative to CK

cannot be guaranteed if these limits are exceeded.

3. For AC operations, all DC clock requirements must be satisfied as well.

4. The value of VIXCK and VIXWCK is expected to equal 70% VDDQ for the transmitting device and must track variations

in the DC level of the same.

5. VIDCK is the magnitude of the difference between the input level in CK and the input level on /CK. The input reference

level for signals other than CK and /CK is VREFC.

6. VIDWCK is the magnitude of the difference between the input level in WCK and the input level on /WCK. The input

reference level for signals other than WCK and /WCK is either VREFD, VREFD2 or the internal VREFD.

7. The CK and /CK input reference level (for timing referenced to CK and /CK) is the point at which CK and /CK cross.

Please refer to the applicable timings in the AC timings table.

8. The WCK and /WCK input reference level (for timing referenced to WCK and /WCK) is the point at which WCK and

/WCK cross. Please refer to the applicable timings in the AC Timings table.

9. VREFD is either VREFD, VREFD2 or the internal VREFD.

10. The slew rate is measured between VREFC crossing and VIXCK(AC).

11. The slew rate is measured between VREFD crossing and VIXWCK(AC).

Data Sheet E1771E11 (Ver. 1.1)

12

EDW1032BBBG

3. Package Drawing

170-ball FBGA

Solder ball: Lead free (Sn-Ag-Cu)

Unit: mm

12.0 0.1

0.2

S A

INDEX MARK

0.2

S B

0.2

S

1.1 0.1

S

0.12

S

0.35 0.05

A

170- 0.45 0.05

M S

A B

0.15

B

INDEX MARK

2.0 0.8

10.4

ECA-TS2-0327-02

Data Sheet E1771E11 (Ver. 1.1)

13

EDW1032BBBG

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR MOS DEVICES

1

Exposing the MOS devices to a strong electric field can cause destruction of the gate

oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop

generation of static electricity as much as possible, and quickly dissipate it, when once

it has occurred. Environmental control must be adequate. When it is dry, humidifier

should be used. It is recommended to avoid using insulators that easily build static

electricity. MOS devices must be stored and transported in an anti-static container,

static shielding bag or conductive material. All test and measurement tools including

work bench and floor should be grounded. The operator should be grounded using

wrist strap. MOS devices must not be touched with bare hands. Similar precautions

need to be taken for PW boards with semiconductor MOS devices on it.

2

HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES

No connection for CMOS devices input pins can be a cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input level may be

generated due to noise, etc., hence causing malfunction. CMOS devices behave

differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected

to VDD or GND with a resistor, if it is considered to have a possibility of being an output

pin. The unused pins must be handled in accordance with the related specifications.

3

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Power-on does not necessarily define initial status of MOS devices. Production process

of MOS does not define the initial operation status of the device. Immediately after the

power source is turned ON, the MOS devices with reset function have not yet been

initialized. Hence, power-on does not guarantee output pin levels, I/O settings or

contents of registers. MOS devices are not initialized until the reset signal is received.

Reset operation must be executed immediately after power-on for MOS devices having

reset function.

CME0107

Data Sheet E1771E11 (Ver. 1.1)

14

EDW1032BBBG

Tꢭe ꢪnformꢩꢨꢪon ꢪn ꢨꢭꢪꢫ documenꢨ ꢪꢫ ꢫubjecꢨ ꢨo cꢭꢩnge wꢪꢨꢭouꢨ noꢨꢪce. Before uꢫꢪng ꢨꢭꢪꢫ documenꢨ, confꢪrm ꢨꢭꢩꢨ ꢨꢭꢪꢫ ꢪꢫ ꢨꢭe lꢩꢨeꢫꢨ verꢫꢪon.

No part of this document may be copied or reproduced in any form or by any means without the prior

written consent of Elpida Memory, Inc.

Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights

(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or

third parties by or arising from the use of the products or information listed in this document. No license,

express, implied or otherwise, is granted under any patents, copyrights or other intellectual property

rights of Elpida Memory, Inc. or others.

Descriptions of circuits, software and other related information in this document are provided for

illustrative purposes in semiconductor product operation and application examples. The incorporation of

these circuits, software and information in the design of the customer's equipment shall be done under

the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses

incurred by customers or third parties arising from the use of these circuits, software and information.

[Producꢨ ꢩpplꢪcꢩꢨꢪonꢫ]

Be aware that this product is for use in typical electronic equipment for general-purpose applications.

Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.

However, this product is not intended for use in the product in aerospace, aeronautics, nuclear power,

combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other

such application in which especially high quality and reliability is demanded or where its failure or

malfunction may directly threaten human life or cause risk of bodily injury. Customers are instructed to

contact Elpida Memory's sales office before using this product for such applications.

[Producꢨ uꢫꢩge]

Design your application so that the product is used within the ranges and conditions guaranteed by

Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation

characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no

responsibility for failure or damage when the product is used beyond the guaranteed ranges and

conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure

rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so

that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other

consequential damage due to the operation of the Elpida Memory, Inc. product.

[ꢬꢫꢩge envꢪronmenꢨ]

Usage in environments with special characteristics as listed below was not considered in the design.

Accordingly, our company assumes no responsibility for loss of a customer or a third party when used in

environments with the special characteristics listed below.

Example:

1) Usage in liquids, including water, oils, chemicals and organic solvents.

2) Usage in exposure to direct sunlight or the outdoors, or in dusty places.

3) Usage involving exposure to significant amounts of corrosive gas, including sea air, CL₂, H₂S, NH₃,

SO₂, and NO .

x

4) Usage in environments with static electricity, or strong electromagnetic waves or radiation.

5) Usage in places where dew forms.

6) Usage in environments with mechanical vibration, impact, or stress.

7) Usage near heating elements, igniters, or flammable items.

If you export the products or technology described in this document that are controlled by the Foreign

Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance

with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by

U.S. export control regulations, or another country's export control laws or regulations, you must follow

the necessary procedures in accordance with such laws or regulations.

If these products/technology are sold, leased, or transferred to a third party, or a third party is granted

license to use these products, that third party must be made aware that they are responsible for

compliance with the relevant laws and regulations.

M01E1007

Data Sheet E1771E11 (Ver. 1.1)

15

EDW1032BBBG

Revision History

Ver.

Date

Apr. 2011 Initial version

Part Number Correction

Description

1.0

1.1

Sep. 2011

Type D : Monolithc Device to Packaged Device

Data Sheet E1771E11 (Ver. 1.1)

16


型号：	EDW1032BBBG-70-F
厂家：	ELPIDA MEMORY
描述：	1G bits GDDR5 SGRAM 1G位GDDR5 SGRAM 双倍数据速率
文件：	总16页 (文件大小：477K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EDW1032BBBG-70-F [ELPIDA]

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