EDW2032BBBG-7A-F_技术文档

DATA SHEET

2G bits GDDR5 SGRAM

EDW2032BBBG (64M words x 32 bits)

Specifications

Features

• Density: 2G bits

• Organization

• x32/x16 mode configuration set at power-up with

EDC pin

• Single ended interface for data, address and command

• Quarter data-rate differential clock inputs CK_t, CK_c

for address and commands

• Two half data-rate differential clock inputs WCK_t,

WCK_c, each associated with two data bytes (DQ,

DBI_n, EDC)

• Double Data Rate (DDR) data (WCK)

• Single Data Rate (SDR) command (CK)

• Double Data Rate (DDR) addressing (CK)

— 4Mbit x 32 I/O x 16 banks

— 8Mbit x 16 I/O x 16 banks

• Package

— 170-ball FBGA

— Lead-free (RoHS compliant) and Halogen-free

• Power supply:

— VDD: 1.6V/1.5V ± 3% and 1.35V ± 3%

— VDDQ: 1.6V/1.5V ± 3% and 1.35V ± 3%

• Data rate: 7.0Gbps/6.0Gbps (max.)

• 16 internal banks

• Write data mask function via address bus

(single/double byte mask)

• Four bank groups for tCCDL = 3tCK

• 8n prefetch architecture: 256 bit per array Read or

Write access for x32; 128 bit for x16

• Data Bus Inversion (DBI) and Address Bus Inversion

(ABI)

• Input/output PLL on/off mode

• Burst length (BL): 8 only

• Duty cycle corrector (DCC) for data clock (WCK)

• Address training: address input monitoring via DQ pins

• WCK2CK clock training: phase information via EDC

pins

• Data read and write training via Read FIFO (FIFO

depth = 6)

• Programmable CAS latency: 6 to 22

• Programmable Write latency: 3 to 7

• Programmable CRC READ latency: 1 to 3

• Programmable CRC WRITE latency: 8 to 14

• Programmable EDC hold pattern for CDR

• Read FIFO pattern preload by LDFF command

• Direct write data load to Read FIFO by WRTR

command

• Consecutive read of Read FIFO by RDTR command

• Read/Write data transmission integrity secured by

cyclic redundancy check (CRC–8)

• Read/Write EDC on/off mode

• DQ Preamble for Read on/off mode

• Low Power modes

• RDQS mode on EDC pin

• On-chip temperature sensor with read-out

• Precharge: auto precharge option for each burst

access

• Refresh: auto-refresh, self-refresh

• Refresh cycles: 16384 cycles/32ms

• Interface: Pseudo open drain (POD-15)

• On-die termination (ODT): nom. values of 60Ω or 120Ω

• Pseudo open drain (POD-15) compatible outputs

— 40Ω pulldown

— 60Ω pullup

• ODT and output driver strength auto-calibration with

external resistor ZQ pin (120Ω)

• Programmable termination and driver strength offsets

• Automatic temperature sensor controlled self-refresh

rate

• Digital RAS lockout

• Selectable external or internal VREF for data inputs;

programmable offsets for internal VREF

• Vendor ID, FIFO depth and Density info fields for

identification

• Mirror function with MF pin

• Separate external VREF for address / command inputs

• Operating case temperature range

— TC = 0°C to +95°C

• Boundary Scan function with SEN pin

Document No. E1864E20 (Ver. 2.0)

Date Published April 2013 (K) Japan

Printed in Japan

URL: http://www.elpida.com

©Elpida Memory, Inc. 2011-2013

EDW2032BBBG

Ordering Information

Organization

Part number

(words x bits)

VDD, VDDQ

Max. Data Rate

Package

EDW2032BBBG-6A-F

EDW2032BBBG-7A-F

64M x 32

1.5V / 1.35V

1.6V / 1.35V

6.0Gbps / 5.0Gbps

7.0Gbps / 5.0Gbps

170-ball FBGA

^{Part Number}E D W 20 32 B B BG - 7A - F

Elpida Memory

Environment Code

Type

F: Lead Free (RoHS compliant)

and Halogen Free

D: Packaged Device

Product Family

W: GDDR5 SGRAM

Speed

6A: 6.0Gbps

7A: 7.0Gbps

Density/Bank

20: 2Gb/16-bank

Organization

32: x32

Package

BG: FBGA

Revision

Power Supply, Interface

B: VDD = 1.6V / 1.5V

Data Sheet E1864E20 (Ver. 2.0)

2

EDW2032BBBG

Pin Configuration

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Data Sheet E1864E20 (Ver. 2.0)

3

EDW2032BBBG

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Signal

Function

Signal

ZQ

Function

CK_t, CK_c

Clock

Impedance Reference

WCK01_t, WCK01_c,

WCK23_t, WCK23_c

Data Clocks

RESET_n

Reset

CKE_n

CS_n

Clock Enable

Chip Select

MF

Mirror Function

SEN

Scan Enable

RAS_n, CAS_n, WE_n Command inputs

VREFC

VREFD

VDDQ

VSSQ

VDD

Reference voltage for command and address

BA0 - BA3

A0 - A12

Bank Address inputs

Address inputs

Reference voltage for DQ and DBI_n

I/O power

DQ0 - DQ31

DBI0_n - DBI3_n

EDC0 - EDC3

ABI_n

Data Input/Output

Data bus inversion

I/O ground

Power supply

Error Detection Code

Address bus inversion

VSS

Ground

NC

Not connected

Data Sheet E1864E20 (Ver. 2.0)

4

EDW2032BBBG

1. Configuration

The Elpida GDDR5 SGRAM is a high speed dynamic random-access memory designed for applications requiring

high bandwidth. It contains 2,147,483,648 bits and is internally configured as a 16-bank DRAM.

The GDDR5 SGRAM uses a 8n prefetch architecture and DDR interface to achieve high-speed operation. The

device can be configured to operate in x32 mode or x16 (clamshell) mode. The mode is detected during device

initialization. The GDDR5 interface transfers two 32 bit wide data words per WCK clock cycle to/from the I/O pins.

Corresponding to the 8n prefetch a single write or read access consists of a 256 bit wide, two CK clock cycle data

transfer at the internal memory core and eight corresponding 32 bit wide one-half WCK clock cycle data transfers

at the I/O pins.

The GDDR5 SGRAM operates from a differential clock CK_t and CK_c. Commands are registered at every rising

edge of CK_t. Addresses are registered at every rising edge of CK_t and every rising edge of CK_c.

GDDR5 replaces the pulsed strobes (WDQS & RDQS) used in previous DRAMs such as GDDR4 with a free running

differential forwarded clock (WCK_t, WCK_c) with both input and output data registered and driven respectively at

both edges of the forwarded WCK.

Read and write accesses to the GDDR5 SGRAM are burst oriented; an access starts at a selected location and

continues for a total of eight data words. Accesses begin with the registration of an ACTIVE command, which is then

followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command and

the next rising CK_c edge are used to select the bank and the row to be accessed. The address bits registered

coincident with the READ or WRITE command and the next rising CK_c edge are used to select the bank and the

column location for the burst access.

Data Sheet E1864E20 (Ver. 2.0)

5

EDW2032BBBG

1.1 Signal Description

Table 1: Signal Description

Signal

Type

Detailed Function

Clock: CK_t and CK_c are differential clock inputs. Command inputs are latched on the rising

edge of CK_t. Address inputs are latched on the rising edge of CK_t and the rising edge of

CK_c. All latencies are referenced to CK_t. CK_t and CK_c are externally terminated.

CK_t, CK_c

Input

WCK01_t,

WCK01_c,

WCK23_t,

WCK23_c

Data Clocks: WCK_t and WCK_c are differential clocks used for WRITE data capture and

READ data output. WCK01_t,WCK01_c is associated with DQ0-DQ15, DBI0_n, DBI1_n,

EDC0 and EDC1. WCK23_t,WCK23_c is associated with DQ16-DQ31, DBI2_n, DBI3_n,

EDC2 and EDC3. WCK clocks operate at nominally twice the CK clock frequency.

Input

Clock Enable: CKE_n low activates and CKE_n high deactivates internal clock, device input

buffers and output drivers. Taking CKE_n high provides Precharge Power-Down and Self-

Refresh operations (all banks idle), or Active Power-Down (row active in any bank). CKE_n is

synchronous for Power-Down entry and exit and for Self-Refresh entry. CKE_n must be

maintained low throughout READ and WRITE accesses. Input buffers excluding CK_t, CK_c,

CKE_n, WCK01_t, WCK01_c, WCK23_t, WCK23_c are disabled during Power-Down. Input

buffers excluding CKE_n are disabled during Self-Refresh. The value of CKE_n latched at

power-up with RESET_n going high determines the termination value of the address and

command inputs.

CKE_n

CS_n

Chip Select: CS_n low enables, and CS_n high disables the command decoder. All commands

are masked when CS_n is registered high, but internal command execution continues. CS_n

provides for individual device selection on memory channels with multiple memory devices.

CS_n is considered part of the command code.

Input

RAS_n, CAS_n,

WE_n

Command inputs: RAS_n, CAS_n and WE_n (along with CS_n) define the command to be

entered.

Bank Address inputs: BA0-BA3 define to which bank an ACTIVE, READ, WRITE or

PRECHARGE command is being applied. BA0-BA3 also determine which Mode Register is

accessed with a MODE REGISTER SET command. BA0-BA3 are sampled with the rising edge

of CK_t.

BA0 - BA3

Address inputs: A0-A12 provide the row address for ACTIVE commands. A0-A5(A6) provide

the column address and A8 defines the auto precharge function for READ and WRITE

commands, to select one location out of the memory array in the respective bank. A8 sampled

during a PRECHARGE command determines whether the PRECHARGE applies to one bank

(A8 low, bank selected by BA0-BA3) or all banks (A8 high). The address inputs also provide

the op-code during an MODE REGISTER SET command, and the data bits during LDFF

commands. A8-A12 are sampled with the rising edge of CK _t and A0-A7 are sampled with the

rising edge of CK_c.

A0 - A12

Input

I/O

DQ0 - DQ31

Data Input/Output: 32 bit data bus

Data bus inversion: DBI0_n is associated with DQ0-DQ7, DBI1_n with DQ8-DQ15, DBI2_n

with DQ16-DQ23, and DBI3_n with DQ24-DQ31.

DBI0_n - DBI3_n I/O

Error Detection Code: The calculated CRC data is transmitted on these pins. In addition these

pins drive a hold pattern when idle and can be used as an RDQS function. EDC0 is associated

with DQ0-DQ7, EDC1 with DQ8-DQ15, EDC2 with DQ16-DQ23, and EDC3 with DQ24-DQ31.

EDC0 - EDC3

Output

ABI_n

ZQ

Input

-

Address bus inversion

Impedance Reference: external reference pin for auto-calibration

Reset: VDDQ CMOS input. A full chip reset may be performed at any time by pulling RESET_n

low. With RESET_n low all ODTs are disabled.

RESET_n

Input

MF

Input

Mirror Function: VDDQ CMOS input. Must be tied to Power or Ground.

Scan Enable: VDDQ CMOS input. Must be tied to Ground when not in use.

Reference voltage for command and address inputs.

Reference voltage for DQ and DBI_n inputs.

Isolated power for the input and output buffers.

Isolated ground for the input and output buffers.

Power supply

SEN

Input

VREFC

VREFD

VDDQ

VSSQ

VDD

Supply

-

VSS

Ground

NC

Not connected

Data Sheet E1864E20 (Ver. 2.0)

6

EDW2032BBBG

1.2 Mirror Function Mode

The GDDR5 SGRAM provides a mirror function (MF) pin to change the physical location of the command, address,

data and WCK pins assisting in routing devices back to back. The MF ball should be tied directly to VSSQ or VDDQ

depending on the control line orientation desired.

The pins affected by this Mirror Function mode are listed in Table 2.

Table 2: Ball Assignment with Mirror Function

Signal

MF=1

Signal

MF=1

Signal

MF=1

A9 A1

Signal

MF=1

Ball

A2

B2

C2

D2

E2

F2

M2

N2

P2

R2

T2

U2

G3

L3

MF=0

DQ1

Ball

A4

B4

D4

E4

F4

MF=0

DQ0

DQ2

Ball

K5

MF=0

Ball

G12

L12

A13

B13

C13

D13

E13

F13

M13

N13

P13

R13

T13

U13

MF=0

CS_n

WE_n

DQ9

DQ25

DQ27

EDC3

DQ24

DQ26

A11 A6

WE_n

CS_n

DQ17

DQ19

EDC2

DQ3

P5

WCK23_c WCK01_c

EDC0

WCK01_t WCK23_t

H10

K10

A11

B11

E11

F11

H11

K11

M11

N11

T11

U11

BA3 A3

BA1 A5

DQ8

BA1 A5

BA3 A3

DQ16

DQ18

DQ20

DQ22

BA2 A4

BA0 A2

DQ14

DQ12

DQ10

DQ8

DBI0_n DBI3_n

DQ4

DQ28

DQ30

A8 A7

A10 A0

DQ6

DQ11

EDC1

DQ5

DQ29

DQ31

DQ7

DQ6

DQ7

H4

K4

M4

N4

P4

T4

A10 A0

A8 A7

DQ30

DQ28

DQ10

DQ12

DQ14

BA0 A2

BA2 A4

DQ22

DQ20

DQ18

DQ16

DBI1_n DBI2_n

DQ31

DQ29

DQ13

DQ15

DQ23

DQ21

DQ23

DQ15

DQ13

DQ5

DBI3_n DBI0_n

DQ4

EDC3

DQ27

DQ25

EDC0

DQ3

WCK23_t WCK01_t

DQ26

DQ24

DQ2

DQ0

DBI2_n DBI1_n

DQ1

U4

D5

H5

EDC2

DQ19

DQ17

EDC1

DQ11

DQ9

RAS_n CAS_n

CAS_n RAS_n

WCK01_c WCK23_c

A9 A1 A11 A6

Functions within the GDDR5 SGRAM that refer to external signals are transparent with respect to Mirror Function

mode, meaning that the signal names shown in the respective functional description apply both to mirrored (MF=1)

and non-mirrored (MF=0) modes. The referenced package pin is determined by the Mirror Function mode the

devices is configured to.

1.3 Clamshell Mode Detection

The GDDR5 SGRAM can operate in a x32 mode or a x16 mode to allow a clamshell configuration with a point to

point connection on the high speed data signals. The disabled pins in x16 mode will be in Hi-Z state, non-terminating.

The x16 mode is detected at power-up on the pin at location C-13 which is EDC1 when configured to MF=0 and

EDC2 when configured to MF=1. For x16 mode this pin is tied to VSSQ; the pin is part of the two bytes that are

disabled in this mode and therefore not needed for EDC functionality. For x32 mode this pin is active and always

terminated to VDDQ in the system or by the controller. The configuration is set with RESET_n going high. Once the

configuration has been set, it cannot be changed during normal operation. Usually the configuration is fixed in the

system.

Table 3: Clamshell Mode and Mirror Function

Mode

MF

EDC1 (MF=0) or EDC2 (MF=1)

x16 non-mirrored

x32 non-mirrored

x16 mirrored

x32 mirrored

VSSQ

VDDQ

VSSQ

VDDQ (terminated by the system or controller)

VSSQ

VDDQ (terminated by the system or controller)

Data Sheet E1864E20 (Ver. 2.0)

7

EDW2032BBBG

Figure 1 shows examples of the board channels and topologies that are supported in GDDR5 in order to illustrate

the expected usage of x16 mode and the MF pin.

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Figure 1: Example GDDR5 PCB Layout Topologies

Data Sheet E1864E20 (Ver. 2.0)

8

EDW2032BBBG

1.4 Clocking

The GDDR5 SGRAM operates from a differential clock CK_t and CK_c. Commands are registered at every rising

edge of CK_t. Addresses are registered at every rising edge of CK_t and every rising edge of CK_c.

GDDR5 uses a double data rate data interface and an 8n-prefetch architecture. The data interface uses two

differential forwarded clocks (WCK_t, WCK_c). DDR means that the data is registered at every rising edge of WCK_t

and rising edge of WCK_c. WCK_t and WCK_c are continuously running and operate at twice the frequency of the

command/address clock (CK_t, CK_c).

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Figure 2: GDDR5 Clocking and Interface Relationship

1.5 Addressing

The GDDR5 SGRAM uses a double data rate address scheme to reduce pins required on the GDDR5 SGRAM as

shown in Table 4. The addresses should be provided to the GDDR5 SGRAM in two parts; the first half is latched on

the rising edge of CK_t along with the command pins such as RAS_n, CAS_n and WE_n; the second half is latched

on the rising edge of CK_c.

The use of DDR addressing allows all address values to be latched in at the same rate as the SDR commands. All

addresses related to command access have been positioned for latching on the initial rising edge for faster

decoding.

Table 4: Address Pairs

Clock Edge

Rising CK_t

Rising CK_c

Address Inputs

A12

BA3

A3

BA2

A4

BA1

A5

BA0

A2

A11

A6

A10

A0

A9

A1

A8

A7

(RFU)

Addressing schemes for x32 mode and x16 mode differ only in the number of valid column addresses, as shown in

Table 5.

Table 5: Addressing Scheme

64M x 32

A0-A12

A0-A5

128M x 16

A0-A12

A0-A6

Row address

Column address

Bank address

Autoprecharge

Page size

BA0-BA3

A8

BA0-BA3

A8

2 KB

Refresh

16K/32ms

1.9 µs

16K/32ms

1.9 µs

Refresh period

Data Sheet E1864E20 (Ver. 2.0)

9

EDW2032BBBG

1.6 Commands

Table 6: Command Truth Table

CKE_n CKE_n CS RAS CAS WE BA3-

A6-A7, A0-A5

Operation

Code

(n-1)

(n)

_n _n

_n

_n BA0 A12 A11 A10 A8 A9

(A6) Note

DESELECT

DESEL

L

X

H

X

2,8

NO OPERATION

(NOP)

NOP

MRS

L

X

L

H

L

H

X

2,8

MODE REGISTER

SET

L

MRA X

OPCODE

2,3

ACTIVATE

READ

ACT

RD

L

H

L

H

BA

RA

2,4

H

X

L

X

CA

2,5,9

READ with

Autoprecharge

RDA

L

H

L

H

BA

X

H

2,5

LOAD FIFO

LDFF

L

H

L

H

L

BST

X

H

L

H

L

DATA

2,7

2

READ TRAINING

RDTR

X

WRITE without Mask WR

WRITE without Mask

BA

CA

2,5

WRA

L

H

L

BA

X

L

H

L

X

CA

2,5

with Autoprecharge

WRITE with Single

Byte Mask

WSM

H

WRITE with

Autoprecharge,

Single Byte Mask

WSMA

WDM

L

H

L

BA

X

L

H

L

H

L

X

CA

2,5

WRITE with Double

Byte Mask

H

WRITE with

Autoprecharge,

Double Byte Mask

WDMA

L

H

WRITE TRAINING

PRECHARGE

PRECHARGE ALL

REFRESH

WRTR

PRE

L

H

L

H

L

H

L

X

H

X

H

X

L

X

2

6

H

L

BA

X

L

PREALL L

L

H

X

REF

L

H

X

H

X

H

X

H

X

H

X

H

X

H

POWER-DOWN

ENTRY

PDE

L

H

X

POWER-DOWN

EXIT

PDX

SRE

SRX

H

L

H

L

X

SELF REFRESH

ENTRY

L

H

6

H

L

X

H

X

H

X

H

SELF REFRESH

EXIT

H

Notes: 1. H = logic high level; L = logic low level; X = Don’t Care. Signal may be H or L, but not floating.

2. Addresses shown are logical addresses; physical addresses are inverted when address bus inversion (ABI) is

activated and ABI_n=L.

3. BA0-BA3 provide the Mode Register address (MRA), A0-A11 the opcode to be loaded.

4. BA0-BA3 provide the bank address (BA), A0-A12 provide the row address (RA).

5. BA0-BA3 provide the bank address, A0-A5 (A6) provide the column address (CA); no sub-word addressing within a

burst of 8.

6. This command is REFRESH when CKE_n(n) = L, and SELF-REFRESH ENTRY when CKE_n(n) is H.

7. BA0-BA2 select burst location (BST) and A0-A9, BA3 provide the data.

8. DESELECT and NO OPERATION are functionally interchangeable.

9. In address training mode READ is decoded from the command pins only with RAS_n = H, CAS_n = L, WE_n= H.

Data Sheet E1864E20 (Ver. 2.0)

10

EDW2032BBBG

2. Electrical Characteristics

Table 7: Absolute Maximum Ratings

Parameter

Symbol

VDD

Min.

-0.5

-55

Max.

2.0

Unit

V

Voltage on VDD supply relative to VSS

Voltage on VDDQ supply relative to VSSQ

Voltage on VREF and inputs relative to VSS

Voltage on I/O pins relative to VSS

Storage Temperature

VDDQ

VIN

2.0

V

2.0

V

VOUT

TSTG

IOUT

2.0

V

+150

50

°C

mA

Short Circuit output current

—

Caution: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent

damage of the device. This is a stress rating only, and functional operation of the device at these

or any other conditions above those indicated in the operational sections of these specification

is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

2.1 Operating Conditions

Table 8: Operating Temperature Range

Parameter

Symbol

Min

Max

Unit

Operating temperature

TC

0

+95

°C

Notes: 1. Operating temperature TC is the case surface temperature on the center / top side of the DRAM. It specifies the

temperature where all DRAM specifications will be supported.

2. For measurement conditions, please refer to JEDEC document JESD51-2.

Table 9: Input Capacitance

Parameter

Symbol

DCIO

DCI1

DCI2

DCI3

CIO

Min

—

Max

0.3

0.2

0.1

1.5

1.6

1.1

Unit Notes

Delta Input/Output Capacitance: DQ, DBI_n, EDC

Delta Input Capacitance: Command and Address

Delta Input Capacitance: CK_t, CK_c

Delta Input Capacitance: WCK_t, WCK_c

Input/Output Capacitance: DQ, DBI_n, EDC

Input Capacitance: Command and Address

Input Capacitance: CK_t, CK_c

pF

1,2

1,3,6

1,4

1,5

1

—

1.0

1.3

1.4

0.9

CI1

1,6

1

CI2

Input Capacitance: WCK_t, WCK_c

CI3

1

Notes: 1. The capacitance is measured according to JEP147 (“PROCEDURE FOR MEASURING INPUT CAPACITANCE

USING A VECTOR NETWORK ANALYZER (VNA)”) with VDD, VDDQ, VSS, VSSQ applied and all other pins floating

(except the pin under test). VDD=VDDQ=1.5V and on-die termination off.

2. DCIO = CIO.MAX - CIO.MIN

3. DCI1 = CI1.MAX - CI1.MIN

4. DCI2 = Absolute value of C CK_t - C CK_c

5. DCI3 = Absolute value of C WCK_t - C WCK_c

6. DCI1 and CI1 apply to RAS_n, CAS_n, WE_n, CS_n, CKE_n, ABI_n, BA3/A3, BA2/A4, BA1/A5, BA0/A2, A12/RFU,

A11/A6, A10/A0, A9/A1, A8/A7

Data Sheet E1864E20 (Ver. 2.0)

11

EDW2032BBBG

GDDR5 SGRAMs are designed for 1.5V typical voltage supplies. This GDDR5 SGRAM does also support 1.35V

typical voltage supplies. The interface of GDDR5 with 1.5V VDDQ will follow the POD15 specification (JESD8-20A).

The interface of GDDR5 with 1.35V VDDQ will follow the POD135 specification Class B (JESD8-21). I/O levels are

given here for reference only. All AC and DC values are measured at the ball.

Table 10: DC Operating Conditions

POD15

typ.

1.6

POD135

typ.

Parameter

Symbol

VDD

min.

1.552

1.455

1.552

1.455

max.

1.648

1.545

1.648

1.545

min.

max. Unit Notes

Device supply voltage (-7A)

Device supply voltage (-6A)

I/O Supply voltage (-7A)

I/O Supply voltage (-6A)

1.3095

1.35

1.3905

V

1

VDD

1.5

1.35

VDDQ

1.6

1.35

1.5

1.35

0.69 *

VDDQ

0.71 *

VDDQ

0.69 *

VDDQ

0.71 *

VDDQ

Reference voltage for DQ and DBI_n pins VREFD

Reference voltage for DQ and DBI_n pins VREFD2

—

V

2,3

2,3,4

5

0.49 *

VDDQ

0.51 *

VDDQ

0.49 *

VDDQ

0.51 *

VDDQ

External reference voltage for address and

command

0.69 *

VDDQ

0.71 *

VDDQ

0.69 *

VDDQ

0.71 *

VDDQ

VREFC

DC input logic high voltage for address and

VIHA(DC)

VREFC

+ 0.15

VREFC

+ 0.135

—

command inputs

DC input logic low voltage for address and

VILA(DC)

VREFC

- 0.15

VREFC

- 0.135

—

command inputs

DC input logic high voltage for DQ, DBI_n

VIHD(DC)

VREFD

+ 0.10

VREFD

+ 0.09

—

inputs with VREFD

DC input logic low voltage for DQ, DBI_n

VILD(DC)

VREFD

- 0.10

VREFD

- 0.09

—

inputs with VREFD

DC input logic high voltage for DQ, DBI_n

VIHD2(DC)

VREFD2

+ 0.30

VREFD2

+ 0.27

—

inputs with VREFD2

DC input logic low voltage for DQ, DBI_n

VILD2(DC)

VREFD2

- 0.30

VREFD2

- 0.27

—

inputs with VREFD2

Input logic high voltage for RESET_n, SEN,

MF

VDDQ

- 0.5

VDDQ

- 0.5

VIHR

—

0.3

—

0.3

—

Input logic low voltage for RESET_n, SEN,

MF

VILR

—

Input logic high voltage for EDC1/2

VIHX

VDDQ

- 0.3

VDDQ

- 0.3

8

(x16 mode detect)

Input logic low voltage for EDC1/2

VILX

—

-5

0.3

—

-5

0.3

(x16 mode detect)

Input leakage current

(any input 0V ≤ VIN ≤ VDDQ; all other pins IL

not under test = 0V)

—

+5

—

+5

µA

9

Output leakage current

(DQs are disabled; 0V ≤ VOUT ≤ VDDQ)

IOZ

—

+5

—

+5

µA 10

Output logic low voltage

External resistor value

VOL(DC)

ZQ

—

0.62

125

—

0.56

125

V

115

120

115

120

Ω

Notes: 1. GDDR5 SGRAMs are designed to tolerate PCB designs with separate VDDQ and VDD power regulators.

2. AC noise in the system is estimated at 50 mV peak-to-peak for the purpose of DRAM design.

3. Source of reference voltage and control of Reference voltage for DQ and DBI_n pins is determined by VREFD, Half

VREFD and VREFD Offset Mode Registers.

4. VREFD Offsets are not supported with VREFD2.

5. External VREFC is to be provided by the controller as there is no alternative supply.

6. DB, DBI_n input slew rate must be greater than or equal to 3V/ns for POD15 and 2.7V/ns for POD135. The slew rate

is measured between VREFD crossing and VIHD(AC) or VILD(AC) or VREFD2 crossing and VIHD2(AC) or

VILD2(AC).

7. ADD/CMD input slew rate must be greater than or equal to 3V/ns for POD15 and 2.7V/ns for POD135. The slew rate

is measured between VREFC crossing and VIHA(AC) or VILA(AC).

Data Sheet E1864E20 (Ver. 2.0)

12

EDW2032BBBG

8. VIHX and VILX define the input voltage levels for the receiver that detects x32 mode or x16 mode with RESET_n going high.

9. IL is measured with ODT off. Any input 0V ≤ VIN ≤ VDDQ; all other pins not under test = 0V.

^{10. IOZ is measured with DQs disabled; 0V}≤ VOUT ≤ VDDQ.

Table 11: AC Operating Conditions

POD15

typ.

POD135

typ.

Parameter

Symbol

min.

max.

min.

max. Unit Notes

AC input logic high voltage for address and

command inputs

VREFC

+ 0.20

VREFC

+ 0.18

VIHA(AC)

—

V

AC input logic low voltage for address and

command inputs

VREFC

- 0.20

VREFC

- 0.18

VILA(AC)

VIHD(AC)

VILD(AC)

VIHD2(AC)

VILD2(AC)

—

AC input logic high voltage for DQ, DBI_n

inputs with VREFD

VREFD

+ 0.15

VREFD

+ 0.135

—

AC input logic low voltage for DQ, DBI_n

inputs with VREFD

VREFD

- 0.15

VREFD

- 0.135

—

AC input logic high voltage for DQ, DBI_n

inputs with VREFD2

VREFD2

+ 0.40

VREFD2

+ 0.36

—

AC input logic low voltage for DQ, DBI_n

inputs with VREFD2

VREFD2

- 0.40

VREFD2

- 0.36

—

Notes: 1. For optimum performance it is recommended that signal swings are larger than shown in the table.

Table 12: Clock Input Operating Conditions

POD15

POD135

Parameter

Symbol

min.

max.

min.

max.

Unit Notes

VREFC

- 0.1

VREFC

+ 0.1

VREFC

- 0.1

VREFC

+ 0.1

Clock input mid-point voltage: CK_t, CK_c

VMP(DC)

V

1,6

Clock input differential voltage: CK_t, CK_c VIDCK(DC)

Clock input differential voltage: CK_t, CK_c VIDCK(AC)

0.22

0.40

—

0.198

0.36

—

V

4,6

2,4,6

Clock input differential voltage: WCK_t,

VIDWCK(DC)

WCK_c

0.20

0.30

-0.3

—

0.18

0.27

-0.3

—

V

5,7

Clock input differential voltage: WCK_t,

VIDWCK(AC)

WCK_c

2,5,7

Clock input voltage level for CK_t, CK_c,

VIN

VDDQ

+ 0.3

VDDQ

+ 0.3

WCK_t, WCK_c single ended inputs

CK_t, CK_c single ended slew rate

CKslew

3

—

2.7

—

V/ns 9

WCK_t, WCK_c single ended slew rate

WCKSlew

V/ns 10

Clock input crossing point voltage: CK_t,

CK_c

VREFC

- 0.12

VREFC

+ 0.12

VREFC

- 0.108

VREFC

+ 0.108

VIXCK(AC)

V

2,3,6

Clock input crossing point voltage:

WCK_t, WCK_c

VREFD

- 0.10

VREFD

+ 0.10

VREFD

- 0.09

VREFD

+ 0.09

2,3,7,

8

VIXWCK(AC)

Notes: 1. This provides a minimum of 0.9V to a maximum of 1.2V, and is nominally 70% of VDDQ with POD15. If POD135, this

provides a minimum of 0.845V to a maximum of 1.045V, and is nominally 70% of VDDQ. DRAM timings relative to CK

cannot be guaranteed if these limits are exceeded.

2. For AC operations, all DC clock requirements must be satisfied as well.

3. The value of VIXCK and VIXWCK is expected to equal 70% VDDQ for the transmitting device and must track variations

in the DC level of the same.

4. VIDCK is the magnitude of the difference between the input level in CK_t and the input level on CK_c. The input

reference level for signals other than CK_t and CK_c is VREFC.

5. VIDWCK is the magnitude of the difference between the input level in WCK_t and the input level on WCK_c. The input

reference level for signals other than WCK_t and WCK_c is either VREFD, VREFD2 or the internal VREFD.

6. The CK_t and CK_c input reference level (for timing referenced to CK_t and CK_c) is the point at which CK_t and

CK_c cross. Please refer to the applicable timings in the AC timings table.

7. The WCK_t and WCK_c input reference level (for timing referenced to WCK_t and WCK_c) is the point at which

WCK_t and WCK_c cross. Please refer to the applicable timings in the AC Timings table.

8. VREFD is either VREFD, VREFD2 or the internal VREFD.

9. The slew rate is measured between VREFC crossing and VIXCK(AC).

10. The slew rate is measured between VREFD crossing and VIXWCK(AC).

Data Sheet E1864E20 (Ver. 2.0)

13

EDW2032BBBG

3. Package Drawing

170-ball FBGA

Solder ball: Lead free (Sn-Ag-Cu)

Unit: mm

12.0 0.1

0.2

S A

INDEX MARK

0.2

S B

0.2

S

1.1 0.1

S

0.12

S

0.35 0.05

A

170- 0.45 0.05

M S

A B

0.15

B

INDEX MARK

2.0 0.8

10.4

ECA-TS2-0327-02

Data Sheet E1864E20 (Ver. 2.0)

14

EDW2032BBBG

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR MOS DEVICES

1

Exposing the MOS devices to a strong electric field can cause destruction of the gate

oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop

generation of static electricity as much as possible, and quickly dissipate it, when once

it has occurred. Environmental control must be adequate. When it is dry, humidifier

should be used. It is recommended to avoid using insulators that easily build static

electricity. MOS devices must be stored and transported in an anti-static container,

static shielding bag or conductive material. All test and measurement tools including

work bench and floor should be grounded. The operator should be grounded using

wrist strap. MOS devices must not be touched with bare hands. Similar precautions

need to be taken for PW boards with semiconductor MOS devices on it.

2

HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES

No connection for CMOS devices input pins can be a cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input level may be

generated due to noise, etc., hence causing malfunction. CMOS devices behave

differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected

to VDD or GND with a resistor, if it is considered to have a possibility of being an output

pin. The unused pins must be handled in accordance with the related specifications.

3

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Power-on does not necessarily define initial status of MOS devices. Production process

of MOS does not define the initial operation status of the device. Immediately after the

power source is turned ON, the MOS devices with reset function have not yet been

initialized. Hence, power-on does not guarantee output pin levels, I/O settings or

contents of registers. MOS devices are not initialized until the reset signal is received.

Reset operation must be executed immediately after power-on for MOS devices having

reset function.

CME0107

Data Sheet E1864E20 (Ver. 2.0)

15

EDW2032BBBG

The information in this document is subject to change without noticeꢞ Before using this documentꢟ confirm that this is the latest versionꢞ

No part of this document may be copied or reproduced in any form or by any means without the prior

written consent of Elpida Memory, Inc.

Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights

(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or

third parties by or arising from the use of the products or information listed in this document. No license,

express, implied or otherwise, is granted under any patents, copyrights or other intellectual property

rights of Elpida Memory, Inc. or others.

Descriptions of circuits, software and other related information in this document are provided for

illustrative purposes in semiconductor product operation and application examples. The incorporation of

these circuits, software and information in the design of the customer's equipment shall be done under

the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses

incurred by customers or third parties arising from the use of these circuits, software and information.

[Product applications]

Be aware that this product is for use in typical electronic equipment for general-purpose applications.

Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.

However, this product is not intended for use in the product in aerospace, aeronautics, nuclear power,

combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other

such application in which especially high quality and reliability is demanded or where its failure or

malfunction may directly threaten human life or cause risk of bodily injury. Customers are instructed to

contact Elpida Memory's sales office before using this product for such applications.

[Product usage]

Design your application so that the product is used within the ranges and conditions guaranteed by

Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation

characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no

responsibility for failure or damage when the product is used beyond the guaranteed ranges and

conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure

rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so

that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other

consequential damage due to the operation of the Elpida Memory, Inc. product.

[Usage environment]

Usage in environments with special characteristics as listed below was not considered in the design.

Accordingly, our company assumes no responsibility for loss of a customer or a third party when used in

environments with the special characteristics listed below.

Example:

1) Usage in liquids, including water, oils, chemicals and organic solvents.

2) Usage in exposure to direct sunlight or the outdoors, or in dusty places.

3) Usage involving exposure to significant amounts of corrosive gas, including sea air, CL₂, H₂S, NH₃,

SO₂, and NO .

x

4) Usage in environments with static electricity, or strong electromagnetic waves or radiation.

5) Usage in places where dew forms.

6) Usage in environments with mechanical vibration, impact, or stress.

7) Usage near heating elements, igniters, or flammable items.

If you export the products or technology described in this document that are controlled by the Foreign

Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance

with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by

U.S. export control regulations, or another country's export control laws or regulations, you must follow

the necessary procedures in accordance with such laws or regulations.

If these products/technology are sold, leased, or transferred to a third party, or a third party is granted

license to use these products, that third party must be made aware that they are responsible for

compliance with the relevant laws and regulations.

M01E1007

Data Sheet E1864E20 (Ver. 2.0)

16

EDW2032BBBG

Revision History

Ver.

1.0

Date

Description

Dec. 2011 Initial version

2.0

Apr. 2013 Speed bins “40” and “50” deleted;

Table “Input Capacitance” added (p11)

Data Sheet E1864E20 (Ver. 2.0)

17


型号：	EDW2032BBBG-7A-F
厂家：	ELPIDA MEMORY
描述：	2G bits GDDR5 SGRAM 2G GDDR5位SGRAM 双倍数据速率
文件：	总17页 (文件大小：222K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EDW2032BBBG-7A-F [ELPIDA]

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