HM5118165TT-6_技术文档

HM5118165 Series

16 M EDO DRAM (1-Mword × 16-bit)

1 k Refresh

E0154H10 (Ver. 1.0)

(Previous ADE-203-636D (Z))

Jul. 6, 2001 (K)

Description

The HM5118165 is a CMOS dynamic RAM organized as 1,048,576-word × 16-bit. It employs the most

advanced 0.5 µm CMOS technology for high performance and low power. The HM5118165 offers Extended

Data Out (EDO) Page Mode as a high speed access mode. It is packaged in 42-pin plastic SOJ and 50-pin

plastic TSOP II.

Features

•

Single 5 V (±10%)

Access time : 50 ns/60 ns/70 ns (max)

Power dissipation

Active mode : 1045 mW/935 mW/825 mW (max)

Standby mode : 11 mW (max)

: 0.83 mW (max) (L-version)

EDO page mode capability

Refresh cycles

•

1024 refresh cycles : 16 ms

: 128 ms (L-version)

•

4 variations of refresh

RAS-only refresh

CAS-before-RAS refresh

Hidden refresh

Self refresh (L-version)

•

2CAS-byte control

Battery backup operation (L-version)

Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.

HM5118165 Series

Ordering Information

Type No.

Access time

Package

HM5118165J-5

HM5118165J-6

HM5118165J-7

50 ns

60 ns

70 ns

400-mil 42-pin plastic SOJ (CP-42D)

HM5118165LJ-5

HM5118165LJ-6

HM5118165LJ-7

50 ns

60 ns

70 ns

HM5118165TT-5

HM5118165TT-6

HM5118165TT-7

50 ns

60 ns

70 ns

400-mil 50-pin plastic TSOP II (TTP-50/44DC)

HM5118165LTT-5

HM5118165LTT-6

HM5118165LTT-7

50 ns

60 ns

70 ns

Data Sheet E0154H10

2

HM5118165 Series

Pin Arrangement

HM5118165J/LJ Series

HM5118165TT/LTT Series

V

1

50

49

48

47

46

45

44

43

42

41

40

V

SS

CC

V

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

V

1

SS

CC

I/O0

I/O1

I/O2

I/O3

2

I/O15

I/O14

I/O13

I/O12

I/O15

I/O14

I/O13

I/O12

I/O0

I/O1

I/O2

I/O3

2

3

4

5

4

V

6

V

5

CC

SS

I/O4

I/O5

I/O6

I/O7

NC

7

I/O11

I/O10

I/O9

I/O8

NC

V

6

SS

CC

8

I/O11

I/O10

I/O9

I/O8

NC

I/O4

I/O5

I/O6

I/O7

NC

WE

RAS

NC

A0

7

9

8

10

11

9

10

11

12

13

14

15

16

17

18

19

20

21

LCAS

UCAS

OE

NC

WE

RAS

NC

A0

15

16

17

18

19

20

21

22

23

24

25

36

35

34

33

32

31

30

29

28

27

26

NC

LCAS

UCAS

OE

A9

A8

A7

A6

A1

A6

A5

A2

A5

A4

A3

A4

V

CC

SS

(Top view)

Pin Description

Pin name

Function

Address input

— Row/Refresh address A0 to A9

A0 to A9

— Column address

Data input/Data output

Row address strobe

A0 to A9

I/O0 to I/O15

RAS

UCAS, LCAS Column address strobe

WE

OE

V_CC

V_SS

NC

Read/Write enable

Output enable

Power supply

Ground

No connection

Data Sheet E0154H10

3

HM5118165 Series

Block Diagram

RAS UCAS LCAS

WE

OE

Timing and control

A0

Column decoder

1M array

A1

to

Column

address

buffers

•

A9

I/O0

to

I/O15

I/O buffers

•

Row

address

buffers

Data Sheet E0154H10

4

HM5118165 Series

Truth Table

RAS

LCAS

UCAS

WE

D

OE

Output

Open

Valid

Operation

H

D

L

D

H

L

D

Standby

Lower byte Read cycle

Upper byte

L

H

L

H

L

H

L

Valid

L

H

L

Valid

Word

L

H

L

L^*2

D

Open

Lower byte Early write cycle

Upper byte

L

H

L

L*²

H to L

D

L

D

Word

L

H

L

H

Undefined Lower byte Delayed write cycle

Undefined Upper byte

L

H

L

H

L

H

Undefined Word

L

H

L

L to H

D

Valid

Open

Lower byte Read-modify-write cycle

L

H

L

Upper byte

Word

L

H

L

H

L

Word

RAS-only refresh cycle

H to L

L

D

CAS-before-RAS refresh cycle or

Self refresh cycle (L-version)

H

L

D

L

D

L

H

Read cycle (Output disabled)

Notes: 1. H: High (inactive) L: Low (active) D: H or L

2. t_WCS≥ 0 ns Early write cycle

t_WCS< 0 ns Delayed write cycle

3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by the earliest of

UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However

write OPERATION and output High-Z control are done independently by each UCAS, LCAS.

ex. if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected.

Data Sheet E0154H10

5

HM5118165 Series

Absolute Maximum Ratings

Parameter

Symbol

V_T

Value

Unit

V

Voltage on any pin relative to V_SS

Supply voltage relative to V_SS

Short circuit output current

Power dissipation

–1.0 to +7.0

50

V_CC

V

Iout

P_T

mA

W

1.0

Operating temperature

Storage temperature

Topr

Tstg

0 to +70

–55 to +125

°C

Recommended DC Operating Conditions (Ta = 0 to +70°C)

Parameter

Symbol

V_CC

Min

4.5

Typ

5.0

—

Max

5.5

6.5

0.8

Unit

Notes

Supply voltage

V

1, 2

1

Input high voltage

Input low voltage

V_IH

2.4

V_IL

–1.0

—

1

Notes: 1. All voltage referred to V_SS

2. The supply voltage with all V_CCpins must be on the same level. The supply voltage with all V_SSpins

must be on the same level.

DC Characteristics (Ta = 0 to +70°C, V_CC= 5 V ± 10%, V_SS= 0 V)

HM5118165

-5

-6

-7

Parameter

Symbol Min Max Min Max Min Max Unit

Test conditions

Operating current*^1,*²

I_CC1

I_CC2

—

200 —

170 — 150 mA

t_RC= min

Standby current

2

—

2

—

2

mA

TTL interface

RAS, UCAS, LCAS = V_IH

Dout = High-Z

—

1

—

1

—

1

mA

CMOS interface

RAS, UCAS,

LCAS ≥ V_CC– 0.2 V

Dout = High-Z

Standby current

(L-version)

I_CC2

150 —

150 — 150 µA

CMOS interface

RAS, UCAS,

LCAS ≥ V_CC– 0.2 V

Dout = High-Z

Data Sheet E0154H10

6

HM5118165 Series

DC Characteristics (Ta = 0 to +70°C, V_CC= 5 V ± 10%, V_SS= 0 V) (cont.)

HM5118165

-5 -6

Symbol Min Max Min Max Min Max Unit

-7

Parameter

Test conditions

RAS-only refresh current*²

Standby current*¹

I_CC3

I_CC5

—

200 —

170 — 150 mA

mA

t_RC= min

5

—

5

—

5

RAS = V_IH,

UCAS, LCAS = V_IL

Dout = enable

CAS-before-RAS refresh

current

I_CC6

—

190 —

170 — 150 mA

t_RC= min

EDO page mode current*^1,*³I_CC7

—

185 —

500 —

165 — 145 mA

500 — 500 µA

t_HPC= min

Battery backup current*⁴

(Standby with CBR refresh)

(L-version)

I_CC10

CMOS interface

Dout = High-Z

CBR refresh: t_RC= 125

µs

t

_RAS≤ 0.3 µs

Self refresh mode current

(L-version)

I_CC11

—

300 —

300 — 300 µA

CMOS interface

RAS, UCAS, LCAS ≤ 0.2

V

Dout = High-Z

Input leakage current

Output leakage current

I_LI

–10 10 –10 10 –10 10 µA

0 V ≤ Vin ≤ 7 V

I_LO

0 V ≤ Vout ≤ 7 V

Dout = disable

Output high voltage

Output low voltage

V_OH

V_OL

2.4 V_CC2.4 V_CC2.4 V_CC

0.4 0.4 0.4

V

High Iout = –2 mA

Low Iout = 2 mA

0

Notes: 1. I_CCdepends on output load condition when the device is selected. I_CCmax is specified at the output

open condition.

2. Address can be changed once or less while RAS = V_IL.

3. Address can be changed once or less while UCAS and LCAS = V_IH.

4. V_IH≥ V_CC– 0.2 V, 0 V ≤ V_IL≤ 0.2 V.

Capacitance (Ta = 25°C, V_CC= 5 V ± 10%)

Parameter

Symbol

C_I1

Typ

—

Max

Unit

pF

Notes

Input capacitance (Address)

Input capacitance (Clocks)

Output capacitance (Data-in, Data-out)

5

7

1

C_I2

—

pF

1

C_I/O

—

pF

1, 2

Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.

2. RAS, UCAS and LCAS = V_IHto disable Dout.

Data Sheet E0154H10

7

HM5118165 Series

AC Characteristics (Ta = 0 to +70°C, V_CC= 5 V ± 10%, V_SS= 0 V)*^1,*^2,*^18,*^19,*²⁰

Test Conditions

•

Input rise and fall time: 2 ns

Input levels: 0 V, 3.0 V

Input timing reference levels: 0.8 V, 2.4 V

Output timing reference levels: 0.8 V, 2.0 V

Output load: 1 TTL gate + C_L(100 pF) (Including scope and jig)

Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)

HM5118165

-5

-6

-7

Parameter

Symbol Min Max Min Max Min Max Unit

Notes

Random read or write cycle time

RAS precharge time

CAS precharge time

RAS pulse width

t_RC

84

30

7

—

104

40

—

124

50

—

ns

t_RP

t_CP

10

13

t_RAS

t_CAS

t_ASR

t_RAH

t_ASC

t_CAH

t_RCD

50

7

10000 60

10000 10

10000 70

10000 13

10000 ns

CAS pulse width

Row address setup time

Row address hold time

Column address setup time

Column address hold time

RAS to CAS delay time

0

—

37

25

—

50

0

—

45

30

—

50

0

—

52

35

—

50

ns

7

10

0

10

0

21

3

7

10

14

12

13

40

5

13

14

12

13

45

5

11

9

RAS to column address delay time t_RAD

4

RAS hold time

t_RSH

t_CSH

t_CRP

t_OED

t_DZO

t_DZC

t_T

10

35

5

CAS hold time

23

22

5

CAS to RAS precharge time

OE to Din delay time

OE delay time from Din

CAS delay time from Din

Transition time (rise and fall)

13

0

15

0

18

0

6

0

6

2

7

Data Sheet E0154H10

8

HM5118165 Series

Read Cycle

HM5118165

-5

-6

-7

Parameter

Symbol Min

Max Min

Max Unit

Notes

8, 9

Access time from RAS

Access time from CAS

Access time from address

Access time from OE

t_RAC

t_CAC

t_AA

—

0

50

13

25

13

—

0

60

15

30

15

—

0

70

18

35

18

—

ns

9, 10, 17

9, 11, 17

9

t_OEA

t_RCS

t_RCH

t_RCHR

Read command setup time

Read command hold time to CAS

21

0

12, 22

Read command hold time from

50

60

70

RAS

Read command hold time to RAS

t_RRH

0

—

13

—

13

—

0

—

15

—

15

—

0

—

15

—

15

—

ns

12

27

Column address to RAS lead time t_RAL

Column address to CAS lead time t_CAL

25

15

0

30

18

0

35

23

0

CAS to output in low-Z

t_CLZ

Output data hold time

t_OH

3

Output data hold time from OE

Output buffer turn-off time

Output buffer turn-off to OE

CAS to Din delay time

t_OHO

t_OFF

t_OEZ

t_CDD

t_OHR

t_OFR

t_WEZ

t_WED

t_RDD

t_RNCD

3

—

13

3

—

15

3

—

18

3

13, 27

13

5

Output data hold time from RAS

Output buffer turn-off to RAS

Output buffer turn-off to WE

WE to Din delay time

27

—

13

50

—

15

60

—

18

70

27

RAS to Din delay time

RAS next CAS delay time

Data Sheet E0154H10

9

HM5118165 Series

Write Cycle

HM5118165

-5

-6

-7

Parameter

Symbol Min

Max Min

Max Unit

Notes

14, 21

21

Write command setup time

Write command hold time

Write command pulse width

Write command to RAS lead time

Write command to CAS lead time

Data-in setup time

t_WCS

t_WCH

t_WP

0

7

0

7

—

0

—

0

—

ns

10

0

13

10

13

0

t_RWL

t_CWL

t_DS

23

15, 23

Data-in hold time

t_DH

10

13

Read-Modify-Write Cycle

-5

-6

-7

Parameter

Symbol Min

Max Min

Max Unit

Notes

Read-modify-write cycle time

RAS to WE delay time

CAS to WE delay time

t_RWC

t_RWD

t_CWD

111

67

30

42

13

—

135

79

34

49

15

—

161

92

40

57

18

—

ns

14

Column address to WE delay time t_AWD

OE hold time from WE

t_OEH

Refresh Cycle

HM5118165

-5

-6

-7

Parameter

Symbol Min

Max Min

Max Unit

Notes

21

CAS setup time (CBR refresh cycle) t_CSR

CAS hold time (CBR refresh cycle) t_CHR

5

7

5

—

5

—

5

—

ns

10

5

10

5

22

RAS precharge to CAS hold time

t_RPC

21

Data Sheet E0154H10

10

HM5118165 Series

EDO Page Mode Cycle

HM5118165

-5

-6

-7

Min Max

30

Parameter

Symbol Min Max

Min Max

Unit

Notes

25

EDO page mode cycle time

t_HPC

20

—

28

3

—

25

100000 —

—

ns

EDO page mode RAS pulse width t_RASP

Access time from CAS precharge t_CPA

100000 — 100000 ns

16

28

—

35

3

35

—

40

3

40

—

ns

9, 17, 22

RAS hold time from CAS precharge t_CPRH

Output data hold time from CAS low t_DOH

9

CAS hold time referred OE

CAS to OE setup time

t_COL

7

10

5

13

5

t_COP

t_RCHC

5

Read command hold time from

28

35

40

CAS precharge

EDO Page Mode Read-Modify-Write Cycle

HM5118165

-5

-6

-7

Parameter

Symbol Min

Max Min

Max Unit

Notes

EDO page mode read-modify-write t_HPRWC

cycle time

57

—

68

—

79

—

ns

WE delay time from CAS precharge t_CPW

45

—

54

—

62

—

ns

14, 22

Refresh

Parameter

Symbol

t_REF

Max

16

Unit

ms

Note

Refresh period

1024 cycles

Refresh period (L-version)

t_REF

128

ms

Data Sheet E0154H10

11

HM5118165 Series

Self Refresh Mode (L-version)

HM5118165L

-5

-6

-7

Parameter

Symbol Min

Max Min

Max Unit

Notes

RAS pulse width (self refresh)

t_RASS

100

—

100

—

100

—

µs

28, 29, 30,

31

RAS precharge time (self refresh) t_RPS

CAS hold time (self refresh) t_CHS

90

—

110

–50

—

130

–50

—

ns

–50

Notes: 1. AC measurements assume t_T= 2 ns.

2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization

cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh).

3. Operation with the t_RCD(max) limit insures that t_RAC(max) can be met, t_RCD(max) is specified as a

reference point only; if t_RCD≥ t_RAD(max) + t_AA(max) – t_CAC(max), then access time is controlled

exclusively by t_CAC

.

4. Operation with the t_RAD(max) limit insures that t_RAC(max) can be met, t_RAD(max) is specified as a

reference point only; if t_RADis greater than the specified t_RAD(max) limit, then access time is

controlled exclusively by t_AA.

5. Either t_OEDor t_CDDmust be satisfied.

6. Either t_DZOor t_DZCmust be satisfied.

7. V_IH(min) and V_IL(max) are reference levels for measuring timing of input signals. Also, transition

times are measured between V_IH(min) and V_IL(max).

8. Assumes that t_RCD≤ t_RCD(max) and t_RAD≤ t_RAD(max). If t_RCDor t_RADis greater than the maximum

recommended value shown in this table, t_RACexceeds the value shown.

9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.

10. Assumes that t_RCD≥ t_RCD(max) and t_RCD+ t_CAC(max) ≥ t_RAD+ t_AA(max).

11. Assumes that t_RAD≥ t_RAD(max) and t_RCD+ t_CAC(max) ≤ t_RAD+ t_AA(max).

12. Either t_RCHor t_RRHmust be satisfied for a read cycles.

13. t_OFF(max) and t_OEZ(max) define the time at which the outputs achieve the open circuit condition and

are not referred to output voltage levels.

14. t_WCS, t_RWD, t_CWD, t_AWDand t_CPWare not restrictive operating parameters. They are included in the data

sheet as electrical characteristics only; if t_WCS≥ t_WCS(min), the cycle is an early write cycle and the

data out pin will remain open circuit (high impedance) throughout the entire cycle; if t_RWD≥ t_RWD

(min), t_CWD≥ t_CWD(min), and t_AWD≥ t_AWD(min), or t_CWD≥ t_CWD(min), t_AWD≥ t_AWD(min) and t_CPW≥ t_CPW

(min), the cycle is a read-modify-write and the data output will contain data read from the selected

cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access

time) is indeterminate.

15. These parameters are referred to UCAS and LCAS leading edge in early write cycles and to WE

leading edge in delayed write or read-modify-write cycles.

16. t_RASPdefines RAS pulse width in EDO page mode cycles.

17. Access time is determined by the longest among t_AA, t_CACand t_CPA

.

18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to

the device.

19. When both UCAS and LCAS go low at the same time, all 16-bit data are written into the device.

UCAS and LCAS cannot be staggered within the same write/read cycles.

Data Sheet E0154H10

12

HM5118165 Series

20 All the V_CCand V_SSpins shall be supplied with the same voltages.

21. t_ASC, t_CAH, t_RCS, t_WCS, t_WCH, t_CSRand t_RPCare determined by the earlier falling edge of UCAS or LCAS.

22. t_CRP, t_CHR, t_RCH, t_CPAand t_CPWare determined by the later rising edge of UCAS or LCAS.

23. t_CWL, t_DH, t_DSand t_CSHshould be satisfied by both UCAS and LCAS.

24. t_CPis determined by the time that both UCAS and LCAS are high.

25. t_HPC(min) can be achieved during a series of EDO page mode write cycles or EDO page mode read

cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page

mode mix cycle (1), (2)), minimum value of CAS cycle (t_CAS+ t_CP+ 2 t_T) becomes greater than the

specified t_HPC(min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO

page mode mix cycle (1) and (2).

26. When output buffers are enabled once, sustain the low impedance state until valid data is obtained.

When output buffer is turned on and off within a very short time, generally it causes large V_CC/V_SS

line noise, which causes to degrade V_IHmin/V_ILmax level.

27. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold

time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS

between t_OHRand t_OH, and between t_OFRand t_OFF

.

28. Please do not use t_RASStiming, 10 µs ≤ t_RASS≤ 100 µs. During this period, the device is in transition

state from normal operation mode to self refresh mode. If t_RASS≥ 100 µs, then RAS precharge time

should use t_RPSinstead of t_RP.

29. If you use distributed CBR refresh mode with 15.6 µs interval in normal read/write cycle, CBR

refresh should be executed within 15.6 µs immediately after exiting from and before entering into

self refresh mode.

30. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 1024 cycles of

distributed CBR refresh with 15.6 µs interval should be executed within 16 ms immediately after

exiting from and before entering into the self refresh mode.

31. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self

fresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again.

32. XXX: H or L (H: V_IH(min) ≤ V_IN≤ V_IH(max), L: V_IL(min) ≤ V ≤ V_IL(max))

IN

///////: Invalid Dout

When the address, clock and input pins are not described on timing waveforms, their pins must be

applied V_IHor V_IL.

Data Sheet E0154H10

13

HM5118165 Series

Notes concerning 2CAS control

Please do not separate the UCAS/LCAS operation timing intentionally. However skew between

UCAS/LCAS are allowed under the following conditions.

1. Each of the UCAS/LCAS should satisfy the timing specifications individually.

2. Different operation mode for upper/lower byte is not allowed; such as following.

RAS

Delayed write

UCAS

Early write

LCAS

WE

3. Closely separated upper/lower byte control is not allowed. However when the condition (t_CP≤ t_UL) is

satisfied, EDO page mode can be performed.

RAS

UCAS

LCAS

t

UL

4. Byte control operation by remaining UCAS or LCAS high is guaranteed.

Data Sheet E0154H10

14

HM5118165 Series

Timing Waveforms*³²

Read Cycle

t

RC

t

RAS

RP

RAS

t

CSH

CRP

t

RCD

RSH

CAS

t

T

UCAS

LCAS

t

RAD

RAL

CAL

t

CAH

ASR

Row

ASC

t

RAH

Address

Column

t

RRH

t

RCHR

t

RCH

CDD

t

RCS

WE

Din

OE

t

WED

t

DZC

t

RDD

High-Z

t

OED

DZO

OEA

t

OEZ

t

OHO

t

CAC

t

OFF

t

AA

t

OH

t

RAC

OFR

t

CLZ

OHR

t

WEZ

Dout

Data Sheet E0154H10

15

HM5118165 Series

Early Write Cycle

t_RC

t_RAS

t_RP

RAS

t_CSH

t_CRP

t_RCD

t_RSH

t_CAS

t_T

UCAS

LCAS

t_ASRt_RAH

t_ASC

t_CAH

Row

Column

Address

t_WCS

t_WCH

WE

t_DS

t_DH

Din

High-Z*

Dout

t

(min)

WCS

*

Data Sheet E0154H10

16

HM5118165 Series

Delayed Write Cycle*¹⁸

t

RC

t

RAS

RP

RAS

t

CRP

CSH

t

RCD

RSH

CAS

t

T

UCAS

LCAS

t

CAH

ASR

RAH

ASC

Row

Column

Address

t

CWL

RWL

WP

t

RCS

WE

t

DH

DZC

DS

High-Z

Din

t

OEH

DZO

t

OED

OE

t

OEZ

t

CLZ

High-Z

Dout

Invalid Dout

Data Sheet E0154H10

17

HM5118165 Series

Read-Modify-Write Cycle*¹⁸

t

RWC

RAS

t

RP

RAS

t

T

t

CRP

RCD

CAS

UCAS

LCAS

t

RAD

t

CAH

ASR

RAH

ASC

Address

Row

Column

t

CWD

CWL

t

RCS

AWD

RWD

RWL

t

WP

WE

Din

OE

t

DH

DZC

t

DS

High-Z

Din

t

OED

t

OEH

t

DZO

t

OEA

t

CAC

t

OEZ

t

AA

t

RAC

OHO

High-Z

Dout

CLZ

Data Sheet E0154H10

18

HM5118165 Series

RAS-Only Refresh Cycle

t

RC

t

RAS

RP

RAS

t

T

t

CRP

RPC

UCAS

LCAS

t

RAH

ASR

Address

Row

t

OFR

t

OFF

High-Z

Dout

Data Sheet E0154H10

19

HM5118165 Series

CAS-Before-RAS Refresh Cycle

t

RC

t

RP

RAS

RP

RAS

t

T

t

CRP

RPC

CP

RPC

CP

t

CHR

CSR

CHR

CSR

UCAS

LCAS

Address

t

OFR

t

OFF

High-Z

Dout

Data Sheet E0154H10

20

HM5118165 Series

Hidden Refresh Cycle

t

RC

t

RP

RAS

RP

RAS

RP

RAS

t

T

t

CRP

RSH

CHR

t

RCD

UCAS

LCAS

t

RAL

RAD

t

CAH

RAH

ASR

ASC

Address

Row

Column

t

RRH

t

RCS

DZC

t

RCH

WE

t

WED

t

CDD

RDD

High-Z

Din

t

OED

DZO

t

OEA

OE

t

OEZ

t

CAC

t

WEZ

OHO

t

AA

t

RAC

OFF

OH

t

CLZ

Dout

t

OFR

t

OHR

Data Sheet E0154H10

21

HM5118165 Series

EDO Page Mode Read Cycle

t

RP

t

RNCD

t

HPC

t

RASP

RAS

t

CRP

HPC

t

HPC

t

CPRH

CP

t

T

CSH

t

CP

t

CP

t

RSH

t

CAS

UCAS

LCAS

CAS

t

RCHC

t

RCHR

t_RCS

t

RRH

RCH

t_RCS

t_RCH

WE

t

RAL

t

CAH

t

t_CAH

WED

t_ASC

t_CAH

t_RAH

ASC

t_ASC

t_ASR

Address

Row

Column 1

Column 2

t

Column 3

t

CAL

Column 4

t

CAL

t

RDD

CDD

t

DZC

High-Z

Din

t

DZO

COP

COL

t

OED

OE

t

OFR

CPA

t

CPA

t

OEA

t

CPA

AA

t

OHR

OEZ

AA

t

OEZ

AA

t

CAC

t

CAC

t

OEZ

t

OHO

CAC

AA

t

CAC

WEZ

OHO

OFF

OH

t_OEA

t

RAC

OEA

t

DOH

t

OHO

Dout

Dout 1

Dout 2

Dout 3

Dout 4

Data Sheet E0154H10

22

HM5118165 Series

EDO Page Mode Read Cycle (2CAS)

t

RP

t

RNCD

t

RASP

RAS

t

HPC

CRP

HPC

t

T

CSH

t

CP

t

CP

t

RSH

t

CAS

LCAS

UCAS

CAS

t

CAS

t

RCHC

t

t_RCS

RRH

RCH

WE

t

RAL

t

WED

t

CAH

t_ASC

t_CAH

t

t_CAH

t_ASC

t_{RAH ASC}

t_ASC

t_ASR

Address

Row

Column 1

t

Column 2

t

Column 3

t

CAL

Column 4

CAL

t

RDD

t

CAL

t

DZC

CDD

High-Z

Din

t

DZO

COP

COL

t

OED

OE

t

OFR

CPA

t

CPA

t

OEA

t

OHR

OEZ

AA

t

OEZ

AA

t

CAC

t

OEZ

t

OHO

AA

t

CAC

OHO

OFF

OH

t

DOH

OEA

t

RAC

t

OHO

L Dout

U Dout

Dout 1

Dout 2

Dout 4

t

CPA

AA

t

OEA

t

CAC

Dout 4

Dout 1

Dout 3

Data Sheet E0154H10

23

HM5118165 Series

EDO Page Mode Early Write Cycle

t_RASP

t_RP

RAS

t_T

t_CSH

t_HPC

t_RSH

t_CAS

t_CP

t_CAS

t_CP

t_CRP

t_CAS

t_RCD

UCAS

LCAS

t_RAH

t_ASR

t_ASCt_CAH

t_ASC

t_CAH

t_ASC

Row

Column 1

Column 2

Column N

Address

t_WCH

t_WCS

t_WCSt_WCH

WE

t_DS

t_DH

t_DS

t_DH

t_DS

t_DH

Din 1

Din 2

Din N

Din

High-Z*

Dout

t

(min)

WCS

*

WCS

Data Sheet E0154H10

24

HM5118165 Series

EDO Page Mode Delayed Write Cycle*¹⁸

t

RASP

t

RP

RAS

t

CP

CRP

T

CP

t

CSH

HPC

RSH

CAS

t

CAS

RCD

CAS

UCAS

LCAS

t

RAD

t

ASR

ASC

t

ASC

t

ASC

t

RAH

CAH

Row

Column 1

Column 2

Column N

Address

t

CWL

t

CWL

t

RWL

t

RCS

WE

t

WP

t

DZC DS

t

DH

Din

1

Din

2

Din

N

Din

t

DZO

OED

t

OED

t

OEH

OE

t

CLZ

t

OEZ

High-Z

Dout

Invalid Dout

Data Sheet E0154H10

25

HM5118165 Series

EDO Page Mode Read-Modify-Write Cycle*¹⁸

t

RASP

t

RP

RAS

t

T

HPRWC

t

RSH

CAS

t

CRP

CP

t

CAS

RCD

CAS

UCAS

LCAS

t

RAD

t

ASC

t

CAH

ASR

ASC

RAH

ASC

t

CAH

Row

Column 1

Column 2

Column N

Address

t

CWL

RWD

AWD

CWL

CPW

AWD

CWL

CPW

AWD

t

RWL

t

CWD

RCS

CWD

RCS

WE

t

WP

t

DS

RCS

DZO

WP

DS

WP

t

DS

t

DZC

t

DH

Din

1

Din

2

Din

N

Din

t

OED

t

DZO

t

OEH

OE

t

OHO

t

OEA

CAC

OEA

CAC

OEA

CAC

t

AA

t

CPA

t

RAC

t

OEZ

t

OEZ

CLZ

High-Z

Dout

Dout 1

Dout 2

Dout N

Data Sheet E0154H10

26

HM5118165 Series

EDO Page Mode Mix Cycle (1)

t

RP

t

RASP

RAS

t

CRP

t

T

t

CP

t

CAS

UCAS

CAS

LCAS

t

CSH

t

RSH

t_RCD

t

t_RCS

RRH

RCH

t_WCS

t_RCS

t_WCH

t

CPW

AWD

t_WP

WE

t

RAL

t_CAH

t_ASC

t_RAH

t_ASC

t

t_ASCt_CAH

t_CAH

CAH

t_ASC

t_ASR

Address

Row

Column 1

Column 2

t

Column 3

Column 4

CAL

t

RDD

t

CAL

t

CDD

DH

t

DH

DS

t

DS

High-Z

Din

Din 1

Din 3

t

OED

t

WED

OE

t

OFR

WEZ

t

CPA

t

CPA

t

AA

t

AA

t

OEZ

t

OEA

AA

CAC

OHO

t

CAC

t_OHO

Dout 3

t

OEA

CAC

t

OFF

OH

t

DOH

Dout

Dout 2

Dout 4

Data Sheet E0154H10

27

HM5118165 Series

EDO Page Mode Mix Cycle (2)

t

RP

t

RNCD

t

RASP

RAS

t

CRP

t

T

t

CSH

t

CP

t

CP

t

CAS

UCAS

LCAS

CAS

t_RCD

t_RCS

t_RCHR

t

RSH

t

RCS

t

RRH

t_WCS

t_WCH

t

RCS

t_RCH

t

RCH

t_WP

t

CPW

WE

t

RAL

t_ASC

t_RAH

t

CAH

t_ASC

t_ASCt_CAH

Column 2

t_CAH

t_ASC

t_ASR

Address

Row

Column 1

Column 3

t

Column 4

t

CAL

t

DS

t

RDD

CDD

t

DH

DS

DH

High-Z

Din

Din 2

Din 3

t

OED

t

COP

OED

t

WED

t

COL

OE

t

OFR

WEZ

t

OEA

t

CPA

t

AA

t

CPA

t

OEA

AA

OEZ

t

AA

OEZ

t

CAC

t

CAC

OEZ

OHO

t

RAC

CAC

t

OEA

t

OFF

OH

t

OHO

Dout

Dout 1

Dout 4

Dout 3

Data Sheet E0154H10

28

HM5118165 Series

Self Refresh Cycle (L-version)*^{28, 29, 30, 31}

t

RASS

RP

RPS

RAS

t

T

t

CRP

RPC

CP

t

CSR

t

CHS

UCAS

LCAS

t

OFR

t

OFF

High-Z

Dout

Data Sheet E0154H10

29

HM5118165 Series

Package Dimensions

HM5118165J/LJ Series (CP-42D)

Unit: mm

27.06

27.43 Max

22

42

21

1

0.74

1.30 Max

1.27

9.40 ± 0.25

CP-42D

Conforms

—

Weight (reference value) 1.75 g

0.43 ± 0.10

0.41 ± 0.08

0.10

Hitachi Code

JEDEC

EIAJ

Dimension including the plating thickness

Base material dimension

Data Sheet E0154H10

30

HM5118165 Series

HM5118165TT/LTT Series (TTP-50/44DC)

Unit: mm

20.95

21.35 Max

50

40 36

26

25

11 15

0.80

1

0.80

0.27 ± 0.07

0.25 ± 0.05

M

0.13

11.76 ± 0.20

1.15 Max

0° – 5°

0.50 ± 0.10

3.20

0.10

Hitachi Code

JEDEC

EIAJ

TTP-50/44DC

Conforms

—

Dimension including the plating thickness

Base material dimension

Weight (reference value) 0.50 g

Data Sheet E0154H10

31

HM5118165 Series

Cautions

1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.’s or any

third party’s patent, copyright, trademark, or other intellectual property rights for information contained in

this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party’s

rights, including intellectual property rights, in connection with use of the information contained in this

document.

2. Products and product specifications may be subject to change without notice. Confirm that you have

received the latest product standards or specifications before final design, purchase or use.

3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.

However, contact Elpida Memory, Inc. before using the product in an application that demands especially

high quality and reliability or where its failure or malfunction may directly threaten human life or cause

risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,

traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc.

particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation

conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage

when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally

foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as

fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury,

fire or other consequential damage due to operation of the Elpida Memory, Inc. product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without

written approval from Elpida Memory, Inc..

7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc.

semiconductor products.

Data Sheet E0154H10

32


型号：	HM5118165TT-6
厂家：	ELPIDA MEMORY
描述：	16 M EDO DRAM (1-Mword x 16-bit) 1 k Refresh 16M的EDO DRAM （ 1 - Mword ×16位）， 1千刷新存储内存集成电路光电二极管动态存储器
文件：	总32页 (文件大小：578K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HM5118165TT-6 [ELPIDA]

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