HM534253BZ-6 [ELPIDA]
1 M VRAM (256-kword x 4-bit); 1M的VRAM （ 256千字×4位）
| 型号： | HM534253BZ-6 |
| 厂家： | 
ELPIDA MEMORY |
| 描述： | 1 M VRAM (256-kword x 4-bit) |
| 文件： | 总45页 (文件大小：448K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM534253B Series
1 M VRAM (256-kword × 4-bit)
E0165H10 (Ver. 1.0)
(Previous ADE-203-204D (Z))
Jul. 6, 2001 (K)
Description
The HM534253B is a 1-Mbit multiport video RAM equipped with a 256-kword × 4-bit dynamic RAM and a
512-word × 4-bit SAM (serial access memory). Its RAM and SAM operate independently and
asynchronously. It can transfer data between RAM and SAM. In addition, it has two modes to realize fast
writing in RAM. Block write and flash write modes clear the data of 4-word × 4-bit and the data of one row
(512-word × 4-bit) respectively in one cycle of RAM. And the HM534253B makes split transfer cycle
possible by dividing SAM into two split buffers equipped with 256-word × 4-bit each. This cycle can transfer
data to SAM which is not active, and enables a continuous serial access.
Features
•
Multiport organization
Asynchronous and simultaneous operation of RAM and SAM capability
RAM: 256-kword × 4-bit
SAM: 512-word × 4-bit
•
•
•
Access time
RAM: 60 ns/70 ns/80 ns/100 ns max
SAM: 20 ns/22 ns/25 ns/25 ns max
Cycle time
RAM: 125 ns/135 ns/150 ns/180 ns min
SAM: 25 ns/25 ns/30 ns/30 ns min
Low power
Active
RAM: 413 mW max
SAM: 275 mW max
Standby 38.5 mW max
•
•
•
•
High-speed page mode capability
Mask write mode capability
Bidirectional data transfer cycle between RAM and SAM capability
Split transfer cycle capability
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
HM534253B Series
•
•
•
Block write mode capability
Flash write mode capability
3 variations of refresh (8 ms/512 cycles)
RAS-only refresh
CAS-before-RAS refresh
Hidden refresh
•
TTL compatible
Ordering Information
Type No.
Access Time
Package
HM534253BJ-6
HM534253BJ-7
HM534253BJ-8
HM534253BJ-10
60 ns
70 ns
80 ns
100 ns
400-mil 28-pin plastic SOJ (CP-28D)
HM534253BZ-6
HM534253BZ-7
HM534253BZ-8
HM534253BZ-10
60 ns
70 ns
80 ns
100 ns
400-mil 28-pin plastic ZIP (ZP-28)
Pin Arrangement
HM534253BZ Series
HM534253BJ Series
1
3
5
7
9
DSF
I/O3
SI/O2
VSS
SC
SI/O0
SI/O1
DT/OE
I/O0
I/O1
WE
NC
RAS
A8
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VSS
SI/O3
SI/O2
SE
I/O3
I/O2
DSF
CAS
QSF
A0
I/O2
SE
SI/O3
SC
SI/O1 10
I/O0 12
WE 14
RAS 16
A6 18
2
4
6
8
SI/O0
11 DT/OE
13 I/O1
15 NC
17 A8
19 A5
21 VCC
23 A3
9
10
11
12
13
14
A4 20
A7 22
A2 24
A0 26
A6
A5
A4
VCC
A1
A2
A3
A7
25 A1
27 QSF
CAS 28
(Top view)
(Bottom view)
Data Sheet E0165H10
2
HM534253B Series
Pin Description
Pin Name
A0 – A8
I/O0 – I/O3
SI/O0 – SI/O3
RAS
Function
Address inputs
RAM port data inputs/outputs
SAM port data inputs/outputs
Row address strobe
Column address strobe
Write enable
CAS
WE
DT/OE
SC
Data transfer/output enable
Serial clock
SE
SAM port enable
DSF
Special function input flag
Special function output flag
Power supply
QSF
VCC
VSS
Ground
NC
No connection
Data Sheet E0165H10
3
HM534253B Series
Block Diagram
A0 – A8
Column Address
Row Address
Buffer
Refresh
Counter
Buffer
Serial Address
Counter
QSF
Row Decoder
Memory Array
Input Data
Control
Serial Output Serial Input
Buffer Buffer
SI/O0 – SI/O3
Input
Buffer
Output
Buffer
Timing Generator
I/O0 – I/O3
Data Sheet E0165H10
4
HM534253B Series
Pin Functions
RAS (input pin): RAS is a basic RAM signal. It is active in low level and standby in high level. Row
address and signals as shown in table 1 are input at the falling edge of RAS. The input level of these signals
determine the operation cycle of the HM534253B.
Table 1
Operation Cycles of the HM534253B
Input Level At The Falling Edge Of RAS
CAS
L
DT/OE WE
SE
X
L
DSF
X
L
DSF At The Falling Edge Of CAS
Operation Mode
CBR refresh
X
L
X
L
—
X
X
X
X
X
L
H
Write transfer
H
L
L
H
X
X
X
X
X
X
X
X
X
L
Pseudo transfer
Split write transfer
Read transfer
H
L
L
H
L
H
L
H
H
L
H
L
H
L
Split read transfer
Read/mask write
Mask block write
Flash write
H
H
H
H
H
H
H
H
L
L
H
X
L
H
L
H
L
H
H
H
H
Read/write
H
L
H
X
Block write
H
H
Color register read/write
Note: X: H or L.
CAS (input pin): Column address and DSF signals are fetched into chip at the falling edge of CAS, which
determines the operation mode of the HM534253B. CAS controls output impedance of I/O in RAM.
A0 – A8 (input pins): Row address is determined by A0 – A8 level at the falling edge of RAS. Column
address is determined by A0 – A8 level at the falling edge of CAS. In transfer cycles, row address is the
address on the word line which transfers data with SAM data register, and column address is the SAM start
address after transfer.
WE (input pin): WE pin has two functions at the falling edge of RAS and after. When WE is low at the
falling edge of RAS, the HM534253B turns to mask write mode. According to the I/O level at the time, write
on each I/O can be masked. (WE level at the falling edge of RAS don’t care in read cycle.) When WE is high
at the falling edge of RAS, a normal write cycle is executed. After that, WE switches read/write cycles as in a
standard DRAM. In a transfer cycle, the direction of transfer is determined by WE level at the falling edge of
RAS. When WE is low, data is transferred from SAM to RAM (data is written into RAM), and when WE is
high, data is transferred from RAM to SAM (data is read from RAM).
Data Sheet E0165H10
5
HM534253B Series
I/O0 – I/O3 (input/output pins): I/O pins function as mask data at the falling edge of RAS (in mask write
mode). Data is written only to high I/O pins. Data on low I/O pins are masked and internal data are retained.
After that, they function as input/output pins as those of a standard DRAM. In block write cycle, they
function as address mask data at the falling edges of CAS.
DT/OE (input pin): D T/OE pin functions as DT (data transfer) pin at the falling edge of RAS and as OE
(output enable) pin after that. When DT is low at the falling edge of RAS, this cycle becomes a transfer cycle.
When DT is high at the falling edge of RAS, RAM and SAM operate independently.
SC (input pin): SC is a basic SAM clock. In a serial read cycle, data outputs from an SI/O pin
synchronously with the rising edge of SC. In a serial write cycle, data on an SI/O pin at the rising edge of SC
is fetched into the SAM data register.
SE(input pin): SE pin activates SAM. When SE is high, SI/O is in the high impedance state in serial read
cycle and data on SI/O is not fetched into the SAM data register in serial write cycle. SE can be used as a
mask for serial write because internal pointer is incremented at the rising edge of SC.
SI/O0 – SI/O3 (input/output pins): SI/Os are input/output pins in SAM. Direction of input/output is
determined by the previous transfer cycle. When it was a read transfer cycle, SI/O outputs data. When it was
a pseudo transfer cycle or write transfer cycle, SI/O inputs data.
DSF (input pin): DSF is a special function data input flag pin. It is set to high at the falling edge of RAS
when new functions such as color register read/write, split transfer, and flash write, are used. DSF is set to
high at the falling edge of CAS when block write is executed.
QSF (output pin): QSF outputs data of address A8 in SAM. QSF is switched from low to high by accessing
address 255 in SAM and from high to low by accessing 511 address in SAM.
Data Sheet E0165H10
6
HM534253B Series
Operation of HM534253B
RAM Port Operation
RAM Read Cycle (DT/OE high, CAS high and DSF low at the falling edge of RAS, DSF low at the falling
edge of CAS)
Row address is entered at the RAS falling edge and column address at the CAS falling edge to the device as in
standard DRAM. Then, when WE is high and DT/OE is low while CAS is low, the selected address data
outputs through I/O pin. At the falling edge of RAS, DT/OE and CAS become high to distinguish RAM read
cycle from transfer cycle and CBR refresh cycle. Address access time (tAA) and RAS to column address delay
time (tRAD) specifications are added to enable high-speed page mode.
RAM Write Cycle (Early Write, Delayed Write, Read-Modify-Write) (DT/OE high, CAS high and DSF
low at the falling edge of RAS, DSF low at the falling edge of CAS)
•
Normal Mode Write Cycle (WE high at the falling edge of RAS)
When CAS and WE are set low after driving RAS low, a write cycle is executed and I/O data is written in
the selected addresses. When all 4 I/Os are written, WE should be high at the falling edge of RAS to
distinguish normal mode from mask write mode.
If WE is set low before the CAS falling edge, this cycle becomes an early write cycle and all I/O become
in high impedance. Data is entered at the CAS falling edge.
If WE is set low after the CAS falling edge, this cycle becomes a delayed write cycle. Data is input at the
WE falling. I/O does not become high impedance in this cycle, so data should be entered with OE in high.
If WE is set low after tCWD (min) and tAWD (min) after the CAS falling edge, this cycle becomes a read-
modify-write cycle and enables read/write at the same address in one cycle. In this cycle also, to avoid I/O
contention, data should be input after reading data and driving OE high.
•
Mask Write Mode (WE low at the falling edge of RAS)
If WE is set low at the falling edge of RAS, the cycle becomes a mask write mode which writes only to
selected I/O. Whether or not an I/O is written depends on I/O level (mask data) at the falling edge of
RAS. Then the data is written in high I/O pins and masked in low ones and internal data is retained. This
mask data is effective during the RAS cycle. So, in high-speed page mode, the mask data is retained
during the page access.
Data Sheet E0165H10
7
HM534253B Series
High-Speed Page Mode Cycle (DT/OE high, CAS high and DSF low at the falling edge of RAS)
High-speed page mode cycle reads/writes the data of the same row address at high speed by toggling CAS
while RAS is low. Its cycle time is one third of the random read/write cycle. In this cycle, read, write, and
block write cycles can be mixed. Note that address access time (tAA), RAS to column address delay time
(tRAD), and access time from CAS precharge (tACP) are added. In one RAS cycle, 512-word memory cells of the
same row address can be accessed. It is necessary to specify access frequency within tRASP max (100 µs).
Color Register Set/Read Cycle (CAS high, DT/OE high, WE high and DSF high at the falling edge of RAS)
In color register set cycle, color data is set to the internal color register used in flash write cycle or block write
cycle. 4 bits of internal color register are provided at each I/O. This register is composed of static circuits, so
once it is set, it retains the data until reset. Color register set cycle is just as same as the usual write cycle
except that DSF is set high at the falling edge of RAS, and read, early write and delayed write cycle can be
executed. In this cycle, the HM534253B refreshes the row address fetched at the falling edge of RAS.
Flash Write Cycle (CAS high, DT/OE high, WE low, and DSF high at the falling edge of RAS)
In a flash write cycle, a row of data (512-word × 4-bit) is cleared to 0 or 1 at each I/O according to the data of
color register mentioned before. It is also necessary to mask I/O in this cycle. When CAS and DT/OE are set
high, WE is low, and DSF is high at the falling edge of RAS, this cycle starts. Then, the row address to clear
is given to row address and mask data is given to I/O. Mask data is as same as that of a RAM write cycle.
High I/O is cleared, low I/O is not cleared and the internal data is retained. Cycle time is the same as those of
RAM read/write cycles, so all bits can be cleared in 1/512 of the usual cycle time. (See figure 1.)
Data Sheet E0165H10
8
HM534253B Series
Color Register Set Cycle
Flash Write Cycle
Flash Write Cycle
RAS
CAS
Address
Row
Xi
Xj
WE
DT/OE
DSF
I/O
*1
Color Data
*1
Execute flash write into each Execute flash write into
Set color register
I/O on row address Xi using
color resister.
each I/O on row address
Xj using color resister.
Note: 1. I/O Mask Data
Low: Mask
High: Non Mask
Figure 1 Use of Flash Write
Block Write Cycle (CAS high, DT/OE high and DSF low at the falling edge of RAS, DSF high at the falling
edge of CAS)
In a block write cycle, 4 columns of data (4-word × 4-bit) are cleared to 0 or 1 at each I/O according to the
data of color register. Column addresses A0 and A1 are disregarded. The data on I/Os and addresses can be
masked. I/O level at the falling edge of CAS determines the address to be cleared. (See figure 2.) In a page
mode cycle, mixed cycle of normal Read/Write and block write can be allowed by controlling DSF.
•
Normal Mode Block Write Cycle (WE high at the falling edge of RAS)
The data on 4 I/Os are all cleared when WE is high at the falling edge of RAS.
Mask Block Write Mode (WE low at the falling edge of RAS)
•
When WE is low at the falling edge of RAS, the HM534253B starts mask block write mode to clear the
data on an optional I/O. The mask data is the same as that of a RAM write cycle. High I/O is cleared, low
I/O is not cleared and the internal data is retained. The mask data is available in the RAS cycle. In page
mode block write cycle, the mask data is retained during the page access.
Data Sheet E0165H10
9
HM534253B Series
Color Register Set Cycle
Block Write Cycle
Block Write Cycle
RAS
CAS
Row
Row
Column A2–A8
Column A2–A8
Row
Address
*1
*1
WE
DT/OE
DSF
I/O
Address Mask
Color Data
Address Mask
*1
*1
Note: 1.
I/O
Mode
Mask
Non mask
WE
Low
High
I/O Mask Data
Don't care
I/O Mask Data
Low: Mask
High: Non Mask
Address Mask Data
Column0 (A0 = 0, A1 = 0) Mask Data
Column1 (A0 = 1, A1 = 0) Mask Data
Column2 (A0 = 0, A1 = 1) Mask Data
I/O0
I/O1
I/O2
Low: Mask
High: Non Mask
I/O3 Column3 (A0 = 1, A1 = 1) Mask Data
Figure 2 Use of Block Write
Transfer Operation
The HM534253B provides the read transfer cycle, split read transfer cycle,pseudo transfer cycle, write
transfer cycle, and split write transfer cycle as data transfer cycles. These transfer cycles are set by driving
CAS high and DT/OE low at the falling edge of RAS. They have following functions:
(1) Transfer data between row address and SAM data register (except for pseudo transfer cycle)
Read transfer cycle and split read transfer cycle: RAM to SAM
Write transfer cycle and split write transfer cycle: SAM to RAM
(2) Determine SI/O state (except for split read transfer cycle and split write transfer cycle)
Read transfer cycle: SI/O output
Pseudo transfer cycle and write transfer cycle: SI/O input
(3) Determine first SAM address to access after transferring at column address (SAM start address).
Data Sheet E0165H10
10
HM534253B Series
SAM start address must be determined by read transfer cycle or pseudo transfer cycle (split transfer cycle
isn’t available) before SAM access, after power on, and determined for each transfer cycle.
Read Transfer Cycle (CAS high, DT/OE low, WE high and DSF low at the falling edge of RAS)
This cycle becomes read transfer cycle by driving DT/OE low, WE high and DSF low at the falling edge of
RAS. The row address data (512 × 4 bits) determined by this cycle is transferred to SAM data register
synchronously at the rising edge of DT/OE. After the rising edge of DT/OE, the new address data outputs
from SAM start address determined by column address. In read transfer cycle, DT/OE must be risen to
transfer data from RAM to SAM.
This cycle can access SAM even during transfer (real time read transfer). In this case, the timing tSDD (min)
specified between the last SAM access before transfer and DT/OE rising edge and tSDH (min) specified
between the first SAM access and DT/OE rising edge must be satisfied. (See figure 3.)
When read transfer cycle is executed, SI/O becomes output state by first SAM access. Input must be set high
impedance before tSZS (min) of the first SAM access to avoid data contention.
RAS
CAS
Address
DT/OE
Xi
Yj
L
DSF
tSDD tSDH
SC
SI/O
Yj
Yj + 1
SAM Data before Transfer
SAM Data after Transfer
Figure 3 Real Time Read Transfer
Pseudo Transfer Cycle (CAS high, DT/OE low, WE low, SE high and DSF low at the falling edge of RAS)
Pseudo transfer cycle switches SI/O to input state and set SAM start address without data transfer to RAM.
This cycle starts when CAS is high, DT/OE low, WE low, SE high and DSF low at the falling edge of RAS.
Data should be input to SI/O later than tSID (min) after RAS becomes low to avoid data contention. SAM
access becomes enabled after tSRD (min) after RAS becomes high. In this cycle, SAM access is inhibited
during RAS low, therefore, SC must not be risen.
Write Transfer Cycle (CAS high, DT/OE low, WE low, SE low, and DSF low at the falling edge of RAS)
Data Sheet E0165H10
11
HM534253B Series
Write transfer cycle can transfer a row of data input by serial write cycle to RAM. The row address of data
transferred into RAM is determined by the address at the falling edge of RAS. The column address is
specified as the first address for serial write after terminating this cycle. Also in this cycle, SAM access
becomes enabled after tSRD (min) after RAS becomes high. SAM access is inhibited during RAS low. In this
period, SC must not be risen. Data transferred to SAM by read transfer cycle or split read transfer cycle can
be written to other addresses of RAM by write transfer cycle. However, the address to write data must be the
same MSB of row address (AX8) as that of the read transfer cycle. Figure 4 shows the example of row bit
data transfer. In case AX8 is 0, data cannot be transferred RAM address within the range of 100000000 to
111111111. Same as the case of AX8 = 1.
SAM
RAM
SAM
Possible
(Row address)
........
(Row address)
........
........
A0
A8
A0
A8
000000000
000000000
RAM
Impossible
011111111
100000000
011111111
100000000
RAM
SAM
RAM
SAM
111111111
111111111
(Read transfer cycle)
(Write transfer cycle)
Figure 4 Example of Row Bit Data Transfer
Split Read Transfer Cycle (CAS high, DT/OE low, WE high and DSF high at the falling edge of RAS)
To execute a continuous serial read by real time read transfer, the HM534253B must satisfy SC and DT/OE
timings and requires an external circuit to detect SAM last address. Split read transfer cycle makes it possible
to execute a continuous serial read without the above timing limitation. Figure 5 shows the block diagram for
a split transfer. SAMdata register (DR) consists of 2 split buffers, whose organizations are 256-word × 4-bit
each. Let us suppose that data is read from upper data register DR1 (The row address AX8 is 0 and SAM
address A8 is 1.). When split read transfer is executed setting row address AX8 0 and SAM start addresses
A0 to A7, 256-word × 4-bit data are transferred from RAM to the lower data register DR0 (SAM address A8
is 0) automatically. After data are read from data register DR1, data start to be read from SAM start addresses
of data register DR0. If the next split read transfer isn’t executed while data are read from data register DR0,
data start to be read from SAM start address 0 of DR1 after data are read from data register DR0. If split read
transfer is executed setting row address AX8 1 and SAM start addresses A0 to A7 while data are read from
data register DR1, 256-word × 4-bit data are transferred to data register DR2. After data are read from data
register DR1, data start to be read from SAM start addresses of data register DR2. If the next split read
transfer isn’t executed while data is read from data register DR2, data start to be read from SAM start address
0 of data register DR3 after data are read from data register DR2. In this time, SAM data is the one
transferred to data register DR3 finally while row address AX8 is 1. In split read data transfer, the SAM start
address A8 is automatically set in the data register which isn’t used.
The data on SAM address A8, which will be accessed next, outputs to QSF. QSF is switched from low to
high by accessing SAM last address 255 and from high to low by accessing address 511.
Data Sheet E0165H10
12
HM534253B Series
Split read transfer cycle is set when CAS is high, DT/OE is low, WE is high and DSF is high at the falling
edge of RAS. The cycle can be executed asyncronously with SC. However, tSTS (min) timing specified
between SC rising and RAS falling must be satisfied. SAM last address must be accessed, satisfying tRST
(min), tCST (min), and tAST (min) timings specified between RAS or CAS falling and column address. (See
figure 6.)
In split read transfer, SI/O isn't switched to output state. Therefore, read transfer must be executed to switch
SI/O to output state when the previous transfer cycle is pseudo transfer or write transfer cycle.
Memory
Array
Memory
Array
AX8 = 0
AX8 = 1
SAM I/O Buffer
SI/O
Figure 5 Block Diagram for Split Transfer
Data Sheet E0165H10
13
HM534253B Series
RAS
tSTS (min)
tRST (min)
CAS
tCST(min)
Yj
Address
Xi
tAST(min)
DT/OE
DSF
255
(511)
n
(n + 255)
511
SC
255 + Yj
(Yj)
(255)
Figure 6 Limitation in Split Transfer
Split Write Transfer Cycle (CAS high, DT/OE low, WE low and DSF high at the falling edge of RAS)
A continuous serial write cannot be executed because accessing SAM is inhibited during RAS low in write
transfer. Split write transfer cycle makes it possible. In this cycle, tSTS (min), t (min), tCST (min) and tAST
RST
(min) timings must be satisfied like split read transfer cycle. And it is impossible to switch SI/O to input state
in this cycle. If SI/O is in output state, pseudo transfer cycle should be executed to switch SI/O into input
state. Data transferred to SAM by read transfer cycle or split read transfer cycle can be written to other
addresses of RAM by split write transfer cycle. However, pseudo transfer cycle must be executed before split
write transfer cycle. And the MSB of row address (AX8) to write data must be the same as that of the read
transfer cycle or the split read transfer cycle.
SAM Port Operation
Serial Read Cycle
SAM port is in read mode when the previous data transfer cycle is read transfer cycle. Access is
synchronized with SC rising, and SAM data is output from SI/O. When SE is set high, SI/O becomes high
impedance, and the internal pointer is incremented by the SC rising. After indicating the last address (address
511), the internal pointer indicates address 0 at the next access.
Data Sheet E0165H10
14
HM534253B Series
Serial Write Cycle
If previous data transfer cycle is pseudo transfer cycle or write transfer cycle, SAM port goes into write mode.
In this cycle, SI/O data is fetched into data register at the SC rising edge like in the serial read cycle. If SE is
high, SI/O data isn’t fetched into data register. Internal pointer is incremented by the SC rising, so SE high
can be used as mask data for SAM. After indicating the last address (address 511), the internal pointer
indicates address 0 at the next access.
Refresh
RAM Refresh
RAM, which is composed of dynamic circuits, requires refresh to retain data. Refresh is executed by
accessing all 512 row addresses within 8 ms. There are three refresh cycles: (1) RAS-only refresh cycle, (2)
CAS-before-RAS (CBR) refresh cycle, and (3) Hidden refresh cycle. Besides them, the cycles which activate
RAS such as read/write cycles or transfer cycles can refresh the row address. Therefore, no refresh cycle is
required when all row addresses are accessed within 8 ms.
(1) RAS-Only Refresh Cycle: RAS-only refresh cycle is executed by activating only RAS cycle with CAS
fixed to high after inputting the row address (= refresh address) from external circuits. To distinguish this
cycle from data transfer cycle, DT/OE must be high at the falling edge of RAS.
(2) CBR Refresh Cycle: CBR refresh cycle is set by activating CAS before RAS. In this cycle, refresh
address need not to be input through external circuits because it is input through an internal refresh
counter. In this cycle, output is in high impedance and power dissipation is lowered because CAS circuits
don’t operate.
(3) Hidden Refresh Cycle: Hidden refresh cycle executes CBR refresh with the data output by reactivating
RAS when DT/OE and CAS keep low in normal RAM read cycles.
SAM Refresh
SAM parts (data register, shift resister and selector), organized as fully static circuitry, require no refresh.
Absolute Maximum Ratings
Parameter
Symbol
VT
Value
Unit
V
Note
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
–1.0 to +7.0
–0.5 to +7.0
50
1
1
VCC
V
Iout
PT
mA
W
1.0
Operating temperature
Storage temperature
Topr
Tstg
0 to +70
–55 to +125
°C
°C
Note: 1. Relative to VSS.
Data Sheet E0165H10
15
HM534253B Series
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
VCC
Min
4.5
Typ
5.0
—
Max
5.5
Unit
V
Notes
Supply voltage
Input high voltage
Input low voltage
1
1
1
VIH
2.4
–0.5*2
6.5
V
VIL
—
0.8
V
Notes: 1. All voltage referred to VSS
–3.0 V for pulse width ≤ 10 ns.
2
DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V)
HM534253B
-6
-7
-8
-10
Parameter Symbol Min Max Min Max Min Max Min Max Unit Test Conditions
Operating
current
ICC1
ICC7
—
—
75
—
—
70
—
—
60
—
—
55
95
mA RAS, CAS cycling SC = VIL,
t
RC = min
SE = VIH
125
120
100
mA
SE = VIL,
SC cycling
tSCC = min
Standby
current
ICC2
ICC8
—
—
7
—
—
7
—
—
7
—
—
7
mA RAS, CAS = VIH
SC = VIL,
SE = VIH
50
50
40
40
mA
SE = VIL,
SC cycling
tSCC = min
RAS-only
refresh
current
ICC3
—
—
—
—
—
—
75
—
—
—
—
—
—
70
—
—
—
—
—
—
60
—
—
—
—
—
—
55
95
65
mA RAS cycling
CAS = VIH
SC = VIL,
SE = VIH
tRC = min
ICC9
125
80
120
80
100
70
mA
SE = VIL,
SC cycling
tSCC = min
Page mode ICC4
current
mA CAS cycling
RAS = VIL
SC = VIL,
SE = VIH
tPC = min
ICC10
130
50
130
45
110
40
105 mA
SE = VIL,
SC cycling
tSCC = min
CAS-before- ICC5
RAS refresh
current
35
75
mA RAS cycling
RC = min
SC = VIL,
SE = VIH
t
ICC11
100
95
80
mA
SE = VIL,
SC cycling
tSCC = min
Data Sheet E0165H10
16
HM534253B Series
DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V) (cont)
HM534253B
-6 -7
Parameter Symbol Min Max Min Max Min Max Min Max Unit Test Conditions
-8
-10
Data
transfer
current
ICC6
ICC12
ILI
—
80
—
75
—
65
—
60
mA RAS, CAS cycling SC = VIL,
t
RC = min
SE = VIH
—
130
—
125
—
105
—
100 mA
SE = VIL,
SC cycling
tSCC = min
Input
leakage
current
–10 10
–10 10
–10 10
–10 10
–10 10
–10 10
–10 10
–10 10
µA
µA
Output
leakage
current
ILO
Output high VOH
voltage
2.4
—
—
2.4
—
—
2.4
—
—
2.4
—
—
V
V
IOH = –2 mA
IOL = 4.2 mA
Output low VOL
voltage
0.4
0.4
0.4
0.4
Notes: 1. ICC depends on output load condition when the device is selected. ICC max is specified at the output
open condition.
2. Address can be changed once while RAS is low and CAS is high.
Capacitance (Ta = 25°C, VCC = 5 V, f = 1 MHz, Bias: Clock, I/O = VCC, address =VSS)
Parameter
Symbol
CI1
Typ
—
Max
Unit
pF
Note
Input capacitance (Address)
Input capacitance (Clocks)
Output capacitance (I/O, SI/O, QSF)
5
5
7
1
1
1
CI2
—
pF
CI/O
—
pF
Note: 1. This parameter is sampled and not 100% tested.
AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V)*1, *16
Test Conditions
•
•
•
•
•
Input rise and fall time: 5 ns
Input pulse levels: VSS to 3.0 V
Input timing reference levels: 0.8 V, 2.4 V
Output timing reference levels: 0.8 V, 2.0 V
Output load: See figures
Data Sheet E0165H10
17
HM534253B Series
Test Conditions (cont)
+ 5 V
+ 5 V
IOH= – 2 mA
IOL = 4.2 mA
IOH= – 2 mA
IOL = 4.2 mA
I / O
SI / O
* 1
100 pF
* 1
50 pF
Output Load (A)
Output Load (B)
Note: 1. Including scope & jig
Common Parameter
HM534253B
-6
-7
-8
-10
Parameter
Symbol Min Max
Min Max
Min Max
Min Max
Unit Notes
Random read or write cycle tRC
time
125
—
135
—
150
—
180
—
ns
RAS precharge time
RAS pulse width
tRP
55
—
55
—
60
—
70
—
ns
tRAS
tCAS
tASR
tRAH
60 10000 70 10000 80 10000 100 10000 ns
CAS pulse width
20
0
—
—
—
—
—
20
0
—
—
—
—
—
20
0
—
—
—
—
—
25
0
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
Row address setup time
Row address hold time
10
0
10
0
10
0
10
0
Column address setup time tASC
Column address hold time
tCAH
tRCD
tRSH
15
15
15
15
RAS to CAS delay time
20 40
20 50
20 60
20 75
2
3
RAS hold time referred to
CAS
20
—
20
—
20
—
25
—
CAS hold time referred to
tCSH
60
—
70
—
80
—
100
—
ns
RAS
CAS to RAS precharge time tCRP
10
3
—
50
8
10
3
—
50
8
10
3
—
50
8
10
3
—
50
8
ns
ns
ms
ns
ns
ns
ns
Transition time (rise to fall)
Refresh period
tT
tREF
tDTS
tDTH
tFSR
tRFH
—
0
—
0
—
0
—
0
DT to RAS setup time
DT to RAS hold time
DSF to RAS setup time
DSF to RAS hold time
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
10
0
10
0
10
0
10
0
10
10
10
10
Data Sheet E0165H10
18
HM534253B Series
Common Parameter (cont)
HM534253B
-6
-7
-8
-10
Parameter
Symbol Min Max
Min Max
Min Max
Min Max
Unit Notes
DSF to CAS setup time
DSF to CAS hold time
Data-in to CAS delay time
Data-in to OE delay time
tFSC
tCFH
tDZC
tDZO
0
—
—
—
—
20
0
—
—
—
—
20
0
—
—
—
—
20
0
—
—
—
—
20
ns
ns
15
0
15
0
15
0
15
0
ns
ns
ns
4
4
5
0
0
0
0
Output buffer turn-off delay tOFF1
—
—
—
—
referred to CAS
Output buffer turn-off delay tOFF2
—
20
—
20
—
20
—
20
ns
5
referred to OE
Read Cycle (RAM), Page Mode Read Cycle
HM534253B
-6
-7
-8
-10
Parameter
Symbol Min Max
Min Max
Min Max
Min Max
Unit Notes
Access time from RAS
Access time from CAS
Access time from OE
Address access time
tRAC
tCAC
tOAC
tAA
—
—
—
—
0
60
20
20
35
—
—
—
—
—
—
—
0
70
20
20
35
—
—
—
—
—
—
—
0
80
20
20
40
—
—
—
—
—
—
—
0
100
25
25
45
—
ns
ns
ns
ns
ns
ns
ns
6, 7
7, 8
7
7, 9
Read command setup time tRCS
Read command hold time
tRCH
tRRH
0
0
0
0
—
10
10
Read command hold time
10
10
10
10
—
referred to RAS
RAS to column address
tRAD
15 25
15 35
15 40
15 55
ns
ns
ns
2
delay time
Column address to RAS lead tRAL
time
35
35
—
—
35
35
—
—
40
40
—
—
45
45
—
—
Column address to CAS lead tCAL
time
Page mode cycle time
tPC
45
10
—
—
—
40
45
10
—
—
—
40
50
10
—
—
—
45
55
10
—
—
—
50
ns
ns
ns
CAS precharge time
tCP
Access time from CAS
precharge
tACP
Page mode RAS pulse width tRASP
60 100000 70 100000 80 100000 100 100000 ns
Data Sheet E0165H10
19
HM534253B Series
Write Cycle (RAM), Page Mode Write Cycle, Color Register Set Cycle
HM534253B
-6
-7
-8
-10
Parameter
Symbol Min Max
Min Max
Min Max
Min Max
Unit Notes
Write command setup time
Write command hold time
tWCS
tWCH
0
—
—
—
—
0
—
—
—
—
0
—
—
—
—
0
—
—
—
—
ns
ns
ns
ns
11
15
15
20
15
15
20
15
15
20
15
15
20
Write command pulse width tWP
Write command to RAS lead tRWL
time
Write command to CAS lead tCWL
time
20
—
20
—
20
—
20
—
ns
Data-in setup time
Data-in hold time
tDS
tDH
tWS
tWH
0
—
—
—
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
12
15
0
15
0
15
0
15
0
WE to RAS setup time
WE to RAS hold time
10
0
10
0
10
0
10
0
Mask data to RAS setup time tMS
Mask data to RAS hold time tMH
OE hold time referred to WE tOEH
10
20
45
10
20
10
20
45
10
20
10
20
50
10
20
10
20
55
10
20
Page mode cycle time
CAS precharge time
tPC
tCP
CAS to data-in delay time
tCDD
13
Page mode RAS pulse width tRASP
60 100000 70 100000 80 10000 100 100000 ns
Data Sheet E0165H10
20
HM534253B Series
Read-Modify-Write Cycle
HM534253B
-6
-7
-8
-10
Parameter
Symbol Min Max
Min Max
Min Max
Min Max
230
Unit Notes
Read-modify-write cycle time tRWC
175
—
185
—
200
—
—
ns
RAS pulse width (read-
modify-write cycle)
tRWS
110 10000 120 10000 130 10000 150 10000 ns
CAS to WE delay time
tCWD
45
60
—
—
45
60
—
—
45
65
—
—
50
70
—
—
ns
ns
14
14
Column address to WE delay tAWD
time
OE to data-in delay time
Access time from RAS
Access time from CAS
Access time from OE
Address access time
tODD
tRAC
tCAC
tOAC
tAA
20
—
—
—
—
—
60
20
20
35
20
—
—
—
—
—
70
20
20
35
20
—
—
—
—
—
80
20
20
40
20
—
—
—
—
—
ns
ns
ns
ns
ns
ns
12
100
25
25
45
6, 7
7, 8
7
7, 9
RAS to column address
delay time
tRAD
15 25
15 35
15 40
15 55
Read command setup time tRCS
0
—
—
0
—
—
0
—
—
0
—
—
ns
ns
Write command to RAS lead tRWL
time
20
20
20
20
Write command to CAS lead tCWL
time
20
—
20
—
20
—
20
—
ns
Write command pulse width tWP
15
0
—
—
—
—
15
0
—
—
—
—
15
0
—
—
—
—
15
0
—
—
—
—
ns
ns
ns
ns
Data-in setup time
Data-in hold time
tDS
tDH
12
12
15
20
15
20
15
20
15
20
OE hold time referred to WE tOEH
Refresh Cycle
HM534253B
-6
-7
-8
-10
Parameter
Symbol Min Max
Min Max
Min Max
Min Max
Unit Notes
CAS setup time (CAS-
before-RAS refresh)
tCSR
10
10
10
—
—
—
10
10
10
—
—
—
10
10
10
—
—
—
10
10
10
—
—
—
ns
CAS hold time (CAS-before- tCHR
RAS refresh)
ns
ns
RAS precharge to CAS hold tRPC
time
Data Sheet E0165H10
21
HM534253B Series
Flash Write Cycle, Block Write Cycle
HM534253B
-6
-7
-8
-10
Parameter
Symbol Min Max
Min Max
Min Max
Min Max
Unit Notes
CAS to data-in delay time
OE to data-in delay time
tCDD
tODD
20
20
—
—
20
20
—
—
20
20
—
—
20
20
—
—
ns
ns
13
13
Read Transfer Cycle
HM534253B
-6
-7
-8
-10
Parameter
Symbol Min Max
Min Max
Min Max
Min Max
Unit Notes
DT hold time referred to RAS tRDH
DT hold time referred to CAS tCDH
50 10000 60 10000 65 10000 80 10000 ns
20
25
—
—
20
25
—
—
20
30
—
—
25
30
—
—
ns
ns
DT hold time referred to
tADH
column address
DT precharge time
tDTP
tDRD
tSRS
tSRH
tSCH
tSAH
20
65
25
60
25
40
—
—
—
—
—
—
20
65
25
70
25
40
—
—
—
—
—
—
20
70
30
80
25
45
—
—
—
—
—
—
30
80
30
100
25
50
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
DT to RAS delay time
SC to RAS setup time
1st SC to RAS hold time
1st SC to CAS hold time
1st SC to column address
hold time
Last SC to DT delay time
Last SC to DT delay time
1st SC to DT hold time
RAS to QSF delay time
CAS to QSF delay time
DT to QSF delay time
tSDD
tSDD2
tSDH
tRQD
tCQD
tDQD
tRQH
5
—
—
—
65
35
35
—
5
—
—
—
70
35
35
—
5
—
—
—
75
40
35
—
5
—
—
—
85
40
35
—
ns
ns
ns
ns
ns
ns
ns
25
10
—
—
—
20
25
10
—
—
—
20
25
15
—
—
—
20
25
15
—
—
—
25
19
15
15
15
QSF hold time referred to
RAS
QSF hold time referred to
tCQH
5
—
5
—
5
—
5
—
ns
CAS
QSF hold time referred to DT tDQH
5
0
—
—
5
0
—
—
5
0
—
—
5
0
—
—
ns
ns
Serial data-in to 1st SC delay tSZS
time
Serial clock cycle time
tSCC
25
—
25
—
30
—
30
—
ns
Data Sheet E0165H10
22
HM534253B Series
Read Transfer Cycle (cont)
HM534253B
-6
-7
-8
-10
Parameter
Symbol Min Max
Min Max
Min Max
Min Max
Unit Notes
SC pulse width
tSC
5
—
—
20
—
—
—
5
—
—
22
—
—
—
10
10
—
5
—
—
25
—
—
—
10
10
—
5
—
—
25
—
—
—
ns
ns
SC precharge time
SC access time
tSCP
tSCA
tSOH
tSIS
10
—
5
10
—
5
ns
ns
ns
ns
ns
15
Serial data-out hold time
Serial data-in setup time
Serial data-in hold time
0
0
0
0
tSIH
tRAD
15
15
15
15
RAS to column address
delay time
15 25
15 35
15 40
15 55
Column address to RAS lead tRAL
35
10
—
—
35
10
—
—
40
10
—
—
45
10
—
—
ns
ns
time
RAS precharge to DT high
tDTHH
18
hold time
Data Sheet E0165H10
23
HM534253B Series
Pseudo Transfer Cycle, Write Transfer Cycle
HM534253B
-6
-7
-8
-10
Parameter
Symbol Min Max
Min Max
Min Max
Min Max
Unit Notes
SE setup time referred to
RAS
tES
0
—
0
—
0
—
0
—
ns
SE hold time referred to RAS tEH
10
25
—
—
10
25
—
—
10
30
—
—
10
30
—
—
ns
ns
SC setup time referred to
tSRS
RAS
RAS to SC delay time
tSRD
tSRZ
20
—
20
—
25
—
25
—
ns
ns
Serial output buffer turn-off
10 40
10 40
10 45
10 50
time referred to RAS
RAS to serial data-in delay
time
tSID
40
—
40
—
45
—
50
—
ns
RAS to QSF delay time
CAS to QSF delay time
tRQD
tCQD
tRQH
—
—
20
65
35
—
—
—
20
70
35
—
—
—
20
75
40
—
—
—
25
85
40
—
ns
ns
ns
15
15
QSF hold time referred to
RAS
QSF hold time referred to
tCQH
5
—
5
—
5
—
5
—
ns
CAS
Serial clock cycle time
SC pulse width
tSCC
tSC
25
5
—
—
—
20
20
—
—
25
5
—
—
—
22
22
—
—
30
10
10
—
—
5
—
—
—
25
25
—
—
30
10
10
—
—
5
—
—
—
25
25
—
—
ns
ns
ns
ns
ns
ns
ns
SC precharge time
SC access time
tSCP
tSCA
tSEA
tSOH
tSWS
10
—
—
5
10
—
—
5
15
15
SE access time
Serial data-out hold time
Serial write enable setup
time
5
5
5
5
Serial data-in setup time
Serial data-in hold time
tSIS
tSIH
0
—
—
0
—
—
0
—
—
0
—
—
ns
ns
15
15
15
15
Data Sheet E0165H10
24
HM534253B Series
Split Read Transfer Cycle, Split Write Transfer Cycle
HM534253B
-6
-7
-8
-10
Parameter
Symbol Min Max
Min Max
Min Max
Min Max
Unit Notes
Split transfer setup time
tSTS
tRST
20
60
—
—
20
70
—
—
20
80
—
—
25
—
—
ns
ns
Split transfer hold time
100
referred to RAS
Split transfer hold time
referred to CAS
tCST
tAST
tSQD
20
35
—
—
20
35
—
—
20
40
—
—
25
45
—
—
ns
ns
Split transfer hold time
referred to column address
SC to QSF delay time
—
5
30
—
—
—
—
20
—
—
—
—
5
30
—
—
—
—
22
—
—
—
—
5
30
—
—
—
—
25
—
—
—
—
5
30
—
—
—
—
25
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
15
QSF hold time referred to SC tSQH
Serial clock cycle time
SC pulse width
tSCC
tSC
25
5
25
5
30
10
10
—
5
30
10
10
—
5
SC precharge time
SC access time
tSCP
tSCA
tSOH
tSIS
10
—
5
10
—
5
Serial data-out hold time
Serial data-in setup time
Serial data-in hold time
0
0
0
0
tSIH
15
15
15
15
RAS to column address
delay time
tRAD
15 25
15 35
15 40
15 55
Column address to RAS lead tRAL
time
35
—
35
—
40
—
45
—
ns
Data Sheet E0165H10
25
HM534253B Series
Serial Read Cycle, Serial Write Cycle
HM534253B
-6
-7
-8
-10
Parameter
Symbol Min Max
Min Max
Min Max
Min Max
Unit Notes
Serial clock cycle time
SC pulse width
tSCC
tSC
25
5
—
—
—
20
20
—
20
25
5
—
—
—
22
22
—
20
30
10
10
—
—
5
—
—
—
25
25
—
20
30
10
10
—
—
5
—
—
—
25
25
—
20
ns
ns
ns
SC precharge width
Access time from SC
Access time from SE
Serial data-out hold time
tSCP
tSCA
tSEA
tSOH
tSEZ
10
—
—
5
10
—
—
5
ns
ns
ns
ns
15
15
Serial output buffer turn-off
—
—
—
—
5
time referred to SE
Serial data-in setup time
Serial data-in hold time
tSIS
0
—
—
—
0
—
—
—
0
—
—
—
0
—
—
—
ns
ns
ns
tSIH
tSWS
15
5
15
5
15
5
15
5
Serial write enable setup
time
Serial write enable hold time tSWH
15
5
—
—
15
5
—
—
15
5
—
—
15
5
—
—
ns
ns
Serial write disable setup
time
tSWIS
Serial write disable hold time tSWIH
15
—
15
—
15
—
15
—
ns
Notes: 1. AC measurements assume tT = 5 ns.
2. When tRCD > tRCD (max) and tRAD > tRAD (max), access time is specified by tCAC or tAA.
3. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition time tT
is measured between VIH and VIL.
4. Data input must be floating before output buffer is turned on. In read cycle, read-modify-write cycle
and delayed write cycle, either tDZC (min) or tDZO (min) must be satisfied.
5. tOFF1 (max), tOFF2 (max), and tSEZ (max) are defined as the time at which the output achieves the open
circuit condition (VOH – 100 mV, VOL + 100 mV).
6. Assume that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
7. Measured with a load circuit equivalent to 2 TTL loads and 100 pF.
8. When tRCD ≥ tRCD (max) and tRAD ≤ tRAD (max), access time is specified by tCAC
9. When tRCD ≤ tRCD (max) and tRAD ≥ tRAD (max), access time is specified by tAA.
10. If either tRCH or tRRH is satisfied, operation is guaranteed.
.
11. When tWCS ≥ tWCS (min), the cycle is an early write cycle, and I/O pins remain in an open circuit (high
impedance) condition.
12. These parameters are specified by the later falling edge of CAS or WE.
13. Either tCDD (min) or tODD (min) must be satisfied because output buffer must be turned off by CAS or
OE prior to applying data to the device when output buffer is on.
14. When tAWD ≥ tAWD (min) and tCWD ≥ tCWD (min) in read-modify-write cycle, the data of the selected
address outputs to an I/O pin and input data is written into the selected address. tODD (min) must be
satisfied because output buffer must be turned off by OE prior to applying data to the device.
15. Measured with a load circuit equivalent to 2 TTL loads and 50 pF.
Data Sheet E0165H10
26
HM534253B Series
16. After power-up, pause for 100 µs or more and execute at least 8 initialization cycle (normal memory
cycle or refresh cycle), then start operation.
17. When the serial write cycle is used, at least one SC pulse is required before proper SAM operation
after VCC stabilized.
18. tDTHH (min) must be satisfied only if DT/OE rises up before RAS rises in a read transfer cycle.
19. After read transfer cycle, if split read transfer cycle is executed without SC access and SC address
is 254 or 510, tSDD2 (min) must be satisfied 25 ns. Except for those cases, tSDD (min) is effective and
satisfied 5 ns.
20. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max))
///////: Invalid Dout
Timing Waveforms*20
Read Cycle
tRC
t RAS
tRP
RAS
CAS
tCRP
t CSH
tRSH
tCAS
tRCD
t RAD
t RAH
tRAL
tCAH
tCAL
t ASR
Row
tASC
Column
tRCS
Address
tRRH
tRCH
WE
tCAC
tAA
tRAC
tCDD
tOFF1
Valid Dout
tOFF2
I/O
(Output)
tOAC
tDZC
I/O
(Input)
tDZO
tDTS
tDTH
DT/OE
DSF
tRFH
tFSC
tFSR
tCFH
Data Sheet E0165H10
27
HM534253B Series
Early Write Cycle
tRC
tRAS
tRP
RAS
tCRP
tCSH
tRCD
tRSH
tCAS
CAS
tASR
tRAH
Row
tWS
tCAH
Column
tWCS
tASC
Address
WE
tWH
tWCH
*1
High-Z
I/O
(Output)
tMH
tMS
tDH
Valid Din
tDS
I/O
(Input)
Mask Data
tDTS tDTH
DT/OE
DSF
tFSR
tRFH
tFSC
tCFH
Note:
1. This cycle becomes a normal mode write cycle when WE is high and a mask write cycle when WE
is low.
Delayed Write Cycle
tRC
tRAS
tRP
RAS
tCRP
tCSH
tRSH
tRCD
tCAS
CAS
tASR
tRAH
tASC
Columun
tCAH
Address
Row
tWS
tRWL
tWP
tWH
tCWL
*1
WE
I/O
(Output)
tDH
tDS
tMS
tMH
tDZC
I/O
(Input)
Valid Din
tOEH
Mask Data
tDTH
tOFF2
tODD
tDTS
DT/OE
DSF
tRFH
tFSR
tCFH
tFSC
Note:
1. This cycle becomes a normal mode write cycle when WE is high and a mask write cycle when WE
is low.
Data Sheet E0165H10
28
HM534253B Series
Read-Modify-Write Cycle
tRWC
tRWS
tRP
RAS
tCRP
tRCD
CAS
tRAD
tRAH
Row
tASR
tCAH
tASC
Address
WE
Column
tAWD
tCWD
tRWL
tCWL
tWP
tWS
tWH
tRCS
tCAC
tAA
tRAC
*1
I/O
Valid Dout
(Output)
tDS
tOAC
tDH
tMS
Mask Data
tDTS
tMH
tDZC
tDZO
I/O
(Input)
Valid Din
tOEH
tOFF2
tODD
tDTH
DT/OE
DSF
tRFH
tFSC
tFSR
tCFH
Note:
1. This cycle becomes a normal mode write cycle when WE is high and a mask write cycle when WE
is low.
Page Mode Read Cycle
tRC
tRASP
tRP
RAS
CAS
tCSH
tRCD
tPC
tRSH
tCAS
tCP
tRAL
tASC
tCRP
tCP
tCAS
tCAS
tRAD
tCAL
tCAH
tCAL
tCAL
tCAH
tASR
tASC
tASC
tCAH
tRAH
Row
Address
WE
Column
Column
Column
tRRH
tRCS
tRCS
tRCS
tRCH
tRCH
t
RCH
tRAC
tAA
tCAC
tOFF1
tAA
tACP
tCAC
tAA
tACP
tCAC
tOFF1
tOFF1
Valid
Dout
Valid
Dout
I/O
(Output)
Valid Dout
tCDD
tOFF2
tCDD
tDZC
tDZC
tDZC
tCDD
tOAC
tOAC
tOAC tOFF2
I/O
(Input)
tDZO
tDTH
tDTS
DT/OE
DSF
tFSR
tRFH
tFSC
tFSC
tCFH
tCFH
tCFH
tFSC
Data Sheet E0165H10
29
HM534253B Series
Page Mode Write Cycle (Early Write)
tRC
tRP
tRASP
RAS
tCSH
tRCD
tPC
tRSH
tCAS
tCP
tCRP
tCP
tCAS
tCAH
tCAS
CAS
tASR
tRAH
tASC
Column
tWCS
tASC
tASC
tCAH
tCAH
Address
Row
tWH
Column
tWCS
Column
tWCS
tWS
tWCH
tWCH
tWCH
WE
*1
High-Z
I/O
(Output)
tMS tMH tDS
tDH
tDH
tDH
tDS
tDS
I/O
(Input)
Mask
Data
Valid Din
Valid Din
Valid Din
tDTS
tDTH
DT/OE
DSF
tFSR
tRFH
tCFH
tFSC
tCFH
tFSC
tCFH
tFSC
Note:
1. This cycle becomes a normal mode write cycle when WE is high and a mask write cycle when WE
is low.
Page Mode Write Cycle (Delayed Write)
tRC
tRASP
tRP
RAS
tCSH
tPC
tRSH
tCAS
tCP
tCRP
tRCD
tASC
tCP
tCAS
tCAH
tCAS
tCAH
CAS
tASR
tRAH
Row
tWS tWH
*1
tASC
tASC
tCAH
Address
Column
Column
Column
tRWL
tCWL
tWP
tCWL
tWP
tCWL
tWP
WE
I/O
(Output)
tMH
tMS
tDH
tDS tDH
tDS tDH
tDS
Mask
Data
I/O
(Input)
Valid
Din
Valid
Din
Valid
Din
tOEH
tDTS
DT/OE
DSF
tRFH
tFSC tCFH
tFSC tCFH
tFSC
tCFH
tFSR
Note:
1. This cycle becomes a normal mode write cycle when WE is high and a mask write cycle when WE
is low.
Data Sheet E0165H10
30
HM534253B Series
RAS-Only Refresh Cycle
tRC
tRP
tRAS
RAS
CAS
tRPC
tCRP
tASR
Row
tRAH
Address
tOFF1
I/O
(Output)
tCDD
tOFF2
I/O
(Input)
tODD
tDTS
tDTH
DT/OE
DSF
tFSR tRFH
CAS-Before-RAS Refresh Cycle
tRC
tRP
tRP
tRAS
tRPC
tCP
tRPC
RAS
tCSR
tCSR
tCHR
Inhibit Falling Transition
CAS
Address
WE
tOFF1
High-Z
I/O
(Output)
DT/OE
DSF
Data Sheet E0165H10
31
HM534253B Series
Hidden Refresh Cycle
tRC
tRC
tRAS
tRAS
tRP
tRP
RAS
tCRP
tRCD
tRSH
tCHR
CAS
tRAD
tRAH
tRAL
tASC
Column
tASR
Row
tCAH
Address
WE
tRCS
tRRH
tCAC
tAA
tRAC
tOFF1
I/O
(Output)
Valid Dout
tDZC
tOAC
tOFF2
I/O
(Input)
tDZO
tDTH
tDTS
tFSR
DT/OE
DSF
tRFH
tFSC
tCFH
Color Register Set Cycle (Early Write)
tRC
tRP
tRAS
RAS
tCSH
tCRP
tRCD
tRAH
tRSH
tCAS
CAS
tASR
Row
Address
WE
tWS
tWH
tWCS
tWCH
High-Z
I/O
(Output)
tDS
Color Data
tDH
I/O
(Input)
tDTS
tDTH
DT/OE
DSF
tFSR
tRFH
Data Sheet E0165H10
32
HM534253B Series
Color Register Set Cycle (Delayed Write)
tRC
tRP
tRAS
RAS
tCSH
tCRP
tRSH
tRCD
tCAS
CAS
tASR
tRAH
Address
Row
tRWL
tCWL
tWS
tWP
WE
I/O
(Output)
High-Z
tDS
tDH
I/O
(Input)
Color Data
tDTS
tOEH
DT/OE
DSF
tFSR
tRFH
Color Register Read Cycle
tRC
tRP
tRAS
RAS
CAS
tCSH
tCRP
tRSH
tCAS
tRCD
tASR
tRAH
Address
WE
Row
tWH
tRCS
tWS
tRRH
tRCH
tCDD
tCAC
tOFF1
tRAC
I/O
(Output)
Valid Out
tOFF2
tOAC
tDZC
tODD
I/O
(Input)
tDZO
tDTH
tDTS
DT/OE
DSF
tFSR tRFH
Data Sheet E0165H10
33
HM534253B Series
Flash Write Cycle
tRC
tRAS
tRP
RAS
tCRP
tRCD
tRAH
CAS
tASR
Row
tWS
Address
tWH
WE
tCDD
tOFF1
High-Z
I/O
(Output)
tOFF2
tMS
tMH
tODD
I/O
(Input)
Mask Data
tDTH
tDTS
DT/OE
DSF
tFSR
tRFH
Block Write Cycle
t RC
t RP
t RASP
RAS
t CSH
t PC
tRSH
t CAS
t CP
t CRP
tRCD
tCP
t CAS
t CAS
CAS
tASR
tRAH
tASC
tCAH
tCAH
tASC
tASC
tCAH
Column
A2-A8
Column
A2-A8
Column
A2-A8
Row
Address
tWS
tWH
*1
WE
High-Z
I/O
(Output)
tDS
tDS
tDS
tMS
tMH
tDH
tDH
tDH
Address
Mask
Address
Mask
I/O
Mask
Address
Mask
I/O
(Input)
tDTH
tDTS
DT/OE
DSF
tFSC
tFSC
tFSC
tCFH
tFSR
tRFH
tCFH
tCFH
Note:
1. This cycle becomes a normal block write cycle when WE is high and a mask block write cycle
when WE is low.
Data Sheet E0165H10
34
HM534253B Series
Page Mode Block Write Cycle
t RC
t RP
t RASP
RAS
t CSH
t PC
tRSH
t CAS
t CP
t CRP
tRCD
tCP
t CAS
t CAS
CAS
tASR
tRAH
tASC
tCAH
tCAH
tASC
tASC
tCAH
Column
A2-A8
Column
A2-A8
Column
A2-A8
Row
Address
WE
tWS
tWH
*1
High-Z
I/O
(Output)
tDS
tDS
tDS
tMS
tMH
tDH
tDH
tDH
Address
Mask
Address
Mask
I/O
Mask
Address
Mask
I/O
(Input)
tDTH
tDTS
DT/OE
DSF
tFSC
tFSC
tFSC
tCFH
tFSR
tRFH
tCFH
tCFH
Note:
1. This cycle becomes a normal block write cycle when WE is high and a mask block write cycle
when WE is low.
Data Sheet E0165H10
35
HM534253B Series
Read Transfer Cycle (1)
tRC
tRP
tRAS
RAS
tCRP
tCSH
tRCD
tRSH
tCAS
CAS
tRAD
tRAH
tRAL
tASR
tCAH
tASC
SAM Start
Address
Address
WE
Row
tWS tWH
tDTHH
High-Z
tDTP
I/O
(Output)
tCDH
tADH
tRDH
tDRD
tDTS
DT/OE
DSF
tRFH
tFSR
tSCC
tSCC
tSCC
tSCC
tSDH
tSDD
tSDD2*
tSC
3
tSCP
SC
tSCA
tSCA
tSOH
tSCA
tSOH
Valid Sout
tSCA
tSOH
tSOH
tSOH
Valid Sout
Valid Sout
Valid Sout
Valid Sout
SI/O
(Output)
Previous Row
tDQD
New Row
SI/O
(Input)
tDQH
QSF *1
SAM Address MSB
tRQD
tCQD
tCQH
tRQH
QSF *2
SAM Address MSB
Notes: 1. This QSF timing is referred when SC is risen once or more between the previous transfer cycle and
CAS falling edge of this cycle (QSF is switched by DT rising).
2. This QSF timing is referred when SC isn't risen between the previous transfer cycle and CAS falling
edge of this cycle (QSF is switched by RAS or CAS falling).
3. After read transfer cycle, if split read transfer cycle is executed without SC access and SC address
is 254 or 510, tSDD2 (min) must be satisfied 25 ns. Except for those cases, tSDD (min) is effective and
satisfied 5 ns.
Data Sheet E0165H10
36
HM534253B Series
Read Transfer Cycle (2)
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRCD
tRSH
tCAS
CAS
tRAD
tRAH
tRAL
tASR
Row
tASC
tCAH
Sam Start
Address
Address
WE
tWH
tWS
tDTHH
High-Z
I/O
(Output)
tDRD
tDTP
tDTS
tDTH
DT/OE
DSF
tFSR
tRFH
tSRS
tSC
tSDH
tSCP
tSCC
tSCP
tSC
Inhibit Rising Transition
tSCH
SC
tSCA
tSCA
tSAH
tSRH
tSOH
Valid Sout
SI/O
(Output)
tSIS
tSIH
tSZS
Valid
Sin
SI/O
(Input)
tDQD
tDQH
SAM Address MSB
QSF
tCQD
tCQH
tRQD
tRQH
Data Sheet E0165H10
37
HM534253B Series
Pseudo Transfer Cycle
t
RC
t
RAS
t
RP
RAS
CAS
t
t
CSH
RSH
CAS
CRP
t
t
RCD
t
t
t
t
t
t
CAH
ASC
RAH
ASR
WS
SAM Start
Address
Address
WE
Row
t
WH
High - Z
I/O
(Output)
t
DTS
FSR
t
DTH
DT/OE
DSF
t
t
RFH
t
t
SEZ
EH
t
SWS
t
ES
SE
SC
t
SRS
t
SCC
t
SRD
SCP
t
t
t
SCP
SC
t
SC
Inhibit Rising Transition
t
SCA
t
SRZ
t
SOH
SI/O
(Output)
Valid
Sout
Valid Sout
t
t
t
SIH
t
t
SIH
SIS
SIS
SID
SI/O
(Input)
Valid Sin
Valid Sin
t
CQD
t
CQH
t
RQD
t
RQH
QSF
SAM Address MSB
Data Sheet E0165H10
38
HM534253B Series
Write Transfer Cycle
t
RC
t
RAS
t
RP
RAS
t
t
CRP
CSH
RSH
t
t
RCD
t
CAS
CAS
t
t
t
t
CAH
ASC
RAH
ASR
SAM Start
Address
Address
WE
Row
t
t
WH
WS
High-Z
I/O
(Output)
t
DTS
FSR
t
DTH
DT/OE
DSF
t
t
RFH
EH
t
t
ES
t
SWS
SE
SC
t
SRS
t
SRD
t
SCC
t
t
SC
SWS
t
t
SCP
t
SC
SCP
Inhibit Rising Transition
SI/O
(Output)
t
t
SIH
SIS
t
t
SIH
t
t
SIS
SIS
SIH
SI/O
(Input)
Valid Sin
Valid Sin
Valid Sin
t
CQD
t
CQH
t
RQD
t
RQH
QSF
SAM Address MSB
Data Sheet E0165H10
39
HM534253B Series
Split Read Transfer Cycle
t
RC
t
t
RP
RAS
RAS
t
CSH
t
t
RSH
t
RCD
CRP
t
CRP
t
CAS
CAS
t
RAD
t
RAL
t
t
ASR
RAH
t
t
CAH
ASC
SAM Start
Address Yi
Address
Row
t
t
WS
WH
WE
t
OFF1
High-Z
I/O
(Output)
t
t
DTH
DTS
DT/OE
DSF
t
RFH
t
FSR
t
CST
t
AST
t
RST
Low
SE
SC
t
SCC
t
t
t
SC
SCP
STS
n
253
(509)
n+1
(n+256)
n+2
(n+257)
254
(510)
255
(511)
511
Yi+255
(Yi)
(n+255)
(255)
t
SCA
t
SCA
t
t
SOH
SOH
SI/O
(Output)
Valid
Sout
Valid
Sout
Valid
Sout
Valid
Sout
Valid
Sout
Valid Sout
SI/O
(Input)
t
t
SQD
SQD
t
SQH
t
SQH
QSF
SAM Address MSB
Data Sheet E0165H10
40
HM534253B Series
Split Write Transfer Cycle
t
RC
t
RP
t
RAS
RAS
t
CSH
t
t
RSH
RCD
t
CAS
CAS
t
RAL
t
t
ASR
RAH
t
t
CAH
ASC
SAM Start
Address Yi
Address
Row
t
t
WH
WS
WE
t
OFF1
High-Z
I/O
(Output)
t
t
DTH
DTS
DT/OE
DSF
t
RFH
t
FSR
t
CST
t
AST
t
RST
Low
SE
SC
t
SCC
t
t
t
t
SC
SCP
STS
n
n+1
(n+256)
n+2
n+3
(n+258)
254
(510)
255
511
(255)
Yi+255
(Yi)
(n+255)
(n+257)
(511)
SI/O
(Output)
t
t
t
t
SIS
t
SIS
SIH
SIS
SIH
SIH
SI/O
(Input)
Valid
Sin
Valid
Sin
Valid
Sin
Valid
Sin
Valid
Sin
Valid Sin
Valid Sin
t
t
SQD
SQD
t
SQH
t
SQH
QSF
SAM Address MSB
Data Sheet E0165H10
41
HM534253B Series
Serial Read Cycle
SE
tSCC
tSCC
tSCC
tSCP
tSC
tSC
tSCP
tSC
tSC
tSCP
SC
tSCA
tSCA
tSEA
tSCA
tSEZ
tSOH
tSOH
Valid
Sout
SI/O
(Output)
Valid Sout
Valid Sout
Valid Sout
Serial Write Cycle
tSWH
tSWIS tSWIH
tSWS
SE
SC
tSCC
tSCC
tSC
tSCC
tSC
tSCP
tSC
tSC
tSIS
Valid Sin
tSCP
tSCP
tSIS
tSIS tSIH
tSIH
tSIH
SI/O
(Input)
Valid Sin
Valid Sin
Data Sheet E0165H10
42
HM534253B Series
Package Dimensions
HM534253BJ Series (CP-28D)
Unit: mm
18.17
18.54 Max
15
14
28
1
0.74
1.30 Max
9.40 ± 0.25
1.27
0.43 ± 0.10
0.41 ± 0.08
0.10
Hitachi Code
JEDEC
EIAJ
CP-28D
Conforms
Conforms
Dimension including the plating thickness
Base material dimension
Weight (reference value) 1.16 g
Data Sheet E0165H10
43
HM534253B Series
HM534253BZ Series (ZP-28)
Unit: mm
35.58
36.57 Max
+ 0.10
– 0.05
0.25
2.54
1
28
1.045 Max
+ 0.08
– 0.12
1.27
0.50
0.25 M
Hitachi Code
JEDEC
ZP-28
—
EIAJ
Conforms
Weight (reference value) 1.95 g
Data Sheet E0165H10
44
HM534253B Series
Cautions
1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.’s or any
third party’s patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party’s
rights, including intellectual property rights, in connection with use of the information contained in this
document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, contact Elpida Memory, Inc. before using the product in an application that demands especially
high quality and reliability or where its failure or malfunction may directly threaten human life or cause
risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc.
particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage
when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally
foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as
fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury,
fire or other consequential damage due to operation of the Elpida Memory, Inc. product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Elpida Memory, Inc..
7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc.
semiconductor products.
Data Sheet E0165H10
45
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